From e6ea9147694c09bb15ad730aabdc3acdefd86e02 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Tue, 25 Aug 2026 18:12:23 -0500 Subject: [PATCH] clk: tegra: dfll: fix use of tune values There was some confusion on the use of the tune values. They were defined in 2 different structs, but only initialzed in one of them. Remove most of the references in struct tegra_dfll_soc_data and adjust the code accordingly. Only tune_high_min_millivolts is left, because this can be adjusted using debugfs. Hence copy the initial value from the cvb table at boot. --- drivers/clk/tegra/clk-dfll.c | 10 +++++----- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 3 +++ 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 0d93d2f383e5..3493c3f7ec66 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -1948,7 +1948,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) int i; unsigned long rate, reg_volt; u8 lut_bottom = MAX_DFLL_VOLTAGES; - int v_min = td->soc->cvb->min_millivolts * 1000; + int v_min = td->soc->min_millivolts * 1000; for (i = 0; i < MAX_DFLL_VOLTAGES; i++) { reg_volt = td->lut_uv[i]; @@ -1968,7 +1968,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) if ((lut_bottom == MAX_DFLL_VOLTAGES) || (lut_bottom + 1 >= td->lut_size)) { dev_err(td->dev, "no voltage above DFLL minimum %d mV\n", - td->soc->cvb->min_millivolts); + td->soc->min_millivolts); return -EINVAL; } td->lut_bottom = lut_bottom; @@ -1977,7 +1977,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) rate = get_dvco_rate_below(td, td->lut_bottom); if (!rate) { dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n", - td->soc->cvb->min_millivolts); + td->soc->min_millivolts); return -EINVAL; } td->dvco_rate_min = rate; @@ -2004,7 +2004,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) int ret = -EINVAL; int j, selector, lut; - v = td->soc->cvb->min_millivolts * 1000; + v = td->soc->min_millivolts * 1000; lut = find_vdd_map_entry_exact(td, v); if (lut < 0) goto out; @@ -2053,7 +2053,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) if (!td->dvco_rate_min) dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", - td->soc->cvb->min_millivolts); + td->soc->min_millivolts); else { ret = 0; for (j = 0; j < td->lut_size; j++) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 28699cd75619..8b9f0c6cb20f 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -864,6 +864,9 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return PTR_ERR(soc->cvb); } + soc->tune_high_min_millivolts = + soc->cvb->cpu_dfll_data.tune_high_min_millivolts; + err = tegra_dfll_register(pdev, soc); if (err < 0) { tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);