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drm/xe: Fix DSB buffer coherency

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[ Upstream commit 71a3161e9d7d2229cb4eefd4c49effb97caf3db3 ]

Add the scanout flag to force WC caching, and add the memory barrier
where needed.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240913114754.7956-2-maarten.lankhorst@linux.intel.com
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Stable-dep-of: a4b1b51ae132 ("drm/xe: Move DSB l2 flush to a more sensible place")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Maarten Lankhorst
2024-09-13 13:47:53 +02:00
committed by Greg Kroah-Hartman
parent 61628111e7
commit e5f01b2b67
1 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/xe/display/xe_dsb_buffer.c
+7 -2
View File
@@ -48,11 +48,12 @@ bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *d
if (!vma) if (!vma)
return false; return false;
/* Set scanout flag for WC mapping */
obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
NULL, PAGE_ALIGN(size), NULL, PAGE_ALIGN(size),
ttm_bo_type_kernel, ttm_bo_type_kernel,
XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
XE_BO_FLAG_GGTT); XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT);
if (IS_ERR(obj)) { if (IS_ERR(obj)) {
kfree(vma); kfree(vma);
return false; return false;
@@ -73,5 +74,9 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf) void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
{ {
/* TODO: add xe specific flush_map() for dsb buffer object. */ /*
* The memory barrier here is to ensure coherency of DSB vs MMIO,
* both for weak ordering archs and discrete cards.
*/
xe_device_wmb(dsb_buf->vma->bo->tile->xe);
} }