From ddc4aa6226d12b6d6c33c11d3a4a8c4e352abb90 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Thu, 16 May 2019 11:23:01 +0530 Subject: [PATCH] PCI: tegra: Access endpoint config only if PCIe link is up Few endpoints like Wi-Fi supports power on/off and to leverage that root port must support hot-plug and hot-unplug. Tegra PCIe doesn't support hot-plug and hot-unplug, however it supports endpoint power on/off feature as follows, - Power off sequence: - Transition of PCIe link to L2 - Power off endpoint - Leave root port in power up state with the link in L2 - Power on sequence: - Power on endpoint - Apply hot reset to get PCIe link up PCIe client driver stops accessing PCIe endpoint config and BAR registers after endpoint is powered off. However, software applications like x11 server or lspci can access endpoint config registers in which case host controller raises "response decoding" errors. To avoid this scenario, add PCIe link up check in config read and write callback functions before accessing endpoint config registers. Change-Id: I47653cb0b580c2b764cb0ad9c42deeb9c8823c58 Signed-off-by: Manikanta Maddireddy Reviewed-on: https://git-master.nvidia.com/r/c/linux-4.14/+/2371131 (cherry picked from commit be664bfdd901138222a8ea8bb17160a2fa9de04a) Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407866 Reviewed-by: automaticguardword Reviewed-by: Bitan Biswas Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/pci/controller/pci-tegra.c | 40 +++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 562369e6221d..ffdde6711484 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -6,7 +6,7 @@ * Author: Mike Rapoport * * Based on NVIDIA PCIe driver - * Copyright (c) 2008-2009, NVIDIA Corporation. + * Copyright (c) 2008-2020, NVIDIA Corporation. * * Bits taken from arch/arm/mach-dove/pcie.c * @@ -402,6 +402,14 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) return readl(pcie->pads + offset); } +static bool tegra_pcie_link_up(struct tegra_pcie_port *port) +{ + u32 value; + + value = readl(port->base + RP_LINK_CONTROL_STATUS); + return !!(value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE); +} + /* * The configuration space mapping on Tegra is somewhat similar to the ECAM * defined by PCIe. However it deviates a bit in how the 4 bits for extended @@ -467,20 +475,50 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) { + struct tegra_pcie *pcie = bus->sysdata; + struct pci_dev *bridge; + struct tegra_pcie_port *port; + if (bus->number == 0) return pci_generic_config_read32(bus, devfn, where, size, value); + bridge = pcie_find_root_port(bus->self); + + list_for_each_entry(port, &pcie->ports, list) + if (port->index + 1 == PCI_SLOT(bridge->devfn)) + break; + + /* If there is no link, then there is no device */ + if (!tegra_pcie_link_up(port)) { + *value = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + return pci_generic_config_read(bus, devfn, where, size, value); } static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) { + struct tegra_pcie *pcie = bus->sysdata; + struct tegra_pcie_port *port; + struct pci_dev *bridge; + if (bus->number == 0) return pci_generic_config_write32(bus, devfn, where, size, value); + bridge = pcie_find_root_port(bus->self); + + list_for_each_entry(port, &pcie->ports, list) + if (port->index + 1 == PCI_SLOT(bridge->devfn)) + break; + + /* If there is no link, then there is no device */ + if (!tegra_pcie_link_up(port)) + return PCIBIOS_DEVICE_NOT_FOUND; + return pci_generic_config_write(bus, devfn, where, size, value); }