Merge drm-upstream/drm-next into drm-misc-next
We got a few conflicts in drm_atomic.c after merging the DRM writeback support, now we need a backmerge to unlock develop development on drm-misc-next. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
This commit is contained in:
Gustavo Padovan
@@ -78,6 +78,12 @@ extern "C" {
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
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AMDGPU_GEM_DOMAIN_GTT | \
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AMDGPU_GEM_DOMAIN_VRAM | \
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AMDGPU_GEM_DOMAIN_GDS | \
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AMDGPU_GEM_DOMAIN_GWS | \
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AMDGPU_GEM_DOMAIN_OA)
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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@@ -95,6 +101,10 @@ extern "C" {
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#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
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/* Flag that BO sharing will be explicitly synchronized */
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#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
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/* Flag that indicates allocating MQD gart on GFX9, where the mtype
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* for the second page onward should be set to NC.
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*/
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#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@@ -520,6 +530,10 @@ union drm_amdgpu_cs {
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/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
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#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
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/* The IB fence should do the L2 writeback but not invalidate any shader
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* caches (L2/vL1/sL1/I$). */
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#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
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struct drm_amdgpu_cs_chunk_ib {
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__u32 _pad;
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/** AMDGPU_IB_FLAG_* */
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@@ -620,6 +634,12 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_ASD 0x0d
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/* Subquery id: Query VCN firmware version */
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#define AMDGPU_INFO_FW_VCN 0x0e
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/* Subquery id: Query GFX RLC SRLC firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
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/* Subquery id: Query GFX RLC SRLG firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
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/* Subquery id: Query GFX RLC SRLS firmware version */
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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/* the used VRAM size */
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@@ -135,6 +135,219 @@ struct drm_exynos_g2d_exec {
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__u64 async;
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};
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/* Exynos DRM IPP v2 API */
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/**
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* Enumerate available IPP hardware modules.
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*
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* @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
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* @reserved: padding
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* @ipp_id_ptr: pointer to ipp_id array or NULL
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*/
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struct drm_exynos_ioctl_ipp_get_res {
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__u32 count_ipps;
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__u32 reserved;
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__u64 ipp_id_ptr;
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};
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enum drm_exynos_ipp_format_type {
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DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
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DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
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};
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struct drm_exynos_ipp_format {
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__u32 fourcc;
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__u32 type;
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__u64 modifier;
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};
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enum drm_exynos_ipp_capability {
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DRM_EXYNOS_IPP_CAP_CROP = 0x01,
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DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
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DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
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DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
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};
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/**
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* Get IPP hardware capabilities and supported image formats.
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*
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* @ipp_id: id of IPP module to query
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* @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
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* @reserved: padding
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* @formats_count: size of formats array (in entries) / number of filled
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* formats (set by driver)
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* @formats_ptr: pointer to formats array or NULL
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*/
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struct drm_exynos_ioctl_ipp_get_caps {
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__u32 ipp_id;
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__u32 capabilities;
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__u32 reserved;
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__u32 formats_count;
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__u64 formats_ptr;
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};
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enum drm_exynos_ipp_limit_type {
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/* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
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DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
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/* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
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DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
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/* image buffer area */
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DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
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/* src/dst rectangle area */
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DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
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/* src/dst rectangle area when rotation enabled */
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DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
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DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
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DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
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};
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struct drm_exynos_ipp_limit_val {
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__u32 min;
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__u32 max;
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__u32 align;
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__u32 reserved;
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};
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/**
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* IPP module limitation.
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*
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* @type: limit type (see drm_exynos_ipp_limit_type enum)
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* @reserved: padding
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* @h: horizontal limits
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* @v: vertical limits
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*/
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struct drm_exynos_ipp_limit {
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__u32 type;
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__u32 reserved;
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struct drm_exynos_ipp_limit_val h;
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struct drm_exynos_ipp_limit_val v;
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};
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/**
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* Get IPP limits for given image format.
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*
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* @ipp_id: id of IPP module to query
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* @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
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* @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
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* @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
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* @limits_count: size of limits array (in entries) / number of filled entries
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* (set by driver)
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* @limits_ptr: pointer to limits array or NULL
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*/
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struct drm_exynos_ioctl_ipp_get_limits {
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__u32 ipp_id;
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__u32 fourcc;
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__u64 modifier;
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__u32 type;
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__u32 limits_count;
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__u64 limits_ptr;
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};
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enum drm_exynos_ipp_task_id {
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/* buffer described by struct drm_exynos_ipp_task_buffer */
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DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
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/* rectangle described by struct drm_exynos_ipp_task_rect */
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DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
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/* transformation described by struct drm_exynos_ipp_task_transform */
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DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
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/* alpha configuration described by struct drm_exynos_ipp_task_alpha */
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DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
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/* source image data (for buffer and rectangle chunks) */
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DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
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/* destination image data (for buffer and rectangle chunks) */
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DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
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};
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/**
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* Memory buffer with image data.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
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* other parameters are same as for AddFB2 generic DRM ioctl
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*/
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struct drm_exynos_ipp_task_buffer {
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__u32 id;
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__u32 fourcc;
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__u32 width, height;
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__u32 gem_id[4];
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__u32 offset[4];
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__u32 pitch[4];
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__u64 modifier;
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};
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/**
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* Rectangle for processing.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
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* @reserved: padding
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* @x,@y: left corner in pixels
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* @w,@h: width/height in pixels
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*/
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struct drm_exynos_ipp_task_rect {
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__u32 id;
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__u32 reserved;
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__u32 x;
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__u32 y;
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__u32 w;
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__u32 h;
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};
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/**
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* Image tranformation description.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
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* @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
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*/
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struct drm_exynos_ipp_task_transform {
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__u32 id;
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__u32 rotation;
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};
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/**
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* Image global alpha configuration for formats without alpha values.
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*
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* @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
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* @value: global alpha value (0-255)
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*/
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struct drm_exynos_ipp_task_alpha {
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__u32 id;
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__u32 value;
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};
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enum drm_exynos_ipp_flag {
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/* generate DRM event after processing */
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DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
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/* dry run, only check task parameters */
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DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
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/* non-blocking processing */
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DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
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};
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#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
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DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
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/**
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* Perform image processing described by array of drm_exynos_ipp_task_*
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* structures (parameters array).
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*
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* @ipp_id: id of IPP module to run the task
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* @flags: bitmask of drm_exynos_ipp_flag values
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* @reserved: padding
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* @params_size: size of parameters array (in bytes)
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* @params_ptr: pointer to parameters array or NULL
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* @user_data: (optional) data for drm event
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*/
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struct drm_exynos_ioctl_ipp_commit {
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__u32 ipp_id;
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__u32 flags;
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__u32 reserved;
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__u32 params_size;
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__u64 params_ptr;
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__u64 user_data;
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};
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#define DRM_EXYNOS_GEM_CREATE 0x00
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#define DRM_EXYNOS_GEM_MAP 0x01
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/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
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@@ -147,6 +360,11 @@ struct drm_exynos_g2d_exec {
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#define DRM_EXYNOS_G2D_EXEC 0x22
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/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
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/* IPP - Image Post Processing */
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#define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
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#define DRM_EXYNOS_IPP_GET_CAPS 0x41
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#define DRM_EXYNOS_IPP_GET_LIMITS 0x42
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#define DRM_EXYNOS_IPP_COMMIT 0x43
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#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
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@@ -165,8 +383,20 @@ struct drm_exynos_g2d_exec {
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#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
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#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_GET_RESOURCES, \
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struct drm_exynos_ioctl_ipp_get_res)
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#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
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#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_GET_LIMITS, \
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struct drm_exynos_ioctl_ipp_get_limits)
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#define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + \
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DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
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/* EXYNOS specific events */
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#define DRM_EXYNOS_G2D_EVENT 0x80000000
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#define DRM_EXYNOS_IPP_EVENT 0x80000002
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struct drm_exynos_g2d_event {
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struct drm_event base;
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@@ -177,6 +407,16 @@ struct drm_exynos_g2d_event {
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__u32 reserved;
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};
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struct drm_exynos_ipp_event {
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struct drm_event base;
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__u64 user_data;
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__u32 tv_sec;
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__u32 tv_usec;
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__u32 ipp_id;
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__u32 sequence;
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__u64 reserved;
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};
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#if defined(__cplusplus)
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}
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#endif
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|
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+492
-20
@@ -32,143 +32,615 @@ extern "C" {
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#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
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#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
|
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|
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/**
|
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* struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
|
||||
*/
|
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struct drm_tegra_gem_create {
|
||||
/**
|
||||
* @size:
|
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*
|
||||
* The size, in bytes, of the buffer object to be created.
|
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*/
|
||||
__u64 size;
|
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|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* A bitmask of flags that influence the creation of GEM objects:
|
||||
*
|
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* DRM_TEGRA_GEM_CREATE_TILED
|
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* Use the 16x16 tiling format for this buffer.
|
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*
|
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* DRM_TEGRA_GEM_CREATE_BOTTOM_UP
|
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* The buffer has a bottom-up layout.
|
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*/
|
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__u32 flags;
|
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|
||||
/**
|
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* @handle:
|
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*
|
||||
* The handle of the created GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_mmap {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle of the GEM object to obtain an mmap offset for.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* The mmap offset for the given GEM object. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_read {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to read the current value from.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The current syncpoint value. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_incr {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to increment.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_syncpt_wait {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to wait on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to wait.
|
||||
*/
|
||||
__u32 thresh;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, to wait.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The new syncpoint value after the wait. Set by the kernel upon
|
||||
* successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_open_channel - parameters for the open channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_open_channel {
|
||||
/**
|
||||
* @client:
|
||||
*
|
||||
* The client ID for this channel.
|
||||
*/
|
||||
__u32 client;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. Set by the kernel upon
|
||||
* successful completion of the IOCTL. This context needs to be passed
|
||||
* to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_close_channel - parameters for the close channel IOCTL
|
||||
*/
|
||||
struct drm_tegra_close_channel {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context of this channel. This is obtained from the
|
||||
* DRM_TEGRA_OPEN_CHANNEL IOCTL.
|
||||
*/
|
||||
__u64 context;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel for which to obtain
|
||||
* the syncpoint ID.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @index:
|
||||
*
|
||||
* Index of the client syncpoint for which to obtain the ID.
|
||||
*/
|
||||
__u32 index;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the given syncpoint. Set by the kernel upon successful
|
||||
* completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
|
||||
*/
|
||||
struct drm_tegra_get_syncpt_base {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying for which channel to obtain the
|
||||
* wait base.
|
||||
*/
|
||||
__u64 context;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint for which to obtain the wait base.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* The ID of the wait base corresponding to the client syncpoint. Set
|
||||
* by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_syncpt - syncpoint increment operation
|
||||
*/
|
||||
struct drm_tegra_syncpt {
|
||||
/**
|
||||
* @id:
|
||||
*
|
||||
* ID of the syncpoint to operate on.
|
||||
*/
|
||||
__u32 id;
|
||||
|
||||
/**
|
||||
* @incrs:
|
||||
*
|
||||
* Number of increments to perform for the syncpoint.
|
||||
*/
|
||||
__u32 incrs;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_cmdbuf - structure describing a command buffer
|
||||
*/
|
||||
struct drm_tegra_cmdbuf {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to a GEM object containing the command buffer.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, into the GEM object identified by @handle at
|
||||
* which the command buffer starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @words:
|
||||
*
|
||||
* Number of 32-bit words in this command buffer.
|
||||
*/
|
||||
__u32 words;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_reloc - GEM object relocation structure
|
||||
*/
|
||||
struct drm_tegra_reloc {
|
||||
struct {
|
||||
/**
|
||||
* @cmdbuf.handle:
|
||||
*
|
||||
* Handle to the GEM object containing the command buffer for
|
||||
* which to perform this GEM object relocation.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @cmdbuf.offset:
|
||||
*
|
||||
* Offset, in bytes, into the command buffer at which to
|
||||
* insert the relocated address.
|
||||
*/
|
||||
__u32 offset;
|
||||
} cmdbuf;
|
||||
struct {
|
||||
/**
|
||||
* @target.handle:
|
||||
*
|
||||
* Handle to the GEM object to be relocated.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @target.offset:
|
||||
*
|
||||
* Offset, in bytes, into the target GEM object at which the
|
||||
* relocated data starts.
|
||||
*/
|
||||
__u32 offset;
|
||||
} target;
|
||||
|
||||
/**
|
||||
* @shift:
|
||||
*
|
||||
* The number of bits by which to shift relocated addresses.
|
||||
*/
|
||||
__u32 shift;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_waitchk - wait check structure
|
||||
*/
|
||||
struct drm_tegra_waitchk {
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object containing a command stream on which to
|
||||
* perform the wait check.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @offset:
|
||||
*
|
||||
* Offset, in bytes, of the location in the command stream to perform
|
||||
* the wait check on.
|
||||
*/
|
||||
__u32 offset;
|
||||
|
||||
/**
|
||||
* @syncpt:
|
||||
*
|
||||
* ID of the syncpoint to wait check.
|
||||
*/
|
||||
__u32 syncpt;
|
||||
|
||||
/**
|
||||
* @thresh:
|
||||
*
|
||||
* Threshold value for which to check.
|
||||
*/
|
||||
__u32 thresh;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_submit - job submission structure
|
||||
*/
|
||||
struct drm_tegra_submit {
|
||||
/**
|
||||
* @context:
|
||||
*
|
||||
* The application context identifying the channel to use for the
|
||||
* execution of this job.
|
||||
*/
|
||||
__u64 context;
|
||||
__u32 num_syncpts;
|
||||
__u32 num_cmdbufs;
|
||||
__u32 num_relocs;
|
||||
__u32 num_waitchks;
|
||||
__u32 waitchk_mask;
|
||||
__u32 timeout;
|
||||
__u64 syncpts;
|
||||
__u64 cmdbufs;
|
||||
__u64 relocs;
|
||||
__u64 waitchks;
|
||||
__u32 fence; /* Return value */
|
||||
|
||||
__u32 reserved[5]; /* future expansion */
|
||||
/**
|
||||
* @num_syncpts:
|
||||
*
|
||||
* The number of syncpoints operated on by this job. This defines the
|
||||
* length of the array pointed to by @syncpts.
|
||||
*/
|
||||
__u32 num_syncpts;
|
||||
|
||||
/**
|
||||
* @num_cmdbufs:
|
||||
*
|
||||
* The number of command buffers to execute as part of this job. This
|
||||
* defines the length of the array pointed to by @cmdbufs.
|
||||
*/
|
||||
__u32 num_cmdbufs;
|
||||
|
||||
/**
|
||||
* @num_relocs:
|
||||
*
|
||||
* The number of relocations to perform before executing this job.
|
||||
* This defines the length of the array pointed to by @relocs.
|
||||
*/
|
||||
__u32 num_relocs;
|
||||
|
||||
/**
|
||||
* @num_waitchks:
|
||||
*
|
||||
* The number of wait checks to perform as part of this job. This
|
||||
* defines the length of the array pointed to by @waitchks.
|
||||
*/
|
||||
__u32 num_waitchks;
|
||||
|
||||
/**
|
||||
* @waitchk_mask:
|
||||
*
|
||||
* Bitmask of valid wait checks.
|
||||
*/
|
||||
__u32 waitchk_mask;
|
||||
|
||||
/**
|
||||
* @timeout:
|
||||
*
|
||||
* Timeout, in milliseconds, before this job is cancelled.
|
||||
*/
|
||||
__u32 timeout;
|
||||
|
||||
/**
|
||||
* @syncpts:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_syncpt structures that
|
||||
* specify the syncpoint operations performed as part of this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_syncpts.
|
||||
*/
|
||||
__u64 syncpts;
|
||||
|
||||
/**
|
||||
* @cmdbufs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_cmdbuf structures that
|
||||
* define the command buffers to execute as part of this job. The
|
||||
* number of elements in the array must be equal to the value given
|
||||
* by @num_syncpts.
|
||||
*/
|
||||
__u64 cmdbufs;
|
||||
|
||||
/**
|
||||
* @relocs:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_reloc structures that
|
||||
* specify the relocations that need to be performed before executing
|
||||
* this job. The number of elements in the array must be equal to the
|
||||
* value given by @num_relocs.
|
||||
*/
|
||||
__u64 relocs;
|
||||
|
||||
/**
|
||||
* @waitchks:
|
||||
*
|
||||
* A pointer to an array of &struct drm_tegra_waitchk structures that
|
||||
* specify the wait checks to be performed while executing this job.
|
||||
* The number of elements in the array must be equal to the value
|
||||
* given by @num_waitchks.
|
||||
*/
|
||||
__u64 waitchks;
|
||||
|
||||
/**
|
||||
* @fence:
|
||||
*
|
||||
* The threshold of the syncpoint associated with this job after it
|
||||
* has been completed. Set by the kernel upon successful completion of
|
||||
* the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
|
||||
* wait for this job to be finished.
|
||||
*/
|
||||
__u32 fence;
|
||||
|
||||
/**
|
||||
* @reserved:
|
||||
*
|
||||
* This field is reserved for future use. Must be 0.
|
||||
*/
|
||||
__u32 reserved[5];
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
|
||||
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode to set. Must be one of:
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_PITCH
|
||||
* pitch linear format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_TILED
|
||||
* 16x16 tiling format
|
||||
*
|
||||
* DRM_TEGRA_GEM_TILING_MODE_BLOCK
|
||||
* 16Bx2 tiling format
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The value to set for the tiling mode parameter.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_tiling {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the tiling parameters.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @mode:
|
||||
*
|
||||
* The tiling mode currently associated with the GEM object. Set by
|
||||
* the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 mode;
|
||||
|
||||
/**
|
||||
* @value:
|
||||
*
|
||||
* The tiling mode parameter currently associated with the GEM object.
|
||||
* Set by the kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 value;
|
||||
|
||||
/**
|
||||
* @pad:
|
||||
*
|
||||
* Structure padding that may be used in the future. Must be 0.
|
||||
*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
|
||||
#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_set_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to set the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags to set for the GEM object.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
|
||||
*/
|
||||
struct drm_tegra_gem_get_flags {
|
||||
/* input */
|
||||
/**
|
||||
* @handle:
|
||||
*
|
||||
* Handle to the GEM object for which to query the flags.
|
||||
*/
|
||||
__u32 handle;
|
||||
/* output */
|
||||
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* The flags currently associated with the GEM object. Set by the
|
||||
* kernel upon successful completion of the IOCTL.
|
||||
*/
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
@@ -193,7 +665,7 @@ struct drm_tegra_gem_get_flags {
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
|
||||
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
|
||||
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
|
||||
#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
|
||||
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
|
||||
#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
|
||||
|
||||
Reference in New Issue
Block a user