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drm/amd/pm: add sysfs node vclk1 and dclk1

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User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of
vcn and dcn

Signed-off-by: Tong Liu01 <Tong.Liu01@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tong Liu01
2023-03-30 11:07:08 +08:00
committed by Alex Deucher
parent fac7c51d62
commit d7001e7285
3 changed files with 42 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/include/kgd_pp_interface.h
+2
View File
@@ -104,7 +104,9 @@ enum pp_clock_type {
PP_FCLK,
PP_DCEFCLK,
PP_VCLK,
PP_VCLK1,
PP_DCLK,
PP_DCLK1,
OD_SCLK,
OD_MCLK,
OD_VDDC_CURVE,
drivers/gpu/drm/amd/pm/amdgpu_pm.c
+32
View File
@@ -1180,6 +1180,21 @@ static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
}
static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t count)
{
return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1195,6 +1210,21 @@ static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
struct device_attribute *attr,
char *buf)
{
return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
}
static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
struct device_attribute *attr,
const char *buf,
size_t count)
{
return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
}
static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -2002,7 +2032,9 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC),
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+8
View File
@@ -2022,8 +2022,12 @@ static int smu_force_ppclk_levels(void *handle,
clk_type = SMU_DCEFCLK; break;
case PP_VCLK:
clk_type = SMU_VCLK; break;
case PP_VCLK1:
clk_type = SMU_VCLK1; break;
case PP_DCLK:
clk_type = SMU_DCLK; break;
case PP_DCLK1:
clk_type = SMU_DCLK1; break;
case OD_SCLK:
clk_type = SMU_OD_SCLK; break;
case OD_MCLK:
@@ -2409,8 +2413,12 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
clk_type = SMU_DCEFCLK; break;
case PP_VCLK:
clk_type = SMU_VCLK; break;
case PP_VCLK1:
clk_type = SMU_VCLK1; break;
case PP_DCLK:
clk_type = SMU_DCLK; break;
case PP_DCLK1:
clk_type = SMU_DCLK1; break;
case OD_SCLK:
clk_type = SMU_OD_SCLK; break;
case OD_MCLK: