Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (50 commits) [MIPS] Add smp_call_function_single() [MIPS] thread_info.h: kmalloc + memset conversion to kzalloc [MIPS] Kexec: Fix several 64-bit bugs. [MIPS] Kexec: Fix several warnings. [MIPS] DDB5477: Remove support [MIPS] Fulong: Remove unneeded header file [MIPS] Cobalt: Enable UART on RaQ1 [MIPS] Remove unused GROUP_TOSHIBA_NAMES [MIPS] remove some duplicate includes [MIPS] Oprofile: Fix rm9000 performance counter handler [MIPS] Use -Werror on subdirectories which build cleanly. [MIPS] Yosemite: Fix warning. [MIPS] PMON: Fix cpustart declaration. [MIPS] Yosemite: Only build ll_ht_smp_irq_handler() if HYPERTRANSPORT. [MIPS] Yosemite: Fix build error due to undeclared titan_mailbox_irq(). [MIPS] Yosemite: Don't declare titan_mailbox_irq() as asmlinkage. [MIPS] Yosemite: Fix warnings in i2c-yoesmite by deleting the unused code. [MIPS] Delete unused arch/mips/gt64120/common/ [MIPS] Fix build warning in unaligned load/store emulator. [MIPS] IP32: Don't ignore request_irq's return value. ...
This commit is contained in:
Linus Torvalds
@@ -38,7 +38,8 @@ struct exec
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#define STACK_TOP TASK_SIZE
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#endif
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#ifdef CONFIG_64BIT
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#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE)
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#define STACK_TOP \
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(test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
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#endif
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#define STACK_TOP_MAX TASK_SIZE
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@@ -85,16 +85,6 @@
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#define MACH_GROUP_COBALT 7 /* Cobalt servers */
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#define MACH_COBALT_27 0 /* Proto "27" hardware */
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/*
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* Valid machtype for group NEC DDB
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*/
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#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */
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#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */
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#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */
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#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */
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#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */
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#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */
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/*
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* Valid machtype for group BAGET
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*/
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@@ -145,9 +135,6 @@
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#define MACH_TOSHIBA_RBTX4937 5
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#define MACH_TOSHIBA_RBTX4938 6
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#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
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"RBTX4927", "RBTX4937" }
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/*
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* Valid machtype for group Alchemy
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*/
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@@ -1,342 +0,0 @@
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/***********************************************************************
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* include/asm-mips/ddb5xxx/ddb5477.h
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* DDB 5477 specific definitions and macros.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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***********************************************************************
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*/
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#ifndef __ASM_DDB5XXX_DDB5477_H
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#define __ASM_DDB5XXX_DDB5477_H
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#include <irq.h>
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/*
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* This contains macros that are specific to DDB5477 or renamed from
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* DDB5476.
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*/
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/*
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* renamed PADRs
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*/
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#define DDB_LCS0 DDB_DCS2
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#define DDB_LCS1 DDB_DCS3
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#define DDB_LCS2 DDB_DCS4
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#define DDB_VRC5477 DDB_INTCS
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/*
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* New CPU interface registers
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*/
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#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
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#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
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#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
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#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
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#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
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#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
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#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
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#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
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#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
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#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
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#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
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#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
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#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
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#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
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#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
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#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
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/*
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* Timer registers
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*/
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#define DDB_REFCTRL_L DDB_T0CTRL
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#define DDB_REFCTRL_H (DDB_T0CTRL+4)
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#define DDB_REFCNTR DDB_T0CNTR
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#define DDB_SPT0CTRL_L DDB_T1CTRL
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#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
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#define DDB_SPT1CTRL_L DDB_T2CTRL
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#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
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#define DDB_SPT1CNTR DDB_T1CTRL
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#define DDB_WDTCTRL_L DDB_T3CTRL
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#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
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#define DDB_WDTCNTR DDB_T3CNTR
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/*
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* DMA registers are moved. We don't care about it for now. TODO.
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*/
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/*
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* BARs for ext PCI (PCI0)
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*/
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#undef DDB_BARC
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#undef DDB_BARB
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#define DDB_BARC0 0x0210 /* PCI0 Control */
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#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
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#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
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#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
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#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
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#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
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#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
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#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
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#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
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#define DDB_BARB0 0x0280 /* PCI0 BOOT */
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#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
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#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
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/*
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* BARs for IOPIC (PCI1)
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*/
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#define DDB_BARC1 0x0610 /* PCI1 Control */
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#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
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#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
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#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
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#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
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#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
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#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
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#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
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#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
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#define DDB_BARB1 0x0680 /* PCI1 BOOT */
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#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
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#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
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/*
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* Other registers for ext PCI (PCI0)
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*/
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#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
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#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
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#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
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#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
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#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
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#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
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#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
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#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
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/*
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* Other registers for IOPCI (PCI1)
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*/
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#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
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#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
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#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
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#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
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#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
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#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
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#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
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#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
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#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
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#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
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/*
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* Local Bus
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*/
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#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
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#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
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#undef DDB_LCST2
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#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
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#undef DDB_LCST3
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#undef DDB_LCST4
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#undef DDB_LCST5
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#undef DDB_LCST6
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#undef DDB_LCST7
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#undef DDB_LCST8
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#define DDB_ERRADR 0x0150 /* Error Address Register */
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#define DDB_ERRCS 0x0160
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#define DDB_BTM 0x0170 /* Boot Time Mode value */
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/*
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* MISC registers
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*/
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#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
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#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
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/*
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* Memory map (physical address)
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*
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* Note most of the following address must be properly aligned by the
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* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
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* PCI_IO_BASE must be aligned along 16MB boundary.
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*/
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/* the actual ram size is detected at run-time */
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#define DDB_SDRAM_BASE 0x00000000
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#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */
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#define DDB_PCI0_MEM_BASE 0x08000000
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#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
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#define DDB_PCI1_MEM_BASE 0x10000000
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#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
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#define DDB_PCI0_CONFIG_BASE 0x18000000
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#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
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#define DDB_PCI1_CONFIG_BASE 0x19000000
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#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
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#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
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#define DDB_PCI0_IO_BASE 0x1a000000
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#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
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#define DDB_PCI1_IO_BASE 0x1b000000
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#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
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#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
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#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
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#define DDB_LCS1_BASE 0x1d000000 /* misc */
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#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
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#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
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#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
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#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
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#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
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#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
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#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
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#define DDB_LED DDB_LCS1_BASE + 0x10000
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/*
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* DDB5477 specific functions
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*/
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#ifndef __ASSEMBLY__
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extern void ddb5477_irq_setup(void);
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/* route irq to cpu int pin */
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extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
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/* low-level routine for enabling vrc5477 irq, bypassing high-level */
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extern void ll_vrc5477_irq_enable(int vrc5477_irq);
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extern void ll_vrc5477_irq_disable(int vrc5477_irq);
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#endif /* !__ASSEMBLY__ */
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/* PCI intr ack share PCIW0 with PCI IO */
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#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
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/*
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* Interrupt mapping
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*
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* We have three interrupt controllers:
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*
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* . CPU itself - 8 sources
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* . i8259 - 16 sources
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* . vrc5477 - 32 sources
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*
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* They connected as follows:
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* all vrc5477 interrupts are routed to cpu IP2 (by software setting)
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* all i8359 are routed to INTC in vrc5477 (by hardware connection)
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*
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* All VRC5477 PCI interrupts are level-triggered (no ack needed).
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* All PCI irq but INTC are active low.
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*/
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/*
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* irq number block assignment
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*/
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#define NUM_CPU_IRQ 8
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#define NUM_VRC5477_IRQ 32
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#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
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#define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
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|
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/*
|
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* vrc5477 irq defs
|
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*/
|
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|
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#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
|
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#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
|
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#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
|
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#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
|
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#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
|
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#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
|
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#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
|
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#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
|
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#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
|
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#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
|
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#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
|
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#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
|
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#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
|
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#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
|
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#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
|
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#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
|
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#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
|
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#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
|
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#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
|
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#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
|
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#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
|
||||
#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
|
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#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
|
||||
#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
|
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#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
|
||||
#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
|
||||
#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
|
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#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
|
||||
#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
|
||||
#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
|
||||
#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
|
||||
#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
|
||||
|
||||
/*
|
||||
* i2859 irq assignment
|
||||
*/
|
||||
#define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE)
|
||||
#define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */
|
||||
#define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE)
|
||||
#define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
|
||||
#define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */
|
||||
#define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */
|
||||
#define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE)
|
||||
#define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE)
|
||||
#define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */
|
||||
#define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */
|
||||
#define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */
|
||||
#define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE)
|
||||
#define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */
|
||||
#define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE)
|
||||
#define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */
|
||||
#define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */
|
||||
|
||||
|
||||
/*
|
||||
* misc
|
||||
*/
|
||||
#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
|
||||
#define CPU_VRC5477_CASCADE 2
|
||||
|
||||
/*
|
||||
* debug routines
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#if defined(CONFIG_RUNTIME_DEBUG)
|
||||
extern void vrc5477_show_pdar_regs(void);
|
||||
extern void vrc5477_show_pci_regs(void);
|
||||
extern void vrc5477_show_bar_regs(void);
|
||||
extern void vrc5477_show_int_regs(void);
|
||||
extern void vrc5477_show_all_regs(void);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* RAM size
|
||||
*/
|
||||
extern int board_ram_size;
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif /* __ASM_DDB5XXX_DDB5477_H */
|
||||
@@ -1,263 +0,0 @@
|
||||
/*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: jsun@mvista.com or jsun@junsun.net
|
||||
*
|
||||
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
|
||||
* Sony Software Development Center Europe (SDCE), Brussels
|
||||
*
|
||||
* include/asm-mips/ddb5xxx/ddb5xxx.h
|
||||
* Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_DDB5XXX_DDB5XXX_H
|
||||
#define __ASM_DDB5XXX_DDB5XXX_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* This file is based on the following documentation:
|
||||
*
|
||||
* NEC Vrc 5074 System Controller Data Sheet, June 1998
|
||||
*
|
||||
* [jsun] It is modified so that this file only contains the macros
|
||||
* that are true for all DDB 5xxx boards. The modification is based on
|
||||
*
|
||||
* uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
|
||||
* Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#define DDB_BASE 0xbfa00000
|
||||
#define DDB_SIZE 0x00200000 /* 2 MB */
|
||||
|
||||
|
||||
/*
|
||||
* Physical Device Address Registers (PDARs)
|
||||
*/
|
||||
|
||||
#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
|
||||
#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
|
||||
#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
|
||||
#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
|
||||
#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
|
||||
#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
|
||||
#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
|
||||
#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
|
||||
#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
|
||||
#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
|
||||
#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
|
||||
#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
|
||||
/* [R/W] */
|
||||
#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
|
||||
/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
|
||||
|
||||
/*
|
||||
* CPU Interface Registers
|
||||
*/
|
||||
#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
|
||||
#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
|
||||
#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
|
||||
#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
|
||||
/* Enable [R/W] */
|
||||
#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
|
||||
#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
|
||||
|
||||
|
||||
/*
|
||||
* Memory-Interface Registers
|
||||
*/
|
||||
#define DDB_MEMCTRL 0x00C0 /* Memory Control */
|
||||
#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
|
||||
#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
|
||||
|
||||
|
||||
/*
|
||||
* PCI-Bus Registers
|
||||
*/
|
||||
#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
|
||||
#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
|
||||
#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
|
||||
#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
|
||||
#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
|
||||
|
||||
|
||||
/*
|
||||
* Local-Bus Registers
|
||||
*/
|
||||
#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
|
||||
#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
|
||||
#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
|
||||
#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
|
||||
#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
|
||||
#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
|
||||
#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
|
||||
#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
|
||||
#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
|
||||
/* Enables [R/W] */
|
||||
#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
|
||||
#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
|
||||
|
||||
|
||||
/*
|
||||
* DMA Registers
|
||||
*/
|
||||
#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
|
||||
#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
|
||||
#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
|
||||
#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
|
||||
#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
|
||||
#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
|
||||
|
||||
|
||||
/*
|
||||
* Timer Registers
|
||||
*/
|
||||
#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
|
||||
#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
|
||||
#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
|
||||
#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
|
||||
#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
|
||||
#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
|
||||
#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
|
||||
#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
|
||||
|
||||
|
||||
/*
|
||||
* PCI Configuration Space Registers
|
||||
*/
|
||||
#define DDB_PCI_BASE 0x0200
|
||||
|
||||
#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
|
||||
#define DDB_DID 0x0202 /* PCI Device ID [R] */
|
||||
#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
|
||||
#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
|
||||
#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
|
||||
#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
|
||||
#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
|
||||
#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
|
||||
#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
|
||||
#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
|
||||
#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
|
||||
#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
|
||||
#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
|
||||
#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
|
||||
/* (unimplemented) */
|
||||
#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
|
||||
#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
|
||||
#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
|
||||
/* (unimplemented) */
|
||||
#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
|
||||
#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
|
||||
#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
|
||||
#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
|
||||
#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
|
||||
#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
|
||||
#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
|
||||
#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
|
||||
#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
|
||||
#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
|
||||
#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
|
||||
#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
|
||||
|
||||
|
||||
/*
|
||||
* Nile 4 Register Access
|
||||
*/
|
||||
|
||||
static inline void ddb_sync(void)
|
||||
{
|
||||
volatile u32 *p = (volatile u32 *)0xbfc00000;
|
||||
(void)(*p);
|
||||
}
|
||||
|
||||
static inline void ddb_out32(u32 offset, u32 val)
|
||||
{
|
||||
*(volatile u32 *)(DDB_BASE+offset) = val;
|
||||
ddb_sync();
|
||||
}
|
||||
|
||||
static inline u32 ddb_in32(u32 offset)
|
||||
{
|
||||
u32 val = *(volatile u32 *)(DDB_BASE+offset);
|
||||
ddb_sync();
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void ddb_out16(u32 offset, u16 val)
|
||||
{
|
||||
*(volatile u16 *)(DDB_BASE+offset) = val;
|
||||
ddb_sync();
|
||||
}
|
||||
|
||||
static inline u16 ddb_in16(u32 offset)
|
||||
{
|
||||
u16 val = *(volatile u16 *)(DDB_BASE+offset);
|
||||
ddb_sync();
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void ddb_out8(u32 offset, u8 val)
|
||||
{
|
||||
*(volatile u8 *)(DDB_BASE+offset) = val;
|
||||
ddb_sync();
|
||||
}
|
||||
|
||||
static inline u8 ddb_in8(u32 offset)
|
||||
{
|
||||
u8 val = *(volatile u8 *)(DDB_BASE+offset);
|
||||
ddb_sync();
|
||||
return val;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Physical Device Address Registers
|
||||
*/
|
||||
|
||||
extern u32
|
||||
ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
|
||||
extern void
|
||||
ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
|
||||
int on_memory_bus, int pci_visible);
|
||||
|
||||
/*
|
||||
* PCI Master Registers
|
||||
*/
|
||||
|
||||
#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
|
||||
#define DDB_PCICMD_IO 1 /* PCI I/O Space */
|
||||
#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
|
||||
#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
|
||||
|
||||
/*
|
||||
* additional options for pci init reg (no shifting needed)
|
||||
*/
|
||||
#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
|
||||
#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
|
||||
|
||||
|
||||
extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
|
||||
|
||||
/*
|
||||
* we need to reset pci bus when we start up and shutdown
|
||||
*/
|
||||
extern void ddb_pci_reset_bus(void);
|
||||
|
||||
|
||||
/*
|
||||
* include the board dependent part
|
||||
*/
|
||||
#if defined(CONFIG_DDB5477)
|
||||
#include <asm/ddb5xxx/ddb5477.h>
|
||||
#else
|
||||
#error "Unknown DDB board!"
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_DDB5XXX_DDB5XXX_H */
|
||||
@@ -265,7 +265,7 @@ do { \
|
||||
#ifdef CONFIG_MIPS32_N32
|
||||
#define __SET_PERSONALITY32_N32() \
|
||||
do { \
|
||||
current->thread.mflags |= MF_N32; \
|
||||
set_thread_flag(TIF_32BIT_ADDR); \
|
||||
current->thread.abi = &mips_abi_n32; \
|
||||
} while (0)
|
||||
#else
|
||||
@@ -276,7 +276,8 @@ do { \
|
||||
#ifdef CONFIG_MIPS32_O32
|
||||
#define __SET_PERSONALITY32_O32() \
|
||||
do { \
|
||||
current->thread.mflags |= MF_O32; \
|
||||
set_thread_flag(TIF_32BIT_REGS); \
|
||||
set_thread_flag(TIF_32BIT_ADDR); \
|
||||
current->thread.abi = &mips_abi_32; \
|
||||
} while (0)
|
||||
#else
|
||||
@@ -299,13 +300,13 @@ do { \
|
||||
|
||||
#define SET_PERSONALITY(ex, ibcs2) \
|
||||
do { \
|
||||
current->thread.mflags &= ~MF_ABI_MASK; \
|
||||
clear_thread_flag(TIF_32BIT_REGS); \
|
||||
clear_thread_flag(TIF_32BIT_ADDR); \
|
||||
\
|
||||
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
|
||||
__SET_PERSONALITY32(ex); \
|
||||
else { \
|
||||
current->thread.mflags |= MF_N64; \
|
||||
else \
|
||||
current->thread.abi = &mips_abi; \
|
||||
} \
|
||||
\
|
||||
if (ibcs2) \
|
||||
set_personality(PER_SVR4); \
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
|
||||
* Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
|
||||
* Copyright (C) MIPS Technologies, Inc.
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
@@ -23,6 +23,11 @@ static inline void name(void) \
|
||||
__asm__ __volatile__ (#name); \
|
||||
}
|
||||
|
||||
/*
|
||||
* MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
|
||||
*/
|
||||
extern void mips_ihb(void);
|
||||
|
||||
#endif
|
||||
|
||||
ASMMACRO(_ssnop,
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
|
||||
#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
|
||||
|
||||
#define cpu_has_llsc 1
|
||||
#define cpu_has_64bits 1
|
||||
#define cpu_has_inclusive_pcaches 0
|
||||
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_smartmips 0
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_ic_fills_f_dc 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
|
||||
#define cpu_has_mips32r1 0
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
|
||||
#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */
|
||||
@@ -0,0 +1,8 @@
|
||||
#ifndef __ASM_MACH_TX49XX_KMALLOC_H
|
||||
#define __ASM_MACH_TX49XX_KMALLOC_H
|
||||
|
||||
/*
|
||||
* All happy, no need to define ARCH_KMALLOC_MINALIGN
|
||||
*/
|
||||
|
||||
#endif /* __ASM_MACH_TX49XX_KMALLOC_H */
|
||||
@@ -67,6 +67,7 @@
|
||||
#define MIPS_REVISION_CORID_CORE_FPGAR2 8
|
||||
#define MIPS_REVISION_CORID_CORE_FPGA3 9
|
||||
#define MIPS_REVISION_CORID_CORE_24K 10
|
||||
#define MIPS_REVISION_CORID_CORE_FPGA4 11
|
||||
|
||||
/**** Artificial corid defines ****/
|
||||
/*
|
||||
|
||||
@@ -8,6 +8,12 @@
|
||||
|
||||
#include <linux/cpumask.h>
|
||||
|
||||
/*
|
||||
* How many VPEs and TCs is Linux allowed to use? 0 means no limit.
|
||||
*/
|
||||
extern int tclimit;
|
||||
extern int vpelimit;
|
||||
|
||||
extern cpumask_t mt_fpu_cpumask;
|
||||
extern unsigned long mt_fpemul_threshold;
|
||||
|
||||
|
||||
@@ -22,7 +22,7 @@ struct callvectors {
|
||||
char* (*gets) (char*);
|
||||
union {
|
||||
int (*smpfork) (unsigned long cp, char *sp);
|
||||
int (*cpustart) (long, long, long, long);
|
||||
int (*cpustart) (long, void (*)(void), void *, long);
|
||||
} _s;
|
||||
int (*semlock) (int sem);
|
||||
void (*semunlock) (int sem);
|
||||
|
||||
@@ -62,8 +62,9 @@ extern unsigned int vced_count, vcei_count;
|
||||
* This decides where the kernel will search for a free chunk of vm
|
||||
* space during mmap's.
|
||||
*/
|
||||
#define TASK_UNMAPPED_BASE ((current->thread.mflags & MF_32BIT_ADDR) ? \
|
||||
PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
|
||||
#define TASK_UNMAPPED_BASE \
|
||||
(test_thread_flag(TIF_32BIT_ADDR) ? \
|
||||
PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
|
||||
#endif
|
||||
|
||||
#define NUM_FPU_REGS 32
|
||||
@@ -132,22 +133,11 @@ struct thread_struct {
|
||||
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
|
||||
unsigned long error_code;
|
||||
unsigned long trap_no;
|
||||
#define MF_FIXADE 1 /* Fix address errors in software */
|
||||
#define MF_LOGADE 2 /* Log address errors to syslog */
|
||||
#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */
|
||||
#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */
|
||||
#define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */
|
||||
unsigned long mflags;
|
||||
unsigned long irix_trampoline; /* Wheee... */
|
||||
unsigned long irix_oldctx;
|
||||
struct mips_abi *abi;
|
||||
};
|
||||
|
||||
#define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR)
|
||||
#define MF_O32 (MF_32BIT_REGS | MF_32BIT_ADDR)
|
||||
#define MF_N32 MF_32BIT_ADDR
|
||||
#define MF_N64 0
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_FPAFF
|
||||
#define FPAFF_INIT \
|
||||
.emulated_fp = 0, \
|
||||
@@ -200,10 +190,6 @@ struct thread_struct {
|
||||
.cp0_baduaddr = 0, \
|
||||
.error_code = 0, \
|
||||
.trap_no = 0, \
|
||||
/* \
|
||||
* For now the default is to fix address errors \
|
||||
*/ \
|
||||
.mflags = MF_FIXADE, \
|
||||
.irix_trampoline = 0, \
|
||||
.irix_oldctx = 0, \
|
||||
}
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
#ifndef __ASM_SECCOMP_H
|
||||
|
||||
#include <linux/thread_info.h>
|
||||
#include <linux/unistd.h>
|
||||
|
||||
#define __NR_seccomp_read __NR_read
|
||||
#define __NR_seccomp_write __NR_write
|
||||
#define __NR_seccomp_exit __NR_exit
|
||||
#define __NR_seccomp_sigreturn __NR_rt_sigreturn
|
||||
|
||||
/*
|
||||
* Kludge alert:
|
||||
*
|
||||
* The generic seccomp code currently allows only a single compat ABI. Until
|
||||
* this is fixed we priorize O32 as the compat ABI over N32.
|
||||
*/
|
||||
#ifdef CONFIG_MIPS32_O32
|
||||
|
||||
#define TIF_32BIT TIF_32BIT_REGS
|
||||
|
||||
#define __NR_seccomp_read_32 4003
|
||||
#define __NR_seccomp_write_32 4004
|
||||
#define __NR_seccomp_exit_32 4001
|
||||
#define __NR_seccomp_sigreturn_32 4193 /* rt_sigreturn */
|
||||
|
||||
#elif defined(CONFIG_MIPS32_N32)
|
||||
|
||||
#define TIF_32BIT _TIF_32BIT_ADDR
|
||||
|
||||
#define __NR_seccomp_read_32 6000
|
||||
#define __NR_seccomp_write_32 6001
|
||||
#define __NR_seccomp_exit_32 6058
|
||||
#define __NR_seccomp_sigreturn_32 6211 /* rt_sigreturn */
|
||||
|
||||
#endif /* CONFIG_MIPS32_O32 */
|
||||
|
||||
#endif /* __ASM_SECCOMP_H */
|
||||
@@ -46,10 +46,12 @@ struct task_struct;
|
||||
|
||||
#define __mips_mt_fpaff_switch_to(prev) \
|
||||
do { \
|
||||
struct thread_info *__prev_ti = task_thread_info(prev); \
|
||||
\
|
||||
if (cpu_has_fpu && \
|
||||
(prev->thread.mflags & MF_FPUBOUND) && \
|
||||
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
|
||||
prev->thread.mflags &= ~MF_FPUBOUND; \
|
||||
test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
|
||||
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
|
||||
clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
|
||||
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
|
||||
} \
|
||||
next->thread.emulated_fp = 0; \
|
||||
|
||||
@@ -46,7 +46,7 @@ struct thread_info {
|
||||
{ \
|
||||
.task = &tsk, \
|
||||
.exec_domain = &default_exec_domain, \
|
||||
.flags = 0, \
|
||||
.flags = _TIF_FIXADE, \
|
||||
.cpu = 0, \
|
||||
.preempt_count = 1, \
|
||||
.addr_limit = KERNEL_DS, \
|
||||
@@ -87,9 +87,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
|
||||
({ \
|
||||
struct thread_info *ret; \
|
||||
\
|
||||
ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \
|
||||
if (ret) \
|
||||
memset(ret, 0, THREAD_SIZE); \
|
||||
ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \
|
||||
\
|
||||
ret; \
|
||||
})
|
||||
#else
|
||||
@@ -118,6 +117,11 @@ register struct thread_info *__current_thread_info __asm__("$28");
|
||||
#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */
|
||||
#define TIF_MEMDIE 18
|
||||
#define TIF_FREEZE 19
|
||||
#define TIF_FIXADE 20 /* Fix address errors in software */
|
||||
#define TIF_LOGADE 21 /* Log address errors to syslog */
|
||||
#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
|
||||
#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
|
||||
#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
|
||||
#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
|
||||
|
||||
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
|
||||
@@ -129,6 +133,11 @@ register struct thread_info *__current_thread_info __asm__("$28");
|
||||
#define _TIF_USEDFPU (1<<TIF_USEDFPU)
|
||||
#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
|
||||
#define _TIF_FREEZE (1<<TIF_FREEZE)
|
||||
#define _TIF_FIXADE (1<<TIF_FIXADE)
|
||||
#define _TIF_LOGADE (1<<TIF_LOGADE)
|
||||
#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
|
||||
#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
|
||||
#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
|
||||
|
||||
/* work to do on interrupt/exception return */
|
||||
#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)
|
||||
|
||||
@@ -52,4 +52,6 @@
|
||||
#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
|
||||
#define RBTX4927_RTL_8019_IRQ (29)
|
||||
|
||||
int toshiba_rbtx4927_irq_nested(int sw_irq);
|
||||
|
||||
#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
|
||||
|
||||
@@ -340,16 +340,17 @@
|
||||
#define __NR_signalfd (__NR_Linux + 317)
|
||||
#define __NR_timerfd (__NR_Linux + 318)
|
||||
#define __NR_eventfd (__NR_Linux + 319)
|
||||
#define __NR_fallocate (__NR_Linux + 320)
|
||||
|
||||
/*
|
||||
* Offset of the last Linux o32 flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 319
|
||||
#define __NR_Linux_syscalls 320
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
|
||||
|
||||
#define __NR_O32_Linux 4000
|
||||
#define __NR_O32_Linux_syscalls 319
|
||||
#define __NR_O32_Linux_syscalls 320
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI64
|
||||
|
||||
@@ -636,16 +637,17 @@
|
||||
#define __NR_signalfd (__NR_Linux + 276)
|
||||
#define __NR_timerfd (__NR_Linux + 277)
|
||||
#define __NR_eventfd (__NR_Linux + 278)
|
||||
#define __NR_fallocate (__NR_Linux + 279)
|
||||
|
||||
/*
|
||||
* Offset of the last Linux 64-bit flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 278
|
||||
#define __NR_Linux_syscalls 279
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
|
||||
|
||||
#define __NR_64_Linux 5000
|
||||
#define __NR_64_Linux_syscalls 278
|
||||
#define __NR_64_Linux_syscalls 279
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_NABI32
|
||||
|
||||
@@ -936,16 +938,17 @@
|
||||
#define __NR_signalfd (__NR_Linux + 280)
|
||||
#define __NR_timerfd (__NR_Linux + 281)
|
||||
#define __NR_eventfd (__NR_Linux + 282)
|
||||
#define __NR_fallocate (__NR_Linux + 283)
|
||||
|
||||
/*
|
||||
* Offset of the last N32 flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 282
|
||||
#define __NR_Linux_syscalls 283
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
|
||||
|
||||
#define __NR_N32_Linux 6000
|
||||
#define __NR_N32_Linux_syscalls 282
|
||||
#define __NR_N32_Linux_syscalls 283
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
|
||||
@@ -182,9 +182,8 @@
|
||||
* exceptions.
|
||||
*/
|
||||
#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
|
||||
defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MOMENCO_OCELOT) || \
|
||||
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_SGI_IP32) || \
|
||||
defined(CONFIG_WR_PPMC)
|
||||
defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \
|
||||
defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
|
||||
#define ICACHE_REFILLS_WORKAROUND_WAR 1
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user