Merge tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - add support for Realtek RTL9302C - add support for Mobileye EyeQ6H - add support for Mobileye EyeQ OLB system controller - improve r4k clocksource - add mode for emulating ieee754 NAN2008 - rework for BMIPS CBR address handling - fixes for Loongson 2K1000 - defconfig updates - cleanups and fixes * tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits) MIPS: config: Add ip30_defconfig MIPS: config: lemote2f: Regenerate defconfig MIPS: config: generic: Add board-litex MIPS: config: Enable MSA and virtualization for MIPS64R6 MIPS: Fix fallback march for SB1 mips: dts: realtek: Add RTL9302C board mips: generic: add fdt fixup for Realtek reference board mips: select REALTEK_OTTO_TIMER for Realtek platforms dt-bindings: interrupt-controller: realtek,rtl-intc: Add rtl9300-intc dt-bindings: mips: realtek: Add rtl930x-soc compatible dt-bindings: vendor-prefixes: Add Cameo Communications mips: dts: realtek: add device_type property to cpu node mips: dts: realtek: use "serial" instead of "uart" in node name MIPS: Implement ieee754 NAN2008 emulation mode MIPS: lantiq: improve USB initialization MIPS: GIC: Generate redirect block accessors MIPS: CPS: Add a couple of multi-cluster utility functions MIPS: Octeron: remove source file executable bit MAINTAINERS: Mobileye: add OLB drivers and dt-bindings MIPS: mobileye: eyeq5: add OLB system-controller node ...
This commit is contained in:
Linus Torvalds
@@ -21,7 +21,9 @@ static struct clocksource clocksource_mips = {
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.name = "MIPS",
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.read = c0_hpt_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS |
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CLOCK_SOURCE_MUST_VERIFY |
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CLOCK_SOURCE_VERIFY_PERCPU,
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};
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static u64 __maybe_unused notrace r4k_read_sched_clock(void)
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@@ -66,6 +68,18 @@ static bool rdhwr_count_usable(void)
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return false;
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}
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static inline __init bool count_can_be_sched_clock(void)
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{
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if (IS_ENABLED(CONFIG_CPU_FREQ))
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return false;
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if (num_possible_cpus() > 1 &&
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!IS_ENABLED(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK))
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return false;
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return true;
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}
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#ifdef CONFIG_CPU_FREQ
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static bool __read_mostly r4k_clock_unstable;
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@@ -111,7 +125,8 @@ int __init init_r4k_clocksource(void)
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return -ENXIO;
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/* Calculate a somewhat reasonable rating value */
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clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
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clocksource_mips.rating = 200;
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clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99);
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/*
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* R2 onwards makes the count accessible to user mode so it can be used
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@@ -122,9 +137,8 @@ int __init init_r4k_clocksource(void)
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clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
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#ifndef CONFIG_CPU_FREQ
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sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
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#endif
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if (count_can_be_sched_clock())
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sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
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return 0;
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}
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@@ -318,6 +318,10 @@ void mips_set_personality_nan(struct arch_elf_state *state)
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t->thread.fpu.fcr31 = c->fpu_csr31;
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switch (state->nan_2008) {
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case 0:
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if (!(c->fpu_msk31 & FPU_CSR_NAN2008))
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t->thread.fpu.fcr31 &= ~FPU_CSR_NAN2008;
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if (!(c->fpu_msk31 & FPU_CSR_ABS2008))
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t->thread.fpu.fcr31 &= ~FPU_CSR_ABS2008;
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break;
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case 1:
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if (!(c->fpu_msk31 & FPU_CSR_NAN2008))
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@@ -144,7 +144,7 @@ static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
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* IEEE 754 conformance mode to use. Affects the NaN encoding and the
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* ABS.fmt/NEG.fmt execution mode.
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*/
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static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
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static enum { STRICT, EMULATED, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
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/*
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* Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
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@@ -160,6 +160,7 @@ static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
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switch (ieee754) {
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case STRICT:
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case EMULATED:
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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@@ -204,6 +205,10 @@ static void cpu_set_nan_2008(struct cpuinfo_mips *c)
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mips_use_nan_legacy = !cpu_has_nan_2008;
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mips_use_nan_2008 = !!cpu_has_nan_2008;
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break;
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case EMULATED:
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/* Pretend ABS2008/NAN2008 options are dynamic */
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c->fpu_msk31 &= ~(FPU_CSR_NAN2008 | FPU_CSR_ABS2008);
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fallthrough;
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case RELAXED:
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mips_use_nan_legacy = true;
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mips_use_nan_2008 = true;
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@@ -226,6 +231,8 @@ static int __init ieee754_setup(char *s)
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return -1;
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else if (!strcmp(s, "strict"))
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ieee754 = STRICT;
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else if (!strcmp(s, "emulated"))
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ieee754 = EMULATED;
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else if (!strcmp(s, "legacy"))
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ieee754 = LEGACY;
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else if (!strcmp(s, "2008"))
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@@ -512,3 +512,40 @@ void mips_cm_error_report(void)
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/* reprime cause register */
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write_gcr_error_cause(cm_error);
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}
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unsigned int mips_cps_first_online_in_cluster(void)
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{
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unsigned int local_cl;
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int i;
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local_cl = cpu_cluster(¤t_cpu_data);
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/*
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* We rely upon knowledge that CPUs are numbered sequentially by
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* cluster - ie. CPUs 0..X will be in cluster 0, CPUs X+1..Y in cluster
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* 1, CPUs Y+1..Z in cluster 2 etc. This means that CPUs in the same
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* cluster will immediately precede or follow one another.
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*
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* First we scan backwards, until we find an online CPU in the cluster
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* or we move on to another cluster.
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*/
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for (i = smp_processor_id() - 1; i >= 0; i--) {
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if (cpu_cluster(&cpu_data[i]) != local_cl)
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break;
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if (!cpu_online(i))
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continue;
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return false;
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}
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/* Then do the same for higher numbered CPUs */
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for (i = smp_processor_id() + 1; i < nr_cpu_ids; i++) {
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if (cpu_cluster(&cpu_data[i]) != local_cl)
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break;
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if (!cpu_online(i))
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continue;
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return false;
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}
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/* We found no online CPUs in the local cluster */
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return true;
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}
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@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, u32 val)
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info.val = val;
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bmips_set_reset_vec_remote(&info);
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} else {
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void __iomem *cbr = BMIPS_GET_CBR();
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void __iomem *cbr = bmips_cbr_addr;
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if (cpu == 0)
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__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
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@@ -591,7 +591,8 @@ asmlinkage void __weak plat_wired_tlb_setup(void)
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void bmips_cpu_setup(void)
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{
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void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
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void __iomem __maybe_unused *cbr = bmips_cbr_addr;
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u32 __maybe_unused rac_addr;
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u32 __maybe_unused cfg;
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switch (current_cpu_type()) {
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@@ -620,6 +621,23 @@ void bmips_cpu_setup(void)
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__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
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break;
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case CPU_BMIPS4350:
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rac_addr = BMIPS_RAC_CONFIG_1;
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if (!(read_c0_brcm_cmt_local() & (1 << 31)))
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rac_addr = BMIPS_RAC_CONFIG;
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/* Enable data RAC */
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cfg = __raw_readl(cbr + rac_addr);
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__raw_writel(cfg | 0xf, cbr + rac_addr);
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__raw_readl(cbr + rac_addr);
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/* Flush stale data out of the readahead cache */
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cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
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__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
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__raw_readl(cbr + BMIPS_RAC_CONFIG);
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break;
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case CPU_BMIPS4380:
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/* CBG workaround for early BMIPS4380 CPUs */
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switch (read_c0_prid()) {
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@@ -462,8 +462,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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return -EIO;
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}
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synchronise_count_master(cpu);
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/* Wait for CPU to finish startup & mark itself online before return */
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wait_for_completion(&cpu_running);
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return 0;
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+207
-84
@@ -2,121 +2,244 @@
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/*
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* Count register synchronisation.
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*
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* All CPUs will have their count registers synchronised to the CPU0 next time
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* value. This can cause a small timewarp for CPU0. All other CPU's should
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* not have done anything significant (but they may have had interrupts
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* enabled briefly - prom_smp_finish() should not be responsible for enabling
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* interrupts...)
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* Derived from arch/x86/kernel/tsc_sync.c
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* Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
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*/
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#include <linux/kernel.h>
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#include <linux/irqflags.h>
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#include <linux/cpumask.h>
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#include <linux/atomic.h>
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#include <linux/nmi.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <asm/r4k-timer.h>
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#include <linux/atomic.h>
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#include <asm/barrier.h>
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#include <asm/mipsregs.h>
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#include <asm/time.h>
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static unsigned int initcount = 0;
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static atomic_t count_count_start = ATOMIC_INIT(0);
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static atomic_t count_count_stop = ATOMIC_INIT(0);
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#define COUNTON 100
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#define NR_LOOPS 3
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#define LOOP_TIMEOUT 20
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#define COUNTON 100
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#define NR_LOOPS 3
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/*
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* Entry/exit counters that make sure that both CPUs
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* run the measurement code at once:
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*/
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static atomic_t start_count;
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static atomic_t stop_count;
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static atomic_t test_runs;
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void synchronise_count_master(int cpu)
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/*
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* We use a raw spinlock in this exceptional case, because
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* we want to have the fastest, inlined, non-debug version
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* of a critical section, to be able to prove counter time-warps:
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*/
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static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
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static uint32_t last_counter;
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static uint32_t max_warp;
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static int nr_warps;
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static int random_warps;
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/*
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* Counter warp measurement loop running on both CPUs.
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*/
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static uint32_t check_counter_warp(void)
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{
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int i;
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unsigned long flags;
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uint32_t start, now, prev, end, cur_max_warp = 0;
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int i, cur_warps = 0;
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pr_info("Synchronize counters for CPU %u: ", cpu);
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start = read_c0_count();
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end = start + (uint32_t) mips_hpt_frequency / 1000 * LOOP_TIMEOUT;
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local_irq_save(flags);
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/*
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* We loop a few times to get a primed instruction cache,
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* then the last pass is more or less synchronised and
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* the master and slaves each set their cycle counters to a known
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* value all at once. This reduces the chance of having random offsets
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* between the processors, and guarantees that the maximum
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* delay between the cycle counters is never bigger than
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* the latency of information-passing (cachelines) between
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* two CPUs.
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*/
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for (i = 0; i < NR_LOOPS; i++) {
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/* slaves loop on '!= 2' */
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while (atomic_read(&count_count_start) != 1)
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mb();
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atomic_set(&count_count_stop, 0);
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smp_wmb();
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/* Let the slave writes its count register */
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atomic_inc(&count_count_start);
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/* Count will be initialised to current timer */
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if (i == 1)
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initcount = read_c0_count();
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for (i = 0; ; i++) {
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/*
|
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* We take the global lock, measure counter, save the
|
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* previous counter that was measured (possibly on
|
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* another CPU) and update the previous counter timestamp.
|
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*/
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arch_spin_lock(&sync_lock);
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prev = last_counter;
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now = read_c0_count();
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last_counter = now;
|
||||
arch_spin_unlock(&sync_lock);
|
||||
|
||||
/*
|
||||
* Everyone initialises count in the last loop:
|
||||
* Be nice every now and then (and also check whether
|
||||
* measurement is done [we also insert a 10 million
|
||||
* loops safety exit, so we dont lock up in case the
|
||||
* counter is totally broken]):
|
||||
*/
|
||||
if (i == NR_LOOPS-1)
|
||||
write_c0_count(initcount);
|
||||
|
||||
if (unlikely(!(i & 7))) {
|
||||
if (now > end || i > 10000000)
|
||||
break;
|
||||
cpu_relax();
|
||||
touch_nmi_watchdog();
|
||||
}
|
||||
/*
|
||||
* Wait for slave to leave the synchronization point:
|
||||
* Outside the critical section we can now see whether
|
||||
* we saw a time-warp of the counter going backwards:
|
||||
*/
|
||||
while (atomic_read(&count_count_stop) != 1)
|
||||
mb();
|
||||
atomic_set(&count_count_start, 0);
|
||||
smp_wmb();
|
||||
atomic_inc(&count_count_stop);
|
||||
if (unlikely(prev > now)) {
|
||||
arch_spin_lock(&sync_lock);
|
||||
max_warp = max(max_warp, prev - now);
|
||||
cur_max_warp = max_warp;
|
||||
/*
|
||||
* Check whether this bounces back and forth. Only
|
||||
* one CPU should observe time going backwards.
|
||||
*/
|
||||
if (cur_warps != nr_warps)
|
||||
random_warps++;
|
||||
nr_warps++;
|
||||
cur_warps = nr_warps;
|
||||
arch_spin_unlock(&sync_lock);
|
||||
}
|
||||
}
|
||||
/* Arrange for an interrupt in a short while */
|
||||
write_c0_compare(read_c0_count() + COUNTON);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
/*
|
||||
* i386 code reported the skew here, but the
|
||||
* count registers were almost certainly out of sync
|
||||
* so no point in alarming people
|
||||
*/
|
||||
pr_cont("done.\n");
|
||||
WARN(!(now-start),
|
||||
"Warning: zero counter calibration delta: %d [max: %d]\n",
|
||||
now-start, end-start);
|
||||
return cur_max_warp;
|
||||
}
|
||||
|
||||
/*
|
||||
* The freshly booted CPU initiates this via an async SMP function call.
|
||||
*/
|
||||
static void check_counter_sync_source(void *__cpu)
|
||||
{
|
||||
unsigned int cpu = (unsigned long)__cpu;
|
||||
int cpus = 2;
|
||||
|
||||
atomic_set(&test_runs, NR_LOOPS);
|
||||
retry:
|
||||
/* Wait for the target to start. */
|
||||
while (atomic_read(&start_count) != cpus - 1)
|
||||
cpu_relax();
|
||||
|
||||
/*
|
||||
* Trigger the target to continue into the measurement too:
|
||||
*/
|
||||
atomic_inc(&start_count);
|
||||
|
||||
check_counter_warp();
|
||||
|
||||
while (atomic_read(&stop_count) != cpus-1)
|
||||
cpu_relax();
|
||||
|
||||
/*
|
||||
* If the test was successful set the number of runs to zero and
|
||||
* stop. If not, decrement the number of runs an check if we can
|
||||
* retry. In case of random warps no retry is attempted.
|
||||
*/
|
||||
if (!nr_warps) {
|
||||
atomic_set(&test_runs, 0);
|
||||
|
||||
pr_info("Counter synchronization [CPU#%d -> CPU#%u]: passed\n",
|
||||
smp_processor_id(), cpu);
|
||||
} else if (atomic_dec_and_test(&test_runs) || random_warps) {
|
||||
/* Force it to 0 if random warps brought us here */
|
||||
atomic_set(&test_runs, 0);
|
||||
|
||||
pr_info("Counter synchronization [CPU#%d -> CPU#%u]:\n",
|
||||
smp_processor_id(), cpu);
|
||||
pr_info("Measured %d cycles counter warp between CPUs", max_warp);
|
||||
if (random_warps)
|
||||
pr_warn("Counter warped randomly between CPUs\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset it - just in case we boot another CPU later:
|
||||
*/
|
||||
atomic_set(&start_count, 0);
|
||||
random_warps = 0;
|
||||
nr_warps = 0;
|
||||
max_warp = 0;
|
||||
last_counter = 0;
|
||||
|
||||
/*
|
||||
* Let the target continue with the bootup:
|
||||
*/
|
||||
atomic_inc(&stop_count);
|
||||
|
||||
/*
|
||||
* Retry, if there is a chance to do so.
|
||||
*/
|
||||
if (atomic_read(&test_runs) > 0)
|
||||
goto retry;
|
||||
}
|
||||
|
||||
/*
|
||||
* Freshly booted CPUs call into this:
|
||||
*/
|
||||
void synchronise_count_slave(int cpu)
|
||||
{
|
||||
int i;
|
||||
unsigned long flags;
|
||||
uint32_t cur_max_warp, gbl_max_warp, count;
|
||||
int cpus = 2;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (!cpu_has_counter || !mips_hpt_frequency)
|
||||
return;
|
||||
|
||||
/* Kick the control CPU into the counter synchronization function */
|
||||
smp_call_function_single(cpumask_first(cpu_online_mask),
|
||||
check_counter_sync_source,
|
||||
(unsigned long *)(unsigned long)cpu, 0);
|
||||
retry:
|
||||
/*
|
||||
* Register this CPU's participation and wait for the
|
||||
* source CPU to start the measurement:
|
||||
*/
|
||||
atomic_inc(&start_count);
|
||||
while (atomic_read(&start_count) != cpus)
|
||||
cpu_relax();
|
||||
|
||||
cur_max_warp = check_counter_warp();
|
||||
|
||||
/*
|
||||
* Not every cpu is online at the time this gets called,
|
||||
* so we first wait for the master to say everyone is ready
|
||||
* Store the maximum observed warp value for a potential retry:
|
||||
*/
|
||||
gbl_max_warp = max_warp;
|
||||
|
||||
for (i = 0; i < NR_LOOPS; i++) {
|
||||
atomic_inc(&count_count_start);
|
||||
while (atomic_read(&count_count_start) != 2)
|
||||
mb();
|
||||
/*
|
||||
* Ok, we are done:
|
||||
*/
|
||||
atomic_inc(&stop_count);
|
||||
|
||||
/*
|
||||
* Everyone initialises count in the last loop:
|
||||
*/
|
||||
if (i == NR_LOOPS-1)
|
||||
write_c0_count(initcount);
|
||||
/*
|
||||
* Wait for the source CPU to print stuff:
|
||||
*/
|
||||
while (atomic_read(&stop_count) != cpus)
|
||||
cpu_relax();
|
||||
|
||||
atomic_inc(&count_count_stop);
|
||||
while (atomic_read(&count_count_stop) != 2)
|
||||
mb();
|
||||
/*
|
||||
* Reset it for the next sync test:
|
||||
*/
|
||||
atomic_set(&stop_count, 0);
|
||||
|
||||
/*
|
||||
* Check the number of remaining test runs. If not zero, the test
|
||||
* failed and a retry with adjusted counter is possible. If zero the
|
||||
* test was either successful or failed terminally.
|
||||
*/
|
||||
if (!atomic_read(&test_runs)) {
|
||||
/* Arrange for an interrupt in a short while */
|
||||
write_c0_compare(read_c0_count() + COUNTON);
|
||||
return;
|
||||
}
|
||||
/* Arrange for an interrupt in a short while */
|
||||
write_c0_compare(read_c0_count() + COUNTON);
|
||||
|
||||
local_irq_restore(flags);
|
||||
/*
|
||||
* If the warp value of this CPU is 0, then the other CPU
|
||||
* observed time going backwards so this counter was ahead and
|
||||
* needs to move backwards.
|
||||
*/
|
||||
if (!cur_max_warp)
|
||||
cur_max_warp = -gbl_max_warp;
|
||||
|
||||
count = read_c0_count();
|
||||
count += cur_max_warp;
|
||||
write_c0_count(count);
|
||||
|
||||
pr_debug("Counter compensate: CPU%u observed %d warp\n", cpu, cur_max_warp);
|
||||
|
||||
goto retry;
|
||||
|
||||
}
|
||||
#undef NR_LOOPS
|
||||
|
||||
Reference in New Issue
Block a user