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Merge tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Browse Source 
Pull MIPS updates from Thomas Bogendoerfer:

 - add support for Realtek RTL9302C

 - add support for Mobileye EyeQ6H

 - add support for Mobileye EyeQ OLB system controller

 - improve r4k clocksource

 - add mode for emulating ieee754 NAN2008

 - rework for BMIPS CBR address handling

 - fixes for Loongson 2K1000

 - defconfig updates

 - cleanups and fixes

* tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits)
  MIPS: config: Add ip30_defconfig
  MIPS: config: lemote2f: Regenerate defconfig
  MIPS: config: generic: Add board-litex
  MIPS: config: Enable MSA and virtualization for MIPS64R6
  MIPS: Fix fallback march for SB1
  mips: dts: realtek: Add RTL9302C board
  mips: generic: add fdt fixup for Realtek reference board
  mips: select REALTEK_OTTO_TIMER for Realtek platforms
  dt-bindings: interrupt-controller: realtek,rtl-intc: Add rtl9300-intc
  dt-bindings: mips: realtek: Add rtl930x-soc compatible
  dt-bindings: vendor-prefixes: Add Cameo Communications
  mips: dts: realtek: add device_type property to cpu node
  mips: dts: realtek: use "serial" instead of "uart" in node name
  MIPS: Implement ieee754 NAN2008 emulation mode
  MIPS: lantiq: improve USB initialization
  MIPS: GIC: Generate redirect block accessors
  MIPS: CPS: Add a couple of multi-cluster utility functions
  MIPS: Octeron: remove source file executable bit
  MAINTAINERS: Mobileye: add OLB drivers and dt-bindings
  MIPS: mobileye: eyeq5: add OLB system-controller node
  ...
This commit is contained in:
Linus Torvalds
2024-07-20 09:03:36 -07:00
parent 3c3ff7be97 bb2d63500b
commit d2be38b9a5
81 changed files with 2148 additions and 399 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/mips/include/asm/bmips.h
+1
View File
@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[];
extern char bmips_smp_int_vec[];
extern char bmips_smp_int_vec_end[];
extern void __iomem *bmips_cbr_addr;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
arch/mips/include/asm/fpu.h
+15
View File
@@ -129,6 +129,18 @@ static inline int __own_fpu(void)
if (ret)
return ret;
if (current->thread.fpu.fcr31 & FPU_CSR_NAN2008) {
if (!cpu_has_nan_2008) {
ret = SIGFPE;
goto failed;
}
} else {
if (!cpu_has_nan_legacy) {
ret = SIGFPE;
goto failed;
}
}
KSTK_STATUS(current) |= ST0_CU1;
if (mode == FPU_64BIT || mode == FPU_HYBRID)
KSTK_STATUS(current) |= ST0_FR;
@@ -137,6 +149,9 @@ static inline int __own_fpu(void)
set_thread_flag(TIF_USEDFPU);
return 0;
failed:
__disable_fpu();
return ret;
}
static inline int own_fpu_inatomic(int restore)
arch/mips/include/asm/mach-loongson64/boot_param.h
+2
View File
@@ -42,12 +42,14 @@ enum loongson_cpu_type {
Legacy_1B = 0x5,
Legacy_2G = 0x6,
Legacy_2H = 0x7,
Legacy_2K = 0x8,
Loongson_1A = 0x100,
Loongson_1B = 0x101,
Loongson_2E = 0x200,
Loongson_2F = 0x201,
Loongson_2G = 0x202,
Loongson_2H = 0x203,
Loongson_2K = 0x204,
Loongson_3A = 0x300,
Loongson_3B = 0x301
};
arch/mips/include/asm/mips-cps.h
+39
View File
@@ -8,6 +8,7 @@
#define __MIPS_ASM_MIPS_CPS_H__
#include <linux/bitfield.h>
#include <linux/cpumask.h>
#include <linux/io.h>
#include <linux/types.h>
@@ -228,4 +229,42 @@ static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int co
return FIELD_GET(CM_GCR_Cx_CONFIG_PVPE, cfg + 1);
}
/**
* mips_cps_multicluster_cpus() - Detect whether CPUs are in multiple clusters
*
* Determine whether the system includes CPUs in multiple clusters - ie.
* whether we can treat the system as single or multi-cluster as far as CPUs
* are concerned. Note that this is slightly different to simply checking
* whether multiple clusters are present - it is possible for there to be
* clusters which contain no CPUs, which this function will effectively ignore.
*
* Returns true if CPUs are spread across multiple clusters, else false.
*/
static inline bool mips_cps_multicluster_cpus(void)
{
unsigned int first_cl, last_cl;
/*
* CPUs are numbered sequentially by cluster - ie. CPUs 0..X will be in
* cluster 0, CPUs X+1..Y in cluster 1, CPUs Y+1..Z in cluster 2 etc.
*
* Thus we can detect multiple clusters trivially by checking whether
* the first & last CPUs belong to the same cluster.
*/
first_cl = cpu_cluster(&boot_cpu_data);
last_cl = cpu_cluster(&cpu_data[nr_cpu_ids - 1]);
return first_cl != last_cl;
}
/**
* mips_cps_first_online_in_cluster() - Detect if CPU is first online in cluster
*
* Determine whether the local CPU is the first to be brought online in its
* cluster - that is, whether there are any other online CPUs in the local
* cluster.
*
* Returns true if this CPU is first online, else false.
*/
extern unsigned int mips_cps_first_online_in_cluster(void);
#endif /* __MIPS_ASM_MIPS_CPS_H__ */
arch/mips/include/asm/mips-gic.h
+34 -16
View File
@@ -28,11 +28,13 @@ extern void __iomem *mips_gic_base;
/* For read-only shared registers */
#define GIC_ACCESSOR_RO(sz, off, name) \
CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
/* For read-write shared registers */
#define GIC_ACCESSOR_RW(sz, off, name) \
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
/* For read-only local registers */
#define GIC_VX_ACCESSOR_RO(sz, off, name) \
@@ -45,7 +47,7 @@ extern void __iomem *mips_gic_base;
CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
/* For read-only shared per-interrupt registers */
#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
#define _GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
static inline void __iomem *addr_gic_##name(unsigned int intr) \
{ \
return mips_gic_base + (off) + (intr * (stride)); \
@@ -58,8 +60,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \
}
/* For read-write shared per-interrupt registers */
#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
#define _GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
\
static inline void write_gic_##name(unsigned int intr, \
unsigned int val) \
@@ -68,22 +70,30 @@ static inline void write_gic_##name(unsigned int intr, \
__raw_writel(val, addr_gic_##name(intr)); \
}
#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name)
#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, stride, redir_##name)
/* For read-only local per-interrupt registers */
#define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name) \
GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
stride, vl_##name) \
GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
_GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
stride, vo_##name)
/* For read-write local per-interrupt registers */
#define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name) \
GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off, \
stride, vl_##name) \
GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
_GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off, \
stride, vo_##name)
/* For read-only shared bit-per-interrupt registers */
#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \
#define _GIC_ACCESSOR_RO_INTR_BIT(off, name) \
static inline void __iomem *addr_gic_##name(void) \
{ \
return mips_gic_base + (off); \
@@ -106,8 +116,8 @@ static inline unsigned int read_gic_##name(unsigned int intr) \
}
/* For read-write shared bit-per-interrupt registers */
#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \
GIC_ACCESSOR_RO_INTR_BIT(off, name) \
#define _GIC_ACCESSOR_RW_INTR_BIT(off, name) \
_GIC_ACCESSOR_RO_INTR_BIT(off, name) \
\
static inline void write_gic_##name(unsigned int intr) \
{ \
@@ -146,6 +156,14 @@ static inline void change_gic_##name(unsigned int intr, \
} \
}
#define GIC_ACCESSOR_RO_INTR_BIT(off, name) \
_GIC_ACCESSOR_RO_INTR_BIT(off, name) \
_GIC_ACCESSOR_RO_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name)
#define GIC_ACCESSOR_RW_INTR_BIT(off, name) \
_GIC_ACCESSOR_RW_INTR_BIT(off, name) \
_GIC_ACCESSOR_RW_INTR_BIT(MIPS_GIC_REDIR_OFS + off, redir_##name)
/* For read-only local bit-per-interrupt registers */
#define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name) \
GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
@@ -155,10 +173,10 @@ static inline void change_gic_##name(unsigned int intr, \
/* For read-write local bit-per-interrupt registers */
#define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name) \
GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
vl_##name) \
GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \
vo_##name)
_GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off, \
vl_##name) \
_GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off, \
vo_##name)
/* GIC_SH_CONFIG - Information about the GIC configuration */
GIC_ACCESSOR_RW(32, 0x000, config)
arch/mips/include/asm/pm.h
+11 -11
View File
@@ -17,7 +17,7 @@
/* Save CPU state to stack for suspend to RAM */
.macro SUSPEND_SAVE_REGS
subu sp, PT_SIZE
PTR_SUBU sp, PT_SIZE
/* Call preserved GPRs */
LONG_S $16, PT_R16(sp)
LONG_S $17, PT_R17(sp)
@@ -56,13 +56,13 @@
LONG_L $31, PT_R31(sp)
/* Pop and return */
jr ra
addiu sp, PT_SIZE
PTR_ADDIU sp, PT_SIZE
.set pop
.endm
/* Get address of static suspend state into t1 */
.macro LA_STATIC_SUSPEND
la t1, mips_static_suspend_state
PTR_LA t1, mips_static_suspend_state
.endm
/* Save important CPU state for early restoration to global data */
@@ -72,11 +72,11 @@
* Segment configuration is saved in global data where it can be easily
* reloaded without depending on the segment configuration.
*/
mfc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */
mfc0 k0, CP0_SEGCTL0
LONG_S k0, SSS_SEGCTL0(t1)
mfc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */
mfc0 k0, CP0_SEGCTL1
LONG_S k0, SSS_SEGCTL1(t1)
mfc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */
mfc0 k0, CP0_SEGCTL2
LONG_S k0, SSS_SEGCTL2(t1)
#endif
/* save stack pointer (pointing to GPRs) */
@@ -92,11 +92,11 @@
* segments.
*/
LONG_L k0, SSS_SEGCTL0(t1)
mtc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */
mtc0 k0, CP0_SEGCTL0
LONG_L k0, SSS_SEGCTL1(t1)
mtc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */
mtc0 k0, CP0_SEGCTL1
LONG_L k0, SSS_SEGCTL2(t1)
mtc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */
mtc0 k0, CP0_SEGCTL2
tlbw_use_hazard
#endif
/* restore stack pointer (pointing to GPRs) */
@@ -105,10 +105,10 @@
/* flush caches to make sure context has reached memory */
.macro SUSPEND_CACHE_FLUSH
.extern __wback_cache_all
.extern __flush_cache_all
.set push
.set noreorder
la t1, __wback_cache_all
PTR_LA t1, __flush_cache_all
LONG_L t0, 0(t1)
jalr t0
nop
arch/mips/include/asm/r4k-timer.h
-5
View File
@@ -12,15 +12,10 @@
#ifdef CONFIG_SYNC_R4K
extern void synchronise_count_master(int cpu);
extern void synchronise_count_slave(int cpu);
#else
static inline void synchronise_count_master(int cpu)
{
}
static inline void synchronise_count_slave(int cpu)
{
}
arch/mips/include/asm/sgi/ip22.h
+3
View File
@@ -76,5 +76,8 @@
extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
extern unsigned short ip22_nvram_read(int reg);
extern void ip22_be_interrupt(int irq);
extern void ip22_be_init(void) __init;
extern void indy_8254timer_irq(void);
#endif