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tegra: dfll: forward-port 4.9 dfll

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This commit is contained in:
Thomas Makin
2025-07-14 23:47:52 -05:00
parent 4c2f0248f2
commit d2ad4efdce
9 changed files with 3213 additions and 661 deletions
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2902
drivers/clk/tegra/clk-dfll.c
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File diff suppressed because it is too large Load Diff

40
drivers/clk/tegra/clk-dfll.h
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@@ -13,36 +13,64 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/types.h>
#include <soc/tegra/tegra-dfll.h>
#include "cvb.h"
struct thermal_tv;
/**
* struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
* @dev: struct device * that holds the OPP table for the DFLL
* @max_freq: maximum frequency supported on this SoC
* @cvb: CPU frequency table for this SoC
* @alignment: parameters of the regulator step and offset
* @init_clock_trimmers: callback to initialize clock trimmers
* @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
* @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
* @tune0_low: DFLL tuning register 0 (low voltage range)
* @tune0_high: DFLL tuning register 0 (high voltage range)
* @tune1: DFLL tuning register 1
* @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage
* @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage
* @thermal_floor_table: table mapping a given temperature to a minimum voltage
* @thermal_cap_table: table mapping a given temperature to a maximum voltage
* @thermal_floor_table_size: size of thermal_floor_table
* @thermal_cap_table_size: size of thermal_cap_table
*/
struct tegra_dfll_soc_data {
struct device *dev;
unsigned long max_freq;
const struct cvb_table *cvb;
struct rail_alignment alignment;
unsigned int min_millivolts;
unsigned int tune_high_min_millivolts;
u32 tune0_low;
u32 tune0_high;
u32 tune1_low;
u32 tune1_high;
unsigned int tune_high_margin_millivolts;
void (*init_clock_trimmers)(void);
void (*set_clock_trimmers_high)(void);
void (*set_clock_trimmers_low)(void);
const struct thermal_tv *thermal_floor_table;
const struct thermal_tv *thermal_cap_table;
unsigned int thermal_floor_table_size;
unsigned int thermal_cap_table_size;
};
/*
* These thermal boundaries are not set in thermal zone as trip-points, but
* must be below/above all other actually set DFLL thermal trip-points.
*/
#define DFLL_THERMAL_CAP_NOCAP 0
#define DFLL_THERMAL_FLOOR_NOFLOOR 125000
int tegra_dfll_register(struct platform_device *pdev,
struct tegra_dfll_soc_data *soc);
struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
void tegra_dfll_suspend(struct platform_device *pdev);
void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll);
int tegra_dfll_resume_tuning(struct device *dev);
int tegra_dfll_runtime_suspend(struct device *dev);
int tegra_dfll_runtime_resume(struct device *dev);
int tegra_dfll_suspend(struct device *dev);
int tegra_dfll_resume(struct device *dev);
#endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */

571
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
View File

@@ -17,15 +17,18 @@
#include <linux/regulator/consumer.h>
#include <soc/tegra/fuse.h>
#include <dt-bindings/thermal/tegra210-dfll-trips.h>
#include <dt-bindings/thermal/tegra210b01-trips.h>
#include "clk.h"
#include "clk-dfll.h"
#include "cvb.h"
struct dfll_fcpu_data {
const unsigned long *cpu_max_freq_table;
unsigned int cpu_max_freq_table_size;
const struct cvb_table *cpu_cvb_tables;
unsigned int cpu_cvb_tables_size;
const struct thermal_table *cpu_thermal_table;
};
/* Maximum CPU frequency, indexed by CPU speedo id */
@@ -42,6 +45,9 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = {
.process_id = -1,
.min_millivolts = 900,
.max_millivolts = 1260,
.alignment = {
.step_uv = 10000, /* 10mV */
},
.speedo_scale = 100,
.voltage_scale = 1000,
.entries = {
@@ -97,142 +103,142 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 1007452, -23865, 370 } }, \
{ 306000000UL, { 1052709, -24875, 370 } }, \
{ 408000000UL, { 1099069, -25895, 370 } }, \
{ 510000000UL, { 1146534, -26905, 370 } }, \
{ 612000000UL, { 1195102, -27915, 370 } }, \
{ 714000000UL, { 1244773, -28925, 370 } }, \
{ 816000000UL, { 1295549, -29935, 370 } }, \
{ 918000000UL, { 1347428, -30955, 370 } }, \
{ 1020000000UL, { 1400411, -31965, 370 } }, \
{ 1122000000UL, { 1454497, -32975, 370 } }, \
{ 1224000000UL, { 1509687, -33985, 370 } }, \
{ 1326000000UL, { 1565981, -35005, 370 } }, \
{ 1428000000UL, { 1623379, -36015, 370 } }, \
{ 1530000000UL, { 1681880, -37025, 370 } }, \
{ 1632000000UL, { 1741485, -38035, 370 } }, \
{ 1734000000UL, { 1802194, -39055, 370 } }, \
{ 1836000000UL, { 1864006, -40065, 370 } }, \
{ 1912500000UL, { 1910780, -40815, 370 } }, \
{ 2014500000UL, { 1227000, 0, 0 } }, \
{ 2218500000UL, { 1227000, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {1007452, -23865, 370} }, \
{306000000UL, {1052709, -24875, 370} }, \
{408000000UL, {1099069, -25895, 370} }, \
{510000000UL, {1146534, -26905, 370} }, \
{612000000UL, {1195102, -27915, 370} }, \
{714000000UL, {1244773, -28925, 370} }, \
{816000000UL, {1295549, -29935, 370} }, \
{918000000UL, {1347428, -30955, 370} }, \
{1020000000UL, {1400411, -31965, 370} }, \
{1122000000UL, {1454497, -32975, 370} }, \
{1224000000UL, {1509687, -33985, 370} }, \
{1326000000UL, {1565981, -35005, 370} }, \
{1428000000UL, {1623379, -36015, 370} }, \
{1530000000UL, {1681880, -37025, 370} }, \
{1632000000UL, {1741485, -38035, 370} }, \
{1734000000UL, {1802194, -39055, 370} }, \
{1836000000UL, {1864006, -40065, 370} }, \
{1912500000UL, {1910780, -40815, 370} }, \
{2014500000UL, {1227000, 0, 0} }, \
{2218500000UL, {1227000, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_XA \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 1250024, -39785, 565 } }, \
{ 306000000UL, { 1297556, -41145, 565 } }, \
{ 408000000UL, { 1346718, -42505, 565 } }, \
{ 510000000UL, { 1397511, -43855, 565 } }, \
{ 612000000UL, { 1449933, -45215, 565 } }, \
{ 714000000UL, { 1503986, -46575, 565 } }, \
{ 816000000UL, { 1559669, -47935, 565 } }, \
{ 918000000UL, { 1616982, -49295, 565 } }, \
{ 1020000000UL, { 1675926, -50645, 565 } }, \
{ 1122000000UL, { 1736500, -52005, 565 } }, \
{ 1224000000UL, { 1798704, -53365, 565 } }, \
{ 1326000000UL, { 1862538, -54725, 565 } }, \
{ 1428000000UL, { 1928003, -56085, 565 } }, \
{ 1530000000UL, { 1995097, -57435, 565 } }, \
{ 1606500000UL, { 2046149, -58445, 565 } }, \
{ 1632000000UL, { 2063822, -58795, 565 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {1250024, -39785, 565} }, \
{306000000UL, {1297556, -41145, 565} }, \
{408000000UL, {1346718, -42505, 565} }, \
{510000000UL, {1397511, -43855, 565} }, \
{612000000UL, {1449933, -45215, 565} }, \
{714000000UL, {1503986, -46575, 565} }, \
{816000000UL, {1559669, -47935, 565} }, \
{918000000UL, {1616982, -49295, 565} }, \
{1020000000UL, {1675926, -50645, 565} }, \
{1122000000UL, {1736500, -52005, 565} }, \
{1224000000UL, {1798704, -53365, 565} }, \
{1326000000UL, {1862538, -54725, 565} }, \
{1428000000UL, {1928003, -56085, 565} }, \
{1530000000UL, {1995097, -57435, 565} }, \
{1606500000UL, {2046149, -58445, 565} }, \
{1632000000UL, {2063822, -58795, 565} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_EUCM1 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 734429, 0, 0 } }, \
{ 306000000UL, { 768191, 0, 0 } }, \
{ 408000000UL, { 801953, 0, 0 } }, \
{ 510000000UL, { 835715, 0, 0 } }, \
{ 612000000UL, { 869477, 0, 0 } }, \
{ 714000000UL, { 903239, 0, 0 } }, \
{ 816000000UL, { 937001, 0, 0 } }, \
{ 918000000UL, { 970763, 0, 0 } }, \
{ 1020000000UL, { 1004525, 0, 0 } }, \
{ 1122000000UL, { 1038287, 0, 0 } }, \
{ 1224000000UL, { 1072049, 0, 0 } }, \
{ 1326000000UL, { 1105811, 0, 0 } }, \
{ 1428000000UL, { 1130000, 0, 0 } }, \
{ 1555500000UL, { 1130000, 0, 0 } }, \
{ 1632000000UL, { 1170000, 0, 0 } }, \
{ 1734000000UL, { 1227500, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {734429, 0, 0} }, \
{306000000UL, {768191, 0, 0} }, \
{408000000UL, {801953, 0, 0} }, \
{510000000UL, {835715, 0, 0} }, \
{612000000UL, {869477, 0, 0} }, \
{714000000UL, {903239, 0, 0} }, \
{816000000UL, {937001, 0, 0} }, \
{918000000UL, {970763, 0, 0} }, \
{1020000000UL, {1004525, 0, 0} }, \
{1122000000UL, {1038287, 0, 0} }, \
{1224000000UL, {1072049, 0, 0} }, \
{1326000000UL, {1105811, 0, 0} }, \
{1428000000UL, {1130000, 0, 0} }, \
{1555500000UL, {1130000, 0, 0} }, \
{1632000000UL, {1170000, 0, 0} }, \
{1734000000UL, {1227500, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_EUCM2 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 742283, 0, 0 } }, \
{ 306000000UL, { 776249, 0, 0 } }, \
{ 408000000UL, { 810215, 0, 0 } }, \
{ 510000000UL, { 844181, 0, 0 } }, \
{ 612000000UL, { 878147, 0, 0 } }, \
{ 714000000UL, { 912113, 0, 0 } }, \
{ 816000000UL, { 946079, 0, 0 } }, \
{ 918000000UL, { 980045, 0, 0 } }, \
{ 1020000000UL, { 1014011, 0, 0 } }, \
{ 1122000000UL, { 1047977, 0, 0 } }, \
{ 1224000000UL, { 1081943, 0, 0 } }, \
{ 1326000000UL, { 1090000, 0, 0 } }, \
{ 1479000000UL, { 1090000, 0, 0 } }, \
{ 1555500000UL, { 1162000, 0, 0 } }, \
{ 1683000000UL, { 1195000, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {742283, 0, 0} }, \
{306000000UL, {776249, 0, 0} }, \
{408000000UL, {810215, 0, 0} }, \
{510000000UL, {844181, 0, 0} }, \
{612000000UL, {878147, 0, 0} }, \
{714000000UL, {912113, 0, 0} }, \
{816000000UL, {946079, 0, 0} }, \
{918000000UL, {980045, 0, 0} }, \
{1020000000UL, {1014011, 0, 0} }, \
{1122000000UL, {1047977, 0, 0} }, \
{1224000000UL, {1081943, 0, 0} }, \
{1326000000UL, {1090000, 0, 0} }, \
{1479000000UL, {1090000, 0, 0} }, \
{1555500000UL, {1162000, 0, 0} }, \
{1683000000UL, {1195000, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 742283, 0, 0 } }, \
{ 306000000UL, { 776249, 0, 0 } }, \
{ 408000000UL, { 810215, 0, 0 } }, \
{ 510000000UL, { 844181, 0, 0 } }, \
{ 612000000UL, { 878147, 0, 0 } }, \
{ 714000000UL, { 912113, 0, 0 } }, \
{ 816000000UL, { 946079, 0, 0 } }, \
{ 918000000UL, { 980045, 0, 0 } }, \
{ 1020000000UL, { 1014011, 0, 0 } }, \
{ 1122000000UL, { 1047977, 0, 0 } }, \
{ 1224000000UL, { 1081943, 0, 0 } }, \
{ 1326000000UL, { 1090000, 0, 0 } }, \
{ 1479000000UL, { 1090000, 0, 0 } }, \
{ 1504500000UL, { 1120000, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {742283, 0, 0} }, \
{306000000UL, {776249, 0, 0} }, \
{408000000UL, {810215, 0, 0} }, \
{510000000UL, {844181, 0, 0} }, \
{612000000UL, {878147, 0, 0} }, \
{714000000UL, {912113, 0, 0} }, \
{816000000UL, {946079, 0, 0} }, \
{918000000UL, {980045, 0, 0} }, \
{1020000000UL, {1014011, 0, 0} }, \
{1122000000UL, {1047977, 0, 0} }, \
{1224000000UL, {1081943, 0, 0} }, \
{1326000000UL, {1090000, 0, 0} }, \
{1479000000UL, {1090000, 0, 0} }, \
{1504500000UL, {1120000, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
#define CPU_CVB_TABLE_ODN \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 721094, 0, 0 } }, \
{ 306000000UL, { 754040, 0, 0 } }, \
{ 408000000UL, { 786986, 0, 0 } }, \
{ 510000000UL, { 819932, 0, 0 } }, \
{ 612000000UL, { 852878, 0, 0 } }, \
{ 714000000UL, { 885824, 0, 0 } }, \
{ 816000000UL, { 918770, 0, 0 } }, \
{ 918000000UL, { 915716, 0, 0 } }, \
{ 1020000000UL, { 984662, 0, 0 } }, \
{ 1122000000UL, { 1017608, 0, 0 } }, \
{ 1224000000UL, { 1050554, 0, 0 } }, \
{ 1326000000UL, { 1083500, 0, 0 } }, \
{ 1428000000UL, { 1116446, 0, 0 } }, \
{ 1581000000UL, { 1130000, 0, 0 } }, \
{ 1683000000UL, { 1168000, 0, 0 } }, \
{ 1785000000UL, { 1227500, 0, 0 } }, \
{ 0UL, { 0, 0, 0 } }, \
{204000000UL, {721094, 0, 0} }, \
{306000000UL, {754040, 0, 0} }, \
{408000000UL, {786986, 0, 0} }, \
{510000000UL, {819932, 0, 0} }, \
{612000000UL, {852878, 0, 0} }, \
{714000000UL, {885824, 0, 0} }, \
{816000000UL, {918770, 0, 0} }, \
{918000000UL, {915716, 0, 0} }, \
{1020000000UL, {984662, 0, 0} }, \
{1122000000UL, {1017608, 0, 0} }, \
{1224000000UL, {1050554, 0, 0} }, \
{1326000000UL, {1083500, 0, 0} }, \
{1428000000UL, {1116446, 0, 0} }, \
{1581000000UL, {1130000, 0, 0} }, \
{1683000000UL, {1168000, 0, 0} }, \
{1785000000UL, {1227500, 0, 0} }, \
{0, { 0, 0, 0} }, \
}
static struct cvb_table tegra210_cpu_cvb_tables[] = {
struct cvb_table tegra210_cpu_cvb_tables[] = {
{
.speedo_id = 10,
.process_id = 0,
@@ -505,94 +511,116 @@ static const unsigned long tegra210b01_cpu_max_freq_table[] = {
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0UL, { 0, 0, 0 } }, \
}
/* f c0, c1, c2 */ \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0, { } }, \
}, \
.vmin_coefficients = { 600000, 0, 0 }, \
.cpu_dfll_data = { \
.tune0_low = 0x0000FFA0, \
.tune0_high = 0x0000FFFF, \
.tune1_low = 0x21107FF, \
.tune_high_min_millivolts = 850, \
.tune_high_margin_millivolts = 38, \
.dvco_calibration_max = ULONG_MAX, \
}, \
.cvb_version = "FCPU Table - p4v3-AggressiveSLT"
#define CPUB01_CVB_TABLE_SLT_B0 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0UL, { 0, 0, 0 } }, \
}
/* f c0, c1, c2 */ \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0, { } }, \
}, \
.vmin_coefficients = { 600000, 0, 0 }, \
.cpu_dfll_data = { \
.tune0_low = 0x0000FF90, \
.tune0_high = 0x0000FFFF, \
.tune1_low = 0x21107FF, \
.tune_high_min_millivolts = 850, \
.tune_high_margin_millivolts = 38, \
.dvco_calibration_max = ULONG_MAX, \
}, \
.cvb_version = "FCPU Table - p4v3-AggressiveSLT"
#define CPUB01_CVB_TABLE \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 721589, -12695, 27 } }, \
{ 306000000UL, { 747134, -14195, 27 } }, \
{ 408000000UL, { 776324, -15705, 27 } }, \
{ 510000000UL, { 809160, -17205, 27 } }, \
{ 612000000UL, { 845641, -18715, 27 } }, \
{ 714000000UL, { 885768, -20215, 27 } }, \
{ 816000000UL, { 929540, -21725, 27 } }, \
{ 918000000UL, { 976958, -23225, 27 } }, \
{ 1020000000UL, { 1028021, -24725, 27 } }, \
{ 1122000000UL, { 1082730, -26235, 27 } }, \
{ 1224000000UL, { 1141084, -27735, 27 } }, \
{ 1326000000UL, { 1203084, -29245, 27 } }, \
{ 1428000000UL, { 1268729, -30745, 27 } }, \
{ 1581000000UL, { 1374032, -33005, 27 } }, \
{ 1683000000UL, { 1448791, -34505, 27 } }, \
{ 1785000000UL, { 1527196, -36015, 27 } }, \
{ 1887000000UL, { 1609246, -37515, 27 } }, \
{ 1963500000UL, { 1675751, -38635, 27 } }, \
{ 2014500000UL, { 1716501, -39395, 27 } }, \
{ 0UL, { 0, 0, 0 } }, \
}
/* f c0, c1, c2 */ \
{ 204000000UL, { 721589, -12695, 27 } }, \
{ 306000000UL, { 747134, -14195, 27 } }, \
{ 408000000UL, { 776324, -15705, 27 } }, \
{ 510000000UL, { 809160, -17205, 27 } }, \
{ 612000000UL, { 845641, -18715, 27 } }, \
{ 714000000UL, { 885768, -20215, 27 } }, \
{ 816000000UL, { 929540, -21725, 27 } }, \
{ 918000000UL, { 976958, -23225, 27 } }, \
{ 1020000000UL, { 1028021, -24725, 27 } }, \
{ 1122000000UL, { 1082730, -26235, 27 } }, \
{ 1224000000UL, { 1141084, -27735, 27 } }, \
{ 1326000000UL, { 1203084, -29245, 27 } }, \
{ 1428000000UL, { 1268729, -30745, 27 } }, \
{ 1581000000UL, { 1374032, -33005, 27 } }, \
{ 1683000000UL, { 1448791, -34505, 27 } }, \
{ 1785000000UL, { 1527196, -36015, 27 } }, \
{ 1887000000UL, { 1609246, -37515, 27 } }, \
{ 1963500000UL, { 1675751, -38635, 27 } }, \
{ 2014500000UL, { 1716501, -39395, 27 } }, \
{ 0, { } }, \
}, \
.vmin_coefficients = { 620000, 0, 0 }, \
.cpu_dfll_data = { \
.tune0_low = 0x0000FFCF, \
.tune1_low = 0x012207FF, \
.tune1_high = 0x03FFF7FF, \
.tune_high_min_millivolts = 850, \
.tune_high_margin_millivolts = 38, \
.dvco_calibration_max = ULONG_MAX, \
}, \
.cvb_version = "FCPU Table - p4v3"
static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
{
.speedo_id = 3,
.process_id = -1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0x0000ffcf,
.tune1_low = 0x012207ff,
.tune_high_min_millivolts = 850,
}
},
struct cvb_table tegra210b01_cpu_cvb_tables[] = {
{
.speedo_id = 3,
.process_id = -1,
@@ -604,37 +632,75 @@ static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
.process_id = 1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE_SLT_B1,
.cpu_dfll_data = {
.tune0_low = 0x0000ffa0,
.tune0_high = 0x0000ffff,
.tune1_low = 0x021107ff,
.tune_high_min_millivolts = 850,
}
},
{
.speedo_id = 2,
.process_id = 0,
.max_millivolts = 1120,
CPUB01_CVB_TABLE_SLT_B0,
.cpu_dfll_data = {
.tune0_low = 0x0000ff90,
.tune0_high = 0x0000ffff,
.tune1_low = 0x021107ff,
.tune_high_min_millivolts = 850,
}
},
{
.speedo_id = -1,
.process_id = -1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0x0000ffcf,
.tune1_low = 0x012207ff,
.tune_high_min_millivolts = 850,
}
},
};
static struct thermal_tv tegra210_thermal_floor_table[] = {
{TEGRA210_DFLL_THERMAL_FLOOR_0 / 1000, 950},
{DFLL_THERMAL_FLOOR_NOFLOOR / 1000, 0},
};
static const struct thermal_tv tegra210_thermal_cap_table[] = {
{DFLL_THERMAL_CAP_NOCAP / 1000, INT_MAX},
{TEGRA210_DFLL_THERMAL_CAP_0 / 1000, 1170},
{TEGRA210_DFLL_THERMAL_CAP_1 / 1000, 1132},
};
static const struct thermal_tv tegra210_thermal_cap_ucm2_table[] = {
{DFLL_THERMAL_CAP_NOCAP / 1000, INT_MAX},
{TEGRA210_DFLL_THERMAL_CAP_0 / 1000, 1162},
{TEGRA210_DFLL_THERMAL_CAP_1 / 1000, 1090},
};
static const struct thermal_table tegra210_cpu_thermal_table = {
.thermal_floor_table = tegra210_thermal_floor_table,
.thermal_floor_table_size = ARRAY_SIZE(tegra210_thermal_floor_table),
.coefficients = { {800000, 0, 0}, 0, 0, 0 },
.speedo_scale = 100,
.voltage_scale = 1000,
.temp_scale = 10,
.thermal_cap_table = tegra210_thermal_cap_table,
.thermal_cap_table_size = ARRAY_SIZE(tegra210_thermal_cap_table),
.thermal_cap_ucm2_table = tegra210_thermal_cap_ucm2_table,
.thermal_cap_ucm2_table_size = ARRAY_SIZE(tegra210_thermal_cap_ucm2_table),
};
static struct thermal_tv tegra210b01_thermal_floor_table[] = {
{TEGRA210B01_DFLL_THERMAL_FLOOR_0 / 1000, 800},
{TEGRA210B01_DFLL_THERMAL_FLOOR_1 / 1000, 0},
{DFLL_THERMAL_FLOOR_NOFLOOR / 1000, 0},
};
static const struct thermal_tv tegra210b01_thermal_cap_table[] = {
{DFLL_THERMAL_CAP_NOCAP / 1000, INT_MAX},
{TEGRA210B01_DFLL_THERMAL_CAP_0 / 1000, 1060},
{TEGRA210B01_DFLL_THERMAL_CAP_1 / 1000, 1010},
};
static const struct thermal_table tegra210b01_cpu_thermal_table = {
.thermal_floor_table = tegra210b01_thermal_floor_table,
.thermal_floor_table_size = ARRAY_SIZE(tegra210b01_thermal_floor_table),
.speedo_scale = 100,
.voltage_scale = 1000,
.temp_scale = 10,
.thermal_cap_table = tegra210b01_thermal_cap_table,
.thermal_cap_table_size = ARRAY_SIZE(tegra210b01_thermal_cap_table),
.thermal_cap_ucm2_table = tegra210b01_thermal_cap_table,
.thermal_cap_ucm2_table_size = ARRAY_SIZE(tegra210b01_thermal_cap_table)
};
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
.cpu_max_freq_table = tegra124_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
@@ -647,6 +713,7 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210_cpu_max_freq_table),
.cpu_cvb_tables = tegra210_cpu_cvb_tables,
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
.cpu_thermal_table = &tegra210_cpu_thermal_table
};
static const struct dfll_fcpu_data tegra210b01_dfll_fcpu_data = {
@@ -654,6 +721,7 @@ static const struct dfll_fcpu_data tegra210b01_dfll_fcpu_data = {
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210b01_cpu_max_freq_table),
.cpu_cvb_tables = tegra210b01_cpu_cvb_tables,
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210b01_cpu_cvb_tables),
.cpu_thermal_table = &tegra210b01_cpu_thermal_table
};
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
@@ -661,7 +729,7 @@ static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
.compatible = "nvidia,tegra124-dfll",
.data = &tegra124_dfll_fcpu_data,
},
{
{
.compatible = "nvidia,tegra210-dfll",
.data = &tegra210_dfll_fcpu_data
},
@@ -675,44 +743,66 @@ static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
static void get_alignment_from_dt(struct device *dev,
struct rail_alignment *align)
{
align->step_uv = 0;
align->offset_uv = 0;
if (of_property_read_u32(dev->of_node,
"nvidia,pwm-voltage-step-microvolts",
&align->step_uv))
&align->step_uv))
align->step_uv = 0;
if (of_property_read_u32(dev->of_node,
"nvidia,pwm-min-microvolts",
&align->offset_uv))
"nvidia,pwm-min-microvolts", &align->offset_uv))
align->offset_uv = 0;
}
static int get_alignment_from_regulator(struct device *dev,
struct rail_alignment *align)
{
struct regulator *reg = regulator_get(dev, "vdd-cpu");
int min_uV, max_uV, n_voltages, ret;
struct regulator *reg = devm_regulator_get(dev, "vdd-cpu");
if (IS_ERR(reg))
return PTR_ERR(reg);
align->offset_uv = regulator_list_voltage(reg, 0);
align->step_uv = regulator_get_linear_step(reg);
ret = regulator_get_constraint_voltages(reg, &min_uV, &max_uV);
if (!ret)
align->offset_uv = min_uV;
regulator_put(reg);
align->step_uv = regulator_get_linear_step(reg);
if (!align->step_uv && !ret) {
n_voltages = regulator_count_voltages(reg);
if (n_voltages > 1)
align->step_uv = (max_uV - min_uV) / (n_voltages - 1);
}
devm_regulator_put(reg);
return 0;
}
#define INIT_TUNE_PRAM(p) \
do { \
if (of_property_read_u32(pdev->dev.of_node, \
"nvidia,dfll-override-" #p, &soc->p)) \
soc->p = soc->cvb->cpu_dfll_data.p; \
} while (0)
static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
{
int process_id, speedo_id, speedo_value, err;
struct tegra_dfll_soc_data *soc;
const struct dfll_fcpu_data *fcpu_data;
struct rail_alignment align;
const struct thermal_table *thermal;
unsigned long max_freq;
u32 f;
bool ucm2;
fcpu_data = of_device_get_match_data(&pdev->dev);
if (!fcpu_data)
return -ENODEV;
ucm2 = tegra_sku_info.ucm == TEGRA_UCM2;
process_id = tegra_sku_info.cpu_process_id;
speedo_id = tegra_sku_info.cpu_speedo_id;
speedo_value = tegra_sku_info.cpu_speedo_value;
@@ -722,6 +812,10 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
speedo_id);
return -ENODEV;
}
max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
if (!of_property_read_u32(pdev->dev.of_node, "nvidia,dfll-max-freq-khz",
&f))
max_freq = min(max_freq, f * 1000UL);
soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
if (!soc)
@@ -733,20 +827,33 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
return -ENODEV;
}
if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")) {
get_alignment_from_dt(&pdev->dev, &align);
get_alignment_from_dt(&pdev->dev, &align);
if (of_property_read_bool(pdev->dev.of_node, "nvidia,pwm-to-pmic")
&& (!align.step_uv || !align.offset_uv)) {
dev_info(&pdev->dev, "Missing required align data in DT");
return -EINVAL;
} else {
err = get_alignment_from_regulator(&pdev->dev, &align);
if (err)
return err;
if (!align.step_uv) {
dev_info(&pdev->dev, "no align data in DT, try from vdd-cpu\n");
err = get_alignment_from_regulator(&pdev->dev, &align);
if (err == -EPROBE_DEFER) {
dev_info(&pdev->dev, "defer probe to get vdd-cpu\n");
return -EPROBE_DEFER;
}
}
}
soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id];
if (!align.step_uv) {
dev_err(&pdev->dev, "missing step uv\n");
return -EINVAL;
}
soc->max_freq = max_freq;
soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables,
fcpu_data->cpu_cvb_tables_size,
&align, process_id, speedo_id,
speedo_value, soc->max_freq);
speedo_value, soc->max_freq,
&soc->min_millivolts);
soc->alignment = align;
if (IS_ERR(soc->cvb)) {
@@ -755,6 +862,33 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
return PTR_ERR(soc->cvb);
}
INIT_TUNE_PRAM(tune0_low);
INIT_TUNE_PRAM(tune0_high);
INIT_TUNE_PRAM(tune1_low);
INIT_TUNE_PRAM(tune1_high);
INIT_TUNE_PRAM(tune_high_min_millivolts);
INIT_TUNE_PRAM(tune_high_margin_millivolts);
thermal = fcpu_data->cpu_thermal_table;
err = tegra_cvb_build_thermal_table(thermal, speedo_value,
soc->min_millivolts);
if (err < 0) {
pr_warn("couldn't build thermal floor table\n");
} else {
soc->thermal_floor_table = thermal->thermal_floor_table;
soc->thermal_floor_table_size = thermal->thermal_floor_table_size;
}
if (thermal && thermal->thermal_cap_table && !ucm2) {
soc->thermal_cap_table = thermal->thermal_cap_table;
soc->thermal_cap_table_size = thermal->thermal_cap_table_size;
} else if (thermal && thermal->thermal_cap_ucm2_table && ucm2) {
soc->thermal_cap_table = thermal->thermal_cap_ucm2_table;
soc->thermal_cap_table_size = thermal->thermal_cap_ucm2_table_size;
} else {
pr_warn("couldn't get thermal cap table\n");
}
err = tegra_dfll_register(pdev, soc);
if (err < 0) {
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
@@ -768,13 +902,10 @@ static void tegra124_dfll_fcpu_remove(struct platform_device *pdev)
{
struct tegra_dfll_soc_data *soc;
/*
* Note that exiting early here is dangerous as after this function
* returns *soc is freed.
*/
soc = tegra_dfll_unregister(pdev);
if (IS_ERR(soc))
return;
dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n",
PTR_ERR(soc));
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
}
@@ -782,7 +913,7 @@ static void tegra124_dfll_fcpu_remove(struct platform_device *pdev)
static const struct dev_pm_ops tegra124_dfll_pm_ops = {
SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
tegra_dfll_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume)
SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, tegra_dfll_resume_tuning)
};
static struct platform_driver tegra124_dfll_fcpu_driver = {

125
drivers/clk/tegra/cvb.c
View File

@@ -11,8 +11,8 @@
#include "cvb.h"
/* cvb_mv = ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) */
static inline int get_cvb_voltage(int speedo, int s_scale,
const struct cvb_coefficients *cvb)
int tegra_get_cvb_voltage(int speedo, int s_scale,
const struct cvb_coefficients *cvb)
{
int mv;
@@ -22,8 +22,21 @@ static inline int get_cvb_voltage(int speedo, int s_scale,
return mv;
}
static int round_cvb_voltage(int mv, int v_scale,
const struct rail_alignment *align)
/* cvb_t_mv =
((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale) / v_scale */
int tegra_get_cvb_t_voltage(int speedo, int s_scale, int t, int t_scale,
struct cvb_coefficients *cvb)
{
/* apply speedo & temperature scales: output mv = cvb_t_mv * v_scale */
int mv;
mv = DIV_ROUND_CLOSEST(cvb->c3 * speedo, s_scale) + cvb->c4 +
DIV_ROUND_CLOSEST(cvb->c5 * t, t_scale);
mv = DIV_ROUND_CLOSEST(mv * t, t_scale);
return mv;
}
int tegra_round_cvb_voltage(int mv, int v_scale,
const struct rail_alignment *align)
{
/* combined: apply voltage scale and round to cvb alignment step */
int uv;
@@ -40,7 +53,7 @@ enum {
UP
};
static int round_voltage(int mv, const struct rail_alignment *align, int up)
int tegra_round_voltage(int mv, const struct rail_alignment *align, int up)
{
if (align->step_uv) {
int uv;
@@ -52,14 +65,46 @@ static int round_voltage(int mv, const struct rail_alignment *align, int up)
return mv;
}
/**
* cvb_t_mv =
* ((c2 * speedo / s_scale + c1) * speedo / s_scale + c0) +
* ((c3 * speedo / s_scale + c4 + c5 * T / t_scale) * T / t_scale)
*/
static inline int get_cvb_thermal_floor(int speedo, int temp,
int s_scale, int t_scale,
const struct thermal_coefficients *coef)
{
int cvb_mv, mv;
cvb_mv = tegra_get_cvb_voltage(speedo, s_scale, &coef->cvb_coef);
mv = DIV_ROUND_CLOSEST(coef->c3 * speedo, s_scale) + coef->c4 +
DIV_ROUND_CLOSEST(coef->c5 * temp, t_scale);
mv = DIV_ROUND_CLOSEST(mv * temp, t_scale) + cvb_mv;
return mv;
}
static int build_opp_table(struct device *dev, const struct cvb_table *table,
struct rail_alignment *align,
int speedo_value, unsigned long max_freq)
int speedo_value, unsigned long max_freq, int *vmin)
{
int i, ret, dfll_mv, min_mv, max_mv;
min_mv = round_voltage(table->min_millivolts, align, UP);
max_mv = round_voltage(table->max_millivolts, align, DOWN);
if (!align->step_uv)
align->step_uv = table->alignment.step_uv;
if (!align->step_uv)
return -EINVAL;
if (!align->offset_uv)
align->offset_uv = table->alignment.offset_uv;
min_mv = tegra_round_voltage(table->min_millivolts, align, UP);
max_mv = tegra_round_voltage(table->max_millivolts, align, DOWN);
dfll_mv = tegra_get_cvb_voltage(
speedo_value, table->speedo_scale, &table->vmin_coefficients);
dfll_mv = tegra_round_cvb_voltage(dfll_mv, table->voltage_scale, align);
min_mv = max(min_mv, dfll_mv);
for (i = 0; i < MAX_DVFS_FREQS; i++) {
const struct cvb_table_freq_entry *entry = &table->entries[i];
@@ -67,10 +112,9 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
if (!entry->freq || (entry->freq > max_freq))
break;
dfll_mv = get_cvb_voltage(speedo_value, table->speedo_scale,
&entry->coefficients);
dfll_mv = round_cvb_voltage(dfll_mv, table->voltage_scale,
align);
dfll_mv = tegra_get_cvb_voltage(
speedo_value, table->speedo_scale, &entry->coefficients);
dfll_mv = tegra_round_cvb_voltage(dfll_mv, table->voltage_scale, align);
dfll_mv = clamp(dfll_mv, min_mv, max_mv);
ret = dev_pm_opp_add(dev, entry->freq, dfll_mv * 1000);
@@ -78,32 +122,35 @@ static int build_opp_table(struct device *dev, const struct cvb_table *table,
return ret;
}
if (vmin)
*vmin = min_mv;
return 0;
}
/**
* tegra_cvb_add_opp_table - build OPP table from Tegra CVB tables
* @dev: the struct device * for which the OPP table is built
* @tables: array of CVB tables
* @count: size of the previously mentioned array
* @align: parameters of the regulator step and offset
* @cvb_tables: array of CVB tables
* @sz: size of the previously mentioned array
* @process_id: process id of the HW module
* @speedo_id: speedo id of the HW module
* @speedo_value: speedo value of the HW module
* @max_freq: highest safe clock rate
* @max_rate: highest safe clock rate
* @opp_dev: the struct device * for which the OPP table is built
* @vmin: final minimum voltage returned to the caller
*
* On Tegra, a CVB table encodes the relationship between operating voltage
* and safe maximal frequency for a given module (e.g. GPU or CPU). This
* function calculates the optimal voltage-frequency operating points
* for the given arguments and exports them via the OPP library for the
* given @dev. Returns a pointer to the struct cvb_table that matched
* given @opp_dev. Returns a pointer to the struct cvb_table that matched
* or an ERR_PTR on failure.
*/
const struct cvb_table *
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
size_t count, struct rail_alignment *align,
int process_id, int speedo_id, int speedo_value,
unsigned long max_freq)
unsigned long max_freq, int *vmin)
{
size_t i;
int ret;
@@ -118,7 +165,7 @@ tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *tables,
continue;
ret = build_opp_table(dev, table, align, speedo_value,
max_freq);
max_freq, vmin);
return ret ? ERR_PTR(ret) : table;
}
@@ -140,3 +187,41 @@ void tegra_cvb_remove_opp_table(struct device *dev,
dev_pm_opp_remove(dev, entry->freq);
}
}
/**
* tegra_cvb_build_thermal_table - build thermal table from Tegra CVB tables
* @table: the hardware characterization thermal table
* @speedo_value: speedo value of the HW module
* @soc_min_mv: minimum voltage applied across all temperature ranges
*
* The minimum voltage for the IP blocks inside Tegra SoCs might depend on
* the current temperature. This function calculates the voltage-thermal
* relations according to the given coefficients. Note that if the
* coefficients are not defined, the fixed thermal floors in the @table will
* be used. Returns 0 on success or a negative error code on failure.
*/
int tegra_cvb_build_thermal_table(const struct thermal_table *table,
int speedo_value, unsigned int soc_min_mv)
{
int i;
if (!table)
return -EINVAL;
/* The vmin for the lowest trip point is fixed */
for (i = 1; i < table->thermal_floor_table_size; i++) {
unsigned int mv;
mv = get_cvb_thermal_floor(speedo_value,
table->thermal_floor_table[i-1].temp,
table->speedo_scale,
table->temp_scale,
&table->coefficients);
mv = DIV_ROUND_UP(mv, table->voltage_scale);
mv = max(mv, soc_min_mv);
table->thermal_floor_table[i].millivolts = max(mv,
table->thermal_floor_table[i].millivolts);
}
return 0;
}

58
drivers/clk/tegra/cvb.h
View File

@@ -21,6 +21,9 @@ struct cvb_coefficients {
int c0;
int c1;
int c2;
int c3;
int c4;
int c5;
};
struct cvb_table_freq_entry {
@@ -32,7 +35,23 @@ struct cvb_cpu_dfll_data {
u32 tune0_low;
u32 tune0_high;
u32 tune1_low;
u32 tune1_high;
unsigned int tune_high_min_millivolts;
unsigned int tune_high_margin_millivolts;
unsigned long dvco_calibration_max;
};
struct thermal_coefficients {
struct cvb_coefficients cvb_coef;
int c3;
int c4;
int c5;
};
/* Thermal trips and voltages */
struct thermal_tv {
int temp;
unsigned int millivolts;
};
struct cvb_table {
@@ -41,20 +60,57 @@ struct cvb_table {
int min_millivolts;
int max_millivolts;
struct rail_alignment alignment;
int speedo_scale;
int voltage_scale;
struct cvb_table_freq_entry entries[MAX_DVFS_FREQS];
struct cvb_cpu_dfll_data cpu_dfll_data;
struct cvb_coefficients vmin_coefficients;
const char *cvb_version;
};
const struct cvb_table *
tegra_cvb_add_opp_table(struct device *dev, const struct cvb_table *cvb_tables,
size_t count, struct rail_alignment *align,
int process_id, int speedo_id, int speedo_value,
unsigned long max_freq);
unsigned long max_freq, int *vmin);
void tegra_cvb_remove_opp_table(struct device *dev,
const struct cvb_table *table,
unsigned long max_freq);
struct thermal_table {
struct thermal_tv *thermal_floor_table;
unsigned int thermal_floor_table_size;
struct thermal_coefficients coefficients;
unsigned int speedo_scale;
unsigned int voltage_scale;
unsigned int temp_scale;
const struct thermal_tv *thermal_cap_table;
unsigned int thermal_cap_table_size;
const struct thermal_tv *thermal_cap_ucm2_table;
unsigned int thermal_cap_ucm2_table_size;
};
const struct cvb_table *tegra_cvb_build_opp_table(
const struct cvb_table *cvb_tables,
size_t sz,
const struct rail_alignment *align,
int process_id,
int speedo_id,
int speedo_value,
unsigned long max_rate,
struct device *opp_dev);
int tegra_get_cvb_voltage(int speedo, int s_scale,
const struct cvb_coefficients *cvb);
int tegra_round_cvb_voltage(int mv, int v_scale,
const struct rail_alignment *align);
int tegra_round_voltage(int mv, const struct rail_alignment *align, int up);
int tegra_get_cvb_t_voltage(int speedo, int s_scale, int t, int t_scale,
struct cvb_coefficients *cvb);
int tegra_cvb_build_thermal_table(const struct thermal_table *table,
int speedo_value, unsigned int soc_min_mv);
#endif

98
include/dt-bindings/clock/tegra210-car.h
View File

@@ -409,9 +409,105 @@
#define TEGRA210_CLK_DMIC3_SYNC_CLK 392
#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393
#define TEGRA210_CLK_C2BUS 401
#define TEGRA210_CLK_C3BUS 402
#define TEGRA210_CLK_VIC03_CBUS 403
#define TEGRA210_CLK_NVJPG_CBUS 404
#define TEGRA210_CLK_SE_CBUS 405
#define TEGRA210_CLK_TSECB_CBUS 406
#define TEGRA210_CLK_CAP_C2BUS 407
#define TEGRA210_CLK_CAP_VCORE_C2BUS 408
#define TEGRA210_CLK_CAP_THROTTLE_C2BUS 409
#define TEGRA210_CLK_FLOOR_C2BUS 410
#define TEGRA210_CLK_OVERRIDE_C2BUS 411
#define TEGRA210_CLK_EDP_C2BUS 412
#define TEGRA210_CLK_NVENC_CBUS 413
#define TEGRA210_CLK_NVDEC_CBUS 414
#define TEGRA210_CLK_VIC_FLOOR_CBUS 415
#define TEGRA210_CLK_CAP_C3BUS 416
#define TEGRA210_CLK_CAP_VCORE_C3BUS 417
#define TEGRA210_CLK_CAP_THROTTLE_C3BUS 418
#define TEGRA210_CLK_FLOOR_C3BUS 419
#define TEGRA210_CLK_OVERRIDE_C3BUS 420
#define TEGRA210_CLK_VI_CBUS 421
#define TEGRA210_CLK_ISP_CBUS 422
#define TEGRA210_CLK_OVERRIDE_CBUS 423
#define TEGRA210_CLK_CAP_VCORE_CBUS 424
#define TEGRA210_CLK_VIA_VI_CBUS 425
#define TEGRA210_CLK_VIB_VI_CBUS 426
#define TEGRA210_CLK_ISPA_ISP_CBUS 427
#define TEGRA210_CLK_ISPB_ISP_CBUS 428
#define TEGRA210_CLK_SBUS 429
#define TEGRA210_CLK_AVP_SCLK 430
#define TEGRA210_CLK_BSEA_SCLK 431
#define TEGRA210_CLK_USBD_SCLK 432
#define TEGRA210_CLK_USB1_SCLK 433
#define TEGRA210_CLK_USB2_SCLK 434
#define TEGRA210_CLK_USB3_SCLK 435
#define TEGRA210_CLK_WAKE_SCLK 436
#define TEGRA210_CLK_CAMERA_SCLK 437
#define TEGRA210_CLK_MON_AVP 438
#define TEGRA210_CLK_CAP_SCLK 439
#define TEGRA210_CLK_CAP_VCORE_SCLK 440
#define TEGRA210_CLK_CAP_THROTTLE_SCLK 441
#define TEGRA210_CLK_FLOOR_SCLK 442
#define TEGRA210_CLK_OVERRIDE_SCLK 443
#define TEGRA210_CLK_SBC1_SCLK 444
#define TEGRA210_CLK_SBC2_SCLK 445
#define TEGRA210_CLK_SBC3_SCLK 446
#define TEGRA210_CLK_SBC4_SCLK 447
#define TEGRA210_CLK_QSPI_SCLK 448
#define TEGRA210_CLK_BOOT_APB_SCLK 449
#define TEGRA210_CLK_EMC_MASTER 450
#define TEGRA210_CLK_GBUS 487
#define TEGRA210_CLK_GM20B_GBUS 488
#define TEGRA210_CLK_CAP_GBUS 489
#define TEGRA210_CLK_EDP_GBUS 490
#define TEGRA210_CLK_CAP_VGPU_GBUS 491
#define TEGRA210_CLK_CAP_THROTTLE_GBUS 492
#define TEGRA210_CLK_CAP_PROFILE_GBUS 493
#define TEGRA210_CLK_OVERRIDE_GBUS 494
#define TEGRA210_CLK_FLOOR_GBUS 495
#define TEGRA210_CLK_FLOOR_PROFILE_GBUS 496
#define TEGRA210_CLK_HOST1X_MASTER 497
#define TEGRA210_CLK_NV_HOST1X 498
#define TEGRA210_CLK_VI_HOST1X 499
#define TEGRA210_CLK_VII2C_HOST1X 500
#define TEGRA210_CLK_CAP_HOST1X 501
#define TEGRA210_CLK_CAP_VCORE_HOST1X 502
#define TEGRA210_CLK_FLOOR_HOST1X 503
#define TEGRA210_CLK_OVERRIDE_HOST1X 504
#define TEGRA210_CLK_MSELECT_MASTER 505
#define TEGRA210_CLK_CPU_MSELECT 506
#define TEGRA210_CLK_PCIE_MSELECT 507
#define TEGRA210_CLK_CAP_VCORE_MSELECT 508
#define TEGRA210_CLK_OVERRIDE_MSELECT 509
#define TEGRA210_CLK_APE_MASTER 510
#define TEGRA210_CLK_ADMA_APE 511
#define TEGRA210_CLK_ADSP_APE 512
#define TEGRA210_CLK_XBAR_APE 513
#define TEGRA210_CLK_CAP_VCORE_APE 514
#define TEGRA210_CLK_OVERRIDE_APE 515
#define TEGRA210_CLK_ABUS 516
#define TEGRA210_CLK_ADSP_CPU_ABUS 517
#define TEGRA210_CLK_CAP_VCORE_ABUS 518
#define TEGRA210_CLK_OVERRIDE_ABUS 519
#define TEGRA210_CLK_VCM_SCLK 520
#define TEGRA210_CLK_VCM_AHB_SCLK 521
#define TEGRA210_CLK_VCM_APB_SCLK 522
#define TEGRA210_CLK_AHB_SCLK 523
#define TEGRA210_CLK_APB_SCLK 524
#define TEGRA210_CLK_SDMMC4_AHB_SCLK 525
/* 526 */
#define TEGRA210_CLK_CBUS 527
#define TEGRA210_CLK_VI_V4L2_CBUS 528
#define TEGRA210_CLK_VI_BYPASS_CBUS 529
#define TEGRA210_CLK_BWMGR_EMC 530
#define TEGRA210_CLK_UTMIPLL_60M 531
#define TEGRA210_CLK_PLL_P_UPHY_OUT 532
#define TEGRA210_CLK_WIFI_SCLK 533
#define TEGRA210_CLK_CLK_MAX 533
#define TEGRA210_CLK_CLK_MAX 534
#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */

16
include/dt-bindings/thermal/tegra210-dfll-trips.h Normal file
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@@ -0,0 +1,16 @@
/*
* This header defines the trip temperatures for Tegra210
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA210_DFLL_TRIPS_H
#define _DT_BINDINGS_THERMAL_TEGRA210_DFLL_TRIPS_H
#define TEGRA210_DFLL_THERMAL_FLOOR_0 15000
#define TEGRA210_DFLL_THERMAL_FLOOR_1 30000
#define TEGRA210_DFLL_THERMAL_FLOOR_2 50000
#define TEGRA210_DFLL_THERMAL_FLOOR_3 70000
#define TEGRA210_DFLL_THERMAL_FLOOR_4 120000
#define TEGRA210_DFLL_THERMAL_CAP_0 66000
#define TEGRA210_DFLL_THERMAL_CAP_1 86000
#endif /* _DT_BINDINGS_THERMAL_TEGRA210_DFLL_TRIPS_H */

28
include/dt-bindings/thermal/tegra210b01-trips.h Normal file
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@@ -0,0 +1,28 @@
/*
* This header defines the trip temperatures for Tegra210b01
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA210B01_TRIPS_H
#define _DT_BINDINGS_THERMAL_TEGRA210B01_TRIPS_H
/* DFLL trips, in millicelsius */
#define TEGRA210B01_DFLL_THERMAL_FLOOR_0 20000
#define TEGRA210B01_DFLL_THERMAL_FLOOR_1 70000
#define TEGRA210B01_DFLL_THERMAL_CAP_0 64000
#define TEGRA210B01_DFLL_THERMAL_CAP_1 84000
/* GPU DVFS thermal trips, in millicelsius */
#define TEGRA210B01_GPU_DVFS_THERMAL_MIN -25000
#define TEGRA210B01_GPU_DVFS_THERMAL_TRIP_1 20000
#define TEGRA210B01_GPU_DVFS_THERMAL_TRIP_2 30000
#define TEGRA210B01_GPU_DVFS_THERMAL_TRIP_3 50000
#define TEGRA210B01_GPU_DVFS_THERMAL_TRIP_4 70000
#define TEGRA210B01_GPU_DVFS_THERMAL_TRIP_5 90000
#define TEGRA210B01_GPU_DVFS_THERMAL_CAP_1 83000
/* SoC DVFS thermal trips, in millicelsius */
#define TEGRA210B01_SOC_THERMAL_FLOOR_0 20000
#define TEGRA210B01_SOC_THERMAL_CAP_0 84000
#endif /* _DT_BINDINGS_THERMAL_TEGRA210B01_TRIPS_H */

36
include/soc/tegra/tegra-dfll.h Normal file
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@@ -0,0 +1,36 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved
*/
#ifndef _TEGRA_DFLL_H_
#define _TEGRA_DFLL_H_
#include <linux/kernel.h>
#include <linux/platform_device.h>
enum tegra_dfll_thermal_type {
TEGRA_DFLL_THERMAL_FLOOR = 0,
TEGRA_DFLL_THERMAL_CAP,
};
struct tegra_dfll;
extern struct tegra_dfll *tegra_dfll_get_by_phandle(struct device_node *np,
const char *prop);
extern int tegra_dfll_update_thermal_index(struct tegra_dfll *td,
enum tegra_dfll_thermal_type type,
unsigned long new_index);
extern int tegra_dfll_get_thermal_index(struct tegra_dfll *td,
enum tegra_dfll_thermal_type type);
extern int tegra_dfll_count_thermal_states(struct tegra_dfll *td,
enum tegra_dfll_thermal_type type);
int tegra_dfll_set_external_floor_mv(int external_floor_mv);
u32 tegra_dfll_get_thermal_floor_mv(void);
u32 tegra_dfll_get_peak_thermal_floor_mv(void);
u32 tegra_dfll_get_thermal_cap_mv(void);
u32 tegra_dfll_get_min_millivolts(void);
struct rail_alignment *tegra_dfll_get_alignment(void);
const char *tegra_dfll_get_cvb_version(void);
#endif