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Merge 09583dfed2 ("Merge tag 'pm-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm") into android-mainline

Browse Source 
Steps on the way to 5.19-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ia47f45f245c5b328148b81c819475152a95e779c
This commit is contained in:
Greg Kroah-Hartman
2022-06-07 18:10:15 +02:00
parent a28c367546 09583dfed2
commit c97046a13c
622 changed files with 21847 additions and 8113 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/ABI/testing/ima_policy
+42 -3
View File
@@ -27,8 +27,9 @@ Description:
[fowner=] [fgroup=]]
lsm: [[subj_user=] [subj_role=] [subj_type=]
[obj_user=] [obj_role=] [obj_type=]]
option: [[appraise_type=]] [template=] [permit_directio]
[appraise_flag=] [appraise_algos=] [keyrings=]
option: [digest_type=] [template=] [permit_directio]
[appraise_type=] [appraise_flag=]
[appraise_algos=] [keyrings=]
base:
func:= [BPRM_CHECK][MMAP_CHECK][CREDS_CHECK][FILE_CHECK][MODULE_CHECK]
[FIRMWARE_CHECK]
@@ -47,10 +48,21 @@ Description:
fgroup:= decimal value
lsm: are LSM specific
option:
appraise_type:= [imasig] [imasig|modsig]
appraise_type:= [imasig] | [imasig|modsig] | [sigv3]
where 'imasig' is the original or the signature
format v2.
where 'modsig' is an appended signature,
where 'sigv3' is the signature format v3. (Currently
limited to fsverity digest based signatures
stored in security.ima xattr. Requires
specifying "digest_type=verity" first.)
appraise_flag:= [check_blacklist]
Currently, blacklist check is only for files signed with appended
signature.
digest_type:= verity
Require fs-verity's file digest instead of the
regular IMA file hash.
keyrings:= list of keyrings
(eg, .builtin_trusted_keys|.ima). Only valid
when action is "measure" and func is KEY_CHECK.
@@ -149,3 +161,30 @@ Description:
security.ima xattr of a file:
appraise func=SETXATTR_CHECK appraise_algos=sha256,sha384,sha512
Example of a 'measure' rule requiring fs-verity's digests
with indication of type of digest in the measurement list.
measure func=FILE_CHECK digest_type=verity \
template=ima-ngv2
Example of 'measure' and 'appraise' rules requiring fs-verity
signatures (format version 3) stored in security.ima xattr.
The 'measure' rule specifies the 'ima-sigv3' template option,
which includes the indication of type of digest and the file
signature in the measurement list.
measure func=BPRM_CHECK digest_type=verity \
template=ima-sigv3
The 'appraise' rule specifies the type and signature format
version (sigv3) required.
appraise func=BPRM_CHECK digest_type=verity \
appraise_type=sigv3
All of these policy rules could, for example, be constrained
either based on a filesystem's UUID (fsuuid) or based on LSM
labels.
Documentation/ABI/testing/sysfs-class-regulator
+81
View File
@@ -370,3 +370,84 @@ Description:
'unknown' means software cannot determine the state, or
the reported state is invalid.
What: /sys/class/regulator/.../under_voltage
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
under_voltage. This indicates if the device reports an
under-voltage fault (1) or not (0).
What: /sys/class/regulator/.../over_current
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
over_current. This indicates if the device reports an
over-current fault (1) or not (0).
What: /sys/class/regulator/.../regulation_out
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
regulation_out. This indicates if the device reports an
out-of-regulation fault (1) or not (0).
What: /sys/class/regulator/.../fail
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
fail. This indicates if the device reports an output failure
(1) or not (0).
What: /sys/class/regulator/.../over_temp
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
over_temp. This indicates if the device reports an
over-temperature fault (1) or not (0).
What: /sys/class/regulator/.../under_voltage_warn
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
under_voltage_warn. This indicates if the device reports an
under-voltage warning (1) or not (0).
What: /sys/class/regulator/.../over_current_warn
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
over_current_warn. This indicates if the device reports an
over-current warning (1) or not (0).
What: /sys/class/regulator/.../over_voltage_warn
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
over_voltage_warn. This indicates if the device reports an
over-voltage warning (1) or not (0).
What: /sys/class/regulator/.../over_temp_warn
Date: April 2022
KernelVersion: 5.18
Contact: Zev Weiss <zev@bewilderbeest.net>
Description:
Some regulator directories will contain a field called
over_temp_warn. This indicates if the device reports an
over-temperature warning (1) or not (0).
Documentation/admin-guide/kernel-parameters.txt
+13 -1
View File
@@ -1922,7 +1922,8 @@
ima_template= [IMA]
Select one of defined IMA measurements template formats.
Formats: { "ima" | "ima-ng" | "ima-sig" }
Formats: { "ima" | "ima-ng" | "ima-ngv2" | "ima-sig" |
"ima-sigv2" }
Default: "ima-ng"
ima_template_fmt=
@@ -6089,11 +6090,22 @@
sources:
- "tpm"
- "tee"
- "caam"
If not specified then it defaults to iterating through
the trust source list starting with TPM and assigns the
first trust source as a backend which is initialized
successfully during iteration.
trusted.rng= [KEYS]
Format: <string>
The RNG used to generate key material for trusted keys.
Can be one of:
- "kernel"
- the same value as trusted.source: "tpm" or "tee"
- "default"
If not specified, "default" is used. In this case,
the RNG's choice is left to each individual trust source.
tsc= Disable clocksource stability checks for TSC.
Format: <string>
[x86] reliable: mark tsc clocksource as reliable, this
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
-212
View File
@@ -1,212 +0,0 @@
* Rockchip rk3399 DMC (Dynamic Memory Controller) device
Required properties:
- compatible: Must be "rockchip,rk3399-dmc".
- devfreq-events: Node to get DDR loading, Refer to
Documentation/devicetree/bindings/devfreq/event/
rockchip-dfi.txt
- clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be
"pclk_ddr_mon";
- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
- rockchip,pmu: Phandle to the syscon managing the "PMU general register
files".
Optional properties:
- interrupts: The CPU interrupt number. The interrupt specifier
format depends on the interrupt controller.
It should be a DCF interrupt. When DDR DVFS finishes
a DCF interrupt is triggered.
- rockchip,pmu: Phandle to the syscon managing the "PMU general register
files".
Following properties relate to DDR timing:
- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
it selects the DDR3 cl-trp-trcd type. It must be
set according to "Speed Bin" in DDR3 datasheet,
DO NOT use a smaller "Speed Bin" than specified
for the DDR3 being used.
- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
power-down idle period in which memories are
placed into power-down mode if bus is idle
for PD_IDLE DFI clock cycles.
- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
self-refresh idle period in which memories are
placed into self-refresh mode if bus is idle
for SR_IDLE * 1024 DFI clock cycles (DFI
clocks freq is half of DRAM clock), default
value is "0".
- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
clock gating idle period. Memories are placed
into self-refresh mode and memory controller
clock arg gating started if bus is idle for
sr_mc_gate_idle*1024 DFI clock cycles.
- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
period in which memories are placed into
self-refresh power down mode if bus is idle
for srpd_lite_idle * 1024 DFI clock cycles.
This parameter is for LPDDR4 only.
- rockchip,standby_idle : Defines the standby idle period in which
memories are placed into self-refresh mode.
The controller, pi, PHY and DRAM clock will
be gated if bus is idle for standby_idle * DFI
clock cycles.
- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
When DDR frequency is less than DRAM_DLL_DISB_FREQ,
DDR3 DLL will be bypassed. Note: if DLL was bypassed,
the odt will also stop working.
- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
MHz (Mega Hz). When DDR frequency is less than
DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
Note: PHY DLL and PHY ODT are independent.
- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
the ODT disable frequency in MHz (Mega Hz).
when the DDR frequency is less then ddr3_odt_dis_freq,
the ODT on the DRAM side and controller side are
both disabled.
- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
the DRAM side driver strength in ohms. Default
value is 40.
- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
is 120.
- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
the phy side CA line (incluing command line,
address line and clock line) driver strength.
Default value is 40.
- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
driver strength. Default value is 40.
- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
the PHY side ODT strength. Default value is 240.
- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
then ODT disable frequency in MHz (Mega Hz).
When DDR frequency is less then ddr3_odt_dis_freq,
the ODT on the DRAM side and controller side are
both disabled.
- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
the DRAM side driver strength in ohms. Default
value is 34.
- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
is 240.
- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side CA line (including command line,
address line and clock line) driver strength.
Default value is 40.
- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
driver strength. Default value is 40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
the phy side odt strength, default value is 240.
- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
defines the ODT disable frequency in
MHz (Mega Hz). When the DDR frequency is less then
ddr3_odt_dis_freq, the ODT on the DRAM side and
controller side are both disabled.
- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
the DRAM side driver strength in ohms. Default
value is 60.
- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on DQS/DQ line strength in ohms.
Default value is 40.
- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on CA line strength in ohms.
Default value is 40.
- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side CA line (including command address
line) driver strength. Default value is 40.
- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side clock line and CS line driver
strength. Default value is 80.
- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
driver strength. Default value is 80.
- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
the PHY side ODT strength. Default value is 60.
Example:
dmc_opp_table: dmc_opp_table {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <900000>;
};
};
dmc: dmc {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
upthreshold = <15>;
downdifferential = <10>;
rockchip,ddr3_speed_bin = <21>;
rockchip,pd_idle = <0x40>;
rockchip,sr_idle = <0x2>;
rockchip,sr_mc_gate_idle = <0x3>;
rockchip,srpd_lite_idle = <0x4>;
rockchip,standby_idle = <0x2000>;
rockchip,dram_dll_dis_freq = <300>;
rockchip,phy_dll_dis_freq = <125>;
rockchip,auto_pd_dis_freq = <666>;
rockchip,ddr3_odt_dis_freq = <333>;
rockchip,ddr3_drv = <40>;
rockchip,ddr3_odt = <120>;
rockchip,phy_ddr3_ca_drv = <40>;
rockchip,phy_ddr3_dq_drv = <40>;
rockchip,phy_ddr3_odt = <240>;
rockchip,lpddr3_odt_dis_freq = <333>;
rockchip,lpddr3_drv = <34>;
rockchip,lpddr3_odt = <240>;
rockchip,phy_lpddr3_ca_drv = <40>;
rockchip,phy_lpddr3_dq_drv = <40>;
rockchip,phy_lpddr3_odt = <240>;
rockchip,lpddr4_odt_dis_freq = <333>;
rockchip,lpddr4_drv = <60>;
rockchip,lpddr4_dq_odt = <40>;
rockchip,lpddr4_ca_odt = <40>;
rockchip,phy_lpddr4_ca_drv = <40>;
rockchip,phy_lpddr4_ck_cs_drv = <80>;
rockchip,phy_lpddr4_dq_drv = <80>;
rockchip,phy_lpddr4_odt = <60>;
};
Documentation/devicetree/bindings/hwmon/adt7475.yaml
+22
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@@ -61,6 +61,26 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
"adi,pin(5|10)-function":
description: |
Configures the function for pin 5 on the adi,adt7473 and adi,adt7475. Or
pin 10 on the adi,adt7476 and adi,adt7490.
$ref: /schemas/types.yaml#/definitions/string
enum:
- pwm2
- smbalert#
"adi,pin(9|14)-function":
description: |
Configures the function for pin 9 on the adi,adt7473 and adi,adt7475. Or
pin 14 on the adi,adt7476 and adi,adt7490
$ref: /schemas/types.yaml#/definitions/string
enum:
- tach4
- therm#
- smbalert#
- gpio
required:
- compatible
- reg
@@ -79,6 +99,8 @@ examples:
adi,bypass-attenuator-in0 = <1>;
adi,bypass-attenuator-in1 = <0>;
adi,pwm-active-state = <1 0 1>;
adi,pin10-function = "smbalert#";
adi,pin14-function = "tach4";
};
};
Documentation/devicetree/bindings/hwmon/lm75.yaml
+1
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@@ -14,6 +14,7 @@ properties:
compatible:
enum:
- adi,adt75
- atmel,at30ts74
- dallas,ds1775
- dallas,ds75
- dallas,ds7505
Documentation/devicetree/bindings/hwmon/microchip,lan966x.yaml
+53
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@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/microchip,lan966x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip LAN966x Hardware Monitor
maintainers:
- Michael Walle <michael@walle.cc>
description: |
Microchip LAN966x temperature monitor and fan controller
properties:
compatible:
enum:
- microchip,lan9668-hwmon
reg:
items:
- description: PVT registers
- description: FAN registers
reg-names:
items:
- const: pvt
- const: fan
clocks:
maxItems: 1
'#thermal-sensor-cells':
const: 0
required:
- compatible
- reg
- reg-names
- clocks
additionalProperties: false
examples:
- |
hwmon: hwmon@e2010180 {
compatible = "microchip,lan9668-hwmon";
reg = <0xe2010180 0xc>,
<0xe20042a8 0xc>;
reg-names = "pvt", "fan";
clocks = <&sys_clk>;
#thermal-sensor-cells = <0>;
};
Documentation/devicetree/bindings/hwmon/national,lm90.yaml
+20
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@@ -34,6 +34,7 @@ properties:
- nxp,sa56004
- onnn,nct1008
- ti,tmp451
- ti,tmp461
- winbond,w83l771
@@ -52,10 +53,29 @@ properties:
vcc-supply:
description: phandle to the regulator that provides the +VCC supply
ti,extended-range-enable:
description: Set to enable extended range temperature.
type: boolean
required:
- compatible
- reg
allOf:
- if:
not:
properties:
compatible:
contains:
enum:
- adi,adt7461
- adi,adt7461a
- ti,tmp451
- ti,tmp461
then:
properties:
ti,extended-range-enable: false
additionalProperties: false
examples:
Documentation/devicetree/bindings/hwmon/nuvoton,nct6775.yaml
+57
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@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/nuvoton,nct6775.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton NCT6775 and compatible Super I/O chips
maintainers:
- Zev Weiss <zev@bewilderbeest.net>
properties:
compatible:
enum:
- nuvoton,nct6106
- nuvoton,nct6116
- nuvoton,nct6775
- nuvoton,nct6776
- nuvoton,nct6779
- nuvoton,nct6791
- nuvoton,nct6792
- nuvoton,nct6793
- nuvoton,nct6795
- nuvoton,nct6796
- nuvoton,nct6797
- nuvoton,nct6798
reg:
maxItems: 1
nuvoton,tsi-channel-mask:
description:
Bitmask indicating which TSI temperature sensor channels are
active. LSB is TSI0, bit 1 is TSI1, etc.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 0xff
default: 0
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
superio@4d {
compatible = "nuvoton,nct6779";
reg = <0x4d>;
nuvoton,tsi-channel-mask = <0x03>;
};
};
Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml
+105
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@@ -0,0 +1,105 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/hwmon/ti,tmp401.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TMP401, TPM411 and TMP43x temperature sensor
maintainers:
- Guenter Roeck <linux@roeck-us.net>
description: |
±1°C Remote and Local temperature sensor
Datasheets:
https://www.ti.com/lit/ds/symlink/tmp401.pdf
https://www.ti.com/lit/ds/symlink/tmp411.pdf
https://www.ti.com/lit/ds/symlink/tmp431.pdf
https://www.ti.com/lit/ds/symlink/tmp435.pdf
properties:
compatible:
enum:
- ti,tmp401
- ti,tmp411
- ti,tmp431
- ti,tmp432
- ti,tmp435
reg:
maxItems: 1
ti,extended-range-enable:
description:
When set, this sensor measures over extended temperature range.
type: boolean
ti,n-factor:
description:
value to be used for converting remote channel measurements to
temperature.
$ref: /schemas/types.yaml#/definitions/int32
items:
minimum: -128
maximum: 127
ti,beta-compensation:
description:
value to select beta correction range.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
allOf:
- if:
properties:
compatible:
contains:
enum:
- ti,tmp401
then:
properties:
ti,n-factor: false
- if:
properties:
compatible:
contains:
enum:
- ti,tmp401
- ti,tmp411
then:
properties:
ti,beta-compensation: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
sensor@4c {
compatible = "ti,tmp401";
reg = <0x4c>;
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
sensor@4c {
compatible = "ti,tmp431";
reg = <0x4c>;
ti,extended-range-enable;
ti,n-factor = <0x3b>;
ti,beta-compensation = <0x7>;
};
};
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+384
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@@ -0,0 +1,384 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# %YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip rk3399 DMC (Dynamic Memory Controller) device
maintainers:
- Brian Norris <briannorris@chromium.org>
properties:
compatible:
enum:
- rockchip,rk3399-dmc
devfreq-events:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Node to get DDR loading. Refer to
Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
clocks:
maxItems: 1
clock-names:
items:
- const: dmc_clk
operating-points-v2: true
center-supply:
description:
DMC regulator supply.
rockchip,pmu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the syscon managing the "PMU general register files".
interrupts:
maxItems: 1
description:
The CPU interrupt number. It should be a DCF interrupt. When DDR DVFS
finishes, a DCF interrupt is triggered.
rockchip,ddr3_speed_bin:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the
DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
being used.
rockchip,pd_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the PD_IDLE value. Defines the power-down idle period in which
memories are placed into power-down mode if bus is idle for PD_IDLE DFI
clock cycles.
See also rockchip,pd-idle-ns.
rockchip,sr_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the SR_IDLE value. Defines the self-refresh idle period in
which memories are placed into self-refresh mode if bus is idle for
SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
See also rockchip,sr-idle-ns.
default: 0
rockchip,sr_mc_gate_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the memory self-refresh and controller clock gating idle period.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
cycles.
See also rockchip,sr-mc-gate-idle-ns.
rockchip,srpd_lite_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
only.
See also rockchip,srpd-lite-idle-ns.
rockchip,standby_idle:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle * DFI clock cycles.
See also rockchip,standby-idle-ns.
rockchip,dram_dll_dis_freq:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
Note: if DLL was bypassed, the odt will also stop working.
rockchip,phy_dll_dis_freq:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
Note: PHY DLL and PHY ODT are independent.
rockchip,auto_pd_dis_freq:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the auto PD disable frequency in MHz.
rockchip,ddr3_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is DDR3, this parameter defines the ODT disable
frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
the ODT on the DRAM side and controller side are both disabled.
rockchip,ddr3_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the DRAM side drive
strength in ohms.
default: 40
rockchip,ddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the DRAM side ODT
strength in ohms.
default: 120
rockchip,phy_ddr3_ca_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the phy side CA line
(incluing command line, address line and clock line) drive strength.
default: 40
rockchip,phy_ddr3_dq_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength.
default: 40
rockchip,phy_ddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is DDR3, this parameter defines the PHY side ODT
strength.
default: 240
rockchip,lpddr3_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is LPDDR3, this parameter defines then ODT disable
frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
ODT on the DRAM side and controller side are both disabled.
rockchip,lpddr3_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
strength in ohms.
default: 34
rockchip,lpddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
strength in ohms.
default: 240
rockchip,phy_lpddr3_ca_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
(including command line, address line and clock line) drive strength.
default: 40
rockchip,phy_lpddr3_dq_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength.
default: 40
rockchip,phy_lpddr3_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When dram type is LPDDR3, this parameter define the phy side odt
strength, default value is 240.
rockchip,lpddr4_odt_dis_freq:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000000 # In case anyone thought this was MHz.
description:
When the DRAM type is LPDDR4, this parameter defines the ODT disable
frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
the ODT on the DRAM side and controller side are both disabled.
rockchip,lpddr4_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
strength in ohms.
default: 60
rockchip,lpddr4_dq_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
DQS/DQ line strength in ohms.
default: 40
rockchip,lpddr4_ca_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
CA line strength in ohms.
default: 40
rockchip,phy_lpddr4_ca_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
(including command address line) drive strength.
default: 40
rockchip,phy_lpddr4_ck_cs_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side clock
line and CS line drive strength.
default: 80
rockchip,phy_lpddr4_dq_drv:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
(including DQS/DQ/DM line) drive strength.
default: 80
rockchip,phy_lpddr4_odt:
deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
strength.
default: 60
rockchip,pd-idle-ns:
description:
Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
period in which memories are placed into power-down mode if bus is idle
for PD_IDLE nanoseconds.
rockchip,sr-idle-ns:
description:
Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
period in which memories are placed into self-refresh mode if bus is idle
for SR_IDLE nanoseconds.
default: 0
rockchip,sr-mc-gate-idle-ns:
description:
Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
rockchip,srpd-lite-idle-ns:
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
rockchip,standby-idle-ns:
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle nanoseconds.
rockchip,pd-idle-dis-freq-hz:
description:
Defines the power-down idle disable frequency in Hz. When the DDR
frequency is greater than pd-idle-dis-freq, power-down idle is disabled.
See also rockchip,pd-idle-ns.
rockchip,sr-idle-dis-freq-hz:
description:
Defines the self-refresh idle disable frequency in Hz. When the DDR
frequency is greater than sr-idle-dis-freq, self-refresh idle is
disabled. See also rockchip,sr-idle-ns.
rockchip,sr-mc-gate-idle-dis-freq-hz:
description:
Defines the self-refresh and memory-controller clock gating disable
frequency in Hz. When the DDR frequency is greater than
sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also
rockchip,sr-mc-gate-idle-ns.
rockchip,srpd-lite-idle-dis-freq-hz:
description:
Defines the self-refresh power down idle disable frequency in Hz. When
the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will
not be placed into self-refresh power down mode when idle. See also
rockchip,srpd-lite-idle-ns.
rockchip,standby-idle-dis-freq-hz:
description:
Defines the standby idle disable frequency in Hz. When the DDR frequency
is greater than standby-idle-dis-freq, standby idle is disabled. See also
rockchip,standby-idle-ns.
required:
- compatible
- devfreq-events
- clocks
- clock-names
- operating-points-v2
- center-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
memory-controller {
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
rockchip,pmu = <&pmu>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DDRC>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
rockchip,pd-idle-ns = <160>;
rockchip,sr-idle-ns = <10240>;
rockchip,sr-mc-gate-idle-ns = <40960>;
rockchip,srpd-lite-idle-ns = <61440>;
rockchip,standby-idle-ns = <81920>;
rockchip,ddr3_odt_dis_freq = <333000000>;
rockchip,lpddr3_odt_dis_freq = <333000000>;
rockchip,lpddr4_odt_dis_freq = <333000000>;
rockchip,pd-idle-dis-freq-hz = <1000000000>;
rockchip,sr-idle-dis-freq-hz = <1000000000>;
rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>;
rockchip,srpd-lite-idle-dis-freq-hz = <0>;
rockchip,standby-idle-dis-freq-hz = <928000000>;
};
Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
+10 -10
View File
@@ -31,7 +31,7 @@ properties:
- const: brcm,sdhci-brcmstb
reg:
minItems: 2
maxItems: 2
reg-names:
items:
@@ -65,15 +65,15 @@ unevaluatedProperties: false
examples:
- |
mmc@84b0000 {
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
sdhci,auto-cmd12;
compatible = "brcm,bcm7216-sdhci",
"brcm,bcm7445-sdhci",
"brcm,sdhci-brcmstb";
reg = <0x84b0000 0x260>, <0x84b0300 0x200>;
reg-names = "host", "cfg";
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
sdhci,auto-cmd12;
interrupts = <0x0 0x26 0x4>;
interrupt-names = "sdio0_0";
clocks = <&scmi_clk 245>;
@@ -81,6 +81,11 @@ examples:
};
mmc@84b1000 {
compatible = "brcm,bcm7216-sdhci",
"brcm,bcm7445-sdhci",
"brcm,sdhci-brcmstb";
reg = <0x84b1000 0x260>, <0x84b1300 0x200>;
reg-names = "host", "cfg";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
@@ -88,11 +93,6 @@ examples:
supports-cqe;
non-removable;
bus-width = <0x8>;
compatible = "brcm,bcm7216-sdhci",
"brcm,bcm7445-sdhci",
"brcm,sdhci-brcmstb";
reg = <0x84b1000 0x260>, <0x84b1300 0x200>;
reg-names = "host", "cfg";
interrupts = <0x0 0x27 0x4>;
interrupt-names = "sdio1_0";
clocks = <&scmi_clk 245>;
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+30 -5
View File
@@ -34,22 +34,47 @@ properties:
- fsl,imx6ull-usdhc
- fsl,imx7d-usdhc
- fsl,imx7ulp-usdhc
- fsl,imx8mm-usdhc
- fsl,imxrt1050-usdhc
- nxp,s32g2-usdhc
- items:
- enum:
- fsl,imx8mm-usdhc
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- fsl,imx8mq-usdhc
- fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
- items:
- enum:
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- fsl,imx93-usdhc
- fsl,imx8ulp-usdhc
- const: fsl,imx8mm-usdhc
- items:
- enum:
- fsl,imx8qm-usdhc
- const: fsl,imx8qxp-usdhc
- items:
- enum:
- fsl,imx8dxl-usdhc
- fsl,imx8mm-usdhc
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
deprecated: true
- items:
- enum:
- fsl,imx8mn-usdhc
- fsl,imx8mp-usdhc
- const: fsl,imx8mm-usdhc
- const: fsl,imx7d-usdhc
deprecated: true
- items:
- enum:
- fsl,imx8qm-usdhc
- const: fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
deprecated: true
reg:
maxItems: 1
Documentation/devicetree/bindings/mmc/marvell,dove-sdhci.yaml
+44
View File
@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/marvell,dove-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell sdhci-dove controller
maintainers:
- Adrian Hunter <adrian.hunter@intel.com>
- Ulf Hansson <ulf.hansson@linaro.org>
allOf:
- $ref: mmc-controller.yaml#
properties:
compatible:
const: marvell,dove-sdhci
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
sdio0: mmc@92000 {
compatible = "marvell,dove-sdhci";
reg = <0x92000 0x100>;
interrupts = <35>;
clocks = <&gate_clk 9>;
};
Documentation/devicetree/bindings/mmc/marvell,orion-sdio.yaml
+44
View File
@@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/marvell,orion-sdio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell orion-sdio controller
maintainers:
- Nicolas Pitre <nico@fluxnic.net>
- Ulf Hansson <ulf.hansson@linaro.org>
allOf:
- $ref: mmc-controller.yaml#
properties:
compatible:
const: marvell,orion-sdio
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
mmc@d00d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd00d4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
};
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
-173
View File
@@ -1,173 +0,0 @@
Marvell Xenon SDHCI Controller device tree bindings
This file documents differences between the core mmc properties
described by mmc.txt and the properties used by the Xenon implementation.
Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
Each SDHC is independent and owns independent resources, such as register sets,
clock and PHY.
Each SDHC should have an independent device tree node.
Required Properties:
- compatible: should be one of the following
- "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
Must provide a second register area and marvell,pad-type.
- "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
- "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
- "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
- clocks:
Array of clocks required for SDHC.
Require at least input clock for Xenon IP core. For Armada AP806 and
CP110, the AXI clock is also mandatory.
- clock-names:
Array of names corresponding to clocks property.
The input clock for Xenon IP core should be named as "core".
The input clock for the AXI bus must be named as "axi".
- reg:
* For "marvell,armada-3700-sdhci", two register areas.
The first one for Xenon IP register. The second one for the Armada 3700 SoC
PHY PAD Voltage Control register.
Please follow the examples with compatible "marvell,armada-3700-sdhci"
in below.
Please also check property marvell,pad-type in below.
* For other compatible strings, one register area for Xenon IP.
Optional Properties:
- marvell,xenon-sdhc-id:
Indicate the corresponding bit index of current SDHC in
SDHC System Operation Control Register Bit[7:0].
Set/clear the corresponding bit to enable/disable current SDHC.
If Xenon IP contains only one SDHC, this property is optional.
- marvell,xenon-phy-type:
Xenon support multiple types of PHYs.
To select eMMC 5.1 PHY, set:
marvell,xenon-phy-type = "emmc 5.1 phy"
eMMC 5.1 PHY is the default choice if this property is not provided.
To select eMMC 5.0 PHY, set:
marvell,xenon-phy-type = "emmc 5.0 phy"
All those types of PHYs can support eMMC, SD and SDIO.
Please note that this property only presents the type of PHY.
It doesn't stand for the entire SDHC type or property.
For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
supports eMMC 5.1.
- marvell,xenon-phy-znr:
Set PHY ZNR value.
Only available for eMMC PHY.
Valid range = [0:0x1F].
ZNR is set as 0xF by default if this property is not provided.
- marvell,xenon-phy-zpr:
Set PHY ZPR value.
Only available for eMMC PHY.
Valid range = [0:0x1F].
ZPR is set as 0xF by default if this property is not provided.
- marvell,xenon-phy-nr-success-tun:
Set the number of required consecutive successful sampling points
used to identify a valid sampling window, in tuning process.
Valid range = [1:7].
Set as 0x4 by default if this property is not provided.
- marvell,xenon-phy-tun-step-divider:
Set the divider for calculating TUN_STEP.
Set as 64 by default if this property is not provided.
- marvell,xenon-phy-slow-mode:
If this property is selected, transfers will bypass PHY.
Only available when bus frequency lower than 55MHz in SDR mode.
Disabled by default. Please only try this property if timing issues
always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
SD Default Speed and HS mode and eMMC legacy speed mode.
- marvell,xenon-tun-count:
Xenon SDHC SoC usually doesn't provide re-tuning counter in
Capabilities Register 3 Bit[11:8].
This property provides the re-tuning counter.
If this property is not set, default re-tuning counter will
be set as 0x9 in driver.
- marvell,pad-type:
Type of Armada 3700 SoC PHY PAD Voltage Controller register.
Only valid when "marvell,armada-3700-sdhci" is selected.
Two types: "sd" and "fixed-1-8v".
If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is
switched to 1.8V when later in higher speed mode.
If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
Please follow the examples with compatible "marvell,armada-3700-sdhci"
in below.
Example:
- For eMMC:
sdhci@aa0000 {
compatible = "marvell,armada-ap806-sdhci";
reg = <0xaa0000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
clocks = <&emmc_clk>,<&axi_clk>;
clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-phy-slow-mode;
marvell,xenon-tun-count = <11>;
non-removable;
no-sd;
no-sdio;
/* Vmmc and Vqmmc are both fixed */
};
- For SD/SDIO:
sdhci@ab0000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0xab0000 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
vqmmc-supply = <&sd_vqmmc_regulator>;
vmmc-supply = <&sd_vmmc_regulator>;
clocks = <&sdclk>, <&axi_clk>;
clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-tun-count = <9>;
};
- For eMMC with compatible "marvell,armada-3700-sdhci":
sdhci@aa0000 {
compatible = "marvell,armada-3700-sdhci";
reg = <0xaa0000 0x1000>,
<phy_addr 0x4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
clocks = <&emmcclk>;
clock-names = "core";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
non-removable;
no-sd;
no-sdio;
/* Vmmc and Vqmmc are both fixed */
marvell,pad-type = "fixed-1-8v";
};
- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
sdhci@ab0000 {
compatible = "marvell,armada-3700-sdhci";
reg = <0xab0000 0x1000>,
<phy_addr 0x4>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
vqmmc-supply = <&sd_regulator>;
/* Vmmc is fixed */
clocks = <&sdclk>;
clock-names = "core";
bus-width = <4>;
marvell,pad-type = "sd";
};
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
+275
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@@ -0,0 +1,275 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Xenon SDHCI Controller
description: |
This file documents differences between the core MMC properties described by
mmc-controller.yaml and the properties used by the Xenon implementation.
Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
Each SDHC is independent and owns independent resources, such as register
sets, clock and PHY.
Each SDHC should have an independent device tree node.
maintainers:
- Ulf Hansson <ulf.hansson@linaro.org>
properties:
compatible:
oneOf:
- enum:
- marvell,armada-cp110-sdhci
- marvell,armada-ap806-sdhci
- items:
- const: marvell,armada-ap807-sdhci
- const: marvell,armada-ap806-sdhci
- items:
- const: marvell,armada-3700-sdhci
- const: marvell,sdhci-xenon
reg:
minItems: 1
maxItems: 2
description: |
For "marvell,armada-3700-sdhci", two register areas. The first one
for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
Voltage Control register. Please follow the examples with compatible
"marvell,armada-3700-sdhci" in below.
Please also check property marvell,pad-type in below.
For other compatible strings, one register area for Xenon IP.
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: axi
marvell,xenon-sdhc-id:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
description: |
Indicate the corresponding bit index of current SDHC in SDHC System
Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
enable/disable current SDHC.
marvell,xenon-phy-type:
$ref: /schemas/types.yaml#/definitions/string
enum:
- "emmc 5.1 phy"
- "emmc 5.0 phy"
description: |
Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
choice if this property is not provided. To select eMMC 5.0 PHY, set:
marvell,xenon-phy-type = "emmc 5.0 phy"
All those types of PHYs can support eMMC, SD and SDIO. Please note that
this property only presents the type of PHY. It doesn't stand for the
entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
that this Xenon SDHC only supports eMMC 5.1.
marvell,xenon-phy-znr:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 0x1f
default: 0xf
description: |
Set PHY ZNR value.
Only available for eMMC PHY.
marvell,xenon-phy-zpr:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 0x1f
default: 0xf
description: |
Set PHY ZPR value.
Only available for eMMC PHY.
marvell,xenon-phy-nr-success-tun:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 7
default: 0x4
description: |
Set the number of required consecutive successful sampling points
used to identify a valid sampling window, in tuning process.
marvell,xenon-phy-tun-step-divider:
$ref: /schemas/types.yaml#/definitions/uint32
default: 64
description: |
Set the divider for calculating TUN_STEP.
marvell,xenon-phy-slow-mode:
type: boolean
description: |
If this property is selected, transfers will bypass PHY.
Only available when bus frequency lower than 55MHz in SDR mode.
Disabled by default. Please only try this property if timing issues
always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
SD Default Speed and HS mode and eMMC legacy speed mode.
marvell,xenon-tun-count:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x9
description: |
Xenon SDHC SoC usually doesn't provide re-tuning counter in
Capabilities Register 3 Bit[11:8].
This property provides the re-tuning counter.
allOf:
- $ref: mmc-controller.yaml#
- if:
properties:
compatible:
contains:
const: marvell,armada-3700-sdhci
then:
properties:
reg:
items:
- description: Xenon IP registers
- description: Armada 3700 SoC PHY PAD Voltage Control register
minItems: 2
marvell,pad-type:
$ref: /schemas/types.yaml#/definitions/string
enum:
- sd
- fixed-1-8v
description: |
Type of Armada 3700 SoC PHY PAD Voltage Controller register.
If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
and is switched to 1.8V when later in higher speed mode.
If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
eMMC.
Please follow the examples with compatible
"marvell,armada-3700-sdhci" in below.
required:
- marvell,pad-type
- if:
properties:
compatible:
contains:
enum:
- marvell,armada-cp110-sdhci
- marvell,armada-ap807-sdhci
- marvell,armada-ap806-sdhci
then:
properties:
clocks:
minItems: 2
clock-names:
items:
- const: core
- const: axi
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
// For eMMC
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
mmc@aa0000 {
compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
reg = <0xaa0000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&emmc_clk 0>, <&axi_clk 0>;
clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-phy-slow-mode;
marvell,xenon-tun-count = <11>;
non-removable;
no-sd;
no-sdio;
/* Vmmc and Vqmmc are both fixed */
};
- |
// For SD/SDIO
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
mmc@ab0000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0xab0000 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
vqmmc-supply = <&sd_vqmmc_regulator>;
vmmc-supply = <&sd_vmmc_regulator>;
clocks = <&sdclk 0>, <&axi_clk 0>;
clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-tun-count = <9>;
};
- |
// For eMMC with compatible "marvell,armada-3700-sdhci":
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
mmc@aa0000 {
compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
reg = <0xaa0000 0x1000>,
<0x17808 0x4>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&emmcclk 0>;
clock-names = "core";
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
non-removable;
no-sd;
no-sdio;
/* Vmmc and Vqmmc are both fixed */
marvell,pad-type = "fixed-1-8v";
};
- |
// For SD/SDIO with compatible "marvell,armada-3700-sdhci":
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
mmc@ab0000 {
compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
reg = <0xab0000 0x1000>,
<0x17808 0x4>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
vqmmc-supply = <&sd_regulator>;
/* Vmmc is fixed */
clocks = <&sdclk 0>;
clock-names = "core";
bus-width = <4>;
marvell,pad-type = "sd";
};
Documentation/devicetree/bindings/mmc/mmc-controller.yaml
+4 -1
View File
@@ -298,7 +298,10 @@ properties:
vqmmc-supply:
description:
Supply for the bus IO line power
Supply for the bus IO line power, such as a level shifter.
If the level shifter is controlled by a GPIO line, this shall
be modeled as a "regulator-fixed" with a GPIO line for
switching the level shifter on/off.
mmc-pwrseq:
$ref: /schemas/types.yaml#/definitions/phandle
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+14 -1
View File
@@ -40,7 +40,10 @@ properties:
- const: mediatek,mt8183-mmc
reg:
maxItems: 1
minItems: 1
items:
- description: base register (required).
- description: top base register (required for MT8183).
clocks:
description:
@@ -168,6 +171,16 @@ required:
- vmmc-supply
- vqmmc-supply
if:
properties:
compatible:
contains:
const: mediatek,mt8183-mmc
then:
properties:
reg:
minItems: 2
unevaluatedProperties: false
examples:
Documentation/devicetree/bindings/mmc/orion-sdio.txt
-16
View File
@@ -1,16 +0,0 @@
* Marvell orion-sdio controller
This file documents differences between the core properties in mmc.txt
and the properties used by the orion-sdio driver.
- compatible: Should be "marvell,orion-sdio"
- clocks: reference to the clock of the SDIO interface
Example:
mvsdio@d00d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd00d4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
};
Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
+7
View File
@@ -186,6 +186,13 @@ properties:
description: Clock Delay Buffer Select
$ref: "/schemas/types.yaml#/definitions/uint32"
ti,fails-without-test-cd:
$ref: /schemas/types.yaml#/definitions/flag
description:
When present, indicates that the CD line is not connected
and the controller is required to be forced into Test mode
to set the TESTCD bit.
required:
- compatible
- reg
Documentation/devicetree/bindings/mmc/sdhci-dove.txt
-14
View File
@@ -1,14 +0,0 @@
* Marvell sdhci-dove controller
This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
- compatible: Should be "marvell,dove-sdhci".
Example:
sdio0: sdio@92000 {
compatible = "marvell,dove-sdhci";
reg = <0x92000 0x100>;
interrupts = <35>;
};
Documentation/devicetree/bindings/mmc/sdhci-msm.txt
-123
View File
@@ -1,123 +0,0 @@
* Qualcomm SDHCI controller (sdhci-msm)
This file documents differences between the core properties in mmc.txt
and the properties used by the sdhci-msm driver.
Required properties:
- compatible: Should contain a SoC-specific string and a IP version string:
version strings:
"qcom,sdhci-msm-v4" for sdcc versions less than 5.0
"qcom,sdhci-msm-v5" for sdcc version 5.0
For SDCC version 5.0.0, MCI registers are removed from SDCC
interface and some registers are moved to HC. New compatible
string is added to support this change - "qcom,sdhci-msm-v5".
full compatible strings with SoC and version:
"qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"
"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
"qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
"qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
"qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
"qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
NOTE that some old device tree files may be floating around that only
have the string "qcom,sdhci-msm-v4" without the SoC compatible string
but doing that should be considered a deprecated practice.
- reg: Base address and length of the register in the following order:
- Host controller register map (required)
- SD Core register map (required for controllers earlier than msm-v5)
- CQE register map (Optional, CQE support is present on SDHC instance meant
for eMMC and version v4.2 and above)
- Inline Crypto Engine register map (optional)
- reg-names: When CQE register map is supplied, below reg-names are required
- "hc" for Host controller register map
- "core" for SD core register map
- "cqhci" for CQE register map
- "ice" for Inline Crypto Engine register map (optional)
- interrupts: Should contain an interrupt-specifiers for the interrupts:
- Host controller interrupt (required)
- pinctrl-names: Should contain only one value - "default".
- pinctrl-0: Should specify pin control groups used for this controller.
- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
- clock-names: Should contain the following:
"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
"core" - SDC MMC clock (MCLK) (required)
"bus" - SDCC bus voter clock (optional)
"xo" - TCXO clock (optional)
"cal" - reference clock for RCLK delay calibration (optional)
"sleep" - sleep clock for RCLK delay calibration (optional)
"ice" - clock for Inline Crypto Engine (optional)
- qcom,ddr-config: Certain chipsets and platforms require particular settings
for the DDR_CONFIG register. Use this field to specify the register
value as per the Hardware Programming Guide.
- qcom,dll-config: Chipset and Platform specific value. Use this field to
specify the DLL_CONFIG register value as per Hardware Programming Guide.
Optional Properties:
* Following bus parameters are required for interconnect bandwidth scaling:
- interconnects: Pairs of phandles and interconnect provider specifier
to denote the edge source and destination ports of
the interconnect path.
- interconnect-names: For sdhc, we have two main paths.
1. Data path : sdhc to ddr
2. Config path : cpu to sdhc
For Data interconnect path the name supposed to be
is "sdhc-ddr" and for config interconnect path it is
"cpu-sdhc".
Please refer to Documentation/devicetree/bindings/
interconnect/ for more details.
Example:
sdhc_1: sdhci@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
interrupts = <0 123 0>;
bus-width = <8>;
non-removable;
vmmc-supply = <&pm8941_l20>;
vqmmc-supply = <&pm8941_s3>;
pinctrl-names = "default";
pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
<&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
};
sdhc_2: sdhci@f98a4900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
interrupts = <0 125 0>;
bus-width = <4>;
cd-gpios = <&msmgpio 62 0x1>;
vmmc-supply = <&pm8941_l21>;
vqmmc-supply = <&pm8941_l13>;
pinctrl-names = "default";
pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
};
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+194
View File
@@ -0,0 +1,194 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm SDHCI controller (sdhci-msm)
maintainers:
- Bhupesh Sharma <bhupesh.sharma@linaro.org>
description:
Secure Digital Host Controller Interface (SDHCI) present on
Qualcomm SOCs supports SD/MMC/SDIO devices.
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,apq8084-sdhci
- qcom,msm8226-sdhci
- qcom,msm8953-sdhci
- qcom,msm8974-sdhci
- qcom,msm8916-sdhci
- qcom,msm8992-sdhci
- qcom,msm8994-sdhci
- qcom,msm8996-sdhci
- qcom,qcs404-sdhci
- qcom,sc7180-sdhci
- qcom,sc7280-sdhci
- qcom,sdm630-sdhci
- qcom,sdm845-sdhci
- qcom,sdx55-sdhci
- qcom,sdx65-sdhci
- qcom,sm6125-sdhci
- qcom,sm6350-sdhci
- qcom,sm8150-sdhci
- qcom,sm8250-sdhci
- enum:
- qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
- qcom,sdhci-msm-v5 # for sdcc version 5.0
- items:
- const: qcom,sdhci-msm-v4 # Deprecated (only for backward compatibility)
# for sdcc versions less than 5.0
reg:
minItems: 1
items:
- description: Host controller register map
- description: SD Core register map
- description: CQE register map
- description: Inline Crypto Engine register map
clocks:
minItems: 3
items:
- description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
- description: SDC MMC clock, MCLK
- description: TCXO clock
- description: clock for Inline Crypto Engine
- description: SDCC bus voter clock
- description: reference clock for RCLK delay calibration
- description: sleep clock for RCLK delay calibration
clock-names:
minItems: 2
items:
- const: iface
- const: core
- const: xo
- const: ice
- const: bus
- const: cal
- const: sleep
interrupts:
maxItems: 2
interrupt-names:
items:
- const: hc_irq
- const: pwr_irq
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
pinctrl-0:
description:
Should specify pin control groups used for this controller.
qcom,ddr-config:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DDR_CONFIG reg.
qcom,dll-config:
$ref: /schemas/types.yaml#/definitions/uint32
description: platform specific settings for DLL_CONFIG reg.
iommus:
minItems: 1
maxItems: 8
description: |
phandle to apps_smmu node with sid mask.
interconnects:
items:
- description: data path, sdhc to ddr
- description: config path, cpu to sdhc
interconnect-names:
items:
- const: sdhc-ddr
- const: cpu-sdhc
power-domains:
description: A phandle to sdhci power domain node
maxItems: 1
patternProperties:
'^opp-table(-[a-z0-9]+)?$':
if:
properties:
compatible:
const: operating-points-v2
then:
patternProperties:
'^opp-?[0-9]+$':
required:
- required-opps
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
additionalProperties: true
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
sdhc_2: sdhci@8804000 {
compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
iommus = <&apps_smmu 0x4a0 0x0>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-19200000 {
opp-hz = /bits/ 64 <19200000>;
required-opps = <&rpmhpd_opp_min_svs>;
};
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+1
View File
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- rockchip,rk3568-dwcmshc
- rockchip,rk3588-dwcmshc
- snps,dwcmshc-sdhci
reg:
Documentation/devicetree/bindings/mtd/aspeed-smc.txt
-51
View File
@@ -1,51 +0,0 @@
* Aspeed Firmware Memory controller
* Aspeed SPI Flash Memory Controller
The Firmware Memory Controller in the Aspeed AST2500 SoC supports
three chip selects, two of which are always of SPI type and the third
can be SPI or NOR type flash. These bindings only describe SPI.
The two SPI flash memory controllers in the AST2500 each support two
chip selects.
Required properties:
- compatible : Should be one of
"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
- reg : the first contains the control register location and length,
the second contains the memory window mapping address and length
- #address-cells : must be 1 corresponding to chip select child binding
- #size-cells : must be 0 corresponding to chip select child binding
Optional properties:
- interrupts : Should contain the interrupt for the dma device if an
FMC
The child nodes are the SPI flash modules which must have a compatible
property as specified in bindings/mtd/jedec,spi-nor.txt
Optionally, the child node can contain properties for SPI mode (may be
ignored):
- spi-max-frequency - max frequency of spi bus
Example:
fmc: fmc@1e620000 {
compatible = "aspeed,ast2500-fmc";
reg = < 0x1e620000 0x94
0x20000000 0x02000000 >;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <19>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
/* spi-max-frequency = <>; */
/* m25p,fast-read; */
#address-cells = <1>;
#size-cells = <1>;
};
};
Documentation/devicetree/bindings/mtd/elm.txt
-16
View File
@@ -1,16 +0,0 @@
Error location module
Required properties:
- compatible: Must be "ti,am3352-elm"
- reg: physical base address and size of the registers map.
- interrupts: Interrupt number for the elm.
Optional properties:
- ti,hwmods: Name of the hwmod associated to the elm
Example:
elm: elm@0 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
interrupts = <4>;
};
Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
-8
View File
@@ -50,10 +50,6 @@ properties:
minItems: 1
maxItems: 2
spi-max-frequency: true
spi-rx-bus-width: true
spi-tx-bus-width: true
m25p,fast-read:
type: boolean
description:
@@ -74,8 +70,6 @@ properties:
be used on such systems, to denote the absence of a reliable reset
mechanism.
label: true
partitions:
type: object
@@ -99,8 +93,6 @@ examples:
#size-cells = <0>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml
+53 -2
View File
@@ -19,7 +19,11 @@ maintainers:
properties:
compatible:
const: fixed-partitions
oneOf:
- const: fixed-partitions
- items:
- const: sercomm,sc-partitions
- const: fixed-partitions
"#address-cells": true
@@ -27,7 +31,24 @@ properties:
patternProperties:
"@[0-9a-f]+$":
$ref: "partition.yaml#"
allOf:
- $ref: "partition.yaml#"
- if:
properties:
compatible:
contains:
const: sercomm,sc-partitions
then:
properties:
sercomm,scpart-id:
description: Partition id in Sercomm partition map. Mtd
parser uses this id to find a record in the partition map
containing offset and size of the current partition. The
values from partition map overrides partition offset and
size defined in reg property of the dts. Frequently these
values are the same, but may differ if device has bad
eraseblocks on a flash.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- "#address-cells"
@@ -52,6 +73,7 @@ examples:
reg = <0x0100000 0x200000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
@@ -64,6 +86,7 @@ examples:
reg = <0x00000000 0x1 0x00000000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
@@ -82,6 +105,7 @@ examples:
reg = <0x2 0x00000000 0x1 0x00000000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
@@ -119,3 +143,30 @@ examples:
};
};
};
- |
partitions {
compatible = "sercomm,sc-partitions", "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
sercomm,scpart-id = <0>;
read-only;
};
partition@100000 {
label = "dynamic partition map";
reg = <0x100000 0x100000>;
sercomm,scpart-id = <1>;
};
partition@200000 {
label = "Factory";
reg = <0x200000 0x100000>;
sercomm,scpart-id = <2>;
read-only;
};
};
Documentation/devicetree/bindings/mtd/renesas-nandc.yaml
+5
View File
@@ -36,11 +36,15 @@ properties:
- const: hclk
- const: eclk
power-domains:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- interrupts
unevaluatedProperties: false
@@ -56,6 +60,7 @@ examples:
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
power-domains = <&sysctrl>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/mtd/ti,elm.yaml
+72
View File
@@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,elm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments Error Location Module (ELM).
maintainers:
- Roger Quadros <rogerq@kernel.org>
description:
ELM module is used together with GPMC and NAND Flash to detect
errors and the location of the error based on BCH algorithms
so they can be corrected if possible.
properties:
compatible:
enum:
- ti,am3352-elm
- ti,am64-elm
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
description: Functional clock.
clock-names:
items:
- const: fck
power-domains:
maxItems: 1
ti,hwmods:
description:
Name of the HWMOD associated with ELM. This is for legacy
platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
required:
- compatible
- reg
- interrupts
allOf:
- if:
properties:
compatible:
contains:
const: ti,am64-elm
then:
required:
- clocks
- clock-names
- power-domains
additionalProperties: false
examples:
- |
elm: ecc@0 {
compatible = "ti,am3352-elm";
reg = <0x0 0x2000>;
interrupts = <4>;
};
Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
+1 -1
View File
@@ -31,7 +31,7 @@ properties:
$ref: "regulator.yaml#"
properties:
regulator-name:
regulator-compatible:
pattern: "^vbuck[1-4]$"
additionalProperties: false
Documentation/devicetree/bindings/regulator/mt6358-regulator.txt
+17 -5
View File
@@ -8,14 +8,14 @@ Documentation/devicetree/bindings/regulator/regulator.txt.
The valid names for regulators are::
BUCK:
buck_vdram1, buck_vcore, buck_vpa, buck_vproc11, buck_vproc12, buck_vgpu,
buck_vs2, buck_vmodem, buck_vs1
buck_vdram1, buck_vcore, buck_vcore_sshub, buck_vpa, buck_vproc11,
buck_vproc12, buck_vgpu, buck_vs2, buck_vmodem, buck_vs1
LDO:
ldo_vdram2, ldo_vsim1, ldo_vibr, ldo_vrf12, ldo_vio18, ldo_vusb, ldo_vcamio,
ldo_vcamd, ldo_vcn18, ldo_vfe28, ldo_vsram_proc11, ldo_vcn28, ldo_vsram_others,
ldo_vsram_gpu, ldo_vxo22, ldo_vefuse, ldo_vaux18, ldo_vmch, ldo_vbif28,
ldo_vsram_proc12, ldo_vcama1, ldo_vemc, ldo_vio28, ldo_va12, ldo_vrf18,
ldo_vcn33_bt, ldo_vcn33_wifi, ldo_vcama2, ldo_vmc, ldo_vldo28, ldo_vaud28,
ldo_vsram_others_sshub, ldo_vsram_gpu, ldo_vxo22, ldo_vefuse, ldo_vaux18,
ldo_vmch, ldo_vbif28, ldo_vsram_proc12, ldo_vcama1, ldo_vemc, ldo_vio28, ldo_va12,
ldo_vrf18, ldo_vcn33_bt, ldo_vcn33_wifi, ldo_vcama2, ldo_vmc, ldo_vldo28, ldo_vaud28,
ldo_vsim2
Example:
@@ -354,5 +354,17 @@ Example:
regulator-max-microvolt = <3100000>;
regulator-enable-ramp-delay = <540>;
};
mt6358_vcore_sshub_reg: buck_vcore_sshub {
regulator-name = "vcore_sshub";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
};
mt6358_vsram_others_sshub_reg: ldo_vsram_others_sshub {
regulator-name = "vsram_others_sshub";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1293750>;
};
};
};
Documentation/devicetree/bindings/regulator/nxp,pca9450-regulator.yaml
+11
View File
@@ -92,6 +92,17 @@ properties:
LDO5CTRL_L or LDO5CTRL_H register. Use this if the SD_VSEL signal is
connected to a host GPIO.
nxp,i2c-lt-enable:
type: boolean
description:
Indicates that the I2C Level Translator is used.
nxp,wdog_b-warm-reset:
type: boolean
description:
When WDOG_B signal is asserted a warm reset will be done instead of cold
reset.
required:
- compatible
- reg
Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml
+246 -16
View File
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. RPMh Regulators
maintainers:
- David Collins <collinsd@codeaurora.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description: |
rpmh-regulator devices support PMIC regulator management via the Voltage
@@ -78,7 +79,7 @@ properties:
RPMh resource name suffix used for the regulators found
on this PMIC.
$ref: /schemas/types.yaml#/definitions/string
enum: [a, b, c, d, e, f]
enum: [a, b, c, d, e, f, h, k]
qcom,always-wait-for-ack:
description: |
@@ -94,35 +95,264 @@ properties:
vdd-rgb-supply:
description: Input supply phandle of rgb.
vin-lvs-1-2-supply:
description: Input supply phandle of one or more regulators.
vdd-bob-supply:
description: BOB regulator parent supply phandle.
bob:
type: object
$ref: "regulator.yaml#"
description: BOB regulator node.
patternProperties:
"^vdd-s([0-9]+)-supply$":
description: Input supply phandle(s) of one or more regulators.
"^vdd-(l[0-9]+[-]){1,5}supply$":
description: Input supply phandle(s) of one or more regulators.
"^(smps|ldo|lvs)[0-9]+$":
type: object
$ref: "regulator.yaml#"
description: smps/ldo regulator nodes(s).
additionalProperties: false
required:
- compatible
- qcom,pmic-id
allOf:
- if:
properties:
compatible:
enum:
- qcom,pm6150-rpmh-regulators
then:
properties:
vdd-l2-l3-supply: true
vdd-l4-l7-l8-supply: true
vdd-l5-l16-l17-l18-l19-supply: true
vdd-l10-l14-l15-supply: true
vdd-l11-l12-l13-supply: true
patternProperties:
"^vdd-l[169]-supply$": true
"^vdd-s[1-5]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm6150l-rpmh-regulators
then:
properties:
vdd-bob-supply:
description: BOB regulator parent supply phandle.
vdd-l1-l8-supply: true
vdd-l2-l3-supply: true
vdd-l4-l5-l6-supply: true
vdd-l7-l11-supply: true
vdd-l9-l10-supply: true
patternProperties:
"^vdd-s[1-8]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm7325-rpmh-regulators
then:
properties:
vdd-l1-l4-l12-l15-supply: true
vdd-l2-l7-supply: true
vdd-l6-l9-l10-supply: true
vdd-l11-l17-l18-l19-supply: true
vdd-l13-supply: true
vdd-l14-l16-supply: true
patternProperties:
"^vdd-l[358]-supply$": true
"^vdd-s[1-8]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8005-rpmh-regulators
then:
patternProperties:
"^vdd-s[1-4]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8009-rpmh-regulators
- qcom,pm8009-1-rpmh-regulators
then:
properties:
vdd-l5-l6-supply: true
patternProperties:
"^vdd-l[1-47]-supply$": true
"^vdd-s[1-2]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8150-rpmh-regulators
- qcom,pmm8155au-rpmh-regulators
then:
properties:
vdd-l1-l8-l11-supply: true
vdd-l2-l10-supply: true
vdd-l3-l4-l5-l18-supply: true
vdd-l6-l9-supply: true
vdd-l7-l12-l14-l15-supply: true
vdd-l13-l16-l17-supply: true
patternProperties:
"^vdd-s([1-9]|10)-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8150l-rpmh-regulators
then:
properties:
vdd-bob-supply:
description: BOB regulator parent supply phandle.
vdd-l1-l8-supply: true
vdd-l2-l3-supply: true
vdd-l4-l5-l6-supply: true
vdd-l7-l11-supply: true
vdd-l9-l10-supply: true
patternProperties:
"^vdd-s[1-8]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8350-rpmh-regulators
then:
properties:
vdd-l1-l4-supply: true
vdd-l2-l7-supply: true
vdd-l3-l5-supply: true
vdd-l6-l9-l10-supply: true
vdd-l8-supply: true
patternProperties:
"^vdd-s([1-9]|1[0-2])-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8350c-rpmh-regulators
then:
properties:
vdd-bob-supply:
description: BOB regulator parent supply phandle.
vdd-l1-l12-supply: true
vdd-l2-l8-supply: true
vdd-l3-l4-l5-l7-l13-supply: true
vdd-l6-l9-l11-supply: true
vdd-l10-supply: true
patternProperties:
"^vdd-s([1-9]|10)-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8450-rpmh-regulators
then:
patternProperties:
"^vdd-l[1-4]-supply$": true
"^vdd-s[1-6]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pm8998-rpmh-regulators
then:
properties:
vdd-l1-l27-supply: true
vdd-l2-l8-l17-supply: true
vdd-l3-l11-supply: true
vdd-l4-l5-supply: true
vdd-l6-supply: true
vdd-l7-l12-l14-l15-supply: true
vdd-l9-supply: true
vdd-l10-l23-l25-supply: true
vdd-l13-l19-l21-supply: true
vdd-l16-l28-supply: true
vdd-l18-l22-supply: true
vdd-l20-l24-supply: true
vdd-l26-supply: true
vin-lvs-1-2-supply: true
patternProperties:
"^vdd-s([1-9]|1[0-3])-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pmg1110-rpmh-regulators
then:
properties:
vdd-s1-supply: true
- if:
properties:
compatible:
enum:
- qcom,pmi8998-rpmh-regulators
then:
properties:
vdd-bob-supply:
description: BOB regulator parent supply phandle.
- if:
properties:
compatible:
enum:
- qcom,pmr735a-rpmh-regulators
then:
properties:
vdd-l1-l2-supply: true
vdd-l3-supply: true
vdd-l4-supply: true
vdd-l5-l6-supply: true
vdd-l7-bob-supply: true
patternProperties:
"^vdd-s[1-3]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pmx55-rpmh-regulators
then:
properties:
vdd-l1-l2-supply: true
vdd-l3-l9-supply: true
vdd-l4-l12-supply: true
vdd-l5-l6-supply: true
vdd-l7-l8-supply: true
vdd-l10-l11-l13-supply: true
patternProperties:
"^vdd-l1[4-6]-supply$": true
"^vdd-s[1-7]-supply$": true
- if:
properties:
compatible:
enum:
- qcom,pmx65-rpmh-regulators
then:
properties:
vdd-l2-l18-supply: true
vdd-l5-l6-l16-supply: true
vdd-l8-l9-supply: true
vdd-l11-l13-supply: true
patternProperties:
"^vdd-l[1347]-supply$": true
"^vdd-l1[0245789]-supply$": true
"^vdd-l2[01]-supply$": true
"^vdd-s[1-8]-supply$": true
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
Documentation/devicetree/bindings/regulator/richtek,rt4801-regulator.yaml
+15 -6
View File
@@ -17,9 +17,6 @@ description: |
Datasheet is available at
https://www.richtek.com/assets/product_file/RT4801H/DS4801H-00.pdf
#The valid names for RT4801 regulator nodes are:
#DSVP, DSVN
properties:
compatible:
enum:
@@ -33,10 +30,13 @@ properties:
The first one is ENP to enable DSVP, and second one is ENM to enable DSVN.
Number of GPIO in the array list could be 1 or 2.
If only one gpio is specified, only one gpio used to control ENP/ENM.
Else both are spefied, DSVP/DSVN could be controlled individually.
Othersie, this property not specified. treat both as always-on regulator.
Else if both are specified, DSVP/DSVN could be controlled individually.
If this property not specified, treat both as always-on regulators.
Property is deprecated. Use enable-gpios in each regulator.
minItems: 1
maxItems: 2
deprecated: true
patternProperties:
"^DSV(P|N)$":
@@ -45,6 +45,14 @@ patternProperties:
description:
Properties for single display bias regulator.
properties:
enable-gpios:
description:
GPIO to use to enable DSVP/DSVN regulator. One GPIO can be configured
for controlling both regulators. If this property not specified for
any regulator, treat both as always-on regulators.
maxItems: 1
required:
- compatible
- reg
@@ -60,19 +68,20 @@ examples:
rt4801@73 {
compatible = "richtek,rt4801";
reg = <0x73>;
enable-gpios = <&gpio26 2 0>, <&gpio26 3 0>;
dsvp: DSVP {
regulator-name = "rt4801,dsvp";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
regulator-boot-on;
enable-gpios = <&gpio26 2 0>;
};
dsvn: DSVN {
regulator-name = "rt4801,dsvn";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <6000000>;
regulator-boot-on;
enable-gpios = <&gpio26 3 0>;
};
};
Documentation/devicetree/bindings/regulator/richtek,rt5759-regulator.yaml
+90
View File
@@ -0,0 +1,90 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/richtek,rt5759-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Richtek RT5759 High Performance DCDC Converter
maintainers:
- ChiYuan Huang <cy_huang@richtek.com>
description: |
The RT5759 is a high-performance, synchronous step-down DC-DC converter that
can deliver up to 9A output current from 3V to 6.5V input supply, The output
voltage can be programmable with I2C controlled 7-Bit VID.
Datasheet is available at
https://www.richtek.com/assets/product_file/RT5759/DS5759-00.pdf
properties:
compatible:
enum:
- richtek,rt5759
- richtek,rt5759a
reg:
maxItems: 1
regulator-allowed-modes:
description: |
buck allowed operating mode
0: auto mode (PSKIP: pulse skipping)
1: force pwm mode
items:
enum: [0, 1]
richtek,watchdog-enable:
description: enable the external watchdog reset pin listening
type: boolean
allOf:
- $ref: regulator.yaml#
- if:
properties:
compatible:
contains:
const: richtek,rt5759
then:
properties:
richtek,watchdog-enable: false
required:
- compatible
- reg
unevaluatedProperties: false
examples:
# example 1 for RT5759
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
regulator@62 {
compatible = "richtek,rt5759";
reg = <0x62>;
regulator-name = "rt5759-buck";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
};
};
# example 2 for RT5759A
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
regulator@62 {
compatible = "richtek,rt5759a";
reg = <0x62>;
regulator-name = "rt5759a-buck";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1725000>;
regulator-boot-on;
richtek,watchdog-enable;
};
};
Documentation/devicetree/bindings/regulator/siliconmitus,sm5703-regulator.yaml
+49
View File
@@ -0,0 +1,49 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/siliconmitus,sm5703-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Mitus SM5703 multi function device regulators
maintainers:
- Markuss Broks <markuss.broks@gmail.com>
description: |
SM5703 regulators node should be a sub node of the SM5703 MFD node. See SM5703 MFD
bindings at Documentation/devicetree/bindings/mfd/siliconmitus,sm5703.yaml
Regulator nodes should be named as USBLDO_<number>, BUCK, VBUS, LDO_<number>.
The definition for each of these nodes is defined using the standard
binding for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
properties:
buck:
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for the BUCK regulator.
vbus:
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for the VBUS regulator.
patternProperties:
"^ldo[1-3]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for single LDO regulator.
"^usbldo[1-2]$":
type: object
$ref: regulator.yaml#
unevaluatedProperties: false
description:
Properties for a single USBLDO regulator.
additionalProperties: false
Documentation/devicetree/bindings/regulator/socionext,uniphier-regulator.yaml
+39 -18
View File
@@ -14,9 +14,6 @@ description: |
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- $ref: "regulator.yaml#"
# USB3 Controller
properties:
@@ -36,27 +33,51 @@ properties:
minItems: 1
maxItems: 2
clock-names:
oneOf:
- items: # for Pro4, Pro5
- const: gio
- const: link
- items: # for others
- const: link
clock-names: true
resets:
minItems: 1
maxItems: 2
reset-names:
oneOf:
- items: # for Pro4, Pro5
- const: gio
- const: link
- items:
- const: link
reset-names: true
additionalProperties: false
allOf:
- $ref: "regulator.yaml#"
- if:
properties:
compatible:
contains:
enum:
- socionext,uniphier-pro4-usb3-regulator
- socionext,uniphier-pro5-usb3-regulator
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: gio
- const: link
resets:
minItems: 2
maxItems: 2
reset-names:
items:
- const: gio
- const: link
else:
properties:
clocks:
maxItems: 1
clock-names:
const: link
resets:
maxItems: 1
reset-names:
const: link
unevaluatedProperties: false
required:
- compatible
Documentation/devicetree/bindings/reserved-memory/phram.yaml
+47
View File
@@ -0,0 +1,47 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/reserved-memory/phram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MTD/block device in RAM
description: |
Specifies that the reserved memory region can be used as an MTD or block
device.
The "phram" node is named after the "MTD in PHysical RAM" driver which
provides an implementation of this functionality in Linux.
maintainers:
- Vincent Whitchurch <vincent.whitchurch@axis.com>
allOf:
- $ref: "reserved-memory.yaml"
- $ref: "/schemas/mtd/mtd.yaml"
properties:
compatible:
const: phram
reg:
description: region of memory that can be used as an MTD/block device
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
phram: flash@12340000 {
compatible = "phram";
label = "rootfs";
reg = <0x12340000 0x00800000>;
};
};
Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+82
View File
@@ -0,0 +1,82 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed SMC controllers bindings
maintainers:
- Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
- Cédric Le Goater <clg@kaod.org>
description: |
This binding describes the Aspeed Static Memory Controllers (FMC and
SPI) of the AST2400, AST2500 and AST2600 SOCs.
allOf:
- $ref: "spi-controller.yaml#"
properties:
compatible:
enum:
- aspeed,ast2600-fmc
- aspeed,ast2600-spi
- aspeed,ast2500-fmc
- aspeed,ast2500-spi
- aspeed,ast2400-fmc
- aspeed,ast2400-spi
reg:
items:
- description: registers
- description: memory mapping
clocks:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
#include <dt-bindings/clock/ast2600-clock.h>
spi@1e620000 {
reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2600-fmc";
clocks = <&syscon ASPEED_CLK_AHB>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
};
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
};
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
};
};
Documentation/devicetree/bindings/spi/ingenic,spi.yaml
+3
View File
@@ -18,7 +18,10 @@ properties:
oneOf:
- enum:
- ingenic,jz4750-spi
- ingenic,jz4775-spi
- ingenic,jz4780-spi
- ingenic,x1000-spi
- ingenic,x2000-spi
- items:
- enum:
- ingenic,jz4760-spi
Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml
+4
View File
@@ -53,16 +53,20 @@ properties:
maxItems: 1
clocks:
minItems: 3
items:
- description: clock used for the parent clock
- description: clock used for the muxes clock
- description: clock used for the clock gate
- description: clock used for the AHB bus, this clock is optional
clock-names:
minItems: 3
items:
- const: parent-clk
- const: sel-clk
- const: spi-clk
- const: hclk
mediatek,pad-select:
$ref: /schemas/types.yaml#/definitions/uint32-array
Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml
+88
View File
@@ -0,0 +1,88 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPI-NAND flash controller for MediaTek ARM SoCs
maintainers:
- Chuanhong Guo <gch981213@gmail.com>
description: |
The Mediatek SPI-NAND flash controller is an extended version of
the Mediatek NAND flash controller. It can perform standard SPI
instructions with one continuous write and one read for up-to 0xa0
bytes. It also supports typical SPI-NAND page cache operations
in single, dual or quad IO mode with pipelined ECC encoding/decoding
using the accompanying ECC engine. There should be only one spi
slave device following generic spi bindings.
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
enum:
- mediatek,mt7622-snand
- mediatek,mt7629-snand
reg:
items:
- description: core registers
interrupts:
items:
- description: NFI interrupt
clocks:
items:
- description: clock used for the controller
- description: clock used for the SPI bus
clock-names:
items:
- const: nfi_clk
- const: pad_clk
nand-ecc-engine:
description: device-tree node of the accompanying ECC engine.
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- nand-ecc-engine
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
snfi: spi@1100d000 {
compatible = "mediatek,mt7622-snand";
reg = <0 0x1100d000 0 0x1000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
clock-names = "nfi_clk", "pad_clk";
nand-ecc-engine = <&bch>;
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
nand-ecc-engine = <&snfi>;
};
};
};
Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
+1
View File
@@ -49,6 +49,7 @@ properties:
maxItems: 2
interconnect-names:
minItems: 1
items:
- const: qspi-config
- const: qspi-memory
Documentation/devicetree/bindings/spi/renesas,rspi.yaml
+2
View File
@@ -21,6 +21,7 @@ properties:
- enum:
- renesas,rspi-r7s72100 # RZ/A1H
- renesas,rspi-r7s9210 # RZ/A2
- renesas,r9a07g043-rspi # RZ/G2UL
- renesas,r9a07g044-rspi # RZ/G2{L,LC}
- renesas,r9a07g054-rspi # RZ/V2L
- const: renesas,rspi-rz
@@ -124,6 +125,7 @@ allOf:
contains:
enum:
- renesas,qspi
- renesas,r9a07g043-rspi
- renesas,r9a07g044-rspi
- renesas,r9a07g054-rspi
then:
Documentation/devicetree/bindings/trivial-devices.yaml
+4
View File
@@ -143,6 +143,10 @@ properties:
- infineon,xdpe12254
# Infineon Multi-phase Digital VR Controller xdpe12284
- infineon,xdpe12284
# Infineon Multi-phase Digital VR Controller xdpe15284
- infineon,xdpe15284
# Infineon Multi-phase Digital VR Controller xdpe152c4
- infineon,xdpe152c4
# Injoinic IP5108 2.0A Power Bank IC with I2C
- injoinic,ip5108
# Injoinic IP5109 2.1A Power Bank IC with I2C
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
View File
@@ -1082,6 +1082,8 @@ patternProperties:
description: Sensirion AG
"^sensortek,.*":
description: Sensortek Technology Corporation
"^sercomm,.*":
description: Sercomm (Suzhou) Corporation
"^sff,.*":
description: Small Form Factor Committee
"^sgd,.*":
Documentation/filesystems/fsverity.rst
+23 -12
View File
@@ -70,12 +70,23 @@ must live on a read-write filesystem because they are independently
updated and potentially user-installed, so dm-verity cannot be used.
The base fs-verity feature is a hashing mechanism only; actually
authenticating the files is up to userspace. However, to meet some
users' needs, fs-verity optionally supports a simple signature
verification mechanism where users can configure the kernel to require
that all fs-verity files be signed by a key loaded into a keyring; see
`Built-in signature verification`_. Support for fs-verity file hashes
in IMA (Integrity Measurement Architecture) policies is also planned.
authenticating the files may be done by:
* Userspace-only
* Builtin signature verification + userspace policy
fs-verity optionally supports a simple signature verification
mechanism where users can configure the kernel to require that
all fs-verity files be signed by a key loaded into a keyring;
see `Built-in signature verification`_.
* Integrity Measurement Architecture (IMA)
IMA supports including fs-verity file digests and signatures in the
IMA measurement list and verifying fs-verity based file signatures
stored as security.ima xattrs, based on policy.
User API
========
@@ -653,12 +664,12 @@ weren't already directly answered in other parts of this document.
hashed and what to do with those hashes, such as log them,
authenticate them, or add them to a measurement list.
IMA is planned to support the fs-verity hashing mechanism as an
alternative to doing full file hashes, for people who want the
performance and security benefits of the Merkle tree based hash.
But it doesn't make sense to force all uses of fs-verity to be
through IMA. As a standalone filesystem feature, fs-verity
already meets many users' needs, and it's testable like other
IMA supports the fs-verity hashing mechanism as an alternative
to full file hashes, for those who want the performance and
security benefits of the Merkle tree based hash. However, it
doesn't make sense to force all uses of fs-verity to be through
IMA. fs-verity already meets many users' needs even as a
standalone filesystem feature, and it's testable like other
filesystem features e.g. with xfstests.
:Q: Isn't fs-verity useless because the attacker can just modify the
Documentation/firmware-guide/acpi/enumeration.rst
+1 -2
View File
@@ -167,8 +167,7 @@ The table below shows an example of its usage::
Name (_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"interrupt-names",
Package (2) {"default", "alert"}},
Package () { "interrupt-names", Package () { "default", "alert" } },
}
...
})
Documentation/hwmon/aquacomputer_d5next.rst
+6 -1
View File
@@ -6,7 +6,9 @@ Kernel driver aquacomputer-d5next
Supported devices:
* Aquacomputer D5 Next watercooling pump
* Aquacomputer Farbwerk RGB controller
* Aquacomputer Farbwerk 360 RGB controller
* Aquacomputer Octo fan controller
Author: Aleksa Savic
@@ -28,7 +30,10 @@ seems to require sending it a complete configuration. That includes addressable
RGB LEDs, for which there is no standard sysfs interface. Thus, that task is
better suited for userspace tools.
The Farbwerk 360 exposes four temperature sensors. Depending on the device,
The Octo exposes four temperature sensors and eight PWM controllable fans, along
with their speed (in RPM), power, voltage and current.
The Farbwerk and Farbwerk 360 expose four temperature sensors. Depending on the device,
not all sysfs and debugfs entries will be available.
Usage notes
Documentation/hwmon/asus_ec_sensors.rst
+15 -10
View File
@@ -4,17 +4,20 @@ Kernel driver asus_ec_sensors
=================================
Supported boards:
* PRIME X570-PRO,
* Pro WS X570-ACE,
* ROG CROSSHAIR VIII DARK HERO,
* PRIME X470-PRO
* PRIME X570-PRO
* Pro WS X570-ACE
* ProArt X570-CREATOR WIFI
* ROG CROSSHAIR VIII DARK HERO
* ROG CROSSHAIR VIII HERO (WI-FI)
* ROG CROSSHAIR VIII FORMULA,
* ROG CROSSHAIR VIII HERO,
* ROG CROSSHAIR VIII IMPACT,
* ROG STRIX B550-E GAMING,
* ROG STRIX B550-I GAMING,
* ROG STRIX X570-E GAMING,
* ROG STRIX X570-F GAMING,
* ROG CROSSHAIR VIII FORMULA
* ROG CROSSHAIR VIII HERO
* ROG CROSSHAIR VIII IMPACT
* ROG STRIX B550-E GAMING
* ROG STRIX B550-I GAMING
* ROG STRIX X570-E GAMING
* ROG STRIX X570-E GAMING WIFI II
* ROG STRIX X570-F GAMING
* ROG STRIX X570-I GAMING
Authors:
@@ -52,3 +55,5 @@ Module Parameters
the path is mostly identical for them). If ASUS changes this path
in a future BIOS update, this parameter can be used to override
the stored in the driver value until it gets updated.
A special string ":GLOBAL_LOCK" can be passed to use the ACPI
global lock instead of a dedicated mutex.
Documentation/hwmon/dell-smm-hwmon.rst
+9
View File
@@ -86,6 +86,13 @@ probe the BIOS on your machine and discover the appropriate codes.
Again, when you find new codes, we'd be happy to have your patches!
``thermal`` interface
---------------------------
The driver also exports the fans as thermal cooling devices with
``type`` set to ``dell-smm-fan[1-3]``. This allows for easy fan control
using one of the thermal governors.
Module parameters
-----------------
@@ -324,6 +331,8 @@ Reading of fan types causes erratic fan behaviour. Studio XPS 8000
Inspiron 580
Inspiron 3505
Fan-related SMM calls take too long (about 500ms). Inspiron 7720
Vostro 3360
Documentation/hwmon/hwmon-kernel-api.rst
+17 -1
View File
@@ -50,6 +50,10 @@ register/unregister functions::
void devm_hwmon_device_unregister(struct device *dev);
char *hwmon_sanitize_name(const char *name);
char *devm_hwmon_sanitize_name(struct device *dev, const char *name);
hwmon_device_register_with_groups registers a hardware monitoring device.
The first parameter of this function is a pointer to the parent device.
The name parameter is a pointer to the hwmon device name. The registration
@@ -72,7 +76,7 @@ hwmon_device_register_with_info is the most comprehensive and preferred means
to register a hardware monitoring device. It creates the standard sysfs
attributes in the hardware monitoring core, letting the driver focus on reading
from and writing to the chip instead of having to bother with sysfs attributes.
The parent device parameter cannot be NULL with non-NULL chip info. Its
The parent device parameter as well as the chip parameter must not be NULL. Its
parameters are described in more detail below.
devm_hwmon_device_register_with_info is similar to
@@ -95,6 +99,18 @@ All supported hwmon device registration functions only accept valid device
names. Device names including invalid characters (whitespace, '*', or '-')
will be rejected. The 'name' parameter is mandatory.
If the driver doesn't use a static device name (for example it uses
dev_name()), and therefore cannot make sure the name only contains valid
characters, hwmon_sanitize_name can be used. This convenience function
will duplicate the string and replace any invalid characters with an
underscore. It will allocate memory for the new string and it is the
responsibility of the caller to release the memory when the device is
removed.
devm_hwmon_sanitize_name is the resource managed version of
hwmon_sanitize_name; the memory will be freed automatically on device
removal.
Using devm_hwmon_device_register_with_info()
--------------------------------------------
Documentation/hwmon/index.rst
+2
View File
@@ -90,6 +90,7 @@ Hardware Monitoring Kernel Drivers
jc42
k10temp
k8temp
lan966x
lineage-pem
lm25066
lm63
@@ -223,6 +224,7 @@ Hardware Monitoring Kernel Drivers
wm8350
xgene-hwmon
xdpe12284
xdpe152c4
zl6100
.. only:: subproject and html
Documentation/hwmon/lan966x.rst
+40
View File
@@ -0,0 +1,40 @@
.. SPDX-License-Identifier: GPL-2.0
Kernel driver lan966x-hwmon
===========================
Supported chips:
* Microchip LAN9668 (sensor in SoC)
Prefix: 'lan9668-hwmon'
Datasheet: https://microchip-ung.github.io/lan9668_reginfo
Authors:
Michael Walle <michael@walle.cc>
Description
-----------
This driver implements support for the Microchip LAN9668 on-chip
temperature sensor as well as its fan controller. It provides one
temperature sensor and one fan controller. The temperature range
of the sensor is specified from -40 to +125 degrees Celsius and
its accuracy is +/- 5 degrees Celsius. The fan controller has a
tacho input and a PWM output with a customizable PWM output
frequency ranging from ~20Hz to ~650kHz.
No alarms are supported by the SoC.
The driver exports temperature values, fan tacho input and PWM
settings via the following sysfs files:
**temp1_input**
**fan1_input**
**pwm1**
**pwm1_freq**
Documentation/hwmon/max16601.rst
+8
View File
@@ -21,6 +21,14 @@ Supported chips:
Datasheet: Not published
* Maxim MAX16602
Prefix: 'max16602'
Addresses scanned: -
Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX16602.pdf
Author: Guenter Roeck <linux@roeck-us.net>
Documentation/hwmon/xdpe152c4.rst
+118
View File
@@ -0,0 +1,118 @@
.. SPDX-License-Identifier: GPL-2.0
Kernel driver xdpe152
=====================
Supported chips:
* Infineon XDPE152C4
Prefix: 'xdpe152c4'
* Infineon XDPE15284
Prefix: 'xdpe15284'
Authors:
Greg Schwendimann <greg.schwendimann@infineon.com>
Description
-----------
This driver implements support for Infineon Digital Multi-phase Controller
XDPE152C4 and XDPE15284 dual loop voltage regulators.
The devices are compliant with:
- Intel VR13, VR13HC and VR14 rev 1.86
converter specification.
- Intel SVID rev 1.93. protocol.
- PMBus rev 1.3.1 interface.
Devices support linear format for reading input and output voltage, input
and output current, input and output power and temperature.
Devices support two pages for telemetry.
The driver provides for current: input, maximum and critical thresholds
and maximum and critical alarms. Low Critical thresholds and Low critical alarm are
supported only for current output.
The driver exports the following attributes for via the sysfs files, where
indexes 1, 2 are for "iin" and 3, 4 for "iout":
**curr[1-4]_crit**
**curr[1-4]_crit_alarm**
**curr[1-4]_input**
**curr[1-4]_label**
**curr[1-4]_max**
**curr[1-4]_max_alarm**
**curr[3-4]_lcrit**
**curr[3-4]_lcrit_alarm**
**curr[3-4]_rated_max**
The driver provides for voltage: input, critical and low critical thresholds
and critical and low critical alarms.
The driver exports the following attributes for via the sysfs files, where
indexes 1, 2 are for "vin" and 3, 4 for "vout":
**in[1-4]_min**
**in[1-4]_crit**
**in[1-4_crit_alarm**
**in[1-4]_input**
**in[1-4]_label**
**in[1-4]_max**
**in[1-4]_max_alarm**
**in[1-4]_min**
**in[1-4]_min_alarm**
**in[3-4]_lcrit**
**in[3-4]_lcrit_alarm**
**in[3-4]_rated_max**
**in[3-4]_rated_min**
The driver provides for power: input and alarms.
The driver exports the following attributes for via the sysfs files, where
indexes 1, 2 are for "pin" and 3, 4 for "pout":
**power[1-2]_alarm**
**power[1-4]_input**
**power[1-4]_label**
**power[1-4]_max**
**power[1-4]_rated_max**
The driver provides for temperature: input, maximum and critical thresholds
and maximum and critical alarms.
The driver exports the following attributes for via the sysfs files:
**temp[1-2]_crit**
**temp[1-2]_crit_alarm**
**temp[1-2]_input**
**temp[1-2]_max**
**temp[1-2]_max_alarm**
Documentation/power/energy-model.rst
+22 -2
View File
@@ -123,6 +123,26 @@ allows a platform to register EM power values which are reflecting total power
(static + dynamic). These power values might be coming directly from
experiments and measurements.
Registration of 'artificial' EM
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
There is an option to provide a custom callback for drivers missing detailed
knowledge about power value for each performance state. The callback
.get_cost() is optional and provides the 'cost' values used by the EAS.
This is useful for platforms that only provide information on relative
efficiency between CPU types, where one could use the information to
create an abstract power model. But even an abstract power model can
sometimes be hard to fit in, given the input power value size restrictions.
The .get_cost() allows to provide the 'cost' values which reflect the
efficiency of the CPUs. This would allow to provide EAS information which
has different relation than what would be forced by the EM internal
formulas calculating 'cost' values. To register an EM for such platform, the
driver must set the flag 'milliwatts' to 0, provide .get_power() callback
and provide .get_cost() callback. The EM framework would handle such platform
properly during registration. A flag EM_PERF_DOMAIN_ARTIFICIAL is set for such
platform. Special care should be taken by other frameworks which are using EM
to test and treat this flag properly.
Registration of 'simple' EM
~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -181,8 +201,8 @@ EM framework::
-> drivers/cpufreq/foo_cpufreq.c
01 static int est_power(unsigned long *mW, unsigned long *KHz,
02 struct device *dev)
01 static int est_power(struct device *dev, unsigned long *mW,
02 unsigned long *KHz)
03 {
04 long freq, power;
05
Documentation/security/IMA-templates.rst
+7 -4
View File
@@ -66,12 +66,13 @@ descriptors by adding their identifier to the format string
calculated with the SHA1 or MD5 hash algorithm;
- 'n': the name of the event (i.e. the file name), with size up to 255 bytes;
- 'd-ng': the digest of the event, calculated with an arbitrary hash
algorithm (field format: [<hash algo>:]digest, where the digest
prefix is shown only if the hash algorithm is not SHA1 or MD5);
algorithm (field format: <hash algo>:digest);
- 'd-ngv2': same as d-ng, but prefixed with the "ima" or "verity" digest type
(field format: <digest type>:<hash algo>:digest);
- 'd-modsig': the digest of the event without the appended modsig;
- 'n-ng': the name of the event, without size limitations;
- 'sig': the file signature, or the EVM portable signature if the file
signature is not found;
- 'sig': the file signature, based on either the file's/fsverity's digest[1],
or the EVM portable signature, if 'security.ima' contains a file hash.
- 'modsig' the appended file signature;
- 'buf': the buffer data that was used to generate the hash without size limitations;
- 'evmsig': the EVM portable signature;
@@ -88,7 +89,9 @@ Below, there is the list of defined template descriptors:
- "ima": its format is ``d|n``;
- "ima-ng" (default): its format is ``d-ng|n-ng``;
- "ima-ngv2": its format is ``d-ngv2|n-ng``;
- "ima-sig": its format is ``d-ng|n-ng|sig``;
- "ima-sigv2": its format is ``d-ngv2|n-ng|sig``;
- "ima-buf": its format is ``d-ng|n-ng|buf``;
- "ima-modsig": its format is ``d-ng|n-ng|sig|d-modsig|modsig``;
- "evm-sig": its format is ``d-ng|n-ng|evmsig|xattrnames|xattrlengths|xattrvalues|iuid|igid|imode``;
Documentation/security/keys/trusted-encrypted.rst
+51 -9
View File
@@ -35,6 +35,13 @@ safe.
Rooted to Hardware Unique Key (HUK) which is generally burnt in on-chip
fuses and is accessible to TEE only.
(3) CAAM (Cryptographic Acceleration and Assurance Module: IP on NXP SoCs)
When High Assurance Boot (HAB) is enabled and the CAAM is in secure
mode, trust is rooted to the OTPMK, a never-disclosed 256-bit key
randomly generated and fused into each SoC at manufacturing time.
Otherwise, a common fixed test key is used instead.
* Execution isolation
(1) TPM
@@ -46,6 +53,10 @@ safe.
Customizable set of operations running in isolated execution
environment verified via Secure/Trusted boot process.
(3) CAAM
Fixed set of operations running in isolated execution environment.
* Optional binding to platform integrity state
(1) TPM
@@ -63,6 +74,11 @@ safe.
Relies on Secure/Trusted boot process for platform integrity. It can
be extended with TEE based measured boot process.
(3) CAAM
Relies on the High Assurance Boot (HAB) mechanism of NXP SoCs
for platform integrity.
* Interfaces and APIs
(1) TPM
@@ -74,10 +90,13 @@ safe.
TEEs have well-documented, standardized client interface and APIs. For
more details refer to ``Documentation/staging/tee.rst``.
(3) CAAM
Interface is specific to silicon vendor.
* Threat model
The strength and appropriateness of a particular TPM or TEE for a given
The strength and appropriateness of a particular trust source for a given
purpose must be assessed when using them to protect security-relevant data.
@@ -87,22 +106,32 @@ Key Generation
Trusted Keys
------------
New keys are created from random numbers generated in the trust source. They
are encrypted/decrypted using a child key in the storage key hierarchy.
Encryption and decryption of the child key must be protected by a strong
access control policy within the trust source.
New keys are created from random numbers. They are encrypted/decrypted using
a child key in the storage key hierarchy. Encryption and decryption of the
child key must be protected by a strong access control policy within the
trust source. The random number generator in use differs according to the
selected trust source:
* TPM (hardware device) based RNG
* TPM: hardware device based RNG
Strength of random numbers may vary from one device manufacturer to
another.
Keys are generated within the TPM. Strength of random numbers may vary
from one device manufacturer to another.
* TEE (OP-TEE based on Arm TrustZone) based RNG
* TEE: OP-TEE based on Arm TrustZone based RNG
RNG is customizable as per platform needs. It can either be direct output
from platform specific hardware RNG or a software based Fortuna CSPRNG
which can be seeded via multiple entropy sources.
* CAAM: Kernel RNG
The normal kernel random number generator is used. To seed it from the
CAAM HWRNG, enable CRYPTO_DEV_FSL_CAAM_RNG_API and ensure the device
is probed.
Users may override this by specifying ``trusted.rng=kernel`` on the kernel
command-line to override the used RNG with the kernel's random number pool.
Encrypted Keys
--------------
@@ -189,6 +218,19 @@ Usage::
specific to TEE device implementation. The key length for new keys is always
in bytes. Trusted Keys can be 32 - 128 bytes (256 - 1024 bits).
Trusted Keys usage: CAAM
------------------------
Usage::
keyctl add trusted name "new keylen" ring
keyctl add trusted name "load hex_blob" ring
keyctl print keyid
"keyctl print" returns an ASCII hex copy of the sealed key, which is in a
CAAM-specific format. The key length for new keys is always in bytes.
Trusted Keys can be 32 - 128 bytes (256 - 1024 bits).
Encrypted Keys usage
--------------------
Documentation/security/landlock.rst
+16 -1
View File
@@ -7,7 +7,7 @@ Landlock LSM: kernel documentation
==================================
:Author: Mickaël Salaün
:Date: March 2021
:Date: May 2022
Landlock's goal is to create scoped access-control (i.e. sandboxing). To
harden a whole system, this feature should be available to any process,
@@ -42,6 +42,21 @@ Guiding principles for safe access controls
* Computation related to Landlock operations (e.g. enforcing a ruleset) shall
only impact the processes requesting them.
Design choices
==============
Filesystem access rights
------------------------
All access rights are tied to an inode and what can be accessed through it.
Reading the content of a directory doesn't imply to be allowed to read the
content of a listed inode. Indeed, a file name is local to its parent
directory, and an inode can be referenced by multiple file names thanks to
(hard) links. Being able to unlink a file only has a direct impact on the
directory, not the unlinked inode. This is the reason why
`LANDLOCK_ACCESS_FS_REMOVE_FILE` or `LANDLOCK_ACCESS_FS_REFER` are not allowed
to be tied to files but only to directories.
Tests
=====
Documentation/userspace-api/landlock.rst
+157 -23
View File
@@ -1,14 +1,14 @@
.. SPDX-License-Identifier: GPL-2.0
.. Copyright © 2017-2020 Mickaël Salaün <mic@digikod.net>
.. Copyright © 2019-2020 ANSSI
.. Copyright © 2021 Microsoft Corporation
.. Copyright © 2021-2022 Microsoft Corporation
=====================================
Landlock: unprivileged access control
=====================================
:Author: Mickaël Salaün
:Date: March 2021
:Date: May 2022
The goal of Landlock is to enable to restrict ambient rights (e.g. global
filesystem access) for a set of processes. Because Landlock is a stackable
@@ -18,6 +18,13 @@ is expected to help mitigate the security impact of bugs or
unexpected/malicious behaviors in user space applications. Landlock empowers
any process, including unprivileged ones, to securely restrict themselves.
We can quickly make sure that Landlock is enabled in the running system by
looking for "landlock: Up and running" in kernel logs (as root): ``dmesg | grep
landlock || journalctl -kg landlock`` . Developers can also easily check for
Landlock support with a :ref:`related system call <landlock_abi_versions>`. If
Landlock is not currently supported, we need to :ref:`configure the kernel
appropriately <kernel_support>`.
Landlock rules
==============
@@ -29,14 +36,15 @@ the thread enforcing it, and its future children.
Defining and enforcing a security policy
----------------------------------------
We first need to create the ruleset that will contain our rules. For this
We first need to define the ruleset that will contain our rules. For this
example, the ruleset will contain rules that only allow read actions, but write
actions will be denied. The ruleset then needs to handle both of these kind of
actions.
actions. This is required for backward and forward compatibility (i.e. the
kernel and user space may not know each other's supported restrictions), hence
the need to be explicit about the denied-by-default access rights.
.. code-block:: c
int ruleset_fd;
struct landlock_ruleset_attr ruleset_attr = {
.handled_access_fs =
LANDLOCK_ACCESS_FS_EXECUTE |
@@ -51,9 +59,34 @@ actions.
LANDLOCK_ACCESS_FS_MAKE_SOCK |
LANDLOCK_ACCESS_FS_MAKE_FIFO |
LANDLOCK_ACCESS_FS_MAKE_BLOCK |
LANDLOCK_ACCESS_FS_MAKE_SYM,
LANDLOCK_ACCESS_FS_MAKE_SYM |
LANDLOCK_ACCESS_FS_REFER,
};
Because we may not know on which kernel version an application will be
executed, it is safer to follow a best-effort security approach. Indeed, we
should try to protect users as much as possible whatever the kernel they are
using. To avoid binary enforcement (i.e. either all security features or
none), we can leverage a dedicated Landlock command to get the current version
of the Landlock ABI and adapt the handled accesses. Let's check if we should
remove the `LANDLOCK_ACCESS_FS_REFER` access right which is only supported
starting with the second version of the ABI.
.. code-block:: c
int abi;
abi = landlock_create_ruleset(NULL, 0, LANDLOCK_CREATE_RULESET_VERSION);
if (abi < 2) {
ruleset_attr.handled_access_fs &= ~LANDLOCK_ACCESS_FS_REFER;
}
This enables to create an inclusive ruleset that will contain our rules.
.. code-block:: c
int ruleset_fd;
ruleset_fd = landlock_create_ruleset(&ruleset_attr, sizeof(ruleset_attr), 0);
if (ruleset_fd < 0) {
perror("Failed to create a ruleset");
@@ -92,6 +125,11 @@ descriptor.
return 1;
}
It may also be required to create rules following the same logic as explained
for the ruleset creation, by filtering access rights according to the Landlock
ABI version. In this example, this is not required because
`LANDLOCK_ACCESS_FS_REFER` is not allowed by any rule.
We now have a ruleset with one rule allowing read access to ``/usr`` while
denying all other handled accesses for the filesystem. The next step is to
restrict the current thread from gaining more privileges (e.g. thanks to a SUID
@@ -125,6 +163,27 @@ ruleset.
Full working code can be found in `samples/landlock/sandboxer.c`_.
Good practices
--------------
It is recommended setting access rights to file hierarchy leaves as much as
possible. For instance, it is better to be able to have ``~/doc/`` as a
read-only hierarchy and ``~/tmp/`` as a read-write hierarchy, compared to
``~/`` as a read-only hierarchy and ``~/tmp/`` as a read-write hierarchy.
Following this good practice leads to self-sufficient hierarchies that don't
depend on their location (i.e. parent directories). This is particularly
relevant when we want to allow linking or renaming. Indeed, having consistent
access rights per directory enables to change the location of such directory
without relying on the destination directory access rights (except those that
are required for this operation, see `LANDLOCK_ACCESS_FS_REFER` documentation).
Having self-sufficient hierarchies also helps to tighten the required access
rights to the minimal set of data. This also helps avoid sinkhole directories,
i.e. directories where data can be linked to but not linked from. However,
this depends on data organization, which might not be controlled by developers.
In this case, granting read-write access to ``~/tmp/``, instead of write-only
access, would potentially allow to move ``~/tmp/`` to a non-readable directory
and still keep the ability to list the content of ``~/tmp/``.
Layers of file path access rights
---------------------------------
@@ -192,6 +251,58 @@ To be allowed to use :manpage:`ptrace(2)` and related syscalls on a target
process, a sandboxed process should have a subset of the target process rules,
which means the tracee must be in a sub-domain of the tracer.
Compatibility
=============
Backward and forward compatibility
----------------------------------
Landlock is designed to be compatible with past and future versions of the
kernel. This is achieved thanks to the system call attributes and the
associated bitflags, particularly the ruleset's `handled_access_fs`. Making
handled access right explicit enables the kernel and user space to have a clear
contract with each other. This is required to make sure sandboxing will not
get stricter with a system update, which could break applications.
Developers can subscribe to the `Landlock mailing list
<https://subspace.kernel.org/lists.linux.dev.html>`_ to knowingly update and
test their applications with the latest available features. In the interest of
users, and because they may use different kernel versions, it is strongly
encouraged to follow a best-effort security approach by checking the Landlock
ABI version at runtime and only enforcing the supported features.
.. _landlock_abi_versions:
Landlock ABI versions
---------------------
The Landlock ABI version can be read with the sys_landlock_create_ruleset()
system call:
.. code-block:: c
int abi;
abi = landlock_create_ruleset(NULL, 0, LANDLOCK_CREATE_RULESET_VERSION);
if (abi < 0) {
switch (errno) {
case ENOSYS:
printf("Landlock is not supported by the current kernel.\n");
break;
case EOPNOTSUPP:
printf("Landlock is currently disabled.\n");
break;
}
return 0;
}
if (abi >= 2) {
printf("Landlock supports LANDLOCK_ACCESS_FS_REFER.\n");
}
The following kernel interfaces are implicitly supported by the first ABI
version. Features only supported from a specific version are explicitly marked
as such.
Kernel interface
================
@@ -228,21 +339,6 @@ Enforcing a ruleset
Current limitations
===================
File renaming and linking
-------------------------
Because Landlock targets unprivileged access controls, it is needed to properly
handle composition of rules. Such property also implies rules nesting.
Properly handling multiple layers of ruleset, each one of them able to restrict
access to files, also implies to inherit the ruleset restrictions from a parent
to its hierarchy. Because files are identified and restricted by their
hierarchy, moving or linking a file from one directory to another implies to
propagate the hierarchy constraints. To protect against privilege escalations
through renaming or linking, and for the sake of simplicity, Landlock currently
limits linking and renaming to the same directory. Future Landlock evolutions
will enable more flexibility for renaming and linking, with dedicated ruleset
flags.
Filesystem topology modification
--------------------------------
@@ -267,8 +363,8 @@ restrict such paths with dedicated ruleset flags.
Ruleset layers
--------------
There is a limit of 64 layers of stacked rulesets. This can be an issue for a
task willing to enforce a new ruleset in complement to its 64 inherited
There is a limit of 16 layers of stacked rulesets. This can be an issue for a
task willing to enforce a new ruleset in complement to its 16 inherited
rulesets. Once this limit is reached, sys_landlock_restrict_self() returns
E2BIG. It is then strongly suggested to carefully build rulesets once in the
life of a thread, especially for applications able to launch other applications
@@ -281,6 +377,44 @@ Memory usage
Kernel memory allocated to create rulesets is accounted and can be restricted
by the Documentation/admin-guide/cgroup-v1/memory.rst.
Previous limitations
====================
File renaming and linking (ABI 1)
---------------------------------
Because Landlock targets unprivileged access controls, it needs to properly
handle composition of rules. Such property also implies rules nesting.
Properly handling multiple layers of rulesets, each one of them able to
restrict access to files, also implies inheritance of the ruleset restrictions
from a parent to its hierarchy. Because files are identified and restricted by
their hierarchy, moving or linking a file from one directory to another implies
propagation of the hierarchy constraints, or restriction of these actions
according to the potentially lost constraints. To protect against privilege
escalations through renaming or linking, and for the sake of simplicity,
Landlock previously limited linking and renaming to the same directory.
Starting with the Landlock ABI version 2, it is now possible to securely
control renaming and linking thanks to the new `LANDLOCK_ACCESS_FS_REFER`
access right.
.. _kernel_support:
Kernel support
==============
Landlock was first introduced in Linux 5.13 but it must be configured at build
time with `CONFIG_SECURITY_LANDLOCK=y`. Landlock must also be enabled at boot
time as the other security modules. The list of security modules enabled by
default is set with `CONFIG_LSM`. The kernel configuration should then
contains `CONFIG_LSM=landlock,[...]` with `[...]` as the list of other
potentially useful security modules for the running system (see the
`CONFIG_LSM` help).
If the running kernel doesn't have `landlock` in `CONFIG_LSM`, then we can
still enable it by adding ``lsm=landlock,[...]`` to
Documentation/admin-guide/kernel-parameters.rst thanks to the bootloader
configuration.
Questions and answers
=====================
MAINTAINERS
+44 -4
View File
@@ -1044,7 +1044,6 @@ F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
F: drivers/net/ethernet/amd/xgbe/
AMD SENSOR FUSION HUB DRIVER
M: Nehal Shah <nehal-bakulchandra.shah@amd.com>
M: Basavaraj Natikar <basavaraj.natikar@amd.com>
L: linux-input@vger.kernel.org
S: Maintained
@@ -1447,6 +1446,7 @@ F: drivers/media/i2c/aptina-pll.*
AQUACOMPUTER D5 NEXT PUMP SENSOR DRIVER
M: Aleksa Savic <savicaleksa83@gmail.com>
M: Jack Doan <me@jackdoan.com>
L: linux-hwmon@vger.kernel.org
S: Maintained
F: Documentation/hwmon/aquacomputer_d5next.rst
@@ -3101,6 +3101,16 @@ S: Maintained
F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
F: drivers/mmc/host/sdhci-of-aspeed*
ASPEED SMC SPI DRIVER
M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
M: Cédric Le Goater <clg@kaod.org>
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
L: linux-spi@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
F: drivers/spi/spi-aspeed-smc.c
ASPEED VIDEO ENGINE DRIVER
M: Eddie James <eajames@linux.ibm.com>
L: linux-media@vger.kernel.org
@@ -4575,7 +4585,9 @@ L: keyrings@vger.kernel.org
S: Maintained
F: Documentation/admin-guide/module-signing.rst
F: certs/
F: scripts/check-blacklist-hashes.awk
F: scripts/sign-file.c
F: tools/certs/
CFAG12864B LCD DRIVER
M: Miguel Ojeda <ojeda@kernel.org>
@@ -8753,6 +8765,14 @@ F: drivers/hid/hid-sensor-*
F: drivers/iio/*/hid-*
F: include/linux/hid-sensor-*
HID WACOM DRIVER
M: Ping Cheng <ping.cheng@wacom.com>
M: Jason Gerecke <jason.gerecke@wacom.com>
L: linux-input@vger.kernel.org
S: Maintained
F: drivers/hid/wacom.h
F: drivers/hid/wacom_*
HIGH-RESOLUTION TIMERS, CLOCKEVENTS
M: Thomas Gleixner <tglx@linutronix.de>
L: linux-kernel@vger.kernel.org
@@ -10872,6 +10892,15 @@ S: Supported
F: include/keys/trusted_tee.h
F: security/keys/trusted-keys/trusted_tee.c
KEYS-TRUSTED-CAAM
M: Ahmad Fatoum <a.fatoum@pengutronix.de>
R: Pengutronix Kernel Team <kernel@pengutronix.de>
L: linux-integrity@vger.kernel.org
L: keyrings@vger.kernel.org
S: Maintained
F: include/keys/trusted_caam.h
F: security/keys/trusted-keys/trusted_caam.c
KEYS/KEYRINGS
M: David Howells <dhowells@redhat.com>
M: Jarkko Sakkinen <jarkko@kernel.org>
@@ -11844,7 +11873,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
M: Hu Ziji <huziji@marvell.com>
L: linux-mmc@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml
F: drivers/mmc/host/sdhci-xenon*
MATROX FRAMEBUFFER DRIVER
@@ -13550,12 +13579,21 @@ M: Samuel Mendoza-Jonas <sam@mendozajonas.com>
S: Maintained
F: net/ncsi/
NCT6775 HARDWARE MONITOR DRIVER
NCT6775 HARDWARE MONITOR DRIVER - CORE & PLATFORM DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org
S: Maintained
F: Documentation/hwmon/nct6775.rst
F: drivers/hwmon/nct6775.c
F: drivers/hwmon/nct6775-core.c
F: drivers/hwmon/nct6775-platform.c
F: drivers/hwmon/nct6775.h
NCT6775 HARDWARE MONITOR DRIVER - I2C DRIVER
M: Zev Weiss <zev@bewilderbeest.net>
L: linux-hwmon@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/hwmon/nuvoton,nct6775.yaml
F: drivers/hwmon/nct6775-i2c.c
NETDEVSIM
M: Jakub Kicinski <kuba@kernel.org>
@@ -19857,6 +19895,7 @@ F: drivers/media/usb/tm6000/
TMIO/SDHI MMC DRIVER
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
L: linux-mmc@vger.kernel.org
L: linux-renesas-soc@vger.kernel.org
S: Supported
F: drivers/mmc/host/renesas_sdhi*
F: drivers/mmc/host/tmio_mmc*
@@ -19866,6 +19905,7 @@ TMP401 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-hwmon@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/hwmon/ti,tmp401.yaml
F: Documentation/hwmon/tmp401.rst
F: drivers/hwmon/tmp401.c
arch/arm64/kernel/smp.c
+1
View File
@@ -517,6 +517,7 @@ struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu)
{
return &cpu_madt_gicc[cpu];
}
EXPORT_SYMBOL_GPL(acpi_cpu_get_madt_gicc);
/*
* acpi_map_gic_cpu_interface - parse processor MADT entry
arch/sh/boards/board-sh7757lcr.c
+1 -1
View File
@@ -16,7 +16,7 @@
#include <linux/io.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/platform_data/sh_mmcif.h>
#include <linux/sh_eth.h>
#include <linux/sh_intc.h>
#include <linux/usb/renesas_usbhs.h>
arch/sh/boards/mach-ecovec24/setup.c
+1 -1
View File
@@ -19,7 +19,7 @@
#include <linux/memblock.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/platform_data/sh_mmcif.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
arch/sh/boot/romimage/mmcif-sh7724.c
+1 -1
View File
@@ -8,7 +8,7 @@
* for more details.
*/
#include <linux/mmc/sh_mmcif.h>
#include <linux/platform_data/sh_mmcif.h>
#include <mach/romimage.h>
#define MMCIF_BASE (void __iomem *)0xa4ca0000
arch/x86/include/asm/msr-index.h
+1
View File
@@ -319,6 +319,7 @@
/* Run Time Average Power Limiting (RAPL) Interface */
#define MSR_VR_CURRENT_CONFIG 0x00000601
#define MSR_RAPL_POWER_UNIT 0x00000606
#define MSR_PKG_POWER_LIMIT 0x00000610
arch/x86/kernel/acpi/boot.c
+4 -5
View File
@@ -435,7 +435,7 @@ static void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
isa_irq_to_gsi[bus_irq] = gsi;
}
static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
static void mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
int polarity)
{
#ifdef CONFIG_X86_MPPARSE
@@ -447,9 +447,9 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
u8 pin;
if (!acpi_ioapic)
return 0;
return;
if (!dev || !dev_is_pci(dev))
return 0;
return;
pdev = to_pci_dev(dev);
number = pdev->bus->number;
@@ -468,7 +468,6 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
mp_save_irq(&mp_irq);
#endif
return 0;
}
static int __init mp_register_ioapic_irq(u8 bus_irq, u8 polarity,
@@ -1863,7 +1862,7 @@ int __acpi_release_global_lock(unsigned int *lock)
void __init arch_reserve_mem_area(acpi_physical_address addr, size_t size)
{
e820__range_add(addr, size, E820_TYPE_ACPI);
e820__range_add(addr, size, E820_TYPE_NVS);
e820__update_table_print();
}
arch/x86/kernel/cpu/mce/apei.c
+3 -5
View File
@@ -177,16 +177,14 @@ retry:
/* no more record */
if (*record_id == APEI_ERST_INVALID_RECORD_ID)
goto out;
rc = erst_read(*record_id, &rcd.hdr, sizeof(rcd));
rc = erst_read_record(*record_id, &rcd.hdr, sizeof(rcd), sizeof(rcd),
&CPER_CREATOR_MCE);
/* someone else has cleared the record, try next one */
if (rc == -ENOENT)
goto retry;
else if (rc < 0)
goto out;
/* try to skip other type records in storage */
else if (rc != sizeof(rcd) ||
!guid_equal(&rcd.hdr.creator_id, &CPER_CREATOR_MCE))
goto retry;
memcpy(m, &rcd.mce, sizeof(*m));
rc = sizeof(*m);
out:
certs/.gitignore
+1
View File
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
/blacklist_hashes_checked
/extract-cert
/x509_certificate_list
/x509_revocation_list
certs/Kconfig
+15 -2
View File
@@ -104,8 +104,11 @@ config SYSTEM_BLACKLIST_HASH_LIST
help
If set, this option should be the filename of a list of hashes in the
form "<hash>", "<hash>", ... . This will be included into a C
wrapper to incorporate the list into the kernel. Each <hash> should
be a string of hex digits.
wrapper to incorporate the list into the kernel. Each <hash> must be a
string starting with a prefix ("tbs" or "bin"), then a colon (":"), and
finally an even number of hexadecimal lowercase characters (up to 128).
Certificate hashes can be generated with
tools/certs/print-cert-tbs-hash.sh .
config SYSTEM_REVOCATION_LIST
bool "Provide system-wide ring of revocation certificates"
@@ -124,4 +127,14 @@ config SYSTEM_REVOCATION_KEYS
containing X.509 certificates to be included in the default blacklist
keyring.
config SYSTEM_BLACKLIST_AUTH_UPDATE
bool "Allow root to add signed blacklist keys"
depends on SYSTEM_BLACKLIST_KEYRING
depends on SYSTEM_DATA_VERIFICATION
help
If set, provide the ability to load new blacklist keys at run time if
they are signed and vouched by a certificate from the builtin trusted
keyring. The PKCS#7 signature of the description is set in the key
payload. Blacklist keys cannot be removed.
endmenu
certs/Makefile
+13 -1
View File
@@ -7,6 +7,18 @@ obj-$(CONFIG_SYSTEM_TRUSTED_KEYRING) += system_keyring.o system_certificates.o c
obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist.o common.o
obj-$(CONFIG_SYSTEM_REVOCATION_LIST) += revocation_certificates.o
ifneq ($(CONFIG_SYSTEM_BLACKLIST_HASH_LIST),)
quiet_cmd_check_blacklist_hashes = CHECK $(patsubst "%",%,$(2))
cmd_check_blacklist_hashes = $(AWK) -f $(srctree)/scripts/check-blacklist-hashes.awk $(2); touch $@
$(eval $(call config_filename,SYSTEM_BLACKLIST_HASH_LIST))
$(obj)/blacklist_hashes.o: $(obj)/blacklist_hashes_checked
CFLAGS_blacklist_hashes.o += -I$(srctree)
targets += blacklist_hashes_checked
$(obj)/blacklist_hashes_checked: $(SYSTEM_BLACKLIST_HASH_LIST_SRCPREFIX)$(SYSTEM_BLACKLIST_HASH_LIST_FILENAME) scripts/check-blacklist-hashes.awk FORCE
$(call if_changed,check_blacklist_hashes,$(SYSTEM_BLACKLIST_HASH_LIST_SRCPREFIX)$(CONFIG_SYSTEM_BLACKLIST_HASH_LIST))
obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist_hashes.o
else
obj-$(CONFIG_SYSTEM_BLACKLIST_KEYRING) += blacklist_nohashes.o
@@ -21,7 +33,7 @@ $(obj)/system_certificates.o: $(obj)/x509_certificate_list
$(obj)/x509_certificate_list: $(CONFIG_SYSTEM_TRUSTED_KEYS) $(obj)/extract-cert FORCE
$(call if_changed,extract_certs)
targets += x509_certificate_list
targets += x509_certificate_list blacklist_hashes_checked
# If module signing is requested, say by allyesconfig, but a key has not been
# supplied, then one will need to be generated to make sure the build does not
certs/blacklist.c
+177 -48
View File
@@ -15,10 +15,24 @@
#include <linux/err.h>
#include <linux/seq_file.h>
#include <linux/uidgid.h>
#include <linux/verification.h>
#include <keys/system_keyring.h>
#include "blacklist.h"
#include "common.h"
/*
* According to crypto/asymmetric_keys/x509_cert_parser.c:x509_note_pkey_algo(),
* the size of the currently longest supported hash algorithm is 512 bits,
* which translates into 128 hex characters.
*/
#define MAX_HASH_LEN 128
#define BLACKLIST_KEY_PERM (KEY_POS_SEARCH | KEY_POS_VIEW | \
KEY_USR_SEARCH | KEY_USR_VIEW)
static const char tbs_prefix[] = "tbs";
static const char bin_prefix[] = "bin";
static struct key *blacklist_keyring;
#ifdef CONFIG_SYSTEM_REVOCATION_LIST
@@ -32,41 +46,89 @@ extern __initconst const unsigned long revocation_certificate_list_size;
*/
static int blacklist_vet_description(const char *desc)
{
int n = 0;
int i, prefix_len, tbs_step = 0, bin_step = 0;
if (*desc == ':')
return -EINVAL;
for (; *desc; desc++)
if (*desc == ':')
goto found_colon;
/* The following algorithm only works if prefix lengths match. */
BUILD_BUG_ON(sizeof(tbs_prefix) != sizeof(bin_prefix));
prefix_len = sizeof(tbs_prefix) - 1;
for (i = 0; *desc; desc++, i++) {
if (*desc == ':') {
if (tbs_step == prefix_len)
goto found_colon;
if (bin_step == prefix_len)
goto found_colon;
return -EINVAL;
}
if (i >= prefix_len)
return -EINVAL;
if (*desc == tbs_prefix[i])
tbs_step++;
if (*desc == bin_prefix[i])
bin_step++;
}
return -EINVAL;
found_colon:
desc++;
for (; *desc; desc++) {
for (i = 0; *desc && i < MAX_HASH_LEN; desc++, i++) {
if (!isxdigit(*desc) || isupper(*desc))
return -EINVAL;
n++;
}
if (*desc)
/* The hash is greater than MAX_HASH_LEN. */
return -ENOPKG;
if (n == 0 || n & 1)
/* Checks for an even number of hexadecimal characters. */
if (i == 0 || i & 1)
return -EINVAL;
return 0;
}
/*
* The hash to be blacklisted is expected to be in the description. There will
* be no payload.
*/
static int blacklist_preparse(struct key_preparsed_payload *prep)
static int blacklist_key_instantiate(struct key *key,
struct key_preparsed_payload *prep)
{
if (prep->datalen > 0)
return -EINVAL;
return 0;
#ifdef CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE
int err;
#endif
/* Sets safe default permissions for keys loaded by user space. */
key->perm = BLACKLIST_KEY_PERM;
/*
* Skips the authentication step for builtin hashes, they are not
* signed but still trusted.
*/
if (key->flags & (1 << KEY_FLAG_BUILTIN))
goto out;
#ifdef CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE
/*
* Verifies the description's PKCS#7 signature against the builtin
* trusted keyring.
*/
err = verify_pkcs7_signature(key->description,
strlen(key->description), prep->data, prep->datalen,
NULL, VERIFYING_UNSPECIFIED_SIGNATURE, NULL, NULL);
if (err)
return err;
#else
/*
* It should not be possible to come here because the keyring doesn't
* have KEY_USR_WRITE and the only other way to call this function is
* for builtin hashes.
*/
WARN_ON_ONCE(1);
return -EPERM;
#endif
out:
return generic_key_instantiate(key, prep);
}
static void blacklist_free_preparse(struct key_preparsed_payload *prep)
static int blacklist_key_update(struct key *key,
struct key_preparsed_payload *prep)
{
return -EPERM;
}
static void blacklist_describe(const struct key *key, struct seq_file *m)
@@ -77,17 +139,48 @@ static void blacklist_describe(const struct key *key, struct seq_file *m)
static struct key_type key_type_blacklist = {
.name = "blacklist",
.vet_description = blacklist_vet_description,
.preparse = blacklist_preparse,
.free_preparse = blacklist_free_preparse,
.instantiate = generic_key_instantiate,
.instantiate = blacklist_key_instantiate,
.update = blacklist_key_update,
.describe = blacklist_describe,
};
static char *get_raw_hash(const u8 *hash, size_t hash_len,
enum blacklist_hash_type hash_type)
{
size_t type_len;
const char *type_prefix;
char *buffer, *p;
switch (hash_type) {
case BLACKLIST_HASH_X509_TBS:
type_len = sizeof(tbs_prefix) - 1;
type_prefix = tbs_prefix;
break;
case BLACKLIST_HASH_BINARY:
type_len = sizeof(bin_prefix) - 1;
type_prefix = bin_prefix;
break;
default:
WARN_ON_ONCE(1);
return ERR_PTR(-EINVAL);
}
buffer = kmalloc(type_len + 1 + hash_len * 2 + 1, GFP_KERNEL);
if (!buffer)
return ERR_PTR(-ENOMEM);
p = memcpy(buffer, type_prefix, type_len);
p += type_len;
*p++ = ':';
bin2hex(p, hash, hash_len);
p += hash_len * 2;
*p = '\0';
return buffer;
}
/**
* mark_hash_blacklisted - Add a hash to the system blacklist
* mark_raw_hash_blacklisted - Add a hash to the system blacklist
* @hash: The hash as a hex string with a type prefix (eg. "tbs:23aa429783")
*/
int mark_hash_blacklisted(const char *hash)
static int mark_raw_hash_blacklisted(const char *hash)
{
key_ref_t key;
@@ -96,8 +189,7 @@ int mark_hash_blacklisted(const char *hash)
hash,
NULL,
0,
((KEY_POS_ALL & ~KEY_POS_SETATTR) |
KEY_USR_VIEW),
BLACKLIST_KEY_PERM,
KEY_ALLOC_NOT_IN_QUOTA |
KEY_ALLOC_BUILT_IN);
if (IS_ERR(key)) {
@@ -107,29 +199,36 @@ int mark_hash_blacklisted(const char *hash)
return 0;
}
int mark_hash_blacklisted(const u8 *hash, size_t hash_len,
enum blacklist_hash_type hash_type)
{
const char *buffer;
int err;
buffer = get_raw_hash(hash, hash_len, hash_type);
if (IS_ERR(buffer))
return PTR_ERR(buffer);
err = mark_raw_hash_blacklisted(buffer);
kfree(buffer);
return err;
}
/**
* is_hash_blacklisted - Determine if a hash is blacklisted
* @hash: The hash to be checked as a binary blob
* @hash_len: The length of the binary hash
* @type: Type of hash
* @hash_type: Type of hash
*/
int is_hash_blacklisted(const u8 *hash, size_t hash_len, const char *type)
int is_hash_blacklisted(const u8 *hash, size_t hash_len,
enum blacklist_hash_type hash_type)
{
key_ref_t kref;
size_t type_len = strlen(type);
char *buffer, *p;
const char *buffer;
int ret = 0;
buffer = kmalloc(type_len + 1 + hash_len * 2 + 1, GFP_KERNEL);
if (!buffer)
return -ENOMEM;
p = memcpy(buffer, type, type_len);
p += type_len;
*p++ = ':';
bin2hex(p, hash, hash_len);
p += hash_len * 2;
*p = 0;
buffer = get_raw_hash(hash, hash_len, hash_type);
if (IS_ERR(buffer))
return PTR_ERR(buffer);
kref = keyring_search(make_key_ref(blacklist_keyring, true),
&key_type_blacklist, buffer, false);
if (!IS_ERR(kref)) {
@@ -144,7 +243,8 @@ EXPORT_SYMBOL_GPL(is_hash_blacklisted);
int is_binary_blacklisted(const u8 *hash, size_t hash_len)
{
if (is_hash_blacklisted(hash, hash_len, "bin") == -EKEYREJECTED)
if (is_hash_blacklisted(hash, hash_len, BLACKLIST_HASH_BINARY) ==
-EKEYREJECTED)
return -EPERM;
return 0;
@@ -166,8 +266,10 @@ int add_key_to_revocation_list(const char *data, size_t size)
NULL,
data,
size,
((KEY_POS_ALL & ~KEY_POS_SETATTR) | KEY_USR_VIEW),
KEY_ALLOC_NOT_IN_QUOTA | KEY_ALLOC_BUILT_IN);
KEY_POS_VIEW | KEY_POS_READ | KEY_POS_SEARCH
| KEY_USR_VIEW,
KEY_ALLOC_NOT_IN_QUOTA | KEY_ALLOC_BUILT_IN
| KEY_ALLOC_BYPASS_RESTRICTION);
if (IS_ERR(key)) {
pr_err("Problem with revocation key (%ld)\n", PTR_ERR(key));
@@ -194,30 +296,57 @@ int is_key_on_revocation_list(struct pkcs7_message *pkcs7)
}
#endif
static int restrict_link_for_blacklist(struct key *dest_keyring,
const struct key_type *type, const union key_payload *payload,
struct key *restrict_key)
{
if (type == &key_type_blacklist)
return 0;
return -EOPNOTSUPP;
}
/*
* Initialise the blacklist
*
* The blacklist_init() function is registered as an initcall via
* device_initcall(). As a result if the blacklist_init() function fails for
* any reason the kernel continues to execute. While cleanly returning -ENODEV
* could be acceptable for some non-critical kernel parts, if the blacklist
* keyring fails to load it defeats the certificate/key based deny list for
* signed modules. If a critical piece of security functionality that users
* expect to be present fails to initialize, panic()ing is likely the right
* thing to do.
*/
static int __init blacklist_init(void)
{
const char *const *bl;
struct key_restriction *restriction;
if (register_key_type(&key_type_blacklist) < 0)
panic("Can't allocate system blacklist key type\n");
restriction = kzalloc(sizeof(*restriction), GFP_KERNEL);
if (!restriction)
panic("Can't allocate blacklist keyring restriction\n");
restriction->check = restrict_link_for_blacklist;
blacklist_keyring =
keyring_alloc(".blacklist",
GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, current_cred(),
(KEY_POS_ALL & ~KEY_POS_SETATTR) |
KEY_USR_VIEW | KEY_USR_READ |
KEY_USR_SEARCH,
KEY_ALLOC_NOT_IN_QUOTA |
KEY_POS_VIEW | KEY_POS_READ | KEY_POS_SEARCH |
KEY_POS_WRITE |
KEY_USR_VIEW | KEY_USR_READ | KEY_USR_SEARCH
#ifdef CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE
| KEY_USR_WRITE
#endif
, KEY_ALLOC_NOT_IN_QUOTA |
KEY_ALLOC_SET_KEEP,
NULL, NULL);
restriction, NULL);
if (IS_ERR(blacklist_keyring))
panic("Can't allocate system blacklist keyring\n");
for (bl = blacklist_hashes; *bl; bl++)
if (mark_hash_blacklisted(*bl) < 0)
if (mark_raw_hash_blacklisted(*bl) < 0)
pr_err("- blacklisting failed\n");
return 0;
}
crypto/asymmetric_keys/x509_public_key.c
+2 -1
View File
@@ -69,7 +69,8 @@ int x509_get_sig_params(struct x509_certificate *cert)
if (ret < 0)
goto error_2;
ret = is_hash_blacklisted(sig->digest, sig->digest_size, "tbs");
ret = is_hash_blacklisted(sig->digest, sig->digest_size,
BLACKLIST_HASH_X509_TBS);
if (ret == -EKEYREJECTED) {
pr_err("Cert %*phN is blacklisted\n",
sig->digest_size, sig->digest);
drivers/acpi/acpica/acapps.h
+2 -2
View File
@@ -3,7 +3,7 @@
*
* Module Name: acapps - common include for ACPI applications/tools
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
@@ -17,7 +17,7 @@
/* Common info for tool signons */
#define ACPICA_NAME "Intel ACPI Component Architecture"
#define ACPICA_COPYRIGHT "Copyright (c) 2000 - 2021 Intel Corporation"
#define ACPICA_COPYRIGHT "Copyright (c) 2000 - 2022 Intel Corporation"
#if ACPI_MACHINE_WIDTH == 64
#define ACPI_WIDTH " (64-bit version)"
drivers/acpi/acpica/accommon.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: accommon.h - Common include files for generation of ACPICA source
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acconvert.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Module Name: acapps - common include for ACPI applications/tools
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acdebug.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acdebug.h - ACPI/AML debugger
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acdispat.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acdispat.h - dispatcher (parser to interpreter interface)
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acevents.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acevents.h - Event subcomponent prototypes and defines
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acglobal.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acglobal.h - Declarations for global variables
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/achware.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: achware.h -- hardware specific interfaces
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acinterp.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acinterp.h - Interpreter subcomponent prototypes and defines
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/aclocal.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: aclocal.h - Internal data types used across the ACPI subsystem
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acmacros.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acmacros.h - C macros for the entire subsystem.
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acnamesp.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acnamesp.h - Namespace subcomponent prototypes and defines
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acobject.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acobject.h - Definition of union acpi_operand_object (Internal object only)
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acopcode.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acopcode.h - AML opcode information for the AML parser and interpreter
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acparser.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Module Name: acparser.h - AML Parser subcomponent prototypes and defines
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acpredef.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acpredef - Information table for ACPI predefined methods and objects
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acresrc.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acresrc.h - Resource Manager function prototypes
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acstruct.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acstruct.h - Internal structs
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/actables.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: actables.h - ACPI table management
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/acutils.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Name: acutils.h -- prototypes for the common (subsystem-wide) procedures
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/amlcode.h
+1 -1
View File
@@ -5,7 +5,7 @@
* Declarations and definitions contained herein are derived
* directly from the ACPI specification.
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/amlresrc.h
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Module Name: amlresrc.h - AML resource descriptors
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/dbhistry.c
+1 -1
View File
@@ -3,7 +3,7 @@
*
* Module Name: dbhistry - debugger HISTORY command
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/
drivers/acpi/acpica/dsargs.c
+1 -1
View File
@@ -4,7 +4,7 @@
* Module Name: dsargs - Support for execution of dynamic arguments for static
* objects (regions, fields, buffer fields, etc.)
*
* Copyright (C) 2000 - 2021, Intel Corp.
* Copyright (C) 2000 - 2022, Intel Corp.
*
*****************************************************************************/

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