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manual update from upstream:

Browse Source 
Applied Al's change 06a544971f
to new location of swiotlb.c

Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Tony Luck
2005-10-31 10:51:57 -08:00
parent 9cec58dc13 581c1b1439
commit c7fb577e2a
3129 changed files with 172658 additions and 82584 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-alpha/atomic.h
+10 -4
View File
@@ -1,6 +1,8 @@
#ifndef _ALPHA_ATOMIC_H
#define _ALPHA_ATOMIC_H
#include <asm/barrier.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc...
@@ -100,18 +102,19 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
static __inline__ long atomic_add_return(int i, atomic_t * v)
{
long temp, result;
smp_mb();
__asm__ __volatile__(
"1: ldl_l %0,%1\n"
" addl %0,%3,%2\n"
" addl %0,%3,%0\n"
" stl_c %0,%1\n"
" beq %0,2f\n"
" mb\n"
".subsection 2\n"
"2: br 1b\n"
".previous"
:"=&r" (temp), "=m" (v->counter), "=&r" (result)
:"Ir" (i), "m" (v->counter) : "memory");
smp_mb();
return result;
}
@@ -120,54 +123,57 @@ static __inline__ long atomic_add_return(int i, atomic_t * v)
static __inline__ long atomic64_add_return(long i, atomic64_t * v)
{
long temp, result;
smp_mb();
__asm__ __volatile__(
"1: ldq_l %0,%1\n"
" addq %0,%3,%2\n"
" addq %0,%3,%0\n"
" stq_c %0,%1\n"
" beq %0,2f\n"
" mb\n"
".subsection 2\n"
"2: br 1b\n"
".previous"
:"=&r" (temp), "=m" (v->counter), "=&r" (result)
:"Ir" (i), "m" (v->counter) : "memory");
smp_mb();
return result;
}
static __inline__ long atomic_sub_return(int i, atomic_t * v)
{
long temp, result;
smp_mb();
__asm__ __volatile__(
"1: ldl_l %0,%1\n"
" subl %0,%3,%2\n"
" subl %0,%3,%0\n"
" stl_c %0,%1\n"
" beq %0,2f\n"
" mb\n"
".subsection 2\n"
"2: br 1b\n"
".previous"
:"=&r" (temp), "=m" (v->counter), "=&r" (result)
:"Ir" (i), "m" (v->counter) : "memory");
smp_mb();
return result;
}
static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
{
long temp, result;
smp_mb();
__asm__ __volatile__(
"1: ldq_l %0,%1\n"
" subq %0,%3,%2\n"
" subq %0,%3,%0\n"
" stq_c %0,%1\n"
" beq %0,2f\n"
" mb\n"
".subsection 2\n"
"2: br 1b\n"
".previous"
:"=&r" (temp), "=m" (v->counter), "=&r" (result)
:"Ir" (i), "m" (v->counter) : "memory");
smp_mb();
return result;
}
include/asm-alpha/barrier.h
+36
View File
@@ -0,0 +1,36 @@
#ifndef __BARRIER_H
#define __BARRIER_H
#include <asm/compiler.h>
#define mb() \
__asm__ __volatile__("mb": : :"memory")
#define rmb() \
__asm__ __volatile__("mb": : :"memory")
#define wmb() \
__asm__ __volatile__("wmb": : :"memory")
#define read_barrier_depends() \
__asm__ __volatile__("mb": : :"memory")
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#endif
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
#define set_wmb(var, value) \
do { var = value; wmb(); } while (0)
#endif /* __BARRIER_H */
include/asm-alpha/dma-mapping.h
+1 -1
View File
@@ -31,7 +31,7 @@
#else /* no PCI - no IOMMU. */
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int gfp);
dma_addr_t *dma_handle, gfp_t gfp);
int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction);
include/asm-alpha/rwsem.h
+5
View File
@@ -262,5 +262,10 @@ static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem)
#endif
}
static inline int rwsem_is_locked(struct rw_semaphore *sem)
{
return (sem->count != 0);
}
#endif /* __KERNEL__ */
#endif /* _ALPHA_RWSEM_H */
include/asm-alpha/semaphore.h
-3
View File
@@ -26,9 +26,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-alpha/system.h
+1 -30
View File
@@ -4,6 +4,7 @@
#include <linux/config.h>
#include <asm/pal.h>
#include <asm/page.h>
#include <asm/barrier.h>
/*
* System defines.. Note that this is included both from .c and .S
@@ -139,36 +140,6 @@ extern void halt(void) __attribute__((noreturn));
struct task_struct;
extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*);
#define mb() \
__asm__ __volatile__("mb": : :"memory")
#define rmb() \
__asm__ __volatile__("mb": : :"memory")
#define wmb() \
__asm__ __volatile__("wmb": : :"memory")
#define read_barrier_depends() \
__asm__ __volatile__("mb": : :"memory")
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#endif
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
#define set_wmb(var, value) \
do { var = value; wmb(); } while (0)
#define imb() \
__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
include/asm-arm/arch-aaec2000/aaec2000.h
+56
View File
@@ -17,6 +17,16 @@
#error You must include hardware.h not this file
#endif /* __ASM_ARCH_HARDWARE_H */
/* Chip selects */
#define AAEC_CS0 0x00000000
#define AAEC_CS1 0x10000000
#define AAEC_CS2 0x20000000
#define AAEC_CS3 0x30000000
/* Flash */
#define AAEC_FLASH_BASE AAEC_CS0
#define AAEC_FLASH_SIZE SZ_64M
/* Interrupt controller */
#define IRQ_BASE __REG(0x80000500)
#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
@@ -148,4 +158,50 @@
#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
/* GPIO Registers */
#define AAEC_GPIO_PHYS 0x80000e00
#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)
#define AAEC_GPIO_PINMUX_PE0CON (1 << 0)
#define AAEC_GPIO_PINMUX_PD0CON (1 << 1)
#define AAEC_GPIO_PINMUX_CODECON (1 << 2)
#define AAEC_GPIO_PINMUX_UART3CON (1 << 3)
/* LCD Controller */
#define AAEC_CLCD_PHYS 0x80003000
#endif /* __ARM_ARCH_AAEC2000_H */
include/asm-arm/arch-aaec2000/aaed2000.h
+40
View File
@@ -0,0 +1,40 @@
/*
* linux/include/asm-arm/arch-aaec2000/aaed2000.h
*
* AAED-2000 specific bits definition
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_AAED2000_H
#define __ASM_ARCH_AAED2000_H
/* External GPIOs. */
#define EXT_GPIO_PBASE AAEC_CS3
#define EXT_GPIO_VBASE 0xf8100000
#define EXT_GPIO_LENGTH 0x00001000
#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x)))
#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x)))
#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE)
#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */
#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */
#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */
#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */
#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */
#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */
#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */
#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */
#endif /* __ARM_ARCH_AAED2000_H */
include/asm-arm/arch-aaec2000/hardware.h
+2 -1
View File
@@ -11,7 +11,8 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <linux/config.h>
#include <asm/sizes.h>
#include <asm/arch/aaec2000.h>
/* The kernel is loaded at physical address 0xf8000000.
* We map the IO space a bit after
include/asm-arm/arch-aaec2000/io.h
+2
View File
@@ -6,6 +6,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-aaec2000/memory.h
+1 -1
View File
@@ -13,7 +13,7 @@
#include <linux/config.h>
#define PHYS_OFFSET (0xf0000000UL)
#define PHYS_OFFSET UL(0xf0000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
include/asm-arm/arch-cl7500/io.h
+2
View File
@@ -10,6 +10,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-cl7500/memory.h
+1 -1
View File
@@ -17,7 +17,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x10000000UL)
#define PHYS_OFFSET UL(0x10000000)
/*
* These are exactly the same on the RiscPC as the
include/asm-arm/arch-clps711x/hardware.h
+117
View File
@@ -235,4 +235,121 @@
#define CEIVA_PB0_BLK_BTN (1<<0)
#endif // #if defined (CONFIG_ARCH_CEIVA)
#if defined (CONFIG_MACH_MP1000)
/* NOR FLASH */
#define MP1000_NIO_BASE 0xf9000000 /* virtual */
#define MP1000_NIO_START CS0_PHYS_BASE /* physical */
#define MP1000_NIO_SIZE 0x00400000
/* DSP Interface */
#define MP1000_DSP_BASE 0xfa000000 /* virtual */
#define MP1000_DSP_START CS1_PHYS_BASE /* physical */
#define MP1000_DSP_SIZE 0x00100000
/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
#define MP1000_LIO_BASE 0xfb000000 /* virtual */
#define MP1000_LIO_START CS2_PHYS_BASE /* physical */
#define MP1000_LIO_SIZE 0x00100000
/* NAND FLASH */
#define MP1000_FIO_BASE 0xfc000000 /* virtual */
#define MP1000_FIO_START CS3_PHYS_BASE /* physical */
#define MP1000_FIO_SIZE 0x00800000
/* Ethernet */
#define MP1000_EIO_BASE 0xfd000000 /* virtual */
#define MP1000_EIO_START CS4_PHYS_BASE /* physical */
#define MP1000_EIO_SIZE 0x00100000
#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
/* IDE */
#define MP1000_IDE_BASE 0xfe000000 /* virtual */
#define MP1000_IDE_START CS5_PHYS_BASE /* physical */
#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
#define IRQ_HARDDISK IRQ_EINT2
/*
* IDE registers definition
*/
#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
#define IDE_BASE_OFF (MP1000_IDE_BASE)
#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
#define IDE_IRQ IRQ_EINT2
#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
#define RTC_ALWAYS_BCD 0
/*
// Definitions of the bit fields in the HwPortA register for the
// MP1000 board.
*/
#define HwPortAKeyboardRow1 0x00000001
#define HwPortAKeyboardRow2 0x00000002
#define HwPortAKeyboardRow3 0x00000004
#define HwPortAKeyboardRow4 0x00000008
#define HwPortAKeyboardRow5 0x00000010
#define HwPortAKeyboardRow6 0x00000020
#define HwPortALCDEnable 0x00000040
#define HwPortAOffhook 0x00000080
/*
// Definitions of the bit fields in the HwPortB register for the
// MP1000 board.
*/
#define HwPortBL3Mode 0x00000001
#define HwPortBL3Clk 0x00000002
#define HwPortBSClk 0x00000001
#define HwPortBSData 0x00000002
#define HwPortBL3Data 0x00000004
#define HwPortBMute 0x00000008
#define HwPortBQD0 0x00000010
#define HwPortBQD1 0x00000020
#define HwPortBQD2 0x00000040
#define HwPortBQD3 0x00000080
/*
// Definitions of the bit fields in the HwPortD register for the
// MP1000 board.
*/
#define HwPortDLED1 0x00000001
#define HwPortDLED2 0x00000002
#define HwPortDLED3 0x00000004
#define HwPortDLED4 0x00000008
#define HwPortDLED5 0x00000010
#define HwPortDEECS 0x00000020
#define HwPortBRTS 0x00000040
#define HwPortBRI 0x00000080
/*
// Definitions of the bit fields in the HwPortE register for the
// MP1000 board.
*/
#define HwPortECLE 0x00000001
#define HwPortESepromDOut 0x00000001
#define HwPortEALE 0x00000002
#define HwPortESepromDIn 0x00000002
#define HwPortENANDCS 0x00000004
#define HwPortESepromCLK 0x00000004
#endif // #if defined (CONFIG_MACH_MP1000)
#endif
include/asm-arm/arch-clps711x/io.h
+2
View File
@@ -20,6 +20,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(a))
include/asm-arm/arch-clps711x/memory.h
+1 -1
View File
@@ -25,7 +25,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0xc0000000UL)
#define PHYS_OFFSET UL(0xc0000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-clps711x/mp1000-seprom.h
+77
View File
@@ -0,0 +1,77 @@
#ifndef MP1000_SEPROM_H
#define MP1000_SEPROM_H
/*
* mp1000-seprom.h
*
*
* This file contains the Serial EEPROM definitions for the MP1000 board
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define COMMAND_ERASE (0x1C0)
#define COMMAND_ERASE_ALL (0x120)
#define COMMAND_WRITE_DISABLE (0x100)
#define COMMAND_WRITE_ENABLE (0x130)
#define COMMAND_READ (0x180)
#define COMMAND_WRITE (0x140)
#define COMMAND_WRITE_ALL (0x110)
//
// Serial EEPROM data format
//
#define PACKED __attribute__ ((packed))
typedef struct _EEPROM {
union {
unsigned char eprom_byte_data[128];
unsigned short eprom_short_data[64];
struct {
unsigned char version PACKED; // EEPROM Version "1" for now
unsigned char box_id PACKED; // Box ID (Standalone, SOHO, embedded, etc)
unsigned char major_hw_version PACKED; // Major Hardware version (Hex)
unsigned char minor_hw_version PACKED; // Minor Hardware Version (Hex)
unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
unsigned char mfg_serial_number[10] PACKED; // Manufacturer Serial number
unsigned char mfg_date[3] PACKED; // Date of Mfg (Formatted YY:MM:DD)
unsigned char country PACKED; // Country of deployment
unsigned char mac_Address[6] PACKED; // MAC Address
unsigned char oem_string[20] PACKED; // OEM ID string
unsigned short feature_bits1 PACKED; // Feature Bits 1
unsigned short feature_bits2 PACKED; // Feature Bits 2
unsigned char filler[75] PACKED; // Unused/Undefined “0” initialized
unsigned short checksum PACKED; // byte accumulated short checksum
} eprom_struct;
} variant;
} eeprom_struct;
/* These settings must be mutually exclusive */
#define FEATURE_BITS1_DRAMSIZE_16MEG 0x0001 /* 0 signifies 4 MEG system */
#define FEATURE_BITS1_DRAMSIZE_8MEG 0x0002 /* 1 in bit 1 = 8MEG system */
#define FEATURE_BITS1_DRAMSIZE_64MEG 0x0004 /* 1 in bit 2 = 64MEG system */
#define FEATURE_BITS1_CPUIS90MEG 0x0010
extern void seprom_init(void);
extern eeprom_struct* get_seprom_ptr(void);
extern unsigned char* get_eeprom_mac_address(void);
#endif /* MP1000_SEPROM_H */
include/asm-arm/arch-ebsa110/memory.h
+1 -1
View File
@@ -19,7 +19,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
/*
* We keep this 1:1 so that we don't interfere
include/asm-arm/arch-ebsa285/io.h
+2
View File
@@ -14,6 +14,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff
/*
include/asm-arm/arch-ebsa285/memory.h
+5 -5
View File
@@ -46,14 +46,14 @@ extern unsigned long __bus_to_virt(unsigned long);
#if defined(CONFIG_ARCH_FOOTBRIDGE)
/* Task size and page offset at 3GB */
#define TASK_SIZE (0xbf000000UL)
#define PAGE_OFFSET (0xc0000000UL)
#define TASK_SIZE UL(0xbf000000)
#define PAGE_OFFSET UL(0xc0000000)
#elif defined(CONFIG_ARCH_CO285)
/* Task size and page offset at 1.5GB */
#define TASK_SIZE (0x5f000000UL)
#define PAGE_OFFSET (0x60000000UL)
#define TASK_SIZE UL(0x5f000000)
#define PAGE_OFFSET UL(0x60000000)
#else
@@ -64,7 +64,7 @@ extern unsigned long __bus_to_virt(unsigned long);
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
/*
* This decides where the kernel will search for a free chunk of vm
include/asm-arm/arch-epxa10db/io.h
+2
View File
@@ -20,6 +20,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff
include/asm-arm/arch-epxa10db/memory.h
+1 -1
View File
@@ -23,7 +23,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-h720x/io.h
+1 -1
View File
@@ -14,7 +14,7 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/arch/hardware.h>
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
include/asm-arm/arch-h720x/memory.h
+1 -1
View File
@@ -11,7 +11,7 @@
* Page offset:
* ( 0xc0000000UL )
*/
#define PHYS_OFFSET (0x40000000UL)
#define PHYS_OFFSET UL(0x40000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-imx/io.h
+2
View File
@@ -20,6 +20,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(a))
include/asm-arm/arch-imx/memory.h
+1 -1
View File
@@ -21,7 +21,7 @@
#ifndef __ASM_ARCH_MMU_H
#define __ASM_ARCH_MMU_H
#define PHYS_OFFSET (0x08000000UL)
#define PHYS_OFFSET UL(0x08000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-integrator/hardware.h
-9
View File
@@ -33,15 +33,6 @@
#define IO_SIZE 0x0B000000 // How much?
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
/*
* Similar to above, but for PCI addresses (memory, IO, Config and the
* V3 chip itself). WARNING: this has to mirror definitions in platform.h
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define PCIO_BASE PCI_IO_VADDR
#define PCIMEM_BASE PCI_MEMORY_VADDR
include/asm-arm/arch-integrator/io.h
+8
View File
@@ -22,6 +22,14 @@
#define IO_SPACE_LIMIT 0xffff
/*
* WARNING: this has to mirror definitions in platform.h
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
include/asm-arm/arch-integrator/memory.h
+2 -2
View File
@@ -23,8 +23,8 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
#define BUS_OFFSET (0x80000000UL)
#define PHYS_OFFSET UL(0x00000000)
#define BUS_OFFSET UL(0x80000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-iop3xx/io.h
+2
View File
@@ -11,6 +11,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)(p))
include/asm-arm/arch-iop3xx/memory.h
+2 -2
View File
@@ -12,9 +12,9 @@
* Physical DRAM offset.
*/
#ifndef CONFIG_ARCH_IOP331
#define PHYS_OFFSET (0xa0000000UL)
#define PHYS_OFFSET UL(0xa0000000)
#else
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
#endif
/*
include/asm-arm/arch-ixp2000/io.h
+2
View File
@@ -15,6 +15,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __mem_pci(a) (a)
include/asm-arm/arch-ixp2000/ixdp2x01.h
+1 -1
View File
@@ -22,7 +22,7 @@
#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
include/asm-arm/arch-ixp2000/ixp2000-regs.h
+43
View File
@@ -392,4 +392,47 @@
#define WDT_RESET_ENABLE 0x01000000
/*
* MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
* units, but the registers that differ between the two don't overlap,
* so we can have one register list for both.
*/
#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
#endif /* _IXP2000_H_ */
include/asm-arm/arch-ixp2000/memory.h
+1 -1
View File
@@ -13,7 +13,7 @@
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-ixp2000/platform.h
+26 -26
View File
@@ -15,40 +15,40 @@
#ifndef __ASSEMBLY__
/*
* The IXP2400 B0 silicon contains an erratum (#66) that causes writes
* to on-chip I/O register to not complete fully. What this means is
* that if you have a write to on-chip I/O followed by a back-to-back
* read or write, the first write will happen twice. OR...if it's
* not a back-to-back transaction, the read or write will generate
* incorrect data.
*
* The official work around for this is to set the on-chip I/O regions
* as XCB=101 and then force a read-back from the register.
*
*/
#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
#include <asm/system.h> /* Pickup local_irq_ functions */
static inline unsigned long ixp2000_reg_read(volatile void *reg)
{
return *((volatile unsigned long *)reg);
}
static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
{
*((volatile unsigned long *)reg) = val;
}
/*
* On the IXP2400, we can't use XCB=000 due to chip bugs. We use
* XCB=101 instead, but that makes all I/O accesses bufferable. This
* is not a problem in general, but we do have to be slightly more
* careful because I/O writes are no longer automatically flushed out
* of the write buffer.
*
* In cases where we want to make sure that a write has been flushed
* out of the write buffer before we proceed, for example when masking
* a device interrupt before re-enabling IRQs in CPSR, we can use this
* function, ixp2000_reg_wrb, which performs a write, a readback, and
* issues a dummy instruction dependent on the value of the readback
* (mov rX, rX) to make sure that the readback has completed before we
* continue.
*/
static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
{
unsigned long dummy;
unsigned long flags;
local_irq_save(flags);
*((volatile unsigned long *)reg) = val;
barrier();
dummy = *((volatile unsigned long *)reg);
local_irq_restore(flags);
__asm__ __volatile__("mov %0, %0" : "+r" (dummy));
}
#else
static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
{
*((volatile unsigned long *)reg) = val;
}
#endif /* IXDP2400 || IXDP2401 */
#define ixp2000_reg_read(reg) (*((volatile unsigned long *)reg))
/*
* Boards may multiplex different devices on the 2nd channel of
include/asm-arm/arch-ixp4xx/io.h
+3 -3
View File
@@ -113,7 +113,7 @@ __ixp4xx_writeb(u8 value, u32 addr)
}
static inline void
__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
__ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count)
{
while (count--)
writeb(*vaddr++, bus_addr);
@@ -136,7 +136,7 @@ __ixp4xx_writew(u16 value, u32 addr)
}
static inline void
__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
__ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count)
{
while (count--)
writew(*vaddr++, bus_addr);
@@ -154,7 +154,7 @@ __ixp4xx_writel(u32 value, u32 addr)
}
static inline void
__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
__ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count)
{
while (count--)
writel(*vaddr++, bus_addr);
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+48 -25
View File
@@ -36,11 +36,11 @@
*
* 0x6000000 0x00004000 ioremap'd QMgr
*
* 0xC0000000 0x00001000 0xffbfe000 PCI CFG
* 0xC0000000 0x00001000 0xffbff000 PCI CFG
*
* 0xC4000000 0x00001000 0xffbfd000 EXP CFG
* 0xC4000000 0x00001000 0xffbfe000 EXP CFG
*
* 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals
* 0xC8000000 0x00013000 0xffbeb000 On-Chip Peripherals
*/
/*
@@ -52,22 +52,22 @@
* Expansion BUS Configuration registers
*/
#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000)
#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000)
#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
/*
* PCI Config registers
*/
#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFE000)
#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000)
#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
/*
* Peripheral space
*/
#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000)
#define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000)
/*
* Debug UART
@@ -115,25 +115,48 @@
/*
* Peripheral Space Register Region Base Addresses
*/
#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
/* ixp46X only */
#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
#define IXP4XX_NPEA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
#define IXP4XX_NPEB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
#define IXP4XX_NPEC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
/* ixp46X only */
#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
/*
* Constants to make it easy to access Interrupt Controller registers
include/asm-arm/arch-ixp4xx/memory.h
+1 -1
View File
@@ -12,7 +12,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
#ifndef __ASSEMBLY__
include/asm-arm/arch-l7200/io.h
+1 -1
View File
@@ -10,7 +10,7 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/arch/hardware.h>
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
include/asm-arm/arch-l7200/memory.h
+1 -1
View File
@@ -15,7 +15,7 @@
/*
* Physical DRAM offset on the L7200 SDB.
*/
#define PHYS_OFFSET (0xf0000000UL)
#define PHYS_OFFSET UL(0xf0000000)
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
include/asm-arm/arch-lh7a40x/io.h
+2
View File
@@ -11,6 +11,8 @@
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/* No ISA or PCI bus on this machine. */
include/asm-arm/arch-lh7a40x/memory.h
+1 -1
View File
@@ -17,7 +17,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0xc0000000UL)
#define PHYS_OFFSET UL(0xc0000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-omap/io.h
+2
View File
@@ -34,6 +34,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-omap/memory.h
+3 -3
View File
@@ -37,9 +37,9 @@
* Physical DRAM offset.
*/
#if defined(CONFIG_ARCH_OMAP1)
#define PHYS_OFFSET (0x10000000UL)
#define PHYS_OFFSET UL(0x10000000)
#elif defined(CONFIG_ARCH_OMAP2)
#define PHYS_OFFSET (0x80000000UL)
#define PHYS_OFFSET UL(0x80000000)
#endif
/*
@@ -66,7 +66,7 @@
/*
* OMAP-1510 Local Bus address offset
*/
#define OMAP1510_LB_OFFSET (0x30000000UL)
#define OMAP1510_LB_OFFSET UL(0x30000000)
#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
include/asm-arm/arch-pxa/hardware.h
+2 -2
View File
@@ -44,12 +44,12 @@
#ifndef __ASSEMBLY__
# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
/* With indexed regs we don't want to feed the index through io_p2v()
especially if it is a variable, otherwise horrible code will result. */
# define __REG2(x,y) \
(*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
(*(volatile u32 *)((u32)&__REG(x) + (y)))
# define __PREG(x) (io_v2p((u32)&(x)))
include/asm-arm/arch-pxa/io.h
+2
View File
@@ -6,6 +6,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-pxa/irda.h
+17
View File
@@ -0,0 +1,17 @@
#ifndef ASMARM_ARCH_IRDA_H
#define ASMARM_ARCH_IRDA_H
/* board specific transceiver capabilities */
#define IR_OFF 1
#define IR_SIRMODE 2
#define IR_FIRMODE 4
struct pxaficp_platform_data {
int transceiver_cap;
void (*transceiver_mode)(struct device *dev, int mode);
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
#endif
include/asm-arm/arch-pxa/memory.h
+1 -1
View File
@@ -15,7 +15,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0xa0000000UL)
#define PHYS_OFFSET UL(0xa0000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/arch-pxa/pxa-regs.h
+40 -2
View File
@@ -326,6 +326,25 @@
#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Hardware UART (HWUART) */
#define HWUART HWRBR
#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
@@ -1013,14 +1032,12 @@
#define ICCR0_LBM (1 << 1) /* Loopback mode */
#define ICCR0_ITR (1 << 0) /* IrDA transmission */
#ifdef CONFIG_PXA27x
#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
#endif
#ifdef CONFIG_PXA27x
#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
@@ -1250,9 +1267,13 @@
#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
#define GPIO41_FFRTS 41 /* FFUART request to send */
#define GPIO42_BTRXD 42 /* BTUART receive data */
#define GPIO42_HWRXD 42 /* HWUART receive data */
#define GPIO43_BTTXD 43 /* BTUART transmit data */
#define GPIO43_HWTXD 43 /* HWUART transmit data */
#define GPIO44_BTCTS 44 /* BTUART clear to send */
#define GPIO44_HWCTS 44 /* HWUART clear to send */
#define GPIO45_BTRTS 45 /* BTUART request to send */
#define GPIO45_HWRTS 45 /* HWUART request to send */
#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
#define GPIO46_ICPRXD 46 /* ICP receive data */
#define GPIO46_STRXD 46 /* STD_UART receive data */
@@ -1378,17 +1399,26 @@
#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
@@ -1763,6 +1793,7 @@
#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
@@ -2282,4 +2313,11 @@
#endif
/* PWRMODE register M field values */
#define PWRMODE_IDLE 0x1
#define PWRMODE_STANDBY 0x2
#define PWRMODE_SLEEP 0x3
#define PWRMODE_DEEPSLEEP 0x7
#endif
include/asm-arm/arch-pxa/uncompress.h
+1
View File
@@ -12,6 +12,7 @@
#define FFUART ((volatile unsigned long *)0x40100000)
#define BTUART ((volatile unsigned long *)0x40200000)
#define STUART ((volatile unsigned long *)0x40700000)
#define HWUART ((volatile unsigned long *)0x41600000)
#define UART FFUART
include/asm-arm/arch-rpc/io.h
+2
View File
@@ -13,6 +13,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-rpc/memory.h
+1 -1
View File
@@ -21,7 +21,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x10000000UL)
#define PHYS_OFFSET UL(0x10000000)
/*
* These are exactly the same on the RiscPC as the
include/asm-arm/arch-s3c2410/fb.h
+2 -1
View File
@@ -13,6 +13,7 @@
* 07-Sep-2004 RTP Created file
* 03-Nov-2004 BJD Updated and minor cleanups
* 03-Aug-2005 RTP Renamed to fb.h
* 26-Oct-2005 BJD Changed name of platdata init
*/
#ifndef __ASM_ARM_FB_H
@@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
unsigned long lpcsel;
};
void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
#endif /* __ASM_ARM_FB_H */
include/asm-arm/arch-s3c2410/io.h
+2
View File
@@ -15,6 +15,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-s3c2410/memory.h
+2 -2
View File
@@ -28,9 +28,9 @@
* and at 0x0C000000 for S3C2400
*/
#ifdef CONFIG_CPU_S3C2400
#define PHYS_OFFSET (0x0C000000UL)
#define PHYS_OFFSET UL(0x0C000000)
#else
#define PHYS_OFFSET (0x30000000UL)
#define PHYS_OFFSET UL(0x30000000)
#endif
/*
include/asm-arm/arch-s3c2410/regs-clock.h
+17 -4
View File
@@ -18,7 +18,9 @@
* 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
* 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
* 27-Aug-2005 Ben Dooks Add clock-slow info
*/
* 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat)
* 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat)
*/
#ifndef __ASM_ARM_REGS_CLOCK
#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
@@ -66,11 +68,16 @@
#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
#define S3C2410_DCLKCON_DCLK1EN (1<<16)
#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
#define S3C2410_CLKDIVN_PDIVN (1<<0)
#define S3C2410_CLKDIVN_HDIVN (1<<1)
@@ -83,10 +90,13 @@
#ifndef __ASSEMBLY__
#include <asm/div64.h>
static inline unsigned int
s3c2410_get_pll(int pllval, int baseclk)
s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
{
int mdiv, pdiv, sdiv;
unsigned int mdiv, pdiv, sdiv;
uint64_t fvco;
mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk)
pdiv &= S3C2410_PLLCON_PDIVMASK;
sdiv &= S3C2410_PLLCON_SDIVMASK;
return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
fvco = (uint64_t)baseclk * (mdiv + 8);
do_div(fvco, (pdiv + 2) << sdiv);
return (unsigned int)fvco;
}
#endif /* __ASSEMBLY__ */
include/asm-arm/arch-s3c2410/regs-gpio.h
+6
View File
@@ -20,6 +20,7 @@
* 18-11-2004 BJD Added S3C2440 AC97 controls
* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
* 28-Mar-2005 LCVR Fixed definition of GPB10
* 26-Oct-2005 BJD Added generic configuration types
*/
@@ -43,6 +44,11 @@
/* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
#define S3C2410_GPIO_INPUT (0xFFFFFFF0)
#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
/* configure GPIO ports A..G */
include/asm-arm/arch-sa1100/hardware.h
-7
View File
@@ -21,13 +21,6 @@
#define UNCACHEABLE_ADDR 0xfa050000
/*
* We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for
* in*()/out*() macros to be usable for all cases.
*/
#define PCIO_BASE 0
/*
* SA1100 internal I/O mappings
*
include/asm-arm/arch-sa1100/io.h
+7 -1
View File
@@ -10,13 +10,19 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)addr;
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
include/asm-arm/arch-sa1100/memory.h
+1 -1
View File
@@ -13,7 +13,7 @@
/*
* Physical DRAM offset is 0xc0000000 on the SA1100
*/
#define PHYS_OFFSET (0xc0000000UL)
#define PHYS_OFFSET UL(0xc0000000)
#ifndef __ASSEMBLY__
include/asm-arm/arch-sa1100/system.h
+1
View File
@@ -4,6 +4,7 @@
* Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
*/
#include <linux/config.h>
#include <asm/hardware.h>
static inline void arch_idle(void)
{
include/asm-arm/arch-shark/io.h
+2
View File
@@ -11,6 +11,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-shark/memory.h
+1 -1
View File
@@ -15,7 +15,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x08000000UL)
#define PHYS_OFFSET UL(0x08000000)
#ifndef __ASSEMBLY__
include/asm-arm/arch-versatile/memory.h
+1 -1
View File
@@ -23,7 +23,7 @@
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET (0x00000000UL)
#define PHYS_OFFSET UL(0x00000000)
/*
* Virtual view <-> DMA view memory address translations
include/asm-arm/bitops.h
-1
View File
@@ -347,7 +347,6 @@ static inline unsigned long __ffs(unsigned long word)
* the clz instruction for much better code efficiency.
*/
static __inline__ int generic_fls(int x);
#define fls(x) \
( __builtin_constant_p(x) ? generic_fls(x) : \
({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
include/asm-arm/dma-mapping.h
+2 -2
View File
@@ -70,7 +70,7 @@ static inline int dma_mapping_error(dma_addr_t dma_addr)
* device-viewed address.
*/
extern void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
/**
* dma_free_coherent - free memory allocated by dma_alloc_coherent
@@ -117,7 +117,7 @@ int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
* device-viewed address.
*/
extern void *
dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
#define dma_free_writecombine(dev,size,cpu_addr,handle) \
dma_free_coherent(dev,size,cpu_addr,handle)
include/asm-arm/io.h
-1
View File
@@ -26,7 +26,6 @@
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/memory.h>
#include <asm/arch/hardware.h>
/*
* ISA I/O bus memory addresses are 1:1 with the physical address.
include/asm-arm/mach/arch.h
+4 -3
View File
@@ -48,10 +48,11 @@ struct machine_desc {
* Set of macros to define architecture features. This is built into
* a table by the linker.
*/
#define MACHINE_START(_type,_name) \
const struct machine_desc __mach_desc_##_type \
#define MACHINE_START(_type,_name) \
static const struct machine_desc __mach_desc_##_type \
__attribute_used__ \
__attribute__((__section__(".arch.info.init"))) = { \
.nr = MACH_TYPE_##_type, \
.nr = MACH_TYPE_##_type, \
.name = _name,
#define MACHINE_END \
include/asm-arm/mach/flash.h
+2
View File
@@ -14,6 +14,7 @@ struct mtd_partition;
/*
* map_name: the map probe function name
* name: flash device name (eg, as used with mtdparts=)
* width: width of mapped device
* init: method called at driver/device initialisation
* exit: method called at driver/device removal
@@ -23,6 +24,7 @@ struct mtd_partition;
*/
struct flash_platform_data {
const char *map_name;
const char *name;
unsigned int width;
int (*init)(void);
void (*exit)(void);
include/asm-arm/mach/map.h
+4 -1
View File
@@ -11,7 +11,7 @@
*/
struct map_desc {
unsigned long virtual;
unsigned long physical;
unsigned long pfn;
unsigned long length;
unsigned int type;
};
@@ -27,6 +27,9 @@ struct meminfo;
#define MT_ROM 6
#define MT_IXP2000_DEVICE 7
#define __phys_to_pfn(paddr) ((paddr) >> PAGE_SHIFT)
#define __pfn_to_phys(pfn) ((pfn) << PAGE_SHIFT)
extern void create_memmap_holes(struct meminfo *);
extern void memtable_init(struct meminfo *);
extern void iotable_init(struct map_desc *, int);
include/asm-arm/memory.h
+21 -4
View File
@@ -12,6 +12,16 @@
#ifndef __ASM_ARM_MEMORY_H
#define __ASM_ARM_MEMORY_H
/*
* Allow for constants defined here to be used from assembly code
* by prepending the UL suffix only with actual C code compilation.
*/
#ifndef __ASSEMBLY__
#define UL(x) (x##UL)
#else
#define UL(x) (x)
#endif
#include <linux/config.h>
#include <linux/compiler.h>
#include <asm/arch/memory.h>
@@ -21,20 +31,20 @@
* TASK_SIZE - the maximum size of a user space task.
* TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
*/
#define TASK_SIZE (0xbf000000UL)
#define TASK_UNMAPPED_BASE (0x40000000UL)
#define TASK_SIZE UL(0xbf000000)
#define TASK_UNMAPPED_BASE UL(0x40000000)
#endif
/*
* The maximum size of a 26-bit user space task.
*/
#define TASK_SIZE_26 (0x04000000UL)
#define TASK_SIZE_26 UL(0x04000000)
/*
* Page offset: 3GB
*/
#ifndef PAGE_OFFSET
#define PAGE_OFFSET (0xc0000000UL)
#define PAGE_OFFSET UL(0xc0000000)
#endif
/*
@@ -58,6 +68,13 @@
#error Top of user space clashes with start of module space
#endif
/*
* The XIP kernel gets mapped at the bottom of the module vm area.
* Since we use sections to map it, this macro replaces the physical address
* with its virtual address while keeping offset from the base section.
*/
#define XIP_VIRT_ADDR(physaddr) (MODULE_START + ((physaddr) & 0x000fffff))
#ifndef __ASSEMBLY__
/*
include/asm-arm/pgtable.h
-3
View File
@@ -397,9 +397,6 @@ static inline pte_t *pmd_page_kernel(pmd_t pmd)
#define pgd_clear(pgdp) do { } while (0)
#define set_pgd(pgd,pgdp) do { } while (0)
#define page_pte_prot(page,prot) mk_pte(page, prot)
#define page_pte(page) mk_pte(page, __pgprot(0))
/* to find an entry in a page-table-directory */
#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
include/asm-arm/semaphore.h
-2
View File
@@ -24,8 +24,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \
}
#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INIT(name,count)
include/asm-arm/tlb.h
+3 -20
View File
@@ -27,11 +27,7 @@
*/
struct mmu_gather {
struct mm_struct *mm;
unsigned int freed;
unsigned int fullmm;
unsigned int flushes;
unsigned int avoided_flushes;
};
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -39,11 +35,9 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
static inline struct mmu_gather *
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
{
int cpu = smp_processor_id();
struct mmu_gather *tlb = &per_cpu(mmu_gathers, cpu);
struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
tlb->mm = mm;
tlb->freed = 0;
tlb->fullmm = full_mm_flush;
return tlb;
@@ -52,24 +46,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
static inline void
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
struct mm_struct *mm = tlb->mm;
unsigned long freed = tlb->freed;
int rss = get_mm_counter(mm, rss);
if (rss < freed)
freed = rss;
add_mm_counter(mm, rss, -freed);
if (tlb->fullmm)
flush_tlb_mm(mm);
flush_tlb_mm(tlb->mm);
/* keep the page table cache within bounds */
check_pgt_cache();
}
static inline unsigned int tlb_is_full_mm(struct mmu_gather *tlb)
{
return tlb->fullmm;
put_cpu_var(mmu_gathers);
}
#define tlb_remove_tlb_entry(tlb,ptep,address) do { } while (0)
include/asm-arm/unistd.h
-1
View File
@@ -544,7 +544,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
asmlinkage int sys_fork(struct pt_regs *regs);
asmlinkage int sys_vfork(struct pt_regs *regs);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-arm26/pgtable.h
-2
View File
@@ -98,8 +98,6 @@ extern struct page *empty_zero_page;
#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
#define page_pte_prot(page,prot) mk_pte(page, prot)
#define page_pte(page) mk_pte(page, __pgprot(0))
/*
* Terminology: PGD = Page Directory, PMD = Page Middle Directory,
include/asm-arm26/semaphore.h
-3
View File
@@ -25,9 +25,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INIT(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INIT(name,count)
include/asm-arm26/tlb.h
+16 -31
View File
@@ -10,24 +10,20 @@
*/
struct mmu_gather {
struct mm_struct *mm;
unsigned int freed;
unsigned int fullmm;
unsigned int flushes;
unsigned int avoided_flushes;
unsigned int need_flush;
unsigned int fullmm;
};
extern struct mmu_gather mmu_gathers[NR_CPUS];
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
static inline struct mmu_gather *
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
{
int cpu = smp_processor_id();
struct mmu_gather *tlb = &mmu_gathers[cpu];
struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
tlb->mm = mm;
tlb->freed = 0;
tlb->fullmm = full_mm_flush;
tlb->need_flush = 0;
tlb->fullmm = full_mm_flush;
return tlb;
}
@@ -35,30 +31,13 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
static inline void
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
struct mm_struct *mm = tlb->mm;
unsigned long freed = tlb->freed;
int rss = get_mm_counter(mm, rss);
if (rss < freed)
freed = rss;
add_mm_counter(mm, rss, -freed);
if (freed) {
flush_tlb_mm(mm);
tlb->flushes++;
} else {
tlb->avoided_flushes++;
}
if (tlb->need_flush)
flush_tlb_mm(tlb->mm);
/* keep the page table cache within bounds */
check_pgt_cache();
}
static inline unsigned int
tlb_is_full_mm(struct mmu_gather *tlb)
{
return tlb->fullmm;
put_cpu_var(mmu_gathers);
}
#define tlb_remove_tlb_entry(tlb,ptep,address) do { } while (0)
@@ -71,7 +50,13 @@ tlb_is_full_mm(struct mmu_gather *tlb)
} while (0)
#define tlb_end_vma(tlb,vma) do { } while (0)
#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
static inline void
tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
tlb->need_flush = 1;
free_page_and_swap_cache(page);
}
#define pte_free_tlb(tlb,ptep) pte_free(ptep)
#define pmd_free_tlb(tlb,pmdp) pmd_free(pmdp)
include/asm-arm26/unistd.h
-1
View File
@@ -480,7 +480,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
asmlinkage int sys_fork(struct pt_regs *regs);
asmlinkage int sys_vfork(struct pt_regs *regs);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-cris/dma-mapping.h
+2 -2
View File
@@ -15,14 +15,14 @@
#ifdef CONFIG_PCI
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
#else
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
BUG();
return NULL;
include/asm-cris/semaphore.h
-3
View File
@@ -33,9 +33,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-cris/unistd.h
-1
View File
@@ -367,7 +367,6 @@ asmlinkage int sys_fork(long r10, long r11, long r12, long r13,
asmlinkage int sys_vfork(long r10, long r11, long r12, long r13,
long mof, long srp, struct pt_regs *regs);
asmlinkage int sys_pipe(unsigned long __user *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-frv/dma-mapping.h
+1 -1
View File
@@ -13,7 +13,7 @@
extern unsigned long __nongprelbss dma_coherent_mem_start;
extern unsigned long __nongprelbss dma_coherent_mem_end;
void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, int gfp);
void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp);
void dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle);
/*
include/asm-frv/pci.h
+1 -1
View File
@@ -32,7 +32,7 @@ extern void pcibios_set_master(struct pci_dev *dev);
extern void pcibios_penalize_isa_irq(int irq);
#ifdef CONFIG_MMU
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle);
extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
extern void consistent_free(void *vaddr);
extern void consistent_sync(void *vaddr, size_t size, int direction);
extern void consistent_sync_page(struct page *page, unsigned long offset,
include/asm-frv/pgtable.h
-2
View File
@@ -436,8 +436,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
return pte;
}
#define page_pte(page) page_pte_prot((page), __pgprot(0))
/* to find an entry in a page-table-directory. */
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
#define pgd_index_k(addr) pgd_index(addr)
include/asm-frv/semaphore.h
-3
View File
@@ -47,9 +47,6 @@ struct semaphore {
#define __SEMAPHORE_INITIALIZER(name,count) \
{ count, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) __SEM_DEBUG_INIT(name) }
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-generic/4level-fixup.h
+3 -8
View File
@@ -10,14 +10,9 @@
#define pud_t pgd_t
#define pmd_alloc(mm, pud, address) \
({ pmd_t *ret; \
if (pgd_none(*pud)) \
ret = __pmd_alloc(mm, pud, address); \
else \
ret = pmd_offset(pud, address); \
ret; \
})
#define pmd_alloc(mm, pud, address) \
((unlikely(pgd_none(*(pud))) && __pmd_alloc(mm, pud, address))? \
NULL: pmd_offset(pud, address))
#define pud_alloc(mm, pgd, address) (pgd)
#define pud_offset(pgd, start) (pgd)
include/asm-generic/dma-mapping-broken.h
+1 -1
View File
@@ -6,7 +6,7 @@
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
BUG();
return NULL;
include/asm-generic/pgtable.h
+1 -1
View File
@@ -8,7 +8,7 @@
* - update the page tables
* - inform the TLB about the new one
*
* We hold the mm semaphore for reading and vma->vm_mm->page_table_lock.
* We hold the mm semaphore for reading, and the pte lock.
*
* Note: the old pte is known to not be writable, so we don't need to
* worry about dirty bits etc getting lost.
include/asm-generic/tlb.h
+4 -19
View File
@@ -35,16 +35,13 @@
#endif
/* struct mmu_gather is an opaque type used by the mm code for passing around
* any data needed by arch specific code for tlb_remove_page. This structure
* can be per-CPU or per-MM as the page table lock is held for the duration of
* TLB shootdown.
* any data needed by arch specific code for tlb_remove_page.
*/
struct mmu_gather {
struct mm_struct *mm;
unsigned int nr; /* set to ~0U means fast mode */
unsigned int need_flush;/* Really unmapped some ptes? */
unsigned int fullmm; /* non-zero means full mm flush */
unsigned long freed;
struct page * pages[FREE_PTE_NR];
};
@@ -57,7 +54,7 @@ DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
static inline struct mmu_gather *
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
{
struct mmu_gather *tlb = &per_cpu(mmu_gathers, smp_processor_id());
struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
tlb->mm = mm;
@@ -65,7 +62,6 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
tlb->nr = num_online_cpus() > 1 ? 0U : ~0U;
tlb->fullmm = full_mm_flush;
tlb->freed = 0;
return tlb;
}
@@ -85,28 +81,17 @@ tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
/* tlb_finish_mmu
* Called at the end of the shootdown operation to free up any resources
* that were required. The page table lock is still held at this point.
* that were required.
*/
static inline void
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
int freed = tlb->freed;
struct mm_struct *mm = tlb->mm;
int rss = get_mm_counter(mm, rss);
if (rss < freed)
freed = rss;
add_mm_counter(mm, rss, -freed);
tlb_flush_mmu(tlb, start, end);
/* keep the page table cache within bounds */
check_pgt_cache();
}
static inline unsigned int
tlb_is_full_mm(struct mmu_gather *tlb)
{
return tlb->fullmm;
put_cpu_var(mmu_gathers);
}
/* tlb_remove_page
include/asm-h8300/semaphore.h
-3
View File
@@ -35,9 +35,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-h8300/unistd.h
-1
View File
@@ -528,7 +528,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
asmlinkage int sys_execve(char *name, char **argv, char **envp,
int dummy, ...);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-i386/apic.h
+2 -1
View File
@@ -118,7 +118,8 @@ extern void release_lapic_nmi(void);
extern void disable_timer_nmi_watchdog(void);
extern void enable_timer_nmi_watchdog(void);
extern void nmi_watchdog_tick (struct pt_regs * regs);
extern int APIC_init_uniprocessor (void);
extern int APIC_init(void);
extern void APIC_late_time_init(void);
extern void disable_APIC_timer(void);
extern void enable_APIC_timer(void);
include/asm-i386/desc.h
+5 -3
View File
@@ -17,6 +17,8 @@
extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
DECLARE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
#define get_cpu_gdt_table(_cpu) (per_cpu(cpu_gdt_table,_cpu))
DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
struct Xgt_desc_struct {
@@ -60,7 +62,7 @@ __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr)
{
_set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[entry], (int)addr,
_set_tssldt_desc(&get_cpu_gdt_table(cpu)[entry], (int)addr,
offsetof(struct tss_struct, __cacheline_filler) - 1, 0x89);
}
@@ -68,7 +70,7 @@ static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *ad
static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size)
{
_set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
_set_tssldt_desc(&get_cpu_gdt_table(cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
}
#define LDT_entry_a(info) \
@@ -109,7 +111,7 @@ static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 en
static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
{
#define C(i) per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
#define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
C(0); C(1); C(2);
#undef C
}
include/asm-i386/hw_irq.h
+1
View File
@@ -55,6 +55,7 @@ void init_8259A(int aeoi);
void FASTCALL(send_IPI_self(int vector));
void init_VISWS_APIC_irqs(void);
void setup_IO_APIC(void);
void IO_APIC_late_time_init(void);
void disable_IO_APIC(void);
void print_IO_APIC(void);
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
include/asm-i386/mach-default/smpboot_hooks.h
-15
View File
@@ -1,11 +1,6 @@
/* two abstractions specific to kernel/smpboot.c, mainly to cater to visws
* which needs to alter them. */
static inline void smpboot_clear_io_apic_irqs(void)
{
io_apic_irqs = 0;
}
static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
{
CMOS_WRITE(0xa, 0xf);
@@ -32,13 +27,3 @@ static inline void smpboot_restore_warm_reset_vector(void)
*((volatile long *) phys_to_virt(0x467)) = 0;
}
static inline void smpboot_setup_io_apic(void)
{
/*
* Here we can be sure that there is an IO-APIC in the system. Let's
* go and set it up:
*/
if (!skip_ioapic_setup && nr_ioapics)
setup_IO_APIC();
}
include/asm-i386/mach-es7000/mach_mpparse.h
+1 -1
View File
@@ -16,7 +16,7 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
extern int parse_unisys_oem (char *oemptr);
extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
extern void setup_unisys();
extern void setup_unisys(void);
static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
char *productid)
include/asm-i386/mach-summit/mach_mpparse.h
-3
View File
@@ -22,7 +22,6 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
{
}
extern int usb_early_handoff;
static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
char *productid)
{
@@ -32,7 +31,6 @@ static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
|| !strncmp(productid, "RUTHLESS SMP", 12))){
use_cyclone = 1; /*enable cyclone-timer*/
setup_summit();
usb_early_handoff = 1;
return 1;
}
return 0;
@@ -46,7 +44,6 @@ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
|| !strncmp(oem_table_id, "EXA", 3))){
use_cyclone = 1; /*enable cyclone-timer*/
setup_summit();
usb_early_handoff = 1;
return 1;
}
return 0;
include/asm-i386/mach-visws/smpboot_hooks.h
-7
View File
@@ -11,14 +11,7 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
/* for visws do nothing for any of these */
static inline void smpboot_clear_io_apic_irqs(void)
{
}
static inline void smpboot_restore_warm_reset_vector(void)
{
}
static inline void smpboot_setup_io_apic(void)
{
}

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