Merge f6cef5f8c3 ("Merge tag 'i3c/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux") into android-mainline
Steps on the way to v6.9-rc1 Signed-off-by: Lee Jones <joneslee@google.com> Change-Id: Ia7e24ee9441885d18475aa4ffc3a3cbd77f7fd4b
This commit is contained in:
Lee Jones
@@ -33,3 +33,37 @@ Description:
|
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device cannot clear poison from the address, -ENXIO is returned.
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The clear_poison attribute is only visible for devices
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supporting the capability.
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What: /sys/kernel/debug/cxl/einj_types
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Date: January, 2024
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KernelVersion: v6.9
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) Prints the CXL protocol error types made available by
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the platform in the format:
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0x<error number> <error type>
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The possible error types are (as of ACPI v6.5):
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0x1000 CXL.cache Protocol Correctable
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0x2000 CXL.cache Protocol Uncorrectable non-fatal
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0x4000 CXL.cache Protocol Uncorrectable fatal
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0x8000 CXL.mem Protocol Correctable
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0x10000 CXL.mem Protocol Uncorrectable non-fatal
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0x20000 CXL.mem Protocol Uncorrectable fatal
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The <error number> can be written to einj_inject to inject
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<error type> into a chosen dport.
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What: /sys/kernel/debug/cxl/$dport_dev/einj_inject
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Date: January, 2024
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KernelVersion: v6.9
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) Writing an integer to this file injects the corresponding
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CXL protocol error into $dport_dev ($dport_dev will be a device
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name from /sys/bus/pci/devices). The integer to type mapping for
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injection can be found by reading from einj_types. If the dport
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was enumerated in RCH mode, a CXL 1.1 error is injected, otherwise
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a CXL 2.0 error is injected.
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@@ -81,3 +81,29 @@ Description: (RO) Read returns, for each Acceleration Engine (AE), the number
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<N>: Number of Compress and Verify (CnV) errors and type
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of the last CnV error detected by Acceleration
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Engine N.
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What: /sys/kernel/debug/qat_<device>_<BDF>/heartbeat/inject_error
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Date: March 2024
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KernelVersion: 6.8
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Contact: qat-linux@intel.com
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Description: (WO) Write to inject an error that simulates an heartbeat
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failure. This is to be used for testing purposes.
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After writing this file, the driver stops arbitration on a
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random engine and disables the fetching of heartbeat counters.
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If a workload is running on the device, a job submitted to the
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accelerator might not get a response and a read of the
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`heartbeat/status` attribute might report -1, i.e. device
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unresponsive.
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The error is unrecoverable thus the device must be restarted to
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restore its functionality.
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This attribute is available only when the kernel is built with
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CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION=y.
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A write of 1 enables error injection.
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The following example shows how to enable error injection::
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# cd /sys/kernel/debug/qat_<device>_<BDF>
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# echo 1 > heartbeat/inject_error
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@@ -111,6 +111,28 @@ Description: QM debug registers(regs) read hardware register value. This
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node is used to show the change of the qm register values. This
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node can be help users to check the change of register values.
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What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/qm_state
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Date: Jan 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Dump the state of the device.
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0: busy, 1: idle.
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Only available for PF, and take no other effect on HPRE.
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What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/dev_timeout
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Date: Feb 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Set the wait time when stop queue fails. Available for both PF
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and VF, and take no other effect on HPRE.
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0: not wait(default), others value: wait dev_timeout * 20 microsecond.
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What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/dev_state
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Date: Feb 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Dump the stop queue status of the QM. The default value is 0,
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if dev_timeout is set, when stop queue fails, the dev_state
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will return non-zero value. Available for both PF and VF,
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and take no other effect on HPRE.
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What: /sys/kernel/debug/hisi_hpre/<bdf>/hpre_dfx/diff_regs
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Date: Mar 2022
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Contact: linux-crypto@vger.kernel.org
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@@ -91,6 +91,28 @@ Description: QM debug registers(regs) read hardware register value. This
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node is used to show the change of the qm register values. This
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node can be help users to check the change of register values.
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What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/qm_state
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Date: Jan 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Dump the state of the device.
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0: busy, 1: idle.
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Only available for PF, and take no other effect on SEC.
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What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/dev_timeout
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Date: Feb 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Set the wait time when stop queue fails. Available for both PF
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and VF, and take no other effect on SEC.
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0: not wait(default), others value: wait dev_timeout * 20 microsecond.
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What: /sys/kernel/debug/hisi_sec2/<bdf>/qm/dev_state
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Date: Feb 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Dump the stop queue status of the QM. The default value is 0,
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if dev_timeout is set, when stop queue fails, the dev_state
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will return non-zero value. Available for both PF and VF,
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and take no other effect on SEC.
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What: /sys/kernel/debug/hisi_sec2/<bdf>/sec_dfx/diff_regs
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Date: Mar 2022
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Contact: linux-crypto@vger.kernel.org
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@@ -104,6 +104,28 @@ Description: QM debug registers(regs) read hardware register value. This
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node is used to show the change of the qm registers value. This
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node can be help users to check the change of register values.
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/qm_state
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Date: Jan 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Dump the state of the device.
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0: busy, 1: idle.
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Only available for PF, and take no other effect on ZIP.
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/dev_timeout
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Date: Feb 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Set the wait time when stop queue fails. Available for both PF
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and VF, and take no other effect on ZIP.
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0: not wait(default), others value: wait dev_timeout * 20 microsecond.
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/dev_state
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Date: Feb 2024
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Contact: linux-crypto@vger.kernel.org
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Description: Dump the stop queue status of the QM. The default value is 0,
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if dev_timeout is set, when stop queue fails, the dev_state
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will return non-zero value. Available for both PF and VF,
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and take no other effect on ZIP.
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What: /sys/kernel/debug/hisi_zip/<bdf>/zip_dfx/diff_regs
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Date: Mar 2022
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Contact: linux-crypto@vger.kernel.org
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@@ -552,3 +552,37 @@ Description:
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attribute is only visible for devices supporting the
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capability. The retrieved errors are logged as kernel
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events when cxl_poison event tracing is enabled.
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What: /sys/bus/cxl/devices/regionZ/accessY/read_bandwidth
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/sys/bus/cxl/devices/regionZ/accessY/write_banwidth
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Date: Jan, 2024
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KernelVersion: v6.9
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The aggregated read or write bandwidth of the region. The
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number is the accumulated read or write bandwidth of all CXL memory
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devices that contributes to the region in MB/s. It is
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identical data that should appear in
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/sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth or
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/sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth.
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See Documentation/ABI/stable/sysfs-devices-node. access0 provides
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the number to the closest initiator and access1 provides the
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number to the closest CPU.
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What: /sys/bus/cxl/devices/regionZ/accessY/read_latency
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/sys/bus/cxl/devices/regionZ/accessY/write_latency
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Date: Jan, 2024
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KernelVersion: v6.9
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The read or write latency of the region. The number is
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the worst read or write latency of all CXL memory devices that
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contributes to the region in nanoseconds. It is identical data
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that should appear in
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/sys/devices/system/node/nodeX/accessY/initiators/read_latency or
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/sys/devices/system/node/nodeX/accessY/initiators/write_latency.
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See Documentation/ABI/stable/sysfs-devices-node. access0 provides
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the number to the closest initiator and access1 provides the
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number to the closest CPU.
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@@ -141,3 +141,23 @@ Description:
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64
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This attribute is only available for qat_4xxx devices.
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What: /sys/bus/pci/devices/<BDF>/qat/auto_reset
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Date: March 2024
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KernelVersion: 6.8
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Contact: qat-linux@intel.com
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Description: (RW) Reports the current state of the autoreset feature
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for a QAT device
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Write to the attribute to enable or disable device auto reset.
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Device auto reset is disabled by default.
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The values are:
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* 1/Yy/on: auto reset enabled. If the device encounters an
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unrecoverable error, it will be reset automatically.
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* 0/Nn/off: auto reset disabled. If the device encounters an
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unrecoverable error, it will not be reset.
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This attribute is only available for qat_4xxx devices.
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@@ -64,9 +64,6 @@ override DTC_FLAGS := \
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-Wno-unique_unit_address \
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-Wunique_unit_address_if_enabled
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# Disable undocumented compatible checks until warning free
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override DT_CHECKER_FLAGS ?=
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$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
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$(call if_changed_rule,chkdt)
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@@ -6,18 +6,6 @@ berlin SoCs are now Synaptics' SoCs now.
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---------------------------------------------------------------
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Work in progress statement:
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Device tree files and bindings applying to Marvell Berlin SoCs and boards are
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considered "unstable". Any Marvell Berlin device tree binding may change at any
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time. Be sure to use a device tree binary and a kernel image generated from the
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same source tree.
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Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
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stable binding/ABI.
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---------------------------------------------------------------
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Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
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shall have the following properties:
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@@ -12,7 +12,11 @@ maintainers:
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properties:
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compatible:
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const: atmel,at91sam9g46-aes
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oneOf:
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- const: atmel,at91sam9g46-aes
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- items:
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- const: microchip,sam9x7-aes
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- const: atmel,at91sam9g46-aes
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||||
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||||
reg:
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maxItems: 1
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||||
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@@ -12,7 +12,11 @@ maintainers:
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||||
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properties:
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compatible:
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const: atmel,at91sam9g46-sha
|
||||
oneOf:
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||||
- const: atmel,at91sam9g46-sha
|
||||
- items:
|
||||
- const: microchip,sam9x7-sha
|
||||
- const: atmel,at91sam9g46-sha
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -12,7 +12,11 @@ maintainers:
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||||
|
||||
properties:
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||||
compatible:
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const: atmel,at91sam9g46-tdes
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oneOf:
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- const: atmel,at91sam9g46-tdes
|
||||
- items:
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||||
- const: microchip,sam9x7-tdes
|
||||
- const: atmel,at91sam9g46-tdes
|
||||
|
||||
reg:
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||||
maxItems: 1
|
||||
|
||||
@@ -14,6 +14,7 @@ properties:
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||||
items:
|
||||
- enum:
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||||
- qcom,sa8775p-inline-crypto-engine
|
||||
- qcom,sc7180-inline-crypto-engine
|
||||
- qcom,sm8450-inline-crypto-engine
|
||||
- qcom,sm8550-inline-crypto-engine
|
||||
- qcom,sm8650-inline-crypto-engine
|
||||
|
||||
@@ -45,6 +45,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-qce
|
||||
- qcom,sm6350-qce
|
||||
- qcom,sm8250-qce
|
||||
- qcom,sm8350-qce
|
||||
- qcom,sm8450-qce
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel's High LCD Controller (HLCDC)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
||||
|
||||
description:
|
||||
The LCD Controller (LCDC) consists of logic for transferring LCD image
|
||||
data from an external display buffer to a TFT LCD panel. The LCDC has one
|
||||
display input buffer per layer that fetches pixels through the single bus
|
||||
host interface and a look-up table to allow palletized display
|
||||
configurations.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,hlcdc-display-controller
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/$defs/port-base
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Output endpoint of the controller, connecting the LCD panel signals.
|
||||
|
||||
properties:
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Endpoint connecting the LCD panel signals.
|
||||
|
||||
properties:
|
||||
bus-width:
|
||||
enum: [ 12, 16, 18, 24 ]
|
||||
|
||||
required:
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- compatible
|
||||
- port@0
|
||||
|
||||
additionalProperties: false
|
||||
@@ -1,75 +0,0 @@
|
||||
Device-Tree bindings for Atmel's HLCDC (High LCD Controller) DRM driver
|
||||
|
||||
The Atmel HLCDC Display Controller is subdevice of the HLCDC MFD device.
|
||||
See ../../mfd/atmel-hlcdc.txt for more details.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "atmel,hlcdc-display-controller"
|
||||
- pinctrl-names: the pin control state names. Should contain "default".
|
||||
- pinctrl-0: should contain the default pinctrl states.
|
||||
- #address-cells: should be set to 1.
|
||||
- #size-cells: should be set to 0.
|
||||
|
||||
Required children nodes:
|
||||
Children nodes are encoding available output ports and their connections
|
||||
to external devices using the OF graph representation (see ../graph.txt).
|
||||
At least one port node is required.
|
||||
|
||||
Optional properties in grandchild nodes:
|
||||
Any endpoint grandchild node may specify a desired video interface
|
||||
according to ../../media/video-interfaces.txt, specifically
|
||||
- bus-width: recognized values are <12>, <16>, <18> and <24>, and
|
||||
override any output mode selection heuristic, forcing "rgb444",
|
||||
"rgb565", "rgb666" and "rgb888" respectively.
|
||||
|
||||
Example:
|
||||
|
||||
hlcdc: hlcdc@f0030000 {
|
||||
compatible = "atmel,sama5d3-hlcdc";
|
||||
reg = <0xf0030000 0x2000>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
|
||||
clock-names = "periph_clk","sys_clk", "slow_clk";
|
||||
|
||||
hlcdc-display-controller {
|
||||
compatible = "atmel,hlcdc-display-controller";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
hlcdc_panel_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hlcdc_pwm: hlcdc-pwm {
|
||||
compatible = "atmel,hlcdc-pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd_pwm>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
Example 2: With a video interface override to force rgb565; as above
|
||||
but with these changes/additions:
|
||||
|
||||
&hlcdc {
|
||||
hlcdc-display-controller {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
|
||||
|
||||
port@0 {
|
||||
hlcdc_panel_output: endpoint@0 {
|
||||
bus-width = <16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -120,13 +120,19 @@ allOf:
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6sx-lcdif
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx6sl-lcdif
|
||||
- fsl,imx6sx-lcdif
|
||||
- fsl,imx8mm-lcdif
|
||||
- fsl,imx8mn-lcdif
|
||||
- fsl,imx8mp-lcdif
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/visionox,r66451.yaml#
|
||||
|
||||
@@ -92,7 +92,8 @@ properties:
|
||||
description: needs firmware more than ver 2
|
||||
- Shared ASRC: 23
|
||||
- SAI: 24
|
||||
- HDMI Audio: 25
|
||||
- Multi SAI: 25
|
||||
- HDMI Audio: 26
|
||||
|
||||
The third cell: transfer priority ID
|
||||
enum:
|
||||
|
||||
@@ -1,479 +0,0 @@
|
||||
FPGA Region Device Tree Binding
|
||||
|
||||
Alan Tull 2016
|
||||
|
||||
CONTENTS
|
||||
- Introduction
|
||||
- Terminology
|
||||
- Sequence
|
||||
- FPGA Region
|
||||
- Supported Use Models
|
||||
- Device Tree Examples
|
||||
- Constraints
|
||||
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
|
||||
the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
|
||||
control.
|
||||
|
||||
This device tree binding document hits some of the high points of FPGA usage and
|
||||
attempts to include terminology used by both major FPGA manufacturers. This
|
||||
document isn't a replacement for any manufacturers specifications for FPGA
|
||||
usage.
|
||||
|
||||
|
||||
Terminology
|
||||
===========
|
||||
|
||||
Full Reconfiguration
|
||||
* The entire FPGA is programmed.
|
||||
|
||||
Partial Reconfiguration (PR)
|
||||
* A section of an FPGA is reprogrammed while the rest of the FPGA is not
|
||||
affected.
|
||||
* Not all FPGA's support PR.
|
||||
|
||||
Partial Reconfiguration Region (PRR)
|
||||
* Also called a "reconfigurable partition"
|
||||
* A PRR is a specific section of an FPGA reserved for reconfiguration.
|
||||
* A base (or static) FPGA image may create a set of PRR's that later may
|
||||
be independently reprogrammed many times.
|
||||
* The size and specific location of each PRR is fixed.
|
||||
* The connections at the edge of each PRR are fixed. The image that is loaded
|
||||
into a PRR must fit and must use a subset of the region's connections.
|
||||
* The busses within the FPGA are split such that each region gets its own
|
||||
branch that may be gated independently.
|
||||
|
||||
Persona
|
||||
* Also called a "partial bit stream"
|
||||
* An FPGA image that is designed to be loaded into a PRR. There may be
|
||||
any number of personas designed to fit into a PRR, but only one at at time
|
||||
may be loaded.
|
||||
* A persona may create more regions.
|
||||
|
||||
FPGA Bridge
|
||||
* FPGA Bridges gate bus signals between a host and FPGA.
|
||||
* FPGA Bridges should be disabled while the FPGA is being programmed to
|
||||
prevent spurious signals on the cpu bus and to the soft logic.
|
||||
* FPGA bridges may be actual hardware or soft logic on an FPGA.
|
||||
* During Full Reconfiguration, hardware bridges between the host and FPGA
|
||||
will be disabled.
|
||||
* During Partial Reconfiguration of a specific region, that region's bridge
|
||||
will be used to gate the busses. Traffic to other regions is not affected.
|
||||
* In some implementations, the FPGA Manager transparently handles gating the
|
||||
buses, eliminating the need to show the hardware FPGA bridges in the
|
||||
device tree.
|
||||
* An FPGA image may create a set of reprogrammable regions, each having its
|
||||
own bridge and its own split of the busses in the FPGA.
|
||||
|
||||
FPGA Manager
|
||||
* An FPGA Manager is a hardware block that programs an FPGA under the control
|
||||
of a host processor.
|
||||
|
||||
Base Image
|
||||
* Also called the "static image"
|
||||
* An FPGA image that is designed to do full reconfiguration of the FPGA.
|
||||
* A base image may set up a set of partial reconfiguration regions that may
|
||||
later be reprogrammed.
|
||||
|
||||
---------------- ----------------------------------
|
||||
| Host CPU | | FPGA |
|
||||
| | | |
|
||||
| ----| | ----------- -------- |
|
||||
| | H | | |==>| Bridge0 |<==>| PRR0 | |
|
||||
| | W | | | ----------- -------- |
|
||||
| | | | | |
|
||||
| | B |<=====>|<==| ----------- -------- |
|
||||
| | R | | |==>| Bridge1 |<==>| PRR1 | |
|
||||
| | I | | | ----------- -------- |
|
||||
| | D | | | |
|
||||
| | G | | | ----------- -------- |
|
||||
| | E | | |==>| Bridge2 |<==>| PRR2 | |
|
||||
| ----| | ----------- -------- |
|
||||
| | | |
|
||||
---------------- ----------------------------------
|
||||
|
||||
Figure 1: An FPGA set up with a base image that created three regions. Each
|
||||
region (PRR0-2) gets its own split of the busses that is independently gated by
|
||||
a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
|
||||
reprogrammed independently while the rest of the system continues to function.
|
||||
|
||||
|
||||
Sequence
|
||||
========
|
||||
|
||||
When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
|
||||
do the following:
|
||||
|
||||
1. Disable appropriate FPGA bridges.
|
||||
2. Program the FPGA using the FPGA manager.
|
||||
3. Enable the FPGA bridges.
|
||||
4. The Device Tree overlay is accepted into the live tree.
|
||||
5. Child devices are populated.
|
||||
|
||||
When the overlay is removed, the child nodes will be removed and the FPGA Region
|
||||
will disable the bridges.
|
||||
|
||||
|
||||
FPGA Region
|
||||
===========
|
||||
|
||||
FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
|
||||
Region brings together the elements needed to program on a running system and
|
||||
add the child devices:
|
||||
|
||||
* FPGA Manager
|
||||
* FPGA Bridges
|
||||
* image-specific information needed to to the programming.
|
||||
* child nodes
|
||||
|
||||
The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
|
||||
FPGA while an operating system is running.
|
||||
|
||||
An FPGA Region that exists in the live Device Tree reflects the current state.
|
||||
If the live tree shows a "firmware-name" property or child nodes under an FPGA
|
||||
Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
|
||||
and adds the "firmware-name" property is taken as a request to reprogram the
|
||||
FPGA. After reprogramming is successful, the overlay is accepted into the live
|
||||
tree.
|
||||
|
||||
The base FPGA Region in the device tree represents the FPGA and supports full
|
||||
reconfiguration. It must include a phandle to an FPGA Manager. The base
|
||||
FPGA region will be the child of one of the hardware bridges (the bridge that
|
||||
allows register access) between the cpu and the FPGA. If there are more than
|
||||
one bridge to control during FPGA programming, the region will also contain a
|
||||
list of phandles to the additional hardware FPGA Bridges.
|
||||
|
||||
For partial reconfiguration (PR), each PR region will have an FPGA Region.
|
||||
These FPGA regions are children of FPGA bridges which are then children of the
|
||||
base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
|
||||
this.
|
||||
|
||||
If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
|
||||
Manager specified by its ancestor FPGA Region. This supports both the case
|
||||
where the same FPGA Manager is used for all of an FPGA as well the case where
|
||||
a different FPGA Manager is used for each region.
|
||||
|
||||
FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
|
||||
shutting down bridges that are upstream from the other active regions while one
|
||||
region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
|
||||
hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
|
||||
within the static image of the FPGA.
|
||||
|
||||
Required properties:
|
||||
- compatible : should contain "fpga-region"
|
||||
- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
|
||||
inherit this property from their ancestor regions. An fpga-mgr property
|
||||
in a region will override any inherited FPGA manager.
|
||||
- #address-cells, #size-cells, ranges : must be present to handle address space
|
||||
mapping for child nodes.
|
||||
|
||||
Optional properties:
|
||||
- firmware-name : should contain the name of an FPGA image file located on the
|
||||
firmware search path. If this property shows up in a live device tree
|
||||
it indicates that the FPGA has already been programmed with this image.
|
||||
If this property is in an overlay targeting an FPGA region, it is a
|
||||
request to program the FPGA with that image.
|
||||
- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
|
||||
controlled during FPGA programming along with the parent FPGA bridge.
|
||||
This property is optional if the FPGA Manager handles the bridges.
|
||||
If the fpga-region is the child of an fpga-bridge, the list should not
|
||||
contain the parent bridge.
|
||||
- partial-fpga-config : boolean, set if partial reconfiguration is to be done,
|
||||
otherwise full reconfiguration is done.
|
||||
- external-fpga-config : boolean, set if the FPGA has already been configured
|
||||
prior to OS boot up.
|
||||
- encrypted-fpga-config : boolean, set if the bitstream is encrypted
|
||||
- region-unfreeze-timeout-us : The maximum time in microseconds to wait for
|
||||
bridges to successfully become enabled after the region has been
|
||||
programmed.
|
||||
- region-freeze-timeout-us : The maximum time in microseconds to wait for
|
||||
bridges to successfully become disabled before the region has been
|
||||
programmed.
|
||||
- config-complete-timeout-us : The maximum time in microseconds time for the
|
||||
FPGA to go to operating mode after the region has been programmed.
|
||||
- child nodes : devices in the FPGA after programming.
|
||||
|
||||
In the example below, when an overlay is applied targeting fpga-region0,
|
||||
fpga_mgr is used to program the FPGA. Two bridges are controlled during
|
||||
programming: the parent fpga_bridge0 and fpga_bridge1. Because the region is
|
||||
the child of fpga_bridge0, only fpga_bridge1 needs to be specified in the
|
||||
fpga-bridges property. During programming, these bridges are disabled, the
|
||||
firmware specified in the overlay is loaded to the FPGA using the FPGA manager
|
||||
specified in the region. If FPGA programming succeeds, the bridges are
|
||||
reenabled and the overlay makes it into the live device tree. The child devices
|
||||
are then populated. If FPGA programming fails, the bridges are left disabled
|
||||
and the overlay is rejected. The overlay's ranges property maps the lwhps
|
||||
bridge's region (0xff200000) and the hps bridge's region (0xc0000000) for use by
|
||||
the two child devices.
|
||||
|
||||
Example:
|
||||
Base tree contains:
|
||||
|
||||
fpga_mgr: fpga-mgr@ff706000 {
|
||||
compatible = "altr,socfpga-fpga-mgr";
|
||||
reg = <0xff706000 0x1000
|
||||
0xffb90000 0x20>;
|
||||
interrupts = <0 175 4>;
|
||||
};
|
||||
|
||||
fpga_bridge0: fpga-bridge@ff400000 {
|
||||
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
||||
reg = <0xff400000 0x100000>;
|
||||
resets = <&rst LWHPS2FPGA_RESET>;
|
||||
clocks = <&l4_main_clk>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
fpga_region0: fpga-region0 {
|
||||
compatible = "fpga-region";
|
||||
fpga-mgr = <&fpga_mgr>;
|
||||
};
|
||||
};
|
||||
|
||||
fpga_bridge1: fpga-bridge@ff500000 {
|
||||
compatible = "altr,socfpga-hps2fpga-bridge";
|
||||
reg = <0xff500000 0x10000>;
|
||||
resets = <&rst HPS2FPGA_RESET>;
|
||||
clocks = <&l4_main_clk>;
|
||||
};
|
||||
|
||||
Overlay contains:
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&fpga_region0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
firmware-name = "soc_system.rbf";
|
||||
fpga-bridges = <&fpga_bridge1>;
|
||||
ranges = <0x20000 0xff200000 0x100000>,
|
||||
<0x0 0xc0000000 0x20000000>;
|
||||
|
||||
gpio@10040 {
|
||||
compatible = "altr,pio-1.0";
|
||||
reg = <0x10040 0x20>;
|
||||
altr,ngpio = <4>;
|
||||
#gpio-cells = <2>;
|
||||
clocks = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
onchip-memory {
|
||||
device_type = "memory";
|
||||
compatible = "altr,onchipmem-15.1";
|
||||
reg = <0x0 0x10000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Supported Use Models
|
||||
====================
|
||||
|
||||
In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
|
||||
a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
|
||||
uses are specific to an FPGA device.
|
||||
|
||||
* No FPGA Bridges
|
||||
In this case, the FPGA Manager which programs the FPGA also handles the
|
||||
bridges behind the scenes. No FPGA Bridge devices are needed for full
|
||||
reconfiguration.
|
||||
|
||||
* Full reconfiguration with hardware bridges
|
||||
In this case, there are hardware bridges between the processor and FPGA that
|
||||
need to be controlled during full reconfiguration. Before the overlay is
|
||||
applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
|
||||
FPGA Region. The FPGA Region is the child of the bridge that allows
|
||||
register access to the FPGA. Additional bridges may be listed in a
|
||||
fpga-bridges property in the FPGA region or in the device tree overlay.
|
||||
|
||||
* Partial reconfiguration with bridges in the FPGA
|
||||
In this case, the FPGA will have one or more PRR's that may be programmed
|
||||
separately while the rest of the FPGA can remain active. To manage this,
|
||||
bridges need to exist in the FPGA that can gate the buses going to each FPGA
|
||||
region while the buses are enabled for other sections. Before any partial
|
||||
reconfiguration can be done, a base FPGA image must be loaded which includes
|
||||
PRR's with FPGA bridges. The device tree should have an FPGA region for each
|
||||
PRR.
|
||||
|
||||
Device Tree Examples
|
||||
====================
|
||||
|
||||
The intention of this section is to give some simple examples, focusing on
|
||||
the placement of the elements detailed above, especially:
|
||||
* FPGA Manager
|
||||
* FPGA Bridges
|
||||
* FPGA Region
|
||||
* ranges
|
||||
* target-path or target
|
||||
|
||||
For the purposes of this section, I'm dividing the Device Tree into two parts,
|
||||
each with its own requirements. The two parts are:
|
||||
* The live DT prior to the overlay being added
|
||||
* The DT overlay
|
||||
|
||||
The live Device Tree must contain an FPGA Region, an FPGA Manager, and any FPGA
|
||||
Bridges. The FPGA Region's "fpga-mgr" property specifies the manager by phandle
|
||||
to handle programming the FPGA. If the FPGA Region is the child of another FPGA
|
||||
Region, the parent's FPGA Manager is used. If FPGA Bridges need to be involved,
|
||||
they are specified in the FPGA Region by the "fpga-bridges" property. During
|
||||
FPGA programming, the FPGA Region will disable the bridges that are in its
|
||||
"fpga-bridges" list and will re-enable them after FPGA programming has
|
||||
succeeded.
|
||||
|
||||
The Device Tree Overlay will contain:
|
||||
* "target-path" or "target"
|
||||
The insertion point where the contents of the overlay will go into the
|
||||
live tree. target-path is a full path, while target is a phandle.
|
||||
* "ranges"
|
||||
The address space mapping from processor to FPGA bus(ses).
|
||||
* "firmware-name"
|
||||
Specifies the name of the FPGA image file on the firmware search
|
||||
path. The search path is described in the firmware class documentation.
|
||||
* "partial-fpga-config"
|
||||
This binding is a boolean and should be present if partial reconfiguration
|
||||
is to be done.
|
||||
* child nodes corresponding to hardware that will be loaded in this region of
|
||||
the FPGA.
|
||||
|
||||
Device Tree Example: Full Reconfiguration without Bridges
|
||||
=========================================================
|
||||
|
||||
Live Device Tree contains:
|
||||
fpga_mgr0: fpga-mgr@f8007000 {
|
||||
compatible = "xlnx,zynq-devcfg-1.0";
|
||||
reg = <0xf8007000 0x100>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 8 4>;
|
||||
clocks = <&clkc 12>;
|
||||
clock-names = "ref_clk";
|
||||
syscon = <&slcr>;
|
||||
};
|
||||
|
||||
fpga_region0: fpga-region0 {
|
||||
compatible = "fpga-region";
|
||||
fpga-mgr = <&fpga_mgr0>;
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
ranges;
|
||||
};
|
||||
|
||||
DT Overlay contains:
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&fpga_region0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
firmware-name = "zynq-gpio.bin";
|
||||
|
||||
gpio1: gpio@40000000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = <0x40000000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
xlnx,gpio-width= <0x6>;
|
||||
};
|
||||
};
|
||||
|
||||
Device Tree Example: Full Reconfiguration to add PRR's
|
||||
======================================================
|
||||
|
||||
The base FPGA Region is specified similar to the first example above.
|
||||
|
||||
This example programs the FPGA to have two regions that can later be partially
|
||||
configured. Each region has its own bridge in the FPGA fabric.
|
||||
|
||||
DT Overlay contains:
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&fpga_region0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
firmware-name = "base.rbf";
|
||||
|
||||
fpga-bridge@4400 {
|
||||
compatible = "altr,freeze-bridge-controller";
|
||||
reg = <0x4400 0x10>;
|
||||
|
||||
fpga_region1: fpga-region1 {
|
||||
compatible = "fpga-region";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
fpga-bridge@4420 {
|
||||
compatible = "altr,freeze-bridge-controller";
|
||||
reg = <0x4420 0x10>;
|
||||
|
||||
fpga_region2: fpga-region2 {
|
||||
compatible = "fpga-region";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Device Tree Example: Partial Reconfiguration
|
||||
============================================
|
||||
|
||||
This example reprograms one of the PRR's set up in the previous example.
|
||||
|
||||
The sequence that occurs when this overlay is similar to the above, the only
|
||||
differences are that the FPGA is partially reconfigured due to the
|
||||
"partial-fpga-config" boolean and the only bridge that is controlled during
|
||||
programming is the FPGA based bridge of fpga_region1.
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&fpga_region1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
firmware-name = "soc_image2.rbf";
|
||||
partial-fpga-config;
|
||||
|
||||
gpio@10040 {
|
||||
compatible = "altr,pio-1.0";
|
||||
reg = <0x10040 0x20>;
|
||||
clocks = <0x2>;
|
||||
altr,ngpio = <0x4>;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-controller;
|
||||
};
|
||||
};
|
||||
|
||||
Constraints
|
||||
===========
|
||||
|
||||
It is beyond the scope of this document to fully describe all the FPGA design
|
||||
constraints required to make partial reconfiguration work[1] [2] [3], but a few
|
||||
deserve quick mention.
|
||||
|
||||
A persona must have boundary connections that line up with those of the partition
|
||||
or region it is designed to go into.
|
||||
|
||||
During programming, transactions through those connections must be stopped and
|
||||
the connections must be held at a fixed logic level. This can be achieved by
|
||||
FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
|
||||
|
||||
--
|
||||
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
|
||||
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
|
||||
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
|
||||
@@ -0,0 +1,358 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: FPGA Region
|
||||
|
||||
maintainers:
|
||||
- Michal Simek <michal.simek@amd.com>
|
||||
|
||||
description: |
|
||||
CONTENTS
|
||||
- Introduction
|
||||
- Terminology
|
||||
- Sequence
|
||||
- FPGA Region
|
||||
- Supported Use Models
|
||||
- Constraints
|
||||
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
|
||||
the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
|
||||
control.
|
||||
|
||||
The documentation hits some of the high points of FPGA usage and
|
||||
attempts to include terminology used by both major FPGA manufacturers. This
|
||||
document isn't a replacement for any manufacturers specifications for FPGA
|
||||
usage.
|
||||
|
||||
|
||||
Terminology
|
||||
===========
|
||||
|
||||
Full Reconfiguration
|
||||
* The entire FPGA is programmed.
|
||||
|
||||
Partial Reconfiguration (PR)
|
||||
* A section of an FPGA is reprogrammed while the rest of the FPGA is not
|
||||
affected.
|
||||
* Not all FPGA's support PR.
|
||||
|
||||
Partial Reconfiguration Region (PRR)
|
||||
* Also called a "reconfigurable partition"
|
||||
* A PRR is a specific section of an FPGA reserved for reconfiguration.
|
||||
* A base (or static) FPGA image may create a set of PRR's that later may
|
||||
be independently reprogrammed many times.
|
||||
* The size and specific location of each PRR is fixed.
|
||||
* The connections at the edge of each PRR are fixed. The image that is loaded
|
||||
into a PRR must fit and must use a subset of the region's connections.
|
||||
* The busses within the FPGA are split such that each region gets its own
|
||||
branch that may be gated independently.
|
||||
|
||||
Persona
|
||||
* Also called a "partial bit stream"
|
||||
* An FPGA image that is designed to be loaded into a PRR. There may be
|
||||
any number of personas designed to fit into a PRR, but only one at a time
|
||||
may be loaded.
|
||||
* A persona may create more regions.
|
||||
|
||||
FPGA Bridge
|
||||
* FPGA Bridges gate bus signals between a host and FPGA.
|
||||
* FPGA Bridges should be disabled while the FPGA is being programmed to
|
||||
prevent spurious signals on the cpu bus and to the soft logic.
|
||||
* FPGA bridges may be actual hardware or soft logic on an FPGA.
|
||||
* During Full Reconfiguration, hardware bridges between the host and FPGA
|
||||
will be disabled.
|
||||
* During Partial Reconfiguration of a specific region, that region's bridge
|
||||
will be used to gate the busses. Traffic to other regions is not affected.
|
||||
* In some implementations, the FPGA Manager transparently handles gating the
|
||||
buses, eliminating the need to show the hardware FPGA bridges in the
|
||||
device tree.
|
||||
* An FPGA image may create a set of reprogrammable regions, each having its
|
||||
own bridge and its own split of the busses in the FPGA.
|
||||
|
||||
FPGA Manager
|
||||
* An FPGA Manager is a hardware block that programs an FPGA under the control
|
||||
of a host processor.
|
||||
|
||||
Base Image
|
||||
* Also called the "static image"
|
||||
* An FPGA image that is designed to do full reconfiguration of the FPGA.
|
||||
* A base image may set up a set of partial reconfiguration regions that may
|
||||
later be reprogrammed.
|
||||
|
||||
---------------- ----------------------------------
|
||||
| Host CPU | | FPGA |
|
||||
| | | |
|
||||
| ----| | ----------- -------- |
|
||||
| | H | | |==>| Bridge0 |<==>| PRR0 | |
|
||||
| | W | | | ----------- -------- |
|
||||
| | | | | |
|
||||
| | B |<=====>|<==| ----------- -------- |
|
||||
| | R | | |==>| Bridge1 |<==>| PRR1 | |
|
||||
| | I | | | ----------- -------- |
|
||||
| | D | | | |
|
||||
| | G | | | ----------- -------- |
|
||||
| | E | | |==>| Bridge2 |<==>| PRR2 | |
|
||||
| ----| | ----------- -------- |
|
||||
| | | |
|
||||
---------------- ----------------------------------
|
||||
|
||||
Figure 1: An FPGA set up with a base image that created three regions. Each
|
||||
region (PRR0-2) gets its own split of the busses that is independently gated by
|
||||
a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
|
||||
reprogrammed independently while the rest of the system continues to function.
|
||||
|
||||
|
||||
Sequence
|
||||
========
|
||||
|
||||
When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
|
||||
do the following:
|
||||
|
||||
1. Disable appropriate FPGA bridges.
|
||||
2. Program the FPGA using the FPGA manager.
|
||||
3. Enable the FPGA bridges.
|
||||
4. The Device Tree overlay is accepted into the live tree.
|
||||
5. Child devices are populated.
|
||||
|
||||
When the overlay is removed, the child nodes will be removed and the FPGA Region
|
||||
will disable the bridges.
|
||||
|
||||
|
||||
FPGA Region
|
||||
===========
|
||||
|
||||
FPGA Regions represent FPGA's and FPGA PR regions in the device tree. An FPGA
|
||||
Region brings together the elements needed to program on a running system and
|
||||
add the child devices:
|
||||
|
||||
* FPGA Manager
|
||||
* FPGA Bridges
|
||||
* image-specific information needed to the programming.
|
||||
* child nodes
|
||||
|
||||
The intended use is that a Device Tree overlay (DTO) can be used to reprogram an
|
||||
FPGA while an operating system is running.
|
||||
|
||||
An FPGA Region that exists in the live Device Tree reflects the current state.
|
||||
If the live tree shows a "firmware-name" property or child nodes under an FPGA
|
||||
Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
|
||||
and adds the "firmware-name" property is taken as a request to reprogram the
|
||||
FPGA. After reprogramming is successful, the overlay is accepted into the live
|
||||
tree.
|
||||
|
||||
The base FPGA Region in the device tree represents the FPGA and supports full
|
||||
reconfiguration. It must include a phandle to an FPGA Manager. The base
|
||||
FPGA region will be the child of one of the hardware bridges (the bridge that
|
||||
allows register access) between the cpu and the FPGA. If there are more than
|
||||
one bridge to control during FPGA programming, the region will also contain a
|
||||
list of phandles to the additional hardware FPGA Bridges.
|
||||
|
||||
For partial reconfiguration (PR), each PR region will have an FPGA Region.
|
||||
These FPGA regions are children of FPGA bridges which are then children of the
|
||||
base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
|
||||
this.
|
||||
|
||||
If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
|
||||
Manager specified by its ancestor FPGA Region. This supports both the case
|
||||
where the same FPGA Manager is used for all of an FPGA as well the case where
|
||||
a different FPGA Manager is used for each region.
|
||||
|
||||
FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
|
||||
shutting down bridges that are upstream from the other active regions while one
|
||||
region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
|
||||
hardware bridges remain enabled. The PR regions' bridges will be FPGA bridges
|
||||
within the static image of the FPGA.
|
||||
|
||||
|
||||
Supported Use Models
|
||||
====================
|
||||
|
||||
In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
|
||||
a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
|
||||
uses are specific to an FPGA device.
|
||||
|
||||
* No FPGA Bridges
|
||||
In this case, the FPGA Manager which programs the FPGA also handles the
|
||||
bridges behind the scenes. No FPGA Bridge devices are needed for full
|
||||
reconfiguration.
|
||||
|
||||
* Full reconfiguration with hardware bridges
|
||||
In this case, there are hardware bridges between the processor and FPGA that
|
||||
need to be controlled during full reconfiguration. Before the overlay is
|
||||
applied, the live DT must include the FPGA Manager, FPGA Bridges, and a
|
||||
FPGA Region. The FPGA Region is the child of the bridge that allows
|
||||
register access to the FPGA. Additional bridges may be listed in a
|
||||
fpga-bridges property in the FPGA region or in the device tree overlay.
|
||||
|
||||
* Partial reconfiguration with bridges in the FPGA
|
||||
In this case, the FPGA will have one or more PRR's that may be programmed
|
||||
separately while the rest of the FPGA can remain active. To manage this,
|
||||
bridges need to exist in the FPGA that can gate the buses going to each FPGA
|
||||
region while the buses are enabled for other sections. Before any partial
|
||||
reconfiguration can be done, a base FPGA image must be loaded which includes
|
||||
PRR's with FPGA bridges. The device tree should have an FPGA region for each
|
||||
PRR.
|
||||
|
||||
Constraints
|
||||
===========
|
||||
|
||||
It is beyond the scope of this document to fully describe all the FPGA design
|
||||
constraints required to make partial reconfiguration work[1] [2] [3], but a few
|
||||
deserve quick mention.
|
||||
|
||||
A persona must have boundary connections that line up with those of the partition
|
||||
or region it is designed to go into.
|
||||
|
||||
During programming, transactions through those connections must be stopped and
|
||||
the connections must be held at a fixed logic level. This can be achieved by
|
||||
FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration.
|
||||
|
||||
--
|
||||
[1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
|
||||
[2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf
|
||||
[3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
|
||||
|
||||
compatible:
|
||||
const: fpga-region
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
"#address-cells": true
|
||||
"#size-cells": true
|
||||
|
||||
config-complete-timeout-us:
|
||||
description:
|
||||
The maximum time in microseconds time for the FPGA to go to operating
|
||||
mode after the region has been programmed.
|
||||
|
||||
encrypted-fpga-config:
|
||||
type: boolean
|
||||
description:
|
||||
Set if the bitstream is encrypted.
|
||||
|
||||
external-fpga-config:
|
||||
type: boolean
|
||||
description:
|
||||
Set if the FPGA has already been configured prior to OS boot up.
|
||||
|
||||
firmware-name:
|
||||
maxItems: 1
|
||||
description:
|
||||
Should contain the name of an FPGA image file located on the firmware
|
||||
search path. If this property shows up in a live device tree it indicates
|
||||
that the FPGA has already been programmed with this image.
|
||||
If this property is in an overlay targeting an FPGA region, it is
|
||||
a request to program the FPGA with that image.
|
||||
|
||||
fpga-bridges:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should contain a list of phandles to FPGA Bridges that must be
|
||||
controlled during FPGA programming along with the parent FPGA bridge.
|
||||
This property is optional if the FPGA Manager handles the bridges.
|
||||
If the fpga-region is the child of an fpga-bridge, the list should not
|
||||
contain the parent bridge.
|
||||
|
||||
fpga-mgr:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Should contain a phandle to an FPGA Manager. Child FPGA Regions
|
||||
inherit this property from their ancestor regions. An fpga-mgr property
|
||||
in a region will override any inherited FPGA manager.
|
||||
|
||||
partial-fpga-config:
|
||||
type: boolean
|
||||
description:
|
||||
Set if partial reconfiguration is to be done, otherwise full
|
||||
reconfiguration is done.
|
||||
|
||||
region-freeze-timeout-us:
|
||||
description:
|
||||
The maximum time in microseconds to wait for bridges to successfully
|
||||
become disabled before the region has been programmed.
|
||||
|
||||
region-unfreeze-timeout-us:
|
||||
description:
|
||||
The maximum time in microseconds to wait for bridges to successfully
|
||||
become enabled after the region has been programmed.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- fpga-mgr
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
/*
|
||||
* Full Reconfiguration without Bridges with DT overlay
|
||||
*/
|
||||
fpga_region0: fpga-region@0 {
|
||||
compatible = "fpga-region";
|
||||
reg = <0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
fpga-mgr = <&fpga_mgr0>;
|
||||
ranges = <0x10000000 0x20000000 0x10000000>;
|
||||
|
||||
/* DT Overlay contains: &fpga_region0 */
|
||||
firmware-name = "zynq-gpio.bin";
|
||||
gpio@40000000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = <0x40000000 0x10000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
/*
|
||||
* Partial reconfiguration with bridge
|
||||
*/
|
||||
fpga_region1: fpga-region@0 {
|
||||
compatible = "fpga-region";
|
||||
reg = <0 0>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
fpga-mgr = <&fpga_mgr1>;
|
||||
fpga-bridges = <&fpga_bridge1>;
|
||||
partial-fpga-config;
|
||||
|
||||
/* DT Overlay contains: &fpga_region1 */
|
||||
firmware-name = "zynq-gpio-partial.bin";
|
||||
clk: clock {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&parentclk>;
|
||||
#clock-cells = <0>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
gpio@40000000 {
|
||||
compatible = "xlnx,xps-gpio-1.00.a";
|
||||
reg = <0x40000000 0x10000>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
clocks = <&clk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,7 +1,6 @@
|
||||
Gateworks PLD GPIO controller bindings
|
||||
|
||||
The GPIO controller should be a child node on an I2C bus,
|
||||
see: i2c/i2c.txt for details.
|
||||
The GPIO controller should be a child node on an I2C bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "gateworks,pld-gpio"
|
||||
|
||||
@@ -9,7 +9,7 @@ title: Marvell PXA GPIO controller
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
- Rob Herring <robh+dt@kernel.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
|
||||
@@ -32,7 +32,6 @@ description: |
|
||||
+-------------------------------+
|
||||
|
||||
allOf:
|
||||
- $ref: i2c-mux.yaml
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
|
||||
properties:
|
||||
@@ -41,6 +40,8 @@ properties:
|
||||
|
||||
i2c-parent:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
maxItems: 1
|
||||
description:
|
||||
List of phandles of I2C masters available for selection. The first one
|
||||
will be used as default.
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Marvell MMP I2C controller
|
||||
|
||||
maintainers:
|
||||
- Rob Herring <robh+dt@kernel.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/i2c/i2c-controller.yaml#
|
||||
|
||||
@@ -1,151 +0,0 @@
|
||||
Generic device tree bindings for I2C busses
|
||||
===========================================
|
||||
|
||||
This document describes generic bindings which can be used to describe I2C
|
||||
busses and their child devices in a device tree.
|
||||
|
||||
Required properties (per bus)
|
||||
-----------------------------
|
||||
|
||||
- #address-cells - should be <1>. Read more about addresses below.
|
||||
- #size-cells - should be <0>.
|
||||
- compatible - name of I2C bus controller
|
||||
|
||||
For other required properties e.g. to describe register sets,
|
||||
clocks, etc. check the binding documentation of the specific driver.
|
||||
|
||||
The cells properties above define that an address of children of an I2C bus
|
||||
are described by a single value.
|
||||
|
||||
Optional properties (per bus)
|
||||
-----------------------------
|
||||
|
||||
These properties may not be supported by all drivers. However, if a driver
|
||||
wants to support one of the below features, it should adapt these bindings.
|
||||
|
||||
- clock-frequency
|
||||
frequency of bus clock in Hz.
|
||||
|
||||
- i2c-bus
|
||||
For I2C adapters that have child nodes that are a mixture of both I2C
|
||||
devices and non-I2C devices, the 'i2c-bus' subnode can be used for
|
||||
populating I2C devices. If the 'i2c-bus' subnode is present, only
|
||||
subnodes of this will be considered as I2C slaves. The properties,
|
||||
'#address-cells' and '#size-cells' must be defined under this subnode
|
||||
if present.
|
||||
|
||||
- i2c-scl-falling-time-ns
|
||||
Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
|
||||
specification.
|
||||
|
||||
- i2c-scl-internal-delay-ns
|
||||
Number of nanoseconds the IP core additionally needs to setup SCL.
|
||||
|
||||
- i2c-scl-rising-time-ns
|
||||
Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
|
||||
specification.
|
||||
|
||||
- i2c-sda-falling-time-ns
|
||||
Number of nanoseconds the SDA signal takes to fall; t(f) in the I2C
|
||||
specification.
|
||||
|
||||
- i2c-analog-filter
|
||||
Enable analog filter for i2c lines.
|
||||
|
||||
- i2c-digital-filter
|
||||
Enable digital filter for i2c lines.
|
||||
|
||||
- i2c-digital-filter-width-ns
|
||||
Width of spikes which can be filtered by digital filter
|
||||
(i2c-digital-filter). This width is specified in nanoseconds.
|
||||
|
||||
- i2c-analog-filter-cutoff-frequency
|
||||
Frequency that the analog filter (i2c-analog-filter) uses to distinguish
|
||||
which signal to filter. Signal with higher frequency than specified will
|
||||
be filtered out. Only lower frequency will pass (this is applicable to
|
||||
a low-pass analog filter). Typical value should be above the normal
|
||||
i2c bus clock frequency (clock-frequency).
|
||||
Specified in Hz.
|
||||
|
||||
- multi-master
|
||||
states that there is another master active on this bus. The OS can use
|
||||
this information to adapt power management to keep the arbitration awake
|
||||
all the time, for example. Can not be combined with 'single-master'.
|
||||
|
||||
- pinctrl
|
||||
add extra pinctrl to configure SCL/SDA pins to GPIO function for bus
|
||||
recovery, call it "gpio" or "recovery" (deprecated) state
|
||||
|
||||
- scl-gpios
|
||||
specify the gpio related to SCL pin. Used for GPIO bus recovery.
|
||||
|
||||
- sda-gpios
|
||||
specify the gpio related to SDA pin. Optional for GPIO bus recovery.
|
||||
|
||||
- single-master
|
||||
states that there is no other master active on this bus. The OS can use
|
||||
this information to detect a stalled bus more reliably, for example.
|
||||
Can not be combined with 'multi-master'.
|
||||
|
||||
- smbus
|
||||
states that additional SMBus restrictions and features apply to this bus.
|
||||
An example of feature is SMBusHostNotify. Examples of restrictions are
|
||||
more reserved addresses and timeout definitions.
|
||||
|
||||
- smbus-alert
|
||||
states that the optional SMBus-Alert feature apply to this bus.
|
||||
|
||||
- mctp-controller
|
||||
indicates that the system is accessible via this bus as an endpoint for
|
||||
MCTP over I2C transport.
|
||||
|
||||
Required properties (per child device)
|
||||
--------------------------------------
|
||||
|
||||
- compatible
|
||||
name of I2C slave device
|
||||
|
||||
- reg
|
||||
One or many I2C slave addresses. These are usually a 7 bit addresses.
|
||||
However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is
|
||||
used to mark a 10 bit address. It is needed to avoid the ambiguity
|
||||
between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050
|
||||
which, in theory, can be on the same bus.
|
||||
Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we
|
||||
listen to be devices ourselves.
|
||||
|
||||
Optional properties (per child device)
|
||||
--------------------------------------
|
||||
|
||||
These properties may not be supported by all drivers. However, if a driver
|
||||
wants to support one of the below features, it should adapt these bindings.
|
||||
|
||||
- host-notify
|
||||
device uses SMBus host notify protocol instead of interrupt line.
|
||||
|
||||
- interrupts
|
||||
interrupts used by the device.
|
||||
|
||||
- interrupt-names
|
||||
"irq", "wakeup" and "smbus_alert" names are recognized by I2C core,
|
||||
other names are left to individual drivers.
|
||||
|
||||
- reg-names
|
||||
Names of map programmable addresses.
|
||||
It can contain any map needing another address than default one.
|
||||
|
||||
- wakeup-source
|
||||
device can be used as a wakeup source.
|
||||
|
||||
Binding may contain optional "interrupts" property, describing interrupts
|
||||
used by the device. I2C core will assign "irq" interrupt (or the very first
|
||||
interrupt if not using interrupt names) as primary interrupt for the slave.
|
||||
|
||||
Alternatively, devices supporting SMBus Host Notify, and connected to
|
||||
adapters that support this feature, may use "host-notify" property. I2C
|
||||
core will create a virtual interrupt for Host Notify and assign it as
|
||||
primary interrupt for the slave.
|
||||
|
||||
Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
|
||||
interrupt for the device. If "wakeup" interrupt name is not present in the
|
||||
binding, then primary interrupt will be used as wakeup interrupt.
|
||||
@@ -21,8 +21,7 @@ description: |
|
||||
See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
|
||||
binding.
|
||||
|
||||
This node represents an I2C controller. See ../i2c/i2c.txt for details
|
||||
of the core I2C binding.
|
||||
This node represents an I2C controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -57,7 +57,7 @@ examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
i3c-master@2000 {
|
||||
i3c@2000 {
|
||||
compatible = "aspeed,ast2600-i3c";
|
||||
reg = <0x2000 0x1000>;
|
||||
#address-cells = <3>;
|
||||
|
||||
@@ -41,7 +41,7 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@d040000 {
|
||||
i3c@d040000 {
|
||||
compatible = "cdns,i3c-master";
|
||||
clocks = <&coreclock>, <&i3csysclock>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
|
||||
@@ -17,7 +17,7 @@ description: |
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^i3c-master@[0-9a-f]+$"
|
||||
pattern: "^i3c@[0-9a-f]+$"
|
||||
|
||||
"#address-cells":
|
||||
const: 3
|
||||
@@ -71,7 +71,7 @@ patternProperties:
|
||||
description: |
|
||||
I2C child, should be named: <device-type>@<i2c-address>
|
||||
|
||||
All properties described in Documentation/devicetree/bindings/i2c/i2c.txt
|
||||
All properties described in dtschema schemas/i2c/i2c-controller.yaml
|
||||
are valid here, except the reg property whose content is changed.
|
||||
|
||||
properties:
|
||||
@@ -153,7 +153,7 @@ additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@d040000 {
|
||||
i3c@d040000 {
|
||||
compatible = "cdns,i3c-master";
|
||||
clocks = <&coreclock>, <&i3csysclock>;
|
||||
clock-names = "pclk", "sysclk";
|
||||
|
||||
@@ -43,7 +43,7 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@a0000000 {
|
||||
i3c@a0000000 {
|
||||
compatible = "mipi-i3c-hci";
|
||||
reg = <0xa0000000 0x2000>;
|
||||
interrupts = <89>;
|
||||
|
||||
@@ -48,7 +48,7 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@a0000000 {
|
||||
i3c@a0000000 {
|
||||
compatible = "silvaco,i3c-master-v1";
|
||||
clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
|
||||
clock-names = "pclk", "fast_clk", "slow_clk";
|
||||
|
||||
@@ -35,7 +35,7 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i3c-master@2000 {
|
||||
i3c@2000 {
|
||||
compatible = "snps,dw-i3c-master-1.00a";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@@ -49,7 +49,6 @@ patternProperties:
|
||||
$ref: input.yaml#
|
||||
properties:
|
||||
label:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Descriptive name of the key
|
||||
|
||||
linux,code: true
|
||||
|
||||
@@ -1,36 +0,0 @@
|
||||
Device tree bindings for Atmel capacitive touch device, typically
|
||||
an Atmel touch sensor connected to AtmegaXX MCU running firmware
|
||||
based on Qtouch library.
|
||||
|
||||
The node for this device must be a child of a I2C controller node, as the
|
||||
device communicates via I2C.
|
||||
|
||||
Required properties:
|
||||
|
||||
compatible: Must be "atmel,captouch".
|
||||
reg: The I2C slave address of the device.
|
||||
interrupts: Property describing the interrupt line the device
|
||||
is connected to. The device only has one interrupt
|
||||
source.
|
||||
linux,keycodes: Specifies an array of numeric keycode values to
|
||||
be used for reporting button presses. The array can
|
||||
contain up to 8 entries.
|
||||
|
||||
Optional properties:
|
||||
|
||||
autorepeat: Enables the Linux input system's autorepeat
|
||||
feature on the input device.
|
||||
|
||||
Example:
|
||||
|
||||
atmel-captouch@51 {
|
||||
compatible = "atmel,captouch";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
|
||||
linux,keycodes = <BTN_0>, <BTN_1>,
|
||||
<BTN_2>, <BTN_3>,
|
||||
<BTN_4>, <BTN_5>,
|
||||
<BTN_6>, <BTN_7>;
|
||||
autorepeat;
|
||||
};
|
||||
@@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/atmel,captouch.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Atmel capacitive touch device
|
||||
|
||||
maintainers:
|
||||
- Dharma balasubiramani <dharma.b@microchip.com>
|
||||
|
||||
description:
|
||||
Atmel capacitive touch device, typically an Atmel touch sensor connected to
|
||||
AtmegaXX MCU running firmware based on Qtouch library.
|
||||
|
||||
allOf:
|
||||
- $ref: input.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: atmel,captouch
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
linux,keycodes:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- linux,keycodes
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
touch@51 {
|
||||
compatible = "atmel,captouch";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&tlmm>;
|
||||
interrupts = <67 IRQ_TYPE_EDGE_FALLING>;
|
||||
linux,keycodes = <BTN_0>, <BTN_1>,
|
||||
<BTN_2>, <BTN_3>,
|
||||
<BTN_4>, <BTN_5>,
|
||||
<BTN_6>, <BTN_7>;
|
||||
autorepeat;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,121 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/samsung,s3c6410-keypad.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung SoC series Keypad Controller
|
||||
|
||||
description:
|
||||
Samsung SoC Keypad controller is used to interface a SoC with a matrix-type
|
||||
keypad device. The keypad controller supports multiple row and column lines.
|
||||
A key can be placed at each intersection of a unique row and a unique column.
|
||||
The keypad controller can sense a key-press and key-release and report the
|
||||
event using a interrupt to the cpu.
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s3c6410-keypad
|
||||
- samsung,s5pv210-keypad
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: keypad
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
wakeup-source: true
|
||||
|
||||
linux,input-no-autorepeat:
|
||||
type: boolean
|
||||
description:
|
||||
Do no enable autorepeat feature.
|
||||
|
||||
linux,input-wakeup:
|
||||
type: boolean
|
||||
deprecated: true
|
||||
|
||||
samsung,keypad-num-columns:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Number of column lines connected to the keypad controller.
|
||||
|
||||
samsung,keypad-num-rows:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Number of row lines connected to the keypad controller.
|
||||
|
||||
patternProperties:
|
||||
'^key-[0-9a-z]+$':
|
||||
type: object
|
||||
$ref: input.yaml#
|
||||
additionalProperties: false
|
||||
description:
|
||||
Each key connected to the keypad controller is represented as a child
|
||||
node to the keypad controller device node.
|
||||
|
||||
properties:
|
||||
keypad,column:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: The column number to which the key is connected.
|
||||
|
||||
keypad,row:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: The row number to which the key is connected.
|
||||
|
||||
linux,code: true
|
||||
|
||||
required:
|
||||
- keypad,column
|
||||
- keypad,row
|
||||
- linux,code
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- samsung,keypad-num-columns
|
||||
- samsung,keypad-num-rows
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos4.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
keypad@100a0000 {
|
||||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100a0000 0x100>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clock CLK_KEYIF>;
|
||||
clock-names = "keypad";
|
||||
|
||||
samsung,keypad-num-rows = <2>;
|
||||
samsung,keypad-num-columns = <8>;
|
||||
linux,input-no-autorepeat;
|
||||
wakeup-source;
|
||||
|
||||
key-1 {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <3>;
|
||||
linux,code = <2>;
|
||||
};
|
||||
|
||||
key-2 {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <4>;
|
||||
linux,code = <3>;
|
||||
};
|
||||
};
|
||||
@@ -1,77 +0,0 @@
|
||||
* Samsung's Keypad Controller device tree bindings
|
||||
|
||||
Samsung's Keypad controller is used to interface a SoC with a matrix-type
|
||||
keypad device. The keypad controller supports multiple row and column lines.
|
||||
A key can be placed at each intersection of a unique row and a unique column.
|
||||
The keypad controller can sense a key-press and key-release and report the
|
||||
event using a interrupt to the cpu.
|
||||
|
||||
Required SoC Specific Properties:
|
||||
- compatible: should be one of the following
|
||||
- "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
|
||||
controller.
|
||||
- "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
|
||||
controller.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- interrupts: The interrupt number to the cpu.
|
||||
|
||||
Required Board Specific Properties:
|
||||
- samsung,keypad-num-rows: Number of row lines connected to the keypad
|
||||
controller.
|
||||
|
||||
- samsung,keypad-num-columns: Number of column lines connected to the
|
||||
keypad controller.
|
||||
|
||||
- Keys represented as child nodes: Each key connected to the keypad
|
||||
controller is represented as a child node to the keypad controller
|
||||
device node and should include the following properties.
|
||||
- keypad,row: the row number to which the key is connected.
|
||||
- keypad,column: the column number to which the key is connected.
|
||||
- linux,code: the key-code to be reported when the key is pressed
|
||||
and released.
|
||||
|
||||
- pinctrl-0: Should specify pin control groups used for this controller.
|
||||
- pinctrl-names: Should contain only one value - "default".
|
||||
|
||||
Optional Properties:
|
||||
- wakeup-source: use any event on keypad as wakeup event.
|
||||
(Legacy property supported: "linux,input-wakeup")
|
||||
|
||||
Optional Properties specific to linux:
|
||||
- linux,keypad-no-autorepeat: do no enable autorepeat feature.
|
||||
|
||||
|
||||
Example:
|
||||
keypad@100a0000 {
|
||||
compatible = "samsung,s5pv210-keypad";
|
||||
reg = <0x100A0000 0x100>;
|
||||
interrupts = <173>;
|
||||
samsung,keypad-num-rows = <2>;
|
||||
samsung,keypad-num-columns = <8>;
|
||||
linux,input-no-autorepeat;
|
||||
wakeup-source;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&keypad_rows &keypad_columns>;
|
||||
|
||||
key_1 {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <3>;
|
||||
linux,code = <2>;
|
||||
};
|
||||
|
||||
key_2 {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <4>;
|
||||
linux,code = <3>;
|
||||
};
|
||||
|
||||
key_3 {
|
||||
keypad,row = <0>;
|
||||
keypad,column = <5>;
|
||||
linux,code = <4>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/touchscreen/fsl,imx6ul-tsc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX6UL Touch Controller
|
||||
|
||||
maintainers:
|
||||
- Haibo Chen <haibo.chen@nxp.com>
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6ul-tsc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: touch controller address
|
||||
- description: ADC2 address
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: touch controller address
|
||||
- description: ADC2 address
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: tsc
|
||||
- const: adc
|
||||
|
||||
xnur-gpios:
|
||||
maxItems: 1
|
||||
description:
|
||||
The X- gpio this controller connect to. This xnur-gpio returns to
|
||||
low once the finger leave the touch screen (The last touch event
|
||||
the touch controller capture).
|
||||
|
||||
measure-delay-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The value of measure delay time. Before X-axis or Y-axis measurement,
|
||||
the screen need some time before even potential distribution ready.
|
||||
default: 0xffff
|
||||
minimum: 0
|
||||
maximum: 0xffffff
|
||||
|
||||
pre-charge-time:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
The touch screen need some time to precharge.
|
||||
default: 0xfff
|
||||
minimum: 0
|
||||
maximum: 0xffffffff
|
||||
|
||||
touchscreen-average-samples:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Number of data samples which are averaged for each read.
|
||||
enum: [ 1, 4, 8, 16, 32 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- xnur-gpios
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/imx6ul-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
touchscreen@2040000 {
|
||||
compatible = "fsl,imx6ul-tsc";
|
||||
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_IPG>,
|
||||
<&clks IMX6UL_CLK_ADC2>;
|
||||
clock-names = "tsc", "adc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc>;
|
||||
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
measure-delay-time = <0xfff>;
|
||||
pre-charge-time = <0xffff>;
|
||||
touchscreen-average-samples = <32>;
|
||||
};
|
||||
@@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/input/touchscreen/goodix,gt9916.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Goodix Berlin series touchscreen controller
|
||||
|
||||
description: The Goodix Berlin series of touchscreen controllers
|
||||
be connected to either I2C or SPI buses.
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
- $ref: /schemas/spi/spi-peripheral-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- goodix,gt9916
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
maxItems: 1
|
||||
|
||||
avdd-supply:
|
||||
description: Analog power supply regulator on AVDD pin
|
||||
|
||||
vddio-supply:
|
||||
description: power supply regulator on VDDIO pin
|
||||
|
||||
spi-max-frequency: true
|
||||
touchscreen-inverted-x: true
|
||||
touchscreen-inverted-y: true
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-swapped-x-y: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- avdd-supply
|
||||
- touchscreen-size-x
|
||||
- touchscreen-size-y
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
touchscreen@5d {
|
||||
compatible = "goodix,gt9916";
|
||||
reg = <0x5d>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
avdd-supply = <&ts_avdd>;
|
||||
touchscreen-size-x = <1024>;
|
||||
touchscreen-size-y = <768>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
spi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
num-cs = <1>;
|
||||
cs-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
|
||||
touchscreen@0 {
|
||||
compatible = "goodix,gt9916";
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
avdd-supply = <&ts_avdd>;
|
||||
spi-max-frequency = <1000000>;
|
||||
touchscreen-size-x = <1024>;
|
||||
touchscreen-size-y = <768>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -37,8 +37,9 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
irq-gpios:
|
||||
description: GPIO pin used for IRQ. The driver uses the interrupt gpio pin
|
||||
as output to reset the device.
|
||||
description: GPIO pin used for IRQ input. Additionally, this line is
|
||||
sampled by the device on reset deassertion to select the I2C client
|
||||
address, thus it can be driven by the host during the reset sequence.
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
|
||||
@@ -9,15 +9,14 @@ title: Imagis IST30XXC family touchscreen controller
|
||||
maintainers:
|
||||
- Markuss Broks <markuss.broks@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^touchscreen@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- imagis,ist3032c
|
||||
- imagis,ist3038b
|
||||
- imagis,ist3038c
|
||||
|
||||
reg:
|
||||
@@ -32,6 +31,10 @@ properties:
|
||||
vddio-supply:
|
||||
description: Power supply regulator for the I2C bus
|
||||
|
||||
linux,keycodes:
|
||||
description: Keycodes for the touch keys
|
||||
maxItems: 5
|
||||
|
||||
touchscreen-size-x: true
|
||||
touchscreen-size-y: true
|
||||
touchscreen-fuzz-x: true
|
||||
@@ -42,6 +45,18 @@ properties:
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: touchscreen.yaml#
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: imagis,ist3032c
|
||||
then:
|
||||
properties:
|
||||
linux,keycodes: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -1,38 +0,0 @@
|
||||
* Freescale i.MX6UL Touch Controller
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "fsl,imx6ul-tsc".
|
||||
- reg: this touch controller address and the ADC2 address.
|
||||
- interrupts: the interrupt of this touch controller and ADC2.
|
||||
- clocks: the root clock of touch controller and ADC2.
|
||||
- clock-names; must be "tsc" and "adc".
|
||||
- xnur-gpio: the X- gpio this controller connect to.
|
||||
This xnur-gpio returns to low once the finger leave the touch screen (The
|
||||
last touch event the touch controller capture).
|
||||
|
||||
Optional properties:
|
||||
- measure-delay-time: the value of measure delay time.
|
||||
Before X-axis or Y-axis measurement, the screen need some time before
|
||||
even potential distribution ready.
|
||||
This value depends on the touch screen.
|
||||
- pre-charge-time: the touch screen need some time to precharge.
|
||||
This value depends on the touch screen.
|
||||
- touchscreen-average-samples: Number of data samples which are averaged for
|
||||
each read. Valid values are 1, 4, 8, 16 and 32.
|
||||
|
||||
Example:
|
||||
tsc: tsc@2040000 {
|
||||
compatible = "fsl,imx6ul-tsc";
|
||||
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_IPG>,
|
||||
<&clks IMX6UL_CLK_ADC2>;
|
||||
clock-names = "tsc", "adc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc>;
|
||||
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
measure-delay-time = <0xfff>;
|
||||
pre-charge-time = <0xffff>;
|
||||
touchscreen-average-samples = <32>;
|
||||
};
|
||||
@@ -17,13 +17,17 @@ properties:
|
||||
pattern: "^touchscreen(@.*)?$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
oneOf:
|
||||
- enum:
|
||||
- melfas,mms114
|
||||
- melfas,mms134s
|
||||
- melfas,mms136
|
||||
- melfas,mms152
|
||||
- melfas,mms345l
|
||||
- items:
|
||||
- enum:
|
||||
- melfas,mms252
|
||||
- const: melfas,mms114
|
||||
|
||||
reg:
|
||||
description: I2C address
|
||||
|
||||
@@ -31,7 +31,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
firmware-name:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
maxItems: 1
|
||||
description: >
|
||||
File basename for board specific firmware
|
||||
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
* Advanced Interrupt Controller (AIC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be:
|
||||
- "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
|
||||
"sama5d3" or "sama5d4"
|
||||
- "microchip,<chip>-aic" where <chip> can be "sam9x60"
|
||||
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
|
||||
The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
|
||||
The second cell is used to specify flags:
|
||||
bits[3:0] trigger type and level flags:
|
||||
1 = low-to-high edge triggered.
|
||||
2 = high-to-low edge triggered.
|
||||
4 = active high level-sensitive.
|
||||
8 = active low level-sensitive.
|
||||
Valid combinations are 1, 2, 3, 4, 8.
|
||||
Default flag for internal sources should be set to 4 (active high).
|
||||
The third cell is used to specify the irq priority from 0 (lowest) to 7
|
||||
(highest).
|
||||
- reg: Should contain AIC registers location and length
|
||||
- atmel,external-irqs: u32 array of external irqs.
|
||||
|
||||
Examples:
|
||||
/*
|
||||
* AIC
|
||||
*/
|
||||
aic: interrupt-controller@fffff000 {
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xfffff000 0x200>;
|
||||
};
|
||||
|
||||
/*
|
||||
* An interrupt generating device that is wired to an AIC.
|
||||
*/
|
||||
dma: dma-controller@ffffec00 {
|
||||
compatible = "atmel,at91sam9g45-dma";
|
||||
reg = <0xffffec00 0x200>;
|
||||
interrupts = <21 4 5>;
|
||||
};
|
||||
@@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Advanced Interrupt Controller (AIC)
|
||||
|
||||
maintainers:
|
||||
- Nicolas Ferre <nicolas.ferre@microchip.com>
|
||||
- Dharma balasubiramani <dharma.b@microchip.com>
|
||||
|
||||
description:
|
||||
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
|
||||
maskable, vectored interrupt controller providing handling of up to one
|
||||
hundred and twenty-eight interrupt sources.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- atmel,at91rm9200-aic
|
||||
- atmel,sama5d2-aic
|
||||
- atmel,sama5d3-aic
|
||||
- atmel,sama5d4-aic
|
||||
- microchip,sam9x60-aic
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 3
|
||||
description: |
|
||||
The 1st cell is the IRQ number (Peripheral IDentifier on datasheet).
|
||||
The 2nd cell specifies flags:
|
||||
bits[3:0] trigger type and level flags:
|
||||
1 = low-to-high edge triggered.
|
||||
2 = high-to-low edge triggered.
|
||||
4 = active high level-sensitive.
|
||||
8 = active low level-sensitive.
|
||||
Valid combinations: 1, 2, 3, 4, 8.
|
||||
Default for internal sources: 4 (active high).
|
||||
The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest).
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
atmel,external-irqs:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: u32 array of external irqs.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: atmel,at91rm9200-aic
|
||||
then:
|
||||
properties:
|
||||
atmel,external-irqs:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
else:
|
||||
properties:
|
||||
atmel,external-irqs:
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
- atmel,external-irqs
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
interrupt-controller@fffff000 {
|
||||
compatible = "atmel,at91rm9200-aic";
|
||||
reg = <0xfffff000 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
atmel,external-irqs = <31>;
|
||||
};
|
||||
...
|
||||
@@ -37,6 +37,9 @@ properties:
|
||||
clock-names:
|
||||
const: ipg
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mt6577-sysirq.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek sysirq
|
||||
|
||||
description:
|
||||
MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
|
||||
interrupt.
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: mediatek,mt6577-sysirq
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-sysirq
|
||||
- mediatek,mt2712-sysirq
|
||||
- mediatek,mt6580-sysirq
|
||||
- mediatek,mt6582-sysirq
|
||||
- mediatek,mt6589-sysirq
|
||||
- mediatek,mt6592-sysirq
|
||||
- mediatek,mt6755-sysirq
|
||||
- mediatek,mt6765-sysirq
|
||||
- mediatek,mt6779-sysirq
|
||||
- mediatek,mt6795-sysirq
|
||||
- mediatek,mt6797-sysirq
|
||||
- mediatek,mt7622-sysirq
|
||||
- mediatek,mt7623-sysirq
|
||||
- mediatek,mt7629-sysirq
|
||||
- mediatek,mt8127-sysirq
|
||||
- mediatek,mt8135-sysirq
|
||||
- mediatek,mt8173-sysirq
|
||||
- mediatek,mt8183-sysirq
|
||||
- mediatek,mt8365-sysirq
|
||||
- mediatek,mt8516-sysirq
|
||||
- const: mediatek,mt6577-sysirq
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
$ref: "arm,gic.yaml#/properties/#interrupt-cells"
|
||||
|
||||
required:
|
||||
- reg
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt6797-sysirq
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
interrupt-controller@10200620 {
|
||||
compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq";
|
||||
reg = <0x10220620 0x20>,
|
||||
<0x10220690 0x10>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
@@ -1,44 +0,0 @@
|
||||
MediaTek sysirq
|
||||
|
||||
MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
|
||||
interrupt.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be
|
||||
"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
|
||||
"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
|
||||
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
|
||||
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
|
||||
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
|
||||
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
|
||||
"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
|
||||
"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
|
||||
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
|
||||
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
|
||||
"mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq": for MT6779
|
||||
"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765
|
||||
"mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755
|
||||
"mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592
|
||||
"mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589
|
||||
"mediatek,mt6582-sysirq", "mediatek,mt6577-sysirq": for MT6582
|
||||
"mediatek,mt6580-sysirq", "mediatek,mt6577-sysirq": for MT6580
|
||||
"mediatek,mt6577-sysirq": for MT6577
|
||||
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
|
||||
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
|
||||
"mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
|
||||
- reg: Physical base address of the intpol registers and length of memory
|
||||
mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
|
||||
need 1.
|
||||
|
||||
Example:
|
||||
sysirq: intpol-controller@10200620 {
|
||||
compatible = "mediatek,mt6797-sysirq",
|
||||
"mediatek,mt6577-sysirq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10220620 0 0x20>,
|
||||
<0 0x10220690 0 0x10>;
|
||||
};
|
||||
@@ -44,7 +44,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 41
|
||||
minItems: 45
|
||||
items:
|
||||
- description: NMI interrupt
|
||||
- description: IRQ0 interrupt
|
||||
@@ -88,9 +88,15 @@ properties:
|
||||
- description: GPIO interrupt, TINT30
|
||||
- description: GPIO interrupt, TINT31
|
||||
- description: Bus error interrupt
|
||||
- description: ECCRAM0 or combined ECCRAM0/1 1bit error interrupt
|
||||
- description: ECCRAM0 or combined ECCRAM0/1 2bit error interrupt
|
||||
- description: ECCRAM0 or combined ECCRAM0/1 error overflow interrupt
|
||||
- description: ECCRAM1 1bit error interrupt
|
||||
- description: ECCRAM1 2bit error interrupt
|
||||
- description: ECCRAM1 error overflow interrupt
|
||||
|
||||
interrupt-names:
|
||||
minItems: 41
|
||||
minItems: 45
|
||||
items:
|
||||
- const: nmi
|
||||
- const: irq0
|
||||
@@ -134,6 +140,12 @@ properties:
|
||||
- const: tint30
|
||||
- const: tint31
|
||||
- const: bus-err
|
||||
- const: ec7tie1-0
|
||||
- const: ec7tie2-0
|
||||
- const: ec7tiovf-0
|
||||
- const: ec7tie1-1
|
||||
- const: ec7tie2-1
|
||||
- const: ec7tiovf-1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
@@ -156,6 +168,7 @@ required:
|
||||
- interrupt-controller
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
@@ -169,16 +182,19 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,r9a07g043u-irqc
|
||||
- renesas,r9a08g045-irqc
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 42
|
||||
maxItems: 45
|
||||
interrupt-names:
|
||||
minItems: 42
|
||||
required:
|
||||
- interrupt-names
|
||||
maxItems: 45
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 48
|
||||
interrupt-names:
|
||||
minItems: 48
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
@@ -233,7 +249,14 @@ examples:
|
||||
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
|
||||
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "nmi",
|
||||
"irq0", "irq1", "irq2", "irq3",
|
||||
"irq4", "irq5", "irq6", "irq7",
|
||||
@@ -244,7 +267,10 @@ examples:
|
||||
"tint16", "tint17", "tint18", "tint19",
|
||||
"tint20", "tint21", "tint22", "tint23",
|
||||
"tint24", "tint25", "tint26", "tint27",
|
||||
"tint28", "tint29", "tint30", "tint31";
|
||||
"tint28", "tint29", "tint30", "tint31",
|
||||
"bus-err", "ec7tie1-0", "ec7tie2-0",
|
||||
"ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
|
||||
"ec7tiovf-1";
|
||||
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
|
||||
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
|
||||
clock-names = "clk", "pclk";
|
||||
|
||||
@@ -23,22 +23,23 @@ properties:
|
||||
- brcm,bmips4380
|
||||
- brcm,bmips5000
|
||||
- brcm,bmips5200
|
||||
- ingenic,xburst-mxu1.0
|
||||
- img,i6500
|
||||
- ingenic,xburst-fpu1.0-mxu1.1
|
||||
- ingenic,xburst-fpu2.0-mxu2.0
|
||||
- ingenic,xburst-mxu1.0
|
||||
- ingenic,xburst2-fpu2.1-mxu2.1-smt
|
||||
- loongson,gs264
|
||||
- mips,m14Kc
|
||||
- mips,mips4Kc
|
||||
- mips,mips4KEc
|
||||
- mips,mips24Kc
|
||||
- mips,mips24KEc
|
||||
- mips,mips74Kc
|
||||
- mips,mips1004Kc
|
||||
- mips,mips24KEc
|
||||
- mips,mips24Kc
|
||||
- mips,mips4KEc
|
||||
- mips,mips4Kc
|
||||
- mips,mips74Kc
|
||||
- mti,interaptiv
|
||||
- mti,mips24KEc
|
||||
- mti,mips14KEc
|
||||
- mti,mips14Kc
|
||||
- mti,mips24KEc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
# Copyright 2023 Mobileye Vision Technologies Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mips/mobileye.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mobileye SoC series
|
||||
|
||||
maintainers:
|
||||
- Vladimir Kondratiev <vladimir.kondratiev@intel.com>
|
||||
- Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
- Théo Lebrun <theo.lebrun@bootlin.com>
|
||||
|
||||
description:
|
||||
Boards with a Mobileye SoC shall have the following properties.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Boards with Mobileye EyeQ5 SoC
|
||||
items:
|
||||
- enum:
|
||||
- mobileye,eyeq5-epm5
|
||||
- const: mobileye,eyeq5
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
@@ -77,6 +77,8 @@ patternProperties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
iommus:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
@@ -1,58 +0,0 @@
|
||||
* Xilinx SDFEC(16nm) IP *
|
||||
|
||||
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
|
||||
which provides high-throughput LDPC and Turbo Code implementations.
|
||||
The LDPC decode & encode functionality is capable of covering a range of
|
||||
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
|
||||
principally covers codes used by LTE. The FEC Engine offers significant
|
||||
power and area savings versus implementations done in the FPGA fabric.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "xlnx,sd-fec-1.1"
|
||||
- clock-names : List of input clock names from the following:
|
||||
- "core_clk", Main processing clock for processing core (required)
|
||||
- "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
|
||||
- "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
|
||||
- "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
|
||||
- "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
|
||||
- "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
|
||||
- "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
|
||||
- "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
|
||||
- clocks : Clock phandles (see clock_bindings.txt for details).
|
||||
- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
|
||||
location and length.
|
||||
- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
|
||||
being used.
|
||||
- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
|
||||
driven with a fixed value and is not present on the device, a value of 1
|
||||
configures the DIN_WORDS to be block based, while a value of 2 configures the
|
||||
DIN_WORDS input to be supplied for each AXI transaction.
|
||||
- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
|
||||
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
|
||||
of "4x128b".
|
||||
- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
|
||||
driven with a fixed value and is not present on the device, a value of 1
|
||||
configures the DOUT_WORDS to be block based, while a value of 2 configures the
|
||||
DOUT_WORDS input to be supplied for each AXI transaction.
|
||||
- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
|
||||
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
|
||||
of "4x128b".
|
||||
Optional properties:
|
||||
- interrupts: should contain SDFEC interrupt number
|
||||
|
||||
Example
|
||||
---------------------------------------
|
||||
sd_fec_0: sd-fec@a0040000 {
|
||||
compatible = "xlnx,sd-fec-1.1";
|
||||
clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
|
||||
clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
|
||||
reg = <0x0 0xa0040000 0x0 0x40000>;
|
||||
interrupt-parent = <&axi_intc>;
|
||||
interrupts = <1 0>;
|
||||
xlnx,sdfec-code = "ldpc";
|
||||
xlnx,sdfec-din-words = <0>;
|
||||
xlnx,sdfec-din-width = <2>;
|
||||
xlnx,sdfec-dout-words = <0>;
|
||||
xlnx,sdfec-dout-width = <1>;
|
||||
};
|
||||
@@ -0,0 +1,140 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx SDFEC(16nm) IP
|
||||
|
||||
maintainers:
|
||||
- Cvetic, Dragan <dragan.cvetic@amd.com>
|
||||
- Erim, Salih <salih.erim@amd.com>
|
||||
|
||||
description:
|
||||
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
|
||||
which provides high-throughput LDPC and Turbo Code implementations.
|
||||
The LDPC decode & encode functionality is capable of covering a range of
|
||||
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
|
||||
principally covers codes used by LTE. The FEC Engine offers significant
|
||||
power and area savings versus implementations done in the FPGA fabric.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,sd-fec-1.1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 8
|
||||
additionalItems: true
|
||||
items:
|
||||
- description: Main processing clock for processing core
|
||||
- description: AXI4-Lite memory-mapped slave interface clock
|
||||
- description: Control input AXI4-Stream Slave interface clock
|
||||
- description: DIN AXI4-Stream Slave interface clock
|
||||
- description: Status output AXI4-Stream Master interface clock
|
||||
- description: DOUT AXI4-Stream Master interface clock
|
||||
- description: DIN_WORDS AXI4-Stream Slave interface clock
|
||||
- description: DOUT_WORDS AXI4-Stream Master interface clock
|
||||
|
||||
clock-names:
|
||||
allOf:
|
||||
- minItems: 2
|
||||
maxItems: 8
|
||||
additionalItems: true
|
||||
items:
|
||||
- const: core_clk
|
||||
- const: s_axi_aclk
|
||||
- items:
|
||||
enum:
|
||||
- core_clk
|
||||
- s_axi_aclk
|
||||
- s_axis_ctrl_aclk
|
||||
- s_axis_din_aclk
|
||||
- m_axis_status_aclk
|
||||
- m_axis_dout_aclk
|
||||
- s_axis_din_words_aclk
|
||||
- m_axis_dout_words_aclk
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
xlnx,sdfec-code:
|
||||
description:
|
||||
The SD-FEC integrated block supports Low Density Parity Check (LDPC)
|
||||
decoding and encoding and Turbo code decoding. The LDPC codes used are
|
||||
highly configurable, and the specific code used can be specified on
|
||||
a codeword-by-codeword basis. The Turbo code decoding is required by LTE
|
||||
standard.
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
items:
|
||||
enum: [ ldpc, turbo ]
|
||||
|
||||
xlnx,sdfec-din-width:
|
||||
description:
|
||||
Configures the DIN AXI stream where a value of 1
|
||||
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
|
||||
of "4x128b".
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 4 ]
|
||||
|
||||
xlnx,sdfec-din-words:
|
||||
description:
|
||||
A value 0 indicates that the DIN_WORDS interface is
|
||||
driven with a fixed value and is not present on the device, a value of 1
|
||||
configures the DIN_WORDS to be block based, while a value of 2 configures the
|
||||
DIN_WORDS input to be supplied for each AXI transaction.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1, 2 ]
|
||||
|
||||
xlnx,sdfec-dout-width:
|
||||
description:
|
||||
Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b",
|
||||
2 a width of "2x128b" and 4 configures a width of "4x128b".
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 4 ]
|
||||
|
||||
xlnx,sdfec-dout-words:
|
||||
description:
|
||||
A value 0 indicates that the DOUT_WORDS interface is
|
||||
driven with a fixed value and is not present on the device, a value of 1
|
||||
configures the DOUT_WORDS to be block based, while a value of 2 configures the
|
||||
DOUT_WORDS input to be supplied for each AXI transaction.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1, 2 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- xlnx,sdfec-code
|
||||
- xlnx,sdfec-din-width
|
||||
- xlnx,sdfec-din-words
|
||||
- xlnx,sdfec-dout-width
|
||||
- xlnx,sdfec-dout-words
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
sd-fec@a0040000 {
|
||||
compatible = "xlnx,sd-fec-1.1";
|
||||
reg = <0xa0040000 0x40000>;
|
||||
clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>,
|
||||
<&misc_clk_1>, <&misc_clk_1>;
|
||||
clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
|
||||
"s_axis_din_aclk", "m_axis_status_aclk",
|
||||
"m_axis_dout_aclk";
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
xlnx,sdfec-code = "ldpc";
|
||||
xlnx,sdfec-din-width = <2>;
|
||||
xlnx,sdfec-din-words = <0>;
|
||||
xlnx,sdfec-dout-width = <1>;
|
||||
xlnx,sdfec-dout-words = <0>;
|
||||
};
|
||||
|
||||
@@ -74,7 +74,7 @@ select:
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: '^mux-controller(@.*|-[0-9a-f]+)?$'
|
||||
pattern: '^mux-controller(@.*|-([0-9]|[1-9][0-9]+))?$'
|
||||
|
||||
'#mux-control-cells':
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Bluetooth Chips
|
||||
|
||||
maintainers:
|
||||
- Balakrishna Godavarthi <bgodavar@codeaurora.org>
|
||||
- Rocky Liao <rjliao@codeaurora.org>
|
||||
- Balakrishna Godavarthi <quic_bgodavar@quicinc.com>
|
||||
- Rocky Liao <quic_rjliao@quicinc.com>
|
||||
|
||||
description:
|
||||
This binding describes Qualcomm UART-attached bluetooth chips.
|
||||
|
||||
@@ -38,6 +38,9 @@ properties:
|
||||
- fsl,imx6ul-flexcan
|
||||
- fsl,imx6sx-flexcan
|
||||
- const: fsl,imx6q-flexcan
|
||||
- items:
|
||||
- const: fsl,imx95-flexcan
|
||||
- const: fsl,imx93-flexcan
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,ls1028ar1-flexcan
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (c) 2023 MediaTek, BayLibre
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek Sensor Interface MIPI CSI CD-PHY
|
||||
|
||||
maintainers:
|
||||
- Julien Stephan <jstephan@baylibre.com>
|
||||
- Andy Hsieh <andy.hsieh@mediatek.com>
|
||||
|
||||
description:
|
||||
The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
|
||||
receivers. The number of PHYs depends on the SoC model.
|
||||
Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
|
||||
capable.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt8365-csi-rx
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
num-lanes:
|
||||
enum: [2, 3, 4]
|
||||
|
||||
'#phy-cells':
|
||||
enum: [0, 1]
|
||||
description: |
|
||||
If the PHY doesn't support mode selection then #phy-cells must be 0 and
|
||||
PHY mode is described using phy-type property.
|
||||
If the PHY supports mode selection, then #phy-cells must be 1 and mode
|
||||
is set in the PHY cells. Supported modes are:
|
||||
- PHY_TYPE_DPHY
|
||||
- PHY_TYPE_CPHY
|
||||
See include/dt-bindings/phy/phy.h for constants.
|
||||
|
||||
phy-type:
|
||||
description:
|
||||
If the PHY doesn't support mode selection then this set the operating mode.
|
||||
See include/dt-bindings/phy/phy.h for constants.
|
||||
const: 10
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- num-lanes
|
||||
- '#phy-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
csi0_rx: phy@11c10000 {
|
||||
compatible = "mediatek,mt8365-csi-rx";
|
||||
reg = <0 0x11c10000 0 0x2000>;
|
||||
num-lanes = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
csi1_rx: phy@11c12000 {
|
||||
compatible = "mediatek,mt8365-csi-rx";
|
||||
reg = <0 0x11c12000 0 0x2000>;
|
||||
phy-type = <PHY_TYPE_DPHY>;
|
||||
num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -20,6 +20,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cdns,torrent-phy
|
||||
- ti,j7200-serdes-10g
|
||||
- ti,j721e-serdes-10g
|
||||
|
||||
'#address-cells':
|
||||
@@ -35,14 +36,18 @@ properties:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description:
|
||||
PHY reference clock for 1 item. Must contain an entry in clock-names.
|
||||
Optional Parent to enable output reference clock.
|
||||
PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
|
||||
pll1_refclk is optional and used for multi-protocol configurations requiring
|
||||
separate reference clock for each protocol.
|
||||
Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
|
||||
Optional parent clock (phy_en_refclk) to enable a reference clock output feature
|
||||
on some platforms to output either derived or received reference clock.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: refclk
|
||||
- const: phy_en_refclk
|
||||
- enum: [ pll1_refclk, phy_en_refclk ]
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm QMP PHY controller (USB, MSM8998)
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description:
|
||||
The QMP PHY controller supports physical layer functionality for USB-C on
|
||||
several Qualcomm chipsets.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,msm8998-qmp-usb3-phy
|
||||
- qcom,qcm2290-qmp-usb3-phy
|
||||
- qcom,sdm660-qmp-usb3-phy
|
||||
- qcom,sm6115-qmp-usb3-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
maxItems: 4
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: phy
|
||||
- const: phy_phy
|
||||
|
||||
vdda-phy-supply: true
|
||||
|
||||
vdda-pll-supply: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
orientation-switch:
|
||||
description:
|
||||
Flag the PHY as possible handler of USB Type-C orientation switching
|
||||
type: boolean
|
||||
|
||||
qcom,tcsr-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to TCSR hardware block
|
||||
- description: offset of the VLS CLAMP register
|
||||
description: Clamp register present in the TCSR
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Output endpoint of the PHY
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Incoming endpoint from the USB controller
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- vdda-phy-supply
|
||||
- vdda-pll-supply
|
||||
- "#clock-cells"
|
||||
- clock-output-names
|
||||
- "#phy-cells"
|
||||
- qcom,tcsr-reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8998-qmp-usb3-phy
|
||||
- qcom,sdm660-qmp-usb3-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux
|
||||
- const: ref
|
||||
- const: cfg_ahb
|
||||
- const: pipe
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcm2290-qmp-usb3-phy
|
||||
- qcom,sm6115-qmp-usb3-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: cfg_ahb
|
||||
- const: ref
|
||||
- const: com_aux
|
||||
- const: pipe
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
phy@c010000 {
|
||||
compatible = "qcom,msm8998-qmp-usb3-phy";
|
||||
reg = <0x0c010000 0x1000>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_CLKREF_CLK>,
|
||||
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
||||
<&gcc GCC_USB3_PHY_PIPE_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"cfg_ahb",
|
||||
"pipe";
|
||||
clock-output-names = "usb3_phy_pipe_clk_src";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
resets = <&gcc GCC_USB3_PHY_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_BCR>;
|
||||
reset-names = "phy",
|
||||
"phy_phy";
|
||||
|
||||
vdda-phy-supply = <&vreg_l1a_0p875>;
|
||||
vdda-pll-supply = <&vreg_l2a_1p2>;
|
||||
|
||||
orientation-switch;
|
||||
|
||||
qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&pmic_typec_mux_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&usb_dwc3_ss>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -38,6 +38,8 @@ properties:
|
||||
- qcom,sm8550-qmp-gen4x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen3x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen4x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen3x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen4x2-pcie-phy
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
@@ -151,6 +153,8 @@ allOf:
|
||||
- qcom,sm8550-qmp-gen4x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen3x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen4x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen3x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen4x2-pcie-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
@@ -194,6 +198,8 @@ allOf:
|
||||
enum:
|
||||
- qcom,sm8550-qmp-gen4x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen4x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen3x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen4x2-pcie-phy
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
|
||||
@@ -19,6 +19,7 @@ properties:
|
||||
- qcom,msm8996-qmp-ufs-phy
|
||||
- qcom,msm8998-qmp-ufs-phy
|
||||
- qcom,sa8775p-qmp-ufs-phy
|
||||
- qcom,sc7180-qmp-ufs-phy
|
||||
- qcom,sc7280-qmp-ufs-phy
|
||||
- qcom,sc8180x-qmp-ufs-phy
|
||||
- qcom,sc8280xp-qmp-ufs-phy
|
||||
@@ -38,15 +39,12 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: ref
|
||||
- const: ref_aux
|
||||
- const: qref
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
@@ -86,22 +84,9 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8998-qmp-ufs-phy
|
||||
- qcom,sa8775p-qmp-ufs-phy
|
||||
- qcom,sc7280-qmp-ufs-phy
|
||||
- qcom,sm8450-qmp-ufs-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
clock-names:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,msm8998-qmp-ufs-phy
|
||||
- qcom,sc8180x-qmp-ufs-phy
|
||||
- qcom,sc8280xp-qmp-ufs-phy
|
||||
- qcom,sdm845-qmp-ufs-phy
|
||||
@@ -112,14 +97,19 @@ allOf:
|
||||
- qcom,sm8150-qmp-ufs-phy
|
||||
- qcom,sm8250-qmp-ufs-phy
|
||||
- qcom,sm8350-qmp-ufs-phy
|
||||
- qcom,sm8450-qmp-ufs-phy
|
||||
- qcom,sm8550-qmp-ufs-phy
|
||||
- qcom,sm8650-qmp-ufs-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: ref
|
||||
- const: ref_aux
|
||||
- const: qref
|
||||
|
||||
- if:
|
||||
properties:
|
||||
@@ -130,22 +120,28 @@ allOf:
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
items:
|
||||
- const: ref
|
||||
- const: qref
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
ufs_mem_phy: phy@1d87000 {
|
||||
compatible = "qcom,sc8280xp-qmp-ufs-phy";
|
||||
reg = <0x01d87000 0x1000>;
|
||||
|
||||
clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
||||
clock-names = "ref", "ref_aux";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
||||
<&gcc GCC_UFS_REF_CLKREF_CLK>;
|
||||
|
||||
clock-names = "ref", "ref_aux", "qref";
|
||||
|
||||
power-domains = <&gcc UFS_PHY_GDSC>;
|
||||
|
||||
|
||||
@@ -20,15 +20,12 @@ properties:
|
||||
- qcom,ipq8074-qmp-usb3-phy
|
||||
- qcom,ipq9574-qmp-usb3-phy
|
||||
- qcom,msm8996-qmp-usb3-phy
|
||||
- qcom,msm8998-qmp-usb3-phy
|
||||
- qcom,qcm2290-qmp-usb3-phy
|
||||
- qcom,sa8775p-qmp-usb3-uni-phy
|
||||
- qcom,sc8280xp-qmp-usb3-uni-phy
|
||||
- qcom,sdm845-qmp-usb3-uni-phy
|
||||
- qcom,sdx55-qmp-usb3-uni-phy
|
||||
- qcom,sdx65-qmp-usb3-uni-phy
|
||||
- qcom,sdx75-qmp-usb3-uni-phy
|
||||
- qcom,sm6115-qmp-usb3-phy
|
||||
- qcom,sm8150-qmp-usb3-uni-phy
|
||||
- qcom,sm8250-qmp-usb3-uni-phy
|
||||
- qcom,sm8350-qmp-usb3-uni-phy
|
||||
@@ -93,7 +90,6 @@ allOf:
|
||||
- qcom,ipq8074-qmp-usb3-phy
|
||||
- qcom,ipq9574-qmp-usb3-phy
|
||||
- qcom,msm8996-qmp-usb3-phy
|
||||
- qcom,msm8998-qmp-usb3-phy
|
||||
- qcom,sdx55-qmp-usb3-uni-phy
|
||||
- qcom,sdx65-qmp-usb3-uni-phy
|
||||
- qcom,sdx75-qmp-usb3-uni-phy
|
||||
@@ -108,24 +104,6 @@ allOf:
|
||||
- const: cfg_ahb
|
||||
- const: pipe
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcm2290-qmp-usb3-phy
|
||||
- qcom,sm6115-qmp-usb3-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 4
|
||||
clock-names:
|
||||
items:
|
||||
- const: cfg_ahb
|
||||
- const: ref
|
||||
- const: com_aux
|
||||
- const: pipe
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
|
||||
|
||||
maintainers:
|
||||
- Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3588-hdptx-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Reference clock
|
||||
- description: APB clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
- const: apb
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: PHY reset line
|
||||
- description: APB reset line
|
||||
- description: INIT reset line
|
||||
- description: CMN reset line
|
||||
- description: LANE reset line
|
||||
- description: ROPLL reset line
|
||||
- description: LCPLL reset line
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: phy
|
||||
- const: apb
|
||||
- const: init
|
||||
- const: cmn
|
||||
- const: lane
|
||||
- const: ropll
|
||||
- const: lcpll
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: Some PHY related data is accessed through GRF regs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#phy-cells"
|
||||
- resets
|
||||
- reset-names
|
||||
- rockchip,grf
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
phy@fed60000 {
|
||||
compatible = "rockchip,rk3588-hdptx-phy";
|
||||
reg = <0x0 0xfed60000 0x0 0x2000>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
||||
clock-names = "ref", "apb";
|
||||
#phy-cells = <0>;
|
||||
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
||||
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
||||
<&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
|
||||
<&cru SRST_HDPTX0_LCPLL>;
|
||||
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
|
||||
rockchip,grf = <&hdptxphy_grf>;
|
||||
};
|
||||
};
|
||||
@@ -1,37 +0,0 @@
|
||||
* Freescale i.MX6 UltraLite IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
|
||||
"fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
|
||||
- fsl,pins: each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
||||
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
|
||||
imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
|
||||
the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
|
||||
Reference Manual for detailed CONFIG settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_HYS (1 << 16)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
PAD_CTL_PUE (1 << 13)
|
||||
PAD_CTL_PKE (1 << 12)
|
||||
PAD_CTL_ODE (1 << 11)
|
||||
PAD_CTL_SPEED_LOW (0 << 6)
|
||||
PAD_CTL_SPEED_MED (1 << 6)
|
||||
PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
PAD_CTL_DSE_260ohm (1 << 3)
|
||||
PAD_CTL_DSE_130ohm (2 << 3)
|
||||
PAD_CTL_DSE_87ohm (3 << 3)
|
||||
PAD_CTL_DSE_65ohm (4 << 3)
|
||||
PAD_CTL_DSE_52ohm (5 << 3)
|
||||
PAD_CTL_DSE_43ohm (6 << 3)
|
||||
PAD_CTL_DSE_37ohm (7 << 3)
|
||||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
@@ -0,0 +1,116 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx6ul-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX6UL IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Dong Aisheng <aisheng.dong@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx6ul-iomuxc
|
||||
- fsl,imx6ull-iomuxc-snvs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm/boot/dts/imx6ul-pinfunc.h>. The last integer
|
||||
CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX6UL Reference Manual for detailed CONFIG settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied:
|
||||
PAD_CTL_HYS (1 << 16)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 14)
|
||||
PAD_CTL_PUS_47K_UP (1 << 14)
|
||||
PAD_CTL_PUS_100K_UP (2 << 14)
|
||||
PAD_CTL_PUS_22K_UP (3 << 14)
|
||||
PAD_CTL_PUE (1 << 13)
|
||||
PAD_CTL_PKE (1 << 12)
|
||||
PAD_CTL_ODE (1 << 11)
|
||||
PAD_CTL_SPEED_LOW (0 << 6)
|
||||
PAD_CTL_SPEED_MED (1 << 6)
|
||||
PAD_CTL_SPEED_HIGH (3 << 6)
|
||||
PAD_CTL_DSE_DISABLE (0 << 3)
|
||||
PAD_CTL_DSE_260ohm (1 << 3)
|
||||
PAD_CTL_DSE_130ohm (2 << 3)
|
||||
PAD_CTL_DSE_87ohm (3 << 3)
|
||||
PAD_CTL_DSE_65ohm (4 << 3)
|
||||
PAD_CTL_DSE_52ohm (5 << 3)
|
||||
PAD_CTL_DSE_43ohm (6 << 3)
|
||||
PAD_CTL_DSE_37ohm (7 << 3)
|
||||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
iomuxc: pinctrl@20e0000 {
|
||||
compatible = "fsl,imx6ul-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
|
||||
mux_uart: uartgrp {
|
||||
fsl,pins = <
|
||||
0x0084 0x0310 0x0000 0 0 0x1b0b1
|
||||
0x0088 0x0314 0x0624 0 3 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
- |
|
||||
iomuxc_snvs: pinctrl@2290000 {
|
||||
compatible = "fsl,imx6ull-iomuxc-snvs";
|
||||
reg = <0x02290000 0x4000>;
|
||||
|
||||
pinctrl_snvs_usbc_det: snvsusbcdetgrp {
|
||||
fsl,pins = <
|
||||
0x0010 0x0054 0x0000 0x5 0x0 0x130b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -27,7 +27,7 @@ List of legacy properties and respective binding document
|
||||
Documentation/devicetree/bindings/mfd/tc3589x.txt
|
||||
Documentation/devicetree/bindings/input/touchscreen/ads7846.txt
|
||||
4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
|
||||
5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung-keypad.txt
|
||||
5. "linux,input-wakeup" Documentation/devicetree/bindings/input/samsung,s3c6410-keypad.yaml
|
||||
6. "nvidia,wakeup-source" Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
|
||||
|
||||
Examples
|
||||
|
||||
@@ -21,6 +21,10 @@ properties:
|
||||
- enum:
|
||||
- microchip,sama7g5-trng
|
||||
- const: atmel,at91sam9g45-trng
|
||||
- items:
|
||||
- enum:
|
||||
- microchip,sam9x7-trng
|
||||
- const: microchip,sam9x60-trng
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
@@ -12,7 +12,7 @@ allOf:
|
||||
maintainers:
|
||||
- Alessandro Zummo <a.zummo@towertech.it>
|
||||
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
- Rob Herring <robh+dt@kernel.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -0,0 +1,128 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/imx/fsl,imx-anatop.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ANATOP register
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6sl-anatop
|
||||
- fsl,imx6sll-anatop
|
||||
- fsl,imx6sx-anatop
|
||||
- fsl,imx6ul-anatop
|
||||
- fsl,imx7d-anatop
|
||||
- const: fsl,imx6q-anatop
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- const: fsl,imx6q-anatop
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Temperature sensor event
|
||||
- description: Brown-out event on either of the support regulators
|
||||
- description: Brown-out event on either the core, gpu or soc regulators
|
||||
|
||||
tempmon:
|
||||
type: object
|
||||
unevaluatedProperties: false
|
||||
$ref: /schemas/thermal/imx-thermal.yaml
|
||||
|
||||
patternProperties:
|
||||
"regulator-((1p1)|(2p5)|(3p0)|(vddcore)|(vddpu)|(vddsoc))$":
|
||||
type: object
|
||||
unevaluatedProperties: false
|
||||
$ref: /schemas/regulator/anatop-regulator.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx6ul-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
anatop: anatop@20c8000 {
|
||||
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
|
||||
"syscon", "simple-mfd";
|
||||
reg = <0x020c8000 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
reg_3p0: regulator-3p0 {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vdd3p0";
|
||||
regulator-min-microvolt = <2625000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
anatop-reg-offset = <0x120>;
|
||||
anatop-vol-bit-shift = <8>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-min-bit-val = <0>;
|
||||
anatop-min-voltage = <2625000>;
|
||||
anatop-max-voltage = <3400000>;
|
||||
anatop-enable-bit = <0>;
|
||||
};
|
||||
|
||||
reg_arm: regulator-vddcore {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "cpu";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <0>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <24>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
reg_soc: regulator-vddsoc {
|
||||
compatible = "fsl,anatop-regulator";
|
||||
regulator-name = "vddsoc";
|
||||
regulator-min-microvolt = <725000>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-always-on;
|
||||
anatop-reg-offset = <0x140>;
|
||||
anatop-vol-bit-shift = <18>;
|
||||
anatop-vol-bit-width = <5>;
|
||||
anatop-delay-reg-offset = <0x170>;
|
||||
anatop-delay-bit-shift = <28>;
|
||||
anatop-delay-bit-width = <2>;
|
||||
anatop-min-bit-val = <1>;
|
||||
anatop-min-voltage = <725000>;
|
||||
anatop-max-voltage = <1450000>;
|
||||
};
|
||||
|
||||
tempmon: tempmon {
|
||||
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
|
||||
interrupt-parent = <&gpc>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
|
||||
nvmem-cell-names = "calib", "temp_grade";
|
||||
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
};
|
||||
@@ -17,7 +17,23 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: fsl,imx8mq-iomuxc-gpr
|
||||
- enum:
|
||||
- fsl,imx6q-iomuxc-gpr
|
||||
- fsl,imx8mq-iomuxc-gpr
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6sl-iomuxc-gpr
|
||||
- fsl,imx6sll-iomuxc-gpr
|
||||
- fsl,imx6ul-iomuxc-gpr
|
||||
- const: fsl,imx6q-iomuxc-gpr
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6sx-iomuxc-gpr
|
||||
- fsl,imx7d-iomuxc-gpr
|
||||
- const: fsl,imx6q-iomuxc-gpr
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
- items:
|
||||
|
||||
@@ -9,7 +9,7 @@ Required properties:
|
||||
number for SPI.
|
||||
|
||||
For required properties on I2C-bus, please consult
|
||||
Documentation/devicetree/bindings/i2c/i2c.txt
|
||||
dtschema schemas/i2c/i2c-controller.yaml
|
||||
For required properties on SPI-bus, please consult
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
|
||||
@@ -15,6 +15,11 @@ I. For patch submitters
|
||||
|
||||
"dt-bindings: <binding dir>: ..."
|
||||
|
||||
Few subsystems, like ASoC, media, regulators and SPI, expect reverse order
|
||||
of the prefixes::
|
||||
|
||||
"<binding dir>: dt-bindings: ..."
|
||||
|
||||
The 80 characters of the subject are precious. It is recommended to not
|
||||
use "Documentation" or "doc" because that is implied. All bindings are
|
||||
docs. Repeating "binding" again should also be avoided.
|
||||
@@ -42,28 +47,18 @@ I. For patch submitters
|
||||
the code implementing the binding.
|
||||
|
||||
6) Any compatible strings used in a chip or board DTS file must be
|
||||
previously documented in the corresponding DT binding text file
|
||||
previously documented in the corresponding DT binding file
|
||||
in Documentation/devicetree/bindings. This rule applies even if
|
||||
the Linux device driver does not yet match on the compatible
|
||||
string. [ checkpatch will emit warnings if this step is not
|
||||
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
|
||||
("checkpatch: add DT compatible string documentation checks"). ]
|
||||
|
||||
7) The wildcard "<chip>" may be used in compatible strings, as in
|
||||
the following example:
|
||||
|
||||
- compatible: Must contain '"nvidia,<chip>-pcie",
|
||||
"nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ...
|
||||
|
||||
As in the above example, the known values of "<chip>" should be
|
||||
documented if it is used.
|
||||
|
||||
8) If a documented compatible string is not yet matched by the
|
||||
7) If a documented compatible string is not yet matched by the
|
||||
driver, the documentation should also include a compatible
|
||||
string that is matched by the driver (as in the "nvidia,tegra20-pcie"
|
||||
example above).
|
||||
string that is matched by the driver.
|
||||
|
||||
9) Bindings are actively used by multiple projects other than the Linux
|
||||
8) Bindings are actively used by multiple projects other than the Linux
|
||||
Kernel, extra care and consideration may need to be taken when making changes
|
||||
to existing bindings.
|
||||
|
||||
|
||||
@@ -1,48 +0,0 @@
|
||||
MediaTek Timers
|
||||
---------------
|
||||
|
||||
MediaTek SoCs have different timers on different platforms,
|
||||
- CPUX (ARM/ARM64 System Timer)
|
||||
- GPT (General Purpose Timer)
|
||||
- SYST (System Timer)
|
||||
|
||||
The proper timer will be selected automatically by driver.
|
||||
|
||||
Required properties:
|
||||
- compatible should contain:
|
||||
For those SoCs that use GPT
|
||||
* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
|
||||
* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
|
||||
* "mediatek,mt6582-timer" for MT6582 compatible timers (GPT)
|
||||
* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
|
||||
* "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
|
||||
* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
|
||||
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
|
||||
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
|
||||
* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
|
||||
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
|
||||
|
||||
For those SoCs that use SYST
|
||||
* "mediatek,mt8183-timer" for MT8183 compatible timers (SYST)
|
||||
* "mediatek,mt8186-timer" for MT8186 compatible timers (SYST)
|
||||
* "mediatek,mt8188-timer" for MT8188 compatible timers (SYST)
|
||||
* "mediatek,mt8192-timer" for MT8192 compatible timers (SYST)
|
||||
* "mediatek,mt8195-timer" for MT8195 compatible timers (SYST)
|
||||
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
|
||||
* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
|
||||
|
||||
For those SoCs that use CPUX
|
||||
* "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)
|
||||
* "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX)
|
||||
|
||||
- reg: Should contain location and length for timer register.
|
||||
- clocks: Should contain system clock.
|
||||
|
||||
Examples:
|
||||
|
||||
timer@10008000 {
|
||||
compatible = "mediatek,mt6577-timer";
|
||||
reg = <0x10008000 0x80>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&system_clk>;
|
||||
};
|
||||
@@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/timer/mediatek,timer.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek SoC timers
|
||||
|
||||
maintainers:
|
||||
- Matthias Brugger <matthias.bgg@gmail.com>
|
||||
|
||||
description:
|
||||
MediaTek SoCs have different timers on different platforms,
|
||||
CPUX (ARM/ARM64 System Timer), GPT (General Purpose Timer)
|
||||
and SYST (System Timer).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt6577-timer
|
||||
- mediatek,mt6765-timer
|
||||
- mediatek,mt6795-systimer
|
||||
# GPT Timers
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-timer
|
||||
- mediatek,mt6580-timer
|
||||
- mediatek,mt6582-timer
|
||||
- mediatek,mt6589-timer
|
||||
- mediatek,mt7623-timer
|
||||
- mediatek,mt8127-timer
|
||||
- mediatek,mt8135-timer
|
||||
- mediatek,mt8173-timer
|
||||
- mediatek,mt8516-timer
|
||||
- const: mediatek,mt6577-timer
|
||||
# SYST Timers
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7629-timer
|
||||
- mediatek,mt8183-timer
|
||||
- mediatek,mt8186-timer
|
||||
- mediatek,mt8188-timer
|
||||
- mediatek,mt8192-timer
|
||||
- mediatek,mt8195-timer
|
||||
- mediatek,mt8365-systimer
|
||||
- const: mediatek,mt6765-timer
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Timer clock
|
||||
- description: RTC or bus clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
timer@10008000 {
|
||||
compatible = "mediatek,mt6577-timer";
|
||||
reg = <0x10008000 0x80>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&system_clk>;
|
||||
};
|
||||
@@ -9,7 +9,7 @@ title: Marvell MMP Timer
|
||||
maintainers:
|
||||
- Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
- Thomas Gleixner <tglx@linutronix.de>
|
||||
- Rob Herring <robh+dt@kernel.org>
|
||||
- Rob Herring <robh@kernel.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
|
||||
@@ -28,6 +28,7 @@ properties:
|
||||
|
||||
compatible:
|
||||
items:
|
||||
# Entries are sorted alphanumerically by the compatible
|
||||
- enum:
|
||||
# Acbel fsg032 power supply
|
||||
- acbel,fsg032
|
||||
@@ -51,12 +52,12 @@ properties:
|
||||
- asteralabs,pt5161l
|
||||
# i2c serial eeprom (24cxx)
|
||||
- at,24c08
|
||||
# i2c h/w elliptic curve crypto module
|
||||
- atmel,atecc508a
|
||||
# ATSHA204 - i2c h/w symmetric crypto module
|
||||
- atmel,atsha204
|
||||
# ATSHA204A - i2c h/w symmetric crypto module
|
||||
- atmel,atsha204a
|
||||
# i2c h/w elliptic curve crypto module
|
||||
- atmel,atecc508a
|
||||
# BPA-RS600: Power Supply
|
||||
- blutek,bpa-rs600
|
||||
# Bosch Sensortec pressure, temperature, humididty and VOC sensor
|
||||
@@ -117,22 +118,6 @@ properties:
|
||||
- fsl,mpl3115
|
||||
# MPR121: Proximity Capacitive Touch Sensor Controller
|
||||
- fsl,mpr121
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2856
|
||||
- mps,mp2856
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2857
|
||||
- mps,mp2857
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2888
|
||||
- mps,mp2888
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2971
|
||||
- mps,mp2971
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2973
|
||||
- mps,mp2973
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2975
|
||||
- mps,mp2975
|
||||
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
|
||||
- mps,mp5990
|
||||
# Monolithic Power Systems Inc. synchronous step-down converter mpq8785
|
||||
- mps,mpq8785
|
||||
# Honeywell Humidicon HIH-6130 humidity/temperature sensor
|
||||
- honeywell,hi6130
|
||||
# IBM Common Form Factor Power Supply Versions (all versions)
|
||||
@@ -141,6 +126,8 @@ properties:
|
||||
- ibm,cffps1
|
||||
# IBM Common Form Factor Power Supply Versions 2
|
||||
- ibm,cffps2
|
||||
# Infineon barometric pressure and temperature sensor
|
||||
- infineon,dps310
|
||||
# Infineon IR36021 digital POL buck controller
|
||||
- infineon,ir36021
|
||||
# Infineon IRPS5401 Voltage Regulator (PMIC)
|
||||
@@ -191,6 +178,8 @@ properties:
|
||||
- maxim,max1237
|
||||
# Temperature Sensor, I2C interface
|
||||
- maxim,max1619
|
||||
# 3-Channel Remote Temperature Sensor
|
||||
- maxim,max31730
|
||||
# 10-bit 10 kOhm linear programmable voltage divider
|
||||
- maxim,max5481
|
||||
# 10-bit 50 kOhm linear programmable voltage divider
|
||||
@@ -203,8 +192,6 @@ properties:
|
||||
- maxim,max6621
|
||||
# 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
|
||||
- maxim,max6625
|
||||
# 3-Channel Remote Temperature Sensor
|
||||
- maxim,max31730
|
||||
# mCube 3-axis 8-bit digital accelerometer
|
||||
- mcube,mc3230
|
||||
# Measurement Specialities I2C temperature and humidity sensor
|
||||
@@ -235,8 +222,6 @@ properties:
|
||||
- memsic,mxc6655
|
||||
# Menlo on-board CPLD trivial SPI device
|
||||
- menlo,m53cpld
|
||||
# Micron SPI NOR Authenta
|
||||
- micron,spi-authenta
|
||||
# Microchip differential I2C ADC, 1 Channel, 18 bit
|
||||
- microchip,mcp3421
|
||||
# Microchip differential I2C ADC, 2 Channel, 18 bit
|
||||
@@ -253,40 +238,58 @@ properties:
|
||||
- microchip,mcp3427
|
||||
# Microchip differential I2C ADC, 4 Channel, 16 bit
|
||||
- microchip,mcp3428
|
||||
# Microchip 7-bit Single I2C Digital POT (5k)
|
||||
- microchip,mcp4017-502
|
||||
# Microchip 7-bit Single I2C Digital POT (10k)
|
||||
- microchip,mcp4017-103
|
||||
# Microchip 7-bit Single I2C Digital POT (50k)
|
||||
- microchip,mcp4017-503
|
||||
# Microchip 7-bit Single I2C Digital POT (100k)
|
||||
- microchip,mcp4017-104
|
||||
# Microchip 7-bit Single I2C Digital POT (5k)
|
||||
- microchip,mcp4018-502
|
||||
- microchip,mcp4017-502
|
||||
# Microchip 7-bit Single I2C Digital POT (50k)
|
||||
- microchip,mcp4017-503
|
||||
# Microchip 7-bit Single I2C Digital POT (10k)
|
||||
- microchip,mcp4018-103
|
||||
# Microchip 7-bit Single I2C Digital POT (50k)
|
||||
- microchip,mcp4018-503
|
||||
# Microchip 7-bit Single I2C Digital POT (100k)
|
||||
- microchip,mcp4018-104
|
||||
# Microchip 7-bit Single I2C Digital POT (5k)
|
||||
- microchip,mcp4019-502
|
||||
- microchip,mcp4018-502
|
||||
# Microchip 7-bit Single I2C Digital POT (50k)
|
||||
- microchip,mcp4018-503
|
||||
# Microchip 7-bit Single I2C Digital POT (10k)
|
||||
- microchip,mcp4019-103
|
||||
# Microchip 7-bit Single I2C Digital POT (50k)
|
||||
- microchip,mcp4019-503
|
||||
# Microchip 7-bit Single I2C Digital POT (100k)
|
||||
- microchip,mcp4019-104
|
||||
# Microchip 7-bit Single I2C Digital POT (5k)
|
||||
- microchip,mcp4019-502
|
||||
# Microchip 7-bit Single I2C Digital POT (50k)
|
||||
- microchip,mcp4019-503
|
||||
# PWM Fan Speed Controller With Fan Fault Detection
|
||||
- microchip,tc654
|
||||
# PWM Fan Speed Controller With Fan Fault Detection
|
||||
- microchip,tc655
|
||||
# Micron SPI NOR Authenta
|
||||
- micron,spi-authenta
|
||||
# MiraMEMS DA226 2-axis 14-bit digital accelerometer
|
||||
- miramems,da226
|
||||
# MiraMEMS DA280 3-axis 14-bit digital accelerometer
|
||||
- miramems,da280
|
||||
# MiraMEMS DA311 3-axis 12-bit digital accelerometer
|
||||
- miramems,da311
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2856
|
||||
- mps,mp2856
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2857
|
||||
- mps,mp2857
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2888
|
||||
- mps,mp2888
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2971
|
||||
- mps,mp2971
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2973
|
||||
- mps,mp2973
|
||||
# Monolithic Power Systems Inc. multi-phase controller mp2975
|
||||
- mps,mp2975
|
||||
# Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990
|
||||
- mps,mp5990
|
||||
# Monolithic Power Systems Inc. synchronous step-down converter mpq8785
|
||||
- mps,mpq8785
|
||||
# Temperature sensor with integrated fan control
|
||||
- national,lm63
|
||||
# Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
|
||||
@@ -317,12 +320,12 @@ properties:
|
||||
- samsung,exynos-sataphy-i2c
|
||||
# Semtech sx1301 baseband processor
|
||||
- semtech,sx1301
|
||||
# Sensirion low power multi-pixel gas sensor with I2C interface
|
||||
- sensirion,sgpc3
|
||||
# Sensirion multi-pixel gas sensor with I2C interface
|
||||
- sensirion,sgp30
|
||||
# Sensirion gas sensor with I2C interface
|
||||
- sensirion,sgp40
|
||||
# Sensirion low power multi-pixel gas sensor with I2C interface
|
||||
- sensirion,sgpc3
|
||||
# Sensirion temperature & humidity sensor with I2C interface
|
||||
- sensirion,sht4x
|
||||
# Sensortek 3 axis accelerometer
|
||||
@@ -368,8 +371,6 @@ properties:
|
||||
- ti,lm74
|
||||
# Temperature sensor with integrated fan control
|
||||
- ti,lm96000
|
||||
# I2C Touch-Screen Controller
|
||||
- ti,tsc2003
|
||||
# Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
- ti,tmp103
|
||||
# Thermometer with SPI interface
|
||||
@@ -391,10 +392,12 @@ properties:
|
||||
- ti,tps544b25
|
||||
- ti,tps544c20
|
||||
- ti,tps544c25
|
||||
# Winbond/Nuvoton H/W Monitor
|
||||
- winbond,w83793
|
||||
# I2C Touch-Screen Controller
|
||||
- ti,tsc2003
|
||||
# Vicor Corporation Digital Supervisor
|
||||
- vicor,pli1209bc
|
||||
# Winbond/Nuvoton H/W Monitor
|
||||
- winbond,w83793
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/usb/cypress,hx3.yaml#
|
||||
|
||||
@@ -238,6 +238,8 @@ patternProperties:
|
||||
description: ByteDance Ltd.
|
||||
"^calamp,.*":
|
||||
description: CalAmp Corp.
|
||||
"^calao,.*":
|
||||
description: CALAO Systems SAS
|
||||
"^calaosystems,.*":
|
||||
description: CALAO Systems SAS
|
||||
"^calxeda,.*":
|
||||
@@ -486,6 +488,9 @@ patternProperties:
|
||||
description: EZchip Semiconductor
|
||||
"^facebook,.*":
|
||||
description: Facebook
|
||||
"^fairchild,.*":
|
||||
description: Fairchild Semiconductor (deprecated, use 'onnn')
|
||||
deprecated: true
|
||||
"^fairphone,.*":
|
||||
description: Fairphone B.V.
|
||||
"^faraday,.*":
|
||||
@@ -552,6 +557,8 @@ patternProperties:
|
||||
description: Giantec Semiconductor, Inc.
|
||||
"^giantplus,.*":
|
||||
description: Giantplus Technology Co., Ltd.
|
||||
"^glinet,.*":
|
||||
description: GL Intelligence, Inc.
|
||||
"^globalscale,.*":
|
||||
description: Globalscale Technologies, Inc.
|
||||
"^globaltop,.*":
|
||||
@@ -611,6 +618,8 @@ patternProperties:
|
||||
description: Honestar Technologies Co., Ltd.
|
||||
"^honeywell,.*":
|
||||
description: Honeywell
|
||||
"^hoperf,.*":
|
||||
description: Shenzhen Hope Microelectronics Co., Ltd.
|
||||
"^hoperun,.*":
|
||||
description: Jiangsu HopeRun Software Co., Ltd.
|
||||
"^hp,.*":
|
||||
@@ -641,12 +650,16 @@ patternProperties:
|
||||
description: Hyundai Technology
|
||||
"^i2se,.*":
|
||||
description: I2SE GmbH
|
||||
"^IBM,.*":
|
||||
description: International Business Machines (IBM)
|
||||
"^ibm,.*":
|
||||
description: International Business Machines (IBM)
|
||||
"^icplus,.*":
|
||||
description: IC Plus Corp.
|
||||
"^idt,.*":
|
||||
description: Integrated Device Technologies, Inc.
|
||||
"^iei,.*":
|
||||
description: IEI Integration Corp.
|
||||
"^ifi,.*":
|
||||
description: Ingenieurburo Fur Ic-Technologie (I/F/I)
|
||||
"^ilitek,.*":
|
||||
@@ -833,6 +846,8 @@ patternProperties:
|
||||
description: LSI Corp. (LSI Logic)
|
||||
"^lunzn,.*":
|
||||
description: Shenzhen Lunzn Technology Co., Ltd.
|
||||
"^luxul,.*":
|
||||
description: Lagrand | AV
|
||||
"^lwn,.*":
|
||||
description: Liebherr-Werk Nenzing GmbH
|
||||
"^lxa,.*":
|
||||
@@ -911,6 +926,9 @@ patternProperties:
|
||||
description: Miniand Tech
|
||||
"^minix,.*":
|
||||
description: MINIX Technology Ltd.
|
||||
"^mips,.*":
|
||||
description: MIPS Technology (deprecated, use 'mti' or 'img')
|
||||
deprecated: true
|
||||
"^miramems,.*":
|
||||
description: MiraMEMS Sensing Technology Co., Ltd.
|
||||
"^mitsubishi,.*":
|
||||
@@ -923,6 +941,8 @@ patternProperties:
|
||||
description: Miyoo
|
||||
"^mntre,.*":
|
||||
description: MNT Research GmbH
|
||||
"^mobileye,.*":
|
||||
description: Mobileye Vision Technologies Ltd.
|
||||
"^modtronix,.*":
|
||||
description: Modtronix Engineering
|
||||
"^moortec,.*":
|
||||
@@ -1005,6 +1025,9 @@ patternProperties:
|
||||
description: Novatek
|
||||
"^novtech,.*":
|
||||
description: NovTech, Inc.
|
||||
"^numonyx,.*":
|
||||
description: Numonyx (deprecated, use micron)
|
||||
deprecated: true
|
||||
"^nutsboard,.*":
|
||||
description: NutsBoard
|
||||
"^nuvoton,.*":
|
||||
@@ -1309,6 +1332,8 @@ patternProperties:
|
||||
description: Skyworks Solutions, Inc.
|
||||
"^smartlabs,.*":
|
||||
description: SmartLabs LLC
|
||||
"^smartrg,.*":
|
||||
description: SmartRG, Inc.
|
||||
"^smi,.*":
|
||||
description: Silicon Motion Technology Corporation
|
||||
"^smsc,.*":
|
||||
@@ -1550,8 +1575,12 @@ patternProperties:
|
||||
description: Voipac Technologies s.r.o.
|
||||
"^vot,.*":
|
||||
description: Vision Optical Technology Co., Ltd.
|
||||
"^vscom,.*":
|
||||
description: VS Visions Systems GmbH
|
||||
"^vxt,.*":
|
||||
description: VXT Ltd
|
||||
"^wacom,.*":
|
||||
description: Wacom
|
||||
"^wanchanglong,.*":
|
||||
description: Wanchanglong Electronics Technology（SHENZHEN）Co.，Ltd.
|
||||
"^wand,.*":
|
||||
|
||||
@@ -50,6 +50,10 @@ properties:
|
||||
- const: wdog_clk
|
||||
- const: apb_pclk
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
description: WDOGRESn input reset signal for sp805 module.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -67,4 +71,5 @@ examples:
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&wdt_clk>, <&apb_pclk>;
|
||||
clock-names = "wdog_clk", "apb_pclk";
|
||||
resets = <&wdt_rst>;
|
||||
};
|
||||
|
||||
@@ -14,10 +14,14 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- atmel,sama5d4-wdt
|
||||
- microchip,sam9x60-wdt
|
||||
- microchip,sama7g5-wdt
|
||||
oneOf:
|
||||
- enum:
|
||||
- atmel,sama5d4-wdt
|
||||
- microchip,sam9x60-wdt
|
||||
- microchip,sama7g5-wdt
|
||||
- items:
|
||||
- const: microchip,sam9x7-wdt
|
||||
- const: microchip,sam9x60-wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -1,18 +0,0 @@
|
||||
BCM2835 Watchdog timer
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "brcm,bcm2835-pm-wdt"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- timeout-sec : Contains the watchdog timeout in seconds
|
||||
|
||||
Example:
|
||||
|
||||
watchdog {
|
||||
compatible = "brcm,bcm2835-pm-wdt";
|
||||
reg = <0x7e100000 0x28>;
|
||||
timeout-sec = <10>;
|
||||
};
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
|
||||
|
||||
maintainers:
|
||||
- Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
|
||||
- Rajendra Nayak <quic_rjendra@quicinc.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
|
||||
@@ -71,6 +71,7 @@ properties:
|
||||
- renesas,r8a779a0-wdt # R-Car V3U
|
||||
- renesas,r8a779f0-wdt # R-Car S4-8
|
||||
- renesas,r8a779g0-wdt # R-Car V4H
|
||||
- renesas,r8a779h0-wdt # R-Car V4M
|
||||
- const: renesas,rcar-gen4-wdt # R-Car Gen4
|
||||
|
||||
reg:
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/watchdog/sprd,sp9860-wdt.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Spreadtrum SP9860 watchdog timer
|
||||
|
||||
maintainers:
|
||||
- Orson Zhai <orsonzhai@gmail.com>
|
||||
- Baolin Wang <baolin.wang7@gmail.com>
|
||||
- Chunyan Zhang <zhang.lyra@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: watchdog.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sprd,sp9860-wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: enable
|
||||
- const: rtc_enable
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- timeout-sec
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sprd,sc9860-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
watchdog@40310000 {
|
||||
compatible = "sprd,sp9860-wdt";
|
||||
reg = <0 0x40310000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&aon_gate CLK_APCPU_WDG_EB>, <&aon_gate CLK_AP_WDG_RTC_EB>;
|
||||
clock-names = "enable", "rtc_enable";
|
||||
timeout-sec = <12>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -1,19 +0,0 @@
|
||||
Spreadtrum SoCs Watchdog timer
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "sprd,sp9860-wdt".
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : Exactly one interrupt specifier.
|
||||
- timeout-sec : Contain the default watchdog timeout in seconds.
|
||||
- clock-names : Contain the input clock names.
|
||||
- clocks : Phandles to input clocks.
|
||||
|
||||
Example:
|
||||
watchdog: watchdog@40310000 {
|
||||
compatible = "sprd,sp9860-wdt";
|
||||
reg = <0 0x40310000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-sec = <12>;
|
||||
clock-names = "enable", "rtc_enable";
|
||||
clocks = <&clk_aon_apb_gates1 8>, <&clk_aon_apb_rtc_gates 9>;
|
||||
};
|
||||
@@ -19,14 +19,16 @@ description:
|
||||
isn't cleared, the watchdog will reset the system unless the watchdog
|
||||
reset is disabled.
|
||||
|
||||
allOf:
|
||||
- $ref: watchdog.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- starfive,jh7100-wdt
|
||||
- starfive,jh7110-wdt
|
||||
oneOf:
|
||||
- enum:
|
||||
- starfive,jh7100-wdt
|
||||
- starfive,jh7110-wdt
|
||||
- items:
|
||||
- enum:
|
||||
- starfive,jh8100-wdt
|
||||
- const: starfive,jh7110-wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -45,9 +47,8 @@ properties:
|
||||
- const: core
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: APB reset
|
||||
- description: Core reset
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@@ -56,6 +57,27 @@ required:
|
||||
- clock-names
|
||||
- resets
|
||||
|
||||
allOf:
|
||||
- $ref: watchdog.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- starfive,jh8100-wdt
|
||||
then:
|
||||
properties:
|
||||
resets:
|
||||
items:
|
||||
- description: Core reset
|
||||
else:
|
||||
properties:
|
||||
resets:
|
||||
items:
|
||||
- description: APB reset
|
||||
- description: Core reset
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -31,7 +31,7 @@ $schema
|
||||
Indicates the meta-schema the schema file adheres to.
|
||||
|
||||
title
|
||||
A one-line description on the contents of the binding schema.
|
||||
A one-line description of the hardware being described in the binding schema.
|
||||
|
||||
maintainers
|
||||
A DT specific property. Contains a list of email address(es)
|
||||
@@ -39,7 +39,7 @@ maintainers
|
||||
|
||||
description
|
||||
Optional. A multi-line text block containing any detailed
|
||||
information about this binding. It should contain things such as what the block
|
||||
information about this hardware. It should contain things such as what the block
|
||||
or device does, standards the device conforms to, and links to datasheets for
|
||||
more information.
|
||||
|
||||
@@ -71,9 +71,31 @@ required
|
||||
A list of DT properties from the 'properties' section that
|
||||
must always be present.
|
||||
|
||||
additionalProperties / unevaluatedProperties
|
||||
Keywords controlling how schema will validate properties not matched by this
|
||||
schema's 'properties' or 'patternProperties'. Each schema is supposed to
|
||||
have exactly one of these keywords in top-level part, so either
|
||||
additionalProperties or unevaluatedProperties. Nested nodes, so properties
|
||||
being objects, are supposed to have one as well.
|
||||
|
||||
* additionalProperties: false
|
||||
Most common case, where no additional schema is referenced or if this
|
||||
binding allows subset of properties from other referenced schemas.
|
||||
|
||||
* unevaluatedProperties: false
|
||||
Used when this binding references other schema whose all properties
|
||||
should be allowed.
|
||||
|
||||
* additionalProperties: true
|
||||
Rare case, used for schemas implementing common set of properties. Such
|
||||
schemas are supposed to be referenced by other schemas, which then use
|
||||
'unevaluatedProperties: false'. Typically bus or common-part schemas.
|
||||
|
||||
examples
|
||||
Optional. A list of one or more DTS hunks implementing the
|
||||
binding. Note: YAML doesn't allow leading tabs, so spaces must be used instead.
|
||||
Optional. A list of one or more DTS hunks implementing this binding only.
|
||||
Example should not contain unrelated device nodes, e.g. consumer nodes in a
|
||||
provider binding, other nodes referenced by phandle.
|
||||
Note: YAML doesn't allow leading tabs, so spaces must be used instead.
|
||||
|
||||
Unless noted otherwise, all properties are required.
|
||||
|
||||
|
||||
@@ -32,6 +32,10 @@ configuration::
|
||||
CONFIG_ACPI_APEI
|
||||
CONFIG_ACPI_APEI_EINJ
|
||||
|
||||
...and to (optionally) enable CXL protocol error injection set::
|
||||
|
||||
CONFIG_ACPI_APEI_EINJ_CXL
|
||||
|
||||
The EINJ user interface is in <debugfs mount point>/apei/einj.
|
||||
|
||||
The following files belong to it:
|
||||
@@ -118,6 +122,24 @@ The following files belong to it:
|
||||
this actually works depends on what operations the BIOS actually
|
||||
includes in the trigger phase.
|
||||
|
||||
CXL error types are supported from ACPI 6.5 onwards (given a CXL port
|
||||
is present). The EINJ user interface for CXL error types is at
|
||||
<debugfs mount point>/cxl. The following files belong to it:
|
||||
|
||||
- einj_types:
|
||||
|
||||
Provides the same functionality as available_error_types above, but
|
||||
for CXL error types
|
||||
|
||||
- $dport_dev/einj_inject:
|
||||
|
||||
Injects a CXL error type into the CXL port represented by $dport_dev,
|
||||
where $dport_dev is the name of the CXL port (usually a PCIe device name).
|
||||
Error injections targeting a CXL 2.0+ port can use the legacy interface
|
||||
under <debugfs mount point>/apei/einj, while CXL 1.1/1.0 port injections
|
||||
must use this file.
|
||||
|
||||
|
||||
BIOS versions based on the ACPI 4.0 specification have limited options
|
||||
in controlling where the errors are injected. Your BIOS may support an
|
||||
extension (enabled with the param_extension=1 module parameter, or boot
|
||||
@@ -181,6 +203,18 @@ You should see something like this in dmesg::
|
||||
[22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0
|
||||
[22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0)
|
||||
|
||||
A CXL error injection example with $dport_dev=0000:e0:01.1::
|
||||
|
||||
# cd /sys/kernel/debug/cxl/
|
||||
# ls
|
||||
0000:e0:01.1 0000:0c:00.0
|
||||
# cat einj_types # See which errors can be injected
|
||||
0x00008000 CXL.mem Protocol Correctable
|
||||
0x00010000 CXL.mem Protocol Uncorrectable non-fatal
|
||||
0x00020000 CXL.mem Protocol Uncorrectable fatal
|
||||
# cd 0000:e0:01.1 # Navigate to dport to inject into
|
||||
# echo 0x8000 > einj_inject # Inject error
|
||||
|
||||
Special notes for injection into SGX enclaves:
|
||||
|
||||
There may be a separate BIOS setup option to enable SGX injection.
|
||||
|
||||
@@ -29,7 +29,7 @@ follows:
|
||||
- Does not support shared LDPC code table wraparound
|
||||
|
||||
The device tree entry is described in:
|
||||
`linux-xlnx/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt <https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/misc/xlnx%2Csd-fec.txt>`_
|
||||
`linux-xlnx/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml <https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/misc/xlnx%2Csd-fec.yaml>`_
|
||||
|
||||
|
||||
Modes of Operation
|
||||
|
||||
@@ -372,7 +372,7 @@ The bits in the dirty bitmap are cleared before the ioctl returns, unless
|
||||
KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2 is enabled. For more information,
|
||||
see the description of the capability.
|
||||
|
||||
Note that the Xen shared info page, if configured, shall always be assumed
|
||||
Note that the Xen shared_info page, if configured, shall always be assumed
|
||||
to be dirty. KVM will not explicitly mark it such.
|
||||
|
||||
|
||||
@@ -5487,8 +5487,9 @@ KVM_PV_ASYNC_CLEANUP_PERFORM
|
||||
__u8 long_mode;
|
||||
__u8 vector;
|
||||
__u8 runstate_update_flag;
|
||||
struct {
|
||||
union {
|
||||
__u64 gfn;
|
||||
__u64 hva;
|
||||
} shared_info;
|
||||
struct {
|
||||
__u32 send_port;
|
||||
@@ -5516,19 +5517,20 @@ type values:
|
||||
|
||||
KVM_XEN_ATTR_TYPE_LONG_MODE
|
||||
Sets the ABI mode of the VM to 32-bit or 64-bit (long mode). This
|
||||
determines the layout of the shared info pages exposed to the VM.
|
||||
determines the layout of the shared_info page exposed to the VM.
|
||||
|
||||
KVM_XEN_ATTR_TYPE_SHARED_INFO
|
||||
Sets the guest physical frame number at which the Xen "shared info"
|
||||
Sets the guest physical frame number at which the Xen shared_info
|
||||
page resides. Note that although Xen places vcpu_info for the first
|
||||
32 vCPUs in the shared_info page, KVM does not automatically do so
|
||||
and instead requires that KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO be used
|
||||
explicitly even when the vcpu_info for a given vCPU resides at the
|
||||
"default" location in the shared_info page. This is because KVM may
|
||||
not be aware of the Xen CPU id which is used as the index into the
|
||||
vcpu_info[] array, so may know the correct default location.
|
||||
and instead requires that KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO or
|
||||
KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA be used explicitly even when
|
||||
the vcpu_info for a given vCPU resides at the "default" location
|
||||
in the shared_info page. This is because KVM may not be aware of
|
||||
the Xen CPU id which is used as the index into the vcpu_info[]
|
||||
array, so may know the correct default location.
|
||||
|
||||
Note that the shared info page may be constantly written to by KVM;
|
||||
Note that the shared_info page may be constantly written to by KVM;
|
||||
it contains the event channel bitmap used to deliver interrupts to
|
||||
a Xen guest, amongst other things. It is exempt from dirty tracking
|
||||
mechanisms — KVM will not explicitly mark the page as dirty each
|
||||
@@ -5537,9 +5539,21 @@ KVM_XEN_ATTR_TYPE_SHARED_INFO
|
||||
any vCPU has been running or any event channel interrupts can be
|
||||
routed to the guest.
|
||||
|
||||
Setting the gfn to KVM_XEN_INVALID_GFN will disable the shared info
|
||||
Setting the gfn to KVM_XEN_INVALID_GFN will disable the shared_info
|
||||
page.
|
||||
|
||||
KVM_XEN_ATTR_TYPE_SHARED_INFO_HVA
|
||||
If the KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA flag is also set in the
|
||||
Xen capabilities, then this attribute may be used to set the
|
||||
userspace address at which the shared_info page resides, which
|
||||
will always be fixed in the VMM regardless of where it is mapped
|
||||
in guest physical address space. This attribute should be used in
|
||||
preference to KVM_XEN_ATTR_TYPE_SHARED_INFO as it avoids
|
||||
unnecessary invalidation of an internal cache when the page is
|
||||
re-mapped in guest physcial address space.
|
||||
|
||||
Setting the hva to zero will disable the shared_info page.
|
||||
|
||||
KVM_XEN_ATTR_TYPE_UPCALL_VECTOR
|
||||
Sets the exception vector used to deliver Xen event channel upcalls.
|
||||
This is the HVM-wide vector injected directly by the hypervisor
|
||||
@@ -5636,6 +5650,21 @@ KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO
|
||||
on dirty logging. Setting the gpa to KVM_XEN_INVALID_GPA will disable
|
||||
the vcpu_info.
|
||||
|
||||
KVM_XEN_VCPU_ATTR_TYPE_VCPU_INFO_HVA
|
||||
If the KVM_XEN_HVM_CONFIG_SHARED_INFO_HVA flag is also set in the
|
||||
Xen capabilities, then this attribute may be used to set the
|
||||
userspace address of the vcpu_info for a given vCPU. It should
|
||||
only be used when the vcpu_info resides at the "default" location
|
||||
in the shared_info page. In this case it is safe to assume the
|
||||
userspace address will not change, because the shared_info page is
|
||||
an overlay on guest memory and remains at a fixed host address
|
||||
regardless of where it is mapped in guest physical address space
|
||||
and hence unnecessary invalidation of an internal cache may be
|
||||
avoided if the guest memory layout is modified.
|
||||
If the vcpu_info does not reside at the "default" location then
|
||||
it is not guaranteed to remain at the same host address and
|
||||
hence the aforementioned cache invalidation is required.
|
||||
|
||||
KVM_XEN_VCPU_ATTR_TYPE_VCPU_TIME_INFO
|
||||
Sets the guest physical address of an additional pvclock structure
|
||||
for a given vCPU. This is typically used for guest vsyscall support.
|
||||
|
||||
+58
-22
@@ -5321,6 +5321,7 @@ M: Dan Williams <dan.j.williams@intel.com>
|
||||
L: linux-cxl@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/cxl/
|
||||
F: include/linux/cxl-einj.h
|
||||
F: include/linux/cxl-event.h
|
||||
F: include/uapi/linux/cxl_mem.h
|
||||
F: tools/testing/cxl/
|
||||
@@ -10158,7 +10159,6 @@ S: Maintained
|
||||
W: https://i2c.wiki.kernel.org/
|
||||
Q: https://patchwork.ozlabs.org/project/linux-i2c/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git
|
||||
F: Documentation/devicetree/bindings/i2c/i2c.txt
|
||||
F: Documentation/i2c/
|
||||
F: drivers/i2c/*
|
||||
F: include/dt-bindings/i2c/i2c.h
|
||||
@@ -10378,12 +10378,17 @@ M: Nayna Jain <nayna@linux.ibm.com>
|
||||
M: Paulo Flabiano Smorigo <pfsmorigo@gmail.com>
|
||||
L: linux-crypto@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/crypto/vmx/Kconfig
|
||||
F: drivers/crypto/vmx/Makefile
|
||||
F: drivers/crypto/vmx/aes*
|
||||
F: drivers/crypto/vmx/ghash*
|
||||
F: drivers/crypto/vmx/ppc-xlate.pl
|
||||
F: drivers/crypto/vmx/vmx.c
|
||||
F: arch/powerpc/crypto/Kconfig
|
||||
F: arch/powerpc/crypto/Makefile
|
||||
F: arch/powerpc/crypto/aes.c
|
||||
F: arch/powerpc/crypto/aes_cbc.c
|
||||
F: arch/powerpc/crypto/aes_ctr.c
|
||||
F: arch/powerpc/crypto/aes_xts.c
|
||||
F: arch/powerpc/crypto/aesp8-ppc.*
|
||||
F: arch/powerpc/crypto/ghash.c
|
||||
F: arch/powerpc/crypto/ghashp8-ppc.pl
|
||||
F: arch/powerpc/crypto/ppc-xlate.pl
|
||||
F: arch/powerpc/crypto/vmx.c
|
||||
|
||||
IBM ServeRAID RAID DRIVER
|
||||
S: Orphan
|
||||
@@ -12464,7 +12469,6 @@ F: drivers/*/*/*pasemi*
|
||||
F: drivers/*/*pasemi*
|
||||
F: drivers/char/tpm/tpm_ibmvtpm*
|
||||
F: drivers/crypto/nx/
|
||||
F: drivers/crypto/vmx/
|
||||
F: drivers/i2c/busses/i2c-opal.c
|
||||
F: drivers/net/ethernet/ibm/ibmveth.*
|
||||
F: drivers/net/ethernet/ibm/ibmvnic.*
|
||||
@@ -13803,6 +13807,13 @@ F: Documentation/devicetree/bindings/media/mediatek-vpu.txt
|
||||
F: drivers/media/platform/mediatek/vcodec/
|
||||
F: drivers/media/platform/mediatek/vpu/
|
||||
|
||||
MEDIATEK MIPI-CSI CDPHY DRIVER
|
||||
M: Julien Stephan <jstephan@baylibre.com>
|
||||
M: Andy Hsieh <andy.hsieh@mediatek.com>
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
|
||||
F: drivers/phy/mediatek/phy-mtk-mipi-csi-0-5*
|
||||
|
||||
MEDIATEK MMC/SD/SDIO DRIVER
|
||||
M: Chaotian Jing <chaotian.jing@mediatek.com>
|
||||
S: Maintained
|
||||
@@ -14312,7 +14323,6 @@ F: drivers/misc/xilinx_tmr_manager.c
|
||||
|
||||
MICROCHIP AT91 DMA DRIVERS
|
||||
M: Ludovic Desroches <ludovic.desroches@microchip.com>
|
||||
M: Tudor Ambarus <tudor.ambarus@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: dmaengine@vger.kernel.org
|
||||
S: Supported
|
||||
@@ -14361,9 +14371,8 @@ F: Documentation/devicetree/bindings/media/microchip,csi2dc.yaml
|
||||
F: drivers/media/platform/microchip/microchip-csi2dc.c
|
||||
|
||||
MICROCHIP ECC DRIVER
|
||||
M: Tudor Ambarus <tudor.ambarus@linaro.org>
|
||||
L: linux-crypto@vger.kernel.org
|
||||
S: Maintained
|
||||
S: Orphan
|
||||
F: drivers/crypto/atmel-ecc.*
|
||||
|
||||
MICROCHIP EIC DRIVER
|
||||
@@ -14468,9 +14477,8 @@ S: Maintained
|
||||
F: drivers/mmc/host/atmel-mci.c
|
||||
|
||||
MICROCHIP NAND DRIVER
|
||||
M: Tudor Ambarus <tudor.ambarus@linaro.org>
|
||||
L: linux-mtd@lists.infradead.org
|
||||
S: Supported
|
||||
S: Orphan
|
||||
F: Documentation/devicetree/bindings/mtd/atmel-nand.txt
|
||||
F: drivers/mtd/nand/raw/atmel/*
|
||||
|
||||
@@ -14749,6 +14757,17 @@ F: arch/mips/
|
||||
F: drivers/platform/mips/
|
||||
F: include/dt-bindings/mips/
|
||||
|
||||
MIPS BAIKAL-T1 PLATFORM
|
||||
M: Serge Semin <fancer.lancer@gmail.com>
|
||||
L: linux-mips@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/bus/baikal,bt1-*.yaml
|
||||
F: Documentation/devicetree/bindings/clock/baikal,bt1-*.yaml
|
||||
F: drivers/bus/bt1-*.c
|
||||
F: drivers/clk/baikal-t1/
|
||||
F: drivers/memory/bt1-l2-ctl.c
|
||||
F: drivers/mtd/maps/physmap-bt1-rom.[ch]
|
||||
|
||||
MIPS BOSTON DEVELOPMENT BOARD
|
||||
M: Paul Burton <paulburton@kernel.org>
|
||||
L: linux-mips@vger.kernel.org
|
||||
@@ -14869,6 +14888,17 @@ W: https://linuxtv.org
|
||||
Q: http://patchwork.linuxtv.org/project/linux-media/list/
|
||||
F: drivers/media/dvb-frontends/mn88473*
|
||||
|
||||
MOBILEYE MIPS SOCS
|
||||
M: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
|
||||
M: Gregory CLEMENT <gregory.clement@bootlin.com>
|
||||
M: Théo Lebrun <theo.lebrun@bootlin.com>
|
||||
L: linux-mips@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/mips/mobileye.yaml
|
||||
F: arch/mips/boot/dts/mobileye/
|
||||
F: arch/mips/configs/eyeq5_defconfig
|
||||
F: arch/mips/mobileye/board-epm5.its.S
|
||||
|
||||
MODULE SUPPORT
|
||||
M: Luis Chamberlain <mcgrof@kernel.org>
|
||||
L: linux-modules@vger.kernel.org
|
||||
@@ -16441,8 +16471,8 @@ S: Supported
|
||||
F: drivers/infiniband/ulp/opa_vnic
|
||||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
M: Frank Rowand <frowand.list@gmail.com>
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
M: Saravana Kannan <saravanak@google.com>
|
||||
L: devicetree@vger.kernel.org
|
||||
S: Maintained
|
||||
W: http://www.devicetree.org/
|
||||
@@ -16458,7 +16488,7 @@ K: of_overlay_fdt_apply
|
||||
K: of_overlay_remove
|
||||
|
||||
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
|
||||
M: Rob Herring <robh+dt@kernel.org>
|
||||
M: Rob Herring <robh@kernel.org>
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
|
||||
M: Conor Dooley <conor+dt@kernel.org>
|
||||
L: devicetree@vger.kernel.org
|
||||
@@ -23150,12 +23180,11 @@ L: kvm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/vfio/pci/mlx5/
|
||||
|
||||
VFIO VIRTIO PCI DRIVER
|
||||
M: Yishai Hadas <yishaih@nvidia.com>
|
||||
VFIO NVIDIA GRACE GPU DRIVER
|
||||
M: Ankit Agrawal <ankita@nvidia.com>
|
||||
L: kvm@vger.kernel.org
|
||||
L: virtualization@lists.linux.dev
|
||||
S: Maintained
|
||||
F: drivers/vfio/pci/virtio
|
||||
S: Supported
|
||||
F: drivers/vfio/pci/nvgrace-gpu/
|
||||
|
||||
VFIO PCI DEVICE SPECIFIC DRIVERS
|
||||
R: Jason Gunthorpe <jgg@nvidia.com>
|
||||
@@ -23180,6 +23209,13 @@ L: kvm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/vfio/platform/
|
||||
|
||||
VFIO VIRTIO PCI DRIVER
|
||||
M: Yishai Hadas <yishaih@nvidia.com>
|
||||
L: kvm@vger.kernel.org
|
||||
L: virtualization@lists.linux.dev
|
||||
S: Maintained
|
||||
F: drivers/vfio/pci/virtio
|
||||
|
||||
VGA_SWITCHEROO
|
||||
R: Lukas Wunner <lukas@wunner.de>
|
||||
S: Maintained
|
||||
@@ -24233,7 +24269,7 @@ XILINX SD-FEC IP CORES
|
||||
M: Derek Kiernan <derek.kiernan@amd.com>
|
||||
M: Dragan Cvetic <dragan.cvetic@amd.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt
|
||||
F: Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
|
||||
F: Documentation/misc-devices/xilinx_sdfec.rst
|
||||
F: drivers/misc/Kconfig
|
||||
F: drivers/misc/Makefile
|
||||
|
||||
@@ -24,8 +24,8 @@
|
||||
|
||||
#include "sha256_glue.h"
|
||||
|
||||
asmlinkage void sha256_block_data_order(u32 *digest, const void *data,
|
||||
unsigned int num_blks);
|
||||
asmlinkage void sha256_block_data_order(struct sha256_state *state,
|
||||
const u8 *data, int num_blks);
|
||||
|
||||
int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int len)
|
||||
@@ -33,23 +33,20 @@ int crypto_sha256_arm_update(struct shash_desc *desc, const u8 *data,
|
||||
/* make sure casting to sha256_block_fn() is safe */
|
||||
BUILD_BUG_ON(offsetof(struct sha256_state, state) != 0);
|
||||
|
||||
return sha256_base_do_update(desc, data, len,
|
||||
(sha256_block_fn *)sha256_block_data_order);
|
||||
return sha256_base_do_update(desc, data, len, sha256_block_data_order);
|
||||
}
|
||||
EXPORT_SYMBOL(crypto_sha256_arm_update);
|
||||
|
||||
static int crypto_sha256_arm_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
sha256_base_do_finalize(desc,
|
||||
(sha256_block_fn *)sha256_block_data_order);
|
||||
sha256_base_do_finalize(desc, sha256_block_data_order);
|
||||
return sha256_base_finish(desc, out);
|
||||
}
|
||||
|
||||
int crypto_sha256_arm_finup(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int len, u8 *out)
|
||||
{
|
||||
sha256_base_do_update(desc, data, len,
|
||||
(sha256_block_fn *)sha256_block_data_order);
|
||||
sha256_base_do_update(desc, data, len, sha256_block_data_order);
|
||||
return crypto_sha256_arm_final(desc, out);
|
||||
}
|
||||
EXPORT_SYMBOL(crypto_sha256_arm_finup);
|
||||
|
||||
@@ -25,27 +25,25 @@ MODULE_ALIAS_CRYPTO("sha512");
|
||||
MODULE_ALIAS_CRYPTO("sha384-arm");
|
||||
MODULE_ALIAS_CRYPTO("sha512-arm");
|
||||
|
||||
asmlinkage void sha512_block_data_order(u64 *state, u8 const *src, int blocks);
|
||||
asmlinkage void sha512_block_data_order(struct sha512_state *state,
|
||||
u8 const *src, int blocks);
|
||||
|
||||
int sha512_arm_update(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int len)
|
||||
{
|
||||
return sha512_base_do_update(desc, data, len,
|
||||
(sha512_block_fn *)sha512_block_data_order);
|
||||
return sha512_base_do_update(desc, data, len, sha512_block_data_order);
|
||||
}
|
||||
|
||||
static int sha512_arm_final(struct shash_desc *desc, u8 *out)
|
||||
{
|
||||
sha512_base_do_finalize(desc,
|
||||
(sha512_block_fn *)sha512_block_data_order);
|
||||
sha512_base_do_finalize(desc, sha512_block_data_order);
|
||||
return sha512_base_finish(desc, out);
|
||||
}
|
||||
|
||||
int sha512_arm_finup(struct shash_desc *desc, const u8 *data,
|
||||
unsigned int len, u8 *out)
|
||||
{
|
||||
sha512_base_do_update(desc, data, len,
|
||||
(sha512_block_fn *)sha512_block_data_order);
|
||||
sha512_base_do_update(desc, data, len, sha512_block_data_order);
|
||||
return sha512_arm_final(desc, out);
|
||||
}
|
||||
|
||||
|
||||
@@ -216,7 +216,6 @@ config ARM64
|
||||
select HAVE_HW_BREAKPOINT if PERF_EVENTS
|
||||
select HAVE_IOREMAP_PROT
|
||||
select HAVE_IRQ_TIME_ACCOUNTING
|
||||
select HAVE_KVM
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select HAVE_NMI
|
||||
select HAVE_PERF_EVENTS
|
||||
|
||||
@@ -268,6 +268,7 @@ config CRYPTO_AES_ARM64_CE_CCM
|
||||
depends on ARM64 && KERNEL_MODE_NEON
|
||||
select CRYPTO_ALGAPI
|
||||
select CRYPTO_AES_ARM64_CE
|
||||
select CRYPTO_AES_ARM64_CE_BLK
|
||||
select CRYPTO_AEAD
|
||||
select CRYPTO_LIB_AES
|
||||
help
|
||||
|
||||
@@ -1,8 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
|
||||
* aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
|
||||
*
|
||||
* Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
|
||||
* Copyright (C) 2013 - 2017 Linaro Ltd.
|
||||
* Copyright (C) 2024 Google LLC
|
||||
*
|
||||
* Author: Ard Biesheuvel <ardb@kernel.org>
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
@@ -11,211 +14,129 @@
|
||||
.text
|
||||
.arch armv8-a+crypto
|
||||
|
||||
/*
|
||||
* u32 ce_aes_ccm_auth_data(u8 mac[], u8 const in[], u32 abytes,
|
||||
* u32 macp, u8 const rk[], u32 rounds);
|
||||
*/
|
||||
SYM_FUNC_START(ce_aes_ccm_auth_data)
|
||||
ld1 {v0.16b}, [x0] /* load mac */
|
||||
cbz w3, 1f
|
||||
sub w3, w3, #16
|
||||
eor v1.16b, v1.16b, v1.16b
|
||||
0: ldrb w7, [x1], #1 /* get 1 byte of input */
|
||||
subs w2, w2, #1
|
||||
add w3, w3, #1
|
||||
ins v1.b[0], w7
|
||||
ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
|
||||
beq 8f /* out of input? */
|
||||
cbnz w3, 0b
|
||||
eor v0.16b, v0.16b, v1.16b
|
||||
1: ld1 {v3.4s}, [x4] /* load first round key */
|
||||
prfm pldl1strm, [x1]
|
||||
cmp w5, #12 /* which key size? */
|
||||
add x6, x4, #16
|
||||
sub w7, w5, #2 /* modified # of rounds */
|
||||
bmi 2f
|
||||
bne 5f
|
||||
mov v5.16b, v3.16b
|
||||
b 4f
|
||||
2: mov v4.16b, v3.16b
|
||||
ld1 {v5.4s}, [x6], #16 /* load 2nd round key */
|
||||
3: aese v0.16b, v4.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
4: ld1 {v3.4s}, [x6], #16 /* load next round key */
|
||||
aese v0.16b, v5.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
5: ld1 {v4.4s}, [x6], #16 /* load next round key */
|
||||
subs w7, w7, #3
|
||||
aese v0.16b, v3.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
ld1 {v5.4s}, [x6], #16 /* load next round key */
|
||||
bpl 3b
|
||||
aese v0.16b, v4.16b
|
||||
subs w2, w2, #16 /* last data? */
|
||||
eor v0.16b, v0.16b, v5.16b /* final round */
|
||||
bmi 6f
|
||||
ld1 {v1.16b}, [x1], #16 /* load next input block */
|
||||
eor v0.16b, v0.16b, v1.16b /* xor with mac */
|
||||
bne 1b
|
||||
6: st1 {v0.16b}, [x0] /* store mac */
|
||||
beq 10f
|
||||
adds w2, w2, #16
|
||||
beq 10f
|
||||
mov w3, w2
|
||||
7: ldrb w7, [x1], #1
|
||||
umov w6, v0.b[0]
|
||||
eor w6, w6, w7
|
||||
strb w6, [x0], #1
|
||||
subs w2, w2, #1
|
||||
beq 10f
|
||||
ext v0.16b, v0.16b, v0.16b, #1 /* rotate out the mac bytes */
|
||||
b 7b
|
||||
8: cbz w3, 91f
|
||||
mov w7, w3
|
||||
add w3, w3, #16
|
||||
9: ext v1.16b, v1.16b, v1.16b, #1
|
||||
adds w7, w7, #1
|
||||
bne 9b
|
||||
91: eor v0.16b, v0.16b, v1.16b
|
||||
st1 {v0.16b}, [x0]
|
||||
10: mov w0, w3
|
||||
ret
|
||||
SYM_FUNC_END(ce_aes_ccm_auth_data)
|
||||
.macro load_round_keys, rk, nr, tmp
|
||||
sub w\tmp, \nr, #10
|
||||
add \tmp, \rk, w\tmp, sxtw #4
|
||||
ld1 {v10.4s-v13.4s}, [\rk]
|
||||
ld1 {v14.4s-v17.4s}, [\tmp], #64
|
||||
ld1 {v18.4s-v21.4s}, [\tmp], #64
|
||||
ld1 {v3.4s-v5.4s}, [\tmp]
|
||||
.endm
|
||||
|
||||
/*
|
||||
* void ce_aes_ccm_final(u8 mac[], u8 const ctr[], u8 const rk[],
|
||||
* u32 rounds);
|
||||
*/
|
||||
SYM_FUNC_START(ce_aes_ccm_final)
|
||||
ld1 {v3.4s}, [x2], #16 /* load first round key */
|
||||
ld1 {v0.16b}, [x0] /* load mac */
|
||||
cmp w3, #12 /* which key size? */
|
||||
sub w3, w3, #2 /* modified # of rounds */
|
||||
ld1 {v1.16b}, [x1] /* load 1st ctriv */
|
||||
bmi 0f
|
||||
bne 3f
|
||||
mov v5.16b, v3.16b
|
||||
b 2f
|
||||
0: mov v4.16b, v3.16b
|
||||
1: ld1 {v5.4s}, [x2], #16 /* load next round key */
|
||||
aese v0.16b, v4.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
aese v1.16b, v4.16b
|
||||
aesmc v1.16b, v1.16b
|
||||
2: ld1 {v3.4s}, [x2], #16 /* load next round key */
|
||||
aese v0.16b, v5.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
aese v1.16b, v5.16b
|
||||
aesmc v1.16b, v1.16b
|
||||
3: ld1 {v4.4s}, [x2], #16 /* load next round key */
|
||||
subs w3, w3, #3
|
||||
aese v0.16b, v3.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
aese v1.16b, v3.16b
|
||||
aesmc v1.16b, v1.16b
|
||||
bpl 1b
|
||||
aese v0.16b, v4.16b
|
||||
aese v1.16b, v4.16b
|
||||
/* final round key cancels out */
|
||||
eor v0.16b, v0.16b, v1.16b /* en-/decrypt the mac */
|
||||
st1 {v0.16b}, [x0] /* store result */
|
||||
ret
|
||||
SYM_FUNC_END(ce_aes_ccm_final)
|
||||
.macro dround, va, vb, vk
|
||||
aese \va\().16b, \vk\().16b
|
||||
aesmc \va\().16b, \va\().16b
|
||||
aese \vb\().16b, \vk\().16b
|
||||
aesmc \vb\().16b, \vb\().16b
|
||||
.endm
|
||||
|
||||
.macro aes_encrypt, va, vb, nr
|
||||
tbz \nr, #2, .L\@
|
||||
dround \va, \vb, v10
|
||||
dround \va, \vb, v11
|
||||
tbz \nr, #1, .L\@
|
||||
dround \va, \vb, v12
|
||||
dround \va, \vb, v13
|
||||
.L\@: .irp v, v14, v15, v16, v17, v18, v19, v20, v21, v3
|
||||
dround \va, \vb, \v
|
||||
.endr
|
||||
aese \va\().16b, v4.16b
|
||||
aese \vb\().16b, v4.16b
|
||||
.endm
|
||||
|
||||
.macro aes_ccm_do_crypt,enc
|
||||
cbz x2, 5f
|
||||
ldr x8, [x6, #8] /* load lower ctr */
|
||||
load_round_keys x3, w4, x10
|
||||
|
||||
ld1 {v0.16b}, [x5] /* load mac */
|
||||
cbz x2, ce_aes_ccm_final
|
||||
ldr x8, [x6, #8] /* load lower ctr */
|
||||
CPU_LE( rev x8, x8 ) /* keep swabbed ctr in reg */
|
||||
0: /* outer loop */
|
||||
ld1 {v1.8b}, [x6] /* load upper ctr */
|
||||
prfm pldl1strm, [x1]
|
||||
add x8, x8, #1
|
||||
rev x9, x8
|
||||
cmp w4, #12 /* which key size? */
|
||||
sub w7, w4, #2 /* get modified # of rounds */
|
||||
ins v1.d[1], x9 /* no carry in lower ctr */
|
||||
ld1 {v3.4s}, [x3] /* load first round key */
|
||||
add x10, x3, #16
|
||||
bmi 1f
|
||||
bne 4f
|
||||
mov v5.16b, v3.16b
|
||||
b 3f
|
||||
1: mov v4.16b, v3.16b
|
||||
ld1 {v5.4s}, [x10], #16 /* load 2nd round key */
|
||||
2: /* inner loop: 3 rounds, 2x interleaved */
|
||||
aese v0.16b, v4.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
aese v1.16b, v4.16b
|
||||
aesmc v1.16b, v1.16b
|
||||
3: ld1 {v3.4s}, [x10], #16 /* load next round key */
|
||||
aese v0.16b, v5.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
aese v1.16b, v5.16b
|
||||
aesmc v1.16b, v1.16b
|
||||
4: ld1 {v4.4s}, [x10], #16 /* load next round key */
|
||||
subs w7, w7, #3
|
||||
aese v0.16b, v3.16b
|
||||
aesmc v0.16b, v0.16b
|
||||
aese v1.16b, v3.16b
|
||||
aesmc v1.16b, v1.16b
|
||||
ld1 {v5.4s}, [x10], #16 /* load next round key */
|
||||
bpl 2b
|
||||
aese v0.16b, v4.16b
|
||||
aese v1.16b, v4.16b
|
||||
|
||||
aes_encrypt v0, v1, w4
|
||||
|
||||
subs w2, w2, #16
|
||||
bmi 6f /* partial block? */
|
||||
bmi ce_aes_ccm_crypt_tail
|
||||
ld1 {v2.16b}, [x1], #16 /* load next input block */
|
||||
.if \enc == 1
|
||||
eor v2.16b, v2.16b, v5.16b /* final round enc+mac */
|
||||
eor v1.16b, v1.16b, v2.16b /* xor with crypted ctr */
|
||||
eor v6.16b, v1.16b, v2.16b /* xor with crypted ctr */
|
||||
.else
|
||||
eor v2.16b, v2.16b, v1.16b /* xor with crypted ctr */
|
||||
eor v1.16b, v2.16b, v5.16b /* final round enc */
|
||||
eor v6.16b, v2.16b, v5.16b /* final round enc */
|
||||
.endif
|
||||
eor v0.16b, v0.16b, v2.16b /* xor mac with pt ^ rk[last] */
|
||||
st1 {v1.16b}, [x0], #16 /* write output block */
|
||||
st1 {v6.16b}, [x0], #16 /* write output block */
|
||||
bne 0b
|
||||
CPU_LE( rev x8, x8 )
|
||||
st1 {v0.16b}, [x5] /* store mac */
|
||||
str x8, [x6, #8] /* store lsb end of ctr (BE) */
|
||||
5: ret
|
||||
|
||||
6: eor v0.16b, v0.16b, v5.16b /* final round mac */
|
||||
eor v1.16b, v1.16b, v5.16b /* final round enc */
|
||||
cbnz x7, ce_aes_ccm_final
|
||||
st1 {v0.16b}, [x5] /* store mac */
|
||||
add w2, w2, #16 /* process partial tail block */
|
||||
7: ldrb w9, [x1], #1 /* get 1 byte of input */
|
||||
umov w6, v1.b[0] /* get top crypted ctr byte */
|
||||
umov w7, v0.b[0] /* get top mac byte */
|
||||
.if \enc == 1
|
||||
eor w7, w7, w9
|
||||
eor w9, w9, w6
|
||||
.else
|
||||
eor w9, w9, w6
|
||||
eor w7, w7, w9
|
||||
.endif
|
||||
strb w9, [x0], #1 /* store out byte */
|
||||
strb w7, [x5], #1 /* store mac byte */
|
||||
subs w2, w2, #1
|
||||
beq 5b
|
||||
ext v0.16b, v0.16b, v0.16b, #1 /* shift out mac byte */
|
||||
ext v1.16b, v1.16b, v1.16b, #1 /* shift out ctr byte */
|
||||
b 7b
|
||||
ret
|
||||
.endm
|
||||
|
||||
SYM_FUNC_START_LOCAL(ce_aes_ccm_crypt_tail)
|
||||
eor v0.16b, v0.16b, v5.16b /* final round mac */
|
||||
eor v1.16b, v1.16b, v5.16b /* final round enc */
|
||||
|
||||
add x1, x1, w2, sxtw /* rewind the input pointer (w2 < 0) */
|
||||
add x0, x0, w2, sxtw /* rewind the output pointer */
|
||||
|
||||
adr_l x8, .Lpermute /* load permute vectors */
|
||||
add x9, x8, w2, sxtw
|
||||
sub x8, x8, w2, sxtw
|
||||
ld1 {v7.16b-v8.16b}, [x9]
|
||||
ld1 {v9.16b}, [x8]
|
||||
|
||||
ld1 {v2.16b}, [x1] /* load a full block of input */
|
||||
tbl v1.16b, {v1.16b}, v7.16b /* move keystream to end of register */
|
||||
eor v7.16b, v2.16b, v1.16b /* encrypt partial input block */
|
||||
bif v2.16b, v7.16b, v22.16b /* select plaintext */
|
||||
tbx v7.16b, {v6.16b}, v8.16b /* insert output from previous iteration */
|
||||
tbl v2.16b, {v2.16b}, v9.16b /* copy plaintext to start of v2 */
|
||||
eor v0.16b, v0.16b, v2.16b /* fold plaintext into mac */
|
||||
|
||||
st1 {v7.16b}, [x0] /* store output block */
|
||||
cbz x7, 0f
|
||||
|
||||
SYM_INNER_LABEL(ce_aes_ccm_final, SYM_L_LOCAL)
|
||||
ld1 {v1.16b}, [x7] /* load 1st ctriv */
|
||||
|
||||
aes_encrypt v0, v1, w4
|
||||
|
||||
/* final round key cancels out */
|
||||
eor v0.16b, v0.16b, v1.16b /* en-/decrypt the mac */
|
||||
0: st1 {v0.16b}, [x5] /* store result */
|
||||
ret
|
||||
SYM_FUNC_END(ce_aes_ccm_crypt_tail)
|
||||
|
||||
/*
|
||||
* void ce_aes_ccm_encrypt(u8 out[], u8 const in[], u32 cbytes,
|
||||
* u8 const rk[], u32 rounds, u8 mac[],
|
||||
* u8 ctr[]);
|
||||
* u8 ctr[], u8 const final_iv[]);
|
||||
* void ce_aes_ccm_decrypt(u8 out[], u8 const in[], u32 cbytes,
|
||||
* u8 const rk[], u32 rounds, u8 mac[],
|
||||
* u8 ctr[]);
|
||||
* u8 ctr[], u8 const final_iv[]);
|
||||
*/
|
||||
SYM_FUNC_START(ce_aes_ccm_encrypt)
|
||||
movi v22.16b, #255
|
||||
aes_ccm_do_crypt 1
|
||||
SYM_FUNC_END(ce_aes_ccm_encrypt)
|
||||
|
||||
SYM_FUNC_START(ce_aes_ccm_decrypt)
|
||||
movi v22.16b, #0
|
||||
aes_ccm_do_crypt 0
|
||||
SYM_FUNC_END(ce_aes_ccm_decrypt)
|
||||
|
||||
.section ".rodata", "a"
|
||||
.align 6
|
||||
.fill 15, 1, 0xff
|
||||
.Lpermute:
|
||||
.byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
|
||||
.byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf
|
||||
.fill 15, 1, 0xff
|
||||
|
||||
@@ -1,8 +1,11 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* aes-ccm-glue.c - AES-CCM transform for ARMv8 with Crypto Extensions
|
||||
* aes-ce-ccm-glue.c - AES-CCM transform for ARMv8 with Crypto Extensions
|
||||
*
|
||||
* Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
|
||||
* Copyright (C) 2013 - 2017 Linaro Ltd.
|
||||
* Copyright (C) 2024 Google LLC
|
||||
*
|
||||
* Author: Ard Biesheuvel <ardb@kernel.org>
|
||||
*/
|
||||
|
||||
#include <asm/neon.h>
|
||||
@@ -15,6 +18,8 @@
|
||||
|
||||
#include "aes-ce-setkey.h"
|
||||
|
||||
MODULE_IMPORT_NS(CRYPTO_INTERNAL);
|
||||
|
||||
static int num_rounds(struct crypto_aes_ctx *ctx)
|
||||
{
|
||||
/*
|
||||
@@ -27,19 +32,17 @@ static int num_rounds(struct crypto_aes_ctx *ctx)
|
||||
return 6 + ctx->key_length / 4;
|
||||
}
|
||||
|
||||
asmlinkage u32 ce_aes_ccm_auth_data(u8 mac[], u8 const in[], u32 abytes,
|
||||
u32 macp, u32 const rk[], u32 rounds);
|
||||
asmlinkage u32 ce_aes_mac_update(u8 const in[], u32 const rk[], int rounds,
|
||||
int blocks, u8 dg[], int enc_before,
|
||||
int enc_after);
|
||||
|
||||
asmlinkage void ce_aes_ccm_encrypt(u8 out[], u8 const in[], u32 cbytes,
|
||||
u32 const rk[], u32 rounds, u8 mac[],
|
||||
u8 ctr[]);
|
||||
u8 ctr[], u8 const final_iv[]);
|
||||
|
||||
asmlinkage void ce_aes_ccm_decrypt(u8 out[], u8 const in[], u32 cbytes,
|
||||
u32 const rk[], u32 rounds, u8 mac[],
|
||||
u8 ctr[]);
|
||||
|
||||
asmlinkage void ce_aes_ccm_final(u8 mac[], u8 const ctr[], u32 const rk[],
|
||||
u32 rounds);
|
||||
u8 ctr[], u8 const final_iv[]);
|
||||
|
||||
static int ccm_setkey(struct crypto_aead *tfm, const u8 *in_key,
|
||||
unsigned int key_len)
|
||||
@@ -94,6 +97,41 @@ static int ccm_init_mac(struct aead_request *req, u8 maciv[], u32 msglen)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 ce_aes_ccm_auth_data(u8 mac[], u8 const in[], u32 abytes,
|
||||
u32 macp, u32 const rk[], u32 rounds)
|
||||
{
|
||||
int enc_after = (macp + abytes) % AES_BLOCK_SIZE;
|
||||
|
||||
do {
|
||||
u32 blocks = abytes / AES_BLOCK_SIZE;
|
||||
|
||||
if (macp == AES_BLOCK_SIZE || (!macp && blocks > 0)) {
|
||||
u32 rem = ce_aes_mac_update(in, rk, rounds, blocks, mac,
|
||||
macp, enc_after);
|
||||
u32 adv = (blocks - rem) * AES_BLOCK_SIZE;
|
||||
|
||||
macp = enc_after ? 0 : AES_BLOCK_SIZE;
|
||||
in += adv;
|
||||
abytes -= adv;
|
||||
|
||||
if (unlikely(rem)) {
|
||||
kernel_neon_end();
|
||||
kernel_neon_begin();
|
||||
macp = 0;
|
||||
}
|
||||
} else {
|
||||
u32 l = min(AES_BLOCK_SIZE - macp, abytes);
|
||||
|
||||
crypto_xor(&mac[macp], in, l);
|
||||
in += l;
|
||||
macp += l;
|
||||
abytes -= l;
|
||||
}
|
||||
} while (abytes > 0);
|
||||
|
||||
return macp;
|
||||
}
|
||||
|
||||
static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[])
|
||||
{
|
||||
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
||||
@@ -101,7 +139,7 @@ static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[])
|
||||
struct __packed { __be16 l; __be32 h; u16 len; } ltag;
|
||||
struct scatter_walk walk;
|
||||
u32 len = req->assoclen;
|
||||
u32 macp = 0;
|
||||
u32 macp = AES_BLOCK_SIZE;
|
||||
|
||||
/* prepend the AAD with a length tag */
|
||||
if (len < 0xff00) {
|
||||
@@ -125,16 +163,11 @@ static void ccm_calculate_auth_mac(struct aead_request *req, u8 mac[])
|
||||
scatterwalk_start(&walk, sg_next(walk.sg));
|
||||
n = scatterwalk_clamp(&walk, len);
|
||||
}
|
||||
n = min_t(u32, n, SZ_4K); /* yield NEON at least every 4k */
|
||||
p = scatterwalk_map(&walk);
|
||||
|
||||
macp = ce_aes_ccm_auth_data(mac, p, n, macp, ctx->key_enc,
|
||||
num_rounds(ctx));
|
||||
|
||||
if (len / SZ_4K > (len - n) / SZ_4K) {
|
||||
kernel_neon_end();
|
||||
kernel_neon_begin();
|
||||
}
|
||||
len -= n;
|
||||
|
||||
scatterwalk_unmap(p);
|
||||
@@ -149,7 +182,7 @@ static int ccm_encrypt(struct aead_request *req)
|
||||
struct crypto_aes_ctx *ctx = crypto_aead_ctx(aead);
|
||||
struct skcipher_walk walk;
|
||||
u8 __aligned(8) mac[AES_BLOCK_SIZE];
|
||||
u8 buf[AES_BLOCK_SIZE];
|
||||
u8 orig_iv[AES_BLOCK_SIZE];
|
||||
u32 len = req->cryptlen;
|
||||
int err;
|
||||
|
||||
@@ -158,42 +191,55 @@ static int ccm_encrypt(struct aead_request *req)
|
||||
return err;
|
||||
|
||||
/* preserve the original iv for the final round */
|
||||
memcpy(buf, req->iv, AES_BLOCK_SIZE);
|
||||
memcpy(orig_iv, req->iv, AES_BLOCK_SIZE);
|
||||
|
||||
err = skcipher_walk_aead_encrypt(&walk, req, false);
|
||||
if (unlikely(err))
|
||||
return err;
|
||||
|
||||
kernel_neon_begin();
|
||||
|
||||
if (req->assoclen)
|
||||
ccm_calculate_auth_mac(req, mac);
|
||||
|
||||
while (walk.nbytes) {
|
||||
do {
|
||||
u32 tail = walk.nbytes % AES_BLOCK_SIZE;
|
||||
bool final = walk.nbytes == walk.total;
|
||||
const u8 *src = walk.src.virt.addr;
|
||||
u8 *dst = walk.dst.virt.addr;
|
||||
u8 buf[AES_BLOCK_SIZE];
|
||||
u8 *final_iv = NULL;
|
||||
|
||||
if (final)
|
||||
if (walk.nbytes == walk.total) {
|
||||
tail = 0;
|
||||
final_iv = orig_iv;
|
||||
}
|
||||
|
||||
ce_aes_ccm_encrypt(walk.dst.virt.addr, walk.src.virt.addr,
|
||||
walk.nbytes - tail, ctx->key_enc,
|
||||
num_rounds(ctx), mac, walk.iv);
|
||||
if (unlikely(walk.nbytes < AES_BLOCK_SIZE))
|
||||
src = dst = memcpy(&buf[sizeof(buf) - walk.nbytes],
|
||||
src, walk.nbytes);
|
||||
|
||||
if (!final)
|
||||
kernel_neon_end();
|
||||
err = skcipher_walk_done(&walk, tail);
|
||||
if (!final)
|
||||
kernel_neon_begin();
|
||||
}
|
||||
ce_aes_ccm_encrypt(dst, src, walk.nbytes - tail,
|
||||
ctx->key_enc, num_rounds(ctx),
|
||||
mac, walk.iv, final_iv);
|
||||
|
||||
ce_aes_ccm_final(mac, buf, ctx->key_enc, num_rounds(ctx));
|
||||
if (unlikely(walk.nbytes < AES_BLOCK_SIZE))
|
||||
memcpy(walk.dst.virt.addr, dst, walk.nbytes);
|
||||
|
||||
if (walk.nbytes) {
|
||||
err = skcipher_walk_done(&walk, tail);
|
||||
}
|
||||
} while (walk.nbytes);
|
||||
|
||||
kernel_neon_end();
|
||||
|
||||
if (unlikely(err))
|
||||
return err;
|
||||
|
||||
/* copy authtag to end of dst */
|
||||
scatterwalk_map_and_copy(mac, req->dst, req->assoclen + req->cryptlen,
|
||||
crypto_aead_authsize(aead), 1);
|
||||
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ccm_decrypt(struct aead_request *req)
|
||||
@@ -203,7 +249,7 @@ static int ccm_decrypt(struct aead_request *req)
|
||||
unsigned int authsize = crypto_aead_authsize(aead);
|
||||
struct skcipher_walk walk;
|
||||
u8 __aligned(8) mac[AES_BLOCK_SIZE];
|
||||
u8 buf[AES_BLOCK_SIZE];
|
||||
u8 orig_iv[AES_BLOCK_SIZE];
|
||||
u32 len = req->cryptlen - authsize;
|
||||
int err;
|
||||
|
||||
@@ -212,34 +258,44 @@ static int ccm_decrypt(struct aead_request *req)
|
||||
return err;
|
||||
|
||||
/* preserve the original iv for the final round */
|
||||
memcpy(buf, req->iv, AES_BLOCK_SIZE);
|
||||
memcpy(orig_iv, req->iv, AES_BLOCK_SIZE);
|
||||
|
||||
err = skcipher_walk_aead_decrypt(&walk, req, false);
|
||||
if (unlikely(err))
|
||||
return err;
|
||||
|
||||
kernel_neon_begin();
|
||||
|
||||
if (req->assoclen)
|
||||
ccm_calculate_auth_mac(req, mac);
|
||||
|
||||
while (walk.nbytes) {
|
||||
do {
|
||||
u32 tail = walk.nbytes % AES_BLOCK_SIZE;
|
||||
bool final = walk.nbytes == walk.total;
|
||||
const u8 *src = walk.src.virt.addr;
|
||||
u8 *dst = walk.dst.virt.addr;
|
||||
u8 buf[AES_BLOCK_SIZE];
|
||||
u8 *final_iv = NULL;
|
||||
|
||||
if (final)
|
||||
if (walk.nbytes == walk.total) {
|
||||
tail = 0;
|
||||
final_iv = orig_iv;
|
||||
}
|
||||
|
||||
ce_aes_ccm_decrypt(walk.dst.virt.addr, walk.src.virt.addr,
|
||||
walk.nbytes - tail, ctx->key_enc,
|
||||
num_rounds(ctx), mac, walk.iv);
|
||||
if (unlikely(walk.nbytes < AES_BLOCK_SIZE))
|
||||
src = dst = memcpy(&buf[sizeof(buf) - walk.nbytes],
|
||||
src, walk.nbytes);
|
||||
|
||||
if (!final)
|
||||
kernel_neon_end();
|
||||
err = skcipher_walk_done(&walk, tail);
|
||||
if (!final)
|
||||
kernel_neon_begin();
|
||||
}
|
||||
ce_aes_ccm_decrypt(dst, src, walk.nbytes - tail,
|
||||
ctx->key_enc, num_rounds(ctx),
|
||||
mac, walk.iv, final_iv);
|
||||
|
||||
ce_aes_ccm_final(mac, buf, ctx->key_enc, num_rounds(ctx));
|
||||
if (unlikely(walk.nbytes < AES_BLOCK_SIZE))
|
||||
memcpy(walk.dst.virt.addr, dst, walk.nbytes);
|
||||
|
||||
if (walk.nbytes) {
|
||||
err = skcipher_walk_done(&walk, tail);
|
||||
}
|
||||
} while (walk.nbytes);
|
||||
|
||||
kernel_neon_end();
|
||||
|
||||
@@ -247,11 +303,11 @@ static int ccm_decrypt(struct aead_request *req)
|
||||
return err;
|
||||
|
||||
/* compare calculated auth tag with the stored one */
|
||||
scatterwalk_map_and_copy(buf, req->src,
|
||||
scatterwalk_map_and_copy(orig_iv, req->src,
|
||||
req->assoclen + req->cryptlen - authsize,
|
||||
authsize, 0);
|
||||
|
||||
if (crypto_memneq(mac, buf, authsize))
|
||||
if (crypto_memneq(mac, orig_iv, authsize))
|
||||
return -EBADMSG;
|
||||
return 0;
|
||||
}
|
||||
@@ -290,6 +346,6 @@ module_init(aes_mod_init);
|
||||
module_exit(aes_mod_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Synchronous AES in CCM mode using ARMv8 Crypto Extensions");
|
||||
MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
|
||||
MODULE_AUTHOR("Ard Biesheuvel <ardb@kernel.org>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS_CRYPTO("ccm(aes)");
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user