diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index be73bfc7f52b..876ba56f6fe3 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -2145,6 +2145,13 @@ static void tegra_pcie_disable_interrupts(struct tegra_pcie *pcie) afi_writel(pcie, value, AFI_INTR_MASK); } +static void update_rp_lanes(struct tegra_pcie *pcie, u32 lanes) +{ + struct tegra_pcie_port *port = NULL; + list_for_each_entry(port, &pcie->ports, list) + port->lanes = (lanes >> (port->index << 3)) & 0xFF; +} + static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, u32 *xbar) { @@ -2173,14 +2180,21 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, "switching to default 2x1, 1x1, 1x1 " "configuration\n"); *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211; + update_rp_lanes(pcie, 0x010102); return 0; } } else if (of_device_is_compatible(np, "nvidia,tegra210b01-pcie")) { switch (lanes) { case 0x0104: - dev_info(pcie->dev, "4x1, 1x1 configuration\n"); + dev_info(dev, "4x1, 1x1 configuration\n"); *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; return 0; + default: + dev_info(dev, "wrong configuration updated in DT, " + "switching to default 4x1, 1x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; + update_rp_lanes(pcie, 0x0104); + return 0; } } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") || of_device_is_compatible(np, "nvidia,tegra210-pcie")) { @@ -2194,6 +2208,13 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, dev_info(dev, "2x1, 1x1 configuration\n"); *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1; return 0; + + default: + dev_info(dev, "wrong configuration updated in DT, " + "switching to default 4x1, 1x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1; + update_rp_lanes(pcie, 0x0104); + return 0; } } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) { switch (lanes) {