diff --git a/drivers/gpu/drm/panel/panel-nx-dsi.c b/drivers/gpu/drm/panel/panel-nx-dsi.c index 96b73786e708..26e66a0b4446 100644 --- a/drivers/gpu/drm/panel/panel-nx-dsi.c +++ b/drivers/gpu/drm/panel/panel-nx-dsi.c @@ -32,39 +32,38 @@ #include /*! MIPI DCS Panel Private CMDs. */ -#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE 0xA0 -#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET 0xB0 -#define MIPI_DCS_PRIV_SM_SET_ELVSS \ - 0xB1 // OLED backlight tuning. Byte7: PWM transition time in frames. -#define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1 -#define MIPI_DCS_PRIV_SET_EXTC 0xB9 // Enable extended commands. -#define MIPI_DCS_PRIV_UNK_BD 0xBD -#define MIPI_DCS_PRIV_UNK_D5 0xD5 -#define MIPI_DCS_PRIV_UNK_D6 0xD6 -#define MIPI_DCS_PRIV_UNK_D8 0xD8 -#define MIPI_DCS_PRIV_UNK_D9 0xD9 +#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE ((u8)0xA0) +#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET ((u8)0xB0) +#define MIPI_DCS_PRIV_SM_SET_ELVSS ((u8)0xB1) /* OLED backlight tuning. Byte7: PWM transition time in frames. */ +#define MIPI_DCS_PRIV_SET_POWER_CONTROL ((u8)0xB1) +#define MIPI_DCS_PRIV_SET_EXTC ((u8)0xB9) /* Enable extended commands. */ +#define MIPI_DCS_PRIV_UNK_BD ((u8)0xBD) +#define MIPI_DCS_PRIV_UNK_D5 ((u8)0xD5) +#define MIPI_DCS_PRIV_UNK_D6 ((u8)0xD6) +#define MIPI_DCS_PRIV_UNK_D8 ((u8)0xD8) +#define MIPI_DCS_PRIV_UNK_D9 ((u8)0xD9) -#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK 0xE2 +#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK ((u8)0xE2) -// BL Control -#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT BIT(2) -#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL BIT(2) -#define DCS_CONTROL_DISPLAY_DIMMING_CTRL BIT(3) -#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5) +/* BL Control */ +#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT ((u8)BIT(2)) +#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL ((u8)BIT(2)) +#define DCS_CONTROL_DISPLAY_DIMMING_CTRL ((u8)BIT(3)) +#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL ((u8)BIT(5)) -// OLED Panels color mode -#define DCS_SM_COLOR_MODE_SATURATED 0x00 // Disabled. Similar to vivid but over-saturated. Wide gamut? -#define DCS_SM_COLOR_MODE_WASHED 0x45 -#define DCS_SM_COLOR_MODE_BASIC 0x03 -#define DCS_SM_COLOR_MODE_POR_RESET 0x20 // Reset value on power on. -#define DCS_SM_COLOR_MODE_NATURAL 0x23 // Not actually natural.. -#define DCS_SM_COLOR_MODE_VIVID 0x65 -#define DCS_SM_COLOR_MODE_NIGHT0 0x43 // Based on washed out. -#define DCS_SM_COLOR_MODE_NIGHT1 0x15 // Based on basic. -#define DCS_SM_COLOR_MODE_NIGHT2 0x35 // Based on natural. -#define DCS_SM_COLOR_MODE_NIGHT3 0x75 // Based on vivid. +/* OLED Panels color mode */ +#define DCS_SM_COLOR_MODE_SATURATED ((u8)0x00) /* Disabled. Similar to vivid but over-saturated. Wide gamut? */ +#define DCS_SM_COLOR_MODE_WASHED ((u8)0x45) +#define DCS_SM_COLOR_MODE_BASIC ((u8)0x03) +#define DCS_SM_COLOR_MODE_POR_RESET ((u8)0x20) /* Reset value on power on. */ +#define DCS_SM_COLOR_MODE_NATURAL ((u8)0x23) /* Not actually natural.. */ +#define DCS_SM_COLOR_MODE_VIVID ((u8)0x65) +#define DCS_SM_COLOR_MODE_NIGHT0 ((u8)0x43) /* Based on washed out. */ +#define DCS_SM_COLOR_MODE_NIGHT1 ((u8)0x15) /* Based on basic. */ +#define DCS_SM_COLOR_MODE_NIGHT2 ((u8)0x35) /* Based on natural. */ +#define DCS_SM_COLOR_MODE_NIGHT3 ((u8)0x75) /* Based on vivid. */ -#define DCS_SM_COLOR_MODE_ENABLE BIT(0) +#define DCS_SM_COLOR_MODE_ENABLE ((u8)BIT(0)) enum { @@ -115,7 +114,7 @@ struct nx_panel { struct init_cmd *init_cmds; struct init_cmd *suspend_cmds; - u8 display_id[3]; + u16 display_id; }; struct init_cmd init_cmds_default[] = { @@ -198,23 +197,23 @@ struct init_cmd init_cmds_PANEL_SAM_AMS699VC01[] = { }, // Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20). - { MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_BASIC << 8), 2, { 0x00, 0x0 } }, + { MIPI_DCS_PRIV_SM_SET_COLOR_MODE, 2, { 0x23, 0x0 } }, // Enable backlight and smooth PWM. - { MIPI_DCS_WRITE_CONTROL_DISPLAY | ((DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL) << 8), 2, { 0x00, 0x0 } }, + { MIPI_DCS_WRITE_CONTROL_DISPLAY, 2, { 0x28, 0x0 } }, // Unlock Level 2 registers. - { MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0x5A, 0x5A, 0x0 } }, + { 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0x5A, 0x5A, 0x0, 0x0 } }, // Set registers offset and set PWM transition to 6 frames (100ms). - { MIPI_DCS_PRIV_SM_SET_REG_OFFSET | (7 << 8), 2, { 0x00, 0x0 } }, - { MIPI_DCS_PRIV_SM_SET_ELVSS | (6 << 8), 2, { 0x00, 0x0 } }, + { MIPI_DCS_PRIV_SM_SET_REG_OFFSET, 2, { 0x07, 0x0 } }, + { MIPI_DCS_PRIV_SM_SET_ELVSS, 2, { 0x06, 0x0 } }, // Relock Level 2 registers. - { MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0xA5, 0xA5, 0x0 } }, + { 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0xA5, 0xA5, 0x0, 0x0 } }, // MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%. - { MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 3, { 0x00, 0x00, 0x0 } }, + { 0x03, 7, { 0x00, 0x00, 0x51, 0x0, 0x0, 0x0, 0x0 } }, { 0xFF, @@ -358,22 +357,21 @@ static void nx_panel_detect(struct nx_panel *nx) printk("nx_panel_detect"); - memset(nx->display_id, 0, sizeof(nx->display_id)); + memset(&(nx->display_id), 0, sizeof(nx->display_id)); ret = mipi_dsi_dcs_read(nx->dsi, MIPI_DCS_GET_DISPLAY_ID, - nx->display_id, sizeof(nx->display_id)); + &(nx->display_id), sizeof(nx->display_id)); if (ret < 0) { dev_err(&nx->dsi->dev, "failed to read panel ID: %d\n", ret); } else { - dev_info(&nx->dsi->dev, "display ID[%d]: %02x %02x %02x\n", - ret, nx->display_id[0], nx->display_id[1], - nx->display_id[2]); + dev_info(&nx->dsi->dev, "display ID[%d]: %04x\n", + ret, nx->display_id); } dev_info(&nx->dsi->dev, - "setting init sequence for ID %02x\n", nx->display_id[0]); + "setting init sequence for ID %04x\n", nx->display_id); - switch (nx->display_id[0]) { + switch (nx->display_id) { case PANEL_JDI_XXX062M: nx->init_cmds = init_cmds_PANEL_JDI_XXX062M; break; @@ -396,9 +394,9 @@ static void nx_panel_detect(struct nx_panel *nx) } dev_info(&nx->dsi->dev, - "setting suspend sequence for ID %02x\n", nx->display_id[0]); + "setting suspend sequence for ID %04x\n", nx->display_id); - switch (nx->display_id[0]) { + switch (nx->display_id) { case PANEL_JDI_XXX062M: nx->suspend_cmds = suspend_cmds_PANEL_JDI_XXX062M; break;