Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/avr32-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoen/avr32-2.6: (25 commits) avr32: Add hardware power-down function call avr32: add include/asm-avr32/serial.h avr32: don't offer PARPORT_PC avr32: don't offer CONFIG_GEN_RTC avr32: don't offer CONFIG_RTC add include/asm-avr32/xor.h avr32: Remove two unused #defines from mm/init.c avr32: Implement set_rate(), set_parent() and mode() for pll1 avr32: Generic clockevents support avr32: Move sleep code into mach-at32ap avr32: Use constants from sysreg.h in asm.h avr32: Delete mostly unused header asm/intc.h avr32: start clocksource cleanup avr32: pass i2c board info through at32_add_device_twi avr32: cleanup - use _AC macro to define PAGE_SIZE Generate raw keyboard codes for AVR32 architecture atmel_usba_udc: Add support for AT91CAP9 UDPHS atmel_usba_udc: Add missing kfree() in usba_udc_remove() atmel_usba_udc: move endpoint declarations into platform data. atmel_usba_udc: Kill GPIO_PIN_NONE ...
This commit is contained in:
Linus Torvalds
@@ -38,9 +38,7 @@ struct platform_device *
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at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
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unsigned long fbmem_start, unsigned long fbmem_len);
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struct usba_platform_data {
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int vbus_pin;
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};
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struct usba_platform_data;
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struct platform_device *
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at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
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@@ -68,7 +66,10 @@ struct platform_device *at32_add_device_pwm(u32 mask);
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struct platform_device *
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at32_add_device_ssc(unsigned int id, unsigned int flags);
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struct platform_device *at32_add_device_twi(unsigned int id);
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struct i2c_board_info;
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struct platform_device *at32_add_device_twi(unsigned int id,
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struct i2c_board_info *b,
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unsigned int n);
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struct platform_device *at32_add_device_mci(unsigned int id);
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struct platform_device *at32_add_device_ac97c(unsigned int id);
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struct platform_device *at32_add_device_abdac(unsigned int id);
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@@ -0,0 +1,48 @@
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/*
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* AVR32 AP Power Management.
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_ARCH_PM_H
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#define __ASM_AVR32_ARCH_PM_H
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/* Possible arguments to the "sleep" instruction */
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#define CPU_SLEEP_IDLE 0
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#define CPU_SLEEP_FROZEN 1
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#define CPU_SLEEP_STANDBY 2
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#define CPU_SLEEP_STOP 3
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#define CPU_SLEEP_STATIC 5
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#ifndef __ASSEMBLY__
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extern void cpu_enter_idle(void);
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extern bool disable_idle_sleep;
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static inline void cpu_disable_idle_sleep(void)
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{
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disable_idle_sleep = true;
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}
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static inline void cpu_enable_idle_sleep(void)
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{
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disable_idle_sleep = false;
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}
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static inline void cpu_idle_sleep(void)
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{
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/*
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* If we're using the COUNT and COMPARE registers for
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* timekeeping, we can't use the IDLE state.
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*/
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if (disable_idle_sleep)
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cpu_relax();
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else
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cpu_enter_idle();
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}
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#endif
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#endif /* __ASM_AVR32_ARCH_PM_H */
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@@ -1,112 +0,0 @@
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/*
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* Copyright (C) 2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
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#define _ASM_AVR32_ARCH_AT32AP_TIME_H
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#include <linux/platform_device.h>
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extern struct irqaction timer_irqaction;
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extern struct platform_device at32_systc0_device;
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extern void local_timer_interrupt(int irq, void *dev_id);
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#define TIMER_BCR 0x000000c0
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#define TIMER_BCR_SYNC 0
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#define TIMER_BMR 0x000000c4
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#define TIMER_BMR_TC0XC0S 0
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#define TIMER_BMR_TC1XC1S 2
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#define TIMER_BMR_TC2XC2S 4
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#define TIMER_CCR 0x00000000
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#define TIMER_CCR_CLKDIS 1
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#define TIMER_CCR_CLKEN 0
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#define TIMER_CCR_SWTRG 2
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#define TIMER_CMR 0x00000004
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#define TIMER_CMR_ABETRG 10
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#define TIMER_CMR_ACPA 16
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#define TIMER_CMR_ACPC 18
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#define TIMER_CMR_AEEVT 20
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#define TIMER_CMR_ASWTRG 22
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#define TIMER_CMR_BCPB 24
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#define TIMER_CMR_BCPC 26
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#define TIMER_CMR_BEEVT 28
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#define TIMER_CMR_BSWTRG 30
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#define TIMER_CMR_BURST 4
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#define TIMER_CMR_CLKI 3
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#define TIMER_CMR_CPCDIS 7
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#define TIMER_CMR_CPCSTOP 6
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#define TIMER_CMR_CPCTRG 14
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#define TIMER_CMR_EEVT 10
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#define TIMER_CMR_EEVTEDG 8
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#define TIMER_CMR_ENETRG 12
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#define TIMER_CMR_ETRGEDG 8
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#define TIMER_CMR_LDBDIS 7
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#define TIMER_CMR_LDBSTOP 6
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#define TIMER_CMR_LDRA 16
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#define TIMER_CMR_LDRB 18
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#define TIMER_CMR_TCCLKS 0
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#define TIMER_CMR_WAVE 15
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#define TIMER_CMR_WAVSEL 13
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#define TIMER_CV 0x00000010
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#define TIMER_CV_CV 0
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#define TIMER_IDR 0x00000028
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#define TIMER_IDR_COVFS 0
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#define TIMER_IDR_CPAS 2
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#define TIMER_IDR_CPBS 3
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#define TIMER_IDR_CPCS 4
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#define TIMER_IDR_ETRGS 7
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#define TIMER_IDR_LDRAS 5
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#define TIMER_IDR_LDRBS 6
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#define TIMER_IDR_LOVRS 1
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#define TIMER_IER 0x00000024
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#define TIMER_IER_COVFS 0
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#define TIMER_IER_CPAS 2
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#define TIMER_IER_CPBS 3
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#define TIMER_IER_CPCS 4
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#define TIMER_IER_ETRGS 7
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#define TIMER_IER_LDRAS 5
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#define TIMER_IER_LDRBS 6
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#define TIMER_IER_LOVRS 1
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#define TIMER_IMR 0x0000002c
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#define TIMER_IMR_COVFS 0
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#define TIMER_IMR_CPAS 2
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#define TIMER_IMR_CPBS 3
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#define TIMER_IMR_CPCS 4
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#define TIMER_IMR_ETRGS 7
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#define TIMER_IMR_LDRAS 5
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#define TIMER_IMR_LDRBS 6
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#define TIMER_IMR_LOVRS 1
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#define TIMER_RA 0x00000014
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#define TIMER_RA_RA 0
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#define TIMER_RB 0x00000018
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#define TIMER_RB_RB 0
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#define TIMER_RC 0x0000001c
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#define TIMER_RC_RC 0
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#define TIMER_SR 0x00000020
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#define TIMER_SR_CLKSTA 16
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#define TIMER_SR_COVFS 0
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#define TIMER_SR_CPAS 2
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#define TIMER_SR_CPBS 3
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#define TIMER_SR_CPCS 4
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#define TIMER_SR_ETRGS 7
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#define TIMER_SR_LDRAS 5
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#define TIMER_SR_LDRBS 6
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#define TIMER_SR_LOVRS 1
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#define TIMER_SR_MTIOA 17
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#define TIMER_SR_MTIOB 18
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||||
|
||||
/* Bit manipulation macros */
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||||
#define TIMER_BIT(name) (1 << TIMER_##name)
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#define TIMER_BF(name,value) ((value) << TIMER_##name)
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||||
|
||||
/* Register access macros */
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||||
#define timer_read(port,instance,reg) \
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__raw_readl(port + (0x40 * instance) + TIMER_##reg)
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#define timer_write(port,instance,reg,value) \
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__raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
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#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
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@@ -12,10 +12,10 @@
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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||||
|
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#define mask_interrupts ssrf SR_GM_BIT
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#define mask_exceptions ssrf SR_EM_BIT
|
||||
#define unmask_interrupts csrf SR_GM_BIT
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||||
#define unmask_exceptions csrf SR_EM_BIT
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||||
#define mask_interrupts ssrf SYSREG_GM_OFFSET
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#define mask_exceptions ssrf SYSREG_EM_OFFSET
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#define unmask_interrupts csrf SYSREG_GM_OFFSET
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#define unmask_exceptions csrf SYSREG_EM_OFFSET
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||||
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#ifdef CONFIG_FRAME_POINTER
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.macro save_fp
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||||
@@ -1,128 +0,0 @@
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#ifndef __ASM_AVR32_INTC_H
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#define __ASM_AVR32_INTC_H
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||||
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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struct irq_controller;
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struct irqaction;
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struct pt_regs;
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struct platform_device;
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/* Information about the internal interrupt controller */
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struct intc_device {
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/* ioremapped address of configuration block */
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void __iomem *regs;
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/* the physical device */
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struct platform_device *pdev;
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/* Number of interrupt lines per group. */
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unsigned int irqs_per_group;
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||||
/* The highest group ID + 1 */
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unsigned int nr_groups;
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|
||||
/*
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* Bitfield indicating which groups are actually in use. The
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* size of the array is
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* ceil(group_max / (8 * sizeof(unsigned int))).
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*/
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unsigned int group_mask[];
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};
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struct irq_controller_class {
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||||
/*
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* A short name identifying this kind of controller.
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*/
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||||
const char *typename;
|
||||
/*
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* Handle the IRQ. Must do any necessary acking and masking.
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||||
*/
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||||
irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
|
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/*
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* Register a new IRQ handler.
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||||
*/
|
||||
int (*setup)(struct irq_controller *ctrl, unsigned int irq,
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||||
struct irqaction *action);
|
||||
/*
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||||
* Unregister a IRQ handler.
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||||
*/
|
||||
void (*free)(struct irq_controller *ctrl, unsigned int irq,
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||||
void *dev_id);
|
||||
/*
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||||
* Mask the IRQ in the interrupt controller.
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||||
*/
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||||
void (*mask)(struct irq_controller *ctrl, unsigned int irq);
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||||
/*
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||||
* Unmask the IRQ in the interrupt controller.
|
||||
*/
|
||||
void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
|
||||
/*
|
||||
* Set the type of the IRQ. See below for possible types.
|
||||
* Return -EINVAL if a given type is not supported
|
||||
*/
|
||||
int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
|
||||
unsigned int type);
|
||||
/*
|
||||
* Return the IRQ type currently set
|
||||
*/
|
||||
unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
|
||||
};
|
||||
|
||||
struct irq_controller {
|
||||
struct irq_controller_class *class;
|
||||
unsigned int irq_group;
|
||||
unsigned int first_irq;
|
||||
unsigned int nr_irqs;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
struct intc_group_desc {
|
||||
struct irq_controller *ctrl;
|
||||
irqreturn_t (*handle)(int, void *, struct pt_regs *);
|
||||
unsigned long flags;
|
||||
void *dev_id;
|
||||
const char *devname;
|
||||
};
|
||||
|
||||
/*
|
||||
* The internal interrupt controller. Defined in board/part-specific
|
||||
* devices.c.
|
||||
* TODO: Should probably be defined per-cpu.
|
||||
*/
|
||||
extern struct intc_device intc;
|
||||
|
||||
extern int request_internal_irq(unsigned int irq,
|
||||
irqreturn_t (*handler)(int, void *, struct pt_regs *),
|
||||
unsigned long irqflags,
|
||||
const char *devname, void *dev_id);
|
||||
extern void free_internal_irq(unsigned int irq);
|
||||
|
||||
/* Only used by time_init() */
|
||||
extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
|
||||
|
||||
/*
|
||||
* Set interrupt priority for a given group. `group' can be found by
|
||||
* using irq_to_group(irq). Priority can be from 0 (lowest) to 3
|
||||
* (highest). Higher-priority interrupts will preempt lower-priority
|
||||
* interrupts (unless interrupts are masked globally).
|
||||
*
|
||||
* This function does not check for conflicts within a group.
|
||||
*/
|
||||
extern int intc_set_priority(unsigned int group,
|
||||
unsigned int priority);
|
||||
|
||||
/*
|
||||
* Returns a bitmask of pending interrupts in a group.
|
||||
*/
|
||||
extern unsigned long intc_get_pending(unsigned int group);
|
||||
|
||||
/*
|
||||
* Register a new external interrupt controller. Returns the first
|
||||
* external IRQ number that is assigned to the new controller.
|
||||
*/
|
||||
extern int intc_register_controller(struct irq_controller *ctrl);
|
||||
|
||||
#endif /* __ASM_AVR32_INTC_H */
|
||||
@@ -14,6 +14,11 @@
|
||||
#ifndef __ASSEMBLER__
|
||||
int nmi_enable(void);
|
||||
void nmi_disable(void);
|
||||
|
||||
/*
|
||||
* Returns a bitmask of pending interrupts in a group.
|
||||
*/
|
||||
extern unsigned long intc_get_pending(unsigned int group);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_AVR32_IOCTLS_H */
|
||||
|
||||
@@ -8,13 +8,11 @@
|
||||
#ifndef __ASM_AVR32_PAGE_H
|
||||
#define __ASM_AVR32_PAGE_H
|
||||
|
||||
#include <linux/const.h>
|
||||
|
||||
/* PAGE_SHIFT determines the page size */
|
||||
#define PAGE_SHIFT 12
|
||||
#ifdef __ASSEMBLY__
|
||||
#define PAGE_SIZE (1 << PAGE_SHIFT)
|
||||
#else
|
||||
#define PAGE_SIZE (1UL << PAGE_SHIFT)
|
||||
#endif
|
||||
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
|
||||
#define PAGE_MASK (~(PAGE_SIZE-1))
|
||||
#define PTE_MASK PAGE_MASK
|
||||
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
#ifndef _ASM_SERIAL_H
|
||||
#define _ASM_SERIAL_H
|
||||
|
||||
/*
|
||||
* This assumes you have a 1.8432 MHz clock for your UART.
|
||||
*
|
||||
* It'd be nice if someone built a serial card with a 24.576 MHz
|
||||
* clock, since the 16550A is capable of handling a top speed of 1.5
|
||||
* megabits/second; but this requires the faster clock.
|
||||
*/
|
||||
#define BASE_BAUD (1843200 / 16)
|
||||
|
||||
#endif /* _ASM_SERIAL_H */
|
||||
@@ -0,0 +1,6 @@
|
||||
#ifndef _ASM_XOR_H
|
||||
#define _ASM_XOR_H
|
||||
|
||||
#include <asm-generic/xor.h>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Timer/Counter Unit (TC) registers.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef ATMEL_TC_H
|
||||
#define ATMEL_TC_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
/*
|
||||
* Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
|
||||
* three general-purpose 16-bit timers. These timers share one register bank.
|
||||
* Depending on the SOC, each timer may have its own clock and IRQ, or those
|
||||
* may be shared by the whole TC block.
|
||||
*
|
||||
* These TC blocks may have up to nine external pins: TCLK0..2 signals for
|
||||
* clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
|
||||
* or triggering. Those pins need to be set up for use with the TC block,
|
||||
* else they will be used as GPIOs or for a different controller.
|
||||
*
|
||||
* Although we expect each TC block to have a platform_device node, those
|
||||
* nodes are not what drivers bind to. Instead, they ask for a specific
|
||||
* TC block, by number ... which is a common approach on systems with many
|
||||
* timers. Then they use clk_get() and platform_get_irq() to get clock and
|
||||
* IRQ resources.
|
||||
*/
|
||||
|
||||
struct clk;
|
||||
|
||||
/**
|
||||
* struct atmel_tc - information about a Timer/Counter Block
|
||||
* @pdev: physical device
|
||||
* @iomem: resource associated with the I/O register
|
||||
* @regs: mapping through which the I/O registers can be accessed
|
||||
* @irq: irq for each of the three channels
|
||||
* @clk: internal clock source for each of the three channels
|
||||
* @node: list node, for tclib internal use
|
||||
*
|
||||
* On some platforms, each TC channel has its own clocks and IRQs,
|
||||
* while on others, all TC channels share the same clock and IRQ.
|
||||
* Drivers should clk_enable() all the clocks they need even though
|
||||
* all the entries in @clk may point to the same physical clock.
|
||||
* Likewise, drivers should request irqs independently for each
|
||||
* channel, but they must use IRQF_SHARED in case some of the entries
|
||||
* in @irq are actually the same IRQ.
|
||||
*/
|
||||
struct atmel_tc {
|
||||
struct platform_device *pdev;
|
||||
struct resource *iomem;
|
||||
void __iomem *regs;
|
||||
int irq[3];
|
||||
struct clk *clk[3];
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
|
||||
extern void atmel_tc_free(struct atmel_tc *tc);
|
||||
|
||||
/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
|
||||
extern const u8 atmel_tc_divisors[5];
|
||||
|
||||
|
||||
/*
|
||||
* Two registers have block-wide controls. These are: configuring the three
|
||||
* "external" clocks (or event sources) used by the timer channels; and
|
||||
* synchronizing the timers by resetting them all at once.
|
||||
*
|
||||
* "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
|
||||
* signals. Or, it can mean "external to timer", using the TIOA output from
|
||||
* one of the other two timers that's being run in waveform mode.
|
||||
*/
|
||||
|
||||
#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
|
||||
#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
|
||||
|
||||
#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
|
||||
#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
|
||||
#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
|
||||
#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
|
||||
#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
|
||||
#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
|
||||
#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
|
||||
#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
|
||||
#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
|
||||
#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
|
||||
#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
|
||||
#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
|
||||
#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
|
||||
#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
|
||||
#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
|
||||
#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
|
||||
|
||||
|
||||
/*
|
||||
* Each TC block has three "channels", each with one counter and controls.
|
||||
*
|
||||
* Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
|
||||
* when it's not "external") is silicon-specific. AT91 platforms use one
|
||||
* set of definitions; AVR32 platforms use a different set. Don't hard-wire
|
||||
* such knowledge into your code, use the global "atmel_tc_divisors" ...
|
||||
* where index N is the divisor for clock N+1, else zero to indicate it uses
|
||||
* the 32 KiHz clock.
|
||||
*
|
||||
* The timers can be chained in various ways, and operated in "waveform"
|
||||
* generation mode (including PWM) or "capture" mode (to time events). In
|
||||
* both modes, behavior can be configured in many ways.
|
||||
*
|
||||
* Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
|
||||
* PWM output, and TIOB as either another PWM or as a trigger. Capture mode
|
||||
* uses them only as inputs.
|
||||
*/
|
||||
#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
|
||||
#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
|
||||
|
||||
#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
|
||||
#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
|
||||
#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
|
||||
#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
|
||||
|
||||
#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
|
||||
|
||||
/* Both modes share some CMR bits */
|
||||
#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
|
||||
#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
|
||||
#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
|
||||
#define ATMEL_TC_XC0 (5 << 0)
|
||||
#define ATMEL_TC_XC1 (6 << 0)
|
||||
#define ATMEL_TC_XC2 (7 << 0)
|
||||
#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
|
||||
#define ATMEL_TC_BURST (3 << 4) /* clock gating */
|
||||
#define ATMEL_TC_GATE_NONE (0 << 4)
|
||||
#define ATMEL_TC_GATE_XC0 (1 << 4)
|
||||
#define ATMEL_TC_GATE_XC1 (2 << 4)
|
||||
#define ATMEL_TC_GATE_XC2 (3 << 4)
|
||||
#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
|
||||
|
||||
/* CAPTURE mode CMR bits */
|
||||
#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
|
||||
#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
|
||||
#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
|
||||
#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
|
||||
#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
|
||||
#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
|
||||
#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
|
||||
#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
|
||||
#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
|
||||
#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
|
||||
#define ATMEL_TC_LDRA_NONE (0 << 16)
|
||||
#define ATMEL_TC_LDRA_RISING (1 << 16)
|
||||
#define ATMEL_TC_LDRA_FALLING (2 << 16)
|
||||
#define ATMEL_TC_LDRA_BOTH (3 << 16)
|
||||
#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
|
||||
#define ATMEL_TC_LDRB_NONE (0 << 18)
|
||||
#define ATMEL_TC_LDRB_RISING (1 << 18)
|
||||
#define ATMEL_TC_LDRB_FALLING (2 << 18)
|
||||
#define ATMEL_TC_LDRB_BOTH (3 << 18)
|
||||
|
||||
/* WAVEFORM mode CMR bits */
|
||||
#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
|
||||
#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
|
||||
#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
|
||||
#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
|
||||
#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
|
||||
#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
|
||||
#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
|
||||
#define ATMEL_TC_EEVT (3 << 10) /* external event source */
|
||||
#define ATMEL_TC_EEVT_TIOB (0 << 10)
|
||||
#define ATMEL_TC_EEVT_XC0 (1 << 10)
|
||||
#define ATMEL_TC_EEVT_XC1 (2 << 10)
|
||||
#define ATMEL_TC_EEVT_XC2 (3 << 10)
|
||||
#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
|
||||
#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
|
||||
#define ATMEL_TC_WAVESEL_UP (0 << 13)
|
||||
#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
|
||||
#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
|
||||
#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
|
||||
#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
|
||||
#define ATMEL_TC_ACPA_NONE (0 << 16)
|
||||
#define ATMEL_TC_ACPA_SET (1 << 16)
|
||||
#define ATMEL_TC_ACPA_CLEAR (2 << 16)
|
||||
#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
|
||||
#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
|
||||
#define ATMEL_TC_ACPC_NONE (0 << 18)
|
||||
#define ATMEL_TC_ACPC_SET (1 << 18)
|
||||
#define ATMEL_TC_ACPC_CLEAR (2 << 18)
|
||||
#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
|
||||
#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
|
||||
#define ATMEL_TC_AEEVT_NONE (0 << 20)
|
||||
#define ATMEL_TC_AEEVT_SET (1 << 20)
|
||||
#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
|
||||
#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
|
||||
#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
|
||||
#define ATMEL_TC_ASWTRG_NONE (0 << 22)
|
||||
#define ATMEL_TC_ASWTRG_SET (1 << 22)
|
||||
#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
|
||||
#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
|
||||
#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
|
||||
#define ATMEL_TC_BCPB_NONE (0 << 24)
|
||||
#define ATMEL_TC_BCPB_SET (1 << 24)
|
||||
#define ATMEL_TC_BCPB_CLEAR (2 << 24)
|
||||
#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
|
||||
#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
|
||||
#define ATMEL_TC_BCPC_NONE (0 << 26)
|
||||
#define ATMEL_TC_BCPC_SET (1 << 26)
|
||||
#define ATMEL_TC_BCPC_CLEAR (2 << 26)
|
||||
#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
|
||||
#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
|
||||
#define ATMEL_TC_BEEVT_NONE (0 << 28)
|
||||
#define ATMEL_TC_BEEVT_SET (1 << 28)
|
||||
#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
|
||||
#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
|
||||
#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
|
||||
#define ATMEL_TC_BSWTRG_NONE (0 << 30)
|
||||
#define ATMEL_TC_BSWTRG_SET (1 << 30)
|
||||
#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
|
||||
#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
|
||||
|
||||
#define ATMEL_TC_CV 0x10 /* counter Value */
|
||||
#define ATMEL_TC_RA 0x14 /* register A */
|
||||
#define ATMEL_TC_RB 0x18 /* register B */
|
||||
#define ATMEL_TC_RC 0x1c /* register C */
|
||||
|
||||
#define ATMEL_TC_SR 0x20 /* status (read-only) */
|
||||
/* Status-only flags */
|
||||
#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
|
||||
#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
|
||||
#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
|
||||
|
||||
#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
|
||||
#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
|
||||
#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
|
||||
|
||||
/* Status and IRQ flags */
|
||||
#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
|
||||
#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
|
||||
#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
|
||||
#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
|
||||
#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
|
||||
#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
|
||||
#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
|
||||
#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Platform data definitions for Atmel USBA gadget driver.
|
||||
*/
|
||||
#ifndef __LINUX_USB_USBA_H
|
||||
#define __LINUX_USB_USBA_H
|
||||
|
||||
struct usba_ep_data {
|
||||
char *name;
|
||||
int index;
|
||||
int fifo_size;
|
||||
int nr_banks;
|
||||
int can_dma;
|
||||
int can_isoc;
|
||||
};
|
||||
|
||||
struct usba_platform_data {
|
||||
int vbus_pin;
|
||||
int num_ep;
|
||||
struct usba_ep_data ep[0];
|
||||
};
|
||||
|
||||
#endif /* __LINUX_USB_USBA_H */
|
||||
Reference in New Issue
Block a user