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Merge branch 'master'

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This commit is contained in:
Jeff Garzik
2005-11-04 21:39:31 -05:00
parent ce1eeb95fc 7015faa7df
commit c2cc87ca95
1852 changed files with 103804 additions and 64836 deletions
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include/asm-alpha/semaphore.h
-3
View File
@@ -26,9 +26,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-arm/arch-clps711x/hardware.h
-117
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@@ -235,121 +235,4 @@
#define CEIVA_PB0_BLK_BTN (1<<0)
#endif // #if defined (CONFIG_ARCH_CEIVA)
#if defined (CONFIG_MACH_MP1000)
/* NOR FLASH */
#define MP1000_NIO_BASE 0xf9000000 /* virtual */
#define MP1000_NIO_START CS0_PHYS_BASE /* physical */
#define MP1000_NIO_SIZE 0x00400000
/* DSP Interface */
#define MP1000_DSP_BASE 0xfa000000 /* virtual */
#define MP1000_DSP_START CS1_PHYS_BASE /* physical */
#define MP1000_DSP_SIZE 0x00100000
/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
#define MP1000_LIO_BASE 0xfb000000 /* virtual */
#define MP1000_LIO_START CS2_PHYS_BASE /* physical */
#define MP1000_LIO_SIZE 0x00100000
/* NAND FLASH */
#define MP1000_FIO_BASE 0xfc000000 /* virtual */
#define MP1000_FIO_START CS3_PHYS_BASE /* physical */
#define MP1000_FIO_SIZE 0x00800000
/* Ethernet */
#define MP1000_EIO_BASE 0xfd000000 /* virtual */
#define MP1000_EIO_START CS4_PHYS_BASE /* physical */
#define MP1000_EIO_SIZE 0x00100000
#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
/* IDE */
#define MP1000_IDE_BASE 0xfe000000 /* virtual */
#define MP1000_IDE_START CS5_PHYS_BASE /* physical */
#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
#define IRQ_HARDDISK IRQ_EINT2
/*
* IDE registers definition
*/
#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
#define IDE_BASE_OFF (MP1000_IDE_BASE)
#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
#define IDE_IRQ IRQ_EINT2
#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
#define RTC_ALWAYS_BCD 0
/*
// Definitions of the bit fields in the HwPortA register for the
// MP1000 board.
*/
#define HwPortAKeyboardRow1 0x00000001
#define HwPortAKeyboardRow2 0x00000002
#define HwPortAKeyboardRow3 0x00000004
#define HwPortAKeyboardRow4 0x00000008
#define HwPortAKeyboardRow5 0x00000010
#define HwPortAKeyboardRow6 0x00000020
#define HwPortALCDEnable 0x00000040
#define HwPortAOffhook 0x00000080
/*
// Definitions of the bit fields in the HwPortB register for the
// MP1000 board.
*/
#define HwPortBL3Mode 0x00000001
#define HwPortBL3Clk 0x00000002
#define HwPortBSClk 0x00000001
#define HwPortBSData 0x00000002
#define HwPortBL3Data 0x00000004
#define HwPortBMute 0x00000008
#define HwPortBQD0 0x00000010
#define HwPortBQD1 0x00000020
#define HwPortBQD2 0x00000040
#define HwPortBQD3 0x00000080
/*
// Definitions of the bit fields in the HwPortD register for the
// MP1000 board.
*/
#define HwPortDLED1 0x00000001
#define HwPortDLED2 0x00000002
#define HwPortDLED3 0x00000004
#define HwPortDLED4 0x00000008
#define HwPortDLED5 0x00000010
#define HwPortDEECS 0x00000020
#define HwPortBRTS 0x00000040
#define HwPortBRI 0x00000080
/*
// Definitions of the bit fields in the HwPortE register for the
// MP1000 board.
*/
#define HwPortECLE 0x00000001
#define HwPortESepromDOut 0x00000001
#define HwPortEALE 0x00000002
#define HwPortESepromDIn 0x00000002
#define HwPortENANDCS 0x00000004
#define HwPortESepromCLK 0x00000004
#endif // #if defined (CONFIG_MACH_MP1000)
#endif
include/asm-arm/arch-clps711x/mp1000-seprom.h
-77
View File
@@ -1,77 +0,0 @@
#ifndef MP1000_SEPROM_H
#define MP1000_SEPROM_H
/*
* mp1000-seprom.h
*
*
* This file contains the Serial EEPROM definitions for the MP1000 board
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define COMMAND_ERASE (0x1C0)
#define COMMAND_ERASE_ALL (0x120)
#define COMMAND_WRITE_DISABLE (0x100)
#define COMMAND_WRITE_ENABLE (0x130)
#define COMMAND_READ (0x180)
#define COMMAND_WRITE (0x140)
#define COMMAND_WRITE_ALL (0x110)
//
// Serial EEPROM data format
//
#define PACKED __attribute__ ((packed))
typedef struct _EEPROM {
union {
unsigned char eprom_byte_data[128];
unsigned short eprom_short_data[64];
struct {
unsigned char version PACKED; // EEPROM Version "1" for now
unsigned char box_id PACKED; // Box ID (Standalone, SOHO, embedded, etc)
unsigned char major_hw_version PACKED; // Major Hardware version (Hex)
unsigned char minor_hw_version PACKED; // Minor Hardware Version (Hex)
unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
unsigned char mfg_serial_number[10] PACKED; // Manufacturer Serial number
unsigned char mfg_date[3] PACKED; // Date of Mfg (Formatted YY:MM:DD)
unsigned char country PACKED; // Country of deployment
unsigned char mac_Address[6] PACKED; // MAC Address
unsigned char oem_string[20] PACKED; // OEM ID string
unsigned short feature_bits1 PACKED; // Feature Bits 1
unsigned short feature_bits2 PACKED; // Feature Bits 2
unsigned char filler[75] PACKED; // Unused/Undefined “0” initialized
unsigned short checksum PACKED; // byte accumulated short checksum
} eprom_struct;
} variant;
} eeprom_struct;
/* These settings must be mutually exclusive */
#define FEATURE_BITS1_DRAMSIZE_16MEG 0x0001 /* 0 signifies 4 MEG system */
#define FEATURE_BITS1_DRAMSIZE_8MEG 0x0002 /* 1 in bit 1 = 8MEG system */
#define FEATURE_BITS1_DRAMSIZE_64MEG 0x0004 /* 1 in bit 2 = 64MEG system */
#define FEATURE_BITS1_CPUIS90MEG 0x0010
extern void seprom_init(void);
extern eeprom_struct* get_seprom_ptr(void);
extern unsigned char* get_eeprom_mac_address(void);
#endif /* MP1000_SEPROM_H */
include/asm-arm/arch-iop3xx/iop321.h
+1 -1
View File
@@ -40,7 +40,7 @@
#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
//#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1)
/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
#define IOP321_PCI_LOWER_MEM_PA 0x80000000
#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
include/asm-arm/arch-ixp2000/enp2611.h
+14 -2
View File
@@ -21,8 +21,20 @@
#ifndef __ENP2611_H
#define __ENP2611_H
#define ENP2611_GPIO_SCL 0x07
#define ENP2611_GPIO_SDA 0x06
#define ENP2611_CALEB_PHYS_BASE 0xc5000000
#define ENP2611_CALEB_VIRT_BASE 0xfe000000
#define ENP2611_CALEB_SIZE 0x00100000
#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000
#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000
#define ENP2611_PM3386_0_SIZE 0x00100000
#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000
#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000
#define ENP2611_PM3386_1_SIZE 0x00100000
#define ENP2611_GPIO_SCL 7
#define ENP2611_GPIO_SDA 6
#endif
include/asm-arm/arch-ixp2000/irqs.h
+34 -1
View File
@@ -67,12 +67,45 @@
#define IRQ_IXP2000_PCIA 40
#define IRQ_IXP2000_PCIB 41
#define NR_IXP2000_IRQS 42
/* Int sources from IRQ_ERROR_STATUS */
#define IRQ_IXP2000_DRAM0_MIN_ERR 42
#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
#define IRQ_IXP2000_DRAM1_MIN_ERR 44
#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
#define IRQ_IXP2000_DRAM2_MIN_ERR 46
#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
/* 48-57 reserved */
#define IRQ_IXP2000_SRAM0_ERR 58
#define IRQ_IXP2000_SRAM1_ERR 59
#define IRQ_IXP2000_SRAM2_ERR 60
#define IRQ_IXP2000_SRAM3_ERR 61
/* 62-65 reserved */
#define IRQ_IXP2000_MEDIA_ERR 66
#define IRQ_IXP2000_PCI_ERR 67
#define IRQ_IXP2000_SP_INT 68
#define NR_IXP2000_IRQS 69
#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
#define IXP2000_VALID_ERR_IRQ_MASK (\
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
/*
* This allows for all the on-chip sources plus up to 32 CPLD based
* IRQs. Should be more than enough.
include/asm-arm/arch-ixp2000/ixdp2x01.h
+1 -1
View File
@@ -22,7 +22,7 @@
#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40)
#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40)
include/asm-arm/arch-ixp2000/ixp2000-regs.h
+4 -3
View File
@@ -59,14 +59,15 @@
#define IXP2000_CAP_SIZE 0x00100000
/*
* Addresses for specific on-chip peripherals
* Addresses for specific on-chip peripherals.
*/
#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
#define IXP2000_UART_PHYS_BASE 0xc0030000
#define IXP2000_UART_VIRT_BASE 0xfef30000
#define IXP2000_TIMER_VIRT_BASE 0xfef20000
#define IXP2000_GPIO_VIRT_BASE 0Xfef10000
#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
#define IXP2000_GPIO_VIRT_BASE 0xfef10000
/*
* Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
@@ -252,7 +253,7 @@
#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Centrolfunction bit */
#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */
#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
/* These are from the IRQ register in the PCI ISR register */
include/asm-arm/arch-ixp2000/system.h
+9 -14
View File
@@ -26,29 +26,24 @@ static inline void arch_reset(char mode)
* RedBoot bank.
*/
if (machine_is_ixdp2401()) {
*IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
| IXDP2X01_CPLD_FLASH_INTERN);
*IXDP2X01_CPLD_RESET_REG = 0xffffffff;
ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
((0 >> IXDP2X01_FLASH_WINDOW_BITS)
| IXDP2X01_CPLD_FLASH_INTERN));
ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
}
/*
* On IXDP2801 we need to write this magic sequence to the CPLD
* to cause a complete reset of the CPU and all external devices
* and moves the flash bank register back to 0.
* and move the flash bank register back to 0.
*/
if (machine_is_ixdp2801()) {
unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
*IXDP2X01_CPLD_RESET_REG = reset_reg;
mb();
*IXDP2X01_CPLD_RESET_REG = 0x80000000;
ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
}
/*
* We do a reset all if we are PCI master. We could be a slave and we
* don't want to do anything funky on the PCI bus.
*/
if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
*(IXP2000_RESET0) |= (RSTALL);
}
ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
}
include/asm-arm/arch-ixp2000/uengine.h
+62
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@@ -0,0 +1,62 @@
/*
* Generic library functions for the microengines found on the Intel
* IXP2000 series of network processors.
*
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of the
* License, or (at your option) any later version.
*/
#ifndef __IXP2000_UENGINE_H
#define __IXP2000_UENGINE_H
extern u32 ixp2000_uengine_mask;
struct ixp2000_uengine_code
{
u32 cpu_model_bitmask;
u8 cpu_min_revision;
u8 cpu_max_revision;
u32 uengine_parameters;
struct ixp2000_reg_value {
int reg;
u32 value;
} *initial_reg_values;
int num_insns;
u8 *insns;
};
u32 ixp2000_uengine_csr_read(int uengine, int offset);
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
void ixp2000_uengine_reset(u32 uengine_mask);
void ixp2000_uengine_set_mode(int uengine, u32 mode);
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
void ixp2000_uengine_init_context(int uengine, int context, int pc);
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
#endif
include/asm-arm/arch-ixp4xx/io.h
+40 -34
View File
@@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr)
#define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x)
#define __arch_iounmap(a) __ixp4xx_iounmap(a)
#define writeb(p, v) __ixp4xx_writeb(p, v)
#define writew(p, v) __ixp4xx_writew(p, v)
#define writel(p, v) __ixp4xx_writel(p, v)
#define writeb(v, p) __ixp4xx_writeb(v, p)
#define writew(v, p) __ixp4xx_writew(v, p)
#define writel(v, p) __ixp4xx_writel(v, p)
#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
@@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr)
#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
static inline void
__ixp4xx_writeb(u8 value, u32 addr)
__ixp4xx_writeb(u8 value, volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START) {
@@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr)
}
static inline void
__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
__ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
{
while (count--)
writeb(*vaddr++, bus_addr);
}
static inline void
__ixp4xx_writew(u16 value, u32 addr)
__ixp4xx_writew(u16 value, volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START) {
@@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr)
}
static inline void
__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
__ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
{
while (count--)
writew(*vaddr++, bus_addr);
}
static inline void
__ixp4xx_writel(u32 value, u32 addr)
__ixp4xx_writel(u32 value, volatile void __iomem *p)
{
u32 addr = (u32)p;
if (addr >= VMALLOC_START) {
__raw_writel(value, addr);
return;
@@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr)
}
static inline void
__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
__ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
{
while (count--)
writel(*vaddr++, bus_addr);
}
static inline unsigned char
__ixp4xx_readb(u32 addr)
__ixp4xx_readb(const volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START)
@@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr)
}
static inline void
__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
__ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readb(bus_addr);
}
static inline unsigned short
__ixp4xx_readw(u32 addr)
__ixp4xx_readw(const volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 n, byte_enables, data;
if (addr >= VMALLOC_START)
@@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr)
}
static inline void
__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
__ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readw(bus_addr);
}
static inline unsigned long
__ixp4xx_readl(u32 addr)
__ixp4xx_readl(const volatile void __iomem *p)
{
u32 addr = (u32)p;
u32 data;
if (addr >= VMALLOC_START)
@@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr)
}
static inline void
__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
__ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
{
while (count--)
*vaddr++ = readl(bus_addr);
@@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
check_signature(unsigned long bus_addr, const unsigned char *signature,
check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature,
int length)
{
int retval = 0;
@@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
static inline unsigned int
__ixp4xx_ioread8(void __iomem *addr)
__ixp4xx_ioread8(const void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
@@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return (unsigned int)__raw_readb(port);
#else
return (unsigned int)__ixp4xx_readb(port);
return (unsigned int)__ixp4xx_readb(addr);
#endif
}
static inline void
__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
__ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
@@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsb(addr, vaddr, count);
#else
__ixp4xx_readsb(port, vaddr, count);
__ixp4xx_readsb(addr, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread16(void __iomem *addr)
__ixp4xx_ioread16(const void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
@@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le16_to_cpu(__raw_readw((u32)port));
#else
return (unsigned int)__ixp4xx_readw((u32)port);
return (unsigned int)__ixp4xx_readw(addr);
#endif
}
static inline void
__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
__ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
@@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsw(addr, vaddr, count);
#else
__ixp4xx_readsw(port, vaddr, count);
__ixp4xx_readsw(addr, vaddr, count);
#endif
}
static inline unsigned int
__ixp4xx_ioread32(void __iomem *addr)
__ixp4xx_ioread32(const void __iomem *addr)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
@@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
return le32_to_cpu(__raw_readl((u32)port));
#else
return (unsigned int)__ixp4xx_readl((u32)port);
return (unsigned int)__ixp4xx_readl(addr);
#endif
}
}
static inline void
__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
__ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
{
unsigned long port = (unsigned long __force)addr;
if (__is_io_address(port))
@@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_readsl(addr, vaddr, count);
#else
__ixp4xx_readsl(port, vaddr, count);
__ixp4xx_readsl(addr, vaddr, count);
#endif
}
@@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writeb(value, port);
#else
__ixp4xx_writeb(value, port);
__ixp4xx_writeb(value, addr);
#endif
}
@@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesb(addr, vaddr, count);
#else
__ixp4xx_writesb(port, vaddr, count);
__ixp4xx_writesb(addr, vaddr, count);
#endif
}
@@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writew(cpu_to_le16(value), addr);
#else
__ixp4xx_writew(value, port);
__ixp4xx_writew(value, addr);
#endif
}
@@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesw(addr, vaddr, count);
#else
__ixp4xx_writesw(port, vaddr, count);
__ixp4xx_writesw(addr, vaddr, count);
#endif
}
@@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writel(cpu_to_le32(value), port);
#else
__ixp4xx_writel(value, port);
__ixp4xx_writel(value, addr);
#endif
}
@@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
__raw_writesl(addr, vaddr, count);
#else
__ixp4xx_writesl(port, vaddr, count);
__ixp4xx_writesl(addr, vaddr, count);
#endif
}
include/asm-arm/arch-realview/debug-macro.S
+38
View File
@@ -0,0 +1,38 @@
/* linux/include/asm-arm/arch-realview/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <asm/hardware/amba_serial.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x10000000
movne \rx, #0xf1000000 @ virtual base
orr \rx, \rx, #0x00009000
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #UART01x_DR]
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm
include/asm-ppc64/pmc.h → include/asm-arm/arch-realview/dma.h
+10 -14
View File
@@ -1,6 +1,8 @@
/*
* pmc.h
* Copyright (C) 2004 David Gibson, IBM Corporation
* linux/include/asm-arm/arch-realview/dma.h
*
* Copyright (C) 2003 ARM Limited.
* Copyright (C) 1997,1998 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,18 +16,12 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _PPC64_PMC_H
#define _PPC64_PMC_H
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <asm/ptrace.h>
#define MAX_DMA_ADDRESS 0xffffffff
#define MAX_DMA_CHANNELS 0
typedef void (*perf_irq_t)(struct pt_regs *);
int reserve_pmc_hardware(perf_irq_t new_perf_irq);
void release_pmc_hardware(void);
void power4_enable_pmcs(void);
#endif /* _PPC64_PMC_H */
#endif /* _ASM_ARCH_DMA_H */
include/asm-arm/arch-realview/entry-macro.S
+49
View File
@@ -0,0 +1,49 @@
/*
* include/asm-arm/arch-realview/entry-macro.S
*
* Low-level IRQ helper macros for RealView platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/gic.h>
.macro disable_fiq
.endm
/*
* The interrupt numbering scheme is defined in the
* interrupt controller spec. To wit:
*
* Interrupts 0-15 are IPI
* 16-28 are reserved
* 29-31 are local. We allow 30 to be used for the watchdog.
* 32-1020 are global
* 1021-1022 are reserved
* 1023 is "spurious" (no interrupt)
*
* For now, we ignore all local interrupts so only return an interrupt if it's
* between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
*
* A simple read from the controller will tell us the number of the highest
* priority enabled interrupt. We then just need to check whether it is in the
* valid range for an IRQ (30-1020 inclusive).
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
ldr \tmp, =1021
bic \irqnr, \irqstat, #0x1c00
cmp \irqnr, #29
cmpcc \irqnr, \irqnr
cmpne \irqnr, \tmp
cmpcs \irqnr, \irqnr
.endm
include/asm-ppc64/iSeries/ItSpCommArea.h → include/asm-arm/arch-realview/hardware.h
+13 -19
View File
@@ -1,6 +1,9 @@
/*
* ItSpCommArea.h
* Copyright (C) 2001 Mike Corrigan IBM Corporation
* linux/include/asm-arm/arch-realview/hardware.h
*
* This file contains the hardware definitions of the RealView boards.
*
* Copyright (C) 2003 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,24 +17,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#ifndef _ITSPCOMMAREA_H
#define _ITSPCOMMAREA_H
#include <asm/sizes.h>
#include <asm/arch/platform.h>
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
struct SpCommArea {
u32 xDesc; // Descriptor (only in new formats) 000-003
u8 xFormat; // Format (only in new formats) 004-004
u8 xRsvd1[11]; // Reserved 005-00F
u64 xRawTbAtIplStart; // Raw HW TB value when IPL is started 010-017
u64 xRawTodAtIplStart; // Raw HW TOD value when IPL is started 018-01F
u64 xBcdTimeAtIplStart; // BCD time when IPL is started 020-027
u64 xBcdTimeAtOsStart; // BCD time when OS passed control 028-02F
u8 xRsvd2[80]; // Reserved 030-07F
};
extern struct SpCommArea xSpCommArea;
#endif /* _ITSPCOMMAREA_H */
#endif
include/asm-ppc64/iSeries/HvCallSm.h → include/asm-arm/arch-realview/io.h
+14 -18
View File
@@ -1,6 +1,7 @@
/*
* HvCallSm.h
* Copyright (C) 2001 Mike Corrigan IBM Corporation
* linux/include/asm-arm/arch-realview/io.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,25 +15,20 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _HVCALLSM_H
#define _HVCALLSM_H
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/*
* This file contains the "hypervisor call" interface which is used to
* drive the hypervisor from the OS.
*/
#define IO_SPACE_LIMIT 0xffffffff
#include <asm/iSeries/HvCallSc.h>
#include <asm/iSeries/HvTypes.h>
#define HvCallSmGet64BitsOfAccessMap HvCallSm + 11
static inline u64 HvCallSm_get64BitsOfAccessMap(HvLpIndex lpIndex,
u64 indexIntoBitMap)
static inline void __iomem *__io(unsigned long addr)
{
return HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, indexIntoBitMap);
return (void __iomem *)addr;
}
#endif /* _HVCALLSM_H */
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
#endif
include/asm-arm/arch-realview/irqs.h
+103
View File
@@ -0,0 +1,103 @@
/*
* linux/include/asm-arm/arch-realview/irqs.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/arch/platform.h>
/*
* IRQ interrupts definitions are the same the INT definitions
* held within platform.h
*/
#define IRQ_GIC_START 32
#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
#define IRQ_USB (IRQ_GIC_START + INT_USB)
#define IRQMASK_WDOGINT INTMASK_WDOGINT
#define IRQMASK_SOFTINT INTMASK_SOFTINT
#define IRQMASK_COMMRx INTMASK_COMMRx
#define IRQMASK_COMMTx INTMASK_COMMTx
#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
#define IRQMASK_RTCINT INTMASK_RTCINT
#define IRQMASK_SSPINT INTMASK_SSPINT
#define IRQMASK_UARTINT0 INTMASK_UARTINT0
#define IRQMASK_UARTINT1 INTMASK_UARTINT1
#define IRQMASK_UARTINT2 INTMASK_UARTINT2
#define IRQMASK_SCIINT INTMASK_SCIINT
#define IRQMASK_CLCDINT INTMASK_CLCDINT
#define IRQMASK_DMAINT INTMASK_DMAINT
#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
#define IRQMASK_MBXINT INTMASK_MBXINT
#define IRQMASK_GNDINT INTMASK_GNDINT
#define IRQMASK_MMCI0B INTMASK_MMCI0B
#define IRQMASK_MMCI1B INTMASK_MMCI1B
#define IRQMASK_KMI0 INTMASK_KMI0
#define IRQMASK_KMI1 INTMASK_KMI1
#define IRQMASK_SCI3 INTMASK_SCI3
#define IRQMASK_UART3 INTMASK_UART3
#define IRQMASK_CLCD INTMASK_CLCD
#define IRQMASK_TOUCH INTMASK_TOUCH
#define IRQMASK_KEYPAD INTMASK_KEYPAD
#define IRQMASK_DoC INTMASK_DoC
#define IRQMASK_MMCI0A INTMASK_MMCI0A
#define IRQMASK_MMCI1A INTMASK_MMCI1A
#define IRQMASK_AACI INTMASK_AACI
#define IRQMASK_ETH INTMASK_ETH
#define IRQMASK_USB INTMASK_USB
#define NR_IRQS (IRQ_GIC_START + 64)
include/asm-arm/arch-realview/memory.h
+38
View File
@@ -0,0 +1,38 @@
/*
* linux/include/asm-arm/arch-realview/memory.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x00000000)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus(x) ((x) - PAGE_OFFSET)
#define __bus_to_virt(x) ((x) + PAGE_OFFSET)
#endif
include/asm-arm/arch-realview/param.h
+19
View File
@@ -0,0 +1,19 @@
/*
* linux/include/asm-arm/arch-realview/param.h
*
* Copyright (C) 2002 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
include/asm-arm/arch-realview/platform.h
+395
View File
@@ -0,0 +1,395 @@
/*
* linux/include/asm-arm/arch-realview/platform.h
*
* Copyright (c) ARM Limited 2003. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __address_h
#define __address_h 1
/*
* Memory definitions
*/
#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
#define REALVIEW_BOOT_ROM_HI 0x30000000
#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
#define REALVIEW_BOOT_ROM_SIZE SZ_64M
#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
#define REALVIEW_SSRAM_SIZE SZ_2M
#define REALVIEW_FLASH_BASE 0x40000000
#define REALVIEW_FLASH_SIZE SZ_64M
/*
* SDRAM
*/
#define REALVIEW_SDRAM_BASE 0x00000000
/*
* Logic expansion modules
*
*/
/* ------------------------------------------------------------------------
* RealView Registers
* ------------------------------------------------------------------------
*
*/
#define REALVIEW_SYS_ID_OFFSET 0x00
#define REALVIEW_SYS_SW_OFFSET 0x04
#define REALVIEW_SYS_LED_OFFSET 0x08
#define REALVIEW_SYS_OSC0_OFFSET 0x0C
#define REALVIEW_SYS_OSC1_OFFSET 0x10
#define REALVIEW_SYS_OSC2_OFFSET 0x14
#define REALVIEW_SYS_OSC3_OFFSET 0x18
#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
#define REALVIEW_SYS_LOCK_OFFSET 0x20
#define REALVIEW_SYS_100HZ_OFFSET 0x24
#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
#define REALVIEW_SYS_FLAGS_OFFSET 0x30
#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
#define REALVIEW_SYS_PCICTL_OFFSET 0x44
#define REALVIEW_SYS_MCI_OFFSET 0x48
#define REALVIEW_SYS_FLASH_OFFSET 0x4C
#define REALVIEW_SYS_CLCD_OFFSET 0x50
#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
#define REALVIEW_SYS_24MHz_OFFSET 0x5C
#define REALVIEW_SYS_MISC_OFFSET 0x60
#define REALVIEW_SYS_IOSEL_OFFSET 0x70
#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80
#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84
#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88
#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C
#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90
#define REALVIEW_SYS_BASE 0x10000000
#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
/*
* Values for REALVIEW_SYS_RESET_CTRL
*/
#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01
#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02
#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03
#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04
#define REALVIEW_SYS_CTRL_RESET_POR 0x05
#define REALVIEW_SYS_CTRL_RESET_DoC 0x06
#define REALVIEW_SYS_CTRL_LED (1 << 0)
/* ------------------------------------------------------------------------
* RealView control registers
* ------------------------------------------------------------------------
*/
/*
* REALVIEW_IDFIELD
*
* 31:24 = manufacturer (0x41 = ARM)
* 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
* 15:12 = FPGA (0x3 = XVC600 or XVC600E)
* 11:4 = build value
* 3:0 = revision number (0x1 = rev B (AHB))
*/
/*
* REALVIEW_SYS_LOCK
* control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
* SYS_CLD, SYS_BOOTCS
*/
#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
/*
* REALVIEW_SYS_FLASH
*/
#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
/*
* REALVIEW_INTREG
* - used to acknowledge and control MMCI and UART interrupts
*/
#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
/* write 1 to acknowledge and clear */
#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
/*
* REALVIEW peripheral addresses
*/
#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
/* Reserved 0x10003000 */
#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
/* Reserved 0x1000F000 */
#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
/* Reserved 0x10016000 */
#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */
/* Reserved 0x1001A000 - 0x1001FFFF */
#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
/* Reserved 0x10090000 - 0x100EFFFF */
#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
/* PCI space */
#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
#define REALVIEW_PCI_CFG_BASE 0x42000000
#define REALVIEW_PCI_MEM_BASE0 0x44000000
#define REALVIEW_PCI_MEM_BASE1 0x50000000
#define REALVIEW_PCI_MEM_BASE2 0x60000000
/* Sizes of above maps */
#define REALVIEW_PCI_BASE_SIZE 0x01000000
#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
/*
* Disk on Chip
*/
#define REALVIEW_DOC_BASE 0x2C000000
#define REALVIEW_DOC_SIZE (16 << 20)
#define REALVIEW_DOC_PAGE_SIZE 512
#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
#define ERASE_UNIT_PAGES 32
#define START_PAGE 0x80
/*
* LED settings, bits [7:0]
*/
#define REALVIEW_SYS_LED0 (1 << 0)
#define REALVIEW_SYS_LED1 (1 << 1)
#define REALVIEW_SYS_LED2 (1 << 2)
#define REALVIEW_SYS_LED3 (1 << 3)
#define REALVIEW_SYS_LED4 (1 << 4)
#define REALVIEW_SYS_LED5 (1 << 5)
#define REALVIEW_SYS_LED6 (1 << 6)
#define REALVIEW_SYS_LED7 (1 << 7)
#define ALL_LEDS 0xFF
#define LED_BANK REALVIEW_SYS_LED
/*
* Control registers
*/
#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
/* ------------------------------------------------------------------------
* Interrupts - bit assignment (primary)
* ------------------------------------------------------------------------
*/
#define INT_WDOGINT 0 /* Watchdog timer */
#define INT_SOFTINT 1 /* Software interrupt */
#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
#define INT_GPIOINT0 6 /* GPIO 0 */
#define INT_GPIOINT1 7 /* GPIO 1 */
#define INT_GPIOINT2 8 /* GPIO 2 */
/* 9 reserved */
#define INT_RTCINT 10 /* Real Time Clock */
#define INT_SSPINT 11 /* Synchronous Serial Port */
#define INT_UARTINT0 12 /* UART 0 on development chip */
#define INT_UARTINT1 13 /* UART 1 on development chip */
#define INT_UARTINT2 14 /* UART 2 on development chip */
#define INT_UARTINT3 15 /* UART 3 on development chip */
#define INT_SCIINT 16 /* Smart Card Interface */
#define INT_MMCI0A 17 /* Multimedia Card 0A */
#define INT_MMCI0B 18 /* Multimedia Card 0B */
#define INT_AACI 19 /* Audio Codec */
#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
#define INT_CHARLCD 22 /* Character LCD */
#define INT_CLCDINT 23 /* CLCD controller */
#define INT_DMAINT 24 /* DMA controller */
#define INT_PWRFAILINT 25 /* Power failure */
#define INT_PISMO 26
#define INT_DoC 27 /* Disk on Chip memory controller */
#define INT_ETH 28 /* Ethernet controller */
#define INT_USB 29 /* USB controller */
#define INT_TSPENINT 30 /* Touchscreen pen */
#define INT_TSKPADINT 31 /* Touchscreen keypad */
/*
* Interrupt bit positions
*
*/
#define INTMASK_WDOGINT (1 << INT_WDOGINT)
#define INTMASK_SOFTINT (1 << INT_SOFTINT)
#define INTMASK_COMMRx (1 << INT_COMMRx)
#define INTMASK_COMMTx (1 << INT_COMMTx)
#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
#define INTMASK_RTCINT (1 << INT_RTCINT)
#define INTMASK_SSPINT (1 << INT_SSPINT)
#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
#define INTMASK_SCIINT (1 << INT_SCIINT)
#define INTMASK_MMCI0A (1 << INT_MMCI0A)
#define INTMASK_MMCI0B (1 << INT_MMCI0B)
#define INTMASK_AACI (1 << INT_AACI)
#define INTMASK_KMI0 (1 << INT_KMI0)
#define INTMASK_KMI1 (1 << INT_KMI1)
#define INTMASK_CHARLCD (1 << INT_CHARLCD)
#define INTMASK_CLCDINT (1 << INT_CLCDINT)
#define INTMASK_DMAINT (1 << INT_DMAINT)
#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
#define INTMASK_PISMO (1 << INT_PISMO)
#define INTMASK_DoC (1 << INT_DoC)
#define INTMASK_ETH (1 << INT_ETH)
#define INTMASK_USB (1 << INT_USB)
#define INTMASK_TSPENINT (1 << INT_TSPENINT)
#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
#define MAXIRQNUM 31
#define MAXFIQNUM 31
#define MAXSWINUM 31
/*
* Application Flash
*
*/
#define FLASH_BASE REALVIEW_FLASH_BASE
#define FLASH_SIZE REALVIEW_FLASH_SIZE
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
#define FLASH_BLOCK_SIZE SZ_128K
/*
* Boot Flash
*
*/
#define EPROM_BASE REALVIEW_BOOT_ROM_HI
#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE
#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
/*
* Clean base - dummy
*
*/
#define CLEAN_BASE EPROM_BASE
/*
* System controller bit assignment
*/
#define REALVIEW_REFCLK 0
#define REALVIEW_TIMCLK 1
#define REALVIEW_TIMER1_EnSel 15
#define REALVIEW_TIMER2_EnSel 17
#define REALVIEW_TIMER3_EnSel 19
#define REALVIEW_TIMER4_EnSel 21
#define MAX_TIMER 2
#define MAX_PERIOD 699050
#define TICKS_PER_uSEC 1
/*
* These are useconds NOT ticks.
*
*/
#define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
#define mSEC_10 (mSEC_1 * 10)
#define mSEC_25 (mSEC_1 * 25)
#define SEC_1 (mSEC_1 * 1000)
#define REALVIEW_CSR_BASE 0x10000000
#define REALVIEW_CSR_SIZE 0x10000000
#endif
/* END */
include/asm-arm/arch-realview/system.h
+51
View File
@@ -0,0 +1,51 @@
/*
* linux/include/asm-arm/arch-realview/system.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/platform.h>
static inline void arch_idle(void)
{
/*
* This should do all the clock switching
* and wait for interrupt tricks
*/
cpu_do_idle();
}
static inline void arch_reset(char mode)
{
unsigned int hdr_ctrl = (IO_ADDRESS(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET);
unsigned int val;
/*
* To reset, we hit the on-board reset register
* in the system FPGA
*/
val = __raw_readl(hdr_ctrl);
val |= REALVIEW_SYS_CTRL_RESET_CONFIGCLR;
__raw_writel(val, hdr_ctrl);
}
#endif
include/asm-arm/arch-realview/timex.h
+23
View File
@@ -0,0 +1,23 @@
/*
* linux/include/asm-arm/arch-realview/timex.h
*
* RealView architecture timex specifications
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define CLOCK_TICK_RATE (50000000 / 16)
include/asm-arm/arch-realview/uncompress.h
+54
View File
@@ -0,0 +1,54 @@
/*
* linux/include/asm-arm/arch-realview/uncompress.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <asm/hardware.h>
#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
#define AMBA_UART_FR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
/*
* This does not append a newline
*/
static void putstr(const char *s)
{
while (*s) {
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = *s;
if (*s == '\n') {
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = '\r';
}
s++;
}
while (AMBA_UART_FR & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
include/asm-arm/arch-realview/vmalloc.h
+21
View File
@@ -0,0 +1,21 @@
/*
* linux/include/asm-arm/arch-realview/vmalloc.h
*
* Copyright (C) 2003 ARM Limited
* Copyright (C) 2000 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
include/asm-arm/arch-s3c2410/regs-iis.h
+1
View File
@@ -55,6 +55,7 @@
#define S3C2410_IISMOD_16FS (0<<0)
#define S3C2410_IISMOD_32FS (1<<0)
#define S3C2410_IISMOD_48FS (2<<0)
#define S3C2410_IISMOD_FS_MASK (3<<0)
#define S3C2410_IISPSR (0x08)
#define S3C2410_IISPSR_INTMASK (31<<5)
include/asm-arm/cpu.h
+1
View File
@@ -16,6 +16,7 @@
struct cpuinfo_arm {
struct cpu cpu;
#ifdef CONFIG_SMP
struct task_struct *idle;
unsigned int loops_per_jiffy;
#endif
};
include/asm-arm/hardware/amba_clcd.h
+1 -1
View File
@@ -22,7 +22,7 @@
#define CLCD_UBAS 0x00000010
#define CLCD_LBAS 0x00000014
#ifndef CONFIG_ARCH_VERSATILE
#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
#define CLCD_IENB 0x00000018
#define CLCD_CNTL 0x0000001c
#else
include/asm-arm/irq.h
+1
View File
@@ -47,5 +47,6 @@ struct irqaction;
struct pt_regs;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
extern void migrate_irqs(void);
#endif
include/asm-arm/mmu_context.h
+2 -1
View File
@@ -86,7 +86,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
cpu_set(cpu, next->cpu_vm_mask);
check_context(next);
cpu_switch_mm(next->pgd, next);
cpu_clear(cpu, prev->cpu_vm_mask);
if (cache_is_vivt())
cpu_clear(cpu, prev->cpu_vm_mask);
}
}
include/asm-arm/pgtable.h
-3
View File
@@ -397,9 +397,6 @@ static inline pte_t *pmd_page_kernel(pmd_t pmd)
#define pgd_clear(pgdp) do { } while (0)
#define set_pgd(pgd,pgdp) do { } while (0)
#define page_pte_prot(page,prot) mk_pte(page, prot)
#define page_pte(page) mk_pte(page, __pgprot(0))
/* to find an entry in a page-table-directory */
#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
include/asm-arm/semaphore.h
-2
View File
@@ -24,8 +24,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \
}
#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INIT(name,count)
include/asm-arm/smp.h
+10
View File
@@ -66,4 +66,14 @@ struct secondary_data {
};
extern struct secondary_data secondary_data;
extern int __cpu_disable(void);
extern int mach_cpu_disable(unsigned int cpu);
extern void __cpu_die(unsigned int cpu);
extern void cpu_die(void);
extern void platform_cpu_die(unsigned int cpu);
extern int platform_cpu_kill(unsigned int cpu);
extern void platform_cpu_enable(unsigned int cpu);
#endif /* ifndef __ASM_ARM_SMP_H */
include/asm-arm/spinlock.h
+3 -3
View File
@@ -80,7 +80,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
*/
#define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0)
static inline void __raw_write_lock(rwlock_t *rw)
static inline void __raw_write_lock(raw_rwlock_t *rw)
{
unsigned long tmp;
@@ -97,7 +97,7 @@ static inline void __raw_write_lock(rwlock_t *rw)
smp_mb();
}
static inline int __raw_write_trylock(rwlock_t *rw)
static inline int __raw_write_trylock(raw_rwlock_t *rw)
{
unsigned long tmp;
@@ -157,7 +157,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
smp_mb();
}
static inline void __raw_read_unlock(rwlock_t *rw)
static inline void __raw_read_unlock(raw_rwlock_t *rw)
{
unsigned long tmp, tmp2;
include/asm-arm/unistd.h
-1
View File
@@ -544,7 +544,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
asmlinkage int sys_fork(struct pt_regs *regs);
asmlinkage int sys_vfork(struct pt_regs *regs);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-arm26/pgtable.h
-2
View File
@@ -98,8 +98,6 @@ extern struct page *empty_zero_page;
#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
#define page_pte_prot(page,prot) mk_pte(page, prot)
#define page_pte(page) mk_pte(page, __pgprot(0))
/*
* Terminology: PGD = Page Directory, PMD = Page Middle Directory,
include/asm-arm26/semaphore.h
-3
View File
@@ -25,9 +25,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait), \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INIT(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INIT(name,count)
include/asm-arm26/unistd.h
-1
View File
@@ -480,7 +480,6 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
asmlinkage int sys_fork(struct pt_regs *regs);
asmlinkage int sys_vfork(struct pt_regs *regs);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-cris/semaphore.h
-3
View File
@@ -33,9 +33,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-cris/unistd.h
-1
View File
@@ -367,7 +367,6 @@ asmlinkage int sys_fork(long r10, long r11, long r12, long r13,
asmlinkage int sys_vfork(long r10, long r11, long r12, long r13,
long mof, long srp, struct pt_regs *regs);
asmlinkage int sys_pipe(unsigned long __user *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-frv/pgtable.h
-2
View File
@@ -436,8 +436,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
return pte;
}
#define page_pte(page) page_pte_prot((page), __pgprot(0))
/* to find an entry in a page-table-directory. */
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
#define pgd_index_k(addr) pgd_index(addr)
include/asm-frv/semaphore.h
-3
View File
@@ -47,9 +47,6 @@ struct semaphore {
#define __SEMAPHORE_INITIALIZER(name,count) \
{ count, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) __SEM_DEBUG_INIT(name) }
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-h8300/semaphore.h
-3
View File
@@ -35,9 +35,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-h8300/unistd.h
-1
View File
@@ -528,7 +528,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
asmlinkage int sys_execve(char *name, char **argv, char **envp,
int dummy, ...);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-i386/desc.h
+5 -3
View File
@@ -17,6 +17,8 @@
extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
DECLARE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
#define get_cpu_gdt_table(_cpu) (per_cpu(cpu_gdt_table,_cpu))
DECLARE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
struct Xgt_desc_struct {
@@ -60,7 +62,7 @@ __asm__ __volatile__ ("movw %w3,0(%2)\n\t" \
static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *addr)
{
_set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[entry], (int)addr,
_set_tssldt_desc(&get_cpu_gdt_table(cpu)[entry], (int)addr,
offsetof(struct tss_struct, __cacheline_filler) - 1, 0x89);
}
@@ -68,7 +70,7 @@ static inline void __set_tss_desc(unsigned int cpu, unsigned int entry, void *ad
static inline void set_ldt_desc(unsigned int cpu, void *addr, unsigned int size)
{
_set_tssldt_desc(&per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
_set_tssldt_desc(&get_cpu_gdt_table(cpu)[GDT_ENTRY_LDT], (int)addr, ((size << 3)-1), 0x82);
}
#define LDT_entry_a(info) \
@@ -109,7 +111,7 @@ static inline void write_ldt_entry(void *ldt, int entry, __u32 entry_a, __u32 en
static inline void load_TLS(struct thread_struct *t, unsigned int cpu)
{
#define C(i) per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
#define C(i) get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]
C(0); C(1); C(2);
#undef C
}
include/asm-i386/mach-es7000/mach_mpparse.h
+1 -1
View File
@@ -16,7 +16,7 @@ static inline void mpc_oem_pci_bus(struct mpc_config_bus *m,
extern int parse_unisys_oem (char *oemptr);
extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
extern void setup_unisys();
extern void setup_unisys(void);
static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
char *productid)
include/asm-i386/pgtable-2level.h
-5
View File
@@ -26,11 +26,6 @@
#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
#define pmd_page_kernel(pmd) \
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
/*
* All present user pages are user-executable:
*/
include/asm-i386/pgtable-3level.h
-5
View File
@@ -74,11 +74,6 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
*/
static inline void pud_clear (pud_t * pud) { }
#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
#define pmd_page_kernel(pmd) \
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pud_page(pud) \
((struct page *) __va(pud_val(pud) & PAGE_MASK))
include/asm-i386/pgtable.h
+5 -2
View File
@@ -323,8 +323,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
return pte;
}
#define page_pte(page) page_pte_prot(page, __pgprot(0))
#define pmd_large(pmd) \
((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
@@ -369,6 +367,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
#define pte_offset_kernel(dir, address) \
((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
#define pmd_page_kernel(pmd) \
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
/*
* Helper function that returns the kernel pagetable entry controlling
* the virtual address 'address'. NULL means no pagetable entry present.
include/asm-i386/semaphore.h
-3
View File
@@ -55,9 +55,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-i386/system.h
+30 -3
View File
@@ -167,6 +167,8 @@ struct __xchg_dummy { unsigned long a[100]; };
#define __xg(x) ((struct __xchg_dummy *)(x))
#ifdef CONFIG_X86_CMPXCHG64
/*
* The semantics of XCHGCMP8B are a bit strange, this is why
* there is a loop and the loading of %%eax and %%edx has to
@@ -221,6 +223,8 @@ static inline void __set_64bit_var (unsigned long long *ptr,
__set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
__set_64bit(ptr, ll_low(value), ll_high(value)) )
#endif
/*
* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
* Note 2: xchg has side effect, so that attribute volatile is necessary,
@@ -259,7 +263,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
#ifdef CONFIG_X86_CMPXCHG
#define __HAVE_ARCH_CMPXCHG 1
#endif
static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
unsigned long new, int size)
@@ -275,13 +278,13 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
case 2:
__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
: "=a"(prev)
: "q"(new), "m"(*__xg(ptr)), "0"(old)
: "r"(new), "m"(*__xg(ptr)), "0"(old)
: "memory");
return prev;
case 4:
__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
: "=a"(prev)
: "q"(new), "m"(*__xg(ptr)), "0"(old)
: "r"(new), "m"(*__xg(ptr)), "0"(old)
: "memory");
return prev;
}
@@ -291,6 +294,30 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
#define cmpxchg(ptr,o,n)\
((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
(unsigned long)(n),sizeof(*(ptr))))
#endif
#ifdef CONFIG_X86_CMPXCHG64
static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
unsigned long long new)
{
unsigned long long prev;
__asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
: "=A"(prev)
: "b"((unsigned long)new),
"c"((unsigned long)(new >> 32)),
"m"(*__xg(ptr)),
"0"(old)
: "memory");
return prev;
}
#define cmpxchg64(ptr,o,n)\
((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
(unsigned long long)(n)))
#endif
#ifdef __KERNEL__
struct alt_instr {
include/asm-i386/unistd.h
-1
View File
@@ -448,7 +448,6 @@ asmlinkage int sys_clone(struct pt_regs regs);
asmlinkage int sys_fork(struct pt_regs regs);
asmlinkage int sys_vfork(struct pt_regs regs);
asmlinkage int sys_pipe(unsigned long __user *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
asmlinkage long sys_iopl(unsigned long unused);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
include/asm-ia64/pgtable.h
-3
View File
@@ -236,9 +236,6 @@ ia64_phys_addr_valid (unsigned long addr)
#define pte_modify(_pte, newprot) \
(__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
#define page_pte_prot(page,prot) mk_pte(page, prot)
#define page_pte(page) page_pte_prot(page, __pgprot(0))
#define pte_none(pte) (!pte_val(pte))
#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
include/asm-ia64/semaphore.h
-2
View File
@@ -24,8 +24,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name, count)
include/asm-ia64/unistd.h
-2
View File
@@ -383,8 +383,6 @@ struct sigaction;
long sys_execve(char __user *filename, char __user * __user *argv,
char __user * __user *envp, struct pt_regs *regs);
asmlinkage long sys_pipe(void);
asmlinkage long sys_ptrace(long request, pid_t pid,
unsigned long addr, unsigned long data);
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
struct sigaction __user *oact,
include/asm-m32r/pgtable.h
-2
View File
@@ -324,8 +324,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
return pte;
}
#define page_pte(page) page_pte_prot(page, __pgprot(0))
/*
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
include/asm-m32r/semaphore.h
-3
View File
@@ -32,9 +32,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-m32r/thread_info.h
+1 -1
View File
@@ -95,7 +95,7 @@ static inline struct thread_info *current_thread_info(void)
}
/* thread information allocation */
#if CONFIG_DEBUG_STACK_USAGE
#ifdef CONFIG_DEBUG_STACK_USAGE
#define alloc_thread_info(tsk) \
({ \
struct thread_info *ret; \
include/asm-m32r/unistd.h
-1
View File
@@ -452,7 +452,6 @@ asmlinkage int sys_clone(struct pt_regs regs);
asmlinkage int sys_fork(struct pt_regs regs);
asmlinkage int sys_vfork(struct pt_regs regs);
asmlinkage int sys_pipe(unsigned long __user *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-m68k/semaphore.h
-3
View File
@@ -36,9 +36,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-m68k/sun3xflop.h
-2
View File
@@ -27,10 +27,8 @@
/* We don't need no stinkin' I/O port allocation crap. */
#undef release_region
#undef check_region
#undef request_region
#define release_region(X, Y) do { } while(0)
#define check_region(X, Y) (0)
#define request_region(X, Y, Z) (1)
struct sun3xflop_private {
include/asm-m68k/unistd.h
-1
View File
@@ -444,7 +444,6 @@ asmlinkage long sys_mmap2(
unsigned long fd, unsigned long pgoff);
asmlinkage int sys_execve(char *name, char **argv, char **envp);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct pt_regs;
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
include/asm-m68knommu/anchor.h
+2 -2
View File
@@ -14,7 +14,7 @@
/*
* Define basic addressing info.
*/
#if defined(CONFIG_MOTOROLA) && defined(CONFIG_M5407)
#if defined(CONFIG_M5407C3)
#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */
#define COMEM_IRQ 25 /* IRQ of anchor part */
#else
@@ -96,7 +96,7 @@
* The PCI bus will be limited in what slots will actually be used.
* Define valid device numbers for different boards.
*/
#if defined(CONFIG_MOTOROLA) && defined(CONFIG_M5407)
#if defined(CONFIG_M5407C3)
#define COMEM_MINDEV 14 /* Minimum valid DEVICE */
#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */
#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */
include/asm-m68knommu/asm-offsets.h
-49
View File
@@ -1,49 +0,0 @@
#ifndef __ASM_OFFSETS_H__
#define __ASM_OFFSETS_H__
/*
* DO NOT MODIFY.
*
* This file was generated by arch/m68knommu/Makefile
*
*/
#define TASK_STATE 0 /* offsetof(struct task_struct, state) */
#define TASK_FLAGS 12 /* offsetof(struct task_struct, flags) */
#define TASK_PTRACE 16 /* offsetof(struct task_struct, ptrace) */
#define TASK_BLOCKED 922 /* offsetof(struct task_struct, blocked) */
#define TASK_THREAD 772 /* offsetof(struct task_struct, thread) */
#define TASK_THREAD_INFO 4 /* offsetof(struct task_struct, thread_info) */
#define TASK_MM 92 /* offsetof(struct task_struct, mm) */
#define TASK_ACTIVE_MM 96 /* offsetof(struct task_struct, active_mm) */
#define CPUSTAT_SOFTIRQ_PENDING 0 /* offsetof(irq_cpustat_t, __softirq_pending) */
#define THREAD_KSP 0 /* offsetof(struct thread_struct, ksp) */
#define THREAD_USP 4 /* offsetof(struct thread_struct, usp) */
#define THREAD_SR 8 /* offsetof(struct thread_struct, sr) */
#define THREAD_FS 10 /* offsetof(struct thread_struct, fs) */
#define THREAD_CRP 12 /* offsetof(struct thread_struct, crp) */
#define THREAD_ESP0 20 /* offsetof(struct thread_struct, esp0) */
#define THREAD_FPREG 24 /* offsetof(struct thread_struct, fp) */
#define THREAD_FPCNTL 120 /* offsetof(struct thread_struct, fpcntl) */
#define THREAD_FPSTATE 132 /* offsetof(struct thread_struct, fpstate) */
#define PT_D0 32 /* offsetof(struct pt_regs, d0) */
#define PT_ORIG_D0 36 /* offsetof(struct pt_regs, orig_d0) */
#define PT_D1 0 /* offsetof(struct pt_regs, d1) */
#define PT_D2 4 /* offsetof(struct pt_regs, d2) */
#define PT_D3 8 /* offsetof(struct pt_regs, d3) */
#define PT_D4 12 /* offsetof(struct pt_regs, d4) */
#define PT_D5 16 /* offsetof(struct pt_regs, d5) */
#define PT_A0 20 /* offsetof(struct pt_regs, a0) */
#define PT_A1 24 /* offsetof(struct pt_regs, a1) */
#define PT_A2 28 /* offsetof(struct pt_regs, a2) */
#define PT_PC 48 /* offsetof(struct pt_regs, pc) */
#define PT_SR 46 /* offsetof(struct pt_regs, sr) */
#define PT_VECTOR 52 /* offsetof(struct pt_regs, pc) + 4 */
#define STAT_IRQ 5140 /* offsetof(struct kernel_stat, irqs) */
#define SIGSEGV 11 /* SIGSEGV */
#define SEGV_MAPERR 196609 /* SEGV_MAPERR */
#define SIGTRAP 5 /* SIGTRAP */
#define TRAP_TRACE 196610 /* TRAP_TRACE */
#define PT_PTRACED 1 /* PT_PTRACED */
#define PT_DTRACE 2 /* PT_DTRACE */
#endif
include/asm-m68knommu/atomic.h
+2 -2
View File
@@ -100,7 +100,7 @@ static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v)
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
extern __inline__ int atomic_add_return(int i, atomic_t * v)
static inline int atomic_add_return(int i, atomic_t * v)
{
unsigned long temp, flags;
@@ -115,7 +115,7 @@ extern __inline__ int atomic_add_return(int i, atomic_t * v)
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
extern __inline__ int atomic_sub_return(int i, atomic_t * v)
static inline int atomic_sub_return(int i, atomic_t * v)
{
unsigned long temp, flags;
include/asm-m68knommu/coldfire.h
+8 -2
View File
@@ -20,9 +20,14 @@
*/
#define MCF_MBAR 0x10000000
#define MCF_MBAR2 0x80000000
#if defined(CONFIG_M520x)
#define MCF_IPSBAR 0xFC000000
#else
#define MCF_IPSBAR 0x40000000
#endif
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M520x)
#undef MCF_MBAR
#define MCF_MBAR MCF_IPSBAR
#endif
@@ -78,7 +83,8 @@
* One some ColdFire family members the bus clock (used by internal
* peripherals) is not the same as the CPU clock.
*/
#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x)
#if defined(CONFIG_M523x) || defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
defined(CONFIG_M520x)
#define MCF_BUSCLK (MCF_CLK / 2)
#else
#define MCF_BUSCLK MCF_CLK
include/asm-m68knommu/delay.h
+2 -2
View File
@@ -8,7 +8,7 @@
#include <asm/param.h>
extern __inline__ void __delay(unsigned long loops)
static inline void __delay(unsigned long loops)
{
#if defined(CONFIG_COLDFIRE)
/* The coldfire runs this loop at significantly different speeds
@@ -48,7 +48,7 @@ extern __inline__ void __delay(unsigned long loops)
extern unsigned long loops_per_jiffy;
extern __inline__ void _udelay(unsigned long usecs)
static inline void _udelay(unsigned long usecs)
{
#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \
defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \
include/asm-m68knommu/ide.h
-444
View File
@@ -1,444 +0,0 @@
/****************************************************************************/
/*
* linux/include/asm-m68knommu/ide.h
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
* Copyright (C) 2001 Lineo Inc., davidm@uclinux.org
*/
/****************************************************************************/
#ifndef _M68KNOMMU_IDE_H
#define _M68KNOMMU_IDE_H
#ifdef __KERNEL__
/****************************************************************************/
#include <linux/config.h>
#include <linux/interrupt.h>
#include <asm/setup.h>
#include <asm/io.h>
#include <asm/irq.h>
/****************************************************************************/
/*
* some coldfire specifics
*/
#ifdef CONFIG_COLDFIRE
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
/*
* Save some space, only have 1 interface
*/
#define MAX_HWIFS 1 /* we only have one interface for now */
#ifdef CONFIG_SECUREEDGEMP3
#define MCFSIM_LOCALCS MCFSIM_CSCR4
#else
#define MCFSIM_LOCALCS MCFSIM_CSCR6
#endif
#endif /* CONFIG_COLDFIRE */
/****************************************************************************/
/*
* Fix up things that may not have been provided
*/
#ifndef MAX_HWIFS
#define MAX_HWIFS 4 /* same as the other archs */
#endif
#undef SUPPORT_SLOW_DATA_PORTS
#define SUPPORT_SLOW_DATA_PORTS 0
#undef SUPPORT_VLB_SYNC
#define SUPPORT_VLB_SYNC 0
/* this definition is used only on startup .. */
#undef HD_DATA
#define HD_DATA NULL
#define DBGIDE(fmt,a...)
// #define DBGIDE(fmt,a...) printk(fmt, ##a)
#define IDE_INLINE __inline__
// #define IDE_INLINE
/****************************************************************************/
typedef union {
unsigned all : 8; /* all of the bits together */
struct {
unsigned bit7 : 1; /* always 1 */
unsigned lba : 1; /* using LBA instead of CHS */
unsigned bit5 : 1; /* always 1 */
unsigned unit : 1; /* drive select number, 0 or 1 */
unsigned head : 4; /* always zeros here */
} b;
} select_t;
/*
* our list of ports/irq's for different boards
*/
static struct m68k_ide_defaults {
ide_ioreg_t base;
int irq;
} m68k_ide_defaults[MAX_HWIFS] = {
#if defined(CONFIG_SECUREEDGEMP3)
{ ((ide_ioreg_t)0x30800000), 29 },
#elif defined(CONFIG_eLIA)
{ ((ide_ioreg_t)0x30c00000), 29 },
#else
{ ((ide_ioreg_t)0x0), 0 }
#endif
};
/****************************************************************************/
static IDE_INLINE int ide_default_irq(ide_ioreg_t base)
{
int i;
for (i = 0; i < MAX_HWIFS; i++)
if (m68k_ide_defaults[i].base == base)
return(m68k_ide_defaults[i].irq);
return 0;
}
static IDE_INLINE ide_ioreg_t ide_default_io_base(int index)
{
if (index >= 0 && index < MAX_HWIFS)
return(m68k_ide_defaults[index].base);
return 0;
}
/*
* Set up a hw structure for a specified data port, control port and IRQ.
* This should follow whatever the default interface uses.
*/
static IDE_INLINE void ide_init_hwif_ports(
hw_regs_t *hw,
ide_ioreg_t data_port,
ide_ioreg_t ctrl_port,
int *irq)
{
ide_ioreg_t reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port) {
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
} else {
hw->io_ports[IDE_CONTROL_OFFSET] = data_port + 0xe;
}
}
#define ide_init_default_irq(base) ide_default_irq(base)
static IDE_INLINE int
ide_request_irq(
unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long flags,
const char *device,
void *dev_id)
{
#ifdef CONFIG_COLDFIRE
mcf_autovector(irq);
#endif
return(request_irq(irq, handler, flags, device, dev_id));
}
static IDE_INLINE void
ide_free_irq(unsigned int irq, void *dev_id)
{
free_irq(irq, dev_id);
}
static IDE_INLINE int
ide_check_region(ide_ioreg_t from, unsigned int extent)
{
return 0;
}
static IDE_INLINE void
ide_request_region(ide_ioreg_t from, unsigned int extent, const char *name)
{
}
static IDE_INLINE void
ide_release_region(ide_ioreg_t from, unsigned int extent)
{
}
static IDE_INLINE void
ide_fix_driveid(struct hd_driveid *id)
{
#ifdef CONFIG_COLDFIRE
int i, n;
unsigned short *wp = (unsigned short *) id;
int avoid[] = {49, 51, 52, 59, -1 }; /* do not swap these words */
/* Need to byte swap shorts, but not char fields */
for (i = n = 0; i < sizeof(*id) / sizeof(*wp); i++, wp++) {
if (avoid[n] == i) {
n++;
continue;
}
*wp = ((*wp & 0xff) << 8) | ((*wp >> 8) & 0xff);
}
/* have to word swap the one 32 bit field */
id->lba_capacity = ((id->lba_capacity & 0xffff) << 16) |
((id->lba_capacity >> 16) & 0xffff);
#endif
}
static IDE_INLINE void
ide_release_lock (int *ide_lock)
{
}
static IDE_INLINE void
ide_get_lock(
int *ide_lock,
void (*handler)(int, void *, struct pt_regs *),
void *data)
{
}
#define ide_ack_intr(hwif) \
((hwif)->hw.ack_intr ? (hwif)->hw.ack_intr(hwif) : 1)
#define ide__sti() __sti()
/****************************************************************************/
/*
* System specific IO requirements
*/
#ifdef CONFIG_COLDFIRE
#ifdef CONFIG_SECUREEDGEMP3
/* Replace standard IO functions for funky mapping of MP3 board */
#undef outb
#undef outb_p
#undef inb
#undef inb_p
#define outb(v, a) ide_outb(v, (unsigned long) (a))
#define outb_p(v, a) ide_outb(v, (unsigned long) (a))
#define inb(a) ide_inb((unsigned long) (a))
#define inb_p(a) ide_inb((unsigned long) (a))
#define ADDR8_PTR(addr) (((addr) & 0x1) ? (0x8000 + (addr) - 1) : (addr))
#define ADDR16_PTR(addr) (addr)
#define ADDR32_PTR(addr) (addr)
#define SWAP8(w) ((((w) & 0xffff) << 8) | (((w) & 0xffff) >> 8))
#define SWAP16(w) (w)
#define SWAP32(w) (w)
static IDE_INLINE void
ide_outb(unsigned int val, unsigned int addr)
{
volatile unsigned short *rp;
DBGIDE("%s(val=%x,addr=%x)\n", __FUNCTION__, val, addr);
rp = (volatile unsigned short *) ADDR8_PTR(addr);
*rp = SWAP8(val);
}
static IDE_INLINE int
ide_inb(unsigned int addr)
{
volatile unsigned short *rp, val;
DBGIDE("%s(addr=%x)\n", __FUNCTION__, addr);
rp = (volatile unsigned short *) ADDR8_PTR(addr);
val = *rp;
return(SWAP8(val));
}
static IDE_INLINE void
ide_outw(unsigned int val, unsigned int addr)
{
volatile unsigned short *rp;
DBGIDE("%s(val=%x,addr=%x)\n", __FUNCTION__, val, addr);
rp = (volatile unsigned short *) ADDR16_PTR(addr);
*rp = SWAP16(val);
}
static IDE_INLINE void
ide_outsw(unsigned int addr, const void *vbuf, unsigned long len)
{
volatile unsigned short *rp, val;
unsigned short *buf;
DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
buf = (unsigned short *) vbuf;
rp = (volatile unsigned short *) ADDR16_PTR(addr);
for (; (len > 0); len--) {
val = *buf++;
*rp = SWAP16(val);
}
}
static IDE_INLINE int
ide_inw(unsigned int addr)
{
volatile unsigned short *rp, val;
DBGIDE("%s(addr=%x)\n", __FUNCTION__, addr);
rp = (volatile unsigned short *) ADDR16_PTR(addr);
val = *rp;
return(SWAP16(val));
}
static IDE_INLINE void
ide_insw(unsigned int addr, void *vbuf, unsigned long len)
{
volatile unsigned short *rp;
unsigned short w, *buf;
DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
buf = (unsigned short *) vbuf;
rp = (volatile unsigned short *) ADDR16_PTR(addr);
for (; (len > 0); len--) {
w = *rp;
*buf++ = SWAP16(w);
}
}
static IDE_INLINE void
ide_insl(unsigned int addr, void *vbuf, unsigned long len)
{
volatile unsigned long *rp;
unsigned long w, *buf;
DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
buf = (unsigned long *) vbuf;
rp = (volatile unsigned long *) ADDR32_PTR(addr);
for (; (len > 0); len--) {
w = *rp;
*buf++ = SWAP32(w);
}
}
static IDE_INLINE void
ide_outsl(unsigned int addr, const void *vbuf, unsigned long len)
{
volatile unsigned long *rp, val;
unsigned long *buf;
DBGIDE("%s(addr=%x,vbuf=%p,len=%x)\n", __FUNCTION__, addr, vbuf, len);
buf = (unsigned long *) vbuf;
rp = (volatile unsigned long *) ADDR32_PTR(addr);
for (; (len > 0); len--) {
val = *buf++;
*rp = SWAP32(val);
}
}
#elif CONFIG_eLIA
/* 8/16 bit acesses are controlled by flicking bits in the CS register */
#define ACCESS_MODE_16BIT() \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_LOCALCS)) = 0x0080
#define ACCESS_MODE_8BIT() \
*((volatile unsigned short *) (MCF_MBAR + MCFSIM_LOCALCS)) = 0x0040
static IDE_INLINE void
ide_outw(unsigned int val, unsigned int addr)
{
ACCESS_MODE_16BIT();
outw(val, addr);
ACCESS_MODE_8BIT();
}
static IDE_INLINE void
ide_outsw(unsigned int addr, const void *vbuf, unsigned long len)
{
ACCESS_MODE_16BIT();
outsw(addr, vbuf, len);
ACCESS_MODE_8BIT();
}
static IDE_INLINE int
ide_inw(unsigned int addr)
{
int ret;
ACCESS_MODE_16BIT();
ret = inw(addr);
ACCESS_MODE_8BIT();
return(ret);
}
static IDE_INLINE void
ide_insw(unsigned int addr, void *vbuf, unsigned long len)
{
ACCESS_MODE_16BIT();
insw(addr, vbuf, len);
ACCESS_MODE_8BIT();
}
static IDE_INLINE void
ide_insl(unsigned int addr, void *vbuf, unsigned long len)
{
ACCESS_MODE_16BIT();
insl(addr, vbuf, len);
ACCESS_MODE_8BIT();
}
static IDE_INLINE void
ide_outsl(unsigned int addr, const void *vbuf, unsigned long len)
{
ACCESS_MODE_16BIT();
outsl(addr, vbuf, len);
ACCESS_MODE_8BIT();
}
#endif /* CONFIG_SECUREEDGEMP3 */
#undef outw
#undef outw_p
#undef outsw
#undef inw
#undef inw_p
#undef insw
#undef insl
#undef outsl
#define outw(v, a) ide_outw(v, (unsigned long) (a))
#define outw_p(v, a) ide_outw(v, (unsigned long) (a))
#define outsw(a, b, n) ide_outsw((unsigned long) (a), b, n)
#define inw(a) ide_inw((unsigned long) (a))
#define inw_p(a) ide_inw((unsigned long) (a))
#define insw(a, b, n) ide_insw((unsigned long) (a), b, n)
#define insl(a, b, n) ide_insl((unsigned long) (a), b, n)
#define outsl(a, b, n) ide_outsl((unsigned long) (a), b, n)
#endif CONFIG_COLDFIRE
/****************************************************************************/
#endif /* __KERNEL__ */
#endif /* _M68KNOMMU_IDE_H */
/****************************************************************************/
include/asm-m68knommu/io.h
+4 -4
View File
@@ -147,19 +147,19 @@ static inline void io_insl(unsigned int addr, void *buf, int len)
extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
extern inline void *ioremap(unsigned long physaddr, unsigned long size)
static inline void *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
include/asm-m68knommu/m520xsim.h
+54
View File
@@ -0,0 +1,54 @@
/****************************************************************************/
/*
* m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
*
* (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
*/
/****************************************************************************/
#ifndef m520xsim_h
#define m520xsim_h
/****************************************************************************/
#include <linux/config.h>
/*
* Define the 5282 SIM register set addresses.
*/
#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFINT_VECBASE 64
#define MCFINT_UART0 26 /* Interrupt number for UART0 */
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
#define MCF_GPIO_PAR_UART (0xA4036)
#define MCF_GPIO_PAR_FECI2C (0xA4033)
#define MCF_GPIO_PAR_FEC (0xA4038)
#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
#define ICR_INTRCONF 0x05
#define MCFPIT_IMR MCFINTC_IMRL
#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
/****************************************************************************/
#endif /* m520xsim_h */
include/asm-m68knommu/mcfcache.h
+14
View File
@@ -117,6 +117,20 @@
.endm
#endif /* CONFIG_M5407 */
#if defined(CONFIG_M520x)
.macro CACHE_ENABLE
move.l #0x01000000,%d0 /* invalidate whole cache */
movec %d0,%CACR
nop
move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
movec %d0,%ACR0
move.l #0x00000000,%d0 /* no other regions cached */
movec %d0,%ACR1
move.l #0x80400000,%d0 /* enable 8K instruction cache */
movec %d0,%CACR
nop
.endm
#endif /* CONFIG_M520x */
/****************************************************************************/
#endif /* __M68KNOMMU_MCFCACHE_H */
include/asm-m68knommu/mcfne.h
+9 -9
View File
@@ -35,7 +35,7 @@
* Define the basic hardware resources of NE2000 boards.
*/
#if defined(CONFIG_M5206) && defined(CONFIG_ARNEWSH)
#if defined(CONFIG_ARN5206)
#define NE2000_ADDR 0x40000300
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0xf0
@@ -44,7 +44,7 @@
#define NE2000_BYTE volatile unsigned short
#endif
#if defined(CONFIG_M5206e) && defined(CONFIG_MOTOROLA)
#if defined(CONFIG_M5206eC3)
#define NE2000_ADDR 0x40000300
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1c
@@ -61,7 +61,7 @@
#define NE2000_BYTE volatile unsigned char
#endif
#if defined(CONFIG_M5206e) && defined(CONFIG_CFV240)
#if defined(CONFIG_CFV240)
#define NE2000_ADDR 0x40010000
#define NE2000_ADDR1 0x40010001
#define NE2000_ODDOFFSET 0x00000000
@@ -72,7 +72,7 @@
#define NE2000_BYTE volatile unsigned char
#endif
#if defined(CONFIG_M5307) && defined(CONFIG_MOTOROLA)
#if defined(CONFIG_M5307C3)
#define NE2000_ADDR 0x40000300
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1b
@@ -114,7 +114,7 @@
#define RSWAP(w) (((w) << 8) | ((w) >> 8))
#endif
#if defined(CONFIG_M5307) && defined(CONFIG_ARNEWSH)
#if defined(CONFIG_ARN5307)
#define NE2000_ADDR 0xfe600300
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1b
@@ -123,7 +123,7 @@
#define NE2000_BYTE volatile unsigned short
#endif
#if defined(CONFIG_M5407)
#if defined(CONFIG_M5407C3)
#define NE2000_ADDR 0x40000300
#define NE2000_ODDOFFSET 0x00010000
#define NE2000_IRQ_VECTOR 0x1b
@@ -264,7 +264,7 @@ void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
* Minor differences between the different board types.
*/
#if defined(CONFIG_M5206) && defined(CONFIG_ARNEWSH)
#if defined(CONFIG_ARN5206)
void ne2000_irqsetup(int irq)
{
volatile unsigned char *icrp;
@@ -275,7 +275,7 @@ void ne2000_irqsetup(int irq)
}
#endif
#if defined(CONFIG_M5206e) && defined(CONFIG_MOTOROLA)
#if defined(CONFIG_M5206eC3)
void ne2000_irqsetup(int irq)
{
volatile unsigned char *icrp;
@@ -286,7 +286,7 @@ void ne2000_irqsetup(int irq)
}
#endif
#if defined(CONFIG_M5206e) && defined(CONFIG_CFV240)
#if defined(CONFIG_CFV240)
void ne2000_irqsetup(int irq)
{
volatile unsigned char *icrp;
include/asm-m68knommu/mcfpit.h
+6 -2
View File
@@ -14,13 +14,17 @@
#include <linux/config.h>
/*
* Get address specific defines for the 5270/5271 and 5280/5282.
* Get address specific defines for the 5270/5271, 5280/5282, and 5208.
*/
#if defined(CONFIG_M520x)
#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */
#else
#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */
#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */
#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */
#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */
#endif
/*
* Define the PIT timer register set addresses.
include/asm-m68knommu/mcfsim.h
+15
View File
@@ -22,6 +22,8 @@
#include <asm/m5204sim.h>
#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e)
#include <asm/m5206sim.h>
#elif defined(CONFIG_M520x)
#include <asm/m520xsim.h>
#elif defined(CONFIG_M523x)
#include <asm/m523xsim.h>
#elif defined(CONFIG_M5249)
@@ -99,6 +101,19 @@
#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
#endif
/*
* PIT interrupt settings, if not found in mXXXXsim.h file.
*/
#ifndef ICR_INTRCONF
#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
#endif
#ifndef MCFPIT_IMR
#define MCFPIT_IMR MCFINTC_IMRH
#endif
#ifndef MCFPIT_IMR_IBIT
#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
#endif
#ifndef __ASSEMBLY__
/*
include/asm-m68knommu/mcfuart.h
+4
View File
@@ -41,6 +41,10 @@
#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
#define MCFUART_BASE2 0x200 /* Base address of UART2 */
#endif
#elif defined(CONFIG_M520x)
#define MCFUART_BASE1 0x60000 /* Base address of UART1 */
#define MCFUART_BASE2 0x64000 /* Base address of UART2 */
#define MCFUART_BASE3 0x68000 /* Base address of UART2 */
#endif
include/asm-m68knommu/mcfwdebug.h
+1 -1
View File
@@ -90,7 +90,7 @@
* that the debug module instructions (2 longs) must be long word aligned and
* some pointer fiddling is performed to ensure this.
*/
extern inline void wdebug(int reg, unsigned long data) {
static inline void wdebug(int reg, unsigned long data) {
unsigned short dbg_spc[6];
unsigned short *dbg;
include/asm-m68knommu/mmu_context.h
+2 -2
View File
@@ -10,7 +10,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
extern inline int
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
// mm->context = virt_to_phys(mm->pgd);
@@ -25,7 +25,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, str
#define deactivate_mm(tsk,mm) do { } while (0)
extern inline void activate_mm(struct mm_struct *prev_mm,
static inline void activate_mm(struct mm_struct *prev_mm,
struct mm_struct *next_mm)
{
}
include/asm-m68knommu/processor.h
+2 -2
View File
@@ -21,7 +21,7 @@
#include <asm/ptrace.h>
#include <asm/current.h>
extern inline unsigned long rdusp(void)
static inline unsigned long rdusp(void)
{
#ifdef CONFIG_COLDFIRE
extern unsigned int sw_usp;
@@ -33,7 +33,7 @@ extern inline unsigned long rdusp(void)
#endif
}
extern inline void wrusp(unsigned long usp)
static inline void wrusp(unsigned long usp)
{
#ifdef CONFIG_COLDFIRE
extern unsigned int sw_usp;
include/asm-m68knommu/semaphore.h
+5 -8
View File
@@ -35,16 +35,13 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
extern inline void sema_init (struct semaphore *sem, int val)
static inline void sema_init (struct semaphore *sem, int val)
{
*sem = (struct semaphore)__SEMAPHORE_INITIALIZER(*sem, val);
}
@@ -76,7 +73,7 @@ extern spinlock_t semaphore_wake_lock;
* "down_failed" is a special asm handler that calls the C
* routine that actually waits. See arch/m68k/lib/semaphore.S
*/
extern inline void down(struct semaphore * sem)
static inline void down(struct semaphore * sem)
{
might_sleep();
__asm__ __volatile__(
@@ -91,7 +88,7 @@ extern inline void down(struct semaphore * sem)
: "cc", "%a0", "%a1", "memory");
}
extern inline int down_interruptible(struct semaphore * sem)
static inline int down_interruptible(struct semaphore * sem)
{
int ret;
@@ -110,7 +107,7 @@ extern inline int down_interruptible(struct semaphore * sem)
return(ret);
}
extern inline int down_trylock(struct semaphore * sem)
static inline int down_trylock(struct semaphore * sem)
{
register struct semaphore *sem1 __asm__ ("%a1") = sem;
register int result __asm__ ("%d0");
@@ -138,7 +135,7 @@ extern inline int down_trylock(struct semaphore * sem)
* The default case (no contention) will result in NO
* jumps for both down() and up().
*/
extern inline void up(struct semaphore * sem)
static inline void up(struct semaphore * sem)
{
__asm__ __volatile__(
"| atomic up operation\n\t"
include/asm-m68knommu/system.h
+13
View File
@@ -312,6 +312,19 @@ cmpxchg(volatile int *p, int old, int new)
moveb #0x80, (%a0); \
"); \
})
#elif defined(CONFIG_M520x)
/*
* The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register
* RCR), that when set, resets the MCF5208.
*/
#define HARD_RESET_NOW() \
({ \
unsigned char volatile *reset; \
asm("move.w #0x2700, %sr"); \
reset = ((volatile unsigned short *)(MCF_IPSBAR + 0xA0000)); \
while(1) \
*reset |= 0x80; \
})
#else
#define HARD_RESET_NOW() ({ \
asm(" \
include/asm-m68knommu/tlbflush.h
+2 -2
View File
@@ -47,12 +47,12 @@ static inline void flush_tlb_range(struct mm_struct *mm,
BUG();
}
extern inline void flush_tlb_kernel_page(unsigned long addr)
static inline void flush_tlb_kernel_page(unsigned long addr)
{
BUG();
}
extern inline void flush_tlb_pgtables(struct mm_struct *mm,
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
BUG();
include/asm-m68knommu/unistd.h
-1
View File
@@ -504,7 +504,6 @@ asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
unsigned long fd, unsigned long pgoff);
asmlinkage int sys_execve(char *name, char **argv, char **envp);
asmlinkage int sys_pipe(unsigned long *fildes);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct pt_regs;
int sys_request_irq(unsigned int,
irqreturn_t (*)(int, void *, struct pt_regs *),
include/asm-mips/pgtable-64.h
-1
View File
@@ -169,7 +169,6 @@ static inline void pud_clear(pud_t *pudp)
#define __pgd_offset(address) pgd_index(address)
#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pmd_offset(address) pmd_index(address)
#define page_pte(page) page_pte_prot(page, __pgprot(0))
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, 0)
include/asm-mips/pgtable.h
-1
View File
@@ -75,7 +75,6 @@ extern void paging_init(void);
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
#define page_pte(page) page_pte_prot(page, __pgprot(0))
#define pmd_phys(pmd) (pmd_val(pmd) - PAGE_OFFSET)
#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
#define pmd_page_kernel(pmd) pmd_val(pmd)
include/asm-mips/semaphore.h
-3
View File
@@ -45,9 +45,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name, 1)
#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-mips/unistd.h
-1
View File
@@ -1177,7 +1177,6 @@ asmlinkage long sys_mmap2(
unsigned long fd, unsigned long pgoff);
asmlinkage int sys_execve(nabi_no_regargs struct pt_regs regs);
asmlinkage int sys_pipe(nabi_no_regargs struct pt_regs regs);
asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-parisc/ide.h
-1
View File
@@ -22,7 +22,6 @@
#define ide_request_irq(irq,hand,flg,dev,id) request_irq((irq),(hand),(flg),(dev),(id))
#define ide_free_irq(irq,dev_id) free_irq((irq), (dev_id))
#define ide_check_region(from,extent) check_region((from), (extent))
#define ide_request_region(from,extent,name) request_region((from), (extent), (name))
#define ide_release_region(from,extent) release_region((from), (extent))
/* Generic I/O and MEMIO string operations. */
include/asm-parisc/semaphore.h
-3
View File
@@ -49,9 +49,6 @@ struct semaphore {
.wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
}
#define __MUTEX_INITIALIZER(name) \
__SEMAPHORE_INITIALIZER(name,1)
#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
include/asm-parisc/unistd.h
-1
View File
@@ -1011,7 +1011,6 @@ int sys_clone(unsigned long clone_flags, unsigned long usp,
struct pt_regs *regs);
int sys_vfork(struct pt_regs *regs);
int sys_pipe(int *fildes);
long sys_ptrace(long request, pid_t pid, long addr, long data);
struct sigaction;
asmlinkage long sys_rt_sigaction(int sig,
const struct sigaction __user *act,
include/asm-ppc64/a.out.h → include/asm-powerpc/a.out.h
+9 -12
View File
@@ -1,14 +1,5 @@
#ifndef __PPC64_A_OUT_H__
#define __PPC64_A_OUT_H__
/*
* c 2001 PPC 64 Team, IBM Corp
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_POWERPC_A_OUT_H
#define _ASM_POWERPC_A_OUT_H
struct exec
{
@@ -27,6 +18,7 @@ struct exec
#define N_SYMSIZE(a) ((a).a_syms)
#ifdef __KERNEL__
#ifdef __powerpc64__
#define STACK_TOP_USER64 TASK_SIZE_USER64
#define STACK_TOP_USER32 TASK_SIZE_USER32
@@ -34,6 +26,11 @@ struct exec
#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
STACK_TOP_USER32 : STACK_TOP_USER64)
#else /* __powerpc64__ */
#define STACK_TOP TASK_SIZE
#endif /* __powerpc64__ */
#endif /* __KERNEL__ */
#endif /* __PPC64_A_OUT_H__ */
#endif /* _ASM_POWERPC_A_OUT_H */
include/asm-ppc/atomic.h → include/asm-powerpc/atomic.h
+20 -25
View File
@@ -1,29 +1,20 @@
#ifndef _ASM_POWERPC_ATOMIC_H_
#define _ASM_POWERPC_ATOMIC_H_
/*
* PowerPC atomic operations
*/
#ifndef _ASM_PPC_ATOMIC_H_
#define _ASM_PPC_ATOMIC_H_
typedef struct { volatile int counter; } atomic_t;
#ifdef __KERNEL__
#include <asm/synch.h>
#define ATOMIC_INIT(i) { (i) }
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) (((v)->counter) = (i))
extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
#ifdef CONFIG_SMP
#define SMP_SYNC "sync"
#define SMP_ISYNC "\n\tisync"
#else
#define SMP_SYNC ""
#define SMP_ISYNC
#endif
/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
* The old ATOMIC_SYNC_FIX covered some but not all of this.
*/
@@ -53,12 +44,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
int t;
__asm__ __volatile__(
EIEIO_ON_SMP
"1: lwarx %0,0,%2 # atomic_add_return\n\
add %0,%1,%0\n"
PPC405_ERR77(0,%2)
" stwcx. %0,0,%2 \n\
bne- 1b"
SMP_ISYNC
ISYNC_ON_SMP
: "=&r" (t)
: "r" (a), "r" (&v->counter)
: "cc", "memory");
@@ -88,12 +80,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
int t;
__asm__ __volatile__(
EIEIO_ON_SMP
"1: lwarx %0,0,%2 # atomic_sub_return\n\
subf %0,%1,%0\n"
PPC405_ERR77(0,%2)
" stwcx. %0,0,%2 \n\
bne- 1b"
SMP_ISYNC
ISYNC_ON_SMP
: "=&r" (t)
: "r" (a), "r" (&v->counter)
: "cc", "memory");
@@ -121,12 +114,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
int t;
__asm__ __volatile__(
EIEIO_ON_SMP
"1: lwarx %0,0,%1 # atomic_inc_return\n\
addic %0,%0,1\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1 \n\
bne- 1b"
SMP_ISYNC
ISYNC_ON_SMP
: "=&r" (t)
: "r" (&v->counter)
: "cc", "memory");
@@ -164,12 +158,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
int t;
__asm__ __volatile__(
EIEIO_ON_SMP
"1: lwarx %0,0,%1 # atomic_dec_return\n\
addic %0,%0,-1\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1\n\
bne- 1b"
SMP_ISYNC
ISYNC_ON_SMP
: "=&r" (t)
: "r" (&v->counter)
: "cc", "memory");
@@ -189,13 +184,14 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
int t;
__asm__ __volatile__(
EIEIO_ON_SMP
"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
addic. %0,%0,-1\n\
blt- 2f\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1\n\
bne- 1b"
SMP_ISYNC
ISYNC_ON_SMP
"\n\
2:" : "=&r" (t)
: "r" (&v->counter)
@@ -204,11 +200,10 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
return t;
}
#define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory")
#define smp_mb__before_atomic_dec() __MB
#define smp_mb__after_atomic_dec() __MB
#define smp_mb__before_atomic_inc() __MB
#define smp_mb__after_atomic_inc() __MB
#define smp_mb__before_atomic_dec() smp_mb()
#define smp_mb__after_atomic_dec() smp_mb()
#define smp_mb__before_atomic_inc() smp_mb()
#define smp_mb__after_atomic_inc() smp_mb()
#endif /* __KERNEL__ */
#endif /* _ASM_PPC_ATOMIC_H_ */
#endif /* _ASM_POWERPC_ATOMIC_H_ */
include/asm-ppc64/auxvec.h → include/asm-powerpc/auxvec.h
+5 -3
View File
@@ -1,5 +1,5 @@
#ifndef __PPC64_AUXVEC_H
#define __PPC64_AUXVEC_H
#ifndef _ASM_POWERPC_AUXVEC_H
#define _ASM_POWERPC_AUXVEC_H
/*
* We need to put in some extra aux table entries to tell glibc what
@@ -14,6 +14,8 @@
/* The vDSO location. We have to use the same value as x86 for glibc's
* sake :-)
*/
#ifdef __powerpc64__
#define AT_SYSINFO_EHDR 33
#endif
#endif /* __PPC64_AUXVEC_H */
#endif
include/asm-ppc/backlight.h → include/asm-powerpc/backlight.h
+5 -4
View File
@@ -1,12 +1,13 @@
/*
* Routines for handling backlight control on PowerBooks
*
* For now, implementation resides in arch/ppc/kernel/pmac_support.c
* For now, implementation resides in
* arch/powerpc/platforms/powermac/pmac_support.c
*
*/
#ifndef __ASM_POWERPC_BACKLIGHT_H
#define __ASM_POWERPC_BACKLIGHT_H
#ifdef __KERNEL__
#ifndef __ASM_PPC_BACKLIGHT_H
#define __ASM_PPC_BACKLIGHT_H
/* Abstract values */
#define BACKLIGHT_OFF 0
@@ -26,5 +27,5 @@ extern int get_backlight_enable(void);
extern int set_backlight_level(int level);
extern int get_backlight_level(void);
#endif
#endif /* __KERNEL__ */
#endif
include/asm-powerpc/bitops.h
+437
View File
@@ -0,0 +1,437 @@
/*
* PowerPC atomic bit operations.
*
* Merged version by David Gibson <david@gibson.dropbear.id.au>.
* Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
* Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
* originally took it from the ppc32 code.
*
* Within a word, bits are numbered LSB first. Lot's of places make
* this assumption by directly testing bits with (val & (1<<nr)).
* This can cause confusion for large (> 1 word) bitmaps on a
* big-endian system because, unlike little endian, the number of each
* bit depends on the word size.
*
* The bitop functions are defined to work on unsigned longs, so for a
* ppc64 system the bits end up numbered:
* |63..............0|127............64|191...........128|255...........196|
* and on ppc32:
* |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
*
* There are a few little-endian macros used mostly for filesystem
* bitmaps, these work on similar bit arrays layouts, but
* byte-oriented:
* |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
*
* The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
* number field needs to be reversed compared to the big-endian bit
* fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_POWERPC_BITOPS_H
#define _ASM_POWERPC_BITOPS_H
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <asm/atomic.h>
#include <asm/synch.h>
/*
* clear_bit doesn't imply a memory barrier
*/
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
#define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
#ifdef CONFIG_PPC64
#define LARXL "ldarx"
#define STCXL "stdcx."
#define CNTLZL "cntlzd"
#else
#define LARXL "lwarx"
#define STCXL "stwcx."
#define CNTLZL "cntlzw"
#endif
static __inline__ void set_bit(int nr, volatile unsigned long *addr)
{
unsigned long old;
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
__asm__ __volatile__(
"1:" LARXL " %0,0,%3 # set_bit\n"
"or %0,%0,%2\n"
PPC405_ERR77(0,%3)
STCXL " %0,0,%3\n"
"bne- 1b"
: "=&r"(old), "=m"(*p)
: "r"(mask), "r"(p), "m"(*p)
: "cc" );
}
static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long old;
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
__asm__ __volatile__(
"1:" LARXL " %0,0,%3 # set_bit\n"
"andc %0,%0,%2\n"
PPC405_ERR77(0,%3)
STCXL " %0,0,%3\n"
"bne- 1b"
: "=&r"(old), "=m"(*p)
: "r"(mask), "r"(p), "m"(*p)
: "cc" );
}
static __inline__ void change_bit(int nr, volatile unsigned long *addr)
{
unsigned long old;
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
__asm__ __volatile__(
"1:" LARXL " %0,0,%3 # set_bit\n"
"xor %0,%0,%2\n"
PPC405_ERR77(0,%3)
STCXL " %0,0,%3\n"
"bne- 1b"
: "=&r"(old), "=m"(*p)
: "r"(mask), "r"(p), "m"(*p)
: "cc" );
}
static __inline__ int test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long old, t;
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
__asm__ __volatile__(
EIEIO_ON_SMP
"1:" LARXL " %0,0,%3 # test_and_set_bit\n"
"or %1,%0,%2 \n"
PPC405_ERR77(0,%3)
STCXL " %1,0,%3 \n"
"bne- 1b"
ISYNC_ON_SMP
: "=&r" (old), "=&r" (t)
: "r" (mask), "r" (p)
: "cc", "memory");
return (old & mask) != 0;
}
static __inline__ int test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long old, t;
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
__asm__ __volatile__(
EIEIO_ON_SMP
"1:" LARXL " %0,0,%3 # test_and_clear_bit\n"
"andc %1,%0,%2 \n"
PPC405_ERR77(0,%3)
STCXL " %1,0,%3 \n"
"bne- 1b"
ISYNC_ON_SMP
: "=&r" (old), "=&r" (t)
: "r" (mask), "r" (p)
: "cc", "memory");
return (old & mask) != 0;
}
static __inline__ int test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long old, t;
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
__asm__ __volatile__(
EIEIO_ON_SMP
"1:" LARXL " %0,0,%3 # test_and_change_bit\n"
"xor %1,%0,%2 \n"
PPC405_ERR77(0,%3)
STCXL " %1,0,%3 \n"
"bne- 1b"
ISYNC_ON_SMP
: "=&r" (old), "=&r" (t)
: "r" (mask), "r" (p)
: "cc", "memory");
return (old & mask) != 0;
}
static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
{
unsigned long old;
__asm__ __volatile__(
"1:" LARXL " %0,0,%3 # set_bit\n"
"or %0,%0,%2\n"
STCXL " %0,0,%3\n"
"bne- 1b"
: "=&r" (old), "=m" (*addr)
: "r" (mask), "r" (addr), "m" (*addr)
: "cc");
}
/* Non-atomic versions */
static __inline__ int test_bit(unsigned long nr,
__const__ volatile unsigned long *addr)
{
return 1UL & (addr[BITOP_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
}
static __inline__ void __set_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
*p |= mask;
}
static __inline__ void __clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
*p &= ~mask;
}
static __inline__ void __change_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
*p ^= mask;
}
static __inline__ int __test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
unsigned long old = *p;
*p = old | mask;
return (old & mask) != 0;
}
static __inline__ int __test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
unsigned long old = *p;
*p = old & ~mask;
return (old & mask) != 0;
}
static __inline__ int __test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
unsigned long mask = BITOP_MASK(nr);
unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
unsigned long old = *p;
*p = old ^ mask;
return (old & mask) != 0;
}
/*
* Return the zero-based bit position (LE, not IBM bit numbering) of
* the most significant 1-bit in a double word.
*/
static __inline__ int __ilog2(unsigned long x)
{
int lz;
asm (CNTLZL " %0,%1" : "=r" (lz) : "r" (x));
return BITS_PER_LONG - 1 - lz;
}
/*
* Determines the bit position of the least significant 0 bit in the
* specified double word. The returned bit position will be
* zero-based, starting from the right side (63/31 - 0).
*/
static __inline__ unsigned long ffz(unsigned long x)
{
/* no zero exists anywhere in the 8 byte area. */
if ((x = ~x) == 0)
return BITS_PER_LONG;
/*
* Calculate the bit position of the least signficant '1' bit in x
* (since x has been changed this will actually be the least signficant
* '0' bit in * the original x). Note: (x & -x) gives us a mask that
* is the least significant * (RIGHT-most) 1-bit of the value in x.
*/
return __ilog2(x & -x);
}
static __inline__ int __ffs(unsigned long x)
{
return __ilog2(x & -x);
}
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static __inline__ int ffs(int x)
{
unsigned long i = (unsigned long)x;
return __ilog2(i & -i) + 1;
}
/*
* fls: find last (most-significant) bit set.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static __inline__ int fls(unsigned int x)
{
int lz;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
return 32 - lz;
}
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight64(x) generic_hweight64(x)
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
unsigned long find_next_zero_bit(const unsigned long *addr,
unsigned long size, unsigned long offset);
/**
* find_first_bit - find the first set bit in a memory region
* @addr: The address to start the search at
* @size: The maximum size to search
*
* Returns the bit-number of the first set bit, not the number of the byte
* containing a bit.
*/
#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
unsigned long find_next_bit(const unsigned long *addr,
unsigned long size, unsigned long offset);
/* Little-endian versions */
static __inline__ int test_le_bit(unsigned long nr,
__const__ unsigned long *addr)
{
__const__ unsigned char *tmp = (__const__ unsigned char *) addr;
return (tmp[nr >> 3] >> (nr & 7)) & 1;
}
#define __set_le_bit(nr, addr) \
__set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
#define __clear_le_bit(nr, addr) \
__clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
#define test_and_set_le_bit(nr, addr) \
test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
#define test_and_clear_le_bit(nr, addr) \
test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
#define __test_and_set_le_bit(nr, addr) \
__test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
#define __test_and_clear_le_bit(nr, addr) \
__test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
#define find_first_zero_le_bit(addr, size) find_next_zero_le_bit((addr), (size), 0)
unsigned long find_next_zero_le_bit(const unsigned long *addr,
unsigned long size, unsigned long offset);
/* Bitmap functions for the ext2 filesystem */
#define ext2_set_bit(nr,addr) \
__test_and_set_le_bit((nr), (unsigned long*)addr)
#define ext2_clear_bit(nr, addr) \
__test_and_clear_le_bit((nr), (unsigned long*)addr)
#define ext2_set_bit_atomic(lock, nr, addr) \
test_and_set_le_bit((nr), (unsigned long*)addr)
#define ext2_clear_bit_atomic(lock, nr, addr) \
test_and_clear_le_bit((nr), (unsigned long*)addr)
#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
#define ext2_find_first_zero_bit(addr, size) \
find_first_zero_le_bit((unsigned long*)addr, size)
#define ext2_find_next_zero_bit(addr, size, off) \
find_next_zero_le_bit((unsigned long*)addr, size, off)
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) \
__test_and_set_le_bit(nr, (unsigned long *)addr)
#define minix_set_bit(nr,addr) \
__set_le_bit(nr, (unsigned long *)addr)
#define minix_test_and_clear_bit(nr,addr) \
__test_and_clear_le_bit(nr, (unsigned long *)addr)
#define minix_test_bit(nr,addr) \
test_le_bit(nr, (unsigned long *)addr)
#define minix_find_first_zero_bit(addr,size) \
find_first_zero_le_bit((unsigned long *)addr, size)
/*
* Every architecture must define this function. It's the fastest
* way of searching a 140-bit bitmap where the first 100 bits are
* unlikely to be set. It's guaranteed that at least one of the 140
* bits is cleared.
*/
static inline int sched_find_first_bit(const unsigned long *b)
{
#ifdef CONFIG_PPC64
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 64;
return __ffs(b[2]) + 128;
#else
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 32;
if (unlikely(b[2]))
return __ffs(b[2]) + 64;
if (b[3])
return __ffs(b[3]) + 96;
return __ffs(b[4]) + 128;
#endif
}
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_BITOPS_H */
include/asm-ppc64/bug.h → include/asm-powerpc/bug.h
+23 -15
View File
@@ -1,5 +1,5 @@
#ifndef _PPC64_BUG_H
#define _PPC64_BUG_H
#ifndef _ASM_POWERPC_BUG_H
#define _ASM_POWERPC_BUG_H
/*
* Define an illegal instr to trap on the bug.
@@ -11,6 +11,14 @@
#ifndef __ASSEMBLY__
#ifdef __powerpc64__
#define BUG_TABLE_ENTRY ".llong"
#define BUG_TRAP_OP "tdnei"
#else
#define BUG_TABLE_ENTRY ".long"
#define BUG_TRAP_OP "twnei"
#endif /* __powerpc64__ */
struct bug_entry {
unsigned long bug_addr;
long line;
@@ -31,29 +39,29 @@ struct bug_entry *find_bug(unsigned long bugaddr);
#define BUG() do { \
__asm__ __volatile__( \
"1: twi 31,0,0\n" \
".section __bug_table,\"a\"\n\t" \
" .llong 1b,%0,%1,%2\n" \
".section __bug_table,\"a\"\n" \
"\t"BUG_TABLE_ENTRY" 1b,%0,%1,%2\n" \
".previous" \
: : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
} while (0)
#define BUG_ON(x) do { \
__asm__ __volatile__( \
"1: tdnei %0,0\n" \
".section __bug_table,\"a\"\n\t" \
" .llong 1b,%1,%2,%3\n" \
"1: "BUG_TRAP_OP" %0,0\n" \
".section __bug_table,\"a\"\n" \
"\t"BUG_TABLE_ENTRY" 1b,%1,%2,%3\n" \
".previous" \
: : "r" ((long long)(x)), "i" (__LINE__), \
: : "r" ((long)(x)), "i" (__LINE__), \
"i" (__FILE__), "i" (__FUNCTION__)); \
} while (0)
#define WARN_ON(x) do { \
__asm__ __volatile__( \
"1: tdnei %0,0\n" \
".section __bug_table,\"a\"\n\t" \
" .llong 1b,%1,%2,%3\n" \
"1: "BUG_TRAP_OP" %0,0\n" \
".section __bug_table,\"a\"\n" \
"\t"BUG_TABLE_ENTRY" 1b,%1,%2,%3\n" \
".previous" \
: : "r" ((long long)(x)), \
: : "r" ((long)(x)), \
"i" (__LINE__ + BUG_WARNING_TRAP), \
"i" (__FILE__), "i" (__FUNCTION__)); \
} while (0)
@@ -61,9 +69,9 @@ struct bug_entry *find_bug(unsigned long bugaddr);
#define HAVE_ARCH_BUG
#define HAVE_ARCH_BUG_ON
#define HAVE_ARCH_WARN_ON
#endif
#endif
#endif /* CONFIG_BUG */
#endif /* __ASSEMBLY __ */
#include <asm-generic/bug.h>
#endif
#endif /* _ASM_POWERPC_BUG_H */
include/asm-ppc64/byteorder.h → include/asm-powerpc/byteorder.h
+7 -4
View File
@@ -1,5 +1,5 @@
#ifndef _PPC64_BYTEORDER_H
#define _PPC64_BYTEORDER_H
#ifndef _ASM_POWERPC_BYTEORDER_H
#define _ASM_POWERPC_BYTEORDER_H
/*
* This program is free software; you can redistribute it and/or
@@ -77,10 +77,13 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
#ifndef __STRICT_ANSI__
#define __BYTEORDER_HAS_U64__
#endif
#ifndef __powerpc64__
#define __SWAB_64_THRU_32__
#endif /* __powerpc64__ */
#endif /* __STRICT_ANSI__ */
#endif /* __GNUC__ */
#include <linux/byteorder/big_endian.h>
#endif /* _PPC64_BYTEORDER_H */
#endif /* _ASM_POWERPC_BYTEORDER_H */
include/asm-ppc64/checksum.h → include/asm-powerpc/checksum.h
+36 -11
View File
@@ -1,5 +1,5 @@
#ifndef _PPC64_CHECKSUM_H
#define _PPC64_CHECKSUM_H
#ifndef _ASM_POWERPC_CHECKSUM_H
#define _ASM_POWERPC_CHECKSUM_H
/*
* This program is free software; you can redistribute it and/or
@@ -41,8 +41,14 @@ extern unsigned int csum_partial(const unsigned char * buff, int len,
unsigned int sum);
/*
* the same as csum_partial, but copies from src to dst while it
* checksums
* Computes the checksum of a memory block at src, length len,
* and adds in "sum" (32-bit), while copying the block to dst.
* If an access exception occurs on src or dst, it stores -EFAULT
* to *src_err or *dst_err respectively (if that pointer is not
* NULL), and, for an error on src, zeroes the rest of dst.
*
* Like csum_partial, this must be called with even lengths,
* except for the last fragment.
*/
extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
int len, unsigned int sum,
@@ -51,12 +57,18 @@ extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
* the same as csum_partial, but copies from src to dst while it
* checksums.
*/
unsigned int csum_partial_copy_nocheck(const char *src,
char *dst,
int len,
unsigned int sum);
#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
csum_partial_copy_generic((src), (dst), (len), (sum), (errp), NULL)
#define csum_partial_copy_nocheck(src, dst, len, sum) \
csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
/*
* turns a 32-bit partial checksum (e.g. from csum_partial) into a
* 1's complement 16-bit checksum.
@@ -83,12 +95,7 @@ static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
return csum_fold(csum_partial(buff, len, 0));
}
#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
csum_partial_copy_generic((src), (dst), (len), (sum), (errp), NULL)
#define csum_partial_copy_nocheck(src, dst, len, sum) \
csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
#ifdef __powerpc64__
static inline u32 csum_tcpudp_nofold(u32 saddr,
u32 daddr,
unsigned short len,
@@ -103,5 +110,23 @@ static inline u32 csum_tcpudp_nofold(u32 saddr,
s += (s >> 32);
return (u32) s;
}
#else
static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum)
{
__asm__("\n\
addc %0,%0,%1 \n\
adde %0,%0,%2 \n\
adde %0,%0,%3 \n\
addze %0,%0 \n\
"
: "=r" (sum)
: "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
return sum;
}
#endif
#endif
include/asm-powerpc/cputable.h
+427
View File
@@ -0,0 +1,427 @@
#ifndef __ASM_POWERPC_CPUTABLE_H
#define __ASM_POWERPC_CPUTABLE_H
#include <linux/config.h>
#include <asm/ppc_asm.h> /* for ASM_CONST */
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
#define PPC_FEATURE_HAS_FPU 0x08000000
#define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
#define PPC_FEATURE_NO_TB 0x00100000
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
/* This structure can grow, it's real size is used by head.S code
* via the mkdefs mechanism.
*/
struct cpu_spec;
struct op_powerpc_model;
typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
struct cpu_spec {
/* CPU is matched via (PVR & pvr_mask) == pvr_value */
unsigned int pvr_mask;
unsigned int pvr_value;
char *cpu_name;
unsigned long cpu_features; /* Kernel features */
unsigned int cpu_user_features; /* Userland features */
/* cache line sizes */
unsigned int icache_bsize;
unsigned int dcache_bsize;
/* number of performance monitor counters */
unsigned int num_pmcs;
/* this is called to initialize various CPU bits like L1 cache,
* BHT, SPD, etc... from head.S before branching to identify_machine
*/
cpu_setup_t cpu_setup;
/* Used by oprofile userspace to select the right counters */
char *oprofile_cpu_type;
/* Processor specific oprofile operations */
struct op_powerpc_model *oprofile_model;
};
extern struct cpu_spec *cur_cpu_spec;
extern void identify_cpu(unsigned long offset, unsigned long cpu);
extern void do_cpu_ftr_fixups(unsigned long offset);
#endif /* __ASSEMBLY__ */
/* CPU kernel features */
/* Retain the 32b definitions all use bottom half of word */
#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
#ifdef __powerpc64__
/* Add the 64b processor unique features in the top half of the word */
#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
#else
/* ensure on 32b processors the flags are available for compiling but
* don't do anything */
#define CPU_FTR_SLB ASM_CONST(0x0)
#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
#define CPU_FTR_TLBIEL ASM_CONST(0x0)
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
#define CPU_FTR_IABR ASM_CONST(0x0)
#define CPU_FTR_MMCRA ASM_CONST(0x0)
#define CPU_FTR_CTRL ASM_CONST(0x0)
#define CPU_FTR_SMT ASM_CONST(0x0)
#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
#endif
#ifndef __ASSEMBLY__
#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
/* iSeries doesn't support large pages */
#ifdef CONFIG_PPC_ISERIES
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
#else
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
#endif /* CONFIG_PPC_ISERIES */
/* We only set the altivec features if the kernel was compiled with altivec
* support
*/
#ifdef CONFIG_ALTIVEC
#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
#else
#define CPU_FTR_ALTIVEC_COMP 0
#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
#endif
/* We need to mark all pages as being coherent if we're SMP or we
* have a 74[45]x and an MPC107 host bridge.
*/
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON 0
#endif
/* The powersave features NAP & DOZE seems to confuse BDI when
debugging. So if a BDI is used, disable theses
*/
#ifndef CONFIG_BDI_SWITCH
#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
#else
#define CPU_FTR_MAYBE_CAN_DOZE 0
#define CPU_FTR_MAYBE_CAN_NAP 0
#endif
#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
!defined(CONFIG_BOOKE))
enum {
CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_NO_DPM,
CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NEED_COHERENT,
CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
CPU_FTR_NEED_COHERENT,
CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB |
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
CPU_FTR_NEED_COHERENT,
CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
CPU_FTR_MAYBE_CAN_NAP,
CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_E200 = CPU_FTR_USE_TB,
CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_BIG_PHYS,
CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
#ifdef __powerpc64__
CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
CPU_FTR_MMCRA | CPU_FTR_CTRL,
CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
CPU_FTR_MMCRA_SIHV,
CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
#endif
CPU_FTRS_POSSIBLE =
#if CLASSIC_PPC
CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
#else
CPU_FTRS_GENERIC_32 |
#endif
#ifdef CONFIG_PPC64BRIDGE
CPU_FTRS_POWER3_32 |
#endif
#ifdef CONFIG_POWER4
CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
#endif
#ifdef CONFIG_8xx
CPU_FTRS_8XX |
#endif
#ifdef CONFIG_40x
CPU_FTRS_40X |
#endif
#ifdef CONFIG_44x
CPU_FTRS_44X |
#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 |
#endif
#ifdef CONFIG_E500
CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif
#ifdef __powerpc64__
CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
#endif
0,
CPU_FTRS_ALWAYS =
#if CLASSIC_PPC
CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
#else
CPU_FTRS_GENERIC_32 &
#endif
#ifdef CONFIG_PPC64BRIDGE
CPU_FTRS_POWER3_32 &
#endif
#ifdef CONFIG_POWER4
CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
#endif
#ifdef CONFIG_8xx
CPU_FTRS_8XX &
#endif
#ifdef CONFIG_40x
CPU_FTRS_40X &
#endif
#ifdef CONFIG_44x
CPU_FTRS_44X &
#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 &
#endif
#ifdef CONFIG_E500
CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif
#ifdef __powerpc64__
CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
#endif
CPU_FTRS_POSSIBLE,
};
static inline int cpu_has_feature(unsigned long feature)
{
return (CPU_FTRS_ALWAYS & feature) ||
(CPU_FTRS_POSSIBLE
& cur_cpu_spec->cpu_features
& feature);
}
#endif /* !__ASSEMBLY__ */
#ifdef __ASSEMBLY__
#define BEGIN_FTR_SECTION 98:
#ifndef __powerpc64__
#define END_FTR_SECTION(msk, val) \
99: \
.section __ftr_fixup,"a"; \
.align 2; \
.long msk; \
.long val; \
.long 98b; \
.long 99b; \
.previous
#else /* __powerpc64__ */
#define END_FTR_SECTION(msk, val) \
99: \
.section __ftr_fixup,"a"; \
.align 3; \
.llong msk; \
.llong val; \
.llong 98b; \
.llong 99b; \
.previous
#endif /* __powerpc64__ */
#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_CPUTABLE_H */
include/asm-ppc/dbdma.h → include/asm-powerpc/dbdma.h
View File
include/asm-ppc/dma.h → include/asm-powerpc/dma.h
+55 -36
View File
@@ -1,18 +1,14 @@
#ifndef _ASM_POWERPC_DMA_H
#define _ASM_POWERPC_DMA_H
/*
* include/asm-ppc/dma.h: Defines for using and allocating dma channels.
* Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
* Changes for ppc sound by Christoph Nadig
*/
#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/system.h>
/*
* Note: Adapted for PowerPC by Gary Thomas
* Modified by Cort Dougan <cort@cs.nmt.edu>
@@ -25,8 +21,10 @@
* with a grain of salt.
*/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <linux/config.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/system.h>
#ifndef MAX_DMA_CHANNELS
#define MAX_DMA_CHANNELS 8
@@ -34,11 +32,9 @@
/* The maximum address that we can perform a DMA transfer to on this platform */
/* Doesn't really apply... */
#define MAX_DMA_ADDRESS 0xFFFFFFFF
#define MAX_DMA_ADDRESS (~0UL)
/* in arch/ppc/kernel/setup.c -- Cort */
extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
extern unsigned long ISA_DMA_THRESHOLD;
#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb outb_p
@@ -171,7 +167,18 @@ extern long ppc_cs4232_dma, ppc_cs4232_dma2;
#define DMA1_EXT_REG 0x40B
#define DMA2_EXT_REG 0x4D6
#ifndef __powerpc64__
/* in arch/ppc/kernel/setup.c -- Cort */
extern unsigned int DMA_MODE_WRITE;
extern unsigned int DMA_MODE_READ;
extern unsigned long ISA_DMA_THRESHOLD;
#else
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#endif
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
extern spinlock_t dma_spin_lock;
@@ -200,8 +207,9 @@ static __inline__ void enable_dma(unsigned int dmanr)
if (dmanr <= 3) {
dma_outb(dmanr, DMA1_MASK_REG);
dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
} else
} else {
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
}
static __inline__ void disable_dma(unsigned int dmanr)
@@ -290,19 +298,26 @@ static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
{
if (dmanr <= 3) {
dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
dma_outb(phys & 0xff,
((dmanr & 3) << 1) + IO_DMA1_BASE);
dma_outb((phys >> 8) & 0xff,
((dmanr & 3) << 1) + IO_DMA1_BASE);
} else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb(phys & 0xff,
((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((phys >> 8) & 0xff,
((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((dmanr & 3), DMA2_EXT_REG);
} else {
dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((phys >> 1) & 0xff,
((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((phys >> 9) & 0xff,
((dmanr & 3) << 2) + IO_DMA2_BASE);
}
set_dma_page(dmanr, phys >> 16);
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
@@ -315,21 +330,24 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
IO_DMA1_BASE);
dma_outb(count & 0xff,
((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
dma_outb((count >> 8) & 0xff,
((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
} else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
IO_DMA2_BASE);
dma_outb(count & 0xff,
((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
dma_outb((count >> 8) & 0xff,
((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
} else {
dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
IO_DMA2_BASE);
dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
IO_DMA2_BASE);
dma_outb((count >> 1) & 0xff,
((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
dma_outb((count >> 9) & 0xff,
((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
@@ -340,8 +358,8 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr <= 3) ?
((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
unsigned int io_port = (dmanr <= 3)
? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
: ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
@@ -352,7 +370,6 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
? count : (count << 1);
}
/* These are in kernel/dma.c: */
@@ -367,5 +384,7 @@ extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* _ASM_DMA_H */
#endif /* __KERNEL__ */
#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
#endif /* _ASM_POWERPC_DMA_H */
include/asm-ppc64/elf.h → include/asm-powerpc/elf.h
+68 -40
View File
@@ -1,10 +1,11 @@
#ifndef __PPC64_ELF_H
#define __PPC64_ELF_H
#ifndef _ASM_POWERPC_ELF_H
#define _ASM_POWERPC_ELF_H
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/cputable.h>
#include <asm/auxvec.h>
#include <asm/page.h>
/* PowerPC relocations defined by the ABIs */
#define R_PPC_NONE 0
@@ -75,7 +76,7 @@
#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
/* Keep this the last entry. */
/* keep this the last entry. */
#define R_PPC_NUM 95
/*
@@ -90,8 +91,6 @@
#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
#define ELF_NFPREG 33 /* includes fpscr */
#define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
#define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
@@ -100,8 +99,21 @@ typedef unsigned int elf_greg_t32;
typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
/*
* These are used to set parameters in the core dumps.
* ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
*/
#ifdef __powerpc64__
# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
# define ELF_GREG_TYPE elf_greg_t64
#else
# define ELF_NEVRREG 34 /* includes acc (as 2) */
# define ELF_NVRREG 33 /* includes vscr */
# define ELF_GREG_TYPE elf_greg_t32
# define ELF_ARCH EM_PPC
# define ELF_CLASS ELFCLASS32
# define ELF_DATA ELFDATA2MSB
#endif /* __powerpc64__ */
#ifndef ELF_ARCH
# define ELF_ARCH EM_PPC64
# define ELF_CLASS ELFCLASS64
@@ -114,8 +126,9 @@ typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
typedef elf_greg_t32 elf_greg_t;
typedef elf_gregset_t32 elf_gregset_t;
# define elf_addr_t u32
#endif
#endif /* ELF_ARCH */
/* Floating point registers */
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
@@ -125,7 +138,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
* The entry with index 32 contains the vscr as the last word (offset 12)
* within the quadword. This allows the vscr to be stored as either a
* quadword (since it must be copied via a vector register to/from storage)
* or as a word. The entry with index 33 contains the vrsave as the first
* or as a word.
*
* 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
* word (offset 0) within the quadword.
*
* This definition of the VMX state is compatible with the current PPC32
@@ -138,7 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
*/
typedef __vector128 elf_vrreg_t;
typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
#ifdef __powerpc64__
typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
#endif
/*
* This is used to ensure we don't load something for the wrong architecture.
@@ -146,7 +163,7 @@ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
#define ELF_EXEC_PAGESIZE PAGE_SIZE
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
@@ -158,26 +175,34 @@ typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
#ifdef __KERNEL__
/* Common routine for both 32-bit and 64-bit processes */
static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs,
static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
struct pt_regs *regs)
{
int i;
int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64);
int i, nregs;
if (gprs > ELF_NGREG)
gprs = ELF_NGREG;
memset((void *)elf_regs, 0, sizeof(elf_gregset_t));
for (i=0; i < gprs; i++)
elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i];
/* Our registers are always unsigned longs, whether we're a 32 bit
* process or 64 bit, on either a 64 bit or 32 bit kernel.
* Don't use ELF_GREG_TYPE here. */
nregs = sizeof(struct pt_regs) / sizeof(unsigned long);
if (nregs > ELF_NGREG)
nregs = ELF_NGREG;
for (i = 0; i < nregs; i++) {
/* This will correctly truncate 64 bit registers to 32 bits
* for a 32 bit process on a 64 bit kernel. */
elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
}
}
#define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs);
#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
static inline int dump_task_regs(struct task_struct *tsk,
elf_gregset_t *elf_regs)
{
struct pt_regs *regs = tsk->thread.regs;
if (regs)
ppc64_elf_core_copy_regs(*elf_regs, regs);
ppc_elf_core_copy_regs(*elf_regs, regs);
return 1;
}
@@ -186,15 +211,17 @@ static inline int dump_task_regs(struct task_struct *tsk,
extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
/* XXX Should we define the XFPREGS using altivec ??? */
#endif /* __KERNEL__ */
#endif
/* This yields a mask that user programs can use to figure out what
/* ELF_HWCAP yields a mask that user programs can use to figure out what
instruction set this cpu supports. This could be done in userspace,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
#ifdef __powerpc64__
# define ELF_PLAT_INIT(_r, load_addr) do { \
_r->gpr[2] = load_addr; \
} while (0)
#endif /* __powerpc64__ */
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
@@ -205,14 +232,10 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
#define ELF_PLATFORM (NULL)
#define ELF_PLAT_INIT(_r, load_addr) do { \
memset(_r->gpr, 0, sizeof(_r->gpr)); \
_r->ctr = _r->link = _r->xer = _r->ccr = 0; \
_r->gpr[2] = load_addr; \
} while (0)
#ifdef __KERNEL__
#define SET_PERSONALITY(ex, ibcs2) \
#ifdef __powerpc64__
# define SET_PERSONALITY(ex, ibcs2) \
do { \
unsigned long new_flags = 0; \
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
@@ -225,7 +248,6 @@ do { \
if (personality(current->personality) != PER_LINUX32) \
set_personality(PER_LINUX); \
} while (0)
/*
* An executable for which elf_read_implies_exec() returns TRUE will
* have the READ_IMPLIES_EXEC personality flag set automatically. This
@@ -233,19 +255,26 @@ do { \
* the 64bit ABI has never had these issues dont enable the workaround
* even if we have an executable stack.
*/
#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
(exec_stk != EXSTACK_DISABLE_X) : 0)
#else
# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
#endif /* __powerpc64__ */
#endif
#endif /* __KERNEL__ */
extern int dcache_bsize;
extern int icache_bsize;
extern int ucache_bsize;
/* We do have an arch_setup_additional_pages for vDSO matters */
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
#ifdef __powerpc64__
struct linux_binprm;
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES /* vDSO has arch_setup_additional_pages */
extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
#else
#define VDSO_AUX_ENT(a,b)
#endif /* __powerpc64__ */
/*
* The requirements here are:
@@ -265,9 +294,8 @@ do { \
NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
/* vDSO base */ \
NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base); \
} while (0)
VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base) \
} while (0)
/* PowerPC64 relocations defined by the ABIs */
#define R_PPC64_NONE R_PPC_NONE
@@ -384,4 +412,4 @@ do { \
/* Keep this the last entry. */
#define R_PPC64_NUM 107
#endif /* __PPC64_ELF_H */
#endif /* _ASM_POWERPC_ELF_H */

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