[MIPS] Fix fpu_save_double on 64-bit.
> Without this fix, _save_fp() in 64-bit kernel is seriously broken. > > ffffffff8010bec0 <_save_fp>: > ffffffff8010bec0: 400d6000 mfc0 t1,c0_status > ffffffff8010bec4: 000c7140 sll t2,t0,0x5 > ffffffff8010bec8: 05c10011 bgez t2,ffffffff8010bf10 <_save_fp+0x50> > ffffffff8010becc: 00000000 nop > ffffffff8010bed0: f4810328 sdc1 $f1,808(a0) > ... Fix register usage in fpu_save_double() and make fpu_restore_double() more symmetric with fpu_save_double(). Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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committed by
Ralf Baechle
parent
734996820f
commit
c138e12f3a
@@ -12,7 +12,7 @@
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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.macro fpu_save_double thread status tmp1=t0 tmp2
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.macro fpu_save_double thread status tmp1=t0
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cfc1 \tmp1, fcr31
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sdc1 $f0, THREAD_FPR0(\thread)
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sdc1 $f2, THREAD_FPR2(\thread)
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@@ -70,7 +70,7 @@
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sw \tmp, THREAD_FCR31(\thread)
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.endm
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.macro fpu_restore_double thread tmp=t0
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.macro fpu_restore_double thread status tmp=t0
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lw \tmp, THREAD_FCR31(\thread)
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ldc1 $f0, THREAD_FPR0(\thread)
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ldc1 $f2, THREAD_FPR2(\thread)
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@@ -53,12 +53,12 @@
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sdc1 $f31, THREAD_FPR31(\thread)
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.endm
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.macro fpu_save_double thread status tmp1 tmp2
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sll \tmp2, \tmp1, 5
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bgez \tmp2, 2f
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.macro fpu_save_double thread status tmp
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sll \tmp, \status, 5
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bgez \tmp, 2f
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fpu_save_16odd \thread
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2:
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fpu_save_16even \thread \tmp1 # clobbers t1
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fpu_save_16even \thread \tmp
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.endm
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.macro fpu_restore_16even thread tmp=t0
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@@ -101,13 +101,12 @@
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ldc1 $f31, THREAD_FPR31(\thread)
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.endm
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.macro fpu_restore_double thread tmp
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mfc0 t0, CP0_STATUS
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sll t1, t0, 5
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bgez t1, 1f # 16 register mode?
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.macro fpu_restore_double thread status tmp
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sll \tmp, \status, 5
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bgez \tmp, 1f # 16 register mode?
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fpu_restore_16odd a0
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1: fpu_restore_16even a0, t0 # clobbers t0
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fpu_restore_16odd \thread
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1: fpu_restore_16even \thread \tmp
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.endm
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.macro cpu_save_nonscratch thread
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