diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x index 651602a61eac..234c33fbdb55 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm3x @@ -236,7 +236,7 @@ What: /sys/bus/coresight/devices/.[etm|ptm]/traceid Date: November 2014 KernelVersion: 3.19 Contact: Mathieu Poirier -Description: (RW) Holds the trace ID that will appear in the trace stream +Description: (RO) Holds the trace ID that will appear in the trace stream coming from this trace entity. What: /sys/bus/coresight/devices/.[etm|ptm]/trigger_event diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm new file mode 100644 index 000000000000..4a58e649550d --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm @@ -0,0 +1,13 @@ +What: /sys/bus/coresight/devices//integration_test +Date: January 2023 +KernelVersion 6.2 +Contact: Jinlong Mao (QUIC) , Tao Zhang (QUIC) +Description: + (Write) Run integration test for tpdm. Integration test + will generate test data for tpdm. It can help to make + sure that the trace path is enabled and the link configurations + are fine. + + Accepts only one of the 2 values - 1 or 2. + 1 : Generate 64 bits data + 2 : Generate 32 bits data diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb new file mode 100644 index 000000000000..f560918ae738 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ultra_smb @@ -0,0 +1,31 @@ +What: /sys/bus/coresight/devices/ultra_smb/enable_sink +Date: January 2023 +KernelVersion: 6.3 +Contact: Junhao He +Description: (RW) Add/remove a SMB device from a trace path. There can be + multiple sources for a single SMB device. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/buf_size +Date: January 2023 +KernelVersion: 6.3 +Contact: Junhao He +Description: (RO) Shows the buffer size of each UltraSoc SMB device. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/buf_status +Date: January 2023 +KernelVersion: 6.3 +Contact: Junhao He +Description: (RO) Shows the value of UltraSoc SMB status register. + BIT(0) is zero means buffer is empty. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/read_pos +Date: January 2023 +KernelVersion: 6.3 +Contact: Junhao He +Description: (RO) Shows the value of UltraSoc SMB Read Pointer register. + +What: /sys/bus/coresight/devices/ultra_smb/mgmt/write_pos +Date: January 2023 +KernelVersion: 6.3 +Contact: Junhao He +Description: (RO) Shows the value of UltraSoc SMB Write Pointer register. diff --git a/Documentation/ABI/testing/sysfs-driver-uacce b/Documentation/ABI/testing/sysfs-driver-uacce index 08f2591138af..d3f0b8f3c589 100644 --- a/Documentation/ABI/testing/sysfs-driver-uacce +++ b/Documentation/ABI/testing/sysfs-driver-uacce @@ -19,6 +19,24 @@ Contact: linux-accelerators@lists.ozlabs.org Description: Available instances left of the device Return -ENODEV if uacce_ops get_available_instances is not provided +What: /sys/class/uacce//isolate_strategy +Date: Nov 2022 +KernelVersion: 6.1 +Contact: linux-accelerators@lists.ozlabs.org +Description: (RW) A sysfs node that configure the error threshold for the hardware + isolation strategy. This size is a configured integer value, which is the + number of threshold for hardware errors occurred in one hour. The default is 0. + 0 means never isolate the device. The maximum value is 65535. You can write + a number of threshold based on your hardware. + +What: /sys/class/uacce//isolate +Date: Nov 2022 +KernelVersion: 6.1 +Contact: linux-accelerators@lists.ozlabs.org +Description: (R) A sysfs node that read the device isolated state. The value 1 + means the device is unavailable. The 0 means the device is + available. + What: /sys/class/uacce//algorithms Date: Feb 2020 KernelVersion: 5.7 diff --git a/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager new file mode 100644 index 000000000000..57b9b68a73ee --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager @@ -0,0 +1,16 @@ +What: /sys/devices/platform/amba_pl//errcnt +Date: Nov 2022 +Contact: appana.durga.kedareswara.rao@amd.com +Description: This control file provides the fault detection count. + This file cannot be written. + Example: + # cat /sys/devices/platform/amba_pl/44a10000.tmr_manager/errcnt + 1 + +What: /sys/devices/platform/amba_pl//dis_block_break +Date: Nov 2022 +Contact: appana.durga.kedareswara.rao@amd.com +Description: Write any value to it, This control file enables the break signal. + This file is write only. + Example: + # echo > /sys/devices/platform/amba_pl/44a10000.tmr_manager/dis_block_break diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9ee6547d75d3..6c6d8f6ca794 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1172,10 +1172,10 @@ specified, the serial port must already be setup and configured. - uart[8250],io,[,options] - uart[8250],mmio,[,options] - uart[8250],mmio32,[,options] - uart[8250],mmio32be,[,options] + uart[8250],io,[,options[,uartclk]] + uart[8250],mmio,[,options[,uartclk]] + uart[8250],mmio32,[,options[,uartclk]] + uart[8250],mmio32be,[,options[,uartclk]] uart[8250],0x[,options] Start an early, polled-mode console on the 8250/16550 UART at the specified I/O port or MMIO address. @@ -1184,7 +1184,9 @@ If none of [io|mmio|mmio32|mmio32be], is assumed to be equivalent to 'mmio'. 'options' are specified in the same format described for "console=ttyS"; if - unspecified, the h/w is not initialized. + unspecified, the h/w is not initialized. 'uartclk' is + the uart clock frequency; if unspecified, it is set + to 'BASE_BAUD' * 16. pl011, pl011,mmio32, diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml new file mode 100644 index 000000000000..2ec9b5b24d73 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Aggregator - TPDA + +description: | + TPDAs are responsible for packetization and timestamping of data sets + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or + more attached TPDM and pushing the resultant (packetized) data out a + master ATB interface. Performing an arbitrated ATB interleaving (funneling) + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows). + + There is no strict binding between TPDM and TPDA. TPDA can have multiple + TPDMs connect to it. But There must be only one TPDA in the path from the + TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or + connect to funnel which will connect to TPDA's inport. + + We can use the commands are similar to the below to validate TPDMs. + Enable coresight sink first. + + echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink + echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source + echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test + echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test + + The test data will be collected in the coresight sink which is enabled. + If rwp register of the sink is keeping updating when do integration_test + (by cat tmc_etf0/mgmt/rwp), it means there is data generated from TPDM + to sink. + +maintainers: + - Mao Jinlong + - Tao Zhang + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tpda + required: + - compatible + +properties: + $nodename: + pattern: "^tpda(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpda + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + in-ports: + type: object + description: | + Input connections from TPDM to TPDA + $ref: /schemas/graph.yaml#/properties/ports + + out-ports: + type: object + description: | + Output connections from the TPDA to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: + Output connection from the TPDA to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + # minimum tpda definition. + - | + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x6004000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_0_in_tpdm_dcc: endpoint { + remote-endpoint = + <&tpdm_dcc_out_tpda_qdss_0>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpda_qdss>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml new file mode 100644 index 000000000000..5c08342664ea --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Trace, Profiling and Diagnostics Monitor - TPDM + +description: | + The TPDM or Monitor serves as data collection component for various dataset + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef), + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete + Single Bit (DSB). It performs data collection in the data producing clock + domain and transfers it to the data collection time domain, generally ATB + clock domain. + + The primary use case of the TPDM is to collect data from different data + sources and send it to a TPDA for packetization, timestamping, and funneling. + +maintainers: + - Mao Jinlong + - Tao Zhang + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tpdm + required: + - compatible + +properties: + $nodename: + pattern: "^tpdm(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-tpdm + - const: arm,primecell + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + out-ports: + description: | + Output connections from the TPDM to coresight funnel/TPDA. + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Output connection from the TPDM to coresight + funnel/TPDA. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum TPDM definition. TPDM connect to coresight TPDA. + - | + tpdm@684c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0684c000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_tpdm_prng>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml index 7332442e5661..b6ba7ad1a8d5 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16201.yaml @@ -41,7 +41,7 @@ unevaluatedProperties: false examples: - | #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml index f6f97164c2ca..5887021cc90f 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adis16240.yaml @@ -39,7 +39,7 @@ examples: - | #include #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml index 185b68ffb536..0c5b64cae965 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl313.yaml @@ -59,7 +59,7 @@ examples: - | #include #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index 346abfb13a3a..07cacc3f6a97 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -49,7 +49,7 @@ examples: - | #include #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; @@ -64,7 +64,7 @@ examples: - | #include #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml index 6b03c4efbb08..c07261c71013 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml @@ -58,34 +58,34 @@ unevaluatedProperties: false examples: - | - #include - #include - i2c { - #address-cells = <1>; - #size-cells = <0>; + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; - /* Example for a I2C device node */ - accelerometer@1d { - compatible = "adi,adxl355"; - reg = <0x1d>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "DRDY"; - }; + /* Example for a I2C device node */ + accelerometer@1d { + compatible = "adi,adxl355"; + reg = <0x1d>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "DRDY"; }; + }; - | - #include - #include - spi { - #address-cells = <1>; - #size-cells = <0>; + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; - accelerometer@0 { - compatible = "adi,adxl355"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "DRDY"; - }; + accelerometer@0 { + compatible = "adi,adxl355"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "DRDY"; }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml index 73a5c8f814cc..62465e36a590 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml @@ -37,32 +37,32 @@ unevaluatedProperties: false examples: - | - #include - #include - i2c0 { - #address-cells = <1>; - #size-cells = <0>; + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; - /* Example for a I2C device node */ - accelerometer@53 { - compatible = "adi,adxl372"; - reg = <0x53>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - }; + /* Example for a I2C device node */ + accelerometer@53 { + compatible = "adi,adxl372"; + reg = <0x53>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; }; + }; - | - #include - #include - spi0 { - #address-cells = <1>; - #size-cells = <0>; + #include + #include + spi { + #address-cells = <1>; + #size-cells = <0>; - accelerometer@0 { - compatible = "adi,adxl372"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - }; + accelerometer@0 { + compatible = "adi,adxl372"; + reg = <0>; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; }; + }; diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml index 5dd06f5905b4..ec643de031a3 100644 --- a/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml +++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma220.yaml @@ -36,7 +36,7 @@ unevaluatedProperties: false examples: - | #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml index 714e48e613de..6ddb03f61bd9 100644 --- a/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml +++ b/Documentation/devicetree/bindings/iio/accel/kionix,kxcjk1013.yaml @@ -44,7 +44,7 @@ examples: accel@f { compatible = "kionix,kxtf9"; - reg = <0x0F>; + reg = <0xf>; mount-matrix = "0", "1", "0", "1", "0", "0", "0", "0", "1"; diff --git a/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml b/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml index 23528dcaa073..d530ec041fe7 100644 --- a/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml +++ b/Documentation/devicetree/bindings/iio/accel/memsensing,msa311.yaml @@ -1,9 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause - %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/accel/memsensing,msa311.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: MEMSensing digital 3-Axis accelerometer diff --git a/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml b/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml index 65ce8ea14b52..783c7ddfcd90 100644 --- a/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml +++ b/Documentation/devicetree/bindings/iio/accel/nxp,fxls8962af.yaml @@ -50,7 +50,7 @@ unevaluatedProperties: false examples: - | #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; @@ -65,7 +65,7 @@ examples: }; - | #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml index b97559f23b3a..ce7ba634643c 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7091r5.yaml @@ -44,11 +44,11 @@ examples: #size-cells = <0>; adc@2f { - compatible = "adi,ad7091r5"; - reg = <0x2f>; + compatible = "adi,ad7091r5"; + reg = <0x2f>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml index 75a7184a4735..35ed04350e28 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml @@ -61,7 +61,7 @@ required: patternProperties: "^channel@([0-9]|1[0-5])$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml index cc347dade4ef..d521d516088b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml @@ -99,26 +99,26 @@ unevaluatedProperties: false examples: - | - spi0 { - #address-cells = <1>; - #size-cells = <0>; + spi { + #address-cells = <1>; + #size-cells = <0>; - adc@0 { - compatible = "adi,ad7192"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - spi-cpha; - clocks = <&ad7192_mclk>; - clock-names = "mclk"; - interrupts = <25 0x2>; - interrupt-parent = <&gpio>; - dvdd-supply = <&dvdd>; - avdd-supply = <&avdd>; + adc@0 { + compatible = "adi,ad7192"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + clocks = <&ad7192_mclk>; + clock-names = "mclk"; + interrupts = <25 0x2>; + interrupt-parent = <&gpio>; + dvdd-supply = <&dvdd>; + avdd-supply = <&avdd>; - adi,refin2-pins-enable; - adi,rejection-60-Hz-enable; - adi,buffer-enable; - adi,burnout-currents-enable; + adi,refin2-pins-enable; + adi,rejection-60-Hz-enable; + adi,buffer-enable; + adi,burnout-currents-enable; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml index 1bfbeed6f299..7cc4ddc4e9b7 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7292.yaml @@ -43,7 +43,7 @@ required: patternProperties: "^channel@[0-7]$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index ac5a47c8f070..7fa46df1f4fb 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -112,30 +112,30 @@ examples: - | #include #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; adc@0 { - compatible = "adi,ad7606-8"; - reg = <0>; - spi-max-frequency = <1000000>; - spi-cpol; - spi-cpha; + compatible = "adi,ad7606-8"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; - avcc-supply = <&adc_vref>; + avcc-supply = <&adc_vref>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; - adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; - adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>, - <&gpio 23 GPIO_ACTIVE_HIGH>, - <&gpio 26 GPIO_ACTIVE_HIGH>; - standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>; - adi,sw-mode; + adi,conversion-start-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + adi,first-data-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>, + <&gpio 23 GPIO_ACTIVE_HIGH>, + <&gpio 26 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio 24 GPIO_ACTIVE_LOW>; + adi,sw-mode; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml index a67ba67dab51..5fcc8dd012f1 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml @@ -72,7 +72,7 @@ additionalProperties: false examples: - | #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml index 29641ce7175b..433ed2c9295f 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad799x.yaml @@ -57,17 +57,17 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - adc1: adc@28 { - reg = <0x28>; - compatible = "adi,ad7991"; - interrupts = <13 2>; - interrupt-parent = <&gpio6>; + adc1: adc@28 { + reg = <0x28>; + compatible = "adi,ad7991"; + interrupts = <13 2>; + interrupt-parent = <&gpio6>; - vcc-supply = <&vcc_3v3>; - vref-supply = <&adc_vref>; + vcc-supply = <&vcc_3v3>; + vref-supply = <&adc_vref>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml index 2d72ff6bcbc0..7aa748d6b7a0 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad9467.yaml @@ -64,10 +64,10 @@ examples: #size-cells = <0>; adc@0 { - compatible = "adi,ad9467"; - reg = <0>; - clocks = <&adc_clk>; - clock-names = "adc-clk"; + compatible = "adi,ad9467"; + reg = <0>; + clocks = <&adc_clk>; + clock-names = "adc-clk"; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml index 8e25773d69be..9996dd93f84b 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,axi-adc.yaml @@ -51,11 +51,11 @@ additionalProperties: false examples: - | axi-adc@44a00000 { - compatible = "adi,axi-adc-10.0.a"; - reg = <0x44a00000 0x10000>; - dmas = <&rx_dma 0>; - dma-names = "rx"; + compatible = "adi,axi-adc-10.0.a"; + reg = <0x44a00000 0x10000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; - adi,adc-dev = <&spi_adc>; + adi,adc-dev = <&spi_adc>; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml index 31f840d59303..4817b840977a 100644 --- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -41,7 +41,7 @@ properties: description: Startup time expressed in ms, it depends on SoC. atmel,trigger-edge-type: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: One of possible edge types for the ADTRG hardware trigger pin. When the specific edge type is detected, the conversion will diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml index 77605f17901c..9c57eb13f892 100644 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/avia-hx711.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/avia-hx711.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: AVIA HX711 ADC chip for weight cells diff --git a/Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml b/Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml new file mode 100644 index 000000000000..6d4fb3e1d2a2 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/cirrus,ep9301-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP930x internal ADC + +description: | + Cirrus Logic EP9301/EP9302 SoCs' internal ADC block. + + User's manual: + https://cdn.embeddedts.com/resource-attachments/ts-7000_ep9301-ug.pdf + +maintainers: + - Alexander Sverdlin + +properties: + compatible: + const: cirrus,ep9301-adc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + adc: adc@80900000 { + compatible = "cirrus,ep9301-adc"; + reg = <0x80900000 0x28>; + clocks = <&syscon 24>; + interrupt-parent = <&vic1>; + interrupts = <30>; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml index 517e8b1fcb73..9cd0fd539782 100644 --- a/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ingenic,adc.yaml @@ -2,8 +2,8 @@ # Copyright 2019-2020 Artur Rojek %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/ingenic,adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Ingenic JZ47xx ADC controller IIO @@ -78,14 +78,14 @@ examples: #include adc@10070000 { - compatible = "ingenic,jz4740-adc"; - #io-channel-cells = <1>; + compatible = "ingenic,jz4740-adc"; + #io-channel-cells = <1>; - reg = <0x10070000 0x30>; + reg = <0x10070000 0x30>; - clocks = <&cgu JZ4740_CLK_ADC>; - clock-names = "adc"; + clocks = <&cgu JZ4740_CLK_ADC>; + clock-names = "adc"; - interrupt-parent = <&intc>; - interrupts = <18>; + interrupt-parent = <&intc>; + interrupts = <18>; }; diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml index d0a7ed26d9ea..e4b362113509 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1027.yaml @@ -54,8 +54,8 @@ examples: - | #include spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; maxadc: adc@0 { compatible = "maxim,max1027"; reg = <0>; diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml index 50bcd72ac9d6..60d7b34e3286 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1238.yaml @@ -10,7 +10,7 @@ maintainers: - Jonathan Cameron description: | - Family of simple ADCs with i2c inteface and internal references. + Family of simple ADCs with i2c interface and internal references. properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml index 58b12fe8070c..ef8d51e74c08 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1241.yaml @@ -54,8 +54,8 @@ examples: - | #include spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; adc@0 { compatible = "maxim,max1241"; diff --git a/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml b/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml index e04f09f35601..96f3f535fe34 100644 --- a/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml +++ b/Documentation/devicetree/bindings/iio/adc/maxim,max1363.yaml @@ -10,7 +10,7 @@ maintainers: - Jonathan Cameron description: | - Family of ADCs with i2c inteface, internal references and threshold + Family of ADCs with i2c interface, internal references and threshold monitoring. properties: diff --git a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml index 2c93fb41f172..f7b3fde4115a 100644 --- a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml +++ b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Marcus Folkesson %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/microchip,mcp3911.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip MCP3911 Dual channel analog front end (ADC) diff --git a/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml new file mode 100644 index 000000000000..dacc526dc695 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/nxp,imx93-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP iMX93 ADC + +maintainers: + - Haibo Chen + +description: + The ADC on iMX93 is a 8-channel 12-bit 1MS/s ADC with 4 channels + connected to pins. it support normal and inject mode, include + One-Shot and Scan (continuous) conversions. Programmable DMA + enables for each channel Also this ADC contain alternate analog + watchdog thresholds, select threshold through input ports. And + also has Self-test logic and Software-initiated calibration. + +properties: + compatible: + const: nxp,imx93-adc + + reg: + maxItems: 1 + + interrupts: + items: + - description: WDGnL, watchdog threshold interrupt requests. + - description: WDGnH, watchdog threshold interrupt requests. + - description: normal conversion, include EOC (End of Conversion), + ECH (End of Chain), JEOC (End of Injected Conversion) and + JECH (End of injected Chain). + - description: Self-testing Interrupts. + + clocks: + maxItems: 1 + + clock-names: + const: ipg + + vref-supply: + description: + The reference voltage which used to establish channel scaling. + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - vref-supply + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells = <1>; + #size-cells = <1>; + adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + vref-supply = <®_vref_1v8>; + #io-channel-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml index d186b713d6a7..58ea1ca4a5ee 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml @@ -160,7 +160,7 @@ examples: }; ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; - }; + }; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml index fa855baa368c..73def67fbe01 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.yaml @@ -20,6 +20,7 @@ properties: compatible: items: - enum: + - qcom,pm8226-iadc - qcom,pm8941-iadc - const: qcom,spmi-iadc @@ -49,7 +50,7 @@ additionalProperties: false examples: - | #include - spmi_bus { + spmi { #address-cells = <1>; #size-cells = <0>; pmic_iadc: adc@3600 { diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml index c8cbfd3444be..b3a626389870 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-rradc.yaml @@ -40,12 +40,12 @@ additionalProperties: false examples: - | pmic { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - pmic_rradc: adc@4500 { - compatible = "qcom,pmi8998-rradc"; - reg = <0x4500>; - #io-channel-cells = <1>; - }; + pmic_rradc: adc@4500 { + compatible = "qcom,pmi8998-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml index 8b743742a5f9..ba86c7b7d622 100644 --- a/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml @@ -69,7 +69,7 @@ required: patternProperties: "^channel@[0-7]$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml index 81c87295912c..582d0a03b814 100644 --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml @@ -52,7 +52,7 @@ properties: vdd-supply: true samsung,syscon-phandle: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (to access the ADC_PHY register on Exynos3250/4x12/5250/5420/5800). @@ -142,7 +142,7 @@ examples: pullup-ohm = <47000>; pulldown-ohm = <0>; io-channels = <&adc 4>; - }; + }; }; - | @@ -150,7 +150,7 @@ examples: adc@126c0000 { compatible = "samsung,exynos3250-adc"; - reg = <0x126C0000 0x100>; + reg = <0x126c0000 0x100>; interrupts = <0 137 0>; #io-channel-cells = <1>; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 1c340c95df16..995cbf8cefc6 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 ADC @@ -80,7 +80,7 @@ properties: description: Phandle to system configuration controller. It can be used to control the analog circuitry on stm32mp1. - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array interrupt-controller: true @@ -341,7 +341,7 @@ patternProperties: patternProperties: "^channel@([0-9]|1[0-9])$": type: object - $ref: "adc.yaml" + $ref: adc.yaml description: Represents the external channels which are connected to the ADC. properties: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml index 333744a2159c..474e35c49348 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stmpe-adc.yaml @@ -35,10 +35,8 @@ additionalProperties: false examples: - | - stmpe { - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */ - }; + adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0f>; /* dont use ADC CH3-0 */ }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml b/Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml new file mode 100644 index 000000000000..caaad777580c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,adc081c.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,adc081c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Single-channel I2C ADCs + +maintainers: + - Jonathan Cameron + - Lars-Peter Clausen + +description: | + Single-channel ADC supporting 8, 10, or 12-bit samples and high/low alerts. + +properties: + compatible: + enum: + - ti,adc081c + - ti,adc101c + - ti,adc121c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vref-supply: + description: + Regulator for the combined power supply and voltage reference + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - vref-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@52 { + compatible = "ti,adc081c"; + reg = <0x52>; + vref-supply = <®_2p5v>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml index 2c3c2cf2145c..2127d639a768 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads1015.yaml @@ -104,12 +104,12 @@ examples: #address-cells = <1>; #size-cells = <0>; channel@0 { - reg = <0>; + reg = <0>; }; channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <5>; + reg = <4>; + ti,gain = <3>; + ti,datarate = <5>; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml index 55c2c73626f4..890f125d422c 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads131e08.yaml @@ -77,7 +77,7 @@ required: patternProperties: "^channel@([0-7])$": - $ref: "adc.yaml" + $ref: adc.yaml type: object description: | Represents the external channels which are connected to the ADC. diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml new file mode 100644 index 000000000000..0d8d06afed8b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads7924.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI ADS7924 4 channels 12 bits I2C analog to digital converter + +maintainers: + - Hugo Villeneuve + +description: | + Texas Instruments ADS7924 4 channels 12 bits I2C analog to digital converter + + Specifications: + https://www.ti.com/lit/gpn/ads7924 + +properties: + compatible: + const: ti,ads7924 + + reg: + maxItems: 1 + + vref-supply: + description: + The regulator supply for the ADC reference voltage (AVDD) + + reset-gpios: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + +patternProperties: + "^channel@[0-3]+$": + $ref: adc.yaml + + description: | + Represents the external channels which are connected to the ADC. + + properties: + reg: + description: | + The channel number. It can have up to 4 channels numbered from 0 to 3. + items: + - minimum: 0 + maximum: 3 + + label: true + + required: + - reg + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - vref-supply + - "#address-cells" + - "#size-cells" + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@48 { + compatible = "ti,ads7924"; + reg = <0x48>; + vref-supply = <&ads7924_reg>; + reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + label = "CH0"; + }; + channel@1 { + reg = <1>; + label = "CH1"; + }; + channel@2 { + reg = <2>; + label = "CH2"; + }; + channel@3 { + reg = <3>; + label = "CH3"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml b/Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml new file mode 100644 index 000000000000..5fb65bf7749d --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,lmp92064.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments LMP92064 Precision Current and Voltage Sensor. + +maintainers: + - Leonard Göhrs + +description: | + The LMP92064 is a two channel ADC intended for combined voltage and current + measurements. + + The device contains two ADCs to allow simultaneous sampling of voltage and + current and thus of instantaneous power consumption. + +properties: + compatible: + enum: + - ti,lmp92064 + + reg: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the main part of the chip + + vdig-supply: + description: | + Regulator that provides power to the digital I/O part of the chip + + shunt-resistor-micro-ohms: + description: | + Value of the shunt resistor (in µΩ) connected between INCP and INCN, + across which current is measured. Used to provide correct scaling of the + raw ADC measurement. + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - shunt-resistor-micro-ohms + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + vdd-supply = <&vdd>; + vdig-supply = <&vdd>; + spi-max-frequency = <20000000>; + shunt-resistor-micro-ohms = <15000>; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml b/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml index bdf3bba2d750..866a05c9db36 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,tsc2046.yaml @@ -41,7 +41,7 @@ required: patternProperties: "^channel@[0-7]$": - $ref: "adc.yaml" + $ref: adc.yaml type: object properties: @@ -83,36 +83,36 @@ examples: #size-cells = <0>; channel@0 { - reg = <0>; + reg = <0>; }; channel@1 { - reg = <1>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@2 { - reg = <2>; + reg = <2>; }; channel@3 { - reg = <3>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@4 { - reg = <4>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@5 { - reg = <5>; - settling-time-us = <700>; - oversampling-ratio = <5>; + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; }; channel@6 { - reg = <6>; + reg = <6>; }; channel@7 { - reg = <7>; + reg = <7>; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index fee0f023a8c8..96340a05754c 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -192,26 +192,26 @@ additionalProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - ad3552r@0 { - compatible = "adi,ad3552r"; - reg = <0>; - spi-max-frequency = <20000000>; - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - adi,output-range-microvolt = <0 10000000>; - }; - channel@1 { - reg = <1>; - custom-output-range-config { - adi,gain-offset = <5>; - adi,gain-scaling-p-inv-log2 = <1>; - adi,gain-scaling-n-inv-log2 = <2>; - adi,rfb-ohms = <1>; - }; + #address-cells = <1>; + #size-cells = <0>; + ad3552r@0 { + compatible = "adi,ad3552r"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + adi,output-range-microvolt = <0 10000000>; + }; + channel@1 { + reg = <1>; + custom-output-range-config { + adi,gain-offset = <5>; + adi,gain-scaling-p-inv-log2 = <1>; + adi,gain-scaling-n-inv-log2 = <2>; + adi,rfb-ohms = <1>; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml index ff50c72c62b5..9eb9928500e2 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5380.yaml @@ -12,6 +12,7 @@ maintainers: description: | DAC devices supporting both SPI and I2C interfaces. + properties: compatible: enum: diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml index 13f214234b8e..b4400c52bec3 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml @@ -33,6 +33,7 @@ properties: - description: I2C devices enum: - adi,ad5311r + - adi,ad5337r - adi,ad5338r - adi,ad5671r - adi,ad5675r diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml index 3c8784a54d2c..212c936bab8d 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5766.yaml @@ -51,15 +51,15 @@ additionalProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - ad5766@0 { - compatible = "adi,ad5766"; - output-range-microvolts = <(-5000000) 5000000>; - reg = <0>; - spi-cpol; - spi-max-frequency = <1000000>; - reset-gpios = <&gpio 22 0>; - }; - }; + ad5766@0 { + compatible = "adi,ad5766"; + output-range-microvolts = <(-5000000) 5000000>; + reg = <0>; + spi-cpol; + spi-max-frequency = <1000000>; + reset-gpios = <&gpio 22 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml index 8e7da0de918f..82b0eed6a7b7 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5770r.yaml @@ -147,49 +147,49 @@ unevaluatedProperties: false examples: - | - spi { - #address-cells = <1>; - #size-cells = <0>; + spi { + #address-cells = <1>; + #size-cells = <0>; - ad5770r@0 { - compatible = "adi,ad5770r"; - reg = <0>; - spi-max-frequency = <1000000>; - vref-supply = <&vref>; - adi,external-resistor; - reset-gpios = <&gpio 22 0>; - #address-cells = <1>; - #size-cells = <0>; + ad5770r@0 { + compatible = "adi,ad5770r"; + reg = <0>; + spi-max-frequency = <1000000>; + vref-supply = <&vref>; + adi,external-resistor; + reset-gpios = <&gpio 22 0>; + #address-cells = <1>; + #size-cells = <0>; - channel@0 { - reg = <0>; - adi,range-microamp = <0 300000>; - }; + channel@0 { + reg = <0>; + adi,range-microamp = <0 300000>; + }; - channel@1 { - reg = <1>; - adi,range-microamp = <0 140000>; - }; + channel@1 { + reg = <1>; + adi,range-microamp = <0 140000>; + }; - channel@2 { - reg = <2>; - adi,range-microamp = <0 55000>; - }; + channel@2 { + reg = <2>; + adi,range-microamp = <0 55000>; + }; - channel@3 { - reg = <3>; - adi,range-microamp = <0 45000>; - }; + channel@3 { + reg = <3>; + adi,range-microamp = <0 45000>; + }; - channel@4 { - reg = <4>; - adi,range-microamp = <0 45000>; - }; + channel@4 { + reg = <4>; + adi,range-microamp = <0 45000>; + }; - channel@5 { - reg = <5>; - adi,range-microamp = <0 45000>; - }; - }; + channel@5 { + reg = <5>; + adi,range-microamp = <0 45000>; + }; }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml index 15cc6bf59b13..f22ef710ecde 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ltc2688.yaml @@ -116,32 +116,32 @@ examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - ltc2688: ltc2688@0 { - compatible = "adi,ltc2688"; - reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + ltc2688: ltc2688@0 { + compatible = "adi,ltc2688"; + reg = <0>; - vcc-supply = <&vcc>; - iovcc-supply = <&vcc>; - vref-supply = <&vref>; + vcc-supply = <&vcc>; + iovcc-supply = <&vcc>; + vref-supply = <&vref>; - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - adi,toggle-mode; - adi,overrange; - }; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + adi,toggle-mode; + adi,overrange; + }; - channel@1 { - reg = <1>; - adi,output-range-microvolt = <0 10000000>; + channel@1 { + reg = <1>; + adi,output-range-microvolt = <0 10000000>; - clocks = <&clock_tgp3>; - adi,toggle-dither-input = <2>; - }; - }; + clocks = <&clock_tgp3>; + adi,toggle-dither-input = <2>; + }; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml index 133b0f867992..c9f51d00fa8f 100644 --- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml +++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Marcus Folkesson %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/dac/lltc,ltc1660.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Linear Technology Micropower octal 8-Bit and 10-Bit DACs diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml index b1eb77335d05..733edc7d6d17 100644 --- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml +++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc2632.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/dac/lltc,ltc2632.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Linear Technology LTC263x 12-/10-/8-Bit Rail-to-Rail DAC @@ -64,14 +64,14 @@ examples: }; spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - dac@0 { - compatible = "lltc,ltc2632-l12"; - reg = <0>; /* CS0 */ - spi-max-frequency = <1000000>; - vref-supply = <&vref>; - }; + dac@0 { + compatible = "lltc,ltc2632-l12"; + reg = <0>; /* CS0 */ + spi-max-frequency = <1000000>; + vref-supply = <&vref>; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml b/Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml new file mode 100644 index 000000000000..24830f56c501 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/maxim,max5522.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/maxim,max5522.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX5522 Dual 10-bit Voltage-Output SPI DACs + +maintainers: + - Angelo Dureghello + - Jonathan Cameron + +description: | + Datasheet available at: + https://www.analog.com/en/products/max5522.html + +properties: + compatible: + const: maxim,max5522 + + reg: + maxItems: 1 + + vdd-supply: true + vrefin-supply: true + +required: + - compatible + - reg + - vrefin-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "maxim,max5522"; + reg = <0>; + vrefin-supply = <&vref>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 0f1bf1110122..04045b932bd2 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 DAC diff --git a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml index 88298bc43b81..79da0323c327 100644 --- a/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml +++ b/Documentation/devicetree/bindings/iio/dac/ti,dac5571.yaml @@ -46,7 +46,7 @@ examples: dac@4c { compatible = "ti,dac5571"; - reg = <0x4C>; + reg = <0x4c>; vref-supply = <&vdd_supply>; }; }; diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml index 0144f74a4768..1cb2adaf66f9 100644 --- a/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml +++ b/Documentation/devicetree/bindings/iio/frequency/adf4371.yaml @@ -53,16 +53,16 @@ unevaluatedProperties: false examples: - | - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; frequency@0 { - compatible = "adi,adf4371"; - reg = <0>; - spi-max-frequency = <1000000>; - clocks = <&adf4371_clkin>; - clock-names = "clkin"; + compatible = "adi,adf4371"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&adf4371_clkin>; + clock-names = "clkin"; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml b/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml index 0ae2464b9bc4..3d94dd4612c4 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/adi,adxrs290.yaml @@ -50,13 +50,13 @@ examples: #address-cells = <1>; #size-cells = <0>; gyro@0 { - compatible = "adi,adxrs290"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpol; - spi-cpha; - interrupt-parent = <&gpio>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; + compatible = "adi,adxrs290"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpol; + spi-cpha; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml b/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml index 2c900e9dddc6..297d519d68f2 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/nxp,fxas21002c.yaml @@ -65,34 +65,34 @@ examples: - | #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; gyroscope@20 { - compatible = "nxp,fxas21002c"; - reg = <0x20>; + compatible = "nxp,fxas21002c"; + reg = <0x20>; - vdd-supply = <®_peri_3p15v>; - vddio-supply = <®_peri_3p15v>; + vdd-supply = <®_peri_3p15v>; + vddio-supply = <®_peri_3p15v>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; }; }; - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; gyroscope@0 { - compatible = "nxp,fxas21002c"; - reg = <0x0>; + compatible = "nxp,fxas21002c"; + reg = <0x0>; - spi-max-frequency = <2000000>; + spi-max-frequency = <2000000>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; }; }; diff --git a/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml b/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml index 6c5ad426a016..b9b5beac33b2 100644 --- a/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml +++ b/Documentation/devicetree/bindings/iio/health/ti,afe4403.yaml @@ -42,7 +42,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - heart_mon@0 { + heart-mon@0 { compatible = "ti,afe4403"; reg = <0>; spi-max-frequency = <10000000>; diff --git a/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml b/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml index c0e815d9999e..2958c4ca75b4 100644 --- a/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml +++ b/Documentation/devicetree/bindings/iio/health/ti,afe4404.yaml @@ -39,7 +39,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - heart_mon@58 { + heart-mon@58 { compatible = "ti,afe4404"; reg = <0x58>; tx-supply = <&vbat>; diff --git a/Documentation/devicetree/bindings/iio/humidity/dht11.yaml b/Documentation/devicetree/bindings/iio/humidity/dht11.yaml index 2247481d0203..0103f4238942 100644 --- a/Documentation/devicetree/bindings/iio/humidity/dht11.yaml +++ b/Documentation/devicetree/bindings/iio/humidity/dht11.yaml @@ -34,7 +34,7 @@ additionalProperties: false examples: - | - humidity_sensor { + humidity-sensor { compatible = "dht11"; gpios = <&gpio0 6 0>; }; diff --git a/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml b/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml index 88384b69f917..a2bc1fa92da0 100644 --- a/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml +++ b/Documentation/devicetree/bindings/iio/humidity/ti,hdc2010.yaml @@ -35,12 +35,12 @@ additionalProperties: false examples: - | - i2c0 { - #address-cells = <1>; - #size-cells = <0>; + i2c { + #address-cells = <1>; + #size-cells = <0>; - humidity@40 { - compatible = "ti,hdc2010"; - reg = <0x40>; - }; + humidity@40 { + compatible = "ti,hdc2010"; + reg = <0x40>; + }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml index d166dbca18c3..4e43c80e5119 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml @@ -42,7 +42,7 @@ examples: - | #include #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml index 5dbfae80bb28..c73533c54588 100644 --- a/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml +++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16475.yaml @@ -114,17 +114,17 @@ examples: - | #include spi { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - adis16475: adis16475-3@0 { - compatible = "adi,adis16475-3"; - reg = <0>; - spi-cpha; - spi-cpol; - spi-max-frequency = <2000000>; - interrupts = <4 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio>; - }; + adis16475: adis16475-3@0 { + compatible = "adi,adis16475-3"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <2000000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml index a0760382548d..47cfba939ca6 100644 --- a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml +++ b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml @@ -64,16 +64,16 @@ examples: #size-cells = <0>; bmi160@68 { - compatible = "bosch,bmi160"; - reg = <0x68>; - vdd-supply = <&pm8916_l17>; - vddio-supply = <&pm8916_l6>; - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; - mount-matrix = "0", "1", "0", - "-1", "0", "0", - "0", "0", "1"; + compatible = "bosch,bmi160"; + reg = <0x68>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; }; }; - | @@ -84,11 +84,11 @@ examples: #size-cells = <0>; bmi160@0 { - compatible = "bosch,bmi160"; - reg = <0>; - spi-max-frequency = <10000000>; - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; + compatible = "bosch,bmi160"; + reg = <0>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml index 13c9abdd3131..7cd05bcbee31 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml @@ -65,35 +65,35 @@ examples: - | #include #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; icm42605@68 { - compatible = "invensense,icm42605"; - reg = <0x68>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&vdd>; - vddio-supply = <&vddio>; + compatible = "invensense,icm42605"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; }; }; - | #include #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; icm42602@0 { - compatible = "invensense,icm42602"; - reg = <0>; - spi-max-frequency = <24000000>; - spi-cpha; - spi-cpol; - interrupt-parent = <&gpio1>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; - vdd-supply = <&vdd>; - vddio-supply = <&vddio>; + compatible = "invensense,icm42602"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-cpha; + spi-cpol; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vdd>; + vddio-supply = <&vddio>; }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml index 24416b59b782..688100b240bc 100644 --- a/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml +++ b/Documentation/devicetree/bindings/iio/imu/nxp,fxos8700.yaml @@ -49,33 +49,33 @@ examples: - | #include #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; + compatible = "nxp,fxos8700"; + reg = <0x1e>; - interrupt-parent = <&gpio2>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; }; }; - | #include #include - spi0 { + spi { #address-cells = <1>; #size-cells = <0>; fxos8700@0 { - compatible = "nxp,fxos8700"; - reg = <0>; + compatible = "nxp,fxos8700"; + reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio1>; - interrupts = <7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT2"; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; }; }; diff --git a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml index 68b481c63318..decf022335d8 100644 --- a/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml +++ b/Documentation/devicetree/bindings/iio/imu/st,lsm6dsx.yaml @@ -63,7 +63,7 @@ properties: description: if defined provides VDD IO power to the sensor. st,drdy-int-pin: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | The pin on the package that will be used to signal data ready enum: diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml b/Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml new file mode 100644 index 000000000000..121d540b7b6e --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/ti,tmag5273.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor + +maintainers: + - Gerald Loacker + +description: + The TI TMAG5273 is a low-power linear 3D Hall-effect sensor. This device + integrates three independent Hall-effect sensors in the X, Y, and Z axes. + The device has an integrated temperature sensor available. The TMAG5273 + can be configured through the I2C interface to enable any combination of + magnetic axes and temperature measurements. An integrated angle calculation + engine (CORDIC) provides full 360° angular position information for both + on-axis and off-axis angle measurement topologies. The angle calculation is + performed using two user-selected magnetic axes. + +properties: + compatible: + const: ti,tmag5273 + + reg: + maxItems: 1 + + "#io-channel-cells": + const: 1 + + ti,angle-measurement: + $ref: /schemas/types.yaml#/definitions/string + description: + Enables angle measurement in the selected plane. + If not specified, "x-y" will be anables as default. + enum: + - off + - x-y + - y-z + - x-z + + vcc-supply: + description: + A regulator providing 1.7 V to 3.6 V supply voltage on the VCC pin, + typically 3.3 V. + + interrupts: + description: + The low active interrupt can be configured to be fixed width or latched. + Interrupt events can be configured to be generated from magnetic + thresholds or when a conversion is completed. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@35 { + compatible = "ti,tmag5273"; + reg = <0x35>; + #io-channel-cells = <1>; + ti,angle-measurement = "x-z"; + vcc-supply = <&vcc3v3>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml b/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml index 9438fffaf0ba..877226e9219b 100644 --- a/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml +++ b/Documentation/devicetree/bindings/iio/magnetometer/yamaha,yas530.yaml @@ -91,12 +91,12 @@ examples: #size-cells = <0>; magnetometer@2e { - compatible = "yamaha,yas530"; - reg = <0x2e>; - vdd-supply = <&ldo1_reg>; - iovdd-supply = <&ldo2_reg>; - reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - interrupts = <13 IRQ_TYPE_EDGE_RISING>; + compatible = "yamaha,yas530"; + reg = <0x2e>; + vdd-supply = <&ldo1_reg>; + iovdd-supply = <&ldo2_reg>; + reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + interrupts = <13 IRQ_TYPE_EDGE_RISING>; }; }; @@ -105,8 +105,8 @@ examples: #size-cells = <0>; magnetometer@2e { - compatible = "yamaha,yas539"; - reg = <0x2e>; - vdd-supply = <&ldo1_reg>; + compatible = "yamaha,yas539"; + reg = <0x2e>; + vdd-supply = <&ldo1_reg>; }; }; diff --git a/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml b/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml index 0ebb6725a1af..b8d7083c97f8 100644 --- a/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml +++ b/Documentation/devicetree/bindings/iio/potentiometer/adi,ad5272.yaml @@ -44,7 +44,7 @@ examples: potentiometer@2f { compatible = "adi,ad5272-020"; - reg = <0x2F>; + reg = <0x2f>; reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; }; }; diff --git a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml index 1f9fe15b4b3c..9fb8d773efa3 100644 --- a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml @@ -39,7 +39,7 @@ examples: - | #include - i2c0 { + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml index 72cd2c2d3f17..63885af6a74b 100644 --- a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml +++ b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml @@ -60,16 +60,16 @@ examples: - | #include #include - i2c0 { - #address-cells = <1>; - #size-cells = <0>; - pressure@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - vddd-supply = <&foo>; - vdda-supply = <&bar>; - }; + i2c { + #address-cells = <1>; + #size-cells = <0>; + pressure@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + interrupt-parent = <&gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + vddd-supply = <&foo>; + vdda-supply = <&bar>; + }; }; diff --git a/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml b/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml index 710d3b9a86d9..c999994e19e3 100644 --- a/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/ams,as3935.yaml @@ -60,7 +60,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - lightning@0 { + lightning@0 { compatible = "ams,as3935"; reg = <0>; spi-max-frequency = <400000>; diff --git a/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml b/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml index 00e3b59641d2..d4e09d2dcd21 100644 --- a/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/google,cros-ec-mkbp-proximity.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml index f088c5d2be99..ad0bb44f41b6 100644 --- a/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml @@ -36,7 +36,7 @@ properties: const: 1 semtech,resolution: - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32 enum: [8, 16, 32, 64, 128, 256, 512, 1024] description: Capacitance measurement resolution. For both phases, "reference" and diff --git a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml index 250439b13152..c6201976378f 100644 --- a/Documentation/devicetree/bindings/iio/st,st-sensors.yaml +++ b/Documentation/devicetree/bindings/iio/st,st-sensors.yaml @@ -39,6 +39,7 @@ properties: - st,lis3lv02dl-accel - st,lng2dm-accel - st,lsm303agr-accel + - st,lsm303c-accel - st,lsm303dl-accel - st,lsm303dlh-accel - st,lsm303dlhc-accel @@ -66,6 +67,7 @@ properties: - st,lis2mdl - st,lis3mdl-magn - st,lsm303agr-magn + - st,lsm303c-magn - st,lsm303dlh-magn - st,lsm303dlhc-magn - st,lsm303dlm-magn diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml index b69813f281da..f44fc32ce87e 100644 --- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml @@ -472,75 +472,74 @@ examples: #size-cells = <0>; temperature-sensor@0 { - compatible = "adi,ltc2983"; - reg = <0>; + compatible = "adi,ltc2983"; + reg = <0>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - interrupts = <20 IRQ_TYPE_EDGE_RISING>; - interrupt-parent = <&gpio>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; - thermocouple@18 { - reg = <18>; - adi,sensor-type = <8>; //Type B - adi,sensor-oc-current-microamp = <10>; - adi,cold-junction-handle = <&diode5>; - }; + thermocouple@18 { + reg = <18>; + adi,sensor-type = <8>; //Type B + adi,sensor-oc-current-microamp = <10>; + adi,cold-junction-handle = <&diode5>; + }; - diode5: diode@5 { - reg = <5>; - adi,sensor-type = <28>; - }; + diode5: diode@5 { + reg = <5>; + adi,sensor-type = <28>; + }; - rsense2: rsense@2 { - reg = <2>; - adi,sensor-type = <29>; - adi,rsense-val-milli-ohms = <1200000>; //1.2Kohms - }; + rsense2: rsense@2 { + reg = <2>; + adi,sensor-type = <29>; + adi,rsense-val-milli-ohms = <1200000>; //1.2Kohms + }; - rtd@14 { - reg = <14>; - adi,sensor-type = <15>; //PT1000 - /*2-wire, internal gnd, no current rotation*/ - adi,number-of-wires = <2>; - adi,rsense-share; - adi,excitation-current-microamp = <500>; - adi,rsense-handle = <&rsense2>; - }; + rtd@14 { + reg = <14>; + adi,sensor-type = <15>; //PT1000 + /*2-wire, internal gnd, no current rotation*/ + adi,number-of-wires = <2>; + adi,rsense-share; + adi,excitation-current-microamp = <500>; + adi,rsense-handle = <&rsense2>; + }; - adc@10 { - reg = <10>; - adi,sensor-type = <30>; - adi,single-ended; - }; + adc@10 { + reg = <10>; + adi,sensor-type = <30>; + adi,single-ended; + }; - thermistor@12 { - reg = <12>; - adi,sensor-type = <26>; //Steinhart - adi,rsense-handle = <&rsense2>; - adi,custom-steinhart = <0x00F371EC 0x12345678 - 0x2C0F8733 0x10018C66 0xA0FEACCD - 0x90021D99>; //6 entries - }; - - thermocouple@20 { - reg = <20>; - adi,sensor-type = <9>; //custom thermocouple - adi,single-ended; - adi,custom-thermocouple = - /bits/ 64 <(-50220000) 0>, - /bits/ 64 <(-30200000) 99100000>, - /bits/ 64 <(-5300000) 135400000>, - /bits/ 64 <0 273150000>, - /bits/ 64 <40200000 361200000>, - /bits/ 64 <55300000 522100000>, - /bits/ 64 <88300000 720300000>, - /bits/ 64 <132200000 811200000>, - /bits/ 64 <188700000 922500000>, - /bits/ 64 <460400000 1000000000>; //10 pairs - }; + thermistor@12 { + reg = <12>; + adi,sensor-type = <26>; //Steinhart + adi,rsense-handle = <&rsense2>; + adi,custom-steinhart = <0x00f371ec 0x12345678 + 0x2c0f8733 0x10018c66 0xa0feaccd + 0x90021d99>; //6 entries + }; + thermocouple@20 { + reg = <20>; + adi,sensor-type = <9>; //custom thermocouple + adi,single-ended; + adi,custom-thermocouple = + /bits/ 64 <(-50220000) 0>, + /bits/ 64 <(-30200000) 99100000>, + /bits/ 64 <(-5300000) 135400000>, + /bits/ 64 <0 273150000>, + /bits/ 64 <40200000 361200000>, + /bits/ 64 <55300000 522100000>, + /bits/ 64 <88300000 720300000>, + /bits/ 64 <132200000 811200000>, + /bits/ 64 <188700000 922500000>, + /bits/ 64 <460400000 1000000000>; //10 pairs + }; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml b/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml index a2823ed6867b..7cc365e0ebc8 100644 --- a/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/maxim,max31865.yaml @@ -43,12 +43,12 @@ examples: #address-cells = <1>; #size-cells = <0>; - temp_sensor@0 { - compatible = "maxim,max31865"; - reg = <0>; - spi-max-frequency = <400000>; - spi-cpha; - maxim,3-wire; + temperature-sensor@0 { + compatible = "maxim,max31865"; + reg = <0>; + spi-max-frequency = <400000>; + spi-cpha; + maxim,3-wire; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml index 347bc16a4671..c4f1c69f9330 100644 --- a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# -title: "TI TMP117 - Digital temperature sensor with integrated NV memory" +title: TI TMP117 - Digital temperature sensor with integrated NV memory description: | TI TMP117 - Digital temperature sensor with integrated NV memory that supports diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 0c720dbde36e..12a0d3ecbabb 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -27,11 +27,13 @@ properties: - qcom,sc7280-cpu-bwmon - qcom,sc8280xp-cpu-bwmon - qcom,sdm845-bwmon + - qcom,sm8550-cpu-bwmon - const: qcom,msm8998-bwmon - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: - qcom,sc8280xp-llcc-bwmon + - qcom,sm8550-llcc-bwmon - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index aadae4424ba9..576992a6dc5a 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -22,6 +22,7 @@ properties: - qcom,sc7180-osm-l3 - qcom,sc8180x-osm-l3 - qcom,sdm845-osm-l3 + - qcom,sm6350-osm-l3 - qcom,sm8150-osm-l3 - const: qcom,osm-l3 - items: diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 5e6be4e79201..d9d243c5514b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -62,6 +62,37 @@ properties: power-domains: maxItems: 1 +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + snoc-mm is a child of snoc, sharing snoc's register address space. + + properties: + compatible: + enum: + - qcom,msm8939-snoc-mm + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: bus + - const: bus_a + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + + required: + - compatible + - '#interconnect-cells' + - clock-names + - clocks + required: - compatible - reg @@ -108,37 +139,6 @@ allOf: - description: Bus Clock - description: Bus A Clock - # Child node's properties - patternProperties: - '^interconnect-[a-z0-9]+$': - type: object - description: - snoc-mm is a child of snoc, sharing snoc's register address space. - - properties: - compatible: - enum: - - qcom,msm8939-snoc-mm - - '#interconnect-cells': - const: 1 - - clock-names: - items: - - const: bus - - const: bus_a - - clocks: - items: - - description: Bus Clock - - description: Bus A Clock - - required: - - compatible - - '#interconnect-cells' - - clock-names - - clocks - - if: properties: compatible: @@ -237,6 +237,17 @@ allOf: - description: Aggregate2 USB3 AXI Clock. - description: Config NoC USB2 AXI Clock. + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,msm8939-snoc + then: + patternProperties: + '^interconnect-[a-z0-9]+$': false + examples: - | #include diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index a429a1ed1006..4d93ad415e0b 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -39,18 +39,6 @@ properties: - qcom,sc7180-npu-noc - qcom,sc7180-qup-virt - qcom,sc7180-system-noc - - qcom,sc7280-aggre1-noc - - qcom,sc7280-aggre2-noc - - qcom,sc7280-clk-virt - - qcom,sc7280-cnoc2 - - qcom,sc7280-cnoc3 - - qcom,sc7280-dc-noc - - qcom,sc7280-gem-noc - - qcom,sc7280-lpass-ag-noc - - qcom,sc7280-mc-virt - - qcom,sc7280-mmss-noc - - qcom,sc7280-nsp-noc - - qcom,sc7280-system-noc - qcom,sc8180x-aggre1-noc - qcom,sc8180x-aggre2-noc - qcom,sc8180x-camnoc-virt @@ -58,23 +46,18 @@ properties: - qcom,sc8180x-config-noc - qcom,sc8180x-dc-noc - qcom,sc8180x-gem-noc - - qcom,sc8180x-ipa-virt - qcom,sc8180x-mc-virt - qcom,sc8180x-mmss-noc - qcom,sc8180x-qup-virt - qcom,sc8180x-system-noc - - qcom,sc8280xp-aggre1-noc - - qcom,sc8280xp-aggre2-noc - - qcom,sc8280xp-clk-virt - - qcom,sc8280xp-config-noc - - qcom,sc8280xp-dc-noc - - qcom,sc8280xp-gem-noc - - qcom,sc8280xp-lpass-ag-noc - - qcom,sc8280xp-mc-virt - - qcom,sc8280xp-mmss-noc - - qcom,sc8280xp-nspa-noc - - qcom,sc8280xp-nspb-noc - - qcom,sc8280xp-system-noc + - qcom,sdm670-aggre1-noc + - qcom,sdm670-aggre2-noc + - qcom,sdm670-config-noc + - qcom,sdm670-dc-noc + - qcom,sdm670-gladiator-noc + - qcom,sdm670-mem-noc + - qcom,sdm670-mmss-noc + - qcom,sdm670-system-noc - qcom,sdm845-aggre1-noc - qcom,sdm845-aggre2-noc - qcom,sdm845-config-noc @@ -96,7 +79,6 @@ properties: - qcom,sm8150-config-noc - qcom,sm8150-dc-noc - qcom,sm8150-gem-noc - - qcom,sm8150-ipa-virt - qcom,sm8150-mc-virt - qcom,sm8150-mmss-noc - qcom,sm8150-system-noc @@ -106,7 +88,6 @@ properties: - qcom,sm8250-config-noc - qcom,sm8250-dc-noc - qcom,sm8250-gem-noc - - qcom,sm8250-ipa-virt - qcom,sm8250-mc-virt - qcom,sm8250-mmss-noc - qcom,sm8250-npu-noc @@ -121,17 +102,6 @@ properties: - qcom,sm8350-mmss-noc - qcom,sm8350-compute-noc - qcom,sm8350-system-noc - - qcom,sm8450-aggre1-noc - - qcom,sm8450-aggre2-noc - - qcom,sm8450-clk-virt - - qcom,sm8450-config-noc - - qcom,sm8450-gem-noc - - qcom,sm8450-lpass-ag-noc - - qcom,sm8450-mc-virt - - qcom,sm8450-mmss-noc - - qcom,sm8450-nsp-noc - - qcom,sm8450-pcie-anoc - - qcom,sm8450-system-noc '#interconnect-cells': true diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml new file mode 100644 index 000000000000..2e0c0bc7a376 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sa8775p-rpmh.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sa8775p-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SA8775P + +maintainers: + - Bartosz Golaszewski + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sa8775p.h + +properties: + compatible: + enum: + - qcom,sa8775p-aggre1-noc + - qcom,sa8775p-aggre2-noc + - qcom,sa8775p-clk-virt + - qcom,sa8775p-config-noc + - qcom,sa8775p-dc-noc + - qcom,sa8775p-gem-noc + - qcom,sa8775p-gpdsp-anoc + - qcom,sa8775p-lpass-ag-noc + - qcom,sa8775p-mc-virt + - qcom,sa8775p-mmss-noc + - qcom,sa8775p-nspa-noc + - qcom,sa8775p-nspb-noc + - qcom,sa8775p-pcie-anoc + - qcom,sa8775p-system-noc + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + +unevaluatedProperties: false + +examples: + - | + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sa8775p-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml new file mode 100644 index 000000000000..b135597d9489 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sc7280-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SC7280 + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sc7280.h + +properties: + compatible: + enum: + - qcom,sc7280-aggre1-noc + - qcom,sc7280-aggre2-noc + - qcom,sc7280-clk-virt + - qcom,sc7280-cnoc2 + - qcom,sc7280-cnoc3 + - qcom,sc7280-dc-noc + - qcom,sc7280-gem-noc + - qcom,sc7280-lpass-ag-noc + - qcom,sc7280-mc-virt + - qcom,sc7280-mmss-noc + - qcom,sc7280-nsp-noc + - qcom,sc7280-system-noc + + reg: + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-clk-virt + then: + properties: + reg: false + else: + required: + - reg + +unevaluatedProperties: false + +examples: + - | + interconnect { + compatible = "qcom,sc7280-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@9100000 { + reg = <0x9100000 0xe2200>; + compatible = "qcom,sc7280-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml new file mode 100644 index 000000000000..6c2da03f0cd2 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sc8280xp-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SC8280XP + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sc8280xp.h + +properties: + compatible: + enum: + - qcom,sc8280xp-aggre1-noc + - qcom,sc8280xp-aggre2-noc + - qcom,sc8280xp-clk-virt + - qcom,sc8280xp-config-noc + - qcom,sc8280xp-dc-noc + - qcom,sc8280xp-gem-noc + - qcom,sc8280xp-lpass-ag-noc + - qcom,sc8280xp-mc-virt + - qcom,sc8280xp-mmss-noc + - qcom,sc8280xp-nspa-noc + - qcom,sc8280xp-nspb-noc + - qcom,sc8280xp-system-noc + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + +unevaluatedProperties: false + +examples: + - | + interconnect-0 { + compatible = "qcom,sc8280xp-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml new file mode 100644 index 000000000000..3cff7e662255 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm8450-rpmh.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450 + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). + + See also:: include/dt-bindings/interconnect/qcom,sm8450.h + +properties: + compatible: + enum: + - qcom,sm8450-aggre1-noc + - qcom,sm8450-aggre2-noc + - qcom,sm8450-clk-virt + - qcom,sm8450-config-noc + - qcom,sm8450-gem-noc + - qcom,sm8450-lpass-ag-noc + - qcom,sm8450-mc-virt + - qcom,sm8450-mmss-noc + - qcom,sm8450-nsp-noc + - qcom,sm8450-pcie-anoc + - qcom,sm8450-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-clk-virt + - qcom,sm8450-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe 0 AXI clock + - description: aggre-NOC PCIe 1 AXI clock + - description: aggre UFS PHY AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8450-aggre1-noc + - qcom,sm8450-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + + interconnect-0 { + compatible = "qcom,sm8450-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@1700000 { + compatible = "qcom,sm8450-aggre2-noc"; + reg = <0x01700000 0x31080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml b/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml index ad9ed596dfef..5e26e48c7217 100644 --- a/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml +++ b/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml @@ -196,6 +196,8 @@ properties: maxItems: 2 operating-points-v2: true + opp-table: + type: object samsung,data-clock-ratio: $ref: /schemas/types.yaml#/definitions/uint32 @@ -227,6 +229,31 @@ examples: operating-points-v2 = <&bus_dmc_opp_table>; devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; vdd-supply = <&buck1_reg>; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; }; ppmu_dmc0: ppmu@106a0000 { diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml new file mode 100644 index 000000000000..1b6020e4ec27 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-inject.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Inject IP + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Inject core provides functional fault + injection by changing selected MicroBlaze instructions, which provides the + possibility to verify that the TMR subsystem error detection and fault + recovery logic is working properly. + +properties: + compatible: + enum: + - xlnx,tmr-inject-1.0 + + reg: + maxItems: 1 + + xlnx,magic: + minimum: 0 + maximum: 255 + description: | + Magic number, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic + +additionalProperties: false + +examples: + - | + fault-inject@44a30000 { + compatible = "xlnx,tmr-inject-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic = <0x46>; + }; diff --git a/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml new file mode 100644 index 000000000000..27de12147a52 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,tmr-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Triple Modular Redundancy(TMR) Manager IP + +maintainers: + - Appana Durga Kedareswara rao + +description: | + The Triple Modular Redundancy(TMR) Manager is responsible for handling the + TMR subsystem state, including fault detection and error recovery. The core + is triplicated in each of the sub-blocks in the TMR subsystem, and provides + majority voting of its internal state. + +properties: + compatible: + enum: + - xlnx,tmr-manager-1.0 + + reg: + maxItems: 1 + + xlnx,magic1: + minimum: 0 + maximum: 255 + description: + Magic byte 1, When configured it allows the controller to perform + recovery. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - xlnx,magic1 + +additionalProperties: false + +examples: + - | + tmr-manager@44a10000 { + compatible = "xlnx,tmr-manager-1.0"; + reg = <0x44a10000 0x10000>; + xlnx,magic1 = <0x46>; + }; diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 8e89b15b535f..2173fe82317d 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -19,16 +19,21 @@ properties: - qcom,apq8064-qfprom - qcom,apq8084-qfprom - qcom,ipq8064-qfprom - - qcom,msm8974-qfprom + - qcom,ipq8074-qfprom - qcom,msm8916-qfprom + - qcom,msm8974-qfprom + - qcom,msm8976-qfprom - qcom,msm8996-qfprom - qcom,msm8998-qfprom - qcom,qcs404-qfprom - qcom,sc7180-qfprom - qcom,sc7280-qfprom - qcom,sdm630-qfprom + - qcom,sdm670-qfprom - qcom,sdm845-qfprom - qcom,sm6115-qfprom + - qcom,sm8150-qfprom + - qcom,sm8250-qfprom - const: qcom,qfprom reg: diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 34b8e59aa9d4..c55865fd371a 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -62,7 +62,6 @@ properties: - const: mrvl,pxa-uart - const: nuvoton,wpcm450-uart - const: nuvoton,npcm750-uart - - const: nuvoton,npcm845-uart - const: nvidia,tegra20-uart - const: nxp,lpc3220-uart - items: @@ -92,6 +91,10 @@ properties: - enum: - ns16550 # Deprecated, unless the FIFO really is broken - ns16550a + - items: + - enum: + - nuvoton,npcm845-uart + - const: nuvoton,npcm750-uart - items: - enum: - ralink,mt7620a-uart @@ -200,12 +203,13 @@ properties: deprecated: true aspeed,lpc-io-reg: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 description: | The VUART LPC address. Only applicable to aspeed,ast2500-vuart. aspeed,lpc-interrupts: - $ref: "/schemas/types.yaml#/definitions/uint32-array" + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 maxItems: 2 description: | diff --git a/Documentation/devicetree/bindings/serial/8250_omap.yaml b/Documentation/devicetree/bindings/serial/8250_omap.yaml index 53dc1212ad2e..eb3488d8f9ee 100644 --- a/Documentation/devicetree/bindings/serial/8250_omap.yaml +++ b/Documentation/devicetree/bindings/serial/8250_omap.yaml @@ -70,11 +70,6 @@ properties: dsr-gpios: true rng-gpios: true dcd-gpios: true - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - rs485-rts-active-high: true - linux,rs485-enabled-at-boot-time: true rts-gpio: true power-domains: true clock-frequency: true @@ -109,12 +104,12 @@ else: examples: - | - serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - dmas = <&sdma 81 &sdma 82>; - dma-names = "tx", "rx"; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - }; + serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml index 7822705ad16c..3cbdde85ed71 100644 --- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml +++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml @@ -19,6 +19,9 @@ description: | is active since power-on and does not need any clock gating and is usable as very early serial console. +allOf: + - $ref: serial.yaml# + properties: compatible: oneOf: @@ -69,14 +72,14 @@ required: - clocks - clock-names -additionalProperties: false +unevaluatedProperties: false examples: - | serial@84c0 { - compatible = "amlogic,meson-gx-uart"; - reg = <0x84c0 0x14>; - interrupts = <26>; - clocks = <&xtal>, <&pclk>, <&xtal>; - clock-names = "xtal", "pclk", "baud"; + compatible = "amlogic,meson-gx-uart"; + reg = <0x84c0 0x14>; + interrupts = <26>; + clocks = <&xtal>, <&pclk>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml index 876b8cf1cafb..a8b323d7bf94 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -9,9 +9,6 @@ title: Cadence UART Controller maintainers: - Michal Simek -allOf: - - $ref: /schemas/serial.yaml# - properties: compatible: oneOf: @@ -46,6 +43,9 @@ properties: port does not use this pin. type: boolean + power-domains: + maxItems: 1 + required: - compatible - reg @@ -53,14 +53,25 @@ required: - clocks - clock-names +allOf: + - $ref: serial.yaml# + - if: + properties: + compatible: + contains: + const: cdns,uart-r1p8 + then: + properties: + power-domains: false + unevaluatedProperties: false examples: - | uart0: serial@e0000000 { - compatible = "xlnx,xuartps", "cdns,uart-r1p8"; - clocks = <&clkc 23>, <&clkc 40>; - clock-names = "uart_clk", "pclk"; - reg = <0xE0000000 0x1000>; - interrupts = <0 27 4>; + compatible = "xlnx,xuartps", "cdns,uart-r1p8"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "uart_clk", "pclk"; + reg = <0xe0000000 0x1000>; + interrupts = <0 27 4>; }; diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml index 8b643bae3c7b..920539926d7e 100644 --- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml @@ -16,7 +16,7 @@ maintainers: - Chester Lin allOf: - - $ref: "serial.yaml" + - $ref: serial.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml index 9d949296a142..4cbe76e1715b 100644 --- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml @@ -10,8 +10,8 @@ maintainers: - Fabio Estevam allOf: - - $ref: "serial.yaml" - - $ref: "rs485.yaml" + - $ref: serial.yaml# + - $ref: rs485.yaml# properties: compatible: @@ -83,13 +83,6 @@ properties: are sensible for most use cases. If you need low latency processing on slow connections this needs to be configured appropriately. - uart-has-rtscts: true - - rs485-rts-delay: true - rs485-rts-active-low: true - rs485-rx-during-tx: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index 74f75f669e77..ab81722293d3 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -10,7 +10,8 @@ maintainers: - Fugang Duan allOf: - - $ref: "rs485.yaml" + - $ref: rs485.yaml# + - $ref: serial.yaml# properties: compatible: @@ -64,9 +65,6 @@ properties: - const: rx - const: tx - rs485-rts-active-low: true - linux,rs485-enabled-at-boot-time: true - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml index 14c7594c88c6..6a400a5e6fc7 100644 --- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml @@ -10,7 +10,7 @@ maintainers: - Fabio Estevam allOf: - - $ref: "serial.yaml" + - $ref: serial.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml index 80af72859876..9571041030b7 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml @@ -10,6 +10,7 @@ maintainers: - Rob Herring allOf: + - $ref: /schemas/arm/primecell.yaml# - $ref: serial.yaml# # Need a custom select here or 'arm,primecell' will match on lots of nodes diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt deleted file mode 100644 index ce8c90161959..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* MSM Serial UART - -The MSM serial UART hardware is designed for low-speed use cases where a -dma-engine isn't needed. From a software perspective it's mostly compatible -with the MSM serial UARTDM except that it only supports reading and writing one -character at a time. - -Required properties: -- compatible: Should contain "qcom,msm-uart" -- reg: Should contain UART register location and length. -- interrupts: Should contain UART interrupt. -- clocks: Should contain the core clock. -- clock-names: Should be "core". - -Example: - -A uart device at 0xa9c00000 with interrupt 11. - -serial@a9c00000 { - compatible = "qcom,msm-uart"; - reg = <0xa9c00000 0x1000>; - interrupts = <11>; - clocks = <&uart_cxc>; - clock-names = "core"; -}; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml new file mode 100644 index 000000000000..a052aaef21f4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM SoC Serial UART + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The MSM serial UART hardware is designed for low-speed use cases where a + dma-engine isn't needed. From a software perspective it's mostly compatible + with the MSM serial UARTDM except that it only supports reading and writing + one character at a time. + +properties: + compatible: + const: qcom,msm-uart + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +unevaluatedProperties: false + +allOf: + - $ref: /schemas/serial/serial.yaml# + +examples: + - | + serial@a9c00000 { + compatible = "qcom,msm-uart"; + reg = <0xa9c00000 0x1000>; + interrupts = <11>; + clocks = <&uart_cxc>; + clock-names = "core"; + }; diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml index b25aca733b72..12d0fa34f9f9 100644 --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -66,9 +66,9 @@ examples: - | #include uart0: serial@e1020000 { - compatible = "renesas,em-uart"; - reg = <0xe1020000 0x38>; - interrupts = ; - clocks = <&usia_u0_sclk>; - clock-names = "sclk"; + compatible = "renesas,em-uart"; + reg = <0xe1020000 0x38>; + interrupts = ; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml index 1957b9d782e8..afedb6edfc34 100644 --- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -131,20 +131,20 @@ examples: #include #include aliases { - serial1 = &hscif1; + serial1 = &hscif1; }; hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0xe6550000 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; - uart-has-rtscts; + compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0xe6550000 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + uart-has-rtscts; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml index bf7708a7a2c0..dc445b327e0b 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml @@ -91,19 +91,19 @@ examples: #include aliases { - serial0 = &sci0; + serial0 = &sci0; }; sci0: serial@1004d000 { - compatible = "renesas,r9a07g044-sci", "renesas,sci"; - reg = <0x1004d000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "eri", "rxi", "txi", "tei"; - clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; - clock-names = "fck"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_SCI0_RST>; + compatible = "renesas,r9a07g044-sci", "renesas,sci"; + reg = <0x1004d000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_SCI0_RST>; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index f81f2d67a1ed..1989bd67d04e 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -180,19 +180,19 @@ examples: #include #include aliases { - serial0 = &scif0; + serial0 = &scif0; }; scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", - "renesas,scif"; - reg = <0xe6e60000 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - resets = <&cpg 721>; + compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0xe6e60000 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml index 3c67d3202e1b..4c3b5e7270da 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml @@ -95,18 +95,18 @@ examples: #include #include aliases { - serial0 = &scifa0; + serial0 = &scifa0; }; scifa0: serial@e6c40000 { - compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", - "renesas,scifa"; - reg = <0xe6c40000 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 204>; - dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; - dma-names = "tx", "rx", "tx", "rx"; + compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa", + "renesas,scifa"; + reg = <0xe6c40000 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; }; diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml index d5571c7a4424..2f7cbbb48960 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml @@ -94,10 +94,10 @@ examples: #include #include scifb: serial@e6c30000 { - compatible = "renesas,scifb-r8a7740", "renesas,scifb"; - reg = <0xe6c30000 0x100>; - interrupts = ; - clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; - clock-names = "fck"; - power-domains = <&pd_a3sp>; + compatible = "renesas,scifb-r8a7740", "renesas,scifb"; + reg = <0xe6c30000 0x100>; + interrupts = ; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "fck"; + power-domains = <&pd_a3sp>; }; diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 789763cf427a..303a443d9e29 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -51,6 +51,12 @@ properties: description: GPIO pin to enable RS485 bus termination. maxItems: 1 + rs485-rx-during-tx-gpios: + description: Output GPIO pin that sets the state of rs485-rx-during-tx. This + signal can be used to control the RX part of an RS485 transceiver. Thereby + the active state enables RX during TX. + maxItems: 1 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml index 11e822bf09e2..e05ad3ac2abc 100644 --- a/Documentation/devicetree/bindings/serial/serial.yaml +++ b/Documentation/devicetree/bindings/serial/serial.yaml @@ -141,13 +141,13 @@ additionalProperties: true examples: - | serial@1234 { - compatible = "ns16550a"; - reg = <0x1234 0x20>; - interrupts = <1>; + compatible = "ns16550a"; + reg = <0x1234 0x20>; + interrupts = <1>; - bluetooth { - compatible = "brcm,bcm4330-bt"; - interrupt-parent = <&gpio>; - interrupts = <10>; - }; + bluetooth { + compatible = "brcm,bcm4330-bt"; + interrupt-parent = <&gpio>; + interrupts = <10>; + }; }; diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/Documentation/devicetree/bindings/serial/sifive-serial.yaml index b0a8871e3641..b0df1cac4968 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -53,13 +53,13 @@ unevaluatedProperties: false examples: - | - #include - serial@10010000 { + #include + serial@10010000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; interrupt-parent = <&plic0>; interrupts = <80>; reg = <0x10010000 0x1000>; clocks = <&prci FU540_PRCI_CLK_TLCLK>; - }; + }; ... diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index b9c2287c5d1e..2becdfab4f15 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -67,6 +67,14 @@ properties: - const: baudclk - const: apb_pclk + dmas: + minItems: 2 + + dma-names: + items: + - const: rx + - const: tx + snps,uart-16550-compatible: description: reflects the value of UART_16550_COMPATIBLE configuration parameter. Define this if your UART does not implement the busy functionality. diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 85876c668f6d..1df8ffe95fc6 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -35,8 +35,6 @@ properties: description: enable hardware flow control (deprecated) $ref: /schemas/types.yaml#/definitions/flag - uart-has-rtscts: true - rx-tx-swap: true dmas: @@ -60,11 +58,6 @@ properties: wakeup-source: true - rs485-rts-delay: true - rs485-rts-active-low: true - linux,rs485-enabled-at-boot-time: true - rs485-rx-during-tx: true - rx-threshold: description: If value is set to 1, RX FIFO threshold is disabled. diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml index 2f4390e8d4e8..08dcb275d8e2 100644 --- a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml @@ -63,7 +63,7 @@ required: - xlnx,use-parity allOf: - - $ref: /schemas/serial.yaml# + - $ref: serial.yaml# - if: properties: xlnx,use-parity: @@ -76,7 +76,7 @@ unevaluatedProperties: false examples: - | - serial@800c0000 { + serial@800c0000 { compatible = "xlnx,xps-uartlite-1.00.a"; reg = <0x800c0000 0x10000>; interrupts = <0x0 0x6e 0x1>; @@ -84,5 +84,5 @@ examples: current-speed = <115200>; xlnx,data-bits = <8>; xlnx,use-parity = <0>; - }; + }; ... diff --git a/Documentation/driver-api/tty/n_gsm.rst b/Documentation/driver-api/tty/n_gsm.rst index 35d7381515b0..9447b8a3b8e2 100644 --- a/Documentation/driver-api/tty/n_gsm.rst +++ b/Documentation/driver-api/tty/n_gsm.rst @@ -25,6 +25,8 @@ Config Initiator #. Switch the serial line to using the n_gsm line discipline by using ``TIOCSETD`` ioctl. +#. Configure the mux using ``GSMIOC_GETCONF_EXT``/``GSMIOC_SETCONF_EXT`` ioctl if needed. + #. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl. #. Obtain base gsmtty number for the used serial port. @@ -42,6 +44,7 @@ Config Initiator int ldisc = N_GSM0710; struct gsm_config c; + struct gsm_config_ext ce; struct termios configuration; uint32_t first; @@ -62,6 +65,12 @@ Config Initiator /* use n_gsm line discipline */ ioctl(fd, TIOCSETD, &ldisc); + /* get n_gsm extended configuration */ + ioctl(fd, GSMIOC_GETCONF_EXT, &ce); + /* use keep-alive once every 5s for modem connection supervision */ + ce.keep_alive = 500; + /* set the new extended configuration */ + ioctl(fd, GSMIOC_SETCONF_EXT, &ce); /* get n_gsm configuration */ ioctl(fd, GSMIOC_GETCONF, &c); /* we are initiator and need encoding 0 (basic) */ @@ -106,6 +115,9 @@ Config Requester #. Switch the serial line to using the *n_gsm* line discipline by using ``TIOCSETD`` ioctl. +#. Configure the mux using ``GSMIOC_GETCONF_EXT``/``GSMIOC_SETCONF_EXT`` + ioctl if needed. + #. Configure the mux using ``GSMIOC_GETCONF``/``GSMIOC_SETCONF`` ioctl. #. Obtain base gsmtty number for the used serial port:: @@ -119,6 +131,7 @@ Config Requester int ldisc = N_GSM0710; struct gsm_config c; + struct gsm_config_ext ce; struct termios configuration; uint32_t first; @@ -132,6 +145,12 @@ Config Requester /* use n_gsm line discipline */ ioctl(fd, TIOCSETD, &ldisc); + /* get n_gsm extended configuration */ + ioctl(fd, GSMIOC_GETCONF_EXT, &ce); + /* use keep-alive once every 5s for peer connection supervision */ + ce.keep_alive = 500; + /* set the new extended configuration */ + ioctl(fd, GSMIOC_SETCONF_EXT, &ce); /* get n_gsm configuration */ ioctl(fd, GSMIOC_GETCONF, &c); /* we are requester and need encoding 0 (basic) */ diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 15b670926084..80255e2dc3e6 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -75,6 +75,125 @@ convenient for software to locate each feature by walking through this list, and can be implemented in register regions of any FPGA device. +Device Feature Header - Version 0 +================================= +Version 0 (DFHv0) is the original version of the Device Feature Header. +All multi-byte quantities in DFHv0 are little-endian. +The format of DFHv0 is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + +- Offset 0x00 + + * Type - The type of DFH (e.g. FME, AFU, or private feature). + * DFH VER - The version of the DFH. + * Rsvd - Currently unused. + * EOL - Set if the DFH is the end of the Device Feature List (DFL). + * Next - The offset in bytes of the next DFH in the DFL from the DFH start, + and the start of a DFH must be aligned to an 8 byte boundary. + If EOL is set, Next is the size of MMIO of the last feature in the list. + * REV - The revision of the feature associated with this header. + * ID - The feature ID if Type is private feature. + +- Offset 0x08 + + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier + (present only if Type is FME or AFU). + +- Offset 0x10 + + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier + (present only if Type is FME or AFU). + + +Device Feature Header - Version 1 +================================= +Version 1 (DFHv1) of the Device Feature Header adds the following functionality: + +* Provides a standardized mechanism for features to describe + parameters/capabilities to software. +* Standardize the use of a GUID for all DFHv1 types. +* Decouples the DFH location from the register space of the feature itself. + +All multi-byte quantities in DFHv1 are little-endian. +The format of Version 1 of the Device Feature Header (DFH) is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + |63 Reg Address/Offset 1| Rel 0| 0x18 + +-----------------------------------------------------------------------+ + |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20 + +-----------------------------------------------------------------------+ + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28 + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| 0x30 + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next 35|34RSV33|EOP32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + +- Offset 0x00 + + * Type - The type of DFH (e.g. FME, AFU, or private feature). + * DFH VER - The version of the DFH. + * Rsvd - Currently unused. + * EOL - Set if the DFH is the end of the Device Feature List (DFL). + * Next - The offset in bytes of the next DFH in the DFL from the DFH start, + and the start of a DFH must be aligned to an 8 byte boundary. + If EOL is set, Next is the size of MMIO of the last feature in the list. + * REV - The revision of the feature associated with this header. + * ID - The feature ID if Type is private feature. + +- Offset 0x08 + + * GUID_L - Least significant 64 bits of a 128-bit Globally Unique Identifier. + +- Offset 0x10 + + * GUID_H - Most significant 64 bits of a 128-bit Globally Unique Identifier. + +- Offset 0x18 + + * Reg Address/Offset - If Rel bit is set, then the value is the high 63 bits + of a 16-bit aligned absolute address of the feature's registers. Otherwise + the value is the offset from the start of the DFH of the feature's registers. + +- Offset 0x20 + + * Reg Size - Size of feature's register set in bytes. + * Params - Set if DFH has a list of parameter blocks. + * Group - Id of group if feature is part of a group. + * Instance - Id of feature instance within a group. + +- Offset 0x28 if feature has parameters + + * Next - Offset to the next parameter block in 8 byte words. If EOP set, + size in 8 byte words of last parameter. + * Param Version - Version of Param ID. + * Param ID - ID of parameter. + +- Offset 0x30 + + * Parameter Data - Parameter data whose size and format is defined by + version and ID of the parameter. + + FIU - FME (FPGA Management Engine) ================================== The FPGA Management Engine performs reconfiguration and other infrastructure diff --git a/Documentation/kbuild/kbuild.rst b/Documentation/kbuild/kbuild.rst index 08f575e6236c..5202186728b4 100644 --- a/Documentation/kbuild/kbuild.rst +++ b/Documentation/kbuild/kbuild.rst @@ -278,6 +278,13 @@ To get all available archs you can also specify all. E.g.:: $ make ALLSOURCE_ARCHS=all tags +IGNORE_DIRS +----------- +For tags/TAGS/cscope targets, you can choose which directories won't +be included in the databases, separated by blank space. E.g.:: + + $ make IGNORE_DIRS="drivers/gpu/drm/radeon tools" cscope + KBUILD_BUILD_TIMESTAMP ---------------------- Setting this to a date string overrides the timestamp used in the diff --git a/Documentation/trace/coresight/coresight-tpda.rst b/Documentation/trace/coresight/coresight-tpda.rst new file mode 100644 index 000000000000..a37f387ceaea --- /dev/null +++ b/Documentation/trace/coresight/coresight-tpda.rst @@ -0,0 +1,52 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================================================= +The trace performance monitoring and diagnostics aggregator(TPDA) +================================================================= + + :Author: Jinlong Mao + :Date: January 2023 + +Hardware Description +-------------------- + +TPDA - The trace performance monitoring and diagnostics aggregator or +TPDA in short serves as an arbitration and packetization engine for the +performance monitoring and diagnostics network specification. +The primary use case of the TPDA is to provide packetization, funneling +and timestamping of Monitor data. + + +Sysfs files and directories +--------------------------- +Root: ``/sys/bus/coresight/devices/tpda`` + +Config details +--------------------------- + +The tpdm and tpda nodes should be observed at the coresight path +"/sys/bus/coresight/devices". +e.g. +/sys/bus/coresight/devices # ls -l | grep tpd +tpda0 -> ../../../devices/platform/soc@0/6004000.tpda/tpda0 +tpdm0 -> ../../../devices/platform/soc@0/6c08000.mm.tpdm/tpdm0 + +We can use the commands are similar to the below to validate TPDMs. +Enable coresight sink first. The port of tpda which is connected to +the tpdm will be enabled after commands below. + +echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink +echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source +echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test +echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test + +The test data will be collected in the coresight sink which is enabled. +If rwp register of the sink is keeping updating when do +integration_test (by cat tmc_etf0/mgmt/rwp), it means there is data +generated from TPDM to sink. + +There must be a tpda between tpdm and the sink. When there are some +other trace event hw components in the same HW block with tpdm, tpdm +and these hw components will connect to the coresight funnel. When +there is only tpdm trace hw in the HW block, tpdm will connect to +tpda directly. diff --git a/Documentation/trace/coresight/coresight-tpdm.rst b/Documentation/trace/coresight/coresight-tpdm.rst new file mode 100644 index 000000000000..72fd5c855d45 --- /dev/null +++ b/Documentation/trace/coresight/coresight-tpdm.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================================== +Trace performance monitoring and diagnostics monitor(TPDM) +========================================================== + + :Author: Jinlong Mao + :Date: January 2023 + +Hardware Description +-------------------- +TPDM - The trace performance monitoring and diagnostics monitor or TPDM in +short serves as data collection component for various dataset types. +The primary use case of the TPDM is to collect data from different data +sources and send it to a TPDA for packetization, timestamping and funneling. + +Sysfs files and directories +--------------------------- +Root: ``/sys/bus/coresight/devices/tpdm`` + +---- + +:File: ``enable_source`` (RW) +:Notes: + - > 0 : enable the datasets of TPDM. + + - = 0 : disable the datasets of TPDM. + +:Syntax: + ``echo 1 > enable_source`` + +---- + +:File: ``integration_test`` (wo) +:Notes: + Integration test will generate test data for tpdm. + +:Syntax: + ``echo value > integration_test`` + + value - 1 or 2. + +---- + +.. This text is intentionally added to make Sphinx happy. diff --git a/Documentation/trace/coresight/ultrasoc-smb.rst b/Documentation/trace/coresight/ultrasoc-smb.rst new file mode 100644 index 000000000000..a05488a75ff0 --- /dev/null +++ b/Documentation/trace/coresight/ultrasoc-smb.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +UltraSoc - HW Assisted Tracing on SoC +====================================== + :Author: Qi Liu + :Date: January 2023 + +Introduction +------------ + +UltraSoc SMB is a per SCCL (Super CPU Cluster) hardware. It provides a +way to buffer and store CPU trace messages in a region of shared system +memory. The device acts as a coresight sink device and the +corresponding trace generators (ETM) are attached as source devices. + +Sysfs files and directories +--------------------------- + +The SMB devices appear on the existing coresight bus alongside other +devices:: + + $# ls /sys/bus/coresight/devices/ + ultra_smb0 ultra_smb1 ultra_smb2 ultra_smb3 + +The ``ultra_smb`` names SMB device associated with SCCL.:: + + $# ls /sys/bus/coresight/devices/ultra_smb0 + enable_sink mgmt + $# ls /sys/bus/coresight/devices/ultra_smb0/mgmt + buf_size buf_status read_pos write_pos + +Key file items are: + + * ``read_pos``: Shows the value on the read pointer register. + * ``write_pos``: Shows the value on the write pointer register. + * ``buf_status``: Shows the value on the status register. + BIT(0) is zero value which means the buffer is empty. + * ``buf_size``: Shows the buffer size of each device. + +Firmware Bindings +----------------- + +The device is only supported with ACPI. Its binding describes device +identifier, resource information and graph structure. + +The device is identified as ACPI HID "HISI03A1". Device resources are allocated +using the _CRS method. Each device must present two base address; the first one +is the configuration base address of the device, the second one is the 32-bit +base address of shared system memory. + +Example:: + + Device(USMB) { \ + Name(_HID, "HISI03A1") \ + Name(_CRS, ResourceTemplate() { \ + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, NonCacheable, \ + ReadWrite, 0x0, 0x95100000, 0x951FFFFF, 0x0, 0x100000) \ + QWordMemory (ResourceConsumer, , MinFixed, MaxFixed, Cacheable, \ + ReadWrite, 0x0, 0x50000000, 0x53FFFFFF, 0x0, 0x4000000) \ + }) \ + Name(_DSD, Package() { \ + ToUUID("ab02a46b-74c7-45a2-bd68-f7d344ef2153"), \ + /* Use CoreSight Graph ACPI bindings to describe connections topology */ + Package() { \ + 0, \ + 1, \ + Package() { \ + 1, \ + ToUUID("3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"), \ + 8, \ + Package() {0x8, 0, \_SB.S00.SL11.CL28.F008, 0}, \ + Package() {0x9, 0, \_SB.S00.SL11.CL29.F009, 0}, \ + Package() {0xa, 0, \_SB.S00.SL11.CL2A.F010, 0}, \ + Package() {0xb, 0, \_SB.S00.SL11.CL2B.F011, 0}, \ + Package() {0xc, 0, \_SB.S00.SL11.CL2C.F012, 0}, \ + Package() {0xd, 0, \_SB.S00.SL11.CL2D.F013, 0}, \ + Package() {0xe, 0, \_SB.S00.SL11.CL2E.F014, 0}, \ + Package() {0xf, 0, \_SB.S00.SL11.CL2F.F015, 0}, \ + } \ + } \ + }) \ + } diff --git a/MAINTAINERS b/MAINTAINERS index 8fe422c8aeb5..e2f76f7961a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2071,8 +2071,10 @@ M: Hartley Sweeten M: Alexander Sverdlin L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/iio/adc/cirrus,ep9301-adc.yaml F: arch/arm/boot/compressed/misc-ep93xx.h F: arch/arm/mach-ep93xx/ +F: drivers/iio/adc/ep93xx_adc.c ARM/CLKDEV SUPPORT M: Russell King @@ -2099,6 +2101,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml +F: Documentation/devicetree/bindings/arm/qcom,coresight-*.yaml F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/trace/coresight/* @@ -9254,11 +9257,15 @@ F: drivers/perf/hisilicon/hns3_pmu.c HISILICON PTT DRIVER M: Yicong Yang +M: Jonathan Cameron L: linux-kernel@vger.kernel.org S: Maintained F: Documentation/ABI/testing/sysfs-devices-hisi_ptt F: Documentation/trace/hisi-ptt.rst F: drivers/hwtracing/ptt/ +F: tools/perf/arch/arm64/util/hisi-ptt.c +F: tools/perf/util/hisi-ptt* +F: tools/perf/util/hisi-ptt-decoder/* HISILICON QM DRIVER M: Weili Qian @@ -10461,6 +10468,7 @@ F: drivers/watchdog/mei_wdt.c F: include/linux/mei_aux.h F: include/linux/mei_cl_bus.h F: include/uapi/linux/mei.h +F: include/uapi/linux/uuid.h F: samples/mei/* INTEL MAX 10 BMC MFD DRIVER @@ -13535,6 +13543,19 @@ W: http://www.monstr.eu/fdt/ T: git git://git.monstr.eu/linux-2.6-microblaze.git F: arch/microblaze/ +MICROBLAZE TMR MANAGER +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/ABI/testing/sysfs-driver-xilinx-tmr-manager +F: Documentation/devicetree/bindings/misc/xlnx,tmr-manager.yaml +F: drivers/misc/xilinx_tmr_manager.c + +MICROBLAZE TMR INJECT +M: Appana Durga Kedareswara rao +S: Supported +F: Documentation/devicetree/bindings/misc/xlnx,tmr-inject.yaml +F: drivers/misc/xilinx_tmr_inject.c + MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches M: Tudor Ambarus @@ -13710,6 +13731,13 @@ L: linux-i2c@vger.kernel.org S: Maintained F: drivers/i2c/busses/i2c-mchp-pci1xxxx.c +MICROCHIP PCIe UART DRIVER +M: Kumaravel Thiagarajan +M: Tharun Kumar P +L: linux-serial@vger.kernel.org +S: Maintained +F: drivers/tty/serial/8250/8250_pci1xxxx.c + MICROCHIP PWM DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -14069,6 +14097,16 @@ F: drivers/regulator/mpq7920.c F: drivers/regulator/mpq7920.h F: include/linux/mfd/mp2629.h +MOST(R) TECHNOLOGY DRIVER +M: Parthiban Veerasooran +M: Christian Gromm +S: Maintained +F: Documentation/ABI/testing/configfs-most +F: Documentation/ABI/testing/sysfs-bus-most +F: drivers/most/ +F: drivers/staging/most/ +F: include/linux/most.h + MOTION EYE VAIO PICTUREBOOK CAMERA DRIVER S: Orphan W: http://popies.net/meye/ @@ -14943,14 +14981,16 @@ S: Maintained F: Documentation/devicetree/bindings/iio/adc/nxp,imx8qxp-adc.yaml F: drivers/iio/adc/imx8qxp-adc.c -NXP i.MX 7D/6SX/6UL AND VF610 ADC DRIVER +NXP i.MX 7D/6SX/6UL/93 AND VF610 ADC DRIVER M: Haibo Chen L: linux-iio@vger.kernel.org L: linux-imx@nxp.com S: Maintained F: Documentation/devicetree/bindings/iio/adc/fsl,imx7d-adc.yaml F: Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml +F: Documentation/devicetree/bindings/iio/adc/nxp,imx93-adc.yaml F: drivers/iio/adc/imx7d_adc.c +F: drivers/iio/adc/imx93_adc.c F: drivers/iio/adc/vf610_adc.c NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER @@ -20746,6 +20786,13 @@ M: Robert Richter S: Odd Fixes F: drivers/gpio/gpio-thunderx.c +TI ADS7924 ADC DRIVER +M: Hugo Villeneuve +L: linux-iio@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/iio/adc/ti,ads7924.yaml +F: drivers/iio/adc/ti-ads7924.c + TI AM437X VPFE DRIVER M: "Lad, Prabhakar" L: linux-media@vger.kernel.org @@ -20865,6 +20912,14 @@ S: Maintained F: sound/soc/codecs/isabelle* F: sound/soc/codecs/lm49453* +TI LMP92064 ADC DRIVER +M: Leonard Göhrs +R: kernel@pengutronix.de +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/adc/ti,lmp92064.yaml +F: drivers/iio/adc/ti-lmp92064.c + TI PCM3060 ASoC CODEC DRIVER M: Kirill Marinushkin L: alsa-devel@alsa-project.org (moderated for non-subscribers) @@ -20878,6 +20933,13 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers) S: Odd Fixes F: sound/soc/codecs/tas571x* +TI TMAG5273 MAGNETOMETER DRIVER +M: Gerald Loacker +L: linux-iio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/iio/magnetometer/ti,tmag5273.yaml +F: drivers/iio/magnetometer/tmag5273.c + TI TRF7970A NFC DRIVER M: Mark Greer L: linux-wireless@vger.kernel.org @@ -21779,7 +21841,6 @@ R: Andy Shevchenko L: linux-kernel@vger.kernel.org S: Maintained F: include/linux/uuid.h -F: include/uapi/linux/uuid.h F: lib/test_uuid.c F: lib/uuid.c diff --git a/arch/arm/include/asm/semihost.h b/arch/arm/include/asm/semihost.h new file mode 100644 index 000000000000..f365787e7c23 --- /dev/null +++ b/arch/arm/include/asm/semihost.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Marc Zyngier + * + * Adapted for ARM and earlycon: + * Copyright (C) 2014 Linaro Ltd. + * Author: Rob Herring + */ + +#ifndef _ARM_SEMIHOST_H_ +#define _ARM_SEMIHOST_H_ + +#ifdef CONFIG_THUMB2_KERNEL +#define SEMIHOST_SWI "0xab" +#else +#define SEMIHOST_SWI "0x123456" +#endif + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("mov r1, %0\n" + "mov r0, #3\n" + "svc " SEMIHOST_SWI "\n" + : : "r" (&c) : "r0", "r1", "memory"); +} + +#endif /* _ARM_SEMIHOST_H_ */ diff --git a/arch/arm64/include/asm/semihost.h b/arch/arm64/include/asm/semihost.h new file mode 100644 index 000000000000..87e353dab868 --- /dev/null +++ b/arch/arm64/include/asm/semihost.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Marc Zyngier + * + * Adapted for ARM and earlycon: + * Copyright (C) 2014 Linaro Ltd. + * Author: Rob Herring + */ + +#ifndef _ARM64_SEMIHOST_H_ +#define _ARM64_SEMIHOST_H_ + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("mov x1, %0\n" + "mov x0, #3\n" + "hlt 0xf000\n" + : : "r" (&c) : "x0", "x1", "memory"); +} + +#endif /* _ARM64_SEMIHOST_H_ */ diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h new file mode 100644 index 000000000000..557a34938193 --- /dev/null +++ b/arch/riscv/include/asm/semihost.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 tinylab.org + * Author: Bin Meng + */ + +#ifndef _RISCV_SEMIHOST_H_ +#define _RISCV_SEMIHOST_H_ + +struct uart_port; + +static inline void smh_putc(struct uart_port *port, unsigned char c) +{ + asm volatile("addi a1, %0, 0\n" + "addi a0, zero, 3\n" + ".balign 16\n" + ".option push\n" + ".option norvc\n" + "slli zero, zero, 0x1f\n" + "ebreak\n" + "srai zero, zero, 0x7\n" + ".option pop\n" + : : "r" (&c) : "a0", "a1", "memory"); +} + +#endif /* _RISCV_SEMIHOST_H_ */ diff --git a/drivers/accessibility/speakup/main.c b/drivers/accessibility/speakup/main.c index 4733fd6334ab..56c073103cbb 100644 --- a/drivers/accessibility/speakup/main.c +++ b/drivers/accessibility/speakup/main.c @@ -2490,7 +2490,7 @@ MODULE_PARM_DESC(punc_level, "Controls the level of punctuation spoken as the sc MODULE_PARM_DESC(reading_punc, "It controls the level of punctuation when reviewing the screen with speakup's screen review commands."); MODULE_PARM_DESC(cursor_time, "This controls cursor delay when using arrow keys."); MODULE_PARM_DESC(say_control, "This controls if speakup speaks shift, alt and control when those keys are pressed or not."); -MODULE_PARM_DESC(say_word_ctl, "Sets thw say_word_ctl on load."); +MODULE_PARM_DESC(say_word_ctl, "Sets the say_word_ctl on load."); MODULE_PARM_DESC(no_interrupt, "Controls if typing interrupts output from speakup."); MODULE_PARM_DESC(key_echo, "Controls if speakup speaks keys when they are typed. One = on zero = off or don't echo keys."); MODULE_PARM_DESC(cur_phonetic, "Controls if speakup speaks letters phonetically during navigation. One = on zero = off or don't speak phonetically."); diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 16f527a7f0be..badcee719f3d 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -280,11 +280,11 @@ _binder_proc_lock(struct binder_proc *proc, int line) /** * binder_proc_unlock() - Release spinlock for given binder_proc - * @proc: struct binder_proc to acquire + * @proc: struct binder_proc to acquire * * Release lock acquired via binder_proc_lock() */ -#define binder_proc_unlock(_proc) _binder_proc_unlock(_proc, __LINE__) +#define binder_proc_unlock(proc) _binder_proc_unlock(proc, __LINE__) static void _binder_proc_unlock(struct binder_proc *proc, int line) __releases(&proc->outer_lock) @@ -381,7 +381,7 @@ _binder_node_inner_lock(struct binder_node *node, int line) } /** - * binder_node_unlock() - Release node and inner locks + * binder_node_inner_unlock() - Release node and inner locks * @node: struct binder_node to acquire * * Release lock acquired via binder_node_lock() @@ -1372,13 +1372,13 @@ static int binder_inc_ref_olocked(struct binder_ref *ref, int strong, } /** - * binder_dec_ref() - dec the ref for given handle + * binder_dec_ref_olocked() - dec the ref for given handle * @ref: ref to be decremented * @strong: if true, strong decrement, else weak * * Decrement the ref. * - * Return: true if ref is cleaned up and ready to be freed + * Return: %true if ref is cleaned up and ready to be freed. */ static bool binder_dec_ref_olocked(struct binder_ref *ref, int strong) { @@ -2906,7 +2906,10 @@ binder_find_outdated_transaction_ilocked(struct binder_transaction *t, * * Return: 0 if the transaction was successfully queued * BR_DEAD_REPLY if the target process or thread is dead - * BR_FROZEN_REPLY if the target process or thread is frozen + * BR_FROZEN_REPLY if the target process or thread is frozen and + * the sync transaction was rejected + * BR_TRANSACTION_PENDING_FROZEN if the target process is frozen + * and the async transaction was successfully queued */ static int binder_proc_transaction(struct binder_transaction *t, struct binder_proc *proc, @@ -2916,6 +2919,7 @@ static int binder_proc_transaction(struct binder_transaction *t, bool oneway = !!(t->flags & TF_ONE_WAY); bool pending_async = false; struct binder_transaction *t_outdated = NULL; + bool frozen = false; BUG_ON(!node); binder_node_lock(node); @@ -2930,15 +2934,16 @@ static int binder_proc_transaction(struct binder_transaction *t, binder_inner_proc_lock(proc); if (proc->is_frozen) { + frozen = true; proc->sync_recv |= !oneway; proc->async_recv |= oneway; } - if ((proc->is_frozen && !oneway) || proc->is_dead || + if ((frozen && !oneway) || proc->is_dead || (thread && thread->is_dead)) { binder_inner_proc_unlock(proc); binder_node_unlock(node); - return proc->is_frozen ? BR_FROZEN_REPLY : BR_DEAD_REPLY; + return frozen ? BR_FROZEN_REPLY : BR_DEAD_REPLY; } if (!thread && !pending_async) @@ -2950,7 +2955,7 @@ static int binder_proc_transaction(struct binder_transaction *t, } else if (!pending_async) { binder_enqueue_work_ilocked(&t->work, &proc->todo); } else { - if ((t->flags & TF_UPDATE_TXN) && proc->is_frozen) { + if ((t->flags & TF_UPDATE_TXN) && frozen) { t_outdated = binder_find_outdated_transaction_ilocked(t, &node->async_todo); if (t_outdated) { @@ -2987,14 +2992,17 @@ static int binder_proc_transaction(struct binder_transaction *t, binder_stats_deleted(BINDER_STAT_TRANSACTION); } + if (oneway && frozen) + return BR_TRANSACTION_PENDING_FROZEN; + return 0; } /** * binder_get_node_refs_for_txn() - Get required refs on node for txn * @node: struct binder_node for which to get refs - * @proc: returns @node->proc if valid - * @error: if no @proc then returns BR_DEAD_REPLY + * @procp: returns @node->proc if valid + * @error: if no @procp then returns BR_DEAD_REPLY * * User-space normally keeps the node alive when creating a transaction * since it has a reference to the target. The local strong ref keeps it @@ -3008,8 +3016,8 @@ static int binder_proc_transaction(struct binder_transaction *t, * constructing the transaction, so we take that here as well. * * Return: The target_node with refs taken or NULL if no @node->proc is NULL. - * Also sets @proc if valid. If the @node->proc is NULL indicating that the - * target proc has died, @error is set to BR_DEAD_REPLY + * Also sets @procp if valid. If the @node->proc is NULL indicating that the + * target proc has died, @error is set to BR_DEAD_REPLY. */ static struct binder_node *binder_get_node_refs_for_txn( struct binder_node *node, @@ -3806,9 +3814,17 @@ static void binder_transaction(struct binder_proc *proc, } else { BUG_ON(target_node == NULL); BUG_ON(t->buffer->async_transaction != 1); - binder_enqueue_thread_work(thread, tcomplete); return_error = binder_proc_transaction(t, target_proc, NULL); - if (return_error) + /* + * Let the caller know when async transaction reaches a frozen + * process and is put in a pending queue, waiting for the target + * process to be unfrozen. + */ + if (return_error == BR_TRANSACTION_PENDING_FROZEN) + tcomplete->type = BINDER_WORK_TRANSACTION_PENDING; + binder_enqueue_thread_work(thread, tcomplete); + if (return_error && + return_error != BR_TRANSACTION_PENDING_FROZEN) goto err_dead_proc_or_thread; } if (target_thread) @@ -4643,10 +4659,13 @@ retry: binder_stat_br(proc, thread, cmd); } break; case BINDER_WORK_TRANSACTION_COMPLETE: + case BINDER_WORK_TRANSACTION_PENDING: case BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT: { if (proc->oneway_spam_detection_enabled && w->type == BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT) cmd = BR_ONEWAY_SPAM_SUSPECT; + else if (w->type == BINDER_WORK_TRANSACTION_PENDING) + cmd = BR_TRANSACTION_PENDING_FROZEN; else cmd = BR_TRANSACTION_COMPLETE; binder_inner_proc_unlock(proc); @@ -5209,20 +5228,14 @@ static __poll_t binder_poll(struct file *filp, return 0; } -static int binder_ioctl_write_read(struct file *filp, - unsigned int cmd, unsigned long arg, +static int binder_ioctl_write_read(struct file *filp, unsigned long arg, struct binder_thread *thread) { int ret = 0; struct binder_proc *proc = filp->private_data; - unsigned int size = _IOC_SIZE(cmd); void __user *ubuf = (void __user *)arg; struct binder_write_read bwr; - if (size != sizeof(struct binder_write_read)) { - ret = -EINVAL; - goto out; - } if (copy_from_user(&bwr, ubuf, sizeof(bwr))) { ret = -EFAULT; goto out; @@ -5499,7 +5512,6 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) int ret; struct binder_proc *proc = filp->private_data; struct binder_thread *thread; - unsigned int size = _IOC_SIZE(cmd); void __user *ubuf = (void __user *)arg; /*pr_info("binder_ioctl: %d:%d %x %lx\n", @@ -5521,7 +5533,7 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) switch (cmd) { case BINDER_WRITE_READ: - ret = binder_ioctl_write_read(filp, cmd, arg, thread); + ret = binder_ioctl_write_read(filp, arg, thread); if (ret) goto err; break; @@ -5564,10 +5576,6 @@ static long binder_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) case BINDER_VERSION: { struct binder_version __user *ver = ubuf; - if (size != sizeof(struct binder_version)) { - ret = -EINVAL; - goto err; - } if (put_user(BINDER_CURRENT_PROTOCOL_VERSION, &ver->protocol_version)) { ret = -EINVAL; @@ -6381,6 +6389,7 @@ static const char * const binder_return_strings[] = { "BR_FAILED_REPLY", "BR_FROZEN_REPLY", "BR_ONEWAY_SPAM_SUSPECT", + "BR_TRANSACTION_PENDING_FROZEN" }; static const char * const binder_command_strings[] = { diff --git a/drivers/android/binder_internal.h b/drivers/android/binder_internal.h index 9132d1483288..bf112299734d 100644 --- a/drivers/android/binder_internal.h +++ b/drivers/android/binder_internal.h @@ -133,7 +133,7 @@ enum binder_stat_types { }; struct binder_stats { - atomic_t br[_IOC_NR(BR_ONEWAY_SPAM_SUSPECT) + 1]; + atomic_t br[_IOC_NR(BR_TRANSACTION_PENDING_FROZEN) + 1]; atomic_t bc[_IOC_NR(BC_REPLY_SG) + 1]; atomic_t obj_created[BINDER_STAT_COUNT]; atomic_t obj_deleted[BINDER_STAT_COUNT]; @@ -152,6 +152,7 @@ struct binder_work { enum binder_work_type { BINDER_WORK_TRANSACTION = 1, BINDER_WORK_TRANSACTION_COMPLETE, + BINDER_WORK_TRANSACTION_PENDING, BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT, BINDER_WORK_RETURN_ERROR, BINDER_WORK_NODE, diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index 348d63d1e3d3..76e7d6676657 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -222,14 +222,14 @@ err: } /** - * binderfs_ctl_ioctl - handle binder device node allocation requests + * binder_ctl_ioctl - handle binder device node allocation requests * * The request handler for the binder-control device. All requests operate on * the binderfs mount the binder-control device resides in: * - BINDER_CTL_ADD * Allocate a new binder device. * - * Return: 0 on success, negative errno on failure + * Return: %0 on success, negative errno on failure. */ static long binder_ctl_ioctl(struct file *file, unsigned int cmd, unsigned long arg) diff --git a/drivers/bus/mhi/Makefile b/drivers/bus/mhi/Makefile index 46981331b38f..354204b0ef3a 100644 --- a/drivers/bus/mhi/Makefile +++ b/drivers/bus/mhi/Makefile @@ -1,5 +1,5 @@ # Host MHI stack -obj-y += host/ +obj-$(CONFIG_MHI_BUS) += host/ # Endpoint MHI stack -obj-y += ep/ +obj-$(CONFIG_MHI_BUS_EP) += ep/ diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 1dc8a3557a46..dffe03658ff9 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -123,6 +123,13 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele int ret; ch_id = MHI_TRE_GET_CMD_CHID(el); + + /* Check if the channel is supported by the controller */ + if ((ch_id >= mhi_cntrl->max_chan) || !mhi_cntrl->mhi_chan[ch_id].name) { + dev_err(dev, "Channel (%u) not supported!\n", ch_id); + return -ENODEV; + } + mhi_chan = &mhi_cntrl->mhi_chan[ch_id]; ch_ring = &mhi_cntrl->mhi_chan[ch_id].ring; @@ -196,9 +203,11 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele mhi_ep_mmio_disable_chdb(mhi_cntrl, ch_id); /* Send channel disconnect status to client drivers */ - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + if (mhi_chan->xfer_cb) { + result.transaction_status = -ENOTCONN; + result.bytes_xferd = 0; + mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + } /* Set channel state to STOP */ mhi_chan->state = MHI_CH_STATE_STOP; @@ -217,7 +226,7 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele mutex_unlock(&mhi_chan->lock); break; case MHI_PKT_TYPE_RESET_CHAN_CMD: - dev_dbg(dev, "Received STOP command for channel (%u)\n", ch_id); + dev_dbg(dev, "Received RESET command for channel (%u)\n", ch_id); if (!ch_ring->started) { dev_err(dev, "Channel (%u) not opened\n", ch_id); return -ENODEV; @@ -228,9 +237,11 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele mhi_ep_ring_reset(mhi_cntrl, ch_ring); /* Send channel disconnect status to client driver */ - result.transaction_status = -ENOTCONN; - result.bytes_xferd = 0; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + if (mhi_chan->xfer_cb) { + result.transaction_status = -ENOTCONN; + result.bytes_xferd = 0; + mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + } /* Set channel state to DISABLED */ mhi_chan->state = MHI_CH_STATE_DISABLED; @@ -719,24 +730,37 @@ static void mhi_ep_ch_ring_worker(struct work_struct *work) list_del(&itr->node); ring = itr->ring; + chan = &mhi_cntrl->mhi_chan[ring->ch_id]; + mutex_lock(&chan->lock); + + /* + * The ring could've stopped while we waited to grab the (chan->lock), so do + * a sanity check before going further. + */ + if (!ring->started) { + mutex_unlock(&chan->lock); + kfree(itr); + continue; + } + /* Update the write offset for the ring */ ret = mhi_ep_update_wr_offset(ring); if (ret) { dev_err(dev, "Error updating write offset for ring\n"); + mutex_unlock(&chan->lock); kfree(itr); continue; } /* Sanity check to make sure there are elements in the ring */ if (ring->rd_offset == ring->wr_offset) { + mutex_unlock(&chan->lock); kfree(itr); continue; } el = &ring->ring_cache[ring->rd_offset]; - chan = &mhi_cntrl->mhi_chan[ring->ch_id]; - mutex_lock(&chan->lock); dev_dbg(dev, "Processing the ring for channel (%u)\n", ring->ch_id); ret = mhi_ep_process_ch_ring(ring, el); if (ret) { @@ -973,44 +997,25 @@ static void mhi_ep_abort_transfer(struct mhi_ep_cntrl *mhi_cntrl) static void mhi_ep_reset_worker(struct work_struct *work) { struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, reset_work); - struct device *dev = &mhi_cntrl->mhi_dev->dev; enum mhi_state cur_state; - int ret; - mhi_ep_abort_transfer(mhi_cntrl); + mhi_ep_power_down(mhi_cntrl); + + mutex_lock(&mhi_cntrl->state_lock); - spin_lock_bh(&mhi_cntrl->state_lock); /* Reset MMIO to signal host that the MHI_RESET is completed in endpoint */ mhi_ep_mmio_reset(mhi_cntrl); cur_state = mhi_cntrl->mhi_state; - spin_unlock_bh(&mhi_cntrl->state_lock); /* * Only proceed further if the reset is due to SYS_ERR. The host will * issue reset during shutdown also and we don't need to do re-init in * that case. */ - if (cur_state == MHI_STATE_SYS_ERR) { - mhi_ep_mmio_init(mhi_cntrl); + if (cur_state == MHI_STATE_SYS_ERR) + mhi_ep_power_up(mhi_cntrl); - /* Set AMSS EE before signaling ready state */ - mhi_ep_mmio_set_env(mhi_cntrl, MHI_EE_AMSS); - - /* All set, notify the host that we are ready */ - ret = mhi_ep_set_ready_state(mhi_cntrl); - if (ret) - return; - - dev_dbg(dev, "READY state notification sent to the host\n"); - - ret = mhi_ep_enable(mhi_cntrl); - if (ret) { - dev_err(dev, "Failed to enable MHI endpoint: %d\n", ret); - return; - } - - enable_irq(mhi_cntrl->irq); - } + mutex_unlock(&mhi_cntrl->state_lock); } /* @@ -1089,11 +1094,11 @@ EXPORT_SYMBOL_GPL(mhi_ep_power_up); void mhi_ep_power_down(struct mhi_ep_cntrl *mhi_cntrl) { - if (mhi_cntrl->enabled) + if (mhi_cntrl->enabled) { mhi_ep_abort_transfer(mhi_cntrl); - - kfree(mhi_cntrl->mhi_event); - disable_irq(mhi_cntrl->irq); + kfree(mhi_cntrl->mhi_event); + disable_irq(mhi_cntrl->irq); + } } EXPORT_SYMBOL_GPL(mhi_ep_power_down); @@ -1119,6 +1124,7 @@ void mhi_ep_suspend_channels(struct mhi_ep_cntrl *mhi_cntrl) dev_dbg(&mhi_chan->mhi_dev->dev, "Suspending channel\n"); /* Set channel state to SUSPENDED */ + mhi_chan->state = MHI_CH_STATE_SUSPENDED; tmp &= ~CHAN_CTX_CHSTATE_MASK; tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_SUSPENDED); mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp); @@ -1148,6 +1154,7 @@ void mhi_ep_resume_channels(struct mhi_ep_cntrl *mhi_cntrl) dev_dbg(&mhi_chan->mhi_dev->dev, "Resuming channel\n"); /* Set channel state to RUNNING */ + mhi_chan->state = MHI_CH_STATE_RUNNING; tmp &= ~CHAN_CTX_CHSTATE_MASK; tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_RUNNING); mhi_cntrl->ch_ctx_cache[i].chcfg = cpu_to_le32(tmp); @@ -1381,8 +1388,8 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl, INIT_LIST_HEAD(&mhi_cntrl->st_transition_list); INIT_LIST_HEAD(&mhi_cntrl->ch_db_list); - spin_lock_init(&mhi_cntrl->state_lock); spin_lock_init(&mhi_cntrl->list_lock); + mutex_init(&mhi_cntrl->state_lock); mutex_init(&mhi_cntrl->event_lock); /* Set MHI version and AMSS EE before enumeration */ diff --git a/drivers/bus/mhi/ep/sm.c b/drivers/bus/mhi/ep/sm.c index 3655c19e23c7..fd200b2ac0bb 100644 --- a/drivers/bus/mhi/ep/sm.c +++ b/drivers/bus/mhi/ep/sm.c @@ -63,24 +63,23 @@ int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl) int ret; /* If MHI is in M3, resume suspended channels */ - spin_lock_bh(&mhi_cntrl->state_lock); + mutex_lock(&mhi_cntrl->state_lock); + old_state = mhi_cntrl->mhi_state; if (old_state == MHI_STATE_M3) mhi_ep_resume_channels(mhi_cntrl); ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M0); - spin_unlock_bh(&mhi_cntrl->state_lock); - if (ret) { mhi_ep_handle_syserr(mhi_cntrl); - return ret; + goto err_unlock; } /* Signal host that the device moved to M0 */ ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M0); if (ret) { dev_err(dev, "Failed sending M0 state change event\n"); - return ret; + goto err_unlock; } if (old_state == MHI_STATE_READY) { @@ -88,11 +87,14 @@ int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl) ret = mhi_ep_send_ee_event(mhi_cntrl, MHI_EE_AMSS); if (ret) { dev_err(dev, "Failed sending AMSS EE event\n"); - return ret; + goto err_unlock; } } - return 0; +err_unlock: + mutex_unlock(&mhi_cntrl->state_lock); + + return ret; } int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl) @@ -100,13 +102,12 @@ int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl) struct device *dev = &mhi_cntrl->mhi_dev->dev; int ret; - spin_lock_bh(&mhi_cntrl->state_lock); - ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M3); - spin_unlock_bh(&mhi_cntrl->state_lock); + mutex_lock(&mhi_cntrl->state_lock); + ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M3); if (ret) { mhi_ep_handle_syserr(mhi_cntrl); - return ret; + goto err_unlock; } mhi_ep_suspend_channels(mhi_cntrl); @@ -115,10 +116,13 @@ int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl) ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M3); if (ret) { dev_err(dev, "Failed sending M3 state change event\n"); - return ret; + goto err_unlock; } - return 0; +err_unlock: + mutex_unlock(&mhi_cntrl->state_lock); + + return ret; } int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl) @@ -127,22 +131,24 @@ int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl) enum mhi_state mhi_state; int ret, is_ready; - spin_lock_bh(&mhi_cntrl->state_lock); + mutex_lock(&mhi_cntrl->state_lock); + /* Ensure that the MHISTATUS is set to RESET by host */ mhi_state = mhi_ep_mmio_masked_read(mhi_cntrl, EP_MHISTATUS, MHISTATUS_MHISTATE_MASK); is_ready = mhi_ep_mmio_masked_read(mhi_cntrl, EP_MHISTATUS, MHISTATUS_READY_MASK); if (mhi_state != MHI_STATE_RESET || is_ready) { dev_err(dev, "READY state transition failed. MHI host not in RESET state\n"); - spin_unlock_bh(&mhi_cntrl->state_lock); - return -EIO; + ret = -EIO; + goto err_unlock; } ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_READY); - spin_unlock_bh(&mhi_cntrl->state_lock); - if (ret) mhi_ep_handle_syserr(mhi_cntrl); +err_unlock: + mutex_unlock(&mhi_cntrl->state_lock); + return ret; } diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index bf672de35131..7307335c4fd1 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -1449,4 +1449,4 @@ postcore_initcall(mhi_init); module_exit(mhi_exit); MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("MHI Host Interface"); +MODULE_DESCRIPTION("Modem Host Interface"); diff --git a/drivers/bus/simple-pm-bus.c b/drivers/bus/simple-pm-bus.c index 6b8d6257ed8a..7afe1947e1c0 100644 --- a/drivers/bus/simple-pm-bus.c +++ b/drivers/bus/simple-pm-bus.c @@ -8,17 +8,24 @@ * for more details. */ +#include #include #include #include #include +struct simple_pm_bus { + struct clk_bulk_data *clks; + int num_clks; +}; + static int simple_pm_bus_probe(struct platform_device *pdev) { const struct device *dev = &pdev->dev; const struct of_dev_auxdata *lookup = dev_get_platdata(dev); struct device_node *np = dev->of_node; const struct of_device_id *match; + struct simple_pm_bus *bus; /* * Allow user to use driver_override to bind this driver to a @@ -44,6 +51,16 @@ static int simple_pm_bus_probe(struct platform_device *pdev) return -ENODEV; } + bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); + if (!bus) + return -ENOMEM; + + bus->num_clks = devm_clk_bulk_get_all(&pdev->dev, &bus->clks); + if (bus->num_clks < 0) + return dev_err_probe(&pdev->dev, bus->num_clks, "failed to get clocks\n"); + + dev_set_drvdata(&pdev->dev, bus); + dev_dbg(&pdev->dev, "%s\n", __func__); pm_runtime_enable(&pdev->dev); @@ -67,6 +84,34 @@ static int simple_pm_bus_remove(struct platform_device *pdev) return 0; } +static int simple_pm_bus_runtime_suspend(struct device *dev) +{ + struct simple_pm_bus *bus = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(bus->num_clks, bus->clks); + + return 0; +} + +static int simple_pm_bus_runtime_resume(struct device *dev) +{ + struct simple_pm_bus *bus = dev_get_drvdata(dev); + int ret; + + ret = clk_bulk_prepare_enable(bus->num_clks, bus->clks); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct dev_pm_ops simple_pm_bus_pm_ops = { + RUNTIME_PM_OPS(simple_pm_bus_runtime_suspend, simple_pm_bus_runtime_resume, NULL) + NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + #define ONLY_BUS ((void *) 1) /* Match if the device is only a bus. */ static const struct of_device_id simple_pm_bus_of_match[] = { @@ -85,6 +130,7 @@ static struct platform_driver simple_pm_bus_driver = { .driver = { .name = "simple-pm-bus", .of_match_table = simple_pm_bus_of_match, + .pm = pm_ptr(&simple_pm_bus_pm_ops), }, }; diff --git a/drivers/char/applicom.c b/drivers/char/applicom.c index 36203d3fa6ea..69314532f38c 100644 --- a/drivers/char/applicom.c +++ b/drivers/char/applicom.c @@ -197,8 +197,10 @@ static int __init applicom_init(void) if (!pci_match_id(applicom_pci_tbl, dev)) continue; - if (pci_enable_device(dev)) + if (pci_enable_device(dev)) { + pci_dev_put(dev); return -EIO; + } RamIO = ioremap(pci_resource_start(dev, 0), LEN_RAM_IO); @@ -207,6 +209,7 @@ static int __init applicom_init(void) "space at 0x%llx\n", (unsigned long long)pci_resource_start(dev, 0)); pci_disable_device(dev); + pci_dev_put(dev); return -EIO; } diff --git a/drivers/char/pcmcia/cm4000_cs.c b/drivers/char/pcmcia/cm4000_cs.c index adaec8fd4b16..e656f42a28ac 100644 --- a/drivers/char/pcmcia/cm4000_cs.c +++ b/drivers/char/pcmcia/cm4000_cs.c @@ -529,7 +529,8 @@ static int set_protocol(struct cm4000_dev *dev, struct ptsreq *ptsreq) DEBUGP(5, dev, "NumRecBytes is valid\n"); break; } - usleep_range(10000, 11000); + /* can not sleep as this is in atomic context */ + mdelay(10); } if (i == 100) { DEBUGP(5, dev, "Timeout waiting for NumRecBytes getting " @@ -549,7 +550,8 @@ static int set_protocol(struct cm4000_dev *dev, struct ptsreq *ptsreq) } break; } - usleep_range(10000, 11000); + /* can not sleep as this is in atomic context */ + mdelay(10); } /* check whether it is a short PTS reply? */ diff --git a/drivers/char/pcmcia/synclink_cs.c b/drivers/char/pcmcia/synclink_cs.c index b2735be81ab2..6ddfeb2fe98f 100644 --- a/drivers/char/pcmcia/synclink_cs.c +++ b/drivers/char/pcmcia/synclink_cs.c @@ -377,8 +377,8 @@ static void async_mode(MGSLPC_INFO *info); static void tx_timeout(struct timer_list *t); -static int carrier_raised(struct tty_port *port); -static void dtr_rts(struct tty_port *port, int onoff); +static bool carrier_raised(struct tty_port *port); +static void dtr_rts(struct tty_port *port, bool active); #if SYNCLINK_GENERIC_HDLC #define dev_to_port(D) (dev_to_hdlc(D)->priv) @@ -483,7 +483,7 @@ static void* mgslpc_get_text_ptr(void) return mgslpc_get_text_ptr; } -/** +/* * line discipline callback wrappers * * The wrappers maintain line discipline references @@ -1309,7 +1309,7 @@ static int startup(MGSLPC_INFO * info, struct tty_struct *tty) if (tty) clear_bit(TTY_IO_ERROR, &tty->flags); - tty_port_set_initialized(&info->port, 1); + tty_port_set_initialized(&info->port, true); return 0; } @@ -1359,7 +1359,7 @@ static void shutdown(MGSLPC_INFO * info, struct tty_struct *tty) if (tty) set_bit(TTY_IO_ERROR, &tty->flags); - tty_port_set_initialized(&info->port, 0); + tty_port_set_initialized(&info->port, false); } static void mgslpc_program_hw(MGSLPC_INFO *info, struct tty_struct *tty) @@ -2430,7 +2430,7 @@ static void mgslpc_hangup(struct tty_struct *tty) tty_port_hangup(&info->port); } -static int carrier_raised(struct tty_port *port) +static bool carrier_raised(struct tty_port *port) { MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port); unsigned long flags; @@ -2439,18 +2439,16 @@ static int carrier_raised(struct tty_port *port) get_signals(info); spin_unlock_irqrestore(&info->lock, flags); - if (info->serial_signals & SerialSignal_DCD) - return 1; - return 0; + return info->serial_signals & SerialSignal_DCD; } -static void dtr_rts(struct tty_port *port, int onoff) +static void dtr_rts(struct tty_port *port, bool active) { MGSLPC_INFO *info = container_of(port, MGSLPC_INFO, port); unsigned long flags; spin_lock_irqsave(&info->lock, flags); - if (onoff) + if (active) info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; else info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); @@ -3857,7 +3855,7 @@ static void tx_timeout(struct timer_list *t) #if SYNCLINK_GENERIC_HDLC -/** +/* * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) * set encoding and frame check sequence (FCS) options * @@ -3910,7 +3908,7 @@ static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, return 0; } -/** +/* * called by generic HDLC layer to send frame * * skb socket buffer containing HDLC frame @@ -3955,7 +3953,7 @@ static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } -/** +/* * called by network layer when interface enabled * claim resources and initialize hardware * @@ -4018,7 +4016,7 @@ static int hdlcdev_open(struct net_device *dev) return 0; } -/** +/* * called by network layer when interface is disabled * shutdown hardware and release resources * @@ -4049,7 +4047,7 @@ static int hdlcdev_close(struct net_device *dev) return 0; } -/** +/* * called by network layer to process IOCTL call to network device * * dev pointer to network device structure @@ -4152,7 +4150,7 @@ static int hdlcdev_wan_ioctl(struct net_device *dev, struct if_settings *ifs) } } -/** +/* * called by network layer when transmit timeout is detected * * dev pointer to network device structure @@ -4175,7 +4173,7 @@ static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue) netif_wake_queue(dev); } -/** +/* * called by device driver when transmit completes * reenable network layer transmit if stopped * @@ -4187,7 +4185,7 @@ static void hdlcdev_tx_done(MGSLPC_INFO *info) netif_wake_queue(info->netdev); } -/** +/* * called by device driver when frame received * pass frame to network layer * @@ -4227,7 +4225,7 @@ static const struct net_device_ops hdlcdev_ops = { .ndo_tx_timeout = hdlcdev_tx_timeout, }; -/** +/* * called by device driver when adding device instance * do generic HDLC initialization * @@ -4275,7 +4273,7 @@ static int hdlcdev_init(MGSLPC_INFO *info) return 0; } -/** +/* * called by device driver when removing device instance * do generic HDLC cleanup * diff --git a/drivers/char/virtio_console.c b/drivers/char/virtio_console.c index 6a821118d553..d5ac4d955bc8 100644 --- a/drivers/char/virtio_console.c +++ b/drivers/char/virtio_console.c @@ -1666,9 +1666,8 @@ static void handle_control_message(struct virtio_device *vdev, "Not enough space to store port name\n"); break; } - strncpy(port->name, buf->buf + buf->offset + sizeof(*cpkt), - name_size - 1); - port->name[name_size - 1] = 0; + strscpy(port->name, buf->buf + buf->offset + sizeof(*cpkt), + name_size); /* * Since we only have one sysfs attribute, 'name', diff --git a/drivers/comedi/Kconfig b/drivers/comedi/Kconfig index 3cb61fa2c5c3..9af280735cba 100644 --- a/drivers/comedi/Kconfig +++ b/drivers/comedi/Kconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -config COMEDI +menuconfig COMEDI tristate "Data acquisition support (comedi)" help Enable support for a wide range of data acquisition devices diff --git a/drivers/comedi/comedi_fops.c b/drivers/comedi/comedi_fops.c index e2114bcf815a..b982903aaa46 100644 --- a/drivers/comedi/comedi_fops.c +++ b/drivers/comedi/comedi_fops.c @@ -1215,6 +1215,7 @@ static int check_insn_config_length(struct comedi_insn *insn, case INSN_CONFIG_GET_CLOCK_SRC: case INSN_CONFIG_SET_OTHER_SRC: case INSN_CONFIG_GET_COUNTER_STATUS: + case INSN_CONFIG_GET_PWM_OUTPUT: case INSN_CONFIG_PWM_SET_H_BRIDGE: case INSN_CONFIG_PWM_GET_H_BRIDGE: case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE: diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig index d388bf26f4dc..b5ba8fb02cf7 100644 --- a/drivers/counter/Kconfig +++ b/drivers/counter/Kconfig @@ -29,6 +29,28 @@ config 104_QUAD_8 array module parameter. The interrupt line numbers for the devices may be configured via the irq array module parameter. +config FTM_QUADDEC + tristate "Flex Timer Module Quadrature decoder driver" + depends on SOC_LS1021A || COMPILE_TEST + depends on HAS_IOMEM && OF + help + Select this option to enable the Flex Timer Quadrature decoder + driver. + + To compile this driver as a module, choose M here: the + module will be called ftm-quaddec. + +config INTEL_QEP + tristate "Intel Quadrature Encoder Peripheral driver" + depends on X86 + depends on PCI + help + Select this option to enable the Intel Quadrature Encoder Peripheral + driver. + + To compile this driver as a module, choose M here: the module + will be called intel-qep. + config INTERRUPT_CNT tristate "Interrupt counter driver" depends on GPIOLIB @@ -39,15 +61,17 @@ config INTERRUPT_CNT To compile this driver as a module, choose M here: the module will be called interrupt-cnt. -config STM32_TIMER_CNT - tristate "STM32 Timer encoder counter driver" - depends on MFD_STM32_TIMERS || COMPILE_TEST +config MICROCHIP_TCB_CAPTURE + tristate "Microchip Timer Counter Capture driver" + depends on SOC_AT91SAM9 || SOC_SAM_V7 || COMPILE_TEST + depends on HAS_IOMEM && OF + select REGMAP_MMIO help - Select this option to enable STM32 Timer quadrature encoder - and counter driver. + Select this option to enable the Microchip Timer Counter Block + capture driver. To compile this driver as a module, choose M here: the - module will be called stm32-timer-cnt. + module will be called microchip-tcb-capture. config STM32_LPTIMER_CNT tristate "STM32 LP Timer encoder counter driver" @@ -59,47 +83,15 @@ config STM32_LPTIMER_CNT To compile this driver as a module, choose M here: the module will be called stm32-lptimer-cnt. -config TI_EQEP - tristate "TI eQEP counter driver" - depends on (SOC_AM33XX || COMPILE_TEST) - select REGMAP_MMIO +config STM32_TIMER_CNT + tristate "STM32 Timer encoder counter driver" + depends on MFD_STM32_TIMERS || COMPILE_TEST help - Select this option to enable the Texas Instruments Enhanced Quadrature - Encoder Pulse (eQEP) counter driver. - - To compile this driver as a module, choose M here: the module will be - called ti-eqep. - -config FTM_QUADDEC - tristate "Flex Timer Module Quadrature decoder driver" - depends on HAS_IOMEM && OF - help - Select this option to enable the Flex Timer Quadrature decoder - driver. + Select this option to enable STM32 Timer quadrature encoder + and counter driver. To compile this driver as a module, choose M here: the - module will be called ftm-quaddec. - -config MICROCHIP_TCB_CAPTURE - tristate "Microchip Timer Counter Capture driver" - depends on HAS_IOMEM && OF - select REGMAP_MMIO - help - Select this option to enable the Microchip Timer Counter Block - capture driver. - - To compile this driver as a module, choose M here: the - module will be called microchip-tcb-capture. - -config INTEL_QEP - tristate "Intel Quadrature Encoder Peripheral driver" - depends on PCI - help - Select this option to enable the Intel Quadrature Encoder Peripheral - driver. - - To compile this driver as a module, choose M here: the module - will be called intel-qep. + module will be called stm32-timer-cnt. config TI_ECAP_CAPTURE tristate "TI eCAP capture driver" @@ -116,4 +108,15 @@ config TI_ECAP_CAPTURE To compile this driver as a module, choose M here: the module will be called ti-ecap-capture. +config TI_EQEP + tristate "TI eQEP counter driver" + depends on (SOC_AM33XX || COMPILE_TEST) + select REGMAP_MMIO + help + Select this option to enable the Texas Instruments Enhanced Quadrature + Encoder Pulse (eQEP) counter driver. + + To compile this driver as a module, choose M here: the module will be + called ti-eqep. + endif # COUNTER diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 133d1c07b3a7..e4c84433a88a 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -357,6 +357,16 @@ struct hisi_qm_resource { struct list_head list; }; +/** + * struct qm_hw_err - Structure describing the device errors + * @list: hardware error list + * @timestamp: timestamp when the error occurred + */ +struct qm_hw_err { + struct list_head list; + unsigned long long timestamp; +}; + struct hisi_qm_hw_ops { int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number); void (*qm_db)(struct hisi_qm *qm, u16 qn, @@ -2458,6 +2468,113 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd, return -EINVAL; } +/** + * qm_hw_err_isolate() - Try to set the isolation status of the uacce device + * according to user's configuration of error threshold. + * @qm: the uacce device + */ +static int qm_hw_err_isolate(struct hisi_qm *qm) +{ + struct qm_hw_err *err, *tmp, *hw_err; + struct qm_err_isolate *isolate; + u32 count = 0; + + isolate = &qm->isolate_data; + +#define SECONDS_PER_HOUR 3600 + + /* All the hw errs are processed by PF driver */ + if (qm->uacce->is_vf || isolate->is_isolate || !isolate->err_threshold) + return 0; + + hw_err = kzalloc(sizeof(*hw_err), GFP_KERNEL); + if (!hw_err) + return -ENOMEM; + + /* + * Time-stamp every slot AER error. Then check the AER error log when the + * next device AER error occurred. if the device slot AER error count exceeds + * the setting error threshold in one hour, the isolated state will be set + * to true. And the AER error logs that exceed one hour will be cleared. + */ + mutex_lock(&isolate->isolate_lock); + hw_err->timestamp = jiffies; + list_for_each_entry_safe(err, tmp, &isolate->qm_hw_errs, list) { + if ((hw_err->timestamp - err->timestamp) / HZ > + SECONDS_PER_HOUR) { + list_del(&err->list); + kfree(err); + } else { + count++; + } + } + list_add(&hw_err->list, &isolate->qm_hw_errs); + mutex_unlock(&isolate->isolate_lock); + + if (count >= isolate->err_threshold) + isolate->is_isolate = true; + + return 0; +} + +static void qm_hw_err_destroy(struct hisi_qm *qm) +{ + struct qm_hw_err *err, *tmp; + + mutex_lock(&qm->isolate_data.isolate_lock); + list_for_each_entry_safe(err, tmp, &qm->isolate_data.qm_hw_errs, list) { + list_del(&err->list); + kfree(err); + } + mutex_unlock(&qm->isolate_data.isolate_lock); +} + +static enum uacce_dev_state hisi_qm_get_isolate_state(struct uacce_device *uacce) +{ + struct hisi_qm *qm = uacce->priv; + struct hisi_qm *pf_qm; + + if (uacce->is_vf) + pf_qm = pci_get_drvdata(pci_physfn(qm->pdev)); + else + pf_qm = qm; + + return pf_qm->isolate_data.is_isolate ? + UACCE_DEV_ISOLATE : UACCE_DEV_NORMAL; +} + +static int hisi_qm_isolate_threshold_write(struct uacce_device *uacce, u32 num) +{ + struct hisi_qm *qm = uacce->priv; + + /* Must be set by PF */ + if (uacce->is_vf) + return -EPERM; + + if (qm->isolate_data.is_isolate) + return -EPERM; + + qm->isolate_data.err_threshold = num; + + /* After the policy is updated, need to reset the hardware err list */ + qm_hw_err_destroy(qm); + + return 0; +} + +static u32 hisi_qm_isolate_threshold_read(struct uacce_device *uacce) +{ + struct hisi_qm *qm = uacce->priv; + struct hisi_qm *pf_qm; + + if (uacce->is_vf) { + pf_qm = pci_get_drvdata(pci_physfn(qm->pdev)); + return pf_qm->isolate_data.err_threshold; + } + + return qm->isolate_data.err_threshold; +} + static const struct uacce_ops uacce_qm_ops = { .get_available_instances = hisi_qm_get_available_instances, .get_queue = hisi_qm_uacce_get_queue, @@ -2467,8 +2584,22 @@ static const struct uacce_ops uacce_qm_ops = { .mmap = hisi_qm_uacce_mmap, .ioctl = hisi_qm_uacce_ioctl, .is_q_updated = hisi_qm_is_q_updated, + .get_isolate_state = hisi_qm_get_isolate_state, + .isolate_err_threshold_write = hisi_qm_isolate_threshold_write, + .isolate_err_threshold_read = hisi_qm_isolate_threshold_read, }; +static void qm_remove_uacce(struct hisi_qm *qm) +{ + struct uacce_device *uacce = qm->uacce; + + if (qm->use_sva) { + qm_hw_err_destroy(qm); + uacce_remove(uacce); + qm->uacce = NULL; + } +} + static int qm_alloc_uacce(struct hisi_qm *qm) { struct pci_dev *pdev = qm->pdev; @@ -2495,8 +2626,7 @@ static int qm_alloc_uacce(struct hisi_qm *qm) qm->use_sva = true; } else { /* only consider sva case */ - uacce_remove(uacce); - qm->uacce = NULL; + qm_remove_uacce(qm); return -EINVAL; } @@ -2529,6 +2659,8 @@ static int qm_alloc_uacce(struct hisi_qm *qm) uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr; qm->uacce = uacce; + INIT_LIST_HEAD(&qm->isolate_data.qm_hw_errs); + mutex_init(&qm->isolate_data.isolate_lock); return 0; } @@ -4017,6 +4149,12 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm) return ret; } + if (qm->use_sva) { + ret = qm_hw_err_isolate(qm); + if (ret) + pci_err(pdev, "failed to isolate hw err!\n"); + } + ret = qm_wait_vf_prepare_finish(qm); if (ret) pci_err(pdev, "failed to stop by vfs in soft reset!\n"); @@ -4321,21 +4459,25 @@ static int qm_controller_reset(struct hisi_qm *qm) qm->err_ini->show_last_dfx_regs(qm); ret = qm_soft_reset(qm); - if (ret) { - pci_err(pdev, "Controller reset failed (%d)\n", ret); - qm_reset_bit_clear(qm); - return ret; - } + if (ret) + goto err_reset; ret = qm_controller_reset_done(qm); - if (ret) { - qm_reset_bit_clear(qm); - return ret; - } + if (ret) + goto err_reset; pci_info(pdev, "Controller reset complete\n"); return 0; + +err_reset: + pci_err(pdev, "Controller reset failed (%d)\n", ret); + qm_reset_bit_clear(qm); + + /* if resetting fails, isolate the device */ + if (qm->use_sva) + qm->isolate_data.is_isolate = true; + return ret; } /** @@ -5255,10 +5397,7 @@ int hisi_qm_init(struct hisi_qm *qm) err_free_qm_memory: hisi_qm_memory_uninit(qm); err_alloc_uacce: - if (qm->use_sva) { - uacce_remove(qm->uacce); - qm->uacce = NULL; - } + qm_remove_uacce(qm); err_irq_register: qm_irqs_unregister(qm); err_pci_init: diff --git a/drivers/firmware/dmi-sysfs.c b/drivers/firmware/dmi-sysfs.c index 66727ad3361b..ed5aff0a4204 100644 --- a/drivers/firmware/dmi-sysfs.c +++ b/drivers/firmware/dmi-sysfs.c @@ -418,10 +418,10 @@ static ssize_t dmi_sel_raw_read_helper(struct dmi_sysfs_entry *entry, return dmi_sel_raw_read_phys32(entry, &sel, state->buf, state->pos, state->count); case DMI_SEL_ACCESS_METHOD_GPNV: - pr_info("dmi-sysfs: GPNV support missing.\n"); + pr_info_ratelimited("dmi-sysfs: GPNV support missing.\n"); return -EIO; default: - pr_info("dmi-sysfs: Unknown access method %02x\n", + pr_info_ratelimited("dmi-sysfs: Unknown access method %02x\n", sel.access_method); return -EIO; } @@ -603,16 +603,16 @@ static void __init dmi_sysfs_register_handle(const struct dmi_header *dh, *ret = kobject_init_and_add(&entry->kobj, &dmi_sysfs_entry_ktype, NULL, "%d-%d", dh->type, entry->instance); - if (*ret) { - kobject_put(&entry->kobj); - return; - } - /* Thread on the global list for cleanup */ spin_lock(&entry_list_lock); list_add_tail(&entry->list, &entry_list); spin_unlock(&entry_list_lock); + if (*ret) { + kobject_put(&entry->kobj); + return; + } + /* Handle specializations by type */ switch (dh->type) { case DMI_ENTRY_SYSTEM_EVENT_LOG: diff --git a/drivers/firmware/google/Kconfig b/drivers/firmware/google/Kconfig index 9f190eab43ed..1bc7cbf2f65d 100644 --- a/drivers/firmware/google/Kconfig +++ b/drivers/firmware/google/Kconfig @@ -44,14 +44,6 @@ config GOOGLE_COREBOOT_TABLE device tree node /firmware/coreboot. If unsure say N. -config GOOGLE_COREBOOT_TABLE_ACPI - tristate - select GOOGLE_COREBOOT_TABLE - -config GOOGLE_COREBOOT_TABLE_OF - tristate - select GOOGLE_COREBOOT_TABLE - config GOOGLE_MEMCONSOLE tristate depends on GOOGLE_MEMCONSOLE_X86_LEGACY || GOOGLE_MEMCONSOLE_COREBOOT diff --git a/drivers/firmware/google/framebuffer-coreboot.c b/drivers/firmware/google/framebuffer-coreboot.c index c6dcc1ef93ac..c323a818805c 100644 --- a/drivers/firmware/google/framebuffer-coreboot.c +++ b/drivers/firmware/google/framebuffer-coreboot.c @@ -43,9 +43,7 @@ static int framebuffer_probe(struct coreboot_device *dev) fb->green_mask_pos == formats[i].green.offset && fb->green_mask_size == formats[i].green.length && fb->blue_mask_pos == formats[i].blue.offset && - fb->blue_mask_size == formats[i].blue.length && - fb->reserved_mask_pos == formats[i].transp.offset && - fb->reserved_mask_size == formats[i].transp.length) + fb->blue_mask_size == formats[i].blue.length) pdata.format = formats[i].name; } if (!pdata.format) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index b4081f4d88a3..bde1f543f529 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -1138,13 +1138,17 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) /* allocate service controller and supporting channel */ controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); - if (!controller) - return -ENOMEM; + if (!controller) { + ret = -ENOMEM; + goto err_destroy_pool; + } chans = devm_kmalloc_array(dev, SVC_NUM_CHANNEL, sizeof(*chans), GFP_KERNEL | __GFP_ZERO); - if (!chans) - return -ENOMEM; + if (!chans) { + ret = -ENOMEM; + goto err_destroy_pool; + } controller->dev = dev; controller->num_chans = SVC_NUM_CHANNEL; @@ -1159,7 +1163,7 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) ret = kfifo_alloc(&controller->svc_fifo, fifo_size, GFP_KERNEL); if (ret) { dev_err(dev, "failed to allocate FIFO\n"); - return ret; + goto err_destroy_pool; } spin_lock_init(&controller->svc_fifo_lock); @@ -1198,19 +1202,20 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) ret = platform_device_add(svc->stratix10_svc_rsu); if (ret) { platform_device_put(svc->stratix10_svc_rsu); - return ret; + goto err_free_kfifo; } svc->intel_svc_fcs = platform_device_alloc(INTEL_FCS, 1); if (!svc->intel_svc_fcs) { dev_err(dev, "failed to allocate %s device\n", INTEL_FCS); - return -ENOMEM; + ret = -ENOMEM; + goto err_unregister_dev; } ret = platform_device_add(svc->intel_svc_fcs); if (ret) { platform_device_put(svc->intel_svc_fcs); - return ret; + goto err_unregister_dev; } dev_set_drvdata(dev, svc); @@ -1219,8 +1224,12 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) return 0; +err_unregister_dev: + platform_device_unregister(svc->stratix10_svc_rsu); err_free_kfifo: kfifo_free(&controller->svc_fifo); +err_destroy_pool: + gen_pool_destroy(genpool); return ret; } diff --git a/drivers/fpga/dfl-afu-region.c b/drivers/fpga/dfl-afu-region.c index 0804b7a0c298..2e7b41629406 100644 --- a/drivers/fpga/dfl-afu-region.c +++ b/drivers/fpga/dfl-afu-region.c @@ -39,6 +39,7 @@ static struct dfl_afu_mmio_region *get_region_by_index(struct dfl_afu *afu, /** * afu_mmio_region_add - add a mmio region to given feature dev. * + * @pdata: afu platform device's pdata. * @region_index: region index. * @region_size: region size. * @phys: region's physical address of this region. diff --git a/drivers/fpga/dfl-afu.h b/drivers/fpga/dfl-afu.h index e5020e2b1f3d..674e9772f0ea 100644 --- a/drivers/fpga/dfl-afu.h +++ b/drivers/fpga/dfl-afu.h @@ -41,7 +41,7 @@ struct dfl_afu_mmio_region { }; /** - * struct fpga_afu_dma_region - afu DMA region data structure + * struct dfl_afu_dma_region - afu DMA region data structure * * @user_addr: region userspace virtual address. * @length: region length. diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c index 587c82be12f7..7422d2bc6f37 100644 --- a/drivers/fpga/dfl-fme-perf.c +++ b/drivers/fpga/dfl-fme-perf.c @@ -141,7 +141,7 @@ * @fab_port_id: used to indicate current working mode of fabric counters. * @fab_lock: lock to protect fabric counters working mode. * @cpu: active CPU to which the PMU is bound for accesses. - * @cpuhp_node: node for CPU hotplug notifier link. + * @node: node for CPU hotplug notifier link. * @cpuhp_state: state for CPU hotplug notification; */ struct fme_perf_priv { diff --git a/drivers/fpga/dfl-fme-pr.c b/drivers/fpga/dfl-fme-pr.c index d61ce9a18879..cdcf6dea4cc9 100644 --- a/drivers/fpga/dfl-fme-pr.c +++ b/drivers/fpga/dfl-fme-pr.c @@ -164,7 +164,7 @@ free_exit: /** * dfl_fme_create_mgr - create fpga mgr platform device as child device - * + * @feature: sub feature info * @pdata: fme platform_device's pdata * * Return: mgr platform device if successful, and error code otherwise. @@ -273,7 +273,7 @@ static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br) } /** - * dfl_fme_destroy_bridge - destroy all fpga bridge platform device + * dfl_fme_destroy_bridges - destroy all fpga bridge platform device * @pdata: fme platform device's pdata */ static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata) diff --git a/drivers/fpga/dfl-fme-pr.h b/drivers/fpga/dfl-fme-pr.h index 096a699089d3..761f80f63312 100644 --- a/drivers/fpga/dfl-fme-pr.h +++ b/drivers/fpga/dfl-fme-pr.h @@ -58,7 +58,7 @@ struct dfl_fme_bridge { }; /** - * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device. + * struct dfl_fme_br_pdata - platform data for FME bridge platform device. * * @cdev: container device. * @port_id: port id. diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index b9aae85ba930..b010f0a83a78 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "dfl.h" @@ -45,7 +46,7 @@ static const char *dfl_pdata_key_strings[DFL_ID_MAX] = { }; /** - * dfl_dev_info - dfl feature device information. + * struct dfl_dev_info - dfl feature device information. * @name: name string of the feature platform device. * @dfh_id: id value in Device Feature Header (DFH) register by DFL spec. * @id: idr id of the feature dev. @@ -67,7 +68,7 @@ static struct dfl_dev_info dfl_devs[] = { }; /** - * dfl_chardev_info - chardev information of dfl feature device + * struct dfl_chardev_info - chardev information of dfl feature device * @name: nmae string of the char device. * @devt: devt of the char device. */ @@ -342,6 +343,8 @@ static void release_dfl_dev(struct device *dev) if (ddev->mmio_res.parent) release_resource(&ddev->mmio_res); + kfree(ddev->params); + ida_free(&dfl_device_ida, ddev->id); kfree(ddev->irqs); kfree(ddev); @@ -380,7 +383,16 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->type = feature_dev_id_type(pdev); ddev->feature_id = feature->id; ddev->revision = feature->revision; + ddev->dfh_version = feature->dfh_version; ddev->cdev = pdata->dfl_cdev; + if (feature->param_size) { + ddev->params = kmemdup(feature->params, feature->param_size, GFP_KERNEL); + if (!ddev->params) { + ret = -ENOMEM; + goto put_dev; + } + ddev->param_size = feature->param_size; + } /* add mmio resource */ parent_res = &pdev->resource[feature->resource_index]; @@ -708,20 +720,27 @@ struct build_feature_devs_info { * struct dfl_feature_info - sub feature info collected during feature dev build * * @fid: id of this sub feature. + * @revision: revision of this sub feature + * @dfh_version: version of Device Feature Header (DFH) * @mmio_res: mmio resource of this sub feature. * @ioaddr: mapped base address of mmio resource. * @node: node in sub_features linked list. * @irq_base: start of irq index in this sub feature. * @nr_irqs: number of irqs of this sub feature. + * @param_size: size DFH parameters. + * @params: DFH parameter data. */ struct dfl_feature_info { u16 fid; u8 revision; + u8 dfh_version; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; unsigned int irq_base; unsigned int nr_irqs; + unsigned int param_size; + u64 params[]; }; static void dfl_fpga_cdev_add_port_dev(struct dfl_fpga_cdev *cdev, @@ -797,7 +816,17 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) feature->dev = fdev; feature->id = finfo->fid; feature->revision = finfo->revision; + feature->dfh_version = finfo->dfh_version; + if (finfo->param_size) { + feature->params = devm_kmemdup(binfo->dev, + finfo->params, finfo->param_size, + GFP_KERNEL); + if (!feature->params) + return -ENOMEM; + + feature->param_size = finfo->param_size; + } /* * the FIU header feature has some fundamental functions (sriov * set, port enable/disable) needed for the dfl bus device and @@ -934,56 +963,115 @@ static u16 feature_id(u64 value) return 0; } +static u64 *find_param(u64 *params, resource_size_t max, int param_id) +{ + u64 *end = params + max / sizeof(u64); + u64 v, next; + + while (params < end) { + v = *params; + if (param_id == FIELD_GET(DFHv1_PARAM_HDR_ID, v)) + return params; + + if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v)) + break; + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + params += next; + } + + return NULL; +} + +/** + * dfh_find_param() - find parameter block for the given parameter id + * @dfl_dev: dfl device + * @param_id: id of dfl parameter + * @psize: destination to store size of parameter data in bytes + * + * Return: pointer to start of parameter data, PTR_ERR otherwise. + */ +void *dfh_find_param(struct dfl_device *dfl_dev, int param_id, size_t *psize) +{ + u64 *phdr = find_param(dfl_dev->params, dfl_dev->param_size, param_id); + + if (!phdr) + return ERR_PTR(-ENOENT); + + if (psize) + *psize = (FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, *phdr) - 1) * sizeof(u64); + + return phdr + 1; +} +EXPORT_SYMBOL_GPL(dfh_find_param); + static int parse_feature_irqs(struct build_feature_devs_info *binfo, - resource_size_t ofst, u16 fid, - unsigned int *irq_base, unsigned int *nr_irqs) + resource_size_t ofst, struct dfl_feature_info *finfo) { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + void *params = finfo->params; enum dfl_id_type type; + u16 fid = finfo->fid; int virq; + u64 *p; u64 v; - type = feature_dev_id_type(binfo->feature_dev); + switch (finfo->dfh_version) { + case 0: + /* + * DFHv0 only provides MMIO resource information for each feature + * in the DFL header. There is no generic interrupt information. + * Instead, features with interrupt functionality provide + * the information in feature specific registers. + */ + type = feature_dev_id_type(binfo->feature_dev); + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + switch (fid) { + case FME_FEATURE_ID_GLOBAL_ERR: + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + break; + } + } + break; - /* - * Ideally DFL framework should only read info from DFL header, but - * current version DFL only provides mmio resources information for - * each feature in DFL Header, no field for interrupt resources. - * Interrupt resource information is provided by specific mmio - * registers of each private feature which supports interrupt. So in - * order to parse and assign irq resources, DFL framework has to look - * into specific capability registers of these private features. - * - * Once future DFL version supports generic interrupt resource - * information in common DFL headers, the generic interrupt parsing - * code will be added. But in order to be compatible to old version - * DFL, the driver may still fall back to these quirks. - */ - if (type == PORT_ID) { - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + case 1: + /* + * DFHv1 provides interrupt resource information in DFHv1 + * parameter blocks. + */ + p = find_param(params, finfo->param_size, DFHv1_PARAM_ID_MSI_X); + if (!p) break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); - break; - } - } else if (type == FME_ID) { - if (fid == FME_FEATURE_ID_GLOBAL_ERR) { - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - } + + p++; + ibase = FIELD_GET(DFHv1_PARAM_MSI_X_STARTV, *p); + inr = FIELD_GET(DFHv1_PARAM_MSI_X_NUMV, *p); + break; + + default: + dev_warn(binfo->dev, "unexpected DFH version %d\n", finfo->dfh_version); + break; } if (!inr) { - *irq_base = 0; - *nr_irqs = 0; + finfo->irq_base = 0; + finfo->nr_irqs = 0; return 0; } @@ -1006,12 +1094,37 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, } } - *irq_base = ibase; - *nr_irqs = inr; + finfo->irq_base = ibase; + finfo->nr_irqs = inr; return 0; } +static int dfh_get_param_size(void __iomem *dfh_base, resource_size_t max) +{ + int size = 0; + u64 v, next; + + if (!FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, + readq(dfh_base + DFHv1_CSR_SIZE_GRP))) + return 0; + + while (size + DFHv1_PARAM_HDR < max) { + v = readq(dfh_base + DFHv1_PARAM_HDR + size); + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + if (!next) + return -EINVAL; + + size += next * sizeof(u64); + + if (FIELD_GET(DFHv1_PARAM_HDR_NEXT_EOP, v)) + return size; + } + + return -ENOENT; +} + /* * when create sub feature instances, for private features, it doesn't need * to provide resource size and feature id as they could be read from DFH @@ -1023,39 +1136,69 @@ static int create_feature_instance(struct build_feature_devs_info *binfo, resource_size_t ofst, resource_size_t size, u16 fid) { - unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; + resource_size_t start, end; + int dfh_psize = 0; u8 revision = 0; + u64 v, addr_off; + u8 dfh_ver = 0; int ret; - u64 v; if (fid != FEATURE_ID_AFU) { v = readq(binfo->ioaddr + ofst); revision = FIELD_GET(DFH_REVISION, v); - + dfh_ver = FIELD_GET(DFH_VERSION, v); /* read feature size and id if inputs are invalid */ size = size ? size : feature_size(v); fid = fid ? fid : feature_id(v); + if (dfh_ver == 1) { + dfh_psize = dfh_get_param_size(binfo->ioaddr + ofst, size); + if (dfh_psize < 0) { + dev_err(binfo->dev, + "failed to read size of DFHv1 parameters %d\n", + dfh_psize); + return dfh_psize; + } + dev_dbg(binfo->dev, "dfhv1_psize %d\n", dfh_psize); + } } if (binfo->len - ofst < size) return -EINVAL; - ret = parse_feature_irqs(binfo, ofst, fid, &irq_base, &nr_irqs); - if (ret) - return ret; - - finfo = kzalloc(sizeof(*finfo), GFP_KERNEL); + finfo = kzalloc(struct_size(finfo, params, dfh_psize / sizeof(u64)), GFP_KERNEL); if (!finfo) return -ENOMEM; + memcpy_fromio(finfo->params, binfo->ioaddr + ofst + DFHv1_PARAM_HDR, dfh_psize); + finfo->param_size = dfh_psize; + finfo->fid = fid; finfo->revision = revision; - finfo->mmio_res.start = binfo->start + ofst; - finfo->mmio_res.end = finfo->mmio_res.start + size - 1; + finfo->dfh_version = dfh_ver; + if (dfh_ver == 1) { + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR); + addr_off = FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + if (FIELD_GET(DFHv1_CSR_ADDR_REL, v)) + start = addr_off << 1; + else + start = binfo->start + ofst + addr_off; + + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP); + end = start + FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v) - 1; + } else { + start = binfo->start + ofst; + end = start + size - 1; + } finfo->mmio_res.flags = IORESOURCE_MEM; - finfo->irq_base = irq_base; - finfo->nr_irqs = nr_irqs; + finfo->mmio_res.start = start; + finfo->mmio_res.end = end; + + ret = parse_feature_irqs(binfo, ofst, finfo); + if (ret) { + kfree(finfo); + return ret; + } list_add_tail(&finfo->node, &binfo->sub_features); binfo->feature_num++; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 06cfcd5e84bb..1d724a28f00a 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -74,11 +74,47 @@ #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ #define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */ #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ #define DFH_TYPE_AFU 1 #define DFH_TYPE_PRIVATE 3 #define DFH_TYPE_FIU 4 +/* + * DFHv1 Register Offset definitons + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA + * as common header registers + */ +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */ +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */ +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */ + +/* + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start), + * 1'b1 = absolute (ARM or other non-PCIe use) + */ +#define DFHv1_CSR_ADDR_REL BIT_ULL(0) + +/* CSR Header Register Bit Definitions */ +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */ + +/* CSR SIZE Goup Register Bit Definitions */ +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */ +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */ +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */ +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */ + +/* PARAM Header Register Bit Definitions */ +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */ +#define DFHv1_PARAM_HDR_VER GENMASK_ULL(31, 16) /* Version Param */ +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 35) /* Offset of next Param */ +#define DFHv1_PARAM_HDR_NEXT_EOP BIT_ULL(32) +#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */ + +#define DFHv1_PARAM_ID_MSI_X 0x1 +#define DFHv1_PARAM_MSI_X_NUMV GENMASK_ULL(63, 32) +#define DFHv1_PARAM_MSI_X_STARTV GENMASK_ULL(31, 0) + /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ @@ -231,6 +267,7 @@ struct dfl_feature_irq_ctx { * * @dev: ptr to pdev of the feature device which has the sub feature. * @id: sub feature id. + * @revision: revision of this sub feature. * @resource_index: each sub feature has one mmio resource for its registers. * this index is used to find its mmio resource from the * feature dev (platform device)'s resources. @@ -240,6 +277,9 @@ struct dfl_feature_irq_ctx { * @ops: ops of this sub feature. * @ddev: ptr to the dfl device of this sub feature. * @priv: priv data of this feature. + * @dfh_version: version of the DFH + * @param_size: size of dfh parameters + * @params: point to memory copy of dfh parameters */ struct dfl_feature { struct platform_device *dev; @@ -252,6 +292,9 @@ struct dfl_feature { const struct dfl_feature_ops *ops; struct dfl_device *ddev; void *priv; + u8 dfh_version; + unsigned int param_size; + void *params; }; #define FEATURE_DEV_ID_UNUSED (-1) diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index 727704431f61..5cd40acab5bf 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -293,12 +293,15 @@ static ssize_t state_show(struct device *dev, struct device_attribute *attr, char *buf) { struct fpga_bridge *bridge = to_fpga_bridge(dev); - int enable = 1; + int state = 1; - if (bridge->br_ops && bridge->br_ops->enable_show) - enable = bridge->br_ops->enable_show(bridge); + if (bridge->br_ops && bridge->br_ops->enable_show) { + state = bridge->br_ops->enable_show(bridge); + if (state < 0) + return state; + } - return sprintf(buf, "%s\n", enable ? "enabled" : "disabled"); + return sysfs_emit(buf, "%s\n", state ? "enabled" : "disabled"); } static DEVICE_ATTR_RO(name); diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c index 7436976ea904..d6070e7f5205 100644 --- a/drivers/fpga/microchip-spi.c +++ b/drivers/fpga/microchip-spi.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -33,7 +34,7 @@ #define MPF_BITS_PER_COMPONENT_SIZE 22 -#define MPF_STATUS_POLL_RETRIES 10000 +#define MPF_STATUS_POLL_TIMEOUT (2 * USEC_PER_SEC) #define MPF_STATUS_BUSY BIT(0) #define MPF_STATUS_READY BIT(1) #define MPF_STATUS_SPI_VIOLATION BIT(2) @@ -42,46 +43,55 @@ struct mpf_priv { struct spi_device *spi; bool program_mode; + u8 tx __aligned(ARCH_KMALLOC_MINALIGN); + u8 rx; }; -static int mpf_read_status(struct spi_device *spi) +static int mpf_read_status(struct mpf_priv *priv) { - u8 status = 0, status_command = MPF_SPI_READ_STATUS; - struct spi_transfer xfers[2] = { 0 }; - int ret; - /* * HW status is returned on MISO in the first byte after CS went * active. However, first reading can be inadequate, so we submit * two identical SPI transfers and use result of the later one. */ - xfers[0].tx_buf = &status_command; - xfers[1].tx_buf = &status_command; - xfers[0].rx_buf = &status; - xfers[1].rx_buf = &status; - xfers[0].len = 1; - xfers[1].len = 1; - xfers[0].cs_change = 1; + struct spi_transfer xfers[2] = { + { + .tx_buf = &priv->tx, + .rx_buf = &priv->rx, + .len = 1, + .cs_change = 1, + }, { + .tx_buf = &priv->tx, + .rx_buf = &priv->rx, + .len = 1, + }, + }; + u8 status; + int ret; - ret = spi_sync_transfer(spi, xfers, 2); + priv->tx = MPF_SPI_READ_STATUS; + + ret = spi_sync_transfer(priv->spi, xfers, 2); + if (ret) + return ret; + + status = priv->rx; if ((status & MPF_STATUS_SPI_VIOLATION) || (status & MPF_STATUS_SPI_ERROR)) - ret = -EIO; + return -EIO; - return ret ? : status; + return status; } static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr) { struct mpf_priv *priv = mgr->priv; - struct spi_device *spi; bool program_mode; int status; - spi = priv->spi; program_mode = priv->program_mode; - status = mpf_read_status(spi); + status = mpf_read_status(priv); if (!program_mode && !status) return FPGA_MGR_STATE_OPERATING; @@ -185,52 +195,53 @@ static int mpf_ops_parse_header(struct fpga_manager *mgr, return 0; } -/* Poll HW status until busy bit is cleared and mask bits are set. */ -static int mpf_poll_status(struct spi_device *spi, u8 mask) +static int mpf_poll_status(struct mpf_priv *priv, u8 mask) { - int status, retries = MPF_STATUS_POLL_RETRIES; + int ret, status; - while (retries--) { - status = mpf_read_status(spi); - if (status < 0) - return status; + /* + * Busy poll HW status. Polling stops if any of the following + * conditions are met: + * - timeout is reached + * - mpf_read_status() returns an error + * - busy bit is cleared AND mask bits are set + */ + ret = read_poll_timeout(mpf_read_status, status, + (status < 0) || + ((status & (MPF_STATUS_BUSY | mask)) == mask), + 0, MPF_STATUS_POLL_TIMEOUT, false, priv); + if (ret < 0) + return ret; - if (status & MPF_STATUS_BUSY) - continue; - - if (!mask || (status & mask)) - return status; - } - - return -EBUSY; + return status; } -static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size) +static int mpf_spi_write(struct mpf_priv *priv, const void *buf, size_t buf_size) { - int status = mpf_poll_status(spi, 0); + int status = mpf_poll_status(priv, 0); if (status < 0) return status; - return spi_write(spi, buf, buf_size); + return spi_write_then_read(priv->spi, buf, buf_size, NULL, 0); } -static int mpf_spi_write_then_read(struct spi_device *spi, +static int mpf_spi_write_then_read(struct mpf_priv *priv, const void *txbuf, size_t txbuf_size, void *rxbuf, size_t rxbuf_size) { const u8 read_command[] = { MPF_SPI_READ_DATA }; int ret; - ret = mpf_spi_write(spi, txbuf, txbuf_size); + ret = mpf_spi_write(priv, txbuf, txbuf_size); if (ret) return ret; - ret = mpf_poll_status(spi, MPF_STATUS_READY); + ret = mpf_poll_status(priv, MPF_STATUS_READY); if (ret < 0) return ret; - return spi_write_then_read(spi, read_command, sizeof(read_command), + return spi_write_then_read(priv->spi, read_command, sizeof(read_command), rxbuf, rxbuf_size); } @@ -242,7 +253,6 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; - struct spi_device *spi; u32 isc_ret = 0; int ret; @@ -251,9 +261,7 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, return -EOPNOTSUPP; } - spi = priv->spi; - - ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command), + ret = mpf_spi_write_then_read(priv, isc_en_command, sizeof(isc_en_command), &isc_ret, sizeof(isc_ret)); if (ret || isc_ret) { dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n", @@ -261,7 +269,7 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, return -EFAULT; } - ret = mpf_spi_write(spi, program_mode, sizeof(program_mode)); + ret = mpf_spi_write(priv, program_mode, sizeof(program_mode)); if (ret) { dev_err(dev, "Failed to enter program mode: %d\n", ret); return ret; @@ -272,13 +280,32 @@ static int mpf_ops_write_init(struct fpga_manager *mgr, return 0; } +static int mpf_spi_frame_write(struct mpf_priv *priv, const char *buf) +{ + struct spi_transfer xfers[2] = { + { + .tx_buf = &priv->tx, + .len = 1, + }, { + .tx_buf = buf, + .len = MPF_SPI_FRAME_SIZE, + }, + }; + int ret; + + ret = mpf_poll_status(priv, 0); + if (ret < 0) + return ret; + + priv->tx = MPF_SPI_FRAME; + + return spi_sync_transfer(priv->spi, xfers, ARRAY_SIZE(xfers)); +} + static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count) { - u8 spi_frame_command[] = { MPF_SPI_FRAME }; - struct spi_transfer xfers[2] = { 0 }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; - struct spi_device *spi; int ret, i; if (count % MPF_SPI_FRAME_SIZE) { @@ -287,19 +314,8 @@ static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count return -EINVAL; } - spi = priv->spi; - - xfers[0].tx_buf = spi_frame_command; - xfers[0].len = sizeof(spi_frame_command); - for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) { - xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE; - xfers[1].len = MPF_SPI_FRAME_SIZE; - - ret = mpf_poll_status(spi, 0); - if (ret >= 0) - ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers)); - + ret = mpf_spi_frame_write(priv, buf + i * MPF_SPI_FRAME_SIZE); if (ret) { dev_err(dev, "Failed to write bitstream frame %d/%zu\n", i, count / MPF_SPI_FRAME_SIZE); @@ -317,12 +333,9 @@ static int mpf_ops_write_complete(struct fpga_manager *mgr, const u8 release_command[] = { MPF_SPI_RELEASE }; struct mpf_priv *priv = mgr->priv; struct device *dev = &mgr->dev; - struct spi_device *spi; int ret; - spi = priv->spi; - - ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command)); + ret = mpf_spi_write(priv, isc_dis_command, sizeof(isc_dis_command)); if (ret) { dev_err(dev, "Failed to disable ISC: %d\n", ret); return ret; @@ -330,7 +343,7 @@ static int mpf_ops_write_complete(struct fpga_manager *mgr, usleep_range(1000, 2000); - ret = mpf_spi_write(spi, release_command, sizeof(release_command)); + ret = mpf_spi_write(priv, release_command, sizeof(release_command)); if (ret) { dev_err(dev, "Failed to exit program mode: %d\n", ret); return ret; diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index 45c1eb5dfcb7..2b5bbfffbc4f 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -201,4 +201,39 @@ config CORESIGHT_TRBE To compile this driver as a module, choose M here: the module will be called coresight-trbe. + +config ULTRASOC_SMB + tristate "Ultrasoc system memory buffer drivers" + depends on ACPI || COMPILE_TEST + depends on ARM64 && CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for the Ultrasoc system memory buffer (SMB). + SMB is responsible for receiving the trace data from Coresight ETM devices + and storing them to a system buffer. + + To compile this driver as a module, choose M here: the module will be + called ultrasoc-smb. + +config CORESIGHT_TPDM + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver" + select CORESIGHT_LINKS_AND_SINKS + select CORESIGHT_TPDA + help + This driver provides support for configuring monitor. Monitors are + primarily responsible for data set collection and support the + ability to collect any permutation of data set types. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpdm. + +config CORESIGHT_TPDA + tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver" + help + This driver provides support for configuring aggregator. This is + primarily useful for pulling the data sets from one or more + attached monitors and pushing the resultant data out. Multiple + monitors are connected on different input ports of TPDA. + + To compile this driver as a module, choose M here: the module will be + called coresight-tpda. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile index b6c4a48140ec..33bcc3f7b8ae 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_CORESIGHT) += coresight.o coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \ coresight-sysfs.o coresight-syscfg.o coresight-config.o \ coresight-cfg-preload.o coresight-cfg-afdo.o \ - coresight-syscfg-configfs.o + coresight-syscfg-configfs.o coresight-trace-id.o obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \ coresight-tmc-etr.o @@ -25,5 +25,8 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o +obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o +obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index f3068175ca9d..d3bf82c0de1d 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,13 @@ static DEFINE_MUTEX(coresight_mutex); static DEFINE_PER_CPU(struct coresight_device *, csdev_sink); +/* + * Use IDR to map the hash of the source's device name + * to the pointer of path for the source. The idr is for + * the sources which aren't associated with CPU. + */ +static DEFINE_IDR(path_idr); + /** * struct coresight_node - elements of a path, from source to sink * @csdev: Address of an element. @@ -42,14 +50,6 @@ struct coresight_node { */ static DEFINE_PER_CPU(struct list_head *, tracer_path); -/* - * As of this writing only a single STM can be found in CS topologies. Since - * there is no way to know if we'll ever see more and what kind of - * configuration they will enact, for the time being only define a single path - * for STM. - */ -static struct list_head *stm_path; - /* * When losing synchronisation a new barrier packet needs to be inserted at the * beginning of the data collected in a buffer. That way the decoder knows that @@ -112,45 +112,6 @@ struct coresight_device *coresight_get_percpu_sink(int cpu) } EXPORT_SYMBOL_GPL(coresight_get_percpu_sink); -static int coresight_id_match(struct device *dev, void *data) -{ - int trace_id, i_trace_id; - struct coresight_device *csdev, *i_csdev; - - csdev = data; - i_csdev = to_coresight_device(dev); - - /* - * No need to care about oneself and components that are not - * sources or not enabled - */ - if (i_csdev == csdev || !i_csdev->enable || - i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE) - return 0; - - /* Get the source ID for both components */ - trace_id = source_ops(csdev)->trace_id(csdev); - i_trace_id = source_ops(i_csdev)->trace_id(i_csdev); - - /* All you need is one */ - if (trace_id == i_trace_id) - return 1; - - return 0; -} - -static int coresight_source_is_unique(struct coresight_device *csdev) -{ - int trace_id = source_ops(csdev)->trace_id(csdev); - - /* this shouldn't happen */ - if (trace_id < 0) - return 0; - - return !bus_for_each_dev(&coresight_bustype, NULL, - csdev, coresight_id_match); -} - static int coresight_find_link_inport(struct coresight_device *csdev, struct coresight_device *parent) { @@ -459,12 +420,6 @@ static int coresight_enable_source(struct coresight_device *csdev, u32 mode) { int ret; - if (!coresight_source_is_unique(csdev)) { - dev_warn(&csdev->dev, "traceID %d not unique\n", - source_ops(csdev)->trace_id(csdev)); - return -EINVAL; - } - if (!csdev->enable) { if (source_ops(csdev)->enable) { ret = coresight_control_assoc_ectdev(csdev, true); @@ -1106,7 +1061,8 @@ static int coresight_validate_source(struct coresight_device *csdev, } if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC && - subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) { + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE && + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS) { dev_err(&csdev->dev, "wrong device subtype in %s\n", function); return -EINVAL; } @@ -1120,6 +1076,7 @@ int coresight_enable(struct coresight_device *csdev) struct coresight_device *sink; struct list_head *path; enum coresight_dev_subtype_source subtype; + u32 hash; subtype = csdev->subtype.source_subtype; @@ -1174,7 +1131,15 @@ int coresight_enable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = path; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - stm_path = path; + case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: + /* + * Use the hash of source's device name as ID + * and map the ID to the pointer of the path. + */ + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL); + if (ret) + goto err_source; break; default: /* We can't be here */ @@ -1198,6 +1163,7 @@ void coresight_disable(struct coresight_device *csdev) { int cpu, ret; struct list_head *path = NULL; + u32 hash; mutex_lock(&coresight_mutex); @@ -1215,8 +1181,15 @@ void coresight_disable(struct coresight_device *csdev) per_cpu(tracer_path, cpu) = NULL; break; case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: - path = stm_path; - stm_path = NULL; + case CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS: + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev))); + /* Find the path by the hash. */ + path = idr_find(&path_idr, hash); + if (path == NULL) { + pr_err("Path is not found for %s\n", dev_name(&csdev->dev)); + goto out; + } + idr_remove(&path_idr, hash); break; default: /* We can't be here */ diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index d2cf4f4848e1..277c890a1f1f 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -107,12 +107,12 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) cti_write_all_hw_regs(drvdata); config->hw_enabled = true; - atomic_inc(&drvdata->config.enable_req_count); + drvdata->config.enable_req_count++; spin_unlock_irqrestore(&drvdata->spinlock, flags); return rc; cti_state_unchanged: - atomic_inc(&drvdata->config.enable_req_count); + drvdata->config.enable_req_count++; /* cannot enable due to error */ cti_err_not_enabled: @@ -129,7 +129,7 @@ static void cti_cpuhp_enable_hw(struct cti_drvdata *drvdata) config->hw_powered = true; /* no need to do anything if no enable request */ - if (!atomic_read(&drvdata->config.enable_req_count)) + if (!drvdata->config.enable_req_count) goto cti_hp_not_enabled; /* try to claim the device */ @@ -151,11 +151,18 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) { struct cti_config *config = &drvdata->config; struct coresight_device *csdev = drvdata->csdev; + int ret = 0; spin_lock(&drvdata->spinlock); + /* don't allow negative refcounts, return an error */ + if (!drvdata->config.enable_req_count) { + ret = -EINVAL; + goto cti_not_disabled; + } + /* check refcount - disable on 0 */ - if (atomic_dec_return(&drvdata->config.enable_req_count) > 0) + if (--drvdata->config.enable_req_count > 0) goto cti_not_disabled; /* no need to do anything if disabled or cpu unpowered */ @@ -171,12 +178,12 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); spin_unlock(&drvdata->spinlock); - return 0; + return ret; /* not disabled this call */ cti_not_disabled: spin_unlock(&drvdata->spinlock); - return 0; + return ret; } void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) @@ -232,7 +239,7 @@ static void cti_set_default_config(struct device *dev, /* Most regs default to 0 as zalloc'ed except...*/ config->trig_filter_enable = true; config->ctigate = GENMASK(config->nr_ctm_channels - 1, 0); - atomic_set(&config->enable_req_count, 0); + config->enable_req_count = 0; } /* @@ -689,7 +696,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, drvdata->config.hw_enabled = false; /* check enable reference count to enable HW */ - if (atomic_read(&drvdata->config.enable_req_count)) { + if (drvdata->config.enable_req_count) { /* check we can claim the device as we re-power */ if (coresight_claim_device(csdev)) goto cti_notify_exit; diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 6d59c815ecf5..e528cff9d4e2 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -84,8 +84,8 @@ static ssize_t enable_show(struct device *dev, bool enabled, powered; struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); - enable_req = atomic_read(&drvdata->config.enable_req_count); spin_lock(&drvdata->spinlock); + enable_req = drvdata->config.enable_req_count; powered = drvdata->config.hw_powered; enabled = drvdata->config.hw_enabled; spin_unlock(&drvdata->spinlock); @@ -108,10 +108,19 @@ static ssize_t enable_store(struct device *dev, if (ret) return ret; - if (val) + if (val) { + ret = pm_runtime_resume_and_get(dev->parent); + if (ret) + return ret; ret = cti_enable(drvdata->csdev); - else + if (ret) + pm_runtime_put(dev->parent); + } else { ret = cti_disable(drvdata->csdev); + if (!ret) + pm_runtime_put(dev->parent); + } + if (ret) return ret; return size; diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index acf7b545e6b9..8b106b13a244 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -141,7 +141,7 @@ struct cti_config { int nr_trig_max; /* cti enable control */ - atomic_t enable_req_count; + int enable_req_count; bool hw_enabled; bool hw_powered; diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 43bbd5dc3d3b..a48c97da8165 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -4,6 +4,7 @@ * Author: Mathieu Poirier */ +#include #include #include #include @@ -22,6 +23,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static struct pmu etm_pmu; static bool etm_perf_up; @@ -228,8 +230,12 @@ static void free_event_data(struct work_struct *work) if (!(IS_ERR_OR_NULL(*ppath))) coresight_release_path(*ppath); *ppath = NULL; + coresight_trace_id_put_cpu_id(cpu); } + /* mark perf event as done for trace id allocator */ + coresight_trace_id_perf_stop(); + free_percpu(event_data->path); kfree(event_data); } @@ -300,6 +306,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, { u32 id, cfg_hash; int cpu = event->cpu; + int trace_id; cpumask_t *mask; struct coresight_device *sink = NULL; struct coresight_device *user_sink = NULL, *last_sink = NULL; @@ -316,6 +323,9 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, sink = user_sink = coresight_get_sink_by_id(id); } + /* tell the trace ID allocator that a perf event is starting up */ + coresight_trace_id_perf_start(); + /* check if user wants a coresight configuration selected */ cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); if (cfg_hash) { @@ -388,6 +398,13 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, continue; } + /* ensure we can allocate a trace ID for this CPU */ + trace_id = coresight_trace_id_get_cpu_id(cpu); + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + cpumask_clear_cpu(cpu, mask); + continue; + } + *etm_event_cpu_path_ptr(event_data, cpu) = path; } @@ -432,6 +449,7 @@ static void etm_event_start(struct perf_event *event, int flags) struct perf_output_handle *handle = &ctxt->handle; struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); struct list_head *path; + u64 hw_id; if (!csdev) goto fail; @@ -477,6 +495,19 @@ static void etm_event_start(struct perf_event *event, int flags) if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path; + /* + * output cpu / trace ID in perf record, once for the lifetime + * of the event. + */ + if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) { + cpumask_set_cpu(cpu, &event_data->aux_hwid_done); + hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, + CS_AUX_HW_ID_CURR_VERSION); + hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, + coresight_trace_id_read_cpu_id(cpu)); + perf_report_aux_output_id(event, hw_id); + } + out: /* Tell the perf core the event is alive */ event->hw.state = 0; diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 468f7799ab4f..bebbadee2ceb 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -48,6 +48,7 @@ struct etm_filters { * struct etm_event_data - Coresight specifics associated to an event * @work: Handle to free allocated memory outside IRQ context. * @mask: Hold the CPU(s) this event was set for. + * @aux_hwid_done: Whether a CPU has emitted the TraceID packet or not. * @snk_config: The sink configuration. * @cfg_hash: The hash id of any coresight config selected. * @path: An array of path, each slot for one CPU. @@ -55,6 +56,7 @@ struct etm_filters { struct etm_event_data { struct work_struct work; cpumask_t mask; + cpumask_t aux_hwid_done; void *snk_config; u32 cfg_hash; struct list_head * __percpu *path; diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index f3ab96eaf44e..9a0d08b092ae 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -283,8 +283,9 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off) } extern const struct attribute_group *coresight_etm_groups[]; -int etm_get_trace_id(struct etm_drvdata *drvdata); void etm_set_default(struct etm_config *config); void etm_config_trace_mode(struct etm_config *config); struct etm_config *get_etm_config(struct etm_drvdata *drvdata); +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata); +void etm_release_trace_id(struct etm_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index d0ab9933472b..afc57195ee52 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -32,6 +32,7 @@ #include "coresight-etm.h" #include "coresight-etm-perf.h" +#include "coresight-trace-id.h" /* * Not really modular but using module_param is the easiest way to @@ -454,52 +455,59 @@ static int etm_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -int etm_get_trace_id(struct etm_drvdata *drvdata) +int etm_read_alloc_trace_id(struct etm_drvdata *drvdata) { - unsigned long flags; - int trace_id = -1; - struct device *etm_dev; + int trace_id; - if (!drvdata) - goto out; - - etm_dev = drvdata->csdev->dev.parent; - if (!local_read(&drvdata->mode)) - return drvdata->traceid; - - pm_runtime_get_sync(etm_dev); - - spin_lock_irqsave(&drvdata->spinlock, flags); - - CS_UNLOCK(drvdata->base); - trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK); - CS_LOCK(drvdata->base); - - spin_unlock_irqrestore(&drvdata->spinlock, flags); - pm_runtime_put(etm_dev); - -out: + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * + * trace id function has its own lock + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->traceid = (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); return trace_id; - } -static int etm_trace_id(struct coresight_device *csdev) +void etm_release_trace_id(struct etm_drvdata *drvdata) { - struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return etm_get_trace_id(drvdata); + coresight_trace_id_put_cpu_id(drvdata->cpu); } static int etm_enable_perf(struct coresight_device *csdev, struct perf_event *event) { struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int trace_id; if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) return -EINVAL; /* Configure the tracer based on the session's specifics */ etm_parse_event_config(drvdata, event); + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return -EINVAL; + } + drvdata->traceid = (u8)trace_id; + /* And enable it */ return etm_enable_hw(drvdata); } @@ -512,6 +520,11 @@ static int etm_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); + /* sysfs needs to allocate and set a trace ID */ + ret = etm_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_enable_sysfs; + /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place on the local CPU during bring up. @@ -528,6 +541,10 @@ static int etm_enable_sysfs(struct coresight_device *csdev) ret = -ENODEV; } + if (ret) + etm_release_trace_id(drvdata); + +unlock_enable_sysfs: spin_unlock(&drvdata->spinlock); if (!ret) @@ -611,6 +628,12 @@ static void etm_disable_perf(struct coresight_device *csdev) coresight_disclaim_device_unlocked(csdev); CS_LOCK(drvdata->base); + + /* + * perf will release trace ids when _free_aux() + * is called at the end of the session + */ + } static void etm_disable_sysfs(struct coresight_device *csdev) @@ -635,6 +658,13 @@ static void etm_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -671,7 +701,6 @@ static void etm_disable(struct coresight_device *csdev, static const struct coresight_ops_source etm_source_ops = { .cpu_id = etm_cpu_id, - .trace_id = etm_trace_id, .enable = etm_enable, .disable = etm_disable, }; @@ -781,11 +810,6 @@ static void etm_init_arch_data(void *info) CS_LOCK(drvdata->base); } -static void etm_init_trace_id(struct etm_drvdata *drvdata) -{ - drvdata->traceid = coresight_get_trace_id(drvdata->cpu); -} - static int __init etm_hp_setup(void) { int ret; @@ -871,7 +895,6 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) if (etm_arch_supported(drvdata->arch) == false) return -EINVAL; - etm_init_trace_id(drvdata); etm_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c index fd81eca3ec18..2f271b7fb048 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -85,6 +85,7 @@ static ssize_t reset_store(struct device *dev, } etm_set_default(config); + etm_release_trace_id(drvdata); spin_unlock(&drvdata->spinlock); } @@ -1189,30 +1190,16 @@ static DEVICE_ATTR_RO(cpu); static ssize_t traceid_show(struct device *dev, struct device_attribute *attr, char *buf) { - unsigned long val; + int trace_id; struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - val = etm_get_trace_id(drvdata); + trace_id = etm_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; - return sprintf(buf, "%#lx\n", val); + return sysfs_emit(buf, "%#x\n", trace_id); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - drvdata->traceid = val & ETM_TRACEID_MASK; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_etm_attrs[] = { &dev_attr_nr_addr_cmp.attr, diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1cc052979e01..1ea8f173cca0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -42,6 +42,7 @@ #include "coresight-etm4x-cfg.h" #include "coresight-self-hosted-trace.h" #include "coresight-syscfg.h" +#include "coresight-trace-id.h" static int boot_enable; module_param(boot_enable, int, 0444); @@ -230,11 +231,28 @@ static int etm4_cpu_id(struct coresight_device *csdev) return drvdata->cpu; } -static int etm4_trace_id(struct coresight_device *csdev) +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) { - struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int trace_id; - return drvdata->trcid; + /* + * This will allocate a trace ID to the cpu, + * or return the one currently allocated. + * The trace id function has its own lock + */ + trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); + if (IS_VALID_CS_TRACE_ID(trace_id)) + drvdata->trcid = (u8)trace_id; + else + dev_err(&drvdata->csdev->dev, + "Failed to allocate trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + return trace_id; +} + +void etm4_release_trace_id(struct etmv4_drvdata *drvdata) +{ + coresight_trace_id_put_cpu_id(drvdata->cpu); } struct etm4_enable_arg { @@ -427,8 +445,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); + } etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); @@ -720,7 +740,7 @@ out: static int etm4_enable_perf(struct coresight_device *csdev, struct perf_event *event) { - int ret = 0; + int ret = 0, trace_id; struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { @@ -732,6 +752,24 @@ static int etm4_enable_perf(struct coresight_device *csdev, ret = etm4_parse_event_config(csdev, event); if (ret) goto out; + + /* + * perf allocates cpu ids as part of _setup_aux() - device needs to use + * the allocated ID. This reads the current version without allocation. + * + * This does not use the trace id lock to prevent lock_dep issues + * with perf locks - we know the ID cannot change until perf shuts down + * the session + */ + trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); + if (!IS_VALID_CS_TRACE_ID(trace_id)) { + dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", + dev_name(&drvdata->csdev->dev), drvdata->cpu); + ret = -EINVAL; + goto out; + } + drvdata->trcid = (u8)trace_id; + /* And enable it */ ret = etm4_enable_hw(drvdata); @@ -756,6 +794,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) spin_lock(&drvdata->spinlock); + /* sysfs needs to read and allocate a trace ID */ + ret = etm4_read_alloc_trace_id(drvdata); + if (ret < 0) + goto unlock_sysfs_enable; + /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled * ensures that register writes occur when cpu is powered. @@ -767,6 +810,11 @@ static int etm4_enable_sysfs(struct coresight_device *csdev) ret = arg.rc; if (!ret) drvdata->sticky_enable = true; + + if (ret) + etm4_release_trace_id(drvdata); + +unlock_sysfs_enable: spin_unlock(&drvdata->spinlock); if (!ret) @@ -898,6 +946,11 @@ static int etm4_disable_perf(struct coresight_device *csdev, /* TRCVICTLR::SSSTATUS, bit[9] */ filters->ssstatus = (control & BIT(9)); + /* + * perf will release trace ids when _free_aux() is + * called at the end of the session. + */ + return 0; } @@ -923,6 +976,13 @@ static void etm4_disable_sysfs(struct coresight_device *csdev) spin_unlock(&drvdata->spinlock); cpus_read_unlock(); + /* + * we only release trace IDs when resetting sysfs. + * This permits sysfs users to read the trace ID after the trace + * session has completed. This maintains operational behaviour with + * prior trace id allocation method + */ + dev_dbg(&csdev->dev, "ETM tracing disabled\n"); } @@ -956,7 +1016,6 @@ static void etm4_disable(struct coresight_device *csdev, static const struct coresight_ops_source etm4_source_ops = { .cpu_id = etm4_cpu_id, - .trace_id = etm4_trace_id, .enable = etm4_enable, .disable = etm4_disable, }; @@ -1565,11 +1624,6 @@ static int etm4_dying_cpu(unsigned int cpu) return 0; } -static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) -{ - drvdata->trcid = coresight_get_trace_id(drvdata->cpu); -} - static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret = 0; @@ -1634,8 +1688,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); - state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + if (drvdata->nrseqstate) { + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); + state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); + } state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { @@ -1763,8 +1819,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) for (i = 0; i < drvdata->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); - etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + if (drvdata->nrseqstate) { + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); + etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); + } etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); for (i = 0; i < drvdata->nr_cntr; i++) { @@ -1946,7 +2004,6 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) if (!desc.name) return -ENOMEM; - etm4_init_trace_id(drvdata); etm4_set_default(&drvdata->config); pdata = coresight_get_platform_data(dev); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index 9cac848cffaf..5e62aa40ecd0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -266,10 +266,11 @@ static ssize_t reset_store(struct device *dev, config->vmid_mask0 = 0x0; config->vmid_mask1 = 0x0; - drvdata->trcid = drvdata->cpu + 1; - spin_unlock(&drvdata->spinlock); + /* for sysfs - only release trace id when resetting */ + etm4_release_trace_id(drvdata); + cscfg_csdev_reset_feats(to_coresight_device(dev)); return size; @@ -2392,6 +2393,26 @@ static struct attribute *coresight_etmv4_attrs[] = { NULL, }; +/* + * Trace ID allocated dynamically on enable - but also allocate on read + * in case sysfs or perf read before enable to ensure consistent metadata + * information for trace decode + */ +static ssize_t trctraceid_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int trace_id; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); + + trace_id = etm4_read_alloc_trace_id(drvdata); + if (trace_id < 0) + return trace_id; + + return sysfs_emit(buf, "0x%x\n", trace_id); +} +static DEVICE_ATTR_RO(trctraceid); + struct etmv4_reg { struct coresight_device *csdev; u32 offset; @@ -2528,7 +2549,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = { coresight_etm4x_reg(trcpidr3, TRCPIDR3), coresight_etm4x_reg(trcoslsr, TRCOSLSR), coresight_etm4x_reg(trcconfig, TRCCONFIGR), - coresight_etm4x_reg(trctraceid, TRCTRACEIDR), + &dev_attr_trctraceid.attr, coresight_etm4x_reg(trcdevarch, TRCDEVARCH), NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4b21bb79f168..434f4e95ee17 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1095,4 +1095,7 @@ static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) { return drvdata->arch >= ETM_ARCH_ETE; } + +int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata); +void etm4_release_trace_id(struct etmv4_drvdata *drvdata); #endif diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index 463f449cfb79..66a614c5492c 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -31,6 +31,7 @@ #include #include "coresight-priv.h" +#include "coresight-trace-id.h" #define STMDMASTARTR 0xc04 #define STMDMASTOPR 0xc08 @@ -280,15 +281,7 @@ static void stm_disable(struct coresight_device *csdev, } } -static int stm_trace_id(struct coresight_device *csdev) -{ - struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - return drvdata->traceid; -} - static const struct coresight_ops_source stm_source_ops = { - .trace_id = stm_trace_id, .enable = stm_enable, .disable = stm_disable, }; @@ -615,24 +608,7 @@ static ssize_t traceid_show(struct device *dev, val = drvdata->traceid; return sprintf(buf, "%#lx\n", val); } - -static ssize_t traceid_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t size) -{ - int ret; - unsigned long val; - struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); - - ret = kstrtoul(buf, 16, &val); - if (ret) - return ret; - - /* traceid field is 7bit wide on STM32 */ - drvdata->traceid = val & 0x7f; - return size; -} -static DEVICE_ATTR_RW(traceid); +static DEVICE_ATTR_RO(traceid); static struct attribute *coresight_stm_attrs[] = { &dev_attr_hwevent_enable.attr, @@ -803,14 +779,6 @@ static void stm_init_default_data(struct stm_drvdata *drvdata) */ drvdata->stmsper = ~0x0; - /* - * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and - * anything equal to or higher than 0x70 is reserved. Since 0x00 is - * also reserved the STM trace ID needs to be higher than 0x00 and - * lowner than 0x10. - */ - drvdata->traceid = 0x1; - /* Set invariant transaction timing on all channels */ bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); } @@ -838,7 +806,7 @@ static void stm_init_generic_data(struct stm_drvdata *drvdata, static int stm_probe(struct amba_device *adev, const struct amba_id *id) { - int ret; + int ret, trace_id; void __iomem *base; struct device *dev = &adev->dev; struct coresight_platform_data *pdata = NULL; @@ -922,12 +890,22 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) goto stm_unregister; } + trace_id = coresight_trace_id_get_system_id(); + if (trace_id < 0) { + ret = trace_id; + goto cs_unregister; + } + drvdata->traceid = (u8)trace_id; + pm_runtime_put(&adev->dev); dev_info(&drvdata->csdev->dev, "%s initialized\n", (char *)coresight_get_uci_data(id)); return 0; +cs_unregister: + coresight_unregister(drvdata->csdev); + stm_unregister: stm_unregister_device(&drvdata->stm); return ret; @@ -937,6 +915,7 @@ static void stm_remove(struct amba_device *adev) { struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + coresight_trace_id_put_system_id(drvdata->traceid); coresight_unregister(drvdata->csdev); stm_unregister_device(&drvdata->stm); diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 07abf28ad725..c106d142e632 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { dev_err(&csdev->dev, "timeout while waiting for TMC to be Ready\n"); + return -EBUSY; } + return 0; } void tmc_flush_and_stop(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 4c4cbd1f7258..0ab1f73c2d06 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -16,12 +16,20 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev, struct perf_output_handle *handle); -static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) { + int rc = 0; + CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to enable: TMC not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | @@ -33,6 +41,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) @@ -42,8 +51,10 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) if (rc) return rc; - __tmc_etb_enable_hw(drvdata); - return 0; + rc = __tmc_etb_enable_hw(drvdata); + if (rc) + coresight_disclaim_device(drvdata->csdev); + return rc; } static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) @@ -91,12 +102,20 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) coresight_disclaim_device(drvdata->csdev); } -static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) { + int rc = 0; + CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to enable : TMC is not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI, @@ -105,6 +124,7 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) @@ -114,8 +134,10 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) if (rc) return rc; - __tmc_etf_enable_hw(drvdata); - return 0; + rc = __tmc_etf_enable_hw(drvdata); + if (rc) + coresight_disclaim_device(drvdata->csdev); + return rc; } static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) @@ -639,6 +661,7 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) char *buf = NULL; enum tmc_mode mode; unsigned long flags; + int rc = 0; /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB && @@ -664,7 +687,11 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) * can't be NULL. */ memset(drvdata->buf, 0, drvdata->size); - __tmc_etb_enable_hw(drvdata); + rc = __tmc_etb_enable_hw(drvdata); + if (rc) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } } else { /* * The ETB/ETF is not tracing and the buffer was just read. diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 867ad8bb9b0c..918d461fcf4a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -983,15 +983,22 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) etr_buf->ops->sync(etr_buf, rrp, rwp); } -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { u32 axictl, sts; struct etr_buf *etr_buf = drvdata->etr_buf; + int rc = 0; CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, + "Failed to enable : TMC not ready\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); @@ -1032,6 +1039,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, @@ -1060,7 +1068,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, rc = coresight_claim_device(drvdata->csdev); if (!rc) { drvdata->etr_buf = etr_buf; - __tmc_etr_enable_hw(drvdata); + rc = __tmc_etr_enable_hw(drvdata); + if (rc) { + drvdata->etr_buf = NULL; + coresight_disclaim_device(drvdata->csdev); + tmc_etr_disable_catu(drvdata); + } } return rc; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 66959557cf39..01c0382a29c0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -255,7 +255,7 @@ struct tmc_sg_table { }; /* Generic functions */ -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c new file mode 100644 index 000000000000..f712e112ecff --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpda.h" +#include "coresight-trace-id.h" + +DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda"); + +/* Settings pre enabling port control register */ +static void tpda_enable_pre_port(struct tpda_drvdata *drvdata) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_CR); + val &= ~TPDA_CR_ATID; + val |= FIELD_PREP(TPDA_CR_ATID, drvdata->atid); + writel_relaxed(val, drvdata->base + TPDA_CR); +} + +static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + /* Enable the port */ + val |= TPDA_Pn_CR_ENA; + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); +} + +static void __tpda_enable(struct tpda_drvdata *drvdata, int port) +{ + CS_UNLOCK(drvdata->base); + + if (!drvdata->csdev->enable) + tpda_enable_pre_port(drvdata); + + tpda_enable_port(drvdata, port); + + CS_LOCK(drvdata->base); +} + +static int tpda_enable(struct coresight_device *csdev, int inport, int outport) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (atomic_read(&csdev->refcnt[inport]) == 0) + __tpda_enable(drvdata, inport); + + atomic_inc(&csdev->refcnt[inport]); + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDA inport %d enabled.\n", inport); + return 0; +} + +static void __tpda_disable(struct tpda_drvdata *drvdata, int port) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); + val &= ~TPDA_Pn_CR_ENA; + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); + + CS_LOCK(drvdata->base); +} + +static void tpda_disable(struct coresight_device *csdev, int inport, + int outport) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (atomic_dec_return(&csdev->refcnt[inport]) == 0) + __tpda_disable(drvdata, inport); + + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", inport); +} + +static const struct coresight_ops_link tpda_link_ops = { + .enable = tpda_enable, + .disable = tpda_disable, +}; + +static const struct coresight_ops tpda_cs_ops = { + .link_ops = &tpda_link_ops, +}; + +static int tpda_init_default_data(struct tpda_drvdata *drvdata) +{ + int atid; + /* + * TPDA must has a unique atid. This atid can uniquely + * identify the TPDM trace source connected to the TPDA. + * The TPDMs which are connected to same TPDA share the + * same trace-id. When TPDA does packetization, different + * port will have unique channel number for decoding. + */ + atid = coresight_trace_id_get_system_id(); + if (atid < 0) + return atid; + + drvdata->atid = atid; + return 0; +} + +static int tpda_probe(struct amba_device *adev, const struct amba_id *id) +{ + int ret; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct tpda_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + void __iomem *base; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + drvdata->base = base; + + spin_lock_init(&drvdata->spinlock); + + ret = tpda_init_default_data(drvdata); + if (ret) + return ret; + + desc.name = coresight_alloc_device_name(&tpda_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type = CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.ops = &tpda_cs_ops; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + desc.access = CSDEV_ACCESS_IOMEM(base); + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + pm_runtime_put(&adev->dev); + + dev_dbg(drvdata->dev, "TPDA initialized\n"); + return 0; +} + +static void tpda_remove(struct amba_device *adev) +{ + struct tpda_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_trace_id_put_system_id(drvdata->atid); + coresight_unregister(drvdata->csdev); +} + +/* + * Different TPDA has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpda_ids[] = { + { + .id = 0x000f0f00, + .mask = 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpda_driver = { + .drv = { + .name = "coresight-tpda", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = tpda_probe, + .remove = tpda_remove, + .id_table = tpda_ids, +}; + +module_amba_driver(tpda_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h new file mode 100644 index 000000000000..0399678df312 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDA_H +#define _CORESIGHT_CORESIGHT_TPDA_H + +#define TPDA_CR (0x000) +#define TPDA_Pn_CR(n) (0x004 + (n * 4)) +/* Aggregator port enable bit */ +#define TPDA_Pn_CR_ENA BIT(0) + +#define TPDA_MAX_INPORTS 32 + +/* Bits 6 ~ 12 is for atid value */ +#define TPDA_CR_ATID GENMASK(12, 6) + +/** + * struct tpda_drvdata - specifics associated to an TPDA component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @spinlock: lock for the drvdata value. + * @enable: enable status of the component. + */ +struct tpda_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + u8 atid; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDA_H */ diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c new file mode 100644 index 000000000000..9479a5e8c672 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" +#include "coresight-tpdm.h" + +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm"); + +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 1 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val |= TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + +/* TPDM enable operations */ +static void __tpdm_enable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + tpdm_enable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + +static int tpdm_enable(struct coresight_device *csdev, + struct perf_event *event, u32 mode) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) { + spin_unlock(&drvdata->spinlock); + return -EBUSY; + } + + __tpdm_enable(drvdata); + drvdata->enable = true; + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDM tracing enabled\n"); + return 0; +} + +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + /* Set the enable bit of DSB control register to 0 */ + val = readl_relaxed(drvdata->base + TPDM_DSB_CR); + val &= ~TPDM_DSB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_DSB_CR); +} + +/* TPDM disable operations */ +static void __tpdm_disable(struct tpdm_drvdata *drvdata) +{ + CS_UNLOCK(drvdata->base); + + /* Check if DSB datasets is present for TPDM. */ + if (drvdata->datasets & TPDM_PIDR0_DS_DSB) + tpdm_disable_dsb(drvdata); + + CS_LOCK(drvdata->base); +} + +static void tpdm_disable(struct coresight_device *csdev, + struct perf_event *event) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + if (!drvdata->enable) { + spin_unlock(&drvdata->spinlock); + return; + } + + __tpdm_disable(drvdata); + drvdata->enable = false; + spin_unlock(&drvdata->spinlock); + + dev_dbg(drvdata->dev, "TPDM tracing disabled\n"); +} + +static const struct coresight_ops_source tpdm_source_ops = { + .enable = tpdm_enable, + .disable = tpdm_disable, +}; + +static const struct coresight_ops tpdm_cs_ops = { + .source_ops = &tpdm_source_ops, +}; + +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata) +{ + u32 pidr; + + CS_UNLOCK(drvdata->base); + /* Get the datasets present on the TPDM. */ + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0); + drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0); + CS_LOCK(drvdata->base); +} + +/* + * value 1: 64 bits test data + * value 2: 32 bits test data + */ +static ssize_t integration_test_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + int i, ret = 0; + unsigned long val; + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + if (val != 1 && val != 2) + return -EINVAL; + + if (!drvdata->enable) + return -EINVAL; + + if (val == 1) + val = ATBCNTRL_VAL_64; + else + val = ATBCNTRL_VAL_32; + CS_UNLOCK(drvdata->base); + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL); + + for (i = 0; i < INTEGRATION_TEST_CYCLE; i++) + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL); + + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL); + CS_LOCK(drvdata->base); + return size; +} +static DEVICE_ATTR_WO(integration_test); + +static struct attribute *tpdm_attrs[] = { + &dev_attr_integration_test.attr, + NULL, +}; + +static struct attribute_group tpdm_attr_grp = { + .attrs = tpdm_attrs, +}; + +static const struct attribute_group *tpdm_attr_grps[] = { + &tpdm_attr_grp, + NULL, +}; + +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) +{ + void __iomem *base; + struct device *dev = &adev->dev; + struct coresight_platform_data *pdata; + struct tpdm_drvdata *drvdata; + struct coresight_desc desc = { 0 }; + + pdata = coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data = pdata; + + /* driver data*/ + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + drvdata->dev = &adev->dev; + dev_set_drvdata(dev, drvdata); + + base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(base)) + return PTR_ERR(base); + + drvdata->base = base; + + /* Set up coresight component description */ + desc.name = coresight_alloc_device_name(&tpdm_devs, dev); + if (!desc.name) + return -ENOMEM; + desc.type = CORESIGHT_DEV_TYPE_SOURCE; + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.ops = &tpdm_cs_ops; + desc.pdata = adev->dev.platform_data; + desc.dev = &adev->dev; + desc.access = CSDEV_ACCESS_IOMEM(base); + desc.groups = tpdm_attr_grps; + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + spin_lock_init(&drvdata->spinlock); + tpdm_init_default_data(drvdata); + /* Decrease pm refcount when probe is done.*/ + pm_runtime_put(&adev->dev); + + return 0; +} + +static void tpdm_remove(struct amba_device *adev) +{ + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); +} + +/* + * Different TPDM has different periph id. + * The difference is 0-7 bits' value. So ignore 0-7 bits. + */ +static struct amba_id tpdm_ids[] = { + { + .id = 0x000f0e00, + .mask = 0x000fff00, + }, + { 0, 0}, +}; + +static struct amba_driver tpdm_driver = { + .drv = { + .name = "coresight-tpdm", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = tpdm_probe, + .id_table = tpdm_ids, + .remove = tpdm_remove, +}; + +module_amba_driver(tpdm_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver"); diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h new file mode 100644 index 000000000000..543854043a2d --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tpdm.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _CORESIGHT_CORESIGHT_TPDM_H +#define _CORESIGHT_CORESIGHT_TPDM_H + +/* The max number of the datasets that TPDM supports */ +#define TPDM_DATASETS 7 + +/* DSB Subunit Registers */ +#define TPDM_DSB_CR (0x780) +/* Enable bit for DSB subunit */ +#define TPDM_DSB_CR_ENA BIT(0) + +/* TPDM integration test registers */ +#define TPDM_ITATBCNTRL (0xEF0) +#define TPDM_ITCNTRL (0xF00) + +/* Register value for integration test */ +#define ATBCNTRL_VAL_32 0xC00F1409 +#define ATBCNTRL_VAL_64 0xC01F1409 + +/* + * Number of cycles to write value when + * integration test. + */ +#define INTEGRATION_TEST_CYCLE 10 + +/** + * The bits of PERIPHIDR0 register. + * The fields [6:0] of PERIPHIDR0 are used to determine what + * interfaces and subunits are present on a given TPDM. + * + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 + */ + +#define TPDM_PIDR0_DS_IMPDEF BIT(0) +#define TPDM_PIDR0_DS_DSB BIT(1) + +/** + * struct tpdm_drvdata - specifics associated to an TPDM component + * @base: memory mapped base address for this component. + * @dev: The device entity associated to this component. + * @csdev: component vitals needed by the framework. + * @spinlock: lock for the drvdata value. + * @enable: enable status of the component. + * @datasets: The datasets types present of the TPDM. + */ + +struct tpdm_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + bool enable; + unsigned long datasets; +}; + +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */ diff --git a/drivers/hwtracing/coresight/coresight-trace-id.c b/drivers/hwtracing/coresight/coresight-trace-id.c new file mode 100644 index 000000000000..af5b4ef59cea --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.c @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Linaro Limited, All rights reserved. + * Author: Mike Leach + */ +#include +#include +#include +#include +#include + +#include "coresight-trace-id.h" + +/* Default trace ID map. Used on systems that don't require per sink mappings */ +static struct coresight_trace_id_map id_map_default; + +/* maintain a record of the mapping of IDs and pending releases per cpu */ +static DEFINE_PER_CPU(atomic_t, cpu_id) = ATOMIC_INIT(0); +static cpumask_t cpu_id_release_pending; + +/* perf session active counter */ +static atomic_t perf_cs_etm_session_active = ATOMIC_INIT(0); + +/* lock to protect id_map and cpu data */ +static DEFINE_SPINLOCK(id_map_lock); + +/* #define TRACE_ID_DEBUG 1 */ +#if defined(TRACE_ID_DEBUG) || defined(CONFIG_COMPILE_TEST) + +static void coresight_trace_id_dump_table(struct coresight_trace_id_map *id_map, + const char *func_name) +{ + pr_debug("%s id_map::\n", func_name); + pr_debug("Used = %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->used_ids); + pr_debug("Pend = %*pb\n", CORESIGHT_TRACE_IDS_MAX, id_map->pend_rel_ids); +} +#define DUMP_ID_MAP(map) coresight_trace_id_dump_table(map, __func__) +#define DUMP_ID_CPU(cpu, id) pr_debug("%s called; cpu=%d, id=%d\n", __func__, cpu, id) +#define DUMP_ID(id) pr_debug("%s called; id=%d\n", __func__, id) +#define PERF_SESSION(n) pr_debug("%s perf count %d\n", __func__, n) +#else +#define DUMP_ID_MAP(map) +#define DUMP_ID(id) +#define DUMP_ID_CPU(cpu, id) +#define PERF_SESSION(n) +#endif + +/* unlocked read of current trace ID value for given CPU */ +static int _coresight_trace_id_read_cpu_id(int cpu) +{ + return atomic_read(&per_cpu(cpu_id, cpu)); +} + +/* look for next available odd ID, return 0 if none found */ +static int coresight_trace_id_find_odd_id(struct coresight_trace_id_map *id_map) +{ + int found_id = 0, bit = 1, next_id; + + while ((bit < CORESIGHT_TRACE_ID_RES_TOP) && !found_id) { + /* + * bitmap length of CORESIGHT_TRACE_ID_RES_TOP, + * search from offset `bit`. + */ + next_id = find_next_zero_bit(id_map->used_ids, + CORESIGHT_TRACE_ID_RES_TOP, bit); + if ((next_id < CORESIGHT_TRACE_ID_RES_TOP) && (next_id & 0x1)) + found_id = next_id; + else + bit = next_id + 1; + } + return found_id; +} + +/* + * Allocate new ID and set in use + * + * if @preferred_id is a valid id then try to use that value if available. + * if @preferred_id is not valid and @prefer_odd_id is true, try for odd id. + * + * Otherwise allocate next available ID. + */ +static int coresight_trace_id_alloc_new_id(struct coresight_trace_id_map *id_map, + int preferred_id, bool prefer_odd_id) +{ + int id = 0; + + /* for backwards compatibility, cpu IDs may use preferred value */ + if (IS_VALID_CS_TRACE_ID(preferred_id) && + !test_bit(preferred_id, id_map->used_ids)) { + id = preferred_id; + goto trace_id_allocated; + } else if (prefer_odd_id) { + /* may use odd ids to avoid preferred legacy cpu IDs */ + id = coresight_trace_id_find_odd_id(id_map); + if (id) + goto trace_id_allocated; + } + + /* + * skip reserved bit 0, look at bitmap length of + * CORESIGHT_TRACE_ID_RES_TOP from offset of bit 1. + */ + id = find_next_zero_bit(id_map->used_ids, CORESIGHT_TRACE_ID_RES_TOP, 1); + if (id >= CORESIGHT_TRACE_ID_RES_TOP) + return -EINVAL; + + /* mark as used */ +trace_id_allocated: + set_bit(id, id_map->used_ids); + return id; +} + +static void coresight_trace_id_free(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) + return; + if (WARN(!test_bit(id, id_map->used_ids), "Freeing unused ID %d\n", id)) + return; + clear_bit(id, id_map->used_ids); +} + +static void coresight_trace_id_set_pend_rel(int id, struct coresight_trace_id_map *id_map) +{ + if (WARN(!IS_VALID_CS_TRACE_ID(id), "Invalid Trace ID %d\n", id)) + return; + set_bit(id, id_map->pend_rel_ids); +} + +/* + * release all pending IDs for all current maps & clear CPU associations + * + * This currently operates on the default id map, but may be extended to + * operate on all registered id maps if per sink id maps are used. + */ +static void coresight_trace_id_release_all_pending(void) +{ + struct coresight_trace_id_map *id_map = &id_map_default; + unsigned long flags; + int cpu, bit; + + spin_lock_irqsave(&id_map_lock, flags); + for_each_set_bit(bit, id_map->pend_rel_ids, CORESIGHT_TRACE_ID_RES_TOP) { + clear_bit(bit, id_map->used_ids); + clear_bit(bit, id_map->pend_rel_ids); + } + for_each_cpu(cpu, &cpu_id_release_pending) { + atomic_set(&per_cpu(cpu_id, cpu), 0); + cpumask_clear_cpu(cpu, &cpu_id_release_pending); + } + spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_MAP(id_map); +} + +static int coresight_trace_id_map_get_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + + /* check for existing allocation for this CPU */ + id = _coresight_trace_id_read_cpu_id(cpu); + if (id) + goto get_cpu_id_clr_pend; + + /* + * Find a new ID. + * + * Use legacy values where possible in the dynamic trace ID allocator to + * allow older tools to continue working if they are not upgraded at the + * same time as the kernel drivers. + * + * If the generated legacy ID is invalid, or not available then the next + * available dynamic ID will be used. + */ + id = coresight_trace_id_alloc_new_id(id_map, + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu), + false); + if (!IS_VALID_CS_TRACE_ID(id)) + goto get_cpu_id_out_unlock; + + /* allocate the new id to the cpu */ + atomic_set(&per_cpu(cpu_id, cpu), id); + +get_cpu_id_clr_pend: + /* we are (re)using this ID - so ensure it is not marked for release */ + cpumask_clear_cpu(cpu, &cpu_id_release_pending); + clear_bit(id, id_map->pend_rel_ids); + +get_cpu_id_out_unlock: + spin_unlock_irqrestore(&id_map_lock, flags); + + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); + return id; +} + +static void coresight_trace_id_map_put_cpu_id(int cpu, struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + /* check for existing allocation for this CPU */ + id = _coresight_trace_id_read_cpu_id(cpu); + if (!id) + return; + + spin_lock_irqsave(&id_map_lock, flags); + + if (atomic_read(&perf_cs_etm_session_active)) { + /* set release at pending if perf still active */ + coresight_trace_id_set_pend_rel(id, id_map); + cpumask_set_cpu(cpu, &cpu_id_release_pending); + } else { + /* otherwise clear id */ + coresight_trace_id_free(id, id_map); + atomic_set(&per_cpu(cpu_id, cpu), 0); + } + + spin_unlock_irqrestore(&id_map_lock, flags); + DUMP_ID_CPU(cpu, id); + DUMP_ID_MAP(id_map); +} + +static int coresight_trace_id_map_get_system_id(struct coresight_trace_id_map *id_map) +{ + unsigned long flags; + int id; + + spin_lock_irqsave(&id_map_lock, flags); + /* prefer odd IDs for system components to avoid legacy CPU IDS */ + id = coresight_trace_id_alloc_new_id(id_map, 0, true); + spin_unlock_irqrestore(&id_map_lock, flags); + + DUMP_ID(id); + DUMP_ID_MAP(id_map); + return id; +} + +static void coresight_trace_id_map_put_system_id(struct coresight_trace_id_map *id_map, int id) +{ + unsigned long flags; + + spin_lock_irqsave(&id_map_lock, flags); + coresight_trace_id_free(id, id_map); + spin_unlock_irqrestore(&id_map_lock, flags); + + DUMP_ID(id); + DUMP_ID_MAP(id_map); +} + +/* API functions */ + +int coresight_trace_id_get_cpu_id(int cpu) +{ + return coresight_trace_id_map_get_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_cpu_id); + +void coresight_trace_id_put_cpu_id(int cpu) +{ + coresight_trace_id_map_put_cpu_id(cpu, &id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_cpu_id); + +int coresight_trace_id_read_cpu_id(int cpu) +{ + return _coresight_trace_id_read_cpu_id(cpu); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_read_cpu_id); + +int coresight_trace_id_get_system_id(void) +{ + return coresight_trace_id_map_get_system_id(&id_map_default); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_get_system_id); + +void coresight_trace_id_put_system_id(int id) +{ + coresight_trace_id_map_put_system_id(&id_map_default, id); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_put_system_id); + +void coresight_trace_id_perf_start(void) +{ + atomic_inc(&perf_cs_etm_session_active); + PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_start); + +void coresight_trace_id_perf_stop(void) +{ + if (!atomic_dec_return(&perf_cs_etm_session_active)) + coresight_trace_id_release_all_pending(); + PERF_SESSION(atomic_read(&perf_cs_etm_session_active)); +} +EXPORT_SYMBOL_GPL(coresight_trace_id_perf_stop); diff --git a/drivers/hwtracing/coresight/coresight-trace-id.h b/drivers/hwtracing/coresight/coresight-trace-id.h new file mode 100644 index 000000000000..3797777d367e --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-trace-id.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright(C) 2022 Linaro Limited. All rights reserved. + * Author: Mike Leach + */ + +#ifndef _CORESIGHT_TRACE_ID_H +#define _CORESIGHT_TRACE_ID_H + +/* + * Coresight trace ID allocation API + * + * With multi cpu systems, and more additional trace sources a scalable + * trace ID reservation system is required. + * + * The system will allocate Ids on a demand basis, and allow them to be + * released when done. + * + * In order to ensure that a consistent cpu / ID matching is maintained + * throughout a perf cs_etm event session - a session in progress flag will + * be maintained, and released IDs not cleared until the perf session is + * complete. This allows the same CPU to be re-allocated its prior ID. + * + * + * Trace ID maps will be created and initialised to prevent architecturally + * reserved IDs from being allocated. + * + * API permits multiple maps to be maintained - for large systems where + * different sets of cpus trace into different independent sinks. + */ + +#include +#include + + +/* architecturally we have 128 IDs some of which are reserved */ +#define CORESIGHT_TRACE_IDS_MAX 128 + +/* ID 0 is reserved */ +#define CORESIGHT_TRACE_ID_RES_0 0 + +/* ID 0x70 onwards are reserved */ +#define CORESIGHT_TRACE_ID_RES_TOP 0x70 + +/* check an ID is in the valid range */ +#define IS_VALID_CS_TRACE_ID(id) \ + ((id > CORESIGHT_TRACE_ID_RES_0) && (id < CORESIGHT_TRACE_ID_RES_TOP)) + +/** + * Trace ID map. + * + * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs. + * Initialised so that the reserved IDs are permanently marked as + * in use. + * @pend_rel_ids: CPU IDs that have been released by the trace source but not + * yet marked as available, to allow re-allocation to the same + * CPU during a perf session. + */ +struct coresight_trace_id_map { + DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX); + DECLARE_BITMAP(pend_rel_ids, CORESIGHT_TRACE_IDS_MAX); +}; + +/* Allocate and release IDs for a single default trace ID map */ + +/** + * Read and optionally allocate a CoreSight trace ID and associate with a CPU. + * + * Function will read the current trace ID for the associated CPU, + * allocating an new ID if one is not currently allocated. + * + * Numeric ID values allocated use legacy allocation algorithm if possible, + * otherwise any available ID is used. + * + * @cpu: The CPU index to allocate for. + * + * return: CoreSight trace ID or -EINVAL if allocation impossible. + */ +int coresight_trace_id_get_cpu_id(int cpu); + +/** + * Release an allocated trace ID associated with the CPU. + * + * This will release the CoreSight trace ID associated with the CPU, + * unless a perf session is in operation. + * + * If a perf session is in operation then the ID will be marked as pending + * release. + * + * @cpu: The CPU index to release the associated trace ID. + */ +void coresight_trace_id_put_cpu_id(int cpu); + +/** + * Read the current allocated CoreSight Trace ID value for the CPU. + * + * Fast read of the current value that does not allocate if no ID allocated + * for the CPU. + * + * Used in perf context where it is known that the value for the CPU will not + * be changing, when perf starts and event on a core and outputs the Trace ID + * for the CPU as a packet in the data file. IDs cannot change during a perf + * session. + * + * This function does not take the lock protecting the ID lists, avoiding + * locking dependency issues with perf locks. + * + * @cpu: The CPU index to read. + * + * return: current value, will be 0 if unallocated. + */ +int coresight_trace_id_read_cpu_id(int cpu); + +/** + * Allocate a CoreSight trace ID for a system component. + * + * Unconditionally allocates a Trace ID, without associating the ID with a CPU. + * + * Used to allocate IDs for system trace sources such as STM. + * + * return: Trace ID or -EINVAL if allocation is impossible. + */ +int coresight_trace_id_get_system_id(void); + +/** + * Release an allocated system trace ID. + * + * Unconditionally release a trace ID allocated to a system component. + * + * @id: value of trace ID allocated. + */ +void coresight_trace_id_put_system_id(int id); + +/* notifiers for perf session start and stop */ + +/** + * Notify the Trace ID allocator that a perf session is starting. + * + * Increase the perf session reference count - called by perf when setting up + * a trace event. + * + * This reference count is used by the ID allocator to ensure that trace IDs + * associated with a CPU cannot change or be released during a perf session. + */ +void coresight_trace_id_perf_start(void); + +/** + * Notify the ID allocator that a perf session is stopping. + * + * Decrease the perf session reference count. + * if this causes the count to go to zero, then all Trace IDs marked as pending + * release, will be released. + */ +void coresight_trace_id_perf_stop(void); + +#endif /* _CORESIGHT_TRACE_ID_H */ diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c new file mode 100644 index 000000000000..b317342c7ce5 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Siemens System Memory Buffer driver. + * Copyright(c) 2022, HiSilicon Limited. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-etm-perf.h" +#include "coresight-priv.h" +#include "ultrasoc-smb.h" + +DEFINE_CORESIGHT_DEVLIST(sink_devs, "ultra_smb"); + +#define ULTRASOC_SMB_DSM_UUID "82ae1283-7f6a-4cbe-aa06-53e8fb24db18" + +static bool smb_buffer_not_empty(struct smb_drv_data *drvdata) +{ + u32 buf_status = readl(drvdata->base + SMB_LB_INT_STS_REG); + + return FIELD_GET(SMB_LB_INT_STS_NOT_EMPTY_MSK, buf_status); +} + +static void smb_update_data_size(struct smb_drv_data *drvdata) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + u32 buf_wrptr; + + buf_wrptr = readl(drvdata->base + SMB_LB_WR_ADDR_REG) - + sdb->buf_hw_base; + + /* Buffer is full */ + if (buf_wrptr == sdb->buf_rdptr && smb_buffer_not_empty(drvdata)) { + sdb->data_size = sdb->buf_size; + return; + } + + /* The buffer mode is circular buffer mode */ + sdb->data_size = CIRC_CNT(buf_wrptr, sdb->buf_rdptr, + sdb->buf_size); +} + +/* + * The read pointer adds @nbytes bytes (may round up to the beginning) + * after the data is read or discarded, while needing to update the + * available data size. + */ +static void smb_update_read_ptr(struct smb_drv_data *drvdata, u32 nbytes) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + + sdb->buf_rdptr += nbytes; + sdb->buf_rdptr %= sdb->buf_size; + writel(sdb->buf_hw_base + sdb->buf_rdptr, + drvdata->base + SMB_LB_RD_ADDR_REG); + + sdb->data_size -= nbytes; +} + +static void smb_reset_buffer(struct smb_drv_data *drvdata) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + u32 write_ptr; + + /* + * We must flush and discard any data left in hardware path + * to avoid corrupting the next session. + * Note: The write pointer will never exceed the read pointer. + */ + writel(SMB_LB_PURGE_PURGED, drvdata->base + SMB_LB_PURGE_REG); + + /* Reset SMB logical buffer status flags */ + writel(SMB_LB_INT_STS_RESET, drvdata->base + SMB_LB_INT_STS_REG); + + write_ptr = readl(drvdata->base + SMB_LB_WR_ADDR_REG); + + /* Do nothing, not data left in hardware path */ + if (!write_ptr || write_ptr == sdb->buf_rdptr + sdb->buf_hw_base) + return; + + /* + * The SMB_LB_WR_ADDR_REG register is read-only, + * Synchronize the read pointer to write pointer. + */ + writel(write_ptr, drvdata->base + SMB_LB_RD_ADDR_REG); + sdb->buf_rdptr = write_ptr - sdb->buf_hw_base; +} + +static int smb_open(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + int ret = 0; + + mutex_lock(&drvdata->mutex); + + if (drvdata->reading) { + ret = -EBUSY; + goto out; + } + + if (atomic_read(drvdata->csdev->refcnt)) { + ret = -EBUSY; + goto out; + } + + smb_update_data_size(drvdata); + + drvdata->reading = true; +out: + mutex_unlock(&drvdata->mutex); + + return ret; +} + +static ssize_t smb_read(struct file *file, char __user *data, size_t len, + loff_t *ppos) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct device *dev = &drvdata->csdev->dev; + ssize_t to_copy = 0; + + if (!len) + return 0; + + mutex_lock(&drvdata->mutex); + + if (!sdb->data_size) + goto out; + + to_copy = min(sdb->data_size, len); + + /* Copy parts of trace data when read pointer wrap around SMB buffer */ + if (sdb->buf_rdptr + to_copy > sdb->buf_size) + to_copy = sdb->buf_size - sdb->buf_rdptr; + + if (copy_to_user(data, sdb->buf_base + sdb->buf_rdptr, to_copy)) { + dev_dbg(dev, "Failed to copy data to user\n"); + to_copy = -EFAULT; + goto out; + } + + *ppos += to_copy; + + smb_update_read_ptr(drvdata, to_copy); + + dev_dbg(dev, "%zu bytes copied\n", to_copy); +out: + if (!sdb->data_size) + smb_reset_buffer(drvdata); + mutex_unlock(&drvdata->mutex); + + return to_copy; +} + +static int smb_release(struct inode *inode, struct file *file) +{ + struct smb_drv_data *drvdata = container_of(file->private_data, + struct smb_drv_data, miscdev); + + mutex_lock(&drvdata->mutex); + drvdata->reading = false; + mutex_unlock(&drvdata->mutex); + + return 0; +} + +static const struct file_operations smb_fops = { + .owner = THIS_MODULE, + .open = smb_open, + .read = smb_read, + .release = smb_release, + .llseek = no_llseek, +}; + +static ssize_t buf_size_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(dev->parent); + + return sysfs_emit(buf, "0x%lx\n", drvdata->sdb.buf_size); +} +static DEVICE_ATTR_RO(buf_size); + +static struct attribute *smb_sink_attrs[] = { + coresight_simple_reg32(read_pos, SMB_LB_RD_ADDR_REG), + coresight_simple_reg32(write_pos, SMB_LB_WR_ADDR_REG), + coresight_simple_reg32(buf_status, SMB_LB_INT_STS_REG), + &dev_attr_buf_size.attr, + NULL +}; + +static const struct attribute_group smb_sink_group = { + .attrs = smb_sink_attrs, + .name = "mgmt", +}; + +static const struct attribute_group *smb_sink_groups[] = { + &smb_sink_group, + NULL +}; + +static void smb_enable_hw(struct smb_drv_data *drvdata) +{ + writel(SMB_GLB_EN_HW_ENABLE, drvdata->base + SMB_GLB_EN_REG); +} + +static void smb_disable_hw(struct smb_drv_data *drvdata) +{ + writel(0x0, drvdata->base + SMB_GLB_EN_REG); +} + +static void smb_enable_sysfs(struct coresight_device *csdev) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + + if (drvdata->mode != CS_MODE_DISABLED) + return; + + smb_enable_hw(drvdata); + drvdata->mode = CS_MODE_SYSFS; +} + +static int smb_enable_perf(struct coresight_device *csdev, void *data) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + struct perf_output_handle *handle = data; + struct cs_buffers *buf = etm_perf_sink_config(handle); + pid_t pid; + + if (!buf) + return -EINVAL; + + /* Get a handle on the pid of the target process */ + pid = buf->pid; + + /* Device is already in used by other session */ + if (drvdata->pid != -1 && drvdata->pid != pid) + return -EBUSY; + + if (drvdata->pid == -1) { + smb_enable_hw(drvdata); + drvdata->pid = pid; + drvdata->mode = CS_MODE_PERF; + } + + return 0; +} + +static int smb_enable(struct coresight_device *csdev, u32 mode, void *data) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret = 0; + + mutex_lock(&drvdata->mutex); + + /* Do nothing, the trace data is reading by other interface now */ + if (drvdata->reading) { + ret = -EBUSY; + goto out; + } + + /* Do nothing, the SMB is already enabled as other mode */ + if (drvdata->mode != CS_MODE_DISABLED && drvdata->mode != mode) { + ret = -EBUSY; + goto out; + } + + switch (mode) { + case CS_MODE_SYSFS: + smb_enable_sysfs(csdev); + break; + case CS_MODE_PERF: + ret = smb_enable_perf(csdev, data); + break; + default: + ret = -EINVAL; + } + + if (ret) + goto out; + + atomic_inc(csdev->refcnt); + + dev_dbg(&csdev->dev, "Ultrasoc SMB enabled\n"); +out: + mutex_unlock(&drvdata->mutex); + + return ret; +} + +static int smb_disable(struct coresight_device *csdev) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret = 0; + + mutex_lock(&drvdata->mutex); + + if (drvdata->reading) { + ret = -EBUSY; + goto out; + } + + if (atomic_dec_return(csdev->refcnt)) { + ret = -EBUSY; + goto out; + } + + /* Complain if we (somehow) got out of sync */ + WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); + + smb_disable_hw(drvdata); + + /* Dissociate from the target process. */ + drvdata->pid = -1; + drvdata->mode = CS_MODE_DISABLED; + + dev_dbg(&csdev->dev, "Ultrasoc SMB disabled\n"); +out: + mutex_unlock(&drvdata->mutex); + + return ret; +} + +static void *smb_alloc_buffer(struct coresight_device *csdev, + struct perf_event *event, void **pages, + int nr_pages, bool overwrite) +{ + struct cs_buffers *buf; + int node; + + node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu); + buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); + if (!buf) + return NULL; + + buf->snapshot = overwrite; + buf->nr_pages = nr_pages; + buf->data_pages = pages; + buf->pid = task_pid_nr(event->owner); + + return buf; +} + +static void smb_free_buffer(void *config) +{ + struct cs_buffers *buf = config; + + kfree(buf); +} + +static void smb_sync_perf_buffer(struct smb_drv_data *drvdata, + struct cs_buffers *buf, + unsigned long head) +{ + struct smb_data_buffer *sdb = &drvdata->sdb; + char **dst_pages = (char **)buf->data_pages; + unsigned long to_copy; + long pg_idx, pg_offset; + + pg_idx = head >> PAGE_SHIFT; + pg_offset = head & (PAGE_SIZE - 1); + + while (sdb->data_size) { + unsigned long pg_space = PAGE_SIZE - pg_offset; + + to_copy = min(sdb->data_size, pg_space); + + /* Copy parts of trace data when read pointer wrap around */ + if (sdb->buf_rdptr + to_copy > sdb->buf_size) + to_copy = sdb->buf_size - sdb->buf_rdptr; + + memcpy(dst_pages[pg_idx] + pg_offset, + sdb->buf_base + sdb->buf_rdptr, to_copy); + + pg_offset += to_copy; + if (pg_offset >= PAGE_SIZE) { + pg_offset = 0; + pg_idx++; + pg_idx %= buf->nr_pages; + } + smb_update_read_ptr(drvdata, to_copy); + } + + smb_reset_buffer(drvdata); +} + +static unsigned long smb_update_buffer(struct coresight_device *csdev, + struct perf_output_handle *handle, + void *sink_config) +{ + struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); + struct smb_data_buffer *sdb = &drvdata->sdb; + struct cs_buffers *buf = sink_config; + unsigned long data_size = 0; + bool lost = false; + + if (!buf) + return 0; + + mutex_lock(&drvdata->mutex); + + /* Don't do anything if another tracer is using this sink. */ + if (atomic_read(csdev->refcnt) != 1) + goto out; + + smb_disable_hw(drvdata); + smb_update_data_size(drvdata); + + /* + * The SMB buffer may be bigger than the space available in the + * perf ring buffer (handle->size). If so advance the offset so + * that we get the latest trace data. + */ + if (sdb->data_size > handle->size) { + smb_update_read_ptr(drvdata, sdb->data_size - handle->size); + lost = true; + } + + data_size = sdb->data_size; + smb_sync_perf_buffer(drvdata, buf, handle->head); + if (!buf->snapshot && lost) + perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); +out: + mutex_unlock(&drvdata->mutex); + + return data_size; +} + +static const struct coresight_ops_sink smb_cs_ops = { + .enable = smb_enable, + .disable = smb_disable, + .alloc_buffer = smb_alloc_buffer, + .free_buffer = smb_free_buffer, + .update_buffer = smb_update_buffer, +}; + +static const struct coresight_ops cs_ops = { + .sink_ops = &smb_cs_ops, +}; + +static int smb_init_data_buffer(struct platform_device *pdev, + struct smb_data_buffer *sdb) +{ + struct resource *res; + void *base; + + res = platform_get_resource(pdev, IORESOURCE_MEM, SMB_BUF_ADDR_RES); + if (!res) { + dev_err(&pdev->dev, "SMB device failed to get resource\n"); + return -EINVAL; + } + + sdb->buf_rdptr = 0; + sdb->buf_hw_base = FIELD_GET(SMB_BUF_ADDR_LO_MSK, res->start); + sdb->buf_size = resource_size(res); + if (sdb->buf_size == 0) + return -EINVAL; + + /* + * This is a chunk of memory, use classic mapping with better + * performance. + */ + base = devm_memremap(&pdev->dev, sdb->buf_hw_base, sdb->buf_size, + MEMREMAP_WB); + if (IS_ERR(base)) + return PTR_ERR(base); + + sdb->buf_base = base; + + return 0; +} + +static void smb_init_hw(struct smb_drv_data *drvdata) +{ + smb_disable_hw(drvdata); + smb_reset_buffer(drvdata); + + writel(SMB_LB_CFG_LO_DEFAULT, drvdata->base + SMB_LB_CFG_LO_REG); + writel(SMB_LB_CFG_HI_DEFAULT, drvdata->base + SMB_LB_CFG_HI_REG); + writel(SMB_GLB_CFG_DEFAULT, drvdata->base + SMB_GLB_CFG_REG); + writel(SMB_GLB_INT_CFG, drvdata->base + SMB_GLB_INT_REG); + writel(SMB_LB_INT_CTRL_CFG, drvdata->base + SMB_LB_INT_CTRL_REG); +} + +static int smb_register_sink(struct platform_device *pdev, + struct smb_drv_data *drvdata) +{ + struct coresight_platform_data *pdata = NULL; + struct coresight_desc desc = { 0 }; + int ret; + + pdata = coresight_get_platform_data(&pdev->dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + desc.type = CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; + desc.ops = &cs_ops; + desc.pdata = pdata; + desc.dev = &pdev->dev; + desc.groups = smb_sink_groups; + desc.name = coresight_alloc_device_name(&sink_devs, &pdev->dev); + if (!desc.name) { + dev_err(&pdev->dev, "Failed to alloc coresight device name"); + return -ENOMEM; + } + desc.access = CSDEV_ACCESS_IOMEM(drvdata->base); + + drvdata->csdev = coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = desc.name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &smb_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) { + coresight_unregister(drvdata->csdev); + dev_err(&pdev->dev, "Failed to register misc, ret=%d\n", ret); + } + + return ret; +} + +static void smb_unregister_sink(struct smb_drv_data *drvdata) +{ + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); +} + +static int smb_config_inport(struct device *dev, bool enable) +{ + u64 func = enable ? 1 : 0; + union acpi_object *obj; + guid_t guid; + u64 rev = 0; + + /* + * Using DSM calls to enable/disable ultrasoc hardwares on + * tracing path, to prevent ultrasoc packet format being exposed. + */ + if (guid_parse(ULTRASOC_SMB_DSM_UUID, &guid)) { + dev_err(dev, "Get GUID failed\n"); + return -EINVAL; + } + + obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, rev, func, NULL); + if (!obj) { + dev_err(dev, "ACPI handle failed\n"); + return -ENODEV; + } + + ACPI_FREE(obj); + + return 0; +} + +static int smb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct smb_drv_data *drvdata; + int ret; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->base = devm_platform_ioremap_resource(pdev, SMB_REG_ADDR_RES); + if (IS_ERR(drvdata->base)) { + dev_err(dev, "Failed to ioremap resource\n"); + return PTR_ERR(drvdata->base); + } + + smb_init_hw(drvdata); + + ret = smb_init_data_buffer(pdev, &drvdata->sdb); + if (ret) { + dev_err(dev, "Failed to init buffer, ret = %d\n", ret); + return ret; + } + + mutex_init(&drvdata->mutex); + drvdata->pid = -1; + + ret = smb_register_sink(pdev, drvdata); + if (ret) { + dev_err(dev, "Failed to register SMB sink\n"); + return ret; + } + + ret = smb_config_inport(dev, true); + if (ret) { + smb_unregister_sink(drvdata); + return ret; + } + + platform_set_drvdata(pdev, drvdata); + + return 0; +} + +static int smb_remove(struct platform_device *pdev) +{ + struct smb_drv_data *drvdata = platform_get_drvdata(pdev); + int ret; + + ret = smb_config_inport(&pdev->dev, false); + if (ret) + return ret; + + smb_unregister_sink(drvdata); + + return 0; +} + +#ifdef CONFIG_ACPI +static const struct acpi_device_id ultrasoc_smb_acpi_match[] = { + {"HISI03A1", 0}, + {} +}; +MODULE_DEVICE_TABLE(acpi, ultrasoc_smb_acpi_match); +#endif + +static struct platform_driver smb_driver = { + .driver = { + .name = "ultrasoc-smb", + .acpi_match_table = ACPI_PTR(ultrasoc_smb_acpi_match), + .suppress_bind_attrs = true, + }, + .probe = smb_probe, + .remove = smb_remove, +}; +module_platform_driver(smb_driver); + +MODULE_DESCRIPTION("UltraSoc SMB CoreSight driver"); +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Jonathan Zhou "); +MODULE_AUTHOR("Qi Liu "); diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.h b/drivers/hwtracing/coresight/ultrasoc-smb.h new file mode 100644 index 000000000000..7dfbe42e37a0 --- /dev/null +++ b/drivers/hwtracing/coresight/ultrasoc-smb.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Siemens System Memory Buffer driver. + * Copyright(c) 2022, HiSilicon Limited. + */ + +#ifndef _ULTRASOC_SMB_H +#define _ULTRASOC_SMB_H + +#include +#include + +/* Offset of SMB global registers */ +#define SMB_GLB_CFG_REG 0x00 +#define SMB_GLB_EN_REG 0x04 +#define SMB_GLB_INT_REG 0x08 + +/* Offset of SMB logical buffer registers */ +#define SMB_LB_CFG_LO_REG 0x40 +#define SMB_LB_CFG_HI_REG 0x44 +#define SMB_LB_INT_CTRL_REG 0x48 +#define SMB_LB_INT_STS_REG 0x4c +#define SMB_LB_RD_ADDR_REG 0x5c +#define SMB_LB_WR_ADDR_REG 0x60 +#define SMB_LB_PURGE_REG 0x64 + +/* Set global config register */ +#define SMB_GLB_CFG_BURST_LEN_MSK GENMASK(11, 4) +#define SMB_GLB_CFG_IDLE_PRD_MSK GENMASK(15, 12) +#define SMB_GLB_CFG_MEM_WR_MSK GENMASK(21, 16) +#define SMB_GLB_CFG_MEM_RD_MSK GENMASK(27, 22) +#define SMB_GLB_CFG_DEFAULT (FIELD_PREP(SMB_GLB_CFG_BURST_LEN_MSK, 0xf) | \ + FIELD_PREP(SMB_GLB_CFG_IDLE_PRD_MSK, 0xf) | \ + FIELD_PREP(SMB_GLB_CFG_MEM_WR_MSK, 0x3) | \ + FIELD_PREP(SMB_GLB_CFG_MEM_RD_MSK, 0x1b)) + +#define SMB_GLB_EN_HW_ENABLE BIT(0) + +/* Set global interrupt control register */ +#define SMB_GLB_INT_EN BIT(0) +#define SMB_GLB_INT_PULSE BIT(1) /* Interrupt type: 1 - Pulse */ +#define SMB_GLB_INT_ACT_H BIT(2) /* Interrupt polarity: 1 - Active high */ +#define SMB_GLB_INT_CFG (SMB_GLB_INT_EN | SMB_GLB_INT_PULSE | \ + SMB_GLB_INT_ACT_H) + +/* Set logical buffer config register lower 32 bits */ +#define SMB_LB_CFG_LO_EN BIT(0) +#define SMB_LB_CFG_LO_SINGLE_END BIT(1) +#define SMB_LB_CFG_LO_INIT BIT(8) +#define SMB_LB_CFG_LO_CONT BIT(11) +#define SMB_LB_CFG_LO_FLOW_MSK GENMASK(19, 16) +#define SMB_LB_CFG_LO_DEFAULT (SMB_LB_CFG_LO_EN | SMB_LB_CFG_LO_SINGLE_END | \ + SMB_LB_CFG_LO_INIT | SMB_LB_CFG_LO_CONT | \ + FIELD_PREP(SMB_LB_CFG_LO_FLOW_MSK, 0xf)) + +/* Set logical buffer config register upper 32 bits */ +#define SMB_LB_CFG_HI_RANGE_UP_MSK GENMASK(15, 8) +#define SMB_LB_CFG_HI_DEFAULT FIELD_PREP(SMB_LB_CFG_HI_RANGE_UP_MSK, 0xff) + +/* + * Set logical buffer interrupt control register. + * The register control the validity of both real-time events and + * interrupts. When logical buffer status changes causes to issue + * an interrupt at the same time as it issues a real-time event. + * Real-time events are used in SMB driver, which needs to get the buffer + * status. Interrupts are used in debugger mode. + * SMB_LB_INT_CTRL_BUF_NOTE_MASK control which events flags or interrupts + * are valid. + */ +#define SMB_LB_INT_CTRL_EN BIT(0) +#define SMB_LB_INT_CTRL_BUF_NOTE_MSK GENMASK(11, 8) +#define SMB_LB_INT_CTRL_CFG (SMB_LB_INT_CTRL_EN | \ + FIELD_PREP(SMB_LB_INT_CTRL_BUF_NOTE_MSK, 0xf)) + +/* Set logical buffer interrupt status register */ +#define SMB_LB_INT_STS_NOT_EMPTY_MSK BIT(0) +#define SMB_LB_INT_STS_BUF_RESET_MSK GENMASK(3, 0) +#define SMB_LB_INT_STS_RESET FIELD_PREP(SMB_LB_INT_STS_BUF_RESET_MSK, 0xf) + +#define SMB_LB_PURGE_PURGED BIT(0) + +#define SMB_REG_ADDR_RES 0 +#define SMB_BUF_ADDR_RES 1 +#define SMB_BUF_ADDR_LO_MSK GENMASK(31, 0) + +/** + * struct smb_data_buffer - Details of the buffer used by SMB + * @buf_base: Memory mapped base address of SMB. + * @buf_hw_base: SMB buffer start Physical base address, only used 32bits. + * @buf_size: Size of the buffer. + * @data_size: Size of the available trace data for SMB. + * @buf_rdptr: Current read position (index) within the buffer. + */ +struct smb_data_buffer { + void *buf_base; + u32 buf_hw_base; + unsigned long buf_size; + unsigned long data_size; + unsigned long buf_rdptr; +}; + +/** + * struct smb_drv_data - specifics associated to an SMB component + * @base: Memory mapped base address for SMB component. + * @csdev: Component vitals needed by the framework. + * @sdb: Data buffer for SMB. + * @miscdev: Specifics to handle "/dev/xyz.smb" entry. + * @mutex: Control data access to one at a time. + * @reading: Synchronise user space access to SMB buffer. + * @pid: Process ID of the process being monitored by the + * session that is using this component. + * @mode: How this SMB is being used, perf mode or sysfs mode. + */ +struct smb_drv_data { + void __iomem *base; + struct coresight_device *csdev; + struct smb_data_buffer sdb; + struct miscdevice miscdev; + struct mutex mutex; + bool reading; + pid_t pid; + u32 mode; +}; + +#endif diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c index 5d5526aa60c4..30f1525639b5 100644 --- a/drivers/hwtracing/ptt/hisi_ptt.c +++ b/drivers/hwtracing/ptt/hisi_ptt.c @@ -356,8 +356,18 @@ static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt) static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data) { + struct pci_dev *root_port = pcie_find_root_port(pdev); struct hisi_ptt_filter_desc *filter; struct hisi_ptt *hisi_ptt = data; + u32 port_devid; + + if (!root_port) + return 0; + + port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn); + if (port_devid < hisi_ptt->lower_bdf || + port_devid > hisi_ptt->upper_bdf) + return 0; /* * We won't fail the probe if filter allocation failed here. The filters diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c index fd70794bfcee..80d586b0be7a 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #define SE_I2C_TX_TRANS_LEN 0x26c diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig index 03ac410c162e..b6b45d359f28 100644 --- a/drivers/iio/accel/Kconfig +++ b/drivers/iio/accel/Kconfig @@ -380,7 +380,7 @@ config IIO_ST_ACCEL_3AXIS select IIO_TRIGGERED_BUFFER if (IIO_BUFFER) help Say yes here to build support for STMicroelectronics accelerometers: - LSM303DLH, LSM303DLHC, LIS3DH, LSM330D, LSM330DL, LSM330DLC, + LSM303C, LSM303DLH, LSM303DLHC, LIS3DH, LSM330D, LSM330DL, LSM330DLC, LIS331DLH, LSM303DL, LSM303DLM, LSM330, LIS2DH12, H3LIS331DL, LNG2DM, LIS3DE, LIS2DE12, LIS2HH12 diff --git a/drivers/iio/accel/bma400.h b/drivers/iio/accel/bma400.h index 36edbaff4f7f..932358b45f17 100644 --- a/drivers/iio/accel/bma400.h +++ b/drivers/iio/accel/bma400.h @@ -141,10 +141,6 @@ #define BMA400_SCALE_MIN 9577 #define BMA400_SCALE_MAX 76617 -#define BMA400_NUM_REGULATORS 2 -#define BMA400_VDD_REGULATOR 0 -#define BMA400_VDDIO_REGULATOR 1 - extern const struct regmap_config bma400_regmap_config; int bma400_probe(struct device *dev, struct regmap *regmap, int irq, diff --git a/drivers/iio/accel/bma400_core.c b/drivers/iio/accel/bma400_core.c index b612d0146d4d..623f37cbaf50 100644 --- a/drivers/iio/accel/bma400_core.c +++ b/drivers/iio/accel/bma400_core.c @@ -98,7 +98,6 @@ enum bma400_activity { struct bma400_data { struct device *dev; struct regmap *regmap; - struct regulator_bulk_data regulators[BMA400_NUM_REGULATORS]; struct mutex mutex; /* data register lock */ struct iio_mount_matrix orientation; enum bma400_power_mode power_mode; @@ -832,13 +831,6 @@ static void bma400_init_tables(void) } } -static void bma400_regulators_disable(void *data_ptr) -{ - struct bma400_data *data = data_ptr; - - regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators); -} - static void bma400_power_disable(void *data_ptr) { struct bma400_data *data = data_ptr; @@ -868,30 +860,17 @@ static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity) static int bma400_init(struct bma400_data *data) { + static const char * const regulator_names[] = { "vdd", "vddio" }; unsigned int val; int ret; - data->regulators[BMA400_VDD_REGULATOR].supply = "vdd"; - data->regulators[BMA400_VDDIO_REGULATOR].supply = "vddio"; - ret = devm_regulator_bulk_get(data->dev, - ARRAY_SIZE(data->regulators), - data->regulators); + ret = devm_regulator_bulk_get_enable(data->dev, + ARRAY_SIZE(regulator_names), + regulator_names); if (ret) return dev_err_probe(data->dev, ret, "Failed to get regulators: %d\n", ret); - ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators), - data->regulators); - if (ret) { - dev_err(data->dev, "Failed to enable regulators: %d\n", - ret); - return ret; - } - - ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data); - if (ret) - return ret; - /* Try to read chip_id register. It must return 0x90. */ ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val); if (ret) { diff --git a/drivers/iio/accel/mma9551_core.c b/drivers/iio/accel/mma9551_core.c index 64ca7d7a9673..b898f865fb87 100644 --- a/drivers/iio/accel/mma9551_core.c +++ b/drivers/iio/accel/mma9551_core.c @@ -296,9 +296,12 @@ int mma9551_read_config_word(struct i2c_client *client, u8 app_id, ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_CONFIG, reg, NULL, 0, (u8 *)&v, 2); + if (ret < 0) + return ret; + *val = be16_to_cpu(v); - return ret; + return 0; } EXPORT_SYMBOL_NS(mma9551_read_config_word, IIO_MMA9551); @@ -354,9 +357,12 @@ int mma9551_read_status_word(struct i2c_client *client, u8 app_id, ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_STATUS, reg, NULL, 0, (u8 *)&v, 2); + if (ret < 0) + return ret; + *val = be16_to_cpu(v); - return ret; + return 0; } EXPORT_SYMBOL_NS(mma9551_read_status_word, IIO_MMA9551); diff --git a/drivers/iio/accel/st_accel.h b/drivers/iio/accel/st_accel.h index 5b0f54e33d9e..56ed0c776d4a 100644 --- a/drivers/iio/accel/st_accel.h +++ b/drivers/iio/accel/st_accel.h @@ -37,6 +37,7 @@ #define LIS2DE12_ACCEL_DEV_NAME "lis2de12" #define LIS2HH12_ACCEL_DEV_NAME "lis2hh12" #define LIS302DL_ACCEL_DEV_NAME "lis302dl" +#define LSM303C_ACCEL_DEV_NAME "lsm303c_accel" #define SC7A20_ACCEL_DEV_NAME "sc7a20" diff --git a/drivers/iio/accel/st_accel_core.c b/drivers/iio/accel/st_accel_core.c index c8c8eb15c34e..6b8562f684d5 100644 --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -929,6 +929,7 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = { .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS, .sensors_supported = { [0] = LIS2HH12_ACCEL_DEV_NAME, + [1] = LSM303C_ACCEL_DEV_NAME, }, .ch = (struct iio_chan_spec *)st_accel_16bit_channels, .odr = { diff --git a/drivers/iio/accel/st_accel_i2c.c b/drivers/iio/accel/st_accel_i2c.c index 45ee0ddc133c..3f02fd5d5946 100644 --- a/drivers/iio/accel/st_accel_i2c.c +++ b/drivers/iio/accel/st_accel_i2c.c @@ -111,6 +111,10 @@ static const struct of_device_id st_accel_of_match[] = { .compatible = "st,lis302dl", .data = LIS302DL_ACCEL_DEV_NAME, }, + { + .compatible = "st,lsm303c-accel", + .data = LSM303C_ACCEL_DEV_NAME, + }, { .compatible = "silan,sc7a20", .data = SC7A20_ACCEL_DEV_NAME, @@ -151,6 +155,7 @@ static const struct i2c_device_id st_accel_id_table[] = { { LIS2DE12_ACCEL_DEV_NAME }, { LIS2HH12_ACCEL_DEV_NAME }, { LIS302DL_ACCEL_DEV_NAME }, + { LSM303C_ACCEL_DEV_NAME }, { SC7A20_ACCEL_DEV_NAME }, {}, }; diff --git a/drivers/iio/accel/st_accel_spi.c b/drivers/iio/accel/st_accel_spi.c index 6c0917750288..5740dc1820bd 100644 --- a/drivers/iio/accel/st_accel_spi.c +++ b/drivers/iio/accel/st_accel_spi.c @@ -96,6 +96,10 @@ static const struct of_device_id st_accel_of_match[] = { .compatible = "st,lis302dl", .data = LIS302DL_ACCEL_DEV_NAME, }, + { + .compatible = "st,lsm303c-accel", + .data = LSM303C_ACCEL_DEV_NAME, + }, {} }; MODULE_DEVICE_TABLE(of, st_accel_of_match); @@ -152,6 +156,7 @@ static const struct spi_device_id st_accel_id_table[] = { { LIS3DHH_ACCEL_DEV_NAME }, { LIS3DE_ACCEL_DEV_NAME }, { LIS302DL_ACCEL_DEV_NAME }, + { LSM303C_ACCEL_DEV_NAME }, {}, }; MODULE_DEVICE_TABLE(spi, st_accel_id_table); diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 99cd305b59d9..45af2302be53 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -441,7 +441,8 @@ config ENVELOPE_DETECTOR config EP93XX_ADC tristate "Cirrus Logic EP93XX ADC driver" - depends on ARCH_EP93XX + depends on ARCH_EP93XX || COMPILE_TEST + depends on HAS_IOMEM help Driver for the ADC module on the EP93XX series of SoC from Cirrus Logic. It's recommended to switch on CONFIG_HIGH_RES_TIMERS option, in this @@ -565,6 +566,16 @@ config IMX8QXP_ADC This driver can also be built as a module. If so, the module will be called imx8qxp-adc. +config IMX93_ADC + tristate "IMX93 ADC driver" + depends on ARCH_MXC || COMPILE_TEST + depends on HAS_IOMEM + help + Say yes here to build support for IMX93 ADC. + + This driver can also be built as a module. If so, the module will be + called imx93_adc. + config LP8788_ADC tristate "LP8788 ADC driver" depends on MFD_LP8788 @@ -1207,6 +1218,17 @@ config TI_ADS1015 This driver can also be built as a module. If so, the module will be called ti-ads1015. +config TI_ADS7924 + tristate "Texas Instruments ADS7924 ADC" + depends on I2C + select REGMAP_I2C + help + If you say yes here you get support for Texas Instruments ADS7924 + 4 channels, 12-bit I2C ADC chip. + + This driver can also be built as a module. If so, the module will be + called ti-ads7924. + config TI_ADS7950 tristate "Texas Instruments ADS7950 ADC driver" depends on SPI && GPIOLIB @@ -1274,6 +1296,16 @@ config TI_AM335X_ADC To compile this driver as a module, choose M here: the module will be called ti_am335x_adc. +config TI_LMP92064 + tristate "Texas Instruments LMP92064 ADC driver" + depends on SPI + help + Say yes here to build support for the LMP92064 Precision Current and Voltage + sensor. + + This driver can also be built as a module. If so, the module will be called + ti-lmp92064. + config TI_TLC4541 tristate "Texas Instruments TLC4541 ADC driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 4ef41a7dfac6..36c18177322a 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_HI8435) += hi8435.o obj-$(CONFIG_HX711) += hx711.o obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o obj-$(CONFIG_IMX8QXP_ADC) += imx8qxp-adc.o +obj-$(CONFIG_IMX93_ADC) += imx93_adc.o obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o obj-$(CONFIG_INGENIC_ADC) += ingenic-adc.o obj-$(CONFIG_INTEL_MRFLD_ADC) += intel_mrfld_adc.o @@ -107,12 +108,14 @@ obj-$(CONFIG_TI_ADC108S102) += ti-adc108s102.o obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o +obj-$(CONFIG_TI_ADS7924) += ti-ads7924.o obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o obj-$(CONFIG_TI_ADS8344) += ti-ads8344.o obj-$(CONFIG_TI_ADS8688) += ti-ads8688.o obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o obj-$(CONFIG_TI_ADS131E08) += ti-ads131e08.o obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o +obj-$(CONFIG_TI_LMP92064) += ti-lmp92064.o obj-$(CONFIG_TI_TLC4541) += ti-tlc4541.o obj-$(CONFIG_TI_TSC2046) += ti-tsc2046.o obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o diff --git a/drivers/iio/adc/ad7291.c b/drivers/iio/adc/ad7291.c index 3dd0105f63d7..f9ee189925de 100644 --- a/drivers/iio/adc/ad7291.c +++ b/drivers/iio/adc/ad7291.c @@ -179,7 +179,7 @@ static unsigned int ad7291_threshold_reg(const struct iio_chan_spec *chan, offset = AD7291_VOLTAGE_OFFSET; break; default: - return 0; + return 0; } switch (info) { diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index ed4f8501bda8..50d02e5fc6fc 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -2181,7 +2181,7 @@ static ssize_t at91_adc_get_fifo_state(struct device *dev, struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct at91_adc_state *st = iio_priv(indio_dev); - return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan); + return sysfs_emit(buf, "%d\n", !!st->dma_st.dma_chan); } static ssize_t at91_adc_get_watermark(struct device *dev, @@ -2190,7 +2190,7 @@ static ssize_t at91_adc_get_watermark(struct device *dev, struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct at91_adc_state *st = iio_priv(indio_dev); - return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); + return sysfs_emit(buf, "%d\n", st->dma_st.watermark); } static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, diff --git a/drivers/iio/adc/ep93xx_adc.c b/drivers/iio/adc/ep93xx_adc.c index fd5a9404c8dc..a35e6cead67d 100644 --- a/drivers/iio/adc/ep93xx_adc.c +++ b/drivers/iio/adc/ep93xx_adc.c @@ -21,6 +21,7 @@ #include #include #include +#include /* * This code could benefit from real HR Timers, but jiffy granularity would @@ -227,9 +228,16 @@ static int ep93xx_adc_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id ep93xx_adc_of_ids[] = { + { .compatible = "cirrus,ep9301-adc" }, + {} +}; +MODULE_DEVICE_TABLE(of, ep93xx_adc_of_ids); + static struct platform_driver ep93xx_adc_driver = { .driver = { .name = "ep93xx-adc", + .of_match_table = ep93xx_adc_of_ids, }, .probe = ep93xx_adc_probe, .remove = ep93xx_adc_remove, diff --git a/drivers/iio/adc/imx93_adc.c b/drivers/iio/adc/imx93_adc.c new file mode 100644 index 000000000000..a775d2e40567 --- /dev/null +++ b/drivers/iio/adc/imx93_adc.c @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NXP i.MX93 ADC driver + * + * Copyright 2023 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IMX93_ADC_DRIVER_NAME "imx93-adc" + +/* Register map definition */ +#define IMX93_ADC_MCR 0x00 +#define IMX93_ADC_MSR 0x04 +#define IMX93_ADC_ISR 0x10 +#define IMX93_ADC_IMR 0x20 +#define IMX93_ADC_CIMR0 0x24 +#define IMX93_ADC_CTR0 0x94 +#define IMX93_ADC_NCMR0 0xA4 +#define IMX93_ADC_PCDR0 0x100 +#define IMX93_ADC_PCDR1 0x104 +#define IMX93_ADC_PCDR2 0x108 +#define IMX93_ADC_PCDR3 0x10c +#define IMX93_ADC_PCDR4 0x110 +#define IMX93_ADC_PCDR5 0x114 +#define IMX93_ADC_PCDR6 0x118 +#define IMX93_ADC_PCDR7 0x11c +#define IMX93_ADC_CALSTAT 0x39C + +/* ADC bit shift */ +#define IMX93_ADC_MCR_MODE_MASK BIT(29) +#define IMX93_ADC_MCR_NSTART_MASK BIT(24) +#define IMX93_ADC_MCR_CALSTART_MASK BIT(14) +#define IMX93_ADC_MCR_ADCLKSE_MASK BIT(8) +#define IMX93_ADC_MCR_PWDN_MASK BIT(0) +#define IMX93_ADC_MSR_CALFAIL_MASK BIT(30) +#define IMX93_ADC_MSR_CALBUSY_MASK BIT(29) +#define IMX93_ADC_MSR_ADCSTATUS_MASK GENMASK(2, 0) +#define IMX93_ADC_ISR_ECH_MASK BIT(0) +#define IMX93_ADC_ISR_EOC_MASK BIT(1) +#define IMX93_ADC_ISR_EOC_ECH_MASK (IMX93_ADC_ISR_EOC_MASK | \ + IMX93_ADC_ISR_ECH_MASK) +#define IMX93_ADC_IMR_JEOC_MASK BIT(3) +#define IMX93_ADC_IMR_JECH_MASK BIT(2) +#define IMX93_ADC_IMR_EOC_MASK BIT(1) +#define IMX93_ADC_IMR_ECH_MASK BIT(0) +#define IMX93_ADC_PCDR_CDATA_MASK GENMASK(11, 0) + +/* ADC status */ +#define IMX93_ADC_MSR_ADCSTATUS_IDLE 0 +#define IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN 1 +#define IMX93_ADC_MSR_ADCSTATUS_WAIT_STATE 2 +#define IMX93_ADC_MSR_ADCSTATUS_BUSY_IN_CALIBRATION 3 +#define IMX93_ADC_MSR_ADCSTATUS_SAMPLE 4 +#define IMX93_ADC_MSR_ADCSTATUS_CONVERSION 6 + +#define IMX93_ADC_TIMEOUT msecs_to_jiffies(100) + +struct imx93_adc { + struct device *dev; + void __iomem *regs; + struct clk *ipg_clk; + int irq; + struct regulator *vref; + /* lock to protect against multiple access to the device */ + struct mutex lock; + struct completion completion; +}; + +#define IMX93_ADC_CHAN(_idx) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = (_idx), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ), \ +} + +static const struct iio_chan_spec imx93_adc_iio_channels[] = { + IMX93_ADC_CHAN(0), + IMX93_ADC_CHAN(1), + IMX93_ADC_CHAN(2), + IMX93_ADC_CHAN(3), +}; + +static void imx93_adc_power_down(struct imx93_adc *adc) +{ + u32 mcr, msr; + int ret; + + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, + ((msr & IMX93_ADC_MSR_ADCSTATUS_MASK) == + IMX93_ADC_MSR_ADCSTATUS_POWER_DOWN), + 1, 50); + if (ret == -ETIMEDOUT) + dev_warn(adc->dev, + "ADC do not in power down mode, current MSR is %x\n", + msr); +} + +static void imx93_adc_power_up(struct imx93_adc *adc) +{ + u32 mcr; + + /* bring ADC out of power down state, in idle state */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); +} + +static void imx93_adc_config_ad_clk(struct imx93_adc *adc) +{ + u32 mcr; + + /* put adc in power down mode */ + imx93_adc_power_down(adc); + + /* config the AD_CLK equal to bus clock */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + imx93_adc_power_up(adc); +} + +static int imx93_adc_calibration(struct imx93_adc *adc) +{ + u32 mcr, msr; + int ret; + + /* make sure ADC in power down mode */ + imx93_adc_power_down(adc); + + /* config SAR controller operating clock */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr &= ~FIELD_PREP(IMX93_ADC_MCR_ADCLKSE_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + imx93_adc_power_up(adc); + + /* + * TODO: we use the default TSAMP/NRSMPL/AVGEN in MCR, + * can add the setting of these bit if need in future. + */ + + /* run calibration */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_CALSTART_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + /* wait calibration to be finished */ + ret = readl_poll_timeout(adc->regs + IMX93_ADC_MSR, msr, + !(msr & IMX93_ADC_MSR_CALBUSY_MASK), 1000, 2000000); + if (ret == -ETIMEDOUT) { + dev_warn(adc->dev, "ADC do not finish calibration in 2 min!\n"); + imx93_adc_power_down(adc); + return ret; + } + + /* check whether calbration is success or not */ + msr = readl(adc->regs + IMX93_ADC_MSR); + if (msr & IMX93_ADC_MSR_CALFAIL_MASK) { + dev_warn(adc->dev, "ADC calibration failed!\n"); + imx93_adc_power_down(adc); + return -EAGAIN; + } + + return 0; +} + +static int imx93_adc_read_channel_conversion(struct imx93_adc *adc, + int channel_number, + int *result) +{ + u32 channel; + u32 imr, mcr, pcda; + long ret; + + reinit_completion(&adc->completion); + + /* config channel mask register */ + channel = 1 << channel_number; + writel(channel, adc->regs + IMX93_ADC_NCMR0); + + /* TODO: can config desired sample time in CTRn if need */ + + /* config interrupt mask */ + imr = FIELD_PREP(IMX93_ADC_IMR_EOC_MASK, 1); + writel(imr, adc->regs + IMX93_ADC_IMR); + writel(channel, adc->regs + IMX93_ADC_CIMR0); + + /* config one-shot mode */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr &= ~FIELD_PREP(IMX93_ADC_MCR_MODE_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + /* start normal conversion */ + mcr = readl(adc->regs + IMX93_ADC_MCR); + mcr |= FIELD_PREP(IMX93_ADC_MCR_NSTART_MASK, 1); + writel(mcr, adc->regs + IMX93_ADC_MCR); + + ret = wait_for_completion_interruptible_timeout(&adc->completion, + IMX93_ADC_TIMEOUT); + if (ret == 0) + return -ETIMEDOUT; + + if (ret < 0) + return ret; + + pcda = readl(adc->regs + IMX93_ADC_PCDR0 + channel_number * 4); + + *result = FIELD_GET(IMX93_ADC_PCDR_CDATA_MASK, pcda); + + return ret; +} + +static int imx93_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct imx93_adc *adc = iio_priv(indio_dev); + struct device *dev = adc->dev; + long ret; + u32 vref_uv; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + pm_runtime_get_sync(dev); + mutex_lock(&adc->lock); + ret = imx93_adc_read_channel_conversion(adc, chan->channel, val); + mutex_unlock(&adc->lock); + pm_runtime_mark_last_busy(dev); + pm_runtime_put_sync_autosuspend(dev); + if (ret < 0) + return ret; + + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + ret = vref_uv = regulator_get_voltage(adc->vref); + if (ret < 0) + return ret; + *val = vref_uv / 1000; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + + case IIO_CHAN_INFO_SAMP_FREQ: + *val = clk_get_rate(adc->ipg_clk); + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static irqreturn_t imx93_adc_isr(int irq, void *dev_id) +{ + struct imx93_adc *adc = dev_id; + u32 isr, eoc, unexpected; + + isr = readl(adc->regs + IMX93_ADC_ISR); + + if (FIELD_GET(IMX93_ADC_ISR_EOC_ECH_MASK, isr)) { + eoc = isr & IMX93_ADC_ISR_EOC_ECH_MASK; + writel(eoc, adc->regs + IMX93_ADC_ISR); + complete(&adc->completion); + } + + unexpected = isr & ~IMX93_ADC_ISR_EOC_ECH_MASK; + if (unexpected) { + writel(unexpected, adc->regs + IMX93_ADC_ISR); + dev_err(adc->dev, "Unexpected interrupt 0x%08x.\n", unexpected); + return IRQ_NONE; + } + + return IRQ_HANDLED; +} + +static const struct iio_info imx93_adc_iio_info = { + .read_raw = &imx93_adc_read_raw, +}; + +static int imx93_adc_probe(struct platform_device *pdev) +{ + struct imx93_adc *adc; + struct iio_dev *indio_dev; + struct device *dev = &pdev->dev; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return dev_err_probe(dev, -ENOMEM, + "Failed allocating iio device\n"); + + adc = iio_priv(indio_dev); + adc->dev = dev; + + mutex_init(&adc->lock); + adc->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(adc->regs)) + return dev_err_probe(dev, PTR_ERR(adc->regs), + "Failed getting ioremap resource\n"); + + /* The third irq is for ADC conversion usage */ + adc->irq = platform_get_irq(pdev, 2); + if (adc->irq < 0) + return adc->irq; + + adc->ipg_clk = devm_clk_get(dev, "ipg"); + if (IS_ERR(adc->ipg_clk)) + return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), + "Failed getting clock.\n"); + + adc->vref = devm_regulator_get(dev, "vref"); + if (IS_ERR(adc->vref)) + return dev_err_probe(dev, PTR_ERR(adc->vref), + "Failed getting reference voltage.\n"); + + ret = regulator_enable(adc->vref); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable reference voltage.\n"); + + platform_set_drvdata(pdev, indio_dev); + + init_completion(&adc->completion); + + indio_dev->name = "imx93-adc"; + indio_dev->info = &imx93_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = imx93_adc_iio_channels; + indio_dev->num_channels = ARRAY_SIZE(imx93_adc_iio_channels); + + ret = clk_prepare_enable(adc->ipg_clk); + if (ret) { + dev_err_probe(dev, ret, + "Failed to enable ipg clock.\n"); + goto error_regulator_disable; + } + + ret = request_irq(adc->irq, imx93_adc_isr, 0, IMX93_ADC_DRIVER_NAME, adc); + if (ret < 0) { + dev_err_probe(dev, ret, + "Failed requesting irq, irq = %d\n", adc->irq); + goto error_ipg_clk_disable; + } + + ret = imx93_adc_calibration(adc); + if (ret < 0) + goto error_free_adc_irq; + + imx93_adc_config_ad_clk(adc); + + ret = iio_device_register(indio_dev); + if (ret) { + dev_err_probe(dev, ret, + "Failed to register this iio device.\n"); + goto error_adc_power_down; + } + + pm_runtime_set_active(dev); + pm_runtime_set_autosuspend_delay(dev, 50); + pm_runtime_use_autosuspend(dev); + pm_runtime_enable(dev); + + return 0; + +error_adc_power_down: + imx93_adc_power_down(adc); +error_free_adc_irq: + free_irq(adc->irq, adc); +error_ipg_clk_disable: + clk_disable_unprepare(adc->ipg_clk); +error_regulator_disable: + regulator_disable(adc->vref); + + return ret; +} + +static int imx93_adc_remove(struct platform_device *pdev) +{ + struct iio_dev *indio_dev = platform_get_drvdata(pdev); + struct imx93_adc *adc = iio_priv(indio_dev); + struct device *dev = adc->dev; + + /* adc power down need clock on */ + pm_runtime_get_sync(dev); + + pm_runtime_disable(dev); + pm_runtime_dont_use_autosuspend(dev); + pm_runtime_put_noidle(dev); + + iio_device_unregister(indio_dev); + imx93_adc_power_down(adc); + free_irq(adc->irq, adc); + clk_disable_unprepare(adc->ipg_clk); + regulator_disable(adc->vref); + + return 0; +} + +static int imx93_adc_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct imx93_adc *adc = iio_priv(indio_dev); + + imx93_adc_power_down(adc); + clk_disable_unprepare(adc->ipg_clk); + regulator_disable(adc->vref); + + return 0; +} + +static int imx93_adc_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct imx93_adc *adc = iio_priv(indio_dev); + int ret; + + ret = regulator_enable(adc->vref); + if (ret) { + dev_err(dev, + "Can't enable adc reference top voltage, err = %d\n", + ret); + return ret; + } + + ret = clk_prepare_enable(adc->ipg_clk); + if (ret) { + dev_err(dev, "Could not prepare or enable clock.\n"); + goto err_disable_reg; + } + + imx93_adc_power_up(adc); + + return 0; + +err_disable_reg: + regulator_disable(adc->vref); + + return ret; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(imx93_adc_pm_ops, + imx93_adc_runtime_suspend, + imx93_adc_runtime_resume, NULL); + +static const struct of_device_id imx93_adc_match[] = { + { .compatible = "nxp,imx93-adc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx93_adc_match); + +static struct platform_driver imx93_adc_driver = { + .probe = imx93_adc_probe, + .remove = imx93_adc_remove, + .driver = { + .name = IMX93_ADC_DRIVER_NAME, + .of_match_table = imx93_adc_match, + .pm = pm_ptr(&imx93_adc_pm_ops), + }, +}; + +module_platform_driver(imx93_adc_driver); + +MODULE_DESCRIPTION("NXP i.MX93 ADC driver"); +MODULE_AUTHOR("Haibo Chen "); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/max11410.c b/drivers/iio/adc/max11410.c index fdc9f03135b5..b74b689ee7de 100644 --- a/drivers/iio/adc/max11410.c +++ b/drivers/iio/adc/max11410.c @@ -4,7 +4,6 @@ * * Copyright 2022 Analog Devices Inc. */ -#include #include #include #include @@ -16,6 +15,8 @@ #include #include +#include + #include #include #include diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 821fee60a765..e90c299c913a 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -543,6 +543,8 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_DEFAULT) [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0, SCALE_HW_CALIB_XOTHERM) + [ADC5_BAT_ID_100K_PU] = ADC5_CHAN_TEMP("bat_id", 0, + SCALE_HW_CALIB_DEFAULT) [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0, SCALE_HW_CALIB_THERM_100K_PULLUP) [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0, @@ -894,10 +896,8 @@ static int adc5_probe(struct platform_device *pdev) mutex_init(&adc->lock); ret = adc5_get_fw_data(adc); - if (ret) { - dev_err(dev, "adc get dt data failed\n"); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "adc get dt data failed\n"); irq_eoc = platform_get_irq(pdev, 0); if (irq_eoc < 0) { diff --git a/drivers/iio/adc/stm32-dfsdm-core.c b/drivers/iio/adc/stm32-dfsdm-core.c index a3d4de6ba4c2..0362df285a57 100644 --- a/drivers/iio/adc/stm32-dfsdm-core.c +++ b/drivers/iio/adc/stm32-dfsdm-core.c @@ -6,6 +6,7 @@ * Author(s): Arnaud Pouliquen for STMicroelectronics. */ +#include #include #include #include @@ -19,7 +20,15 @@ #include "stm32-dfsdm.h" +/** + * struct stm32_dfsdm_dev_data - DFSDM compatible configuration data + * @ipid: DFSDM identification number. Used only if hardware provides identification registers + * @num_filters: DFSDM number of filters. Unused if identification registers are available + * @num_channels: DFSDM number of channels. Unused if identification registers are available + * @regmap_cfg: SAI register map configuration pointer + */ struct stm32_dfsdm_dev_data { + u32 ipid; unsigned int num_filters; unsigned int num_channels; const struct regmap_config *regmap_cfg; @@ -27,8 +36,6 @@ struct stm32_dfsdm_dev_data { #define STM32H7_DFSDM_NUM_FILTERS 4 #define STM32H7_DFSDM_NUM_CHANNELS 8 -#define STM32MP1_DFSDM_NUM_FILTERS 6 -#define STM32MP1_DFSDM_NUM_CHANNELS 8 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg) { @@ -75,8 +82,7 @@ static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = { }; static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = { - .num_filters = STM32MP1_DFSDM_NUM_FILTERS, - .num_channels = STM32MP1_DFSDM_NUM_CHANNELS, + .ipid = STM32MP15_IPIDR_NUMBER, .regmap_cfg = &stm32mp1_dfsdm_regmap_cfg, }; @@ -295,6 +301,65 @@ static const struct of_device_id stm32_dfsdm_of_match[] = { }; MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match); +static int stm32_dfsdm_probe_identification(struct platform_device *pdev, + struct dfsdm_priv *priv, + const struct stm32_dfsdm_dev_data *dev_data) +{ + struct device_node *np = pdev->dev.of_node; + struct device_node *child; + struct stm32_dfsdm *dfsdm = &priv->dfsdm; + const char *compat; + int ret, count = 0; + u32 id, val; + + if (!dev_data->ipid) { + dfsdm->num_fls = dev_data->num_filters; + dfsdm->num_chs = dev_data->num_channels; + return 0; + } + + ret = regmap_read(dfsdm->regmap, DFSDM_IPIDR, &id); + if (ret) + return ret; + + if (id != dev_data->ipid) { + dev_err(&pdev->dev, "Unexpected IP version: 0x%x", id); + return -EINVAL; + } + + for_each_child_of_node(np, child) { + ret = of_property_read_string(child, "compatible", &compat); + if (ret) + continue; + /* Count only child nodes with dfsdm compatible */ + if (strstr(compat, "dfsdm")) + count++; + } + + ret = regmap_read(dfsdm->regmap, DFSDM_HWCFGR, &val); + if (ret) + return ret; + + dfsdm->num_fls = FIELD_GET(DFSDM_HWCFGR_NBF_MASK, val); + dfsdm->num_chs = FIELD_GET(DFSDM_HWCFGR_NBT_MASK, val); + + if (count > dfsdm->num_fls) { + dev_err(&pdev->dev, "Unexpected child number: %d", count); + return -EINVAL; + } + + ret = regmap_read(dfsdm->regmap, DFSDM_VERR, &val); + if (ret) + return ret; + + dev_dbg(&pdev->dev, "DFSDM version: %lu.%lu. %d channels/%d filters\n", + FIELD_GET(DFSDM_VERR_MAJREV_MASK, val), + FIELD_GET(DFSDM_VERR_MINREV_MASK, val), + dfsdm->num_chs, dfsdm->num_fls); + + return 0; +} + static int stm32_dfsdm_probe(struct platform_device *pdev) { struct dfsdm_priv *priv; @@ -311,18 +376,6 @@ static int stm32_dfsdm_probe(struct platform_device *pdev) dev_data = of_device_get_match_data(&pdev->dev); dfsdm = &priv->dfsdm; - dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters, - sizeof(*dfsdm->fl_list), GFP_KERNEL); - if (!dfsdm->fl_list) - return -ENOMEM; - - dfsdm->num_fls = dev_data->num_filters; - dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels, - sizeof(*dfsdm->ch_list), - GFP_KERNEL); - if (!dfsdm->ch_list) - return -ENOMEM; - dfsdm->num_chs = dev_data->num_channels; ret = stm32_dfsdm_parse_of(pdev, priv); if (ret < 0) @@ -338,6 +391,20 @@ static int stm32_dfsdm_probe(struct platform_device *pdev) return ret; } + ret = stm32_dfsdm_probe_identification(pdev, priv, dev_data); + if (ret < 0) + return ret; + + dfsdm->fl_list = devm_kcalloc(&pdev->dev, dfsdm->num_fls, + sizeof(*dfsdm->fl_list), GFP_KERNEL); + if (!dfsdm->fl_list) + return -ENOMEM; + + dfsdm->ch_list = devm_kcalloc(&pdev->dev, dfsdm->num_chs, + sizeof(*dfsdm->ch_list), GFP_KERNEL); + if (!dfsdm->ch_list) + return -ENOMEM; + platform_set_drvdata(pdev, dfsdm); ret = stm32_dfsdm_clk_prepare_enable(dfsdm); diff --git a/drivers/iio/adc/stm32-dfsdm.h b/drivers/iio/adc/stm32-dfsdm.h index 4afc1f528b78..570a1552aec4 100644 --- a/drivers/iio/adc/stm32-dfsdm.h +++ b/drivers/iio/adc/stm32-dfsdm.h @@ -13,25 +13,29 @@ /* * STM32 DFSDM - global register map - * ________________________________________________________ - * | Offset | Registers block | - * -------------------------------------------------------- - * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS | - * -------------------------------------------------------- - * | 0x020 | CHANNEL 1 | - * -------------------------------------------------------- - * | ... | ..... | - * -------------------------------------------------------- - * | 0x0E0 | CHANNEL 7 | - * -------------------------------------------------------- - * | 0x100 | FILTER 0 + COMMON FILTER FIELDs | - * -------------------------------------------------------- - * | 0x200 | FILTER 1 | - * -------------------------------------------------------- - * | 0x300 | FILTER 2 | - * -------------------------------------------------------- - * | 0x400 | FILTER 3 | - * -------------------------------------------------------- + * __________________________________________________________ + * | Offset | Registers block | + * ---------------------------------------------------------- + * | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS | + * ---------------------------------------------------------- + * | 0x020 | CHANNEL 1 | + * ---------------------------------------------------------- + * | ... | ..... | + * ---------------------------------------------------------- + * | 0x20 x n | CHANNEL n | + * ---------------------------------------------------------- + * | 0x100 | FILTER 0 + COMMON FILTER FIELDs | + * ---------------------------------------------------------- + * | 0x200 | FILTER 1 | + * ---------------------------------------------------------- + * | | ..... | + * ---------------------------------------------------------- + * | 0x100 x m | FILTER m | + * ---------------------------------------------------------- + * | | ..... | + * ---------------------------------------------------------- + * | 0x7F0-7FC | Identification registers | + * ---------------------------------------------------------- */ /* @@ -231,6 +235,24 @@ #define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8) #define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v) +/* + * Identification register definitions + */ +#define DFSDM_HWCFGR 0x7F0 +#define DFSDM_VERR 0x7F4 +#define DFSDM_IPIDR 0x7F8 +#define DFSDM_SIDR 0x7FC + +/* HWCFGR: Hardware configuration register */ +#define DFSDM_HWCFGR_NBT_MASK GENMASK(7, 0) +#define DFSDM_HWCFGR_NBF_MASK GENMASK(15, 8) + +/* VERR: Version register */ +#define DFSDM_VERR_MINREV_MASK GENMASK(3, 0) +#define DFSDM_VERR_MAJREV_MASK GENMASK(7, 4) + +#define STM32MP15_IPIDR_NUMBER 0x00110031 + /* DFSDM filter order */ enum stm32_dfsdm_sinc_order { DFSDM_FASTSINC_ORDER, /* FastSinc filter type */ diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c index b3d5b9b7255b..a456ea78462f 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -9,14 +9,13 @@ * https://www.ti.com/lit/ds/symlink/adc124s021.pdf */ -#include #include -#include -#include -#include #include +#include +#include #include #include +#include struct adc128_configuration { const struct iio_chan_spec *channels; @@ -139,16 +138,11 @@ static void adc128_disable_regulator(void *reg) static int adc128_probe(struct spi_device *spi) { + const struct adc128_configuration *config; struct iio_dev *indio_dev; - unsigned int config; struct adc128 *adc; int ret; - if (dev_fwnode(&spi->dev)) - config = (unsigned long) device_get_match_data(&spi->dev); - else - config = spi_get_device_id(spi)->driver_data; - indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); if (!indio_dev) return -ENOMEM; @@ -160,8 +154,10 @@ static int adc128_probe(struct spi_device *spi) indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->info = &adc128_info; - indio_dev->channels = adc128_config[config].channels; - indio_dev->num_channels = adc128_config[config].num_channels; + config = spi_get_device_match_data(spi); + + indio_dev->channels = config->channels; + indio_dev->num_channels = config->num_channels; adc->reg = devm_regulator_get(&spi->dev, "vref"); if (IS_ERR(adc->reg)) @@ -181,42 +177,40 @@ static int adc128_probe(struct spi_device *spi) } static const struct of_device_id adc128_of_match[] = { - { .compatible = "ti,adc128s052", .data = (void*)0L, }, - { .compatible = "ti,adc122s021", .data = (void*)1L, }, - { .compatible = "ti,adc122s051", .data = (void*)1L, }, - { .compatible = "ti,adc122s101", .data = (void*)1L, }, - { .compatible = "ti,adc124s021", .data = (void*)2L, }, - { .compatible = "ti,adc124s051", .data = (void*)2L, }, - { .compatible = "ti,adc124s101", .data = (void*)2L, }, + { .compatible = "ti,adc128s052", .data = &adc128_config[0] }, + { .compatible = "ti,adc122s021", .data = &adc128_config[1] }, + { .compatible = "ti,adc122s051", .data = &adc128_config[1] }, + { .compatible = "ti,adc122s101", .data = &adc128_config[1] }, + { .compatible = "ti,adc124s021", .data = &adc128_config[2] }, + { .compatible = "ti,adc124s051", .data = &adc128_config[2] }, + { .compatible = "ti,adc124s101", .data = &adc128_config[2] }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, adc128_of_match); static const struct spi_device_id adc128_id[] = { - { "adc128s052", 0 }, /* index into adc128_config */ - { "adc122s021", 1 }, - { "adc122s051", 1 }, - { "adc122s101", 1 }, - { "adc124s021", 2 }, - { "adc124s051", 2 }, - { "adc124s101", 2 }, + { "adc128s052", (kernel_ulong_t)&adc128_config[0] }, + { "adc122s021", (kernel_ulong_t)&adc128_config[1] }, + { "adc122s051", (kernel_ulong_t)&adc128_config[1] }, + { "adc122s101", (kernel_ulong_t)&adc128_config[1] }, + { "adc124s021", (kernel_ulong_t)&adc128_config[2] }, + { "adc124s051", (kernel_ulong_t)&adc128_config[2] }, + { "adc124s101", (kernel_ulong_t)&adc128_config[2] }, { } }; MODULE_DEVICE_TABLE(spi, adc128_id); -#ifdef CONFIG_ACPI static const struct acpi_device_id adc128_acpi_match[] = { - { "AANT1280", 2 }, /* ADC124S021 compatible ACPI ID */ + { "AANT1280", (kernel_ulong_t)&adc128_config[2] }, { } }; MODULE_DEVICE_TABLE(acpi, adc128_acpi_match); -#endif static struct spi_driver adc128_driver = { .driver = { .name = "adc128s052", .of_match_table = adc128_of_match, - .acpi_match_table = ACPI_PTR(adc128_acpi_match), + .acpi_match_table = adc128_acpi_match, }, .probe = adc128_probe, .id_table = adc128_id, diff --git a/drivers/iio/adc/ti-ads7924.c b/drivers/iio/adc/ti-ads7924.c new file mode 100644 index 000000000000..b02abb026966 --- /dev/null +++ b/drivers/iio/adc/ti-ads7924.c @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IIO driver for Texas Instruments ADS7924 ADC, 12-bit, 4-Channels, I2C + * + * Author: Hugo Villeneuve + * Copyright 2022 DimOnOff + * + * based on iio/adc/ti-ads1015.c + * Copyright (c) 2016, Intel Corporation. + * + * Datasheet: https://www.ti.com/lit/gpn/ads7924 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define ADS7924_CHANNELS 4 +#define ADS7924_BITS 12 +#define ADS7924_DATA_SHIFT 4 + +/* Registers. */ +#define ADS7924_MODECNTRL_REG 0x00 +#define ADS7924_INTCNTRL_REG 0x01 +#define ADS7924_DATA0_U_REG 0x02 +#define ADS7924_DATA0_L_REG 0x03 +#define ADS7924_DATA1_U_REG 0x04 +#define ADS7924_DATA1_L_REG 0x05 +#define ADS7924_DATA2_U_REG 0x06 +#define ADS7924_DATA2_L_REG 0x07 +#define ADS7924_DATA3_U_REG 0x08 +#define ADS7924_DATA3_L_REG 0x09 +#define ADS7924_ULR0_REG 0x0A +#define ADS7924_LLR0_REG 0x0B +#define ADS7924_ULR1_REG 0x0C +#define ADS7924_LLR1_REG 0x0D +#define ADS7924_ULR2_REG 0x0E +#define ADS7924_LLR2_REG 0x0F +#define ADS7924_ULR3_REG 0x10 +#define ADS7924_LLR3_REG 0x11 +#define ADS7924_INTCONFIG_REG 0x12 +#define ADS7924_SLPCONFIG_REG 0x13 +#define ADS7924_ACQCONFIG_REG 0x14 +#define ADS7924_PWRCONFIG_REG 0x15 +#define ADS7924_RESET_REG 0x16 + +/* + * Register address INC bit: when set to '1', the register address is + * automatically incremented after every register read which allows convenient + * reading of multiple registers. Set INC to '0' when reading a single register. + */ +#define ADS7924_AUTO_INCREMENT_BIT BIT(7) + +#define ADS7924_MODECNTRL_MODE_MASK GENMASK(7, 2) + +#define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0) + +#define ADS7924_CFG_INTPOL_BIT 1 +#define ADS7924_CFG_INTTRIG_BIT 0 + +#define ADS7924_CFG_INTPOL_MASK BIT(ADS7924_CFG_INTPOL_BIT) +#define ADS7924_CFG_INTTRIG_MASK BIT(ADS7924_CFG_INTTRIG_BIT) + +/* Interrupt pin polarity */ +#define ADS7924_CFG_INTPOL_LOW 0 +#define ADS7924_CFG_INTPOL_HIGH 1 + +/* Interrupt pin signaling */ +#define ADS7924_CFG_INTTRIG_LEVEL 0 +#define ADS7924_CFG_INTTRIG_EDGE 1 + +/* Mode control values */ +#define ADS7924_MODECNTRL_IDLE 0x00 +#define ADS7924_MODECNTRL_AWAKE 0x20 +#define ADS7924_MODECNTRL_MANUAL_SINGLE 0x30 +#define ADS7924_MODECNTRL_MANUAL_SCAN 0x32 +#define ADS7924_MODECNTRL_AUTO_SINGLE 0x31 +#define ADS7924_MODECNTRL_AUTO_SCAN 0x33 +#define ADS7924_MODECNTRL_AUTO_SINGLE_SLEEP 0x39 +#define ADS7924_MODECNTRL_AUTO_SCAN_SLEEP 0x3B +#define ADS7924_MODECNTRL_AUTO_BURST_SLEEP 0x3F + +#define ADS7924_ACQTIME_MASK GENMASK(4, 0) + +#define ADS7924_PWRUPTIME_MASK GENMASK(4, 0) + +/* + * The power-up time is allowed to elapse whenever the device has been shutdown + * in idle mode. Power-up time can allow external circuits, such as an + * operational amplifier, between the MUXOUT and ADCIN pins to turn on. + * The nominal time programmed by the PUTIME[4:0] register bits is given by: + * t PU = PWRUPTIME[4:0] × 2 μs + * If a power-up time is not required, set the bits to '0' to effectively bypass. + */ +#define ADS7924_PWRUPTIME_US 0 /* Bypass (0us). */ + +/* + * Acquisition Time according to ACQTIME[4:0] register bits. + * The Acquisition Time is given by: + * t ACQ = (ACQTIME[4:0] × 2 μs) + 6 μs + * Using default value of 0 for ACQTIME[4:0] results in a minimum acquisition + * time of 6us. + */ +#define ADS7924_ACQTIME_US 6 + +/* The conversion time is always 4μs and cannot be programmed by the user. */ +#define ADS7924_CONVTIME_US 4 + +#define ADS7924_TOTAL_CONVTIME_US (ADS7924_PWRUPTIME_US + ADS7924_ACQTIME_US + \ + ADS7924_CONVTIME_US) + +#define ADS7924_V_CHAN(_chan, _addr) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = _chan, \ + .address = _addr, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .datasheet_name = "AIN"#_chan, \ +} + +struct ads7924_data { + struct device *dev; + struct regmap *regmap; + struct regulator *vref_reg; + + /* GPIO descriptor for device hard-reset pin. */ + struct gpio_desc *reset_gpio; + + /* + * Protects ADC ops, e.g: concurrent sysfs/buffered + * data reads, configuration updates + */ + struct mutex lock; + + /* + * Set to true when the ADC is switched to the continuous-conversion + * mode and exits from a power-down state. This flag is used to avoid + * getting the stale result from the conversion register. + */ + bool conv_invalid; +}; + +static bool ads7924_is_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case ADS7924_MODECNTRL_REG: + case ADS7924_INTCNTRL_REG: + case ADS7924_ULR0_REG: + case ADS7924_LLR0_REG: + case ADS7924_ULR1_REG: + case ADS7924_LLR1_REG: + case ADS7924_ULR2_REG: + case ADS7924_LLR2_REG: + case ADS7924_ULR3_REG: + case ADS7924_LLR3_REG: + case ADS7924_INTCONFIG_REG: + case ADS7924_SLPCONFIG_REG: + case ADS7924_ACQCONFIG_REG: + case ADS7924_PWRCONFIG_REG: + case ADS7924_RESET_REG: + return true; + default: + return false; + } +} + +static const struct regmap_config ads7924_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = ADS7924_RESET_REG, + .writeable_reg = ads7924_is_writeable_reg, +}; + +static const struct iio_chan_spec ads7924_channels[] = { + ADS7924_V_CHAN(0, ADS7924_DATA0_U_REG), + ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG), + ADS7924_V_CHAN(2, ADS7924_DATA2_U_REG), + ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG), +}; + +static int ads7924_get_adc_result(struct ads7924_data *data, + struct iio_chan_spec const *chan, int *val) +{ + int ret; + __be16 be_val; + + if (chan->channel < 0 || chan->channel >= ADS7924_CHANNELS) + return -EINVAL; + + if (data->conv_invalid) { + int conv_time; + + conv_time = ADS7924_TOTAL_CONVTIME_US; + /* Allow 10% for internal clock inaccuracy. */ + conv_time += conv_time / 10; + usleep_range(conv_time, conv_time + 1); + data->conv_invalid = false; + } + + ret = regmap_raw_read(data->regmap, ADS7924_AUTO_INCREMENT_BIT | + chan->address, &be_val, sizeof(be_val)); + if (ret) + return ret; + + *val = be16_to_cpu(be_val) >> ADS7924_DATA_SHIFT; + + return 0; +} + +static int ads7924_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + int ret, vref_uv; + struct ads7924_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + mutex_lock(&data->lock); + ret = ads7924_get_adc_result(data, chan, val); + mutex_unlock(&data->lock); + if (ret < 0) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + vref_uv = regulator_get_voltage(data->vref_reg); + if (vref_uv < 0) + return vref_uv; + + *val = vref_uv / 1000; /* Convert reg voltage to mV */ + *val2 = ADS7924_BITS; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info ads7924_info = { + .read_raw = ads7924_read_raw, +}; + +static int ads7924_get_channels_config(struct i2c_client *client, + struct iio_dev *indio_dev) +{ + struct ads7924_data *priv = iio_priv(indio_dev); + struct device *dev = priv->dev; + struct fwnode_handle *node; + int num_channels = 0; + + device_for_each_child_node(dev, node) { + u32 pval; + unsigned int channel; + + if (fwnode_property_read_u32(node, "reg", &pval)) { + dev_err(dev, "invalid reg on %pfw\n", node); + continue; + } + + channel = pval; + if (channel >= ADS7924_CHANNELS) { + dev_err(dev, "invalid channel index %d on %pfw\n", + channel, node); + continue; + } + + num_channels++; + } + + if (!num_channels) + return -EINVAL; + + return 0; +} + +static int ads7924_set_conv_mode(struct ads7924_data *data, int mode) +{ + int ret; + unsigned int mode_field; + struct device *dev = data->dev; + + /* + * When switching between modes, be sure to first select the Awake mode + * and then switch to the desired mode. This procedure ensures the + * internal control logic is properly synchronized. + */ + if (mode != ADS7924_MODECNTRL_IDLE) { + mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, + ADS7924_MODECNTRL_AWAKE); + + ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG, + ADS7924_MODECNTRL_MODE_MASK, + mode_field); + if (ret) { + dev_err(dev, "failed to set awake mode (%pe)\n", + ERR_PTR(ret)); + return ret; + } + } + + mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, mode); + + ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG, + ADS7924_MODECNTRL_MODE_MASK, mode_field); + if (ret) + dev_err(dev, "failed to set mode %d (%pe)\n", mode, + ERR_PTR(ret)); + + return ret; +} + +static int ads7924_reset(struct iio_dev *indio_dev) +{ + struct ads7924_data *data = iio_priv(indio_dev); + + if (data->reset_gpio) { + gpiod_set_value(data->reset_gpio, 1); /* Assert. */ + /* Educated guess: assert time not specified in datasheet... */ + mdelay(100); + gpiod_set_value(data->reset_gpio, 0); /* Deassert. */ + return 0; + } + + /* + * A write of 10101010 to this register will generate a + * software reset of the ADS7924. + */ + return regmap_write(data->regmap, ADS7924_RESET_REG, 0b10101010); +}; + +static void ads7924_reg_disable(void *data) +{ + regulator_disable(data); +} + +static void ads7924_set_idle_mode(void *data) +{ + ads7924_set_conv_mode(data, ADS7924_MODECNTRL_IDLE); +} + +static int ads7924_probe(struct i2c_client *client) +{ + struct iio_dev *indio_dev; + struct ads7924_data *data; + struct device *dev = &client->dev; + int ret; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate iio device\n"); + + data = iio_priv(indio_dev); + + data->dev = dev; + + /* Initialize the reset GPIO as output with an initial value of 0. */ + data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(data->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(data->reset_gpio), + "failed to get request reset GPIO\n"); + + mutex_init(&data->lock); + + indio_dev->name = "ads7924"; + indio_dev->modes = INDIO_DIRECT_MODE; + + indio_dev->channels = ads7924_channels; + indio_dev->num_channels = ARRAY_SIZE(ads7924_channels); + indio_dev->info = &ads7924_info; + + ret = ads7924_get_channels_config(client, indio_dev); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to get channels configuration\n"); + + data->regmap = devm_regmap_init_i2c(client, &ads7924_regmap_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), + "failed to init regmap\n"); + + data->vref_reg = devm_regulator_get(dev, "vref"); + if (IS_ERR(data->vref_reg)) + return dev_err_probe(dev, PTR_ERR(data->vref_reg), + "failed to get vref regulator\n"); + + ret = regulator_enable(data->vref_reg); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable regulator\n"); + + ret = devm_add_action_or_reset(dev, ads7924_reg_disable, data->vref_reg); + if (ret) + return dev_err_probe(dev, ret, + "failed to add regulator disable action\n"); + + ret = ads7924_reset(indio_dev); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to reset device\n"); + + ret = ads7924_set_conv_mode(data, ADS7924_MODECNTRL_AUTO_SCAN); + if (ret) + return dev_err_probe(dev, ret, + "failed to set conversion mode\n"); + + ret = devm_add_action_or_reset(dev, ads7924_set_idle_mode, data); + if (ret) + return dev_err_probe(dev, ret, + "failed to add idle mode action\n"); + + /* Use minimum signal acquire time. */ + ret = regmap_update_bits(data->regmap, ADS7924_ACQCONFIG_REG, + ADS7924_ACQTIME_MASK, + FIELD_PREP(ADS7924_ACQTIME_MASK, 0)); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to configure signal acquire time\n"); + + /* Disable power-up time. */ + ret = regmap_update_bits(data->regmap, ADS7924_PWRCONFIG_REG, + ADS7924_PWRUPTIME_MASK, + FIELD_PREP(ADS7924_PWRUPTIME_MASK, 0)); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to configure power-up time\n"); + + data->conv_invalid = true; + + ret = devm_iio_device_register(dev, indio_dev); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to register IIO device\n"); + + return 0; +} + +static const struct i2c_device_id ads7924_id[] = { + { "ads7924", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, ads7924_id); + +static const struct of_device_id ads7924_of_match[] = { + { .compatible = "ti,ads7924", }, + {} +}; +MODULE_DEVICE_TABLE(of, ads7924_of_match); + +static struct i2c_driver ads7924_driver = { + .driver = { + .name = "ads7924", + .of_match_table = ads7924_of_match, + }, + .probe_new = ads7924_probe, + .id_table = ads7924_id, +}; + +module_i2c_driver(ads7924_driver); + +MODULE_AUTHOR("Hugo Villeneuve "); +MODULE_DESCRIPTION("Texas Instruments ADS7924 ADC I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/ti-lmp92064.c b/drivers/iio/adc/ti-lmp92064.c new file mode 100644 index 000000000000..c30ed824924f --- /dev/null +++ b/drivers/iio/adc/ti-lmp92064.c @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments LMP92064 SPI ADC driver + * + * Copyright (c) 2022 Leonard Göhrs , Pengutronix + * + * Based on linux/drivers/iio/adc/ti-tsc2046.c + * Copyright (c) 2021 Oleksij Rempel , Pengutronix + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TI_LMP92064_REG_CONFIG_A 0x0000 +#define TI_LMP92064_REG_CONFIG_B 0x0001 +#define TI_LMP92064_REG_CHIP_REV 0x0006 + +#define TI_LMP92064_REG_MFR_ID1 0x000C +#define TI_LMP92064_REG_MFR_ID2 0x000D + +#define TI_LMP92064_REG_REG_UPDATE 0x000F +#define TI_LMP92064_REG_CONFIG_REG 0x0100 +#define TI_LMP92064_REG_STATUS 0x0103 + +#define TI_LMP92064_REG_DATA_VOUT_LSB 0x0200 +#define TI_LMP92064_REG_DATA_VOUT_MSB 0x0201 +#define TI_LMP92064_REG_DATA_COUT_LSB 0x0202 +#define TI_LMP92064_REG_DATA_COUT_MSB 0x0203 + +#define TI_LMP92064_VAL_CONFIG_A 0x99 +#define TI_LMP92064_VAL_CONFIG_B 0x00 +#define TI_LMP92064_VAL_STATUS_OK 0x01 + +/* + * Channel number definitions for the two channels of the device + * - IN Current (INC) + * - IN Voltage (INV) + */ +#define TI_LMP92064_CHAN_INC 0 +#define TI_LMP92064_CHAN_INV 1 + +static const struct regmap_range lmp92064_readable_reg_ranges[] = { + regmap_reg_range(TI_LMP92064_REG_CONFIG_A, TI_LMP92064_REG_CHIP_REV), + regmap_reg_range(TI_LMP92064_REG_MFR_ID1, TI_LMP92064_REG_MFR_ID2), + regmap_reg_range(TI_LMP92064_REG_REG_UPDATE, TI_LMP92064_REG_REG_UPDATE), + regmap_reg_range(TI_LMP92064_REG_CONFIG_REG, TI_LMP92064_REG_CONFIG_REG), + regmap_reg_range(TI_LMP92064_REG_STATUS, TI_LMP92064_REG_STATUS), + regmap_reg_range(TI_LMP92064_REG_DATA_VOUT_LSB, TI_LMP92064_REG_DATA_COUT_MSB), +}; + +static const struct regmap_access_table lmp92064_readable_regs = { + .yes_ranges = lmp92064_readable_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(lmp92064_readable_reg_ranges), +}; + +static const struct regmap_range lmp92064_writable_reg_ranges[] = { + regmap_reg_range(TI_LMP92064_REG_CONFIG_A, TI_LMP92064_REG_CONFIG_B), + regmap_reg_range(TI_LMP92064_REG_REG_UPDATE, TI_LMP92064_REG_REG_UPDATE), + regmap_reg_range(TI_LMP92064_REG_CONFIG_REG, TI_LMP92064_REG_CONFIG_REG), +}; + +static const struct regmap_access_table lmp92064_writable_regs = { + .yes_ranges = lmp92064_writable_reg_ranges, + .n_yes_ranges = ARRAY_SIZE(lmp92064_writable_reg_ranges), +}; + +static const struct regmap_config lmp92064_spi_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = TI_LMP92064_REG_DATA_COUT_MSB, + .rd_table = &lmp92064_readable_regs, + .wr_table = &lmp92064_writable_regs, +}; + +struct lmp92064_adc_priv { + int shunt_resistor_uohm; + struct spi_device *spi; + struct regmap *regmap; +}; + +static const struct iio_chan_spec lmp92064_adc_channels[] = { + { + .type = IIO_CURRENT, + .address = TI_LMP92064_CHAN_INC, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .datasheet_name = "INC", + }, + { + .type = IIO_VOLTAGE, + .address = TI_LMP92064_CHAN_INV, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .datasheet_name = "INV", + }, +}; + +static int lmp92064_read_meas(struct lmp92064_adc_priv *priv, u16 *res) +{ + __be16 raw[2]; + int ret; + + /* + * The ADC only latches in new samples if all DATA registers are read + * in descending sequential order. + * The ADC auto-decrements the register index with each clocked byte. + * Read both channels in single SPI transfer by selecting the highest + * register using the command below and clocking out all four data + * bytes. + */ + + ret = regmap_bulk_read(priv->regmap, TI_LMP92064_REG_DATA_COUT_MSB, + &raw, sizeof(raw)); + + if (ret) { + dev_err(&priv->spi->dev, "regmap_bulk_read failed: %pe\n", + ERR_PTR(ret)); + return ret; + } + + res[0] = be16_to_cpu(raw[0]); + res[1] = be16_to_cpu(raw[1]); + + return 0; +} + +static int lmp92064_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct lmp92064_adc_priv *priv = iio_priv(indio_dev); + u16 raw[2]; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = lmp92064_read_meas(priv, raw); + if (ret < 0) + return ret; + + *val = (chan->address == TI_LMP92064_CHAN_INC) ? raw[0] : raw[1]; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + if (chan->address == TI_LMP92064_CHAN_INC) { + /* + * processed (mA) = raw * current_lsb (mA) + * current_lsb (mA) = shunt_voltage_lsb (nV) / shunt_resistor (uOhm) + * shunt_voltage_lsb (nV) = 81920000 / 4096 = 20000 + */ + *val = 20000; + *val2 = priv->shunt_resistor_uohm; + } else { + /* + * processed (mV) = raw * voltage_lsb (mV) + * voltage_lsb (mV) = 2048 / 4096 + */ + *val = 2048; + *val2 = 4096; + } + return IIO_VAL_FRACTIONAL; + default: + return -EINVAL; + } +} + +static int lmp92064_reset(struct lmp92064_adc_priv *priv, + struct gpio_desc *gpio_reset) +{ + unsigned int status; + int ret, i; + + if (gpio_reset) { + /* + * Perform a hard reset if gpio_reset is available. + * The datasheet specifies a very low 3.5ns reset pulse duration and does not + * specify how long to wait after a reset to access the device. + * Use more conservative pulse lengths to allow analog RC filtering of the + * reset line at the board level (as recommended in the datasheet). + */ + gpiod_set_value_cansleep(gpio_reset, 1); + usleep_range(1, 10); + gpiod_set_value_cansleep(gpio_reset, 0); + usleep_range(500, 750); + } else { + /* + * Perform a soft-reset if not. + * Also write default values to the config registers that are not + * affected by soft reset. + */ + ret = regmap_write(priv->regmap, TI_LMP92064_REG_CONFIG_A, + TI_LMP92064_VAL_CONFIG_A); + if (ret < 0) + return ret; + + ret = regmap_write(priv->regmap, TI_LMP92064_REG_CONFIG_B, + TI_LMP92064_VAL_CONFIG_B); + if (ret < 0) + return ret; + } + + /* + * Wait for the device to signal readiness to prevent reading bogus data + * and make sure device is actually connected. + * The datasheet does not specify how long this takes but usually it is + * not more than 3-4 iterations of this loop. + */ + for (i = 0; i < 10; i++) { + ret = regmap_read(priv->regmap, TI_LMP92064_REG_STATUS, &status); + if (ret < 0) + return ret; + + if (status == TI_LMP92064_VAL_STATUS_OK) + return 0; + + usleep_range(1000, 2000); + } + + /* + * No (correct) response received. + * Device is mostly likely not connected to the bus. + */ + return -ENXIO; +} + +static const struct iio_info lmp92064_adc_info = { + .read_raw = lmp92064_read_raw, +}; + +static int lmp92064_adc_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct lmp92064_adc_priv *priv; + struct gpio_desc *gpio_reset; + struct iio_dev *indio_dev; + u32 shunt_resistor_uohm; + struct regmap *regmap; + int ret; + + ret = spi_setup(spi); + if (ret < 0) + return dev_err_probe(dev, ret, "Error in SPI setup\n"); + + regmap = devm_regmap_init_spi(spi, &lmp92064_spi_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to set up SPI regmap\n"); + + indio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); + if (!indio_dev) + return -ENOMEM; + + priv = iio_priv(indio_dev); + + priv->spi = spi; + priv->regmap = regmap; + + ret = device_property_read_u32(dev, "shunt-resistor-micro-ohms", + &shunt_resistor_uohm); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get shunt-resistor value\n"); + + /* + * The shunt resistance is passed to userspace as the denominator of an iio + * fraction. Make sure it is in range for that. + */ + if (shunt_resistor_uohm == 0 || shunt_resistor_uohm > INT_MAX) { + dev_err(dev, "Shunt resistance is out of range\n"); + return -EINVAL; + } + + priv->shunt_resistor_uohm = shunt_resistor_uohm; + + ret = devm_regulator_get_enable(dev, "vdd"); + if (ret) + return ret; + + ret = devm_regulator_get_enable(dev, "vdig"); + if (ret) + return ret; + + gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(gpio_reset)) + return dev_err_probe(dev, PTR_ERR(gpio_reset), + "Failed to get GPIO reset pin\n"); + + ret = lmp92064_reset(priv, gpio_reset); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to reset device\n"); + + indio_dev->name = "lmp92064"; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = lmp92064_adc_channels; + indio_dev->num_channels = ARRAY_SIZE(lmp92064_adc_channels); + indio_dev->info = &lmp92064_adc_info; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct spi_device_id lmp92064_id_table[] = { + { "lmp92064" }, + {} +}; +MODULE_DEVICE_TABLE(spi, lmp92064_id_table); + +static const struct of_device_id lmp92064_of_table[] = { + { .compatible = "ti,lmp92064" }, + {} +}; +MODULE_DEVICE_TABLE(of, lmp92064_of_table); + +static struct spi_driver lmp92064_adc_driver = { + .driver = { + .name = "lmp92064", + .of_match_table = lmp92064_of_table, + }, + .probe = lmp92064_adc_probe, + .id_table = lmp92064_id_table, +}; +module_spi_driver(lmp92064_adc_driver); + +MODULE_AUTHOR("Leonard Göhrs "); +MODULE_DESCRIPTION("TI LMP92064 ADC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/xilinx-ams.c b/drivers/iio/adc/xilinx-ams.c index a507d2e17079..34cf336b3490 100644 --- a/drivers/iio/adc/xilinx-ams.c +++ b/drivers/iio/adc/xilinx-ams.c @@ -1220,8 +1220,7 @@ static int ams_init_module(struct iio_dev *indio_dev, int num_channels = 0; int ret; - if (fwnode_property_match_string(fwnode, "compatible", - "xlnx,zynqmp-ams-ps") == 0) { + if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) { ams->ps_base = fwnode_iomap(fwnode, 0); if (!ams->ps_base) return -ENXIO; @@ -1232,8 +1231,7 @@ static int ams_init_module(struct iio_dev *indio_dev, /* add PS channels to iio device channels */ memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels)); num_channels = ARRAY_SIZE(ams_ps_channels); - } else if (fwnode_property_match_string(fwnode, "compatible", - "xlnx,zynqmp-ams-pl") == 0) { + } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) { ams->pl_base = fwnode_iomap(fwnode, 0); if (!ams->pl_base) return -ENXIO; @@ -1247,8 +1245,7 @@ static int ams_init_module(struct iio_dev *indio_dev, num_channels += AMS_PL_MAX_FIXED_CHANNEL; num_channels = ams_get_ext_chan(fwnode, channels, num_channels); - } else if (fwnode_property_match_string(fwnode, "compatible", - "xlnx,zynqmp-ams") == 0) { + } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) { /* add AMS channels to iio device channels */ memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels)); num_channels += ARRAY_SIZE(ams_ctrl_channels); diff --git a/drivers/iio/cdc/ad7746.c b/drivers/iio/cdc/ad7746.c index 6f68651ce1d5..a1db5469f2d1 100644 --- a/drivers/iio/cdc/ad7746.c +++ b/drivers/iio/cdc/ad7746.c @@ -285,8 +285,7 @@ static int ad7746_select_channel(struct iio_dev *indio_dev, if (ret < 0) return ret; - if (chip->capdac_set != chan->channel) - chip->capdac_set = chan->channel; + chip->capdac_set = chan->channel; break; case IIO_VOLTAGE: case IIO_TEMP: diff --git a/drivers/iio/chemical/scd30_core.c b/drivers/iio/chemical/scd30_core.c index 682fca39d14d..7be5a45cf71a 100644 --- a/drivers/iio/chemical/scd30_core.c +++ b/drivers/iio/chemical/scd30_core.c @@ -354,7 +354,7 @@ static ssize_t sampling_frequency_available_show(struct device *dev, struct devi ssize_t len = 0; do { - len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09u ", 1000000000 / i); + len += sysfs_emit_at(buf, len, "0.%09u ", 1000000000 / i); /* * Not all values fit PAGE_SIZE buffer hence print every 6th * (each frequency differs by 6s in time domain from the @@ -380,7 +380,7 @@ static ssize_t calibration_auto_enable_show(struct device *dev, struct device_at ret = scd30_command_read(state, CMD_ASC, &val); mutex_unlock(&state->lock); - return ret ?: sprintf(buf, "%d\n", val); + return ret ?: sysfs_emit(buf, "%d\n", val); } static ssize_t calibration_auto_enable_store(struct device *dev, struct device_attribute *attr, @@ -414,7 +414,7 @@ static ssize_t calibration_forced_value_show(struct device *dev, struct device_a ret = scd30_command_read(state, CMD_FRC, &val); mutex_unlock(&state->lock); - return ret ?: sprintf(buf, "%d\n", val); + return ret ?: sysfs_emit(buf, "%d\n", val); } static ssize_t calibration_forced_value_store(struct device *dev, struct device_attribute *attr, @@ -642,10 +642,8 @@ static int scd30_setup_trigger(struct iio_dev *indio_dev) trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, iio_device_id(indio_dev)); - if (!trig) { - dev_err(dev, "failed to allocate trigger\n"); - return -ENOMEM; - } + if (!trig) + return dev_err_probe(dev, -ENOMEM, "failed to allocate trigger\n"); trig->ops = &scd30_trigger_ops; iio_trigger_set_drvdata(trig, indio_dev); @@ -667,9 +665,9 @@ static int scd30_setup_trigger(struct iio_dev *indio_dev) IRQF_NO_AUTOEN, indio_dev->name, indio_dev); if (ret) - dev_err(dev, "failed to request irq\n"); + return dev_err_probe(dev, ret, "failed to request irq\n"); - return ret; + return 0; } int scd30_probe(struct device *dev, int irq, const char *name, void *priv, @@ -717,17 +715,13 @@ int scd30_probe(struct device *dev, int irq, const char *name, void *priv, return ret; ret = scd30_reset(state); - if (ret) { - dev_err(dev, "failed to reset device: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to reset device\n"); if (state->irq > 0) { ret = scd30_setup_trigger(indio_dev); - if (ret) { - dev_err(dev, "failed to setup trigger: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to setup trigger\n"); } ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, scd30_trigger_handler, NULL); @@ -735,23 +729,17 @@ int scd30_probe(struct device *dev, int irq, const char *name, void *priv, return ret; ret = scd30_command_read(state, CMD_FW_VERSION, &val); - if (ret) { - dev_err(dev, "failed to read firmware version: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to read firmware version\n"); dev_info(dev, "firmware version: %d.%d\n", val >> 8, (char)val); ret = scd30_command_write(state, CMD_MEAS_INTERVAL, state->meas_interval); - if (ret) { - dev_err(dev, "failed to set measurement interval: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to set measurement interval\n"); ret = scd30_command_write(state, CMD_START_MEAS, state->pressure_comp); - if (ret) { - dev_err(dev, "failed to start measurement: %d\n", ret); - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "failed to start measurement\n"); ret = devm_add_action_or_reset(dev, scd30_stop_meas, state); if (ret) diff --git a/drivers/iio/common/scmi_sensors/scmi_iio.c b/drivers/iio/common/scmi_sensors/scmi_iio.c index d92f7f651f7b..0c2caf3570db 100644 --- a/drivers/iio/common/scmi_sensors/scmi_iio.c +++ b/drivers/iio/common/scmi_sensors/scmi_iio.c @@ -400,12 +400,12 @@ static ssize_t scmi_iio_get_raw_available(struct iio_dev *iio_dev, rem = do_div(resolution, int_pow(10, abs(exponent)) ); - len = scnprintf(buf, PAGE_SIZE, + len = sysfs_emit(buf, "[%lld %llu.%llu %lld]\n", min_range, resolution, rem, max_range); } else { resolution = resolution * int_pow(10, exponent); - len = scnprintf(buf, PAGE_SIZE, "[%lld %llu %lld]\n", + len = sysfs_emit(buf, "[%lld %llu %lld]\n", min_range, resolution, max_range); } } diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 80521bd28d0f..d3f90cf86143 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -162,10 +162,10 @@ config AD5696_I2C depends on I2C select AD5686 help - Say yes here to build support for Analog Devices AD5311R, AD5338R, - AD5671R, AD5673R, AD5675R, AD5677R, AD5691R, AD5692R, AD5693, AD5693R, - AD5694, AD5694R, AD5695R, AD5696, and AD5696R Digital to Analog - converters. + Say yes here to build support for Analog Devices AD5311R, AD5337, + AD5338R, AD5671R, AD5673R, AD5675R, AD5677R, AD5691R, AD5692R, AD5693, + AD5693R, AD5694, AD5694R, AD5695R, AD5696, and AD5696R Digital to + Analog converters. To compile this driver as a module, choose M here: the module will be called ad5696. @@ -357,6 +357,19 @@ config MAX517 This driver can also be built as a module. If so, the module will be called max517. +config MAX5522 + tristate "Maxim MAX5522 DAC driver" + depends on SPI_MASTER + select REGMAP_SPI + help + Say Y here if you want to build a driver for the Maxim MAX5522. + + MAX5522 is a dual, ultra-low-power, 10-Bit, voltage-output + digital to analog converter (DAC) offering rail-to-rail buffered + voltage outputs. + + If compiled as a module, it will be called max5522. + config MAX5821 tristate "Maxim MAX5821 DAC driver" depends on I2C diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index ec3e42713f00..6c74fea21736 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_LTC2632) += ltc2632.o obj-$(CONFIG_LTC2688) += ltc2688.o obj-$(CONFIG_M62332) += m62332.o obj-$(CONFIG_MAX517) += max517.o +obj-$(CONFIG_MAX5522) += max5522.o obj-$(CONFIG_MAX5821) += max5821.o obj-$(CONFIG_MCP4725) += mcp4725.o obj-$(CONFIG_MCP4922) += mcp4922.o diff --git a/drivers/iio/dac/ad5686.c b/drivers/iio/dac/ad5686.c index 15361d8bbf94..57cc0f0eedc6 100644 --- a/drivers/iio/dac/ad5686.c +++ b/drivers/iio/dac/ad5686.c @@ -258,6 +258,7 @@ static const struct iio_chan_spec name[] = { \ DECLARE_AD5693_CHANNELS(ad5310r_channels, 10, 2); DECLARE_AD5693_CHANNELS(ad5311r_channels, 10, 6); +DECLARE_AD5338_CHANNELS(ad5337r_channels, 8, 8); DECLARE_AD5338_CHANNELS(ad5338r_channels, 10, 6); DECLARE_AD5676_CHANNELS(ad5672_channels, 12, 4); DECLARE_AD5679_CHANNELS(ad5674r_channels, 12, 4); @@ -283,6 +284,12 @@ static const struct ad5686_chip_info ad5686_chip_info_tbl[] = { .num_channels = 1, .regmap_type = AD5693_REGMAP, }, + [ID_AD5337R] = { + .channels = ad5337r_channels, + .int_vref_mv = 2500, + .num_channels = 2, + .regmap_type = AD5686_REGMAP, + }, [ID_AD5338R] = { .channels = ad5338r_channels, .int_vref_mv = 2500, diff --git a/drivers/iio/dac/ad5686.h b/drivers/iio/dac/ad5686.h index b7ade3a6b9b6..760f852911df 100644 --- a/drivers/iio/dac/ad5686.h +++ b/drivers/iio/dac/ad5686.h @@ -54,6 +54,7 @@ enum ad5686_supported_device_ids { ID_AD5310R, ID_AD5311R, + ID_AD5337R, ID_AD5338R, ID_AD5671R, ID_AD5672R, diff --git a/drivers/iio/dac/ad5696-i2c.c b/drivers/iio/dac/ad5696-i2c.c index 160e80cf9135..8a95f0278018 100644 --- a/drivers/iio/dac/ad5696-i2c.c +++ b/drivers/iio/dac/ad5696-i2c.c @@ -72,6 +72,7 @@ static void ad5686_i2c_remove(struct i2c_client *i2c) static const struct i2c_device_id ad5686_i2c_id[] = { {"ad5311r", ID_AD5311R}, + {"ad5337r", ID_AD5337R}, {"ad5338r", ID_AD5338R}, {"ad5671r", ID_AD5671R}, {"ad5673r", ID_AD5673R}, @@ -92,6 +93,7 @@ MODULE_DEVICE_TABLE(i2c, ad5686_i2c_id); static const struct of_device_id ad5686_of_match[] = { { .compatible = "adi,ad5311r" }, + { .compatible = "adi,ad5337r" }, { .compatible = "adi,ad5338r" }, { .compatible = "adi,ad5671r" }, { .compatible = "adi,ad5675r" }, diff --git a/drivers/iio/dac/max5522.c b/drivers/iio/dac/max5522.c new file mode 100644 index 000000000000..00ba4e98fb9c --- /dev/null +++ b/drivers/iio/dac/max5522.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Maxim MAX5522 + * Dual, Ultra-Low-Power 10-Bit, Voltage-Output DACs + * + * Copyright 2022 Timesys Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MAX5522_MAX_ADDR 15 +#define MAX5522_CTRL_NONE 0 +#define MAX5522_CTRL_LOAD_IN_A 9 +#define MAX5522_CTRL_LOAD_IN_B 10 + +#define MAX5522_REG_DATA(x) ((x) + MAX5522_CTRL_LOAD_IN_A) + +struct max5522_chip_info { + const char *name; + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +struct max5522_state { + struct regmap *regmap; + const struct max5522_chip_info *chip_info; + unsigned short dac_cache[2]; + struct regulator *vrefin_reg; +}; + +#define MAX5522_CHANNEL(chan) { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .output = 1, \ + .channel = chan, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 10, \ + .storagebits = 16, \ + .shift = 2, \ + } \ +} + +const struct iio_chan_spec max5522_channels[] = { + MAX5522_CHANNEL(0), + MAX5522_CHANNEL(1), +}; + +enum max5522_type { + ID_MAX5522, +}; + +static const struct max5522_chip_info max5522_chip_info_tbl[] = { + [ID_MAX5522] = { + .name = "max5522", + .channels = max5522_channels, + .num_channels = 2, + }, +}; + +static inline int max5522_info_to_reg(struct iio_chan_spec const *chan) +{ + return MAX5522_REG_DATA(chan->channel); +} + +static int max5522_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long info) +{ + struct max5522_state *state = iio_priv(indio_dev); + int ret; + + switch (info) { + case IIO_CHAN_INFO_RAW: + *val = state->dac_cache[chan->channel]; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + ret = regulator_get_voltage(state->vrefin_reg); + if (ret < 0) + return -EINVAL; + *val = ret / 1000; + *val2 = 10; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } + + return -EINVAL; +} + +static int max5522_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + struct max5522_state *state = iio_priv(indio_dev); + int rval; + + if (val > 1023 || val < 0) + return -EINVAL; + + rval = regmap_write(state->regmap, max5522_info_to_reg(chan), + val << chan->scan_type.shift); + if (rval < 0) + return rval; + + state->dac_cache[chan->channel] = val; + + return 0; +} + +static const struct iio_info max5522_info = { + .read_raw = max5522_read_raw, + .write_raw = max5522_write_raw, +}; + +static const struct regmap_config max5522_regmap_config = { + .reg_bits = 4, + .val_bits = 12, + .max_register = MAX5522_MAX_ADDR, +}; + +static int max5522_spi_probe(struct spi_device *spi) +{ + const struct spi_device_id *id = spi_get_device_id(spi); + struct iio_dev *indio_dev; + struct max5522_state *state; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state)); + if (indio_dev == NULL) { + dev_err(&spi->dev, "failed to allocate iio device\n"); + return -ENOMEM; + } + + state = iio_priv(indio_dev); + state->chip_info = device_get_match_data(&spi->dev); + if (!state->chip_info) { + state->chip_info = + (struct max5522_chip_info *)(id->driver_data); + if (!state->chip_info) + return -EINVAL; + } + + state->vrefin_reg = devm_regulator_get(&spi->dev, "vrefin"); + if (IS_ERR(state->vrefin_reg)) + return dev_err_probe(&spi->dev, PTR_ERR(state->vrefin_reg), + "Vrefin regulator not specified\n"); + + ret = regulator_enable(state->vrefin_reg); + if (ret) { + return dev_err_probe(&spi->dev, ret, + "Failed to enable vref regulators\n"); + } + + state->regmap = devm_regmap_init_spi(spi, &max5522_regmap_config); + + if (IS_ERR(state->regmap)) + return PTR_ERR(state->regmap); + + indio_dev->info = &max5522_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = max5522_channels; + indio_dev->num_channels = ARRAY_SIZE(max5522_channels); + indio_dev->name = max5522_chip_info_tbl[ID_MAX5522].name; + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id max5522_ids[] = { + { "max5522", (kernel_ulong_t)&max5522_chip_info_tbl[ID_MAX5522] }, + {} +}; +MODULE_DEVICE_TABLE(spi, max5522_ids); + +static const struct of_device_id max5522_of_match[] = { + { + .compatible = "maxim,max5522", + .data = &max5522_chip_info_tbl[ID_MAX5522], + }, + {} +}; +MODULE_DEVICE_TABLE(of, max5522_of_match); + +static struct spi_driver max5522_spi_driver = { + .driver = { + .name = "max5522", + .of_match_table = max5522_of_match, + }, + .probe = max5522_spi_probe, + .id_table = max5522_ids, +}; +module_spi_driver(max5522_spi_driver); + +MODULE_AUTHOR("Angelo Dureghello wake_duration); if (ret < 0) { - dev_err(&data->client->dev, "Errow writing reg_wuf_timer\n"); + dev_err(&data->client->dev, "Error writing reg_wuf_timer\n"); return ret; } diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index 5b6f195748fc..499fcf8875b4 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -93,7 +93,7 @@ enum st_lsm6dsx_hw_id { .endianness = IIO_LE, \ }, \ .event_spec = &st_lsm6dsx_event, \ - .ext_info = st_lsm6dsx_accel_ext_info, \ + .ext_info = st_lsm6dsx_ext_info, \ .num_event_specs = 1, \ } @@ -113,6 +113,7 @@ enum st_lsm6dsx_hw_id { .storagebits = 16, \ .endianness = IIO_LE, \ }, \ + .ext_info = st_lsm6dsx_ext_info, \ } struct st_lsm6dsx_reg { @@ -528,7 +529,7 @@ st_lsm6dsx_device_set_enable(struct st_lsm6dsx_sensor *sensor, bool enable) } static const -struct iio_chan_spec_ext_info __maybe_unused st_lsm6dsx_accel_ext_info[] = { +struct iio_chan_spec_ext_info __maybe_unused st_lsm6dsx_ext_info[] = { IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, st_lsm6dsx_get_mount_matrix), { } }; diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c index f2b64b4956a3..c1b444520d2a 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_shub.c @@ -704,18 +704,18 @@ static ssize_t st_lsm6dsx_shub_scale_avail(struct device *dev, static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_shub_sampling_freq_avail); static IIO_DEVICE_ATTR(in_scale_available, 0444, st_lsm6dsx_shub_scale_avail, NULL, 0); -static struct attribute *st_lsm6dsx_ext_attributes[] = { +static struct attribute *st_lsm6dsx_shub_attributes[] = { &iio_dev_attr_sampling_frequency_available.dev_attr.attr, &iio_dev_attr_in_scale_available.dev_attr.attr, NULL, }; -static const struct attribute_group st_lsm6dsx_ext_attribute_group = { - .attrs = st_lsm6dsx_ext_attributes, +static const struct attribute_group st_lsm6dsx_shub_attribute_group = { + .attrs = st_lsm6dsx_shub_attributes, }; -static const struct iio_info st_lsm6dsx_ext_info = { - .attrs = &st_lsm6dsx_ext_attribute_group, +static const struct iio_info st_lsm6dsx_shub_info = { + .attrs = &st_lsm6dsx_shub_attribute_group, .read_raw = st_lsm6dsx_shub_read_raw, .write_raw = st_lsm6dsx_shub_write_raw, .hwfifo_set_watermark = st_lsm6dsx_set_watermark, @@ -737,7 +737,7 @@ st_lsm6dsx_shub_alloc_iiodev(struct st_lsm6dsx_hw *hw, return NULL; iio_dev->modes = INDIO_DIRECT_MODE; - iio_dev->info = &st_lsm6dsx_ext_info; + iio_dev->info = &st_lsm6dsx_shub_info; sensor = iio_priv(iio_dev); sensor->id = id; diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 52e690f031cb..c117f50d0cf3 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -8,30 +8,32 @@ #define pr_fmt(fmt) "iio-core: " fmt -#include -#include +#include +#include +#include +#include +#include +#include #include #include -#include -#include -#include +#include +#include +#include #include #include #include -#include -#include #include -#include -#include -#include -#include -#include -#include "iio_core.h" -#include "iio_core_trigger.h" -#include -#include +#include + #include #include +#include +#include +#include +#include + +#include "iio_core.h" +#include "iio_core_trigger.h" /* IDA to assign each registered device a unique id */ static DEFINE_IDA(iio_ida); @@ -205,36 +207,6 @@ bool iio_buffer_enabled(struct iio_dev *indio_dev) } EXPORT_SYMBOL_GPL(iio_buffer_enabled); -/** - * iio_sysfs_match_string_with_gaps - matches given string in an array with gaps - * @array: array of strings - * @n: number of strings in the array - * @str: string to match with - * - * Returns index of @str in the @array or -EINVAL, similar to match_string(). - * Uses sysfs_streq instead of strcmp for matching. - * - * This routine will look for a string in an array of strings. - * The search will continue until the element is found or the n-th element - * is reached, regardless of any NULL elements in the array. - */ -static int iio_sysfs_match_string_with_gaps(const char * const *array, size_t n, - const char *str) -{ - const char *item; - int index; - - for (index = 0; index < n; index++) { - item = array[index]; - if (!item) - continue; - if (sysfs_streq(item, str)) - return index; - } - - return -EINVAL; -} - #if defined(CONFIG_DEBUG_FS) /* * There's also a CONFIG_DEBUG_FS guard in include/linux/iio/iio.h for @@ -569,7 +541,7 @@ ssize_t iio_enum_write(struct iio_dev *indio_dev, if (!e->set) return -EINVAL; - ret = iio_sysfs_match_string_with_gaps(e->items, e->num_items, buf); + ret = __sysfs_match_string(e->items, e->num_items, buf); if (ret < 0) return ret; diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile index 6f23817fae6f..d74d2b5ff14c 100644 --- a/drivers/iio/light/Makefile +++ b/drivers/iio/light/Makefile @@ -39,7 +39,6 @@ obj-$(CONFIG_NOA1305) += noa1305.o obj-$(CONFIG_OPT3001) += opt3001.o obj-$(CONFIG_PA12203001) += pa12203001.o obj-$(CONFIG_RPR0521) += rpr0521.o -obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o obj-$(CONFIG_SI1133) += si1133.o obj-$(CONFIG_SI1145) += si1145.o obj-$(CONFIG_STK3310) += stk3310.o @@ -48,6 +47,7 @@ obj-$(CONFIG_ST_UVIS25_I2C) += st_uvis25_i2c.o obj-$(CONFIG_ST_UVIS25_SPI) += st_uvis25_spi.o obj-$(CONFIG_TCS3414) += tcs3414.o obj-$(CONFIG_TCS3472) += tcs3472.o +obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o obj-$(CONFIG_TSL2583) += tsl2583.o obj-$(CONFIG_TSL2591) += tsl2591.o obj-$(CONFIG_TSL2772) += tsl2772.o diff --git a/drivers/iio/light/max44009.c b/drivers/iio/light/max44009.c index 801e5a0ad496..3dadace09fe2 100644 --- a/drivers/iio/light/max44009.c +++ b/drivers/iio/light/max44009.c @@ -487,8 +487,7 @@ static irqreturn_t max44009_threaded_irq_handler(int irq, void *p) return IRQ_NONE; } -static int max44009_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int max44009_probe(struct i2c_client *client) { struct max44009_data *data; struct iio_dev *indio_dev; @@ -538,7 +537,7 @@ static struct i2c_driver max44009_driver = { .driver = { .name = MAX44009_DRV_NAME, }, - .probe = max44009_probe, + .probe_new = max44009_probe, .id_table = max44009_id, }; module_i2c_driver(max44009_driver); diff --git a/drivers/iio/light/tsl2563.c b/drivers/iio/light/tsl2563.c index d0e42b73203a..f2f55239a072 100644 --- a/drivers/iio/light/tsl2563.c +++ b/drivers/iio/light/tsl2563.c @@ -11,69 +11,63 @@ * Amit Kucheria */ -#include -#include -#include +#include +#include +#include #include #include #include -#include +#include +#include +#include #include -#include #include -#include +#include +#include #include +#include #include #include -#include -#include /* Use this many bits for fraction part. */ #define ADC_FRAC_BITS 14 /* Given number of 1/10000's in ADC_FRAC_BITS precision. */ -#define FRAC10K(f) (((f) * (1L << (ADC_FRAC_BITS))) / (10000)) +#define FRAC10K(f) (((f) * BIT(ADC_FRAC_BITS)) / (10000)) /* Bits used for fraction in calibration coefficients.*/ #define CALIB_FRAC_BITS 10 -/* 0.5 in CALIB_FRAC_BITS precision */ -#define CALIB_FRAC_HALF (1 << (CALIB_FRAC_BITS - 1)) -/* Make a fraction from a number n that was multiplied with b. */ -#define CALIB_FRAC(n, b) (((n) << CALIB_FRAC_BITS) / (b)) /* Decimal 10^(digits in sysfs presentation) */ #define CALIB_BASE_SYSFS 1000 -#define TSL2563_CMD 0x80 -#define TSL2563_CLEARINT 0x40 +#define TSL2563_CMD BIT(7) +#define TSL2563_CLEARINT BIT(6) #define TSL2563_REG_CTRL 0x00 #define TSL2563_REG_TIMING 0x01 -#define TSL2563_REG_LOWLOW 0x02 /* data0 low threshold, 2 bytes */ -#define TSL2563_REG_LOWHIGH 0x03 -#define TSL2563_REG_HIGHLOW 0x04 /* data0 high threshold, 2 bytes */ -#define TSL2563_REG_HIGHHIGH 0x05 +#define TSL2563_REG_LOW 0x02 /* data0 low threshold, 2 bytes */ +#define TSL2563_REG_HIGH 0x04 /* data0 high threshold, 2 bytes */ #define TSL2563_REG_INT 0x06 #define TSL2563_REG_ID 0x0a -#define TSL2563_REG_DATA0LOW 0x0c /* broadband sensor value, 2 bytes */ -#define TSL2563_REG_DATA0HIGH 0x0d -#define TSL2563_REG_DATA1LOW 0x0e /* infrared sensor value, 2 bytes */ -#define TSL2563_REG_DATA1HIGH 0x0f +#define TSL2563_REG_DATA0 0x0c /* broadband sensor value, 2 bytes */ +#define TSL2563_REG_DATA1 0x0e /* infrared sensor value, 2 bytes */ #define TSL2563_CMD_POWER_ON 0x03 #define TSL2563_CMD_POWER_OFF 0x00 -#define TSL2563_CTRL_POWER_MASK 0x03 +#define TSL2563_CTRL_POWER_MASK GENMASK(1, 0) #define TSL2563_TIMING_13MS 0x00 #define TSL2563_TIMING_100MS 0x01 #define TSL2563_TIMING_400MS 0x02 -#define TSL2563_TIMING_MASK 0x03 +#define TSL2563_TIMING_MASK GENMASK(1, 0) #define TSL2563_TIMING_GAIN16 0x10 #define TSL2563_TIMING_GAIN1 0x00 #define TSL2563_INT_DISABLED 0x00 #define TSL2563_INT_LEVEL 0x10 -#define TSL2563_INT_PERSIST(n) ((n) & 0x0F) +#define TSL2563_INT_MASK GENMASK(5, 4) +#define TSL2563_INT_PERSIST(n) ((n) & GENMASK(3, 0)) struct tsl2563_gainlevel_coeff { u8 gaintime; @@ -161,24 +155,16 @@ static int tsl2563_configure(struct tsl2563_chip *chip) chip->gainlevel->gaintime); if (ret) goto error_ret; - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | TSL2563_REG_HIGHLOW, - chip->high_thres & 0xFF); + ret = i2c_smbus_write_word_data(chip->client, + TSL2563_CMD | TSL2563_REG_HIGH, + chip->high_thres); if (ret) goto error_ret; - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | TSL2563_REG_HIGHHIGH, - (chip->high_thres >> 8) & 0xFF); + ret = i2c_smbus_write_word_data(chip->client, + TSL2563_CMD | TSL2563_REG_LOW, + chip->low_thres); if (ret) goto error_ret; - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | TSL2563_REG_LOWLOW, - chip->low_thres & 0xFF); - if (ret) - goto error_ret; - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | TSL2563_REG_LOWHIGH, - (chip->low_thres >> 8) & 0xFF); /* * Interrupt register is automatically written anyway if it is relevant * so is not here. @@ -223,6 +209,24 @@ static int tsl2563_read_id(struct tsl2563_chip *chip, u8 *id) return 0; } +static int tsl2563_configure_irq(struct tsl2563_chip *chip, bool enable) +{ + int ret; + + chip->intr &= ~TSL2563_INT_MASK; + if (enable) + chip->intr |= TSL2563_INT_LEVEL; + + ret = i2c_smbus_write_byte_data(chip->client, + TSL2563_CMD | TSL2563_REG_INT, + chip->intr); + if (ret < 0) + return ret; + + chip->int_enabled = enable; + return 0; +} + /* * "Normalized" ADC value is one obtained with 400ms of integration time and * 16x gain. This function returns the number of bits of shift needed to @@ -325,13 +329,13 @@ static int tsl2563_get_adc(struct tsl2563_chip *chip) while (retry) { ret = i2c_smbus_read_word_data(client, - TSL2563_CMD | TSL2563_REG_DATA0LOW); + TSL2563_CMD | TSL2563_REG_DATA0); if (ret < 0) goto out; adc0 = ret; ret = i2c_smbus_read_word_data(client, - TSL2563_CMD | TSL2563_REG_DATA1LOW); + TSL2563_CMD | TSL2563_REG_DATA1); if (ret < 0) goto out; adc1 = ret; @@ -352,12 +356,12 @@ out: static inline int tsl2563_calib_to_sysfs(u32 calib) { - return (int) (((calib * CALIB_BASE_SYSFS) + - CALIB_FRAC_HALF) >> CALIB_FRAC_BITS); + return (int)DIV_ROUND_CLOSEST(calib * CALIB_BASE_SYSFS, BIT(CALIB_FRAC_BITS)); } static inline u32 tsl2563_calib_from_sysfs(int value) { + /* Make a fraction from a number n that was multiplied with b. */ return (((u32) value) << CALIB_FRAC_BITS) / CALIB_BASE_SYSFS; } @@ -584,20 +588,18 @@ static int tsl2563_write_thresh(struct iio_dev *indio_dev, { struct tsl2563_chip *chip = iio_priv(indio_dev); int ret; - u8 address; + + mutex_lock(&chip->lock); if (dir == IIO_EV_DIR_RISING) - address = TSL2563_REG_HIGHLOW; + ret = i2c_smbus_write_word_data(chip->client, + TSL2563_CMD | TSL2563_REG_HIGH, val); else - address = TSL2563_REG_LOWLOW; - mutex_lock(&chip->lock); - ret = i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | address, - val & 0xFF); + ret = i2c_smbus_write_word_data(chip->client, + TSL2563_CMD | TSL2563_REG_LOW, val); if (ret) goto error_ret; - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | (address + 1), - (val >> 8) & 0xFF); + if (dir == IIO_EV_DIR_RISING) chip->high_thres = val; else @@ -634,9 +636,7 @@ static int tsl2563_write_interrupt_config(struct iio_dev *indio_dev, int ret = 0; mutex_lock(&chip->lock); - if (state && !(chip->intr & 0x30)) { - chip->intr &= ~0x30; - chip->intr |= 0x10; + if (state && !(chip->intr & TSL2563_INT_MASK)) { /* ensure the chip is actually on */ cancel_delayed_work_sync(&chip->poweroff_work); if (!tsl2563_get_power(chip)) { @@ -647,18 +647,11 @@ static int tsl2563_write_interrupt_config(struct iio_dev *indio_dev, if (ret) goto out; } - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | TSL2563_REG_INT, - chip->intr); - chip->int_enabled = true; + ret = tsl2563_configure_irq(chip, true); } - if (!state && (chip->intr & 0x30)) { - chip->intr &= ~0x30; - ret = i2c_smbus_write_byte_data(chip->client, - TSL2563_CMD | TSL2563_REG_INT, - chip->intr); - chip->int_enabled = false; + if (!state && (chip->intr & TSL2563_INT_MASK)) { + ret = tsl2563_configure_irq(chip, false); /* now the interrupt is not enabled, we can go to sleep */ schedule_delayed_work(&chip->poweroff_work, 5 * HZ); } @@ -682,7 +675,7 @@ static int tsl2563_read_interrupt_config(struct iio_dev *indio_dev, if (ret < 0) return ret; - return !!(ret & 0x30); + return !!(ret & TSL2563_INT_MASK); } static const struct iio_info tsl2563_info_no_irq = { @@ -701,13 +694,14 @@ static const struct iio_info tsl2563_info = { static int tsl2563_probe(struct i2c_client *client) { + struct device *dev = &client->dev; struct iio_dev *indio_dev; struct tsl2563_chip *chip; - struct tsl2563_platform_data *pdata = client->dev.platform_data; - int err = 0; + unsigned long irq_flags; u8 id = 0; + int err; - indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); + indio_dev = devm_iio_device_alloc(dev, sizeof(*chip)); if (!indio_dev) return -ENOMEM; @@ -717,16 +711,12 @@ static int tsl2563_probe(struct i2c_client *client) chip->client = client; err = tsl2563_detect(chip); - if (err) { - dev_err(&client->dev, "detect error %d\n", -err); - return err; - } + if (err) + return dev_err_probe(dev, err, "detect error\n"); err = tsl2563_read_id(chip, &id); - if (err) { - dev_err(&client->dev, "read id error %d\n", -err); - return err; - } + if (err) + return dev_err_probe(dev, err, "read id error\n"); mutex_init(&chip->lock); @@ -738,16 +728,10 @@ static int tsl2563_probe(struct i2c_client *client) chip->calib0 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS); chip->calib1 = tsl2563_calib_from_sysfs(CALIB_BASE_SYSFS); - if (pdata) { - chip->cover_comp_gain = pdata->cover_comp_gain; - } else { - err = device_property_read_u32(&client->dev, "amstaos,cover-comp-gain", - &chip->cover_comp_gain); - if (err) - chip->cover_comp_gain = 1; - } + chip->cover_comp_gain = 1; + device_property_read_u32(dev, "amstaos,cover-comp-gain", &chip->cover_comp_gain); - dev_info(&client->dev, "model %d, rev. %d\n", id >> 4, id & 0x0f); + dev_info(dev, "model %d, rev. %d\n", id >> 4, id & 0x0f); indio_dev->name = client->name; indio_dev->channels = tsl2563_channels; indio_dev->num_channels = ARRAY_SIZE(tsl2563_channels); @@ -759,23 +743,24 @@ static int tsl2563_probe(struct i2c_client *client) indio_dev->info = &tsl2563_info_no_irq; if (client->irq) { - err = devm_request_threaded_irq(&client->dev, client->irq, + irq_flags = irq_get_trigger_type(client->irq); + if (irq_flags == IRQF_TRIGGER_NONE) + irq_flags = IRQF_TRIGGER_RISING; + irq_flags |= IRQF_ONESHOT; + + err = devm_request_threaded_irq(dev, client->irq, NULL, &tsl2563_event_handler, - IRQF_TRIGGER_RISING | IRQF_ONESHOT, + irq_flags, "tsl2563_event", indio_dev); - if (err) { - dev_err(&client->dev, "irq request error %d\n", -err); - return err; - } + if (err) + return dev_err_probe(dev, err, "irq request error\n"); } err = tsl2563_configure(chip); - if (err) { - dev_err(&client->dev, "configure error %d\n", -err); - return err; - } + if (err) + return dev_err_probe(dev, err, "configure error\n"); INIT_DELAYED_WORK(&chip->poweroff_work, tsl2563_poweroff_work); @@ -784,7 +769,7 @@ static int tsl2563_probe(struct i2c_client *client) err = iio_device_register(indio_dev); if (err) { - dev_err(&client->dev, "iio registration error %d\n", -err); + dev_err_probe(dev, err, "iio registration error\n"); goto fail; } @@ -804,15 +789,13 @@ static void tsl2563_remove(struct i2c_client *client) if (!chip->int_enabled) cancel_delayed_work_sync(&chip->poweroff_work); /* Ensure that interrupts are disabled - then flush any bottom halves */ - chip->intr &= ~0x30; - i2c_smbus_write_byte_data(chip->client, TSL2563_CMD | TSL2563_REG_INT, - chip->intr); + tsl2563_configure_irq(chip, false); tsl2563_set_power(chip, 0); } static int tsl2563_suspend(struct device *dev) { - struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct iio_dev *indio_dev = dev_get_drvdata(dev); struct tsl2563_chip *chip = iio_priv(indio_dev); int ret; @@ -831,7 +814,7 @@ out: static int tsl2563_resume(struct device *dev) { - struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); + struct iio_dev *indio_dev = dev_get_drvdata(dev); struct tsl2563_chip *chip = iio_priv(indio_dev); int ret; diff --git a/drivers/iio/light/vcnl4000.c b/drivers/iio/light/vcnl4000.c index cc1a2062e76d..6bdfce9747f9 100644 --- a/drivers/iio/light/vcnl4000.c +++ b/drivers/iio/light/vcnl4000.c @@ -60,8 +60,11 @@ #define VCNL4200_AL_CONF 0x00 /* Ambient light configuration */ #define VCNL4200_PS_CONF1 0x03 /* Proximity configuration */ +#define VCNL4040_PS_THDL_LM 0x06 /* Proximity threshold low */ +#define VCNL4040_PS_THDH_LM 0x07 /* Proximity threshold high */ #define VCNL4200_PS_DATA 0x08 /* Proximity data */ #define VCNL4200_AL_DATA 0x09 /* Ambient light data */ +#define VCNL4040_INT_FLAGS 0x0b /* Interrupt register */ #define VCNL4200_DEV_ID 0x0e /* Device ID, slave address and version */ #define VCNL4040_DEV_ID 0x0c /* Device ID and version */ @@ -78,6 +81,9 @@ #define VCNL4040_ALS_CONF_ALS_SHUTDOWN BIT(0) #define VCNL4040_PS_CONF1_PS_SHUTDOWN BIT(0) #define VCNL4040_PS_CONF2_PS_IT GENMASK(3, 1) /* Proximity integration time */ +#define VCNL4040_PS_CONF2_PS_INT GENMASK(9, 8) /* Proximity interrupt mode */ +#define VCNL4040_PS_IF_AWAY BIT(8) /* Proximity event cross low threshold */ +#define VCNL4040_PS_IF_CLOSE BIT(9) /* Proximity event cross high threshold */ /* Bit masks for interrupt registers. */ #define VCNL4010_INT_THR_SEL BIT(0) /* Select threshold interrupt source */ @@ -138,6 +144,7 @@ struct vcnl4000_data { enum vcnl4000_device_ids id; int rev; int al_scale; + u8 ps_int; /* proximity interrupt mode */ const struct vcnl4000_chip_spec *chip_spec; struct mutex vcnl4000_lock; struct vcnl4200_channel vcnl4200_al; @@ -150,11 +157,13 @@ struct vcnl4000_chip_spec { struct iio_chan_spec const *channels; const int num_channels; const struct iio_info *info; - bool irq_support; + const struct iio_buffer_setup_ops *buffer_setup_ops; int (*init)(struct vcnl4000_data *data); int (*measure_light)(struct vcnl4000_data *data, int *val); int (*measure_proximity)(struct vcnl4000_data *data, int *val); int (*set_power_state)(struct vcnl4000_data *data, bool on); + irqreturn_t (*irq_thread)(int irq, void *priv); + irqreturn_t (*trig_buffer_func)(int irq, void *priv); }; static const struct i2c_device_id vcnl4000_id[] = { @@ -254,6 +263,10 @@ static int vcnl4200_set_power_state(struct vcnl4000_data *data, bool on) { int ret; + /* Do not power down if interrupts are enabled */ + if (!on && data->ps_int) + return 0; + ret = vcnl4000_write_als_enable(data, on); if (ret < 0) return ret; @@ -295,6 +308,7 @@ static int vcnl4200_init(struct vcnl4000_data *data) dev_dbg(&data->client->dev, "device id 0x%x", id); data->rev = (ret >> 8) & 0xf; + data->ps_int = 0; data->vcnl4200_al.reg = VCNL4200_AL_DATA; data->vcnl4200_ps.reg = VCNL4200_PS_DATA; @@ -795,6 +809,64 @@ static int vcnl4010_write_event(struct iio_dev *indio_dev, } } +static int vcnl4040_read_event(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int *val, int *val2) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + switch (dir) { + case IIO_EV_DIR_RISING: + ret = i2c_smbus_read_word_data(data->client, + VCNL4040_PS_THDH_LM); + if (ret < 0) + return ret; + *val = ret; + return IIO_VAL_INT; + case IIO_EV_DIR_FALLING: + ret = i2c_smbus_read_word_data(data->client, + VCNL4040_PS_THDL_LM); + if (ret < 0) + return ret; + *val = ret; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int vcnl4040_write_event(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, + int val, int val2) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + switch (dir) { + case IIO_EV_DIR_RISING: + ret = i2c_smbus_write_word_data(data->client, + VCNL4040_PS_THDH_LM, val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + case IIO_EV_DIR_FALLING: + ret = i2c_smbus_write_word_data(data->client, + VCNL4040_PS_THDL_LM, val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + static bool vcnl4010_is_thr_enabled(struct vcnl4000_data *data) { int ret; @@ -877,6 +949,86 @@ static int vcnl4010_write_event_config(struct iio_dev *indio_dev, } } +static int vcnl4040_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + int ret; + struct vcnl4000_data *data = iio_priv(indio_dev); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + return ret; + + data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, ret); + + return (dir == IIO_EV_DIR_RISING) ? + FIELD_GET(VCNL4040_PS_IF_AWAY, ret) : + FIELD_GET(VCNL4040_PS_IF_CLOSE, ret); +} + +static int vcnl4040_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, int state) +{ + int ret; + u16 val, mask; + struct vcnl4000_data *data = iio_priv(indio_dev); + + mutex_lock(&data->vcnl4000_lock); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + goto out; + + if (dir == IIO_EV_DIR_RISING) + mask = VCNL4040_PS_IF_AWAY; + else + mask = VCNL4040_PS_IF_CLOSE; + + val = state ? (ret | mask) : (ret & ~mask); + + data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, val); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, val); + +out: + mutex_unlock(&data->vcnl4000_lock); + data->chip_spec->set_power_state(data, data->ps_int != 0); + + return ret; +} + +static irqreturn_t vcnl4040_irq_thread(int irq, void *p) +{ + struct iio_dev *indio_dev = p; + struct vcnl4000_data *data = iio_priv(indio_dev); + int ret; + + ret = i2c_smbus_read_word_data(data->client, VCNL4040_INT_FLAGS); + if (ret < 0) + return IRQ_HANDLED; + + if (ret & VCNL4040_PS_IF_CLOSE) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + } + + if (ret & VCNL4040_PS_IF_AWAY) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_FALLING), + iio_get_time_ns(indio_dev)); + } + + return IRQ_HANDLED; +} + static ssize_t vcnl4000_read_near_level(struct iio_dev *indio_dev, uintptr_t priv, const struct iio_chan_spec *chan, @@ -887,149 +1039,6 @@ static ssize_t vcnl4000_read_near_level(struct iio_dev *indio_dev, return sprintf(buf, "%u\n", data->near_level); } -static const struct iio_chan_spec_ext_info vcnl4000_ext_info[] = { - { - .name = "nearlevel", - .shared = IIO_SEPARATE, - .read = vcnl4000_read_near_level, - }, - { /* sentinel */ } -}; - -static const struct iio_event_spec vcnl4000_event_spec[] = { - { - .type = IIO_EV_TYPE_THRESH, - .dir = IIO_EV_DIR_RISING, - .mask_separate = BIT(IIO_EV_INFO_VALUE), - }, { - .type = IIO_EV_TYPE_THRESH, - .dir = IIO_EV_DIR_FALLING, - .mask_separate = BIT(IIO_EV_INFO_VALUE), - }, { - .type = IIO_EV_TYPE_THRESH, - .dir = IIO_EV_DIR_EITHER, - .mask_separate = BIT(IIO_EV_INFO_ENABLE), - } -}; - -static const struct iio_chan_spec vcnl4000_channels[] = { - { - .type = IIO_LIGHT, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), - }, { - .type = IIO_PROXIMITY, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), - .ext_info = vcnl4000_ext_info, - } -}; - -static const struct iio_chan_spec vcnl4010_channels[] = { - { - .type = IIO_LIGHT, - .scan_index = -1, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), - }, { - .type = IIO_PROXIMITY, - .scan_index = 0, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SAMP_FREQ), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), - .event_spec = vcnl4000_event_spec, - .num_event_specs = ARRAY_SIZE(vcnl4000_event_spec), - .ext_info = vcnl4000_ext_info, - .scan_type = { - .sign = 'u', - .realbits = 16, - .storagebits = 16, - .endianness = IIO_CPU, - }, - }, - IIO_CHAN_SOFT_TIMESTAMP(1), -}; - -static const struct iio_chan_spec vcnl4040_channels[] = { - { - .type = IIO_LIGHT, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), - }, { - .type = IIO_PROXIMITY, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_INT_TIME), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME), - .ext_info = vcnl4000_ext_info, - } -}; - -static const struct iio_info vcnl4000_info = { - .read_raw = vcnl4000_read_raw, -}; - -static const struct iio_info vcnl4010_info = { - .read_raw = vcnl4010_read_raw, - .read_avail = vcnl4010_read_avail, - .write_raw = vcnl4010_write_raw, - .read_event_value = vcnl4010_read_event, - .write_event_value = vcnl4010_write_event, - .read_event_config = vcnl4010_read_event_config, - .write_event_config = vcnl4010_write_event_config, -}; - -static const struct iio_info vcnl4040_info = { - .read_raw = vcnl4000_read_raw, - .write_raw = vcnl4040_write_raw, - .read_avail = vcnl4040_read_avail, -}; - -static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { - [VCNL4000] = { - .prod = "VCNL4000", - .init = vcnl4000_init, - .measure_light = vcnl4000_measure_light, - .measure_proximity = vcnl4000_measure_proximity, - .set_power_state = vcnl4000_set_power_state, - .channels = vcnl4000_channels, - .num_channels = ARRAY_SIZE(vcnl4000_channels), - .info = &vcnl4000_info, - .irq_support = false, - }, - [VCNL4010] = { - .prod = "VCNL4010/4020", - .init = vcnl4000_init, - .measure_light = vcnl4000_measure_light, - .measure_proximity = vcnl4000_measure_proximity, - .set_power_state = vcnl4000_set_power_state, - .channels = vcnl4010_channels, - .num_channels = ARRAY_SIZE(vcnl4010_channels), - .info = &vcnl4010_info, - .irq_support = true, - }, - [VCNL4040] = { - .prod = "VCNL4040", - .init = vcnl4200_init, - .measure_light = vcnl4200_measure_light, - .measure_proximity = vcnl4200_measure_proximity, - .set_power_state = vcnl4200_set_power_state, - .channels = vcnl4040_channels, - .num_channels = ARRAY_SIZE(vcnl4040_channels), - .info = &vcnl4040_info, - .irq_support = false, - }, - [VCNL4200] = { - .prod = "VCNL4200", - .init = vcnl4200_init, - .measure_light = vcnl4200_measure_light, - .measure_proximity = vcnl4200_measure_proximity, - .set_power_state = vcnl4200_set_power_state, - .channels = vcnl4000_channels, - .num_channels = ARRAY_SIZE(vcnl4000_channels), - .info = &vcnl4000_info, - .irq_support = false, - }, -}; - static irqreturn_t vcnl4010_irq_thread(int irq, void *p) { struct iio_dev *indio_dev = p; @@ -1158,6 +1167,167 @@ static const struct iio_buffer_setup_ops vcnl4010_buffer_ops = { .predisable = &vcnl4010_buffer_predisable, }; +static const struct iio_chan_spec_ext_info vcnl4000_ext_info[] = { + { + .name = "nearlevel", + .shared = IIO_SEPARATE, + .read = vcnl4000_read_near_level, + }, + { /* sentinel */ } +}; + +static const struct iio_event_spec vcnl4000_event_spec[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = BIT(IIO_EV_INFO_ENABLE), + } +}; + +static const struct iio_event_spec vcnl4040_event_spec[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), + }, +}; + +static const struct iio_chan_spec vcnl4000_channels[] = { + { + .type = IIO_LIGHT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, { + .type = IIO_PROXIMITY, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .ext_info = vcnl4000_ext_info, + } +}; + +static const struct iio_chan_spec vcnl4010_channels[] = { + { + .type = IIO_LIGHT, + .scan_index = -1, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, { + .type = IIO_PROXIMITY, + .scan_index = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .event_spec = vcnl4000_event_spec, + .num_event_specs = ARRAY_SIZE(vcnl4000_event_spec), + .ext_info = vcnl4000_ext_info, + .scan_type = { + .sign = 'u', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct iio_chan_spec vcnl4040_channels[] = { + { + .type = IIO_LIGHT, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + }, { + .type = IIO_PROXIMITY, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_INT_TIME), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME), + .ext_info = vcnl4000_ext_info, + .event_spec = vcnl4040_event_spec, + .num_event_specs = ARRAY_SIZE(vcnl4040_event_spec), + } +}; + +static const struct iio_info vcnl4000_info = { + .read_raw = vcnl4000_read_raw, +}; + +static const struct iio_info vcnl4010_info = { + .read_raw = vcnl4010_read_raw, + .read_avail = vcnl4010_read_avail, + .write_raw = vcnl4010_write_raw, + .read_event_value = vcnl4010_read_event, + .write_event_value = vcnl4010_write_event, + .read_event_config = vcnl4010_read_event_config, + .write_event_config = vcnl4010_write_event_config, +}; + +static const struct iio_info vcnl4040_info = { + .read_raw = vcnl4000_read_raw, + .write_raw = vcnl4040_write_raw, + .read_event_value = vcnl4040_read_event, + .write_event_value = vcnl4040_write_event, + .read_event_config = vcnl4040_read_event_config, + .write_event_config = vcnl4040_write_event_config, + .read_avail = vcnl4040_read_avail, +}; + +static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { + [VCNL4000] = { + .prod = "VCNL4000", + .init = vcnl4000_init, + .measure_light = vcnl4000_measure_light, + .measure_proximity = vcnl4000_measure_proximity, + .set_power_state = vcnl4000_set_power_state, + .channels = vcnl4000_channels, + .num_channels = ARRAY_SIZE(vcnl4000_channels), + .info = &vcnl4000_info, + }, + [VCNL4010] = { + .prod = "VCNL4010/4020", + .init = vcnl4000_init, + .measure_light = vcnl4000_measure_light, + .measure_proximity = vcnl4000_measure_proximity, + .set_power_state = vcnl4000_set_power_state, + .channels = vcnl4010_channels, + .num_channels = ARRAY_SIZE(vcnl4010_channels), + .info = &vcnl4010_info, + .irq_thread = vcnl4010_irq_thread, + .trig_buffer_func = vcnl4010_trigger_handler, + .buffer_setup_ops = &vcnl4010_buffer_ops, + }, + [VCNL4040] = { + .prod = "VCNL4040", + .init = vcnl4200_init, + .measure_light = vcnl4200_measure_light, + .measure_proximity = vcnl4200_measure_proximity, + .set_power_state = vcnl4200_set_power_state, + .channels = vcnl4040_channels, + .num_channels = ARRAY_SIZE(vcnl4040_channels), + .info = &vcnl4040_info, + .irq_thread = vcnl4040_irq_thread, + }, + [VCNL4200] = { + .prod = "VCNL4200", + .init = vcnl4200_init, + .measure_light = vcnl4200_measure_light, + .measure_proximity = vcnl4200_measure_proximity, + .set_power_state = vcnl4200_set_power_state, + .channels = vcnl4000_channels, + .num_channels = ARRAY_SIZE(vcnl4000_channels), + .info = &vcnl4000_info, + }, +}; + static const struct iio_trigger_ops vcnl4010_trigger_ops = { .validate_device = iio_trigger_validate_own_device, }; @@ -1214,22 +1384,25 @@ static int vcnl4000_probe(struct i2c_client *client) indio_dev->name = VCNL4000_DRV_NAME; indio_dev->modes = INDIO_DIRECT_MODE; - if (client->irq && data->chip_spec->irq_support) { + if (data->chip_spec->trig_buffer_func && + data->chip_spec->buffer_setup_ops) { ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL, - vcnl4010_trigger_handler, - &vcnl4010_buffer_ops); + data->chip_spec->trig_buffer_func, + data->chip_spec->buffer_setup_ops); if (ret < 0) { dev_err(&client->dev, "unable to setup iio triggered buffer\n"); return ret; } + } + if (client->irq && data->chip_spec->irq_thread) { ret = devm_request_threaded_irq(&client->dev, client->irq, - NULL, vcnl4010_irq_thread, + NULL, data->chip_spec->irq_thread, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, - "vcnl4010_irq", + "vcnl4000_irq", indio_dev); if (ret < 0) { dev_err(&client->dev, "irq request failed\n"); diff --git a/drivers/iio/magnetometer/Kconfig b/drivers/iio/magnetometer/Kconfig index b91fc5e6a26e..38532d840f2a 100644 --- a/drivers/iio/magnetometer/Kconfig +++ b/drivers/iio/magnetometer/Kconfig @@ -119,7 +119,7 @@ config IIO_ST_MAGN_3AXIS select IIO_TRIGGERED_BUFFER if (IIO_BUFFER) help Say yes here to build support for STMicroelectronics magnetometers: - LSM303DLHC, LSM303DLM, LIS3MDL. + LSM303C, LSM303DLHC, LSM303DLM, LIS3MDL. Also need to enable at least one of I2C and SPI interface drivers below. @@ -208,6 +208,18 @@ config SENSORS_RM3100_SPI To compile this driver as a module, choose M here: the module will be called rm3100-spi. +config TI_TMAG5273 + tristate "TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor" + depends on I2C + select REGMAP_I2C + help + Say Y here to add support for the TI TMAG5273 Low-Power + Linear 3D Hall-Effect Sensor. + + This driver can also be compiled as a module. + To compile this driver as a module, choose M here: the module + will be called tmag5273. + config YAMAHA_YAS530 tristate "Yamaha YAS530 family of 3-Axis Magnetometers (I2C)" depends on I2C diff --git a/drivers/iio/magnetometer/Makefile b/drivers/iio/magnetometer/Makefile index b9f45b7fafc3..b1c784ea71c8 100644 --- a/drivers/iio/magnetometer/Makefile +++ b/drivers/iio/magnetometer/Makefile @@ -29,4 +29,6 @@ obj-$(CONFIG_SENSORS_RM3100) += rm3100-core.o obj-$(CONFIG_SENSORS_RM3100_I2C) += rm3100-i2c.o obj-$(CONFIG_SENSORS_RM3100_SPI) += rm3100-spi.o +obj-$(CONFIG_TI_TMAG5273) += tmag5273.o + obj-$(CONFIG_YAMAHA_YAS530) += yamaha-yas530.o diff --git a/drivers/iio/magnetometer/st_magn.h b/drivers/iio/magnetometer/st_magn.h index 785b7f7b8b06..89945984d966 100644 --- a/drivers/iio/magnetometer/st_magn.h +++ b/drivers/iio/magnetometer/st_magn.h @@ -22,6 +22,7 @@ #define LIS2MDL_MAGN_DEV_NAME "lis2mdl" #define LSM9DS1_MAGN_DEV_NAME "lsm9ds1_magn" #define IIS2MDC_MAGN_DEV_NAME "iis2mdc" +#define LSM303C_MAGN_DEV_NAME "lsm303c_magn" #ifdef CONFIG_IIO_BUFFER int st_magn_allocate_ring(struct iio_dev *indio_dev); diff --git a/drivers/iio/magnetometer/st_magn_core.c b/drivers/iio/magnetometer/st_magn_core.c index e2fd233b3626..8faa7409d9e1 100644 --- a/drivers/iio/magnetometer/st_magn_core.c +++ b/drivers/iio/magnetometer/st_magn_core.c @@ -305,6 +305,7 @@ static const struct st_sensor_settings st_magn_sensors_settings[] = { .sensors_supported = { [0] = LIS3MDL_MAGN_DEV_NAME, [1] = LSM9DS1_MAGN_DEV_NAME, + [2] = LSM303C_MAGN_DEV_NAME, }, .ch = (struct iio_chan_spec *)st_magn_2_16bit_channels, .odr = { diff --git a/drivers/iio/magnetometer/st_magn_i2c.c b/drivers/iio/magnetometer/st_magn_i2c.c index b4098d3b3813..cc0e0e94b129 100644 --- a/drivers/iio/magnetometer/st_magn_i2c.c +++ b/drivers/iio/magnetometer/st_magn_i2c.c @@ -50,6 +50,10 @@ static const struct of_device_id st_magn_of_match[] = { .compatible = "st,iis2mdc", .data = IIS2MDC_MAGN_DEV_NAME, }, + { + .compatible = "st,lsm303c-magn", + .data = LSM303C_MAGN_DEV_NAME, + }, {}, }; MODULE_DEVICE_TABLE(of, st_magn_of_match); @@ -97,6 +101,7 @@ static const struct i2c_device_id st_magn_id_table[] = { { LIS2MDL_MAGN_DEV_NAME }, { LSM9DS1_MAGN_DEV_NAME }, { IIS2MDC_MAGN_DEV_NAME }, + { LSM303C_MAGN_DEV_NAME }, {}, }; MODULE_DEVICE_TABLE(i2c, st_magn_id_table); diff --git a/drivers/iio/magnetometer/st_magn_spi.c b/drivers/iio/magnetometer/st_magn_spi.c index 6ddc4318564a..f203e1f87eec 100644 --- a/drivers/iio/magnetometer/st_magn_spi.c +++ b/drivers/iio/magnetometer/st_magn_spi.c @@ -45,6 +45,10 @@ static const struct of_device_id st_magn_of_match[] = { .compatible = "st,iis2mdc", .data = IIS2MDC_MAGN_DEV_NAME, }, + { + .compatible = "st,lsm303c-magn", + .data = LSM303C_MAGN_DEV_NAME, + }, {} }; MODULE_DEVICE_TABLE(of, st_magn_of_match); @@ -89,6 +93,7 @@ static const struct spi_device_id st_magn_id_table[] = { { LIS2MDL_MAGN_DEV_NAME }, { LSM9DS1_MAGN_DEV_NAME }, { IIS2MDC_MAGN_DEV_NAME }, + { LSM303C_MAGN_DEV_NAME }, {}, }; MODULE_DEVICE_TABLE(spi, st_magn_id_table); diff --git a/drivers/iio/magnetometer/tmag5273.c b/drivers/iio/magnetometer/tmag5273.c new file mode 100644 index 000000000000..28bb7efe8df8 --- /dev/null +++ b/drivers/iio/magnetometer/tmag5273.c @@ -0,0 +1,743 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor + * + * Copyright (C) 2022 WolfVision GmbH + * + * Author: Gerald Loacker + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define TMAG5273_DEVICE_CONFIG_1 0x00 +#define TMAG5273_DEVICE_CONFIG_2 0x01 +#define TMAG5273_SENSOR_CONFIG_1 0x02 +#define TMAG5273_SENSOR_CONFIG_2 0x03 +#define TMAG5273_X_THR_CONFIG 0x04 +#define TMAG5273_Y_THR_CONFIG 0x05 +#define TMAG5273_Z_THR_CONFIG 0x06 +#define TMAG5273_T_CONFIG 0x07 +#define TMAG5273_INT_CONFIG_1 0x08 +#define TMAG5273_MAG_GAIN_CONFIG 0x09 +#define TMAG5273_MAG_OFFSET_CONFIG_1 0x0A +#define TMAG5273_MAG_OFFSET_CONFIG_2 0x0B +#define TMAG5273_I2C_ADDRESS 0x0C +#define TMAG5273_DEVICE_ID 0x0D +#define TMAG5273_MANUFACTURER_ID_LSB 0x0E +#define TMAG5273_MANUFACTURER_ID_MSB 0x0F +#define TMAG5273_T_MSB_RESULT 0x10 +#define TMAG5273_T_LSB_RESULT 0x11 +#define TMAG5273_X_MSB_RESULT 0x12 +#define TMAG5273_X_LSB_RESULT 0x13 +#define TMAG5273_Y_MSB_RESULT 0x14 +#define TMAG5273_Y_LSB_RESULT 0x15 +#define TMAG5273_Z_MSB_RESULT 0x16 +#define TMAG5273_Z_LSB_RESULT 0x17 +#define TMAG5273_CONV_STATUS 0x18 +#define TMAG5273_ANGLE_RESULT_MSB 0x19 +#define TMAG5273_ANGLE_RESULT_LSB 0x1A +#define TMAG5273_MAGNITUDE_RESULT 0x1B +#define TMAG5273_DEVICE_STATUS 0x1C +#define TMAG5273_MAX_REG TMAG5273_DEVICE_STATUS + +#define TMAG5273_AUTOSLEEP_DELAY_MS 5000 +#define TMAG5273_MAX_AVERAGE 32 + +/* + * bits in the TMAG5273_MANUFACTURER_ID_LSB / MSB register + * 16-bit unique manufacturer ID 0x49 / 0x54 = "TI" + */ +#define TMAG5273_MANUFACTURER_ID 0x5449 + +/* bits in the TMAG5273_DEVICE_CONFIG_1 register */ +#define TMAG5273_AVG_MODE_MASK GENMASK(4, 2) +#define TMAG5273_AVG_1_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 0) +#define TMAG5273_AVG_2_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 1) +#define TMAG5273_AVG_4_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 2) +#define TMAG5273_AVG_8_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 3) +#define TMAG5273_AVG_16_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 4) +#define TMAG5273_AVG_32_MODE FIELD_PREP(TMAG5273_AVG_MODE_MASK, 5) + +/* bits in the TMAG5273_DEVICE_CONFIG_2 register */ +#define TMAG5273_OP_MODE_MASK GENMASK(1, 0) +#define TMAG5273_OP_MODE_STANDBY FIELD_PREP(TMAG5273_OP_MODE_MASK, 0) +#define TMAG5273_OP_MODE_SLEEP FIELD_PREP(TMAG5273_OP_MODE_MASK, 1) +#define TMAG5273_OP_MODE_CONT FIELD_PREP(TMAG5273_OP_MODE_MASK, 2) +#define TMAG5273_OP_MODE_WAKEUP FIELD_PREP(TMAG5273_OP_MODE_MASK, 3) + +/* bits in the TMAG5273_SENSOR_CONFIG_1 register */ +#define TMAG5273_MAG_CH_EN_MASK GENMASK(7, 4) +#define TMAG5273_MAG_CH_EN_X_Y_Z 7 + +/* bits in the TMAG5273_SENSOR_CONFIG_2 register */ +#define TMAG5273_Z_RANGE_MASK BIT(0) +#define TMAG5273_X_Y_RANGE_MASK BIT(1) +#define TMAG5273_ANGLE_EN_MASK GENMASK(3, 2) +#define TMAG5273_ANGLE_EN_OFF 0 +#define TMAG5273_ANGLE_EN_X_Y 1 +#define TMAG5273_ANGLE_EN_Y_Z 2 +#define TMAG5273_ANGLE_EN_X_Z 3 + +/* bits in the TMAG5273_T_CONFIG register */ +#define TMAG5273_T_CH_EN BIT(0) + +/* bits in the TMAG5273_DEVICE_ID register */ +#define TMAG5273_VERSION_MASK GENMASK(1, 0) + +/* bits in the TMAG5273_CONV_STATUS register */ +#define TMAG5273_CONV_STATUS_COMPLETE BIT(0) + +enum tmag5273_channels { + TEMPERATURE = 0, + AXIS_X, + AXIS_Y, + AXIS_Z, + ANGLE, + MAGNITUDE, +}; + +enum tmag5273_scale_index { + MAGN_RANGE_LOW = 0, + MAGN_RANGE_HIGH, + MAGN_RANGE_NUM +}; + +/* state container for the TMAG5273 driver */ +struct tmag5273_data { + struct device *dev; + unsigned int devid; + unsigned int version; + char name[16]; + unsigned int conv_avg; + unsigned int scale; + enum tmag5273_scale_index scale_index; + unsigned int angle_measurement; + struct regmap *map; + struct regulator *vcc; + + /* + * Locks the sensor for exclusive use during a measurement (which + * involves several register transactions so the regmap lock is not + * enough) so that measurements get serialized in a + * first-come-first-serve manner. + */ + struct mutex lock; +}; + +static const char *const tmag5273_angle_names[] = { "off", "x-y", "y-z", "x-z" }; + +/* + * Averaging enables additional sampling of the sensor data to reduce the noise + * effect, but also increases conversion time. + */ +static const unsigned int tmag5273_avg_table[] = { + 1, 2, 4, 8, 16, 32, +}; + +/* + * Magnetic resolution in Gauss for different TMAG5273 versions. + * Scale[Gauss] = Range[mT] * 1000 / 2^15 * 10, (1 mT = 10 Gauss) + * Only version 1 and 2 are valid, version 0 and 3 are reserved. + */ +static const struct iio_val_int_plus_micro tmag5273_scale[][MAGN_RANGE_NUM] = { + { { 0, 0 }, { 0, 0 } }, + { { 0, 12200 }, { 0, 24400 } }, + { { 0, 40600 }, { 0, 81200 } }, + { { 0, 0 }, { 0, 0 } }, +}; + +static int tmag5273_get_measure(struct tmag5273_data *data, s16 *t, s16 *x, + s16 *y, s16 *z, u16 *angle, u16 *magnitude) +{ + unsigned int status, val; + __be16 reg_data[4]; + int ret; + + mutex_lock(&data->lock); + + /* + * Max. conversion time is 2425 us in 32x averaging mode for all three + * channels. Since we are in continuous measurement mode, a measurement + * may already be there, so poll for completed measurement with + * timeout. + */ + ret = regmap_read_poll_timeout(data->map, TMAG5273_CONV_STATUS, status, + status & TMAG5273_CONV_STATUS_COMPLETE, + 100, 10000); + if (ret) { + dev_err(data->dev, "timeout waiting for measurement\n"); + goto out_unlock; + } + + ret = regmap_bulk_read(data->map, TMAG5273_T_MSB_RESULT, reg_data, + sizeof(reg_data)); + if (ret) + goto out_unlock; + *t = be16_to_cpu(reg_data[0]); + *x = be16_to_cpu(reg_data[1]); + *y = be16_to_cpu(reg_data[2]); + *z = be16_to_cpu(reg_data[3]); + + ret = regmap_bulk_read(data->map, TMAG5273_ANGLE_RESULT_MSB, + ®_data[0], sizeof(reg_data[0])); + if (ret) + goto out_unlock; + /* + * angle has 9 bits integer value and 4 bits fractional part + * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * 0 0 0 a a a a a a a a a f f f f + */ + *angle = be16_to_cpu(reg_data[0]); + + ret = regmap_read(data->map, TMAG5273_MAGNITUDE_RESULT, &val); + if (ret < 0) + goto out_unlock; + *magnitude = val; + +out_unlock: + mutex_unlock(&data->lock); + return ret; +} + +static int tmag5273_write_osr(struct tmag5273_data *data, int val) +{ + int i; + + if (val == data->conv_avg) + return 0; + + for (i = 0; i < ARRAY_SIZE(tmag5273_avg_table); i++) { + if (tmag5273_avg_table[i] == val) + break; + } + if (i == ARRAY_SIZE(tmag5273_avg_table)) + return -EINVAL; + data->conv_avg = val; + + return regmap_update_bits(data->map, TMAG5273_DEVICE_CONFIG_1, + TMAG5273_AVG_MODE_MASK, + FIELD_PREP(TMAG5273_AVG_MODE_MASK, i)); +} + +static int tmag5273_write_scale(struct tmag5273_data *data, int scale_micro) +{ + u32 value; + int i; + + for (i = 0; i < ARRAY_SIZE(tmag5273_scale[0]); i++) { + if (tmag5273_scale[data->version][i].micro == scale_micro) + break; + } + if (i == ARRAY_SIZE(tmag5273_scale[0])) + return -EINVAL; + data->scale_index = i; + + if (data->scale_index == MAGN_RANGE_LOW) + value = 0; + else + value = TMAG5273_Z_RANGE_MASK | TMAG5273_X_Y_RANGE_MASK; + + return regmap_update_bits(data->map, TMAG5273_SENSOR_CONFIG_2, + TMAG5273_Z_RANGE_MASK | TMAG5273_X_Y_RANGE_MASK, value); +} + +static int tmag5273_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + struct tmag5273_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals = tmag5273_avg_table; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(tmag5273_avg_table); + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_MAGN: + *type = IIO_VAL_INT_PLUS_MICRO; + *vals = (int *)tmag5273_scale[data->version]; + *length = ARRAY_SIZE(tmag5273_scale[data->version]) * + MAGN_RANGE_NUM; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static int tmag5273_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, int *val, + int *val2, long mask) +{ + struct tmag5273_data *data = iio_priv(indio_dev); + s16 t, x, y, z; + u16 angle, magnitude; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + case IIO_CHAN_INFO_RAW: + ret = pm_runtime_resume_and_get(data->dev); + if (ret < 0) + return ret; + + ret = tmag5273_get_measure(data, &t, &x, &y, &z, &angle, &magnitude); + if (ret) + return ret; + + pm_runtime_mark_last_busy(data->dev); + pm_runtime_put_autosuspend(data->dev); + + switch (chan->address) { + case TEMPERATURE: + *val = t; + return IIO_VAL_INT; + case AXIS_X: + *val = x; + return IIO_VAL_INT; + case AXIS_Y: + *val = y; + return IIO_VAL_INT; + case AXIS_Z: + *val = z; + return IIO_VAL_INT; + case ANGLE: + *val = angle; + return IIO_VAL_INT; + case MAGNITUDE: + *val = magnitude; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_TEMP: + /* + * Convert device specific value to millicelsius. + * Resolution from the sensor is 60.1 LSB/celsius and + * the reference value at 25 celsius is 17508 LSBs. + */ + *val = 10000; + *val2 = 601; + return IIO_VAL_FRACTIONAL; + case IIO_MAGN: + /* Magnetic resolution in uT */ + *val = 0; + *val2 = tmag5273_scale[data->version] + [data->scale_index].micro; + return IIO_VAL_INT_PLUS_MICRO; + case IIO_ANGL: + /* + * Angle is in degrees and has four fractional bits, + * therefore use 1/16 * pi/180 to convert to radians. + */ + *val = 1000; + *val2 = 916732; + return IIO_VAL_FRACTIONAL; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_OFFSET: + switch (chan->type) { + case IIO_TEMP: + *val = -266314; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val = data->conv_avg; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static int tmag5273_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + struct tmag5273_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return tmag5273_write_osr(data, val); + case IIO_CHAN_INFO_SCALE: + switch (chan->type) { + case IIO_MAGN: + if (val) + return -EINVAL; + return tmag5273_write_scale(data, val2); + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +#define TMAG5273_AXIS_CHANNEL(axis, index) \ + { \ + .type = IIO_MAGN, \ + .modified = 1, \ + .channel2 = IIO_MOD_##axis, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_shared_by_all_available = \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .address = index, \ + .scan_index = index, \ + .scan_type = { \ + .sign = 's', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_CPU, \ + }, \ + } + +static const struct iio_chan_spec tmag5273_channels[] = { + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .address = TEMPERATURE, + .scan_index = TEMPERATURE, + .scan_type = { + .sign = 'u', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + }, + TMAG5273_AXIS_CHANNEL(X, AXIS_X), + TMAG5273_AXIS_CHANNEL(Y, AXIS_Y), + TMAG5273_AXIS_CHANNEL(Z, AXIS_Z), + { + .type = IIO_ANGL, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .address = ANGLE, + .scan_index = ANGLE, + .scan_type = { + .sign = 'u', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + }, + { + .type = IIO_DISTANCE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_all = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .address = MAGNITUDE, + .scan_index = MAGNITUDE, + .scan_type = { + .sign = 'u', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(6), +}; + +static const struct iio_info tmag5273_info = { + .read_avail = tmag5273_read_avail, + .read_raw = tmag5273_read_raw, + .write_raw = tmag5273_write_raw, +}; + +static bool tmag5273_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg >= TMAG5273_T_MSB_RESULT && reg <= TMAG5273_MAGNITUDE_RESULT; +} + +static const struct regmap_config tmag5273_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = TMAG5273_MAX_REG, + .volatile_reg = tmag5273_volatile_reg, +}; + +static int tmag5273_set_operating_mode(struct tmag5273_data *data, + unsigned int val) +{ + return regmap_write(data->map, TMAG5273_DEVICE_CONFIG_2, val); +} + +static void tmag5273_read_device_property(struct tmag5273_data *data) +{ + struct device *dev = data->dev; + const char *str; + int ret; + + data->angle_measurement = TMAG5273_ANGLE_EN_X_Y; + + ret = device_property_read_string(dev, "ti,angle-measurement", &str); + if (ret) + return; + + ret = match_string(tmag5273_angle_names, + ARRAY_SIZE(tmag5273_angle_names), str); + if (ret >= 0) + data->angle_measurement = ret; +} + +static void tmag5273_wake_up(struct tmag5273_data *data) +{ + int val; + + /* Wake up the chip by sending a dummy I2C command */ + regmap_read(data->map, TMAG5273_DEVICE_ID, &val); + /* + * Time to go to stand-by mode from sleep mode is 50us + * typically, during this time no I2C access is possible. + */ + usleep_range(80, 200); +} + +static int tmag5273_chip_init(struct tmag5273_data *data) +{ + int ret; + + ret = regmap_write(data->map, TMAG5273_DEVICE_CONFIG_1, + TMAG5273_AVG_32_MODE); + if (ret) + return ret; + data->conv_avg = 32; + + ret = regmap_write(data->map, TMAG5273_DEVICE_CONFIG_2, + TMAG5273_OP_MODE_CONT); + if (ret) + return ret; + + ret = regmap_write(data->map, TMAG5273_SENSOR_CONFIG_1, + FIELD_PREP(TMAG5273_MAG_CH_EN_MASK, + TMAG5273_MAG_CH_EN_X_Y_Z)); + if (ret) + return ret; + + ret = regmap_write(data->map, TMAG5273_SENSOR_CONFIG_2, + FIELD_PREP(TMAG5273_ANGLE_EN_MASK, + data->angle_measurement)); + if (ret) + return ret; + data->scale_index = MAGN_RANGE_LOW; + + return regmap_write(data->map, TMAG5273_T_CONFIG, TMAG5273_T_CH_EN); +} + +static int tmag5273_check_device_id(struct tmag5273_data *data) +{ + __le16 devid; + int val, ret; + + ret = regmap_read(data->map, TMAG5273_DEVICE_ID, &val); + if (ret) + return dev_err_probe(data->dev, ret, "failed to power on device\n"); + data->version = FIELD_PREP(TMAG5273_VERSION_MASK, val); + + ret = regmap_bulk_read(data->map, TMAG5273_MANUFACTURER_ID_LSB, &devid, + sizeof(devid)); + if (ret) + return dev_err_probe(data->dev, ret, "failed to read device ID\n"); + data->devid = le16_to_cpu(devid); + + switch (data->devid) { + case TMAG5273_MANUFACTURER_ID: + /* + * The device name matches the orderable part number. 'x' stands + * for A, B, C or D devices, which have different I2C addresses. + * Versions 1 or 2 (0 and 3 is reserved) stands for different + * magnetic strengths. + */ + snprintf(data->name, sizeof(data->name), "tmag5273x%1u", data->version); + if (data->version < 1 || data->version > 2) + dev_warn(data->dev, "Unsupported device %s\n", data->name); + return 0; + default: + /* + * Only print warning in case of unknown device ID to allow + * fallback compatible in device tree. + */ + dev_warn(data->dev, "Unknown device ID 0x%x\n", data->devid); + return 0; + } +} + +static void tmag5273_power_down(void *data) +{ + tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_SLEEP); +} + +static int tmag5273_probe(struct i2c_client *i2c) +{ + struct device *dev = &i2c->dev; + struct tmag5273_data *data; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + data->dev = dev; + i2c_set_clientdata(i2c, indio_dev); + + data->map = devm_regmap_init_i2c(i2c, &tmag5273_regmap_config); + if (IS_ERR(data->map)) + return dev_err_probe(dev, PTR_ERR(data->map), + "failed to allocate register map\n"); + + mutex_init(&data->lock); + + ret = devm_regulator_get_enable(dev, "vcc"); + if (ret) + return dev_err_probe(dev, ret, "failed to enable regulator\n"); + + tmag5273_wake_up(data); + + ret = tmag5273_check_device_id(data); + if (ret) + return ret; + + ret = tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_CONT); + if (ret) + return dev_err_probe(dev, ret, "failed to power on device\n"); + + /* + * Register powerdown deferred callback which suspends the chip + * after module unloaded. + * + * TMAG5273 should be in SUSPEND mode in the two cases: + * 1) When driver is loaded, but we do not have any data or + * configuration requests to it (we are solving it using + * autosuspend feature). + * 2) When driver is unloaded and device is not used (devm action is + * used in this case). + */ + ret = devm_add_action_or_reset(dev, tmag5273_power_down, data); + if (ret) + return dev_err_probe(dev, ret, "failed to add powerdown action\n"); + + ret = pm_runtime_set_active(dev); + if (ret < 0) + return ret; + + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + pm_runtime_get_noresume(dev); + pm_runtime_set_autosuspend_delay(dev, TMAG5273_AUTOSLEEP_DELAY_MS); + pm_runtime_use_autosuspend(dev); + + tmag5273_read_device_property(data); + + ret = tmag5273_chip_init(data); + if (ret) + return dev_err_probe(dev, ret, "failed to init device\n"); + + indio_dev->info = &tmag5273_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->name = data->name; + indio_dev->channels = tmag5273_channels; + indio_dev->num_channels = ARRAY_SIZE(tmag5273_channels); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return dev_err_probe(dev, ret, "device register failed\n"); + + return 0; +} + +static int tmag5273_runtime_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct tmag5273_data *data = iio_priv(indio_dev); + int ret; + + ret = tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_SLEEP); + if (ret) + dev_err(dev, "failed to power off device (%pe)\n", ERR_PTR(ret)); + + return ret; +} + +static int tmag5273_runtime_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct tmag5273_data *data = iio_priv(indio_dev); + int ret; + + tmag5273_wake_up(data); + + ret = tmag5273_set_operating_mode(data, TMAG5273_OP_MODE_CONT); + if (ret) + dev_err(dev, "failed to power on device (%pe)\n", ERR_PTR(ret)); + + return ret; +} + +static DEFINE_RUNTIME_DEV_PM_OPS(tmag5273_pm_ops, + tmag5273_runtime_suspend, tmag5273_runtime_resume, + NULL); + +static const struct i2c_device_id tmag5273_id[] = { + { "tmag5273" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, tmag5273_id); + +static const struct of_device_id tmag5273_of_match[] = { + { .compatible = "ti,tmag5273" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tmag5273_of_match); + +static struct i2c_driver tmag5273_driver = { + .driver = { + .name = "tmag5273", + .of_match_table = tmag5273_of_match, + .pm = pm_ptr(&tmag5273_pm_ops), + }, + .probe_new = tmag5273_probe, + .id_table = tmag5273_id, +}; +module_i2c_driver(tmag5273_driver); + +MODULE_DESCRIPTION("TI TMAG5273 Low-Power Linear 3D Hall-Effect Sensor driver"); +MODULE_AUTHOR("Gerald Loacker "); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/pressure/ms5611.h b/drivers/iio/pressure/ms5611.h index 550b75b7186f..a78acd3fb18f 100644 --- a/drivers/iio/pressure/ms5611.h +++ b/drivers/iio/pressure/ms5611.h @@ -13,8 +13,6 @@ #include #include -struct regulator; - #define MS5611_RESET 0x1e #define MS5611_READ_ADC 0x00 #define MS5611_READ_PROM_WORD 0xA0 @@ -52,11 +50,9 @@ struct ms5611_state { int (*compensate_temp_and_pressure)(struct ms5611_state *st, s32 *temp, s32 *pressure); - struct regulator *vdd; }; int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, const char *name, int type); -void ms5611_remove(struct iio_dev *indio_dev); #endif /* _MS5611_H */ diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c index c564a1d6cafe..627497e61a63 100644 --- a/drivers/iio/pressure/ms5611_core.c +++ b/drivers/iio/pressure/ms5611_core.c @@ -380,40 +380,21 @@ static const struct iio_info ms5611_info = { static int ms5611_init(struct iio_dev *indio_dev) { int ret; - struct ms5611_state *st = iio_priv(indio_dev); /* Enable attached regulator if any. */ - st->vdd = devm_regulator_get(indio_dev->dev.parent, "vdd"); - if (IS_ERR(st->vdd)) - return PTR_ERR(st->vdd); - - ret = regulator_enable(st->vdd); - if (ret) { - dev_err(indio_dev->dev.parent, - "failed to enable Vdd supply: %d\n", ret); + ret = devm_regulator_get_enable(indio_dev->dev.parent, "vdd"); + if (ret) return ret; - } ret = ms5611_reset(indio_dev); if (ret < 0) - goto err_regulator_disable; + return ret; ret = ms5611_read_prom(indio_dev); if (ret < 0) - goto err_regulator_disable; + return ret; return 0; - -err_regulator_disable: - regulator_disable(st->vdd); - return ret; -} - -static void ms5611_fini(const struct iio_dev *indio_dev) -{ - const struct ms5611_state *st = iio_priv(indio_dev); - - regulator_disable(st->vdd); } int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, @@ -453,37 +434,23 @@ int ms5611_probe(struct iio_dev *indio_dev, struct device *dev, if (ret < 0) return ret; - ret = iio_triggered_buffer_setup(indio_dev, NULL, + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, ms5611_trigger_handler, NULL); if (ret < 0) { dev_err(dev, "iio triggered buffer setup failed\n"); - goto err_fini; + return ret; } - ret = iio_device_register(indio_dev); + ret = devm_iio_device_register(dev, indio_dev); if (ret < 0) { dev_err(dev, "unable to register iio device\n"); - goto err_buffer_cleanup; + return ret; } return 0; - -err_buffer_cleanup: - iio_triggered_buffer_cleanup(indio_dev); -err_fini: - ms5611_fini(indio_dev); - return ret; } EXPORT_SYMBOL_NS(ms5611_probe, IIO_MS5611); -void ms5611_remove(struct iio_dev *indio_dev) -{ - iio_device_unregister(indio_dev); - iio_triggered_buffer_cleanup(indio_dev); - ms5611_fini(indio_dev); -} -EXPORT_SYMBOL_NS(ms5611_remove, IIO_MS5611); - MODULE_AUTHOR("Tomasz Duszynski "); MODULE_DESCRIPTION("MS5611 core driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/pressure/ms5611_i2c.c b/drivers/iio/pressure/ms5611_i2c.c index caf882497656..e3c68a3ed76a 100644 --- a/drivers/iio/pressure/ms5611_i2c.c +++ b/drivers/iio/pressure/ms5611_i2c.c @@ -105,11 +105,6 @@ static int ms5611_i2c_probe(struct i2c_client *client) return ms5611_probe(indio_dev, &client->dev, id->name, id->driver_data); } -static void ms5611_i2c_remove(struct i2c_client *client) -{ - ms5611_remove(i2c_get_clientdata(client)); -} - static const struct of_device_id ms5611_i2c_matches[] = { { .compatible = "meas,ms5611" }, { .compatible = "meas,ms5607" }, @@ -131,7 +126,6 @@ static struct i2c_driver ms5611_driver = { }, .id_table = ms5611_id, .probe_new = ms5611_i2c_probe, - .remove = ms5611_i2c_remove, }; module_i2c_driver(ms5611_driver); diff --git a/drivers/iio/pressure/ms5611_spi.c b/drivers/iio/pressure/ms5611_spi.c index a0a7205c9c3a..cc9d1f68c53c 100644 --- a/drivers/iio/pressure/ms5611_spi.c +++ b/drivers/iio/pressure/ms5611_spi.c @@ -107,11 +107,6 @@ static int ms5611_spi_probe(struct spi_device *spi) spi_get_device_id(spi)->driver_data); } -static void ms5611_spi_remove(struct spi_device *spi) -{ - ms5611_remove(spi_get_drvdata(spi)); -} - static const struct of_device_id ms5611_spi_matches[] = { { .compatible = "meas,ms5611" }, { .compatible = "meas,ms5607" }, @@ -133,7 +128,6 @@ static struct spi_driver ms5611_driver = { }, .id_table = ms5611_id, .probe = ms5611_spi_probe, - .remove = ms5611_spi_remove, }; module_spi_driver(ms5611_driver); diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 25debded65a8..0f392f59b135 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -1079,15 +1079,19 @@ void icc_provider_del(struct icc_provider *provider) } EXPORT_SYMBOL_GPL(icc_provider_del); +static const struct of_device_id __maybe_unused ignore_list[] = { + { .compatible = "qcom,sc7180-ipa-virt" }, + { .compatible = "qcom,sc8180x-ipa-virt" }, + { .compatible = "qcom,sdx55-ipa-virt" }, + { .compatible = "qcom,sm8150-ipa-virt" }, + { .compatible = "qcom,sm8250-ipa-virt" }, + {} +}; + static int of_count_icc_providers(struct device_node *np) { struct device_node *child; int count = 0; - const struct of_device_id __maybe_unused ignore_list[] = { - { .compatible = "qcom,sc7180-ipa-virt" }, - { .compatible = "qcom,sdx55-ipa-virt" }, - {} - }; for_each_available_child_of_node(np, child) { if (of_property_read_bool(child, "#interconnect-cells") && diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig index cd689b782f97..92d65c7bda23 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -92,6 +92,15 @@ config INTERCONNECT_QCOM_RPMH_POSSIBLE config INTERCONNECT_QCOM_RPMH tristate +config INTERCONNECT_QCOM_SA8775P + tristate "Qualcomm SA8775P interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sa8775p-based + platforms. + config INTERCONNECT_QCOM_SC7180 tristate "Qualcomm SC7180 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE @@ -137,6 +146,15 @@ config INTERCONNECT_QCOM_SDM660 This is a driver for the Qualcomm Network-on-Chip on sdm660-based platforms. +config INTERCONNECT_QCOM_SDM670 + tristate "Qualcomm SDM670 interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on sdm670-based + platforms. + config INTERCONNECT_QCOM_SDM845 tristate "Qualcomm SDM845 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 3fd4c2713c4a..ab988926433c 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -13,11 +13,13 @@ qnoc-qcm2290-objs := qcm2290.o qnoc-qcs404-objs := qcs404.o qnoc-qdu1000-objs := qdu1000.o icc-rpmh-obj := icc-rpmh.o +qnoc-sa8775p-objs := sa8775p.o qnoc-sc7180-objs := sc7180.o qnoc-sc7280-objs := sc7280.o qnoc-sc8180x-objs := sc8180x.o qnoc-sc8280xp-objs := sc8280xp.o qnoc-sdm660-objs := sdm660.o +qnoc-sdm670-objs := sdm670.o qnoc-sdm845-objs := sdm845.o qnoc-sdx55-objs := sdx55.o qnoc-sdx65-objs := sdx65.o @@ -39,11 +41,13 @@ obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o +obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o obj-$(CONFIG_INTERCONNECT_QCOM_SC8280XP) += qnoc-sc8280xp.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o +obj-$(CONFIG_INTERCONNECT_QCOM_SDM670) += qnoc-sdm670.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c new file mode 100644 index 000000000000..da21cc31a580 --- /dev/null +++ b/drivers/interconnect/qcom/sa8775p.c @@ -0,0 +1,2541 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +#define SA8775P_MASTER_GPU_TCU 0 +#define SA8775P_MASTER_PCIE_TCU 1 +#define SA8775P_MASTER_SYS_TCU 2 +#define SA8775P_MASTER_APPSS_PROC 3 +#define SA8775P_MASTER_LLCC 4 +#define SA8775P_MASTER_CNOC_LPASS_AG_NOC 5 +#define SA8775P_MASTER_GIC_AHB 6 +#define SA8775P_MASTER_CDSP_NOC_CFG 7 +#define SA8775P_MASTER_CDSPB_NOC_CFG 8 +#define SA8775P_MASTER_QDSS_BAM 9 +#define SA8775P_MASTER_QUP_0 10 +#define SA8775P_MASTER_QUP_1 11 +#define SA8775P_MASTER_QUP_2 12 +#define SA8775P_MASTER_A1NOC_SNOC 13 +#define SA8775P_MASTER_A2NOC_SNOC 14 +#define SA8775P_MASTER_CAMNOC_HF 15 +#define SA8775P_MASTER_CAMNOC_ICP 16 +#define SA8775P_MASTER_CAMNOC_SF 17 +#define SA8775P_MASTER_COMPUTE_NOC 18 +#define SA8775P_MASTER_COMPUTE_NOC_1 19 +#define SA8775P_MASTER_CNOC_A2NOC 20 +#define SA8775P_MASTER_CNOC_DC_NOC 21 +#define SA8775P_MASTER_GEM_NOC_CFG 22 +#define SA8775P_MASTER_GEM_NOC_CNOC 23 +#define SA8775P_MASTER_GEM_NOC_PCIE_SNOC 24 +#define SA8775P_MASTER_GPDSP_SAIL 25 +#define SA8775P_MASTER_GFX3D 26 +#define SA8775P_MASTER_LPASS_ANOC 27 +#define SA8775P_MASTER_MDP0 28 +#define SA8775P_MASTER_MDP1 29 +#define SA8775P_MASTER_MDP_CORE1_0 30 +#define SA8775P_MASTER_MDP_CORE1_1 31 +#define SA8775P_MASTER_MNOC_HF_MEM_NOC 32 +#define SA8775P_MASTER_CNOC_MNOC_HF_CFG 33 +#define SA8775P_MASTER_MNOC_SF_MEM_NOC 34 +#define SA8775P_MASTER_CNOC_MNOC_SF_CFG 35 +#define SA8775P_MASTER_ANOC_PCIE_GEM_NOC 36 +#define SA8775P_MASTER_SNOC_CFG 37 +#define SA8775P_MASTER_SNOC_GC_MEM_NOC 38 +#define SA8775P_MASTER_SNOC_SF_MEM_NOC 39 +#define SA8775P_MASTER_VIDEO_P0 40 +#define SA8775P_MASTER_VIDEO_P1 41 +#define SA8775P_MASTER_VIDEO_PROC 42 +#define SA8775P_MASTER_VIDEO_V_PROC 43 +#define SA8775P_MASTER_QUP_CORE_0 44 +#define SA8775P_MASTER_QUP_CORE_1 45 +#define SA8775P_MASTER_QUP_CORE_2 46 +#define SA8775P_MASTER_QUP_CORE_3 47 +#define SA8775P_MASTER_CRYPTO_CORE0 48 +#define SA8775P_MASTER_CRYPTO_CORE1 49 +#define SA8775P_MASTER_DSP0 50 +#define SA8775P_MASTER_DSP1 51 +#define SA8775P_MASTER_IPA 52 +#define SA8775P_MASTER_LPASS_PROC 53 +#define SA8775P_MASTER_CDSP_PROC 54 +#define SA8775P_MASTER_CDSP_PROC_B 55 +#define SA8775P_MASTER_PIMEM 56 +#define SA8775P_MASTER_QUP_3 57 +#define SA8775P_MASTER_EMAC 58 +#define SA8775P_MASTER_EMAC_1 59 +#define SA8775P_MASTER_GIC 60 +#define SA8775P_MASTER_PCIE_0 61 +#define SA8775P_MASTER_PCIE_1 62 +#define SA8775P_MASTER_QDSS_ETR_0 63 +#define SA8775P_MASTER_QDSS_ETR_1 64 +#define SA8775P_MASTER_SDC 65 +#define SA8775P_MASTER_UFS_CARD 66 +#define SA8775P_MASTER_UFS_MEM 67 +#define SA8775P_MASTER_USB2 68 +#define SA8775P_MASTER_USB3_0 69 +#define SA8775P_MASTER_USB3_1 70 +#define SA8775P_SLAVE_EBI1 512 +#define SA8775P_SLAVE_AHB2PHY_0 513 +#define SA8775P_SLAVE_AHB2PHY_1 514 +#define SA8775P_SLAVE_AHB2PHY_2 515 +#define SA8775P_SLAVE_AHB2PHY_3 516 +#define SA8775P_SLAVE_ANOC_THROTTLE_CFG 517 +#define SA8775P_SLAVE_AOSS 518 +#define SA8775P_SLAVE_APPSS 519 +#define SA8775P_SLAVE_BOOT_ROM 520 +#define SA8775P_SLAVE_CAMERA_CFG 521 +#define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG 522 +#define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG 523 +#define SA8775P_SLAVE_CLK_CTL 524 +#define SA8775P_SLAVE_CDSP_CFG 525 +#define SA8775P_SLAVE_CDSP1_CFG 526 +#define SA8775P_SLAVE_RBCPR_CX_CFG 527 +#define SA8775P_SLAVE_RBCPR_MMCX_CFG 528 +#define SA8775P_SLAVE_RBCPR_MX_CFG 529 +#define SA8775P_SLAVE_CPR_NSPCX 530 +#define SA8775P_SLAVE_CRYPTO_0_CFG 531 +#define SA8775P_SLAVE_CX_RDPM 532 +#define SA8775P_SLAVE_DISPLAY_CFG 533 +#define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG 534 +#define SA8775P_SLAVE_DISPLAY1_CFG 535 +#define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536 +#define SA8775P_SLAVE_EMAC_CFG 537 +#define SA8775P_SLAVE_EMAC1_CFG 538 +#define SA8775P_SLAVE_GP_DSP0_CFG 539 +#define SA8775P_SLAVE_GP_DSP1_CFG 540 +#define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG 541 +#define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG 542 +#define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG 543 +#define SA8775P_SLAVE_GFX3D_CFG 544 +#define SA8775P_SLAVE_HWKM 545 +#define SA8775P_SLAVE_IMEM_CFG 546 +#define SA8775P_SLAVE_IPA_CFG 547 +#define SA8775P_SLAVE_IPC_ROUTER_CFG 548 +#define SA8775P_SLAVE_LLCC_CFG 549 +#define SA8775P_SLAVE_LPASS 550 +#define SA8775P_SLAVE_LPASS_CORE_CFG 551 +#define SA8775P_SLAVE_LPASS_LPI_CFG 552 +#define SA8775P_SLAVE_LPASS_MPU_CFG 553 +#define SA8775P_SLAVE_LPASS_THROTTLE_CFG 554 +#define SA8775P_SLAVE_LPASS_TOP_CFG 555 +#define SA8775P_SLAVE_MX_RDPM 556 +#define SA8775P_SLAVE_MXC_RDPM 557 +#define SA8775P_SLAVE_PCIE_0_CFG 558 +#define SA8775P_SLAVE_PCIE_1_CFG 559 +#define SA8775P_SLAVE_PCIE_RSC_CFG 560 +#define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG 561 +#define SA8775P_SLAVE_PCIE_THROTTLE_CFG 562 +#define SA8775P_SLAVE_PDM 563 +#define SA8775P_SLAVE_PIMEM_CFG 564 +#define SA8775P_SLAVE_PKA_WRAPPER_CFG 565 +#define SA8775P_SLAVE_QDSS_CFG 566 +#define SA8775P_SLAVE_QM_CFG 567 +#define SA8775P_SLAVE_QM_MPU_CFG 568 +#define SA8775P_SLAVE_QUP_0 569 +#define SA8775P_SLAVE_QUP_1 570 +#define SA8775P_SLAVE_QUP_2 571 +#define SA8775P_SLAVE_QUP_3 572 +#define SA8775P_SLAVE_SAIL_THROTTLE_CFG 573 +#define SA8775P_SLAVE_SDC1 574 +#define SA8775P_SLAVE_SECURITY 575 +#define SA8775P_SLAVE_SNOC_THROTTLE_CFG 576 +#define SA8775P_SLAVE_TCSR 577 +#define SA8775P_SLAVE_TLMM 578 +#define SA8775P_SLAVE_TSC_CFG 579 +#define SA8775P_SLAVE_UFS_CARD_CFG 580 +#define SA8775P_SLAVE_UFS_MEM_CFG 581 +#define SA8775P_SLAVE_USB2 582 +#define SA8775P_SLAVE_USB3_0 583 +#define SA8775P_SLAVE_USB3_1 584 +#define SA8775P_SLAVE_VENUS_CFG 585 +#define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG 586 +#define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587 +#define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588 +#define SA8775P_SLAVE_A1NOC_SNOC 589 +#define SA8775P_SLAVE_A2NOC_SNOC 590 +#define SA8775P_SLAVE_DDRSS_CFG 591 +#define SA8775P_SLAVE_GEM_NOC_CNOC 592 +#define SA8775P_SLAVE_GEM_NOC_CFG 593 +#define SA8775P_SLAVE_SNOC_GEM_NOC_GC 594 +#define SA8775P_SLAVE_SNOC_GEM_NOC_SF 595 +#define SA8775P_SLAVE_GP_DSP_SAIL_NOC 596 +#define SA8775P_SLAVE_GPDSP_NOC_CFG 597 +#define SA8775P_SLAVE_HCP_A 598 +#define SA8775P_SLAVE_LLCC 599 +#define SA8775P_SLAVE_MNOC_HF_MEM_NOC 600 +#define SA8775P_SLAVE_MNOC_SF_MEM_NOC 601 +#define SA8775P_SLAVE_CNOC_MNOC_HF_CFG 602 +#define SA8775P_SLAVE_CNOC_MNOC_SF_CFG 603 +#define SA8775P_SLAVE_CDSP_MEM_NOC 604 +#define SA8775P_SLAVE_CDSPB_MEM_NOC 605 +#define SA8775P_SLAVE_HCP_B 606 +#define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 607 +#define SA8775P_SLAVE_PCIE_ANOC_CFG 608 +#define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC 609 +#define SA8775P_SLAVE_SNOC_CFG 610 +#define SA8775P_SLAVE_LPASS_SNOC 611 +#define SA8775P_SLAVE_QUP_CORE_0 612 +#define SA8775P_SLAVE_QUP_CORE_1 613 +#define SA8775P_SLAVE_QUP_CORE_2 614 +#define SA8775P_SLAVE_QUP_CORE_3 615 +#define SA8775P_SLAVE_BOOT_IMEM 616 +#define SA8775P_SLAVE_IMEM 617 +#define SA8775P_SLAVE_PIMEM 618 +#define SA8775P_SLAVE_SERVICE_NSP_NOC 619 +#define SA8775P_SLAVE_SERVICE_NSPB_NOC 620 +#define SA8775P_SLAVE_SERVICE_GEM_NOC_1 621 +#define SA8775P_SLAVE_SERVICE_MNOC_HF 622 +#define SA8775P_SLAVE_SERVICE_MNOC_SF 623 +#define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC 624 +#define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 625 +#define SA8775P_SLAVE_SERVICE_GEM_NOC_2 626 +#define SA8775P_SLAVE_SERVICE_SNOC 627 +#define SA8775P_SLAVE_SERVICE_GEM_NOC 628 +#define SA8775P_SLAVE_SERVICE_GEM_NOC2 629 +#define SA8775P_SLAVE_PCIE_0 630 +#define SA8775P_SLAVE_PCIE_1 631 +#define SA8775P_SLAVE_QDSS_STM 632 +#define SA8775P_SLAVE_TCU 633 + +static struct qcom_icc_node qxm_qup3 = { + .name = "qxm_qup3", + .id = SA8775P_MASTER_QUP_3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emac_0 = { + .name = "xm_emac_0", + .id = SA8775P_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emac_1 = { + .name = "xm_emac_1", + .id = SA8775P_MASTER_EMAC_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SA8775P_MASTER_SDC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SA8775P_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb2_2 = { + .name = "xm_usb2_2", + .id = SA8775P_MASTER_USB2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SA8775P_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SA8775P_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SA8775P_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SA8775P_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SA8775P_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SA8775P_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc_datapath = { + .name = "qnm_cnoc_datapath", + .id = SA8775P_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto_0 = { + .name = "qxm_crypto_0", + .id = SA8775P_MASTER_CRYPTO_CORE0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto_1 = { + .name = "qxm_crypto_1", + .id = SA8775P_MASTER_CRYPTO_CORE1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SA8775P_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 = { + .name = "xm_qdss_etr_0", + .id = SA8775P_MASTER_QDSS_ETR_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 = { + .name = "xm_qdss_etr_1", + .id = SA8775P_MASTER_QDSS_ETR_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SA8775P_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SA8775P_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SA8775P_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = SA8775P_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qup3_core_master = { + .name = "qup3_core_master", + .id = SA8775P_MASTER_QUP_CORE_3, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_QUP_CORE_3 }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SA8775P_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 82, + .links = { SA8775P_SLAVE_AHB2PHY_0, + SA8775P_SLAVE_AHB2PHY_1, + SA8775P_SLAVE_AHB2PHY_2, + SA8775P_SLAVE_AHB2PHY_3, + SA8775P_SLAVE_ANOC_THROTTLE_CFG, + SA8775P_SLAVE_AOSS, + SA8775P_SLAVE_APPSS, + SA8775P_SLAVE_BOOT_ROM, + SA8775P_SLAVE_CAMERA_CFG, + SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, + SA8775P_SLAVE_CLK_CTL, + SA8775P_SLAVE_CDSP_CFG, + SA8775P_SLAVE_CDSP1_CFG, + SA8775P_SLAVE_RBCPR_CX_CFG, + SA8775P_SLAVE_RBCPR_MMCX_CFG, + SA8775P_SLAVE_RBCPR_MX_CFG, + SA8775P_SLAVE_CPR_NSPCX, + SA8775P_SLAVE_CRYPTO_0_CFG, + SA8775P_SLAVE_CX_RDPM, + SA8775P_SLAVE_DISPLAY_CFG, + SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SA8775P_SLAVE_DISPLAY1_CFG, + SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, + SA8775P_SLAVE_EMAC_CFG, + SA8775P_SLAVE_EMAC1_CFG, + SA8775P_SLAVE_GP_DSP0_CFG, + SA8775P_SLAVE_GP_DSP1_CFG, + SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, + SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, + SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, + SA8775P_SLAVE_GFX3D_CFG, + SA8775P_SLAVE_HWKM, + SA8775P_SLAVE_IMEM_CFG, + SA8775P_SLAVE_IPA_CFG, + SA8775P_SLAVE_IPC_ROUTER_CFG, + SA8775P_SLAVE_LPASS, + SA8775P_SLAVE_LPASS_THROTTLE_CFG, + SA8775P_SLAVE_MX_RDPM, + SA8775P_SLAVE_MXC_RDPM, + SA8775P_SLAVE_PCIE_0_CFG, + SA8775P_SLAVE_PCIE_1_CFG, + SA8775P_SLAVE_PCIE_RSC_CFG, + SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, + SA8775P_SLAVE_PCIE_THROTTLE_CFG, + SA8775P_SLAVE_PDM, + SA8775P_SLAVE_PIMEM_CFG, + SA8775P_SLAVE_PKA_WRAPPER_CFG, + SA8775P_SLAVE_QDSS_CFG, + SA8775P_SLAVE_QM_CFG, + SA8775P_SLAVE_QM_MPU_CFG, + SA8775P_SLAVE_QUP_0, + SA8775P_SLAVE_QUP_1, + SA8775P_SLAVE_QUP_2, + SA8775P_SLAVE_QUP_3, + SA8775P_SLAVE_SAIL_THROTTLE_CFG, + SA8775P_SLAVE_SDC1, + SA8775P_SLAVE_SECURITY, + SA8775P_SLAVE_SNOC_THROTTLE_CFG, + SA8775P_SLAVE_TCSR, + SA8775P_SLAVE_TLMM, + SA8775P_SLAVE_TSC_CFG, + SA8775P_SLAVE_UFS_CARD_CFG, + SA8775P_SLAVE_UFS_MEM_CFG, + SA8775P_SLAVE_USB2, + SA8775P_SLAVE_USB3_0, + SA8775P_SLAVE_USB3_1, + SA8775P_SLAVE_VENUS_CFG, + SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, + SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, + SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, + SA8775P_SLAVE_DDRSS_CFG, + SA8775P_SLAVE_GPDSP_NOC_CFG, + SA8775P_SLAVE_CNOC_MNOC_HF_CFG, + SA8775P_SLAVE_CNOC_MNOC_SF_CFG, + SA8775P_SLAVE_PCIE_ANOC_CFG, + SA8775P_SLAVE_SNOC_CFG, + SA8775P_SLAVE_BOOT_IMEM, + SA8775P_SLAVE_IMEM, + SA8775P_SLAVE_PIMEM, + SA8775P_SLAVE_QDSS_STM, + SA8775P_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SA8775P_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SA8775P_SLAVE_PCIE_0, + SA8775P_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc = { + .name = "qnm_cnoc_dc_noc", + .id = SA8775P_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SA8775P_SLAVE_LLCC_CFG, + SA8775P_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SA8775P_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_pcie_tcu = { + .name = "alm_pcie_tcu", + .id = SA8775P_MASTER_PCIE_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SA8775P_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SA8775P_MASTER_APPSS_PROC, + .channels = 4, + .buswidth = 32, + .num_links = 3, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc0 = { + .name = "qnm_cmpnoc0", + .id = SA8775P_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc1 = { + .name = "qnm_cmpnoc1", + .id = SA8775P_MASTER_COMPUTE_NOC_1, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = SA8775P_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 4, + .links = { SA8775P_SLAVE_SERVICE_GEM_NOC_1, + SA8775P_SLAVE_SERVICE_GEM_NOC_2, + SA8775P_SLAVE_SERVICE_GEM_NOC, + SA8775P_SLAVE_SERVICE_GEM_NOC2 + }, +}; + +static struct qcom_icc_node qnm_gpdsp_sail = { + .name = "qnm_gpdsp_sail", + .id = SA8775P_MASTER_GPDSP_SAIL, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SA8775P_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SA8775P_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SA8775P_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SA8775P_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SA8775P_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SA8775P_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SA8775P_SLAVE_GEM_NOC_CNOC, + SA8775P_SLAVE_LLCC, + SA8775P_SLAVE_GEM_NOC_PCIE_CNOC }, +}; + +static struct qcom_icc_node qxm_dsp0 = { + .name = "qxm_dsp0", + .id = SA8775P_MASTER_DSP0, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, +}; + +static struct qcom_icc_node qxm_dsp1 = { + .name = "qxm_dsp1", + .id = SA8775P_MASTER_DSP1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .id = SA8775P_MASTER_CNOC_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 6, + .links = { SA8775P_SLAVE_LPASS_CORE_CFG, + SA8775P_SLAVE_LPASS_LPI_CFG, + SA8775P_SLAVE_LPASS_MPU_CFG, + SA8775P_SLAVE_LPASS_TOP_CFG, + SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, + SA8775P_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node qxm_lpass_dsp = { + .name = "qxm_lpass_dsp", + .id = SA8775P_MASTER_LPASS_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 4, + .links = { SA8775P_SLAVE_LPASS_TOP_CFG, + SA8775P_SLAVE_LPASS_SNOC, + SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, + SA8775P_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SA8775P_MASTER_LLCC, + .channels = 8, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SA8775P_MASTER_CAMNOC_HF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = SA8775P_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = SA8775P_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp0_0 = { + .name = "qnm_mdp0_0", + .id = SA8775P_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp0_1 = { + .name = "qnm_mdp0_1", + .id = SA8775P_MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp1_0 = { + .name = "qnm_mdp1_0", + .id = SA8775P_MASTER_MDP_CORE1_0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mdp1_1 = { + .name = "qnm_mdp1_1", + .id = SA8775P_MASTER_MDP_CORE1_1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_cfg = { + .name = "qnm_mnoc_hf_cfg", + .id = SA8775P_MASTER_CNOC_MNOC_HF_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_SERVICE_MNOC_HF }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_cfg = { + .name = "qnm_mnoc_sf_cfg", + .id = SA8775P_MASTER_CNOC_MNOC_SF_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_SERVICE_MNOC_SF }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SA8775P_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = SA8775P_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SA8775P_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_v_cpu = { + .name = "qnm_video_v_cpu", + .id = SA8775P_MASTER_VIDEO_V_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .id = SA8775P_MASTER_CDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .id = SA8775P_MASTER_CDSP_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nspb_noc_config = { + .name = "qhm_nspb_noc_config", + .id = SA8775P_MASTER_CDSPB_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_SERVICE_NSPB_NOC }, +}; + +static struct qcom_icc_node qxm_nspb = { + .name = "qxm_nspb", + .id = SA8775P_MASTER_CDSP_PROC_B, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SA8775P_MASTER_PCIE_0, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SA8775P_MASTER_PCIE_1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qhm_gic = { + .name = "qhm_gic", + .id = SA8775P_MASTER_GIC_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SA8775P_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SA8775P_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_lpass_noc = { + .name = "qnm_lpass_noc", + .id = SA8775P_MASTER_LPASS_ANOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .id = SA8775P_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SA8775P_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SA8775P_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SA8775P_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SA8775P_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SA8775P_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SA8775P_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SA8775P_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup3_core_slave = { + .name = "qup3_core_slave", + .id = SA8775P_SLAVE_QUP_CORE_3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SA8775P_SLAVE_AHB2PHY_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SA8775P_SLAVE_AHB2PHY_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .id = SA8775P_SLAVE_AHB2PHY_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy3 = { + .name = "qhs_ahb2phy3", + .id = SA8775P_SLAVE_AHB2PHY_3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_anoc_throttle_cfg = { + .name = "qhs_anoc_throttle_cfg", + .id = SA8775P_SLAVE_ANOC_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SA8775P_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SA8775P_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .name = "qhs_boot_rom", + .id = SA8775P_SLAVE_BOOT_ROM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SA8775P_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { + .name = "qhs_camera_nrt_throttle_cfg", + .id = SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { + .name = "qhs_camera_rt_throttle_cfg", + .id = SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SA8775P_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute0_cfg = { + .name = "qhs_compute0_cfg", + .id = SA8775P_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_CDSP_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_compute1_cfg = { + .name = "qhs_compute1_cfg", + .id = SA8775P_SLAVE_CDSP1_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_CDSPB_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SA8775P_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SA8775P_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SA8775P_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_nspcx = { + .name = "qhs_cpr_nspcx", + .id = SA8775P_SLAVE_CPR_NSPCX, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SA8775P_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SA8775P_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display0_cfg = { + .name = "qhs_display0_cfg", + .id = SA8775P_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { + .name = "qhs_display0_rt_throttle_cfg", + .id = SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display1_cfg = { + .name = "qhs_display1_cfg", + .id = SA8775P_SLAVE_DISPLAY1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display1_rt_throttle_cfg = { + .name = "qhs_display1_rt_throttle_cfg", + .id = SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac0_cfg = { + .name = "qhs_emac0_cfg", + .id = SA8775P_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac1_cfg = { + .name = "qhs_emac1_cfg", + .id = SA8775P_SLAVE_EMAC1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gp_dsp0_cfg = { + .name = "qhs_gp_dsp0_cfg", + .id = SA8775P_SLAVE_GP_DSP0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gp_dsp1_cfg = { + .name = "qhs_gp_dsp1_cfg", + .id = SA8775P_SLAVE_GP_DSP1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { + .name = "qhs_gpdsp0_throttle_cfg", + .id = SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = { + .name = "qhs_gpdsp1_throttle_cfg", + .id = SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { + .name = "qhs_gpu_tcu_throttle_cfg", + .id = SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SA8775P_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_hwkm = { + .name = "qhs_hwkm", + .id = SA8775P_SLAVE_HWKM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SA8775P_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SA8775P_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SA8775P_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SA8775P_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_lpass_throttle_cfg = { + .name = "qhs_lpass_throttle_cfg", + .id = SA8775P_SLAVE_LPASS_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .id = SA8775P_SLAVE_MX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mxc_rdpm = { + .name = "qhs_mxc_rdpm", + .id = SA8775P_SLAVE_MXC_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SA8775P_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SA8775P_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_rsc_cfg = { + .name = "qhs_pcie_rsc_cfg", + .id = SA8775P_SLAVE_PCIE_RSC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { + .name = "qhs_pcie_tcu_throttle_cfg", + .id = SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_throttle_cfg = { + .name = "qhs_pcie_throttle_cfg", + .id = SA8775P_SLAVE_PCIE_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SA8775P_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SA8775P_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pke_wrapper_cfg = { + .name = "qhs_pke_wrapper_cfg", + .id = SA8775P_SLAVE_PKA_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SA8775P_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .name = "qhs_qm_cfg", + .id = SA8775P_SLAVE_QM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .name = "qhs_qm_mpu_cfg", + .id = SA8775P_SLAVE_QM_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SA8775P_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SA8775P_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SA8775P_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup3 = { + .name = "qhs_qup3", + .id = SA8775P_SLAVE_QUP_3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sail_throttle_cfg = { + .name = "qhs_sail_throttle_cfg", + .id = SA8775P_SLAVE_SAIL_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SA8775P_SLAVE_SDC1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SA8775P_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_throttle_cfg = { + .name = "qhs_snoc_throttle_cfg", + .id = SA8775P_SLAVE_SNOC_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SA8775P_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SA8775P_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsc_cfg = { + .name = "qhs_tsc_cfg", + .id = SA8775P_SLAVE_TSC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SA8775P_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SA8775P_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb2_0 = { + .name = "qhs_usb2_0", + .id = SA8775P_SLAVE_USB2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SA8775P_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SA8775P_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SA8775P_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { + .name = "qhs_venus_cvp_throttle_cfg", + .id = SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { + .name = "qhs_venus_v_cpu_throttle_cfg", + .id = SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { + .name = "qhs_venus_vcodec_throttle_cfg", + .id = SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SA8775P_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qns_gpdsp_noc_cfg = { + .name = "qns_gpdsp_noc_cfg", + .id = SA8775P_SLAVE_GPDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mnoc_hf_cfg = { + .name = "qns_mnoc_hf_cfg", + .id = SA8775P_SLAVE_CNOC_MNOC_HF_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_CNOC_MNOC_HF_CFG }, +}; + +static struct qcom_icc_node qns_mnoc_sf_cfg = { + .name = "qns_mnoc_sf_cfg", + .id = SA8775P_SLAVE_CNOC_MNOC_SF_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_CNOC_MNOC_SF_CFG }, +}; + +static struct qcom_icc_node qns_pcie_anoc_cfg = { + .name = "qns_pcie_anoc_cfg", + .id = SA8775P_SLAVE_PCIE_ANOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .id = SA8775P_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .id = SA8775P_SLAVE_BOOT_IMEM, + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SA8775P_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SA8775P_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SA8775P_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 16, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SA8775P_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SA8775P_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SA8775P_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SA8775P_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SA8775P_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SA8775P_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = SA8775P_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SA8775P_SLAVE_LLCC, + .channels = 6, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SA8775P_SLAVE_GEM_NOC_PCIE_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SA8775P_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SA8775P_SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SA8775P_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc_2 = { + .name = "srvc_sys_gemnoc_2", + .id = SA8775P_SLAVE_SERVICE_GEM_NOC2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gp_dsp_sail_noc = { + .name = "qns_gp_dsp_sail_noc", + .id = SA8775P_SLAVE_GP_DSP_SAIL_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_GPDSP_SAIL }, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .id = SA8775P_SLAVE_LPASS_CORE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .id = SA8775P_SLAVE_LPASS_LPI_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .id = SA8775P_SLAVE_LPASS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .id = SA8775P_SLAVE_LPASS_TOP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_sysnoc = { + .name = "qns_sysnoc", + .id = SA8775P_SLAVE_LPASS_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_LPASS_ANOC }, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .id = SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .id = SA8775P_SLAVE_SERVICE_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SA8775P_SLAVE_EBI1, + .channels = 8, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SA8775P_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SA8775P_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc_hf = { + .name = "srvc_mnoc_hf", + .id = SA8775P_SLAVE_SERVICE_MNOC_HF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_mnoc_sf = { + .name = "srvc_mnoc_sf", + .id = SA8775P_SLAVE_SERVICE_MNOC_SF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_hcp = { + .name = "qns_hcp", + .id = SA8775P_SLAVE_HCP_A, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .id = SA8775P_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .id = SA8775P_SLAVE_SERVICE_NSP_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nspb_gemnoc = { + .name = "qns_nspb_gemnoc", + .id = SA8775P_SLAVE_CDSPB_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_MASTER_COMPUTE_NOC_1 }, +}; + +static struct qcom_icc_node qns_nspb_hcp = { + .name = "qns_nspb_hcp", + .id = SA8775P_SLAVE_HCP_B, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node service_nspb_noc = { + .name = "service_nspb_noc", + .id = SA8775P_SLAVE_SERVICE_NSPB_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SA8775P_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SA8775P_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SA8775P_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SA8775P_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SA8775P_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SA8775P_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SA8775P_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .num_nodes = 2, + .nodes = { &qxm_crypto_0, &qxm_crypto_1 }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 2, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .num_nodes = 76, + .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_ahb2phy2, &qhs_ahb2phy3, + &qhs_anoc_throttle_cfg, &qhs_aoss, + &qhs_apss, &qhs_boot_rom, + &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, + &qhs_compute0_cfg, &qhs_compute1_cfg, + &qhs_cpr_cx, &qhs_cpr_mmcx, + &qhs_cpr_mx, &qhs_cpr_nspcx, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, + &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg, + &qhs_emac0_cfg, &qhs_emac1_cfg, + &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg, + &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg, + &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg, + &qhs_hwkm, &qhs_imem_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_lpass_cfg, &qhs_lpass_throttle_cfg, + &qhs_mx_rdpm, &qhs_mxc_rdpm, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg, + &qhs_pcie_throttle_cfg, &qhs_pdm, + &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, + &qhs_qdss_cfg, &qhs_qm_cfg, + &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg, + &qhs_sdc1, &qhs_security, + &qhs_snoc_throttle_cfg, &qhs_tcsr, + &qhs_tlmm, &qhs_tsc_cfg, + &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, + &qhs_usb2_0, &qhs_usb3_0, + &qhs_usb3_1, &qhs_venus_cfg, + &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, + &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, + &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, + &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, + &qns_snoc_cfg, &qxs_boot_imem, + &qxs_imem, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_cn2 = { + .name = "CN2", + .num_nodes = 4, + .nodes = { &qhs_qup0, &qhs_qup1, + &qhs_qup2, &qhs_qup3 }, +}; + +static struct qcom_icc_bcm bcm_cn3 = { + .name = "CN3", + .num_nodes = 2, + .nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_gna0 = { + .name = "GNA0", + .num_nodes = 1, + .nodes = { &qxm_dsp0 }, +}; + +static struct qcom_icc_bcm bcm_gnb0 = { + .name = "GNB0", + .num_nodes = 1, + .nodes = { &qxm_dsp1 }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 5, + .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, + &qnm_mdp0_1, &qnm_mdp1_0, + &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .num_nodes = 7, + .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, + &qnm_video0, &qnm_video1, + &qnm_video_cvp, &qnm_video_v_cpu, + &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_nsa0 = { + .name = "NSA0", + .num_nodes = 2, + .nodes = { &qns_hcp, &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_nsa1 = { + .name = "NSA1", + .num_nodes = 1, + .nodes = { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_nsb0 = { + .name = "NSB0", + .num_nodes = 2, + .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp }, +}; + +static struct qcom_icc_bcm bcm_nsb1 = { + .name = "NSB1", + .num_nodes = 1, + .nodes = { &qxm_nspb }, +}; + +static struct qcom_icc_bcm bcm_pci0 = { + .name = "PCI0", + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 = { + .name = "QUP1", + .vote_scale = 1, + .num_nodes = 1, + .nodes = { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 = { + .name = "QUP2", + .vote_scale = 1, + .num_nodes = 2, + .nodes = { &qup2_core_slave, &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .num_nodes = 2, + .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .num_nodes = 2, + .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .num_nodes = 2, + .nodes = { &qns_sysnoc, &qnm_lpass_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm *aggre1_noc_bcms[] = { + &bcm_sn3, +}; + +static struct qcom_icc_node *aggre1_noc_nodes[] = { + [MASTER_QUP_3] = &qxm_qup3, + [MASTER_EMAC] = &xm_emac_0, + [MASTER_EMAC_1] = &xm_emac_1, + [MASTER_SDC] = &xm_sdc1, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [MASTER_USB2] = &xm_usb2_2, + [MASTER_USB3_0] = &xm_usb3_0, + [MASTER_USB3_1] = &xm_usb3_1, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, +}; + +static const struct qcom_icc_desc sa8775p_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm *aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_sn4, +}; + +static struct qcom_icc_node *aggre2_noc_nodes[] = { + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_QUP_0] = &qhm_qup0, + [MASTER_QUP_1] = &qhm_qup1, + [MASTER_QUP_2] = &qhm_qup2, + [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, + [MASTER_CRYPTO_CORE0] = &qxm_crypto_0, + [MASTER_CRYPTO_CORE1] = &qxm_crypto_1, + [MASTER_IPA] = &qxm_ipa, + [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, + [MASTER_UFS_CARD] = &xm_ufs_card, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, +}; + +static const struct qcom_icc_desc sa8775p_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm *clk_virt_bcms[] = { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, +}; + +static struct qcom_icc_node *clk_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [MASTER_QUP_CORE_3] = &qup3_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, + [SLAVE_QUP_CORE_3] = &qup3_core_slave, +}; + +static const struct qcom_icc_desc sa8775p_clk_virt = { + .nodes = clk_virt_nodes, + .num_nodes = ARRAY_SIZE(clk_virt_nodes), + .bcms = clk_virt_bcms, + .num_bcms = ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm *config_noc_bcms[] = { + &bcm_cn0, + &bcm_cn1, + &bcm_cn2, + &bcm_cn3, + &bcm_sn2, + &bcm_sn10, +}; + +static struct qcom_icc_node *config_noc_nodes[] = { + [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, + [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, + [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, + [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_BOOT_ROM] = &qhs_boot_rom, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, + [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, + [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, + [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] = &qhs_cx_rdpm, + [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, + [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg, + [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, + [SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg, + [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, + [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, + [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg, + [SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg, + [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg, + [SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg, + [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg, + [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_HWKM] = &qhs_hwkm, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, + [SLAVE_LPASS] = &qhs_lpass_cfg, + [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg, + [SLAVE_MX_RDPM] = &qhs_mx_rdpm, + [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, + [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, + [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, + [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg, + [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_QM_CFG] = &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, + [SLAVE_QUP_0] = &qhs_qup0, + [SLAVE_QUP_1] = &qhs_qup1, + [SLAVE_QUP_2] = &qhs_qup2, + [SLAVE_QUP_3] = &qhs_qup3, + [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg, + [SLAVE_SDC1] = &qhs_sdc1, + [SLAVE_SECURITY] = &qhs_security, + [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM] = &qhs_tlmm, + [SLAVE_TSC_CFG] = &qhs_tsc_cfg, + [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB2] = &qhs_usb2_0, + [SLAVE_USB3_0] = &qhs_usb3_0, + [SLAVE_USB3_1] = &qhs_usb3_1, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, + [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg, + [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg, + [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, + [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg, + [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg, + [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, + [SLAVE_SNOC_CFG] = &qns_snoc_cfg, + [SLAVE_BOOT_IMEM] = &qxs_boot_imem, + [SLAVE_IMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_PCIE_0] = &xs_pcie_0, + [SLAVE_PCIE_1] = &xs_pcie_1, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, +}; + +static const struct qcom_icc_desc sa8775p_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm *dc_noc_bcms[] = { +}; + +static struct qcom_icc_node *dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, + [SLAVE_LLCC_CFG] = &qhs_llcc, + [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, +}; + +static const struct qcom_icc_desc sa8775p_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), + .bcms = dc_noc_bcms, + .num_bcms = ARRAY_SIZE(dc_noc_bcms), +}; + +static struct qcom_icc_bcm *gem_noc_bcms[] = { + &bcm_sh0, + &bcm_sh2, +}; + +static struct qcom_icc_node *gem_noc_nodes[] = { + [MASTER_GPU_TCU] = &alm_gpu_tcu, + [MASTER_PCIE_TCU] = &alm_pcie_tcu, + [MASTER_SYS_TCU] = &alm_sys_tcu, + [MASTER_APPSS_PROC] = &chm_apps, + [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, + [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, + [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, + [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail, + [MASTER_GFX3D] = &qnm_gpu, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, + [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, + [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, + [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, + [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, +}; + +static const struct qcom_icc_desc sa8775p_gem_noc = { + .nodes = gem_noc_nodes, + .num_nodes = ARRAY_SIZE(gem_noc_nodes), + .bcms = gem_noc_bcms, + .num_bcms = ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = { + &bcm_gna0, + &bcm_gnb0, +}; + +static struct qcom_icc_node *gpdsp_anoc_nodes[] = { + [MASTER_DSP0] = &qxm_dsp0, + [MASTER_DSP1] = &qxm_dsp1, + [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, +}; + +static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { + .nodes = gpdsp_anoc_nodes, + .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), + .bcms = gpdsp_anoc_bcms, + .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms), +}; + +static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { + &bcm_sn9, +}; + +static struct qcom_icc_node *lpass_ag_noc_nodes[] = { + [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, + [MASTER_LPASS_PROC] = &qxm_lpass_dsp, + [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, + [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, + [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, + [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, + [SLAVE_LPASS_SNOC] = &qns_sysnoc, + [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, + [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, +}; + +static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { + .nodes = lpass_ag_noc_nodes, + .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), + .bcms = lpass_ag_noc_bcms, + .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), +}; + +static struct qcom_icc_bcm *mc_virt_bcms[] = { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node *mc_virt_nodes[] = { + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI1] = &ebi, +}; + +static const struct qcom_icc_desc sa8775p_mc_virt = { + .nodes = mc_virt_nodes, + .num_nodes = ARRAY_SIZE(mc_virt_nodes), + .bcms = mc_virt_bcms, + .num_bcms = ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm *mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node *mmss_noc_nodes[] = { + [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, + [MASTER_MDP0] = &qnm_mdp0_0, + [MASTER_MDP1] = &qnm_mdp0_1, + [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, + [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, + [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg, + [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg, + [MASTER_VIDEO_P0] = &qnm_video0, + [MASTER_VIDEO_P1] = &qnm_video1, + [MASTER_VIDEO_PROC] = &qnm_video_cvp, + [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, + [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, +}; + +static const struct qcom_icc_desc sa8775p_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm *nspa_noc_bcms[] = { + &bcm_nsa0, + &bcm_nsa1, +}; + +static struct qcom_icc_node *nspa_noc_nodes[] = { + [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, + [MASTER_CDSP_PROC] = &qxm_nsp, + [SLAVE_HCP_A] = &qns_hcp, + [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, + [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, +}; + +static const struct qcom_icc_desc sa8775p_nspa_noc = { + .nodes = nspa_noc_nodes, + .num_nodes = ARRAY_SIZE(nspa_noc_nodes), + .bcms = nspa_noc_bcms, + .num_bcms = ARRAY_SIZE(nspa_noc_bcms), +}; + +static struct qcom_icc_bcm *nspb_noc_bcms[] = { + &bcm_nsb0, + &bcm_nsb1, +}; + +static struct qcom_icc_node *nspb_noc_nodes[] = { + [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, + [MASTER_CDSP_PROC_B] = &qxm_nspb, + [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, + [SLAVE_HCP_B] = &qns_nspb_hcp, + [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, +}; + +static const struct qcom_icc_desc sa8775p_nspb_noc = { + .nodes = nspb_noc_nodes, + .num_nodes = ARRAY_SIZE(nspb_noc_nodes), + .bcms = nspb_noc_bcms, + .num_bcms = ARRAY_SIZE(nspb_noc_bcms), +}; + +static struct qcom_icc_bcm *pcie_anoc_bcms[] = { + &bcm_pci0, +}; + +static struct qcom_icc_node *pcie_anoc_nodes[] = { + [MASTER_PCIE_0] = &xm_pcie3_0, + [MASTER_PCIE_1] = &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, +}; + +static const struct qcom_icc_desc sa8775p_pcie_anoc = { + .nodes = pcie_anoc_nodes, + .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), + .bcms = pcie_anoc_bcms, + .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm *system_noc_bcms[] = { + &bcm_sn0, + &bcm_sn1, + &bcm_sn3, + &bcm_sn4, + &bcm_sn9, +}; + +static struct qcom_icc_node *system_noc_nodes[] = { + [MASTER_GIC_AHB] = &qhm_gic, + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_LPASS_ANOC] = &qnm_lpass_noc, + [MASTER_SNOC_CFG] = &qnm_snoc_cfg, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, +}; + +static const struct qcom_icc_desc sa8775p_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, }, + { .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, }, + { .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, }, + { .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, }, + { .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, }, + { .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, }, + { .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, }, + { .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, }, + { .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, }, + { .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, }, + { .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, }, + { .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, }, + { .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, }, + { .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sa8775p", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h index c6212a10c2f6..7a2b3eb00923 100644 --- a/drivers/interconnect/qcom/sc7180.h +++ b/drivers/interconnect/qcom/sc7180.h @@ -11,7 +11,7 @@ #define SC7180_MASTER_APPSS_PROC 0 #define SC7180_MASTER_SYS_TCU 1 #define SC7180_MASTER_NPU_SYS 2 -#define SC7180_MASTER_IPA_CORE 3 +/* 3 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define SC7180_MASTER_LLCC 4 #define SC7180_MASTER_A1NOC_CFG 5 #define SC7180_MASTER_A2NOC_CFG 6 @@ -58,7 +58,7 @@ #define SC7180_MASTER_USB3 47 #define SC7180_MASTER_EMMC 48 #define SC7180_SLAVE_EBI1 49 -#define SC7180_SLAVE_IPA_CORE 50 +/* 50 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SC7180_SLAVE_A1NOC_CFG 51 #define SC7180_SLAVE_A2NOC_CFG 52 #define SC7180_SLAVE_AHB2PHY_SOUTH 53 diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index 0f515bf10bd7..c76e3a6a98cd 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -469,15 +469,6 @@ static struct qcom_icc_node mas_qxm_ecc = { .links = { SC8180X_SLAVE_LLCC } }; -static struct qcom_icc_node mas_ipa_core_master = { - .name = "mas_ipa_core_master", - .id = SC8180X_MASTER_IPA_CORE, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { SC8180X_SLAVE_IPA_CORE } -}; - static struct qcom_icc_node mas_llcc_mc = { .name = "mas_llcc_mc", .id = SC8180X_MASTER_LLCC, @@ -1201,13 +1192,6 @@ static struct qcom_icc_node slv_srvc_gemnoc1 = { .buswidth = 4 }; -static struct qcom_icc_node slv_ipa_core_slave = { - .name = "slv_ipa_core_slave", - .id = SC8180X_SLAVE_IPA_CORE, - .channels = 1, - .buswidth = 8 -}; - static struct qcom_icc_node slv_ebi = { .name = "slv_ebi", .id = SC8180X_SLAVE_EBI_CH0, @@ -1524,11 +1508,6 @@ static struct qcom_icc_bcm bcm_co2 = { .nodes = { &mas_qnm_npu } }; -static struct qcom_icc_bcm bcm_ip0 = { - .name = "IP0", - .nodes = { &slv_ipa_core_slave } -}; - static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", .keepalive = true, @@ -1604,10 +1583,6 @@ static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh3, }; -static struct qcom_icc_bcm * const ipa_virt_bcms[] = { - &bcm_ip0, -}; - static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, &bcm_acv, @@ -1766,11 +1741,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, }; -static struct qcom_icc_node * const ipa_virt_nodes[] = { - [MASTER_IPA_CORE] = &mas_ipa_core_master, - [SLAVE_IPA_CORE] = &slv_ipa_core_slave, -}; - static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &mas_llcc_mc, [SLAVE_EBI_CH0] = &slv_ebi, @@ -1857,13 +1827,6 @@ static const struct qcom_icc_desc sc8180x_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static const struct qcom_icc_desc sc8180x_ipa_virt = { - .nodes = ipa_virt_nodes, - .num_nodes = ARRAY_SIZE(ipa_virt_nodes), - .bcms = ipa_virt_bcms, - .num_bcms = ARRAY_SIZE(ipa_virt_bcms), -}; - static const struct qcom_icc_desc sc8180x_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), @@ -1913,7 +1876,6 @@ static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc }, { .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc }, { .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc }, - { .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt }, { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt }, { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc }, { .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt }, diff --git a/drivers/interconnect/qcom/sc8180x.h b/drivers/interconnect/qcom/sc8180x.h index 2eafd35543c7..c138dcd350f1 100644 --- a/drivers/interconnect/qcom/sc8180x.h +++ b/drivers/interconnect/qcom/sc8180x.h @@ -51,7 +51,7 @@ #define SC8180X_MASTER_SNOC_GC_MEM_NOC 41 #define SC8180X_MASTER_SNOC_SF_MEM_NOC 42 #define SC8180X_MASTER_ECC 43 -#define SC8180X_MASTER_IPA_CORE 44 +/* 44 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define SC8180X_MASTER_LLCC 45 #define SC8180X_MASTER_CNOC_MNOC_CFG 46 #define SC8180X_MASTER_CAMNOC_HF0 47 @@ -146,7 +146,7 @@ #define SC8180X_SLAVE_LLCC 136 #define SC8180X_SLAVE_SERVICE_GEM_NOC 137 #define SC8180X_SLAVE_SERVICE_GEM_NOC_1 138 -#define SC8180X_SLAVE_IPA_CORE 139 +/* 139 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SC8180X_SLAVE_EBI_CH0 140 #define SC8180X_SLAVE_MNOC_SF_MEM_NOC 141 #define SC8180X_SLAVE_MNOC_HF_MEM_NOC 142 diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index 507fe5f89791..e56df893ec3e 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -284,15 +284,6 @@ static struct qcom_icc_node xm_ufs_card = { .links = { SC8280XP_SLAVE_A2NOC_SNOC }, }; -static struct qcom_icc_node ipa_core_master = { - .name = "ipa_core_master", - .id = SC8280XP_MASTER_IPA_CORE, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { SC8280XP_SLAVE_IPA_CORE }, -}; - static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", .id = SC8280XP_MASTER_QUP_CORE_0, @@ -882,13 +873,6 @@ static struct qcom_icc_node srvc_aggre2_noc = { .buswidth = 4, }; -static struct qcom_icc_node ipa_core_slave = { - .name = "ipa_core_slave", - .id = SC8280XP_SLAVE_IPA_CORE, - .channels = 1, - .buswidth = 8, -}; - static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", .id = SC8280XP_SLAVE_QUP_CORE_0, @@ -1845,12 +1829,6 @@ static struct qcom_icc_bcm bcm_cn3 = { }, }; -static struct qcom_icc_bcm bcm_ip0 = { - .name = "IP0", - .num_nodes = 1, - .nodes = { &ipa_core_slave }, -}; - static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, @@ -2077,18 +2055,15 @@ static const struct qcom_icc_desc sc8280xp_aggre2_noc = { }; static struct qcom_icc_bcm * const clk_virt_bcms[] = { - &bcm_ip0, &bcm_qup0, &bcm_qup1, &bcm_qup2, }; static struct qcom_icc_node * const clk_virt_nodes[] = { - [MASTER_IPA_CORE] = &ipa_core_master, [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [MASTER_QUP_CORE_2] = &qup2_core_master, - [SLAVE_IPA_CORE] = &ipa_core_slave, [SLAVE_QUP_CORE_0] = &qup0_core_slave, [SLAVE_QUP_CORE_1] = &qup1_core_slave, [SLAVE_QUP_CORE_2] = &qup2_core_slave, diff --git a/drivers/interconnect/qcom/sc8280xp.h b/drivers/interconnect/qcom/sc8280xp.h index 74d8fa412d65..c5c410fd5ec3 100644 --- a/drivers/interconnect/qcom/sc8280xp.h +++ b/drivers/interconnect/qcom/sc8280xp.h @@ -10,7 +10,7 @@ #define SC8280XP_MASTER_PCIE_TCU 1 #define SC8280XP_MASTER_SYS_TCU 2 #define SC8280XP_MASTER_APPSS_PROC 3 -#define SC8280XP_MASTER_IPA_CORE 4 +/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SC8280XP_MASTER_LLCC 5 #define SC8280XP_MASTER_CNOC_LPASS_AG_NOC 6 #define SC8280XP_MASTER_CDSP_NOC_CFG 7 @@ -84,7 +84,7 @@ #define SC8280XP_MASTER_USB4_0 75 #define SC8280XP_MASTER_USB4_1 76 #define SC8280XP_SLAVE_EBI1 512 -#define SC8280XP_SLAVE_IPA_CORE 513 +/* 513 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SC8280XP_SLAVE_AHB2PHY_0 514 #define SC8280XP_SLAVE_AHB2PHY_1 515 #define SC8280XP_SLAVE_AHB2PHY_2 516 diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c new file mode 100644 index 000000000000..bda955035518 --- /dev/null +++ b/drivers/interconnect/qcom/sdm670.c @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" +#include "sdm670.h" + +DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC); +DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC); +DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC); +DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); +DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC); +DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG); +DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG); +DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC); +DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC); +DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0); +DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); +DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG); +DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); +DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); +DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); +DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC); +DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC); +DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); +DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC); +DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); +DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC); +DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); +DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); +DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); +DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); +DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC); +DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4); +DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC); +DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4); +DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32); +DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG); +DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG); +DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4); +DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4); +DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4); +DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4); +DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4); +DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4); +DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4); +DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC); +DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4); +DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4); +DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4); +DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4); +DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8); +DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4); +DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG); +DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4); +DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4); +DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4); +DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4); +DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4); +DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4); +DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4); +DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4); +DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4); +DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG); +DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4); +DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4); +DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4); +DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4); +DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4); +DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4); +DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4); +DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4); +DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4); +DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC); +DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4); +DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4); +DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG); +DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC); +DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC); +DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4); +DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4); +DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); +DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32); +DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC); +DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC); +DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4); +DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC); +DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC); +DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4); +DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8); +DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC); +DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC); +DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC); +DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8); +DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8); +DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4); +DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4); +DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8); + +DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); +DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); +DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); +DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); +DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); +DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); +DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); +DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); +DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); +DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); +DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); +DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); +DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); +DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); +DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); +DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); +DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); +DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); +DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem); +DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); +DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc); +DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc); +DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic); +DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc); + +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { + &bcm_qup0, + &bcm_sn8, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] = { + [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, + [MASTER_BLSP_1] = &qhm_qup1, + [MASTER_TSIF] = &qhm_tsif, + [MASTER_EMMC] = &xm_emmc, + [MASTER_SDCC_2] = &xm_sdc2, + [MASTER_SDCC_4] = &xm_sdc4, + [MASTER_UFS_MEM] = &xm_ufs_mem, + [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, + [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, +}; + +static const struct qcom_icc_desc sdm670_aggre1_noc = { + .nodes = aggre1_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), + .bcms = aggre1_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { + &bcm_ce0, + &bcm_qup0, + &bcm_sn10, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] = { + [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, + [MASTER_QDSS_BAM] = &qhm_qdss_bam, + [MASTER_BLSP_2] = &qhm_qup2, + [MASTER_CNOC_A2NOC] = &qnm_cnoc, + [MASTER_CRYPTO_CORE_0] = &qxm_crypto, + [MASTER_IPA] = &qxm_ipa, + [MASTER_QDSS_ETR] = &xm_qdss_etr, + [MASTER_USB3] = &xm_usb3_0, + [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, + [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, +}; + +static const struct qcom_icc_desc sdm670_aggre2_noc = { + .nodes = aggre2_noc_nodes, + .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), + .bcms = aggre2_noc_bcms, + .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const config_noc_bcms[] = { + &bcm_cn0, +}; + +static struct qcom_icc_node * const config_noc_nodes[] = { + [MASTER_SPDM] = &qhm_spdm, + [MASTER_SNOC_CNOC] = &qnm_snoc, + [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, + [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, + [SLAVE_AOP] = &qhs_aop, + [SLAVE_AOSS] = &qhs_aoss, + [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, + [SLAVE_CLK_CTL] = &qhs_clk_ctl, + [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, + [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, + [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, + [SLAVE_DCC_CFG] = &qhs_dcc_cfg, + [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, + [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, + [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, + [SLAVE_GLM] = &qhs_glm, + [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] = &qhs_imem_cfg, + [SLAVE_IPA_CFG] = &qhs_ipa, + [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, + [SLAVE_PDM] = &qhs_pdm, + [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, + [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, + [SLAVE_PRNG] = &qhs_prng, + [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, + [SLAVE_BLSP_2] = &qhs_qupv3_north, + [SLAVE_BLSP_1] = &qhs_qupv3_south, + [SLAVE_SDCC_2] = &qhs_sdc2, + [SLAVE_SDCC_4] = &qhs_sdc4, + [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, + [SLAVE_SPDM_WRAPPER] = &qhs_spdm, + [SLAVE_TCSR] = &qhs_tcsr, + [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, + [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, + [SLAVE_TSIF] = &qhs_tsif, + [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, + [SLAVE_USB3] = &qhs_usb3_0, + [SLAVE_VENUS_CFG] = &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, + [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, + [SLAVE_SERVICE_CNOC] = &srvc_cnoc, +}; + +static const struct qcom_icc_desc sdm670_config_noc = { + .nodes = config_noc_nodes, + .num_nodes = ARRAY_SIZE(config_noc_nodes), + .bcms = config_noc_bcms, + .num_bcms = ARRAY_SIZE(config_noc_bcms), +}; + +static struct qcom_icc_bcm * const dc_noc_bcms[] = { +}; + +static struct qcom_icc_node * const dc_noc_nodes[] = { + [MASTER_CNOC_DC_NOC] = &qhm_cnoc, + [SLAVE_LLCC_CFG] = &qhs_llcc, + [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, +}; + +static const struct qcom_icc_desc sdm670_dc_noc = { + .nodes = dc_noc_nodes, + .num_nodes = ARRAY_SIZE(dc_noc_nodes), + .bcms = dc_noc_bcms, + .num_bcms = ARRAY_SIZE(dc_noc_bcms), +}; + +static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { +}; + +static struct qcom_icc_node * const gladiator_noc_nodes[] = { + [MASTER_AMPSS_M0] = &acm_l3, + [MASTER_GNOC_CFG] = &pm_gnoc_cfg, + [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, + [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, + [SLAVE_SERVICE_GNOC] = &srvc_gnoc, +}; + +static const struct qcom_icc_desc sdm670_gladiator_noc = { + .nodes = gladiator_noc_nodes, + .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), + .bcms = gladiator_noc_bcms, + .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), +}; + +static struct qcom_icc_bcm * const mem_noc_bcms[] = { + &bcm_acv, + &bcm_mc0, + &bcm_sh0, + &bcm_sh1, + &bcm_sh2, + &bcm_sh3, + &bcm_sh5, +}; + +static struct qcom_icc_node * const mem_noc_nodes[] = { + [MASTER_TCU_0] = &acm_tcu, + [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, + [MASTER_GNOC_MEM_NOC] = &qnm_apps, + [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, + [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, + [MASTER_GRAPHICS_3D] = &qxm_gpu, + [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, + [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, + [SLAVE_LLCC] = &qns_llcc, + [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, + [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, + [MASTER_LLCC] = &llcc_mc, + [SLAVE_EBI_CH0] = &ebi, +}; + +static const struct qcom_icc_desc sdm670_mem_noc = { + .nodes = mem_noc_nodes, + .num_nodes = ARRAY_SIZE(mem_noc_nodes), + .bcms = mem_noc_bcms, + .num_bcms = ARRAY_SIZE(mem_noc_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] = { + &bcm_mm0, + &bcm_mm1, + &bcm_mm2, + &bcm_mm3, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] = { + [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, + [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, + [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, + [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, + [MASTER_MDP_PORT0] = &qxm_mdp0, + [MASTER_MDP_PORT1] = &qxm_mdp1, + [MASTER_ROTATOR] = &qxm_rot, + [MASTER_VIDEO_P0] = &qxm_venus0, + [MASTER_VIDEO_P1] = &qxm_venus1, + [MASTER_VIDEO_PROC] = &qxm_venus_arm9, + [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, + [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, + [SLAVE_SERVICE_MNOC] = &srvc_mnoc, +}; + +static const struct qcom_icc_desc sdm670_mmss_noc = { + .nodes = mmss_noc_nodes, + .num_nodes = ARRAY_SIZE(mmss_noc_nodes), + .bcms = mmss_noc_bcms, + .num_bcms = ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] = { + &bcm_mm1, + &bcm_sn0, + &bcm_sn1, + &bcm_sn10, + &bcm_sn11, + &bcm_sn13, + &bcm_sn2, + &bcm_sn3, + &bcm_sn4, + &bcm_sn5, + &bcm_sn8, +}; + +static struct qcom_icc_node * const system_noc_nodes[] = { + [MASTER_SNOC_CFG] = &qhm_snoc_cfg, + [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, + [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, + [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, + [MASTER_PIMEM] = &qxm_pimem, + [MASTER_GIC] = &xm_gic, + [SLAVE_APPSS] = &qhs_apss, + [SLAVE_SNOC_CNOC] = &qns_cnoc, + [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, + [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, + [SLAVE_OCIMEM] = &qxs_imem, + [SLAVE_PIMEM] = &qxs_pimem, + [SLAVE_SERVICE_SNOC] = &srvc_snoc, + [SLAVE_QDSS_STM] = &xs_qdss_stm, + [SLAVE_TCU] = &xs_sys_tcu_cfg, + [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, + [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, + [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, + [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, +}; + +static const struct qcom_icc_desc sdm670_system_noc = { + .nodes = system_noc_nodes, + .num_nodes = ARRAY_SIZE(system_noc_nodes), + .bcms = system_noc_bcms, + .num_bcms = ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,sdm670-aggre1-noc", + .data = &sdm670_aggre1_noc}, + { .compatible = "qcom,sdm670-aggre2-noc", + .data = &sdm670_aggre2_noc}, + { .compatible = "qcom,sdm670-config-noc", + .data = &sdm670_config_noc}, + { .compatible = "qcom,sdm670-dc-noc", + .data = &sdm670_dc_noc}, + { .compatible = "qcom,sdm670-gladiator-noc", + .data = &sdm670_gladiator_noc}, + { .compatible = "qcom,sdm670-mem-noc", + .data = &sdm670_mem_noc}, + { .compatible = "qcom,sdm670-mmss-noc", + .data = &sdm670_mmss_noc}, + { .compatible = "qcom,sdm670-system-noc", + .data = &sdm670_system_noc}, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qcom_icc_rpmh_probe, + .remove = qcom_icc_rpmh_remove, + .driver = { + .name = "qnoc-sdm670", + .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, + }, +}; +module_platform_driver(qnoc_driver); + +MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/sdm670.h b/drivers/interconnect/qcom/sdm670.h new file mode 100644 index 000000000000..14155f244c43 --- /dev/null +++ b/drivers/interconnect/qcom/sdm670.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm #define SDM670 interconnect IDs + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM670_H +#define __DRIVERS_INTERCONNECT_QCOM_SDM670_H + +#define SDM670_MASTER_A1NOC_CFG 0 +#define SDM670_MASTER_A1NOC_SNOC 1 +#define SDM670_MASTER_A2NOC_CFG 2 +#define SDM670_MASTER_A2NOC_SNOC 3 +#define SDM670_MASTER_AMPSS_M0 4 +#define SDM670_MASTER_BLSP_1 5 +#define SDM670_MASTER_BLSP_2 6 +#define SDM670_MASTER_CAMNOC_HF0 7 +#define SDM670_MASTER_CAMNOC_HF0_UNCOMP 8 +#define SDM670_MASTER_CAMNOC_HF1 9 +#define SDM670_MASTER_CAMNOC_HF1_UNCOMP 10 +#define SDM670_MASTER_CAMNOC_SF 11 +#define SDM670_MASTER_CAMNOC_SF_UNCOMP 12 +#define SDM670_MASTER_CNOC_A2NOC 13 +#define SDM670_MASTER_CNOC_DC_NOC 14 +#define SDM670_MASTER_CNOC_MNOC_CFG 15 +#define SDM670_MASTER_CRYPTO_CORE_0 16 +#define SDM670_MASTER_EMMC 17 +#define SDM670_MASTER_GIC 18 +#define SDM670_MASTER_GNOC_CFG 19 +#define SDM670_MASTER_GNOC_MEM_NOC 20 +#define SDM670_MASTER_GNOC_SNOC 21 +#define SDM670_MASTER_GRAPHICS_3D 22 +#define SDM670_MASTER_IPA 23 +#define SDM670_MASTER_LLCC 24 +#define SDM670_MASTER_MDP_PORT0 25 +#define SDM670_MASTER_MDP_PORT1 26 +#define SDM670_MASTER_MEM_NOC_CFG 27 +#define SDM670_MASTER_MEM_NOC_SNOC 28 +#define SDM670_MASTER_MNOC_HF_MEM_NOC 29 +#define SDM670_MASTER_MNOC_SF_MEM_NOC 30 +#define SDM670_MASTER_PIMEM 31 +#define SDM670_MASTER_QDSS_BAM 32 +#define SDM670_MASTER_QDSS_ETR 33 +#define SDM670_MASTER_ROTATOR 34 +#define SDM670_MASTER_SDCC_2 35 +#define SDM670_MASTER_SDCC_4 36 +#define SDM670_MASTER_SNOC_CFG 37 +#define SDM670_MASTER_SNOC_CNOC 38 +#define SDM670_MASTER_SNOC_GC_MEM_NOC 39 +#define SDM670_MASTER_SNOC_SF_MEM_NOC 40 +#define SDM670_MASTER_SPDM 41 +#define SDM670_MASTER_TCU_0 42 +#define SDM670_MASTER_TSIF 43 +#define SDM670_MASTER_UFS_MEM 44 +#define SDM670_MASTER_USB3 45 +#define SDM670_MASTER_VIDEO_P0 46 +#define SDM670_MASTER_VIDEO_P1 47 +#define SDM670_MASTER_VIDEO_PROC 48 +#define SDM670_SLAVE_A1NOC_CFG 49 +#define SDM670_SLAVE_A1NOC_SNOC 50 +#define SDM670_SLAVE_A2NOC_CFG 51 +#define SDM670_SLAVE_A2NOC_SNOC 52 +#define SDM670_SLAVE_AOP 53 +#define SDM670_SLAVE_AOSS 54 +#define SDM670_SLAVE_APPSS 55 +#define SDM670_SLAVE_BLSP_1 56 +#define SDM670_SLAVE_BLSP_2 57 +#define SDM670_SLAVE_CAMERA_CFG 58 +#define SDM670_SLAVE_CAMNOC_UNCOMP 59 +#define SDM670_SLAVE_CDSP_CFG 60 +#define SDM670_SLAVE_CLK_CTL 61 +#define SDM670_SLAVE_CNOC_A2NOC 62 +#define SDM670_SLAVE_CNOC_DDRSS 63 +#define SDM670_SLAVE_CNOC_MNOC_CFG 64 +#define SDM670_SLAVE_CRYPTO_0_CFG 65 +#define SDM670_SLAVE_DCC_CFG 66 +#define SDM670_SLAVE_DISPLAY_CFG 67 +#define SDM670_SLAVE_EBI_CH0 68 +#define SDM670_SLAVE_EMMC_CFG 69 +#define SDM670_SLAVE_GLM 70 +#define SDM670_SLAVE_GNOC_MEM_NOC 71 +#define SDM670_SLAVE_GNOC_SNOC 72 +#define SDM670_SLAVE_GRAPHICS_3D_CFG 73 +#define SDM670_SLAVE_IMEM_CFG 74 +#define SDM670_SLAVE_IPA_CFG 75 +#define SDM670_SLAVE_LLCC 76 +#define SDM670_SLAVE_LLCC_CFG 77 +#define SDM670_SLAVE_MEM_NOC_CFG 78 +#define SDM670_SLAVE_MEM_NOC_GNOC 79 +#define SDM670_SLAVE_MEM_NOC_SNOC 80 +#define SDM670_SLAVE_MNOC_HF_MEM_NOC 81 +#define SDM670_SLAVE_MNOC_SF_MEM_NOC 82 +#define SDM670_SLAVE_MSS_PROC_MS_MPU_CFG 83 +#define SDM670_SLAVE_OCIMEM 84 +#define SDM670_SLAVE_PDM 85 +#define SDM670_SLAVE_PIMEM 86 +#define SDM670_SLAVE_PIMEM_CFG 87 +#define SDM670_SLAVE_PRNG 88 +#define SDM670_SLAVE_QDSS_CFG 89 +#define SDM670_SLAVE_QDSS_STM 90 +#define SDM670_SLAVE_RBCPR_CX_CFG 91 +#define SDM670_SLAVE_SDCC_2 92 +#define SDM670_SLAVE_SDCC_4 93 +#define SDM670_SLAVE_SERVICE_A1NOC 94 +#define SDM670_SLAVE_SERVICE_A2NOC 95 +#define SDM670_SLAVE_SERVICE_CNOC 96 +#define SDM670_SLAVE_SERVICE_GNOC 97 +#define SDM670_SLAVE_SERVICE_MEM_NOC 98 +#define SDM670_SLAVE_SERVICE_MNOC 99 +#define SDM670_SLAVE_SERVICE_SNOC 100 +#define SDM670_SLAVE_SNOC_CFG 101 +#define SDM670_SLAVE_SNOC_CNOC 102 +#define SDM670_SLAVE_SNOC_MEM_NOC_GC 103 +#define SDM670_SLAVE_SNOC_MEM_NOC_SF 104 +#define SDM670_SLAVE_SOUTH_PHY_CFG 105 +#define SDM670_SLAVE_SPDM_WRAPPER 106 +#define SDM670_SLAVE_TCSR 107 +#define SDM670_SLAVE_TCU 108 +#define SDM670_SLAVE_TLMM_NORTH 109 +#define SDM670_SLAVE_TLMM_SOUTH 110 +#define SDM670_SLAVE_TSIF 111 +#define SDM670_SLAVE_UFS_MEM_CFG 112 +#define SDM670_SLAVE_USB3 113 +#define SDM670_SLAVE_VENUS_CFG 114 +#define SDM670_SLAVE_VSENSE_CTRL_CFG 115 + +#endif diff --git a/drivers/interconnect/qcom/sdx55.h b/drivers/interconnect/qcom/sdx55.h index deff8afe0631..46cbabec8aa1 100644 --- a/drivers/interconnect/qcom/sdx55.h +++ b/drivers/interconnect/qcom/sdx55.h @@ -6,7 +6,7 @@ #ifndef __DRIVERS_INTERCONNECT_QCOM_SDX55_H #define __DRIVERS_INTERCONNECT_QCOM_SDX55_H -#define SDX55_MASTER_IPA_CORE 0 +/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define SDX55_MASTER_LLCC 1 #define SDX55_MASTER_TCU_0 2 #define SDX55_MASTER_SNOC_GC_MEM_NOC 3 @@ -28,7 +28,7 @@ #define SDX55_MASTER_QDSS_ETR 19 #define SDX55_MASTER_SDCC_1 20 #define SDX55_MASTER_USB3 21 -#define SDX55_SLAVE_IPA_CORE 22 +/* 22 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SDX55_SLAVE_EBI_CH0 23 #define SDX55_SLAVE_LLCC 24 #define SDX55_SLAVE_MEM_NOC_SNOC 25 diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index 1d04a4bfea80..c5ab29322164 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -56,7 +56,6 @@ DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC); DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC); DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(ipa_core_master, SM8150_MASTER_IPA_CORE, 1, 8, SM8150_SLAVE_IPA_CORE); DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0); DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC); DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); @@ -139,7 +138,6 @@ DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32); DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC); DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC); DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ipa_core_slave, SM8150_SLAVE_IPA_CORE, 1, 8); DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4); DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC); DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC); @@ -172,7 +170,6 @@ DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu); -DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave); DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2); DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); @@ -398,22 +395,6 @@ static const struct qcom_icc_desc sm8150_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm * const ipa_virt_bcms[] = { - &bcm_ip0, -}; - -static struct qcom_icc_node * const ipa_virt_nodes[] = { - [MASTER_IPA_CORE] = &ipa_core_master, - [SLAVE_IPA_CORE] = &ipa_core_slave, -}; - -static const struct qcom_icc_desc sm8150_ipa_virt = { - .nodes = ipa_virt_nodes, - .num_nodes = ARRAY_SIZE(ipa_virt_nodes), - .bcms = ipa_virt_bcms, - .num_bcms = ARRAY_SIZE(ipa_virt_bcms), -}; - static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, @@ -517,8 +498,6 @@ static const struct of_device_id qnoc_of_match[] = { .data = &sm8150_dc_noc}, { .compatible = "qcom,sm8150-gem-noc", .data = &sm8150_gem_noc}, - { .compatible = "qcom,sm8150-ipa-virt", - .data = &sm8150_ipa_virt}, { .compatible = "qcom,sm8150-mc-virt", .data = &sm8150_mc_virt}, { .compatible = "qcom,sm8150-mmss-noc", diff --git a/drivers/interconnect/qcom/sm8150.h b/drivers/interconnect/qcom/sm8150.h index 97996f64d799..023161681fb8 100644 --- a/drivers/interconnect/qcom/sm8150.h +++ b/drivers/interconnect/qcom/sm8150.h @@ -35,7 +35,7 @@ #define SM8150_MASTER_GPU_TCU 24 #define SM8150_MASTER_GRAPHICS_3D 25 #define SM8150_MASTER_IPA 26 -#define SM8150_MASTER_IPA_CORE 27 +/* 27 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SM8150_MASTER_LLCC 28 #define SM8150_MASTER_MDP_PORT0 29 #define SM8150_MASTER_MDP_PORT1 30 @@ -94,7 +94,7 @@ #define SM8150_SLAVE_GRAPHICS_3D_CFG 83 #define SM8150_SLAVE_IMEM_CFG 84 #define SM8150_SLAVE_IPA_CFG 85 -#define SM8150_SLAVE_IPA_CORE 86 +/* 86 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SM8150_SLAVE_LLCC 87 #define SM8150_SLAVE_LLCC_CFG 88 #define SM8150_SLAVE_MNOC_HF_MEM_NOC 89 diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index 5cdb058fa095..e3bb008cb219 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -51,7 +51,6 @@ DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLC DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC); DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(ipa_core_master, SM8250_MASTER_IPA_CORE, 1, 8, SM8250_SLAVE_IPA_CORE); DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0); DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC); DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); @@ -138,7 +137,6 @@ DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_G DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4); DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4); DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ipa_core_slave, SM8250_SLAVE_IPA_CORE, 1, 8); DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4); DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC); DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC); @@ -171,7 +169,6 @@ DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave); DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); @@ -386,22 +383,6 @@ static const struct qcom_icc_desc sm8250_gem_noc = { .num_bcms = ARRAY_SIZE(gem_noc_bcms), }; -static struct qcom_icc_bcm * const ipa_virt_bcms[] = { - &bcm_ip0, -}; - -static struct qcom_icc_node * const ipa_virt_nodes[] = { - [MASTER_IPA_CORE] = &ipa_core_master, - [SLAVE_IPA_CORE] = &ipa_core_slave, -}; - -static const struct qcom_icc_desc sm8250_ipa_virt = { - .nodes = ipa_virt_nodes, - .num_nodes = ARRAY_SIZE(ipa_virt_nodes), - .bcms = ipa_virt_bcms, - .num_bcms = ARRAY_SIZE(ipa_virt_bcms), -}; - static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, @@ -531,8 +512,6 @@ static const struct of_device_id qnoc_of_match[] = { .data = &sm8250_dc_noc}, { .compatible = "qcom,sm8250-gem-noc", .data = &sm8250_gem_noc}, - { .compatible = "qcom,sm8250-ipa-virt", - .data = &sm8250_ipa_virt}, { .compatible = "qcom,sm8250-mc-virt", .data = &sm8250_mc_virt}, { .compatible = "qcom,sm8250-mmss-noc", diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h index b31fb431a20f..e3fc56bc7ca0 100644 --- a/drivers/interconnect/qcom/sm8250.h +++ b/drivers/interconnect/qcom/sm8250.h @@ -31,7 +31,7 @@ #define SM8250_MASTER_GPU_TCU 20 #define SM8250_MASTER_GRAPHICS_3D 21 #define SM8250_MASTER_IPA 22 -#define SM8250_MASTER_IPA_CORE 23 +/* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define SM8250_MASTER_LLCC 24 #define SM8250_MASTER_MDP_PORT0 25 #define SM8250_MASTER_MDP_PORT1 26 @@ -92,7 +92,7 @@ #define SM8250_SLAVE_GRAPHICS_3D_CFG 81 #define SM8250_SLAVE_IMEM_CFG 82 #define SM8250_SLAVE_IPA_CFG 83 -#define SM8250_SLAVE_IPA_CORE 84 +/* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SM8250_SLAVE_IPC_ROUTER_CFG 85 #define SM8250_SLAVE_ISENSE_CFG 86 #define SM8250_SLAVE_LLCC 87 diff --git a/drivers/ipack/devices/ipoctal.c b/drivers/ipack/devices/ipoctal.c index fc00274070b6..a01c15812b70 100644 --- a/drivers/ipack/devices/ipoctal.c +++ b/drivers/ipack/devices/ipoctal.c @@ -253,7 +253,7 @@ static void ipoctal_irq_channel(struct ipoctal_channel *channel) static irqreturn_t ipoctal_irq_handler(void *arg) { unsigned int i; - struct ipoctal *ipoctal = (struct ipoctal *) arg; + struct ipoctal *ipoctal = arg; /* Clear the IPack device interrupt */ readw(ipoctal->int_space + ACK_INT_REQ0); @@ -647,7 +647,7 @@ static void ipoctal_hangup(struct tty_struct *tty) tty_port_hangup(&channel->tty_port); ipoctal_reset_channel(channel); - tty_port_set_initialized(&channel->tty_port, 0); + tty_port_set_initialized(&channel->tty_port, false); wake_up_interruptible(&channel->tty_port.open_wait); } @@ -659,7 +659,7 @@ static void ipoctal_shutdown(struct tty_struct *tty) return; ipoctal_reset_channel(channel); - tty_port_set_initialized(&channel->tty_port, 0); + tty_port_set_initialized(&channel->tty_port, false); } static void ipoctal_cleanup(struct tty_struct *tty) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index c99b9c387556..77e30c8605d4 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -534,6 +534,26 @@ config VCPU_STALL_DETECTOR If you do not intend to run this kernel as a guest, say N. +config TMR_MANAGER + tristate "Select TMR Manager" + depends on MICROBLAZE && MB_MANAGER + help + This option enables the driver developed for TMR Manager. + The Triple Modular Redundancy(TMR) manager provides support for + fault detection. + + Say N here unless you know what you are doing. + +config TMR_INJECT + tristate "Select TMR Inject" + depends on TMR_MANAGER && FAULT_INJECTION_DEBUG_FS + help + This option enables the driver developed for TMR Inject. + The Triple Modular Redundancy(TMR) Inject provides + fault injection. + + Say N here unless you know what you are doing. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e00ac8c68176..c7c632c43f51 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -63,4 +63,6 @@ obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o obj-$(CONFIG_OPEN_DICE) += open-dice.o obj-$(CONFIG_GP_PCI1XXXX) += mchp_pci1xxxx/ obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o +obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o +obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o obj-$(CONFIG_UID_SYS_STATS) += uid_sys_stats.o diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c index bdffc6543f6f..65d49a6de1a7 100644 --- a/drivers/misc/eeprom/at25.c +++ b/drivers/misc/eeprom/at25.c @@ -437,12 +437,6 @@ static int at25_probe(struct spi_device *spi) struct spi_eeprom *pdata; bool is_fram; - err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25"); - if (err >= 0) - is_fram = true; - else - is_fram = false; - /* * Ping the chip ... the status register is pretty portable, * unlike probing manufacturer IDs. We do expect that system @@ -462,6 +456,8 @@ static int at25_probe(struct spi_device *spi) at25->spi = spi; spi_set_drvdata(spi, at25); + is_fram = fwnode_device_is_compatible(dev_fwnode(&spi->dev), "cypress,fm25"); + /* Chip description */ pdata = dev_get_platdata(&spi->dev); if (pdata) { diff --git a/drivers/misc/eeprom/idt_89hpesx.c b/drivers/misc/eeprom/idt_89hpesx.c index 4e07ee9cb500..7075d0b37881 100644 --- a/drivers/misc/eeprom/idt_89hpesx.c +++ b/drivers/misc/eeprom/idt_89hpesx.c @@ -1566,12 +1566,20 @@ static struct i2c_driver idt_driver = { */ static int __init idt_init(void) { + int ret; + /* Create Debugfs directory first */ if (debugfs_initialized()) csr_dbgdir = debugfs_create_dir("idt_csr", NULL); /* Add new i2c-device driver */ - return i2c_add_driver(&idt_driver); + ret = i2c_add_driver(&idt_driver); + if (ret) { + debugfs_remove_recursive(csr_dbgdir); + return ret; + } + + return 0; } module_init(idt_init); diff --git a/drivers/misc/enclosure.c b/drivers/misc/enclosure.c index 1b010d9267c9..4ba966529458 100644 --- a/drivers/misc/enclosure.c +++ b/drivers/misc/enclosure.c @@ -32,7 +32,7 @@ static struct class enclosure_class; * found. @start can be used as a starting point to obtain multiple * enclosures per parent (should begin with NULL and then be set to * each returned enclosure device). Obtains a reference to the - * enclosure class device which must be released with device_put(). + * enclosure class device which must be released with put_device(). * If @start is not NULL, a reference must be taken on it which is * released before returning (this allows a loop through all * enclosures to exit with only the reference on the enclosure of diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 5310606113fe..7ccaca1b7cb8 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -2315,7 +2315,18 @@ static int fastrpc_rpmsg_probe(struct rpmsg_device *rpdev) data->domain_id = domain_id; data->rpdev = rpdev; - return of_platform_populate(rdev->of_node, NULL, NULL, rdev); + err = of_platform_populate(rdev->of_node, NULL, NULL, rdev); + if (err) + goto populate_error; + + return 0; + +populate_error: + if (data->fdevice) + misc_deregister(&data->fdevice->miscdev); + if (data->secure_fdevice) + misc_deregister(&data->secure_fdevice->miscdev); + fdev_error: kfree(data); return err; diff --git a/drivers/misc/genwqe/card_utils.c b/drivers/misc/genwqe/card_utils.c index 1167463f26fb..f778e11237a6 100644 --- a/drivers/misc/genwqe/card_utils.c +++ b/drivers/misc/genwqe/card_utils.c @@ -151,6 +151,9 @@ int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len) return i; } +#define CRC32_POLYNOMIAL 0x20044009 +static u32 crc32_tab[256]; /* crc32 lookup table */ + /** * genwqe_init_crc32() - Prepare a lookup table for fast crc32 calculations * @@ -159,9 +162,6 @@ int genwqe_read_app_id(struct genwqe_dev *cd, char *app_name, int len) * * Genwqe's Polynomial = 0x20044009 */ -#define CRC32_POLYNOMIAL 0x20044009 -static u32 crc32_tab[256]; /* crc32 lookup table */ - void genwqe_init_crc32(void) { int i, j; diff --git a/drivers/misc/isl29003.c b/drivers/misc/isl29003.c index aeda2fa89e61..147b58f7968d 100644 --- a/drivers/misc/isl29003.c +++ b/drivers/misc/isl29003.c @@ -186,7 +186,7 @@ static ssize_t isl29003_show_range(struct device *dev, { struct i2c_client *client = to_i2c_client(dev); - return sprintf(buf, "%i\n", isl29003_get_range(client)); + return sysfs_emit(buf, "%i\n", isl29003_get_range(client)); } static ssize_t isl29003_store_range(struct device *dev, @@ -222,7 +222,7 @@ static ssize_t isl29003_show_resolution(struct device *dev, { struct i2c_client *client = to_i2c_client(dev); - return sprintf(buf, "%d\n", isl29003_get_resolution(client)); + return sysfs_emit(buf, "%d\n", isl29003_get_resolution(client)); } static ssize_t isl29003_store_resolution(struct device *dev, @@ -256,7 +256,7 @@ static ssize_t isl29003_show_mode(struct device *dev, { struct i2c_client *client = to_i2c_client(dev); - return sprintf(buf, "%d\n", isl29003_get_mode(client)); + return sysfs_emit(buf, "%d\n", isl29003_get_mode(client)); } static ssize_t isl29003_store_mode(struct device *dev, @@ -291,7 +291,7 @@ static ssize_t isl29003_show_power_state(struct device *dev, { struct i2c_client *client = to_i2c_client(dev); - return sprintf(buf, "%d\n", isl29003_get_power_state(client)); + return sysfs_emit(buf, "%d\n", isl29003_get_power_state(client)); } static ssize_t isl29003_store_power_state(struct device *dev, @@ -327,7 +327,7 @@ static ssize_t isl29003_show_lux(struct device *dev, if (!isl29003_get_power_state(client)) return -EBUSY; - return sprintf(buf, "%d\n", isl29003_get_adc_value(client)); + return sysfs_emit(buf, "%d\n", isl29003_get_adc_value(client)); } static DEVICE_ATTR(lux, S_IRUGO, isl29003_show_lux, NULL); diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 6df7679d9739..211536109308 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2013-2022, Intel Corporation. All rights reserved. + * Copyright (c) 2013-2023, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ @@ -151,7 +151,7 @@ static int mei_fwver(struct mei_cl_device *cldev) ret = __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, MEI_CL_IO_TX_BLOCKING); if (ret < 0) { - dev_err(&cldev->dev, "Could not send ReqFWVersion cmd\n"); + dev_info(&cldev->dev, "Could not send ReqFWVersion cmd ret = %d\n", ret); return ret; } @@ -163,7 +163,7 @@ static int mei_fwver(struct mei_cl_device *cldev) * Should be at least one version block, * error out if nothing found */ - dev_err(&cldev->dev, "Could not read FW version\n"); + dev_info(&cldev->dev, "Could not read FW version ret = %d\n", bytes_recv); return -EIO; } @@ -220,15 +220,15 @@ static void mei_mkhi_fix(struct mei_cl_device *cldev) if (cldev->bus->fw_f_fw_ver_supported) { ret = mei_fwver(cldev); if (ret < 0) - dev_err(&cldev->dev, "FW version command failed %d\n", - ret); + dev_info(&cldev->dev, "FW version command failed %d\n", + ret); } if (cldev->bus->hbm_f_os_supported) { ret = mei_osver(cldev); if (ret < 0) - dev_err(&cldev->dev, "OS version command failed %d\n", - ret); + dev_info(&cldev->dev, "OS version command failed %d\n", + ret); } mei_cldev_disable(cldev); } @@ -247,7 +247,7 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev) ret = mei_fwver(cldev); if (ret < 0) - dev_err(&cldev->dev, "FW version command failed %d\n", ret); + dev_info(&cldev->dev, "FW version command failed %d\n", ret); mei_cldev_disable(cldev); } @@ -278,8 +278,8 @@ static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev) ret = mei_fwver(cldev); if (ret < 0) - dev_err(&cldev->dev, "FW version command failed %d\n", - ret); + dev_info(&cldev->dev, "FW version command failed %d\n", + ret); out: mei_cldev_disable(cldev); } @@ -380,7 +380,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, ret = __mei_cl_send(cl, (u8 *)&cmd, sizeof(cmd), 0, MEI_CL_IO_TX_BLOCKING); if (ret < 0) { - dev_err(bus->dev, "Could not send IF version cmd\n"); + dev_err(bus->dev, "Could not send IF version cmd ret = %d\n", ret); return ret; } @@ -395,7 +395,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, bytes_recv = __mei_cl_recv(cl, (u8 *)reply, if_version_length, &vtag, 0, 0); if (bytes_recv < 0 || (size_t)bytes_recv < if_version_length) { - dev_err(bus->dev, "Could not read IF version\n"); + dev_err(bus->dev, "Could not read IF version ret = %d\n", bytes_recv); ret = -EIO; goto err; } @@ -403,7 +403,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, memcpy(ver, reply->data, sizeof(*ver)); dev_info(bus->dev, "NFC MEI VERSION: IVN 0x%x Vendor ID 0x%x Type 0x%x\n", - ver->fw_ivn, ver->vendor_id, ver->radio_type); + ver->fw_ivn, ver->vendor_id, ver->radio_type); err: kfree(reply); diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index a81b890c7ee6..71d53d7ffdba 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2012-2019, Intel Corporation. All rights reserved. + * Copyright (c) 2012-2023, Intel Corporation. All rights reserved. * Intel Management Engine Interface (Intel MEI) Linux driver */ @@ -1392,6 +1392,7 @@ static int mei_cl_bus_dev_add(struct mei_cl_device *cldev) */ static void mei_cl_bus_dev_stop(struct mei_cl_device *cldev) { + cldev->do_match = 0; if (cldev->is_added) device_release_driver(&cldev->dev); } diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index e889a8bd7ac8..e0dcd5c114db 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -859,8 +859,8 @@ static void mei_hdcp_remove(struct mei_cl_device *cldev) dev_warn(&cldev->dev, "mei_cldev_disable() failed\n"); } -#define MEI_UUID_HDCP GUID_INIT(0xB638AB7E, 0x94E2, 0x4EA2, 0xA5, \ - 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04) +#define MEI_UUID_HDCP UUID_LE(0xB638AB7E, 0x94E2, 0x4EA2, 0xA5, \ + 0x52, 0xD1, 0xC5, 0x4B, 0x62, 0x7F, 0x04) static const struct mei_cl_device_id mei_hdcp_tbl[] = { { .uuid = MEI_UUID_HDCP, .version = MEI_CL_VERSION_ANY }, diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index 996b70a988be..895011b7a0bf 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -13,6 +13,11 @@ #include #include +static inline int uuid_le_cmp(const uuid_le u1, const uuid_le u2) +{ + return memcmp(&u1, &u2, sizeof(uuid_le)); +} + #include "hw.h" #include "hbm.h" diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c index 8dd09b1722eb..7ee1fa7b1cb3 100644 --- a/drivers/misc/mei/pxp/mei_pxp.c +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -238,8 +238,8 @@ static void mei_pxp_remove(struct mei_cl_device *cldev) } /* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/ -#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \ - 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1) +#define MEI_GUID_PXP UUID_LE(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \ + 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1) static struct mei_cl_device_id mei_pxp_tbl[] = { { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY }, diff --git a/drivers/misc/sgi-gru/grukservices.c b/drivers/misc/sgi-gru/grukservices.c index fa1f5a632e7f..37e804bbb1f2 100644 --- a/drivers/misc/sgi-gru/grukservices.c +++ b/drivers/misc/sgi-gru/grukservices.c @@ -425,7 +425,7 @@ int gru_get_cb_exception_detail(void *cb, static char *gru_get_cb_exception_detail_str(int ret, void *cb, char *buf, int size) { - struct gru_control_block_status *gen = (void *)cb; + struct gru_control_block_status *gen = cb; struct control_block_extended_exc_detail excdet; if (ret > 0 && gen->istatus == CBS_EXCEPTION) { @@ -452,7 +452,7 @@ static int gru_wait_idle_or_exception(struct gru_control_block_status *gen) static int gru_retry_exception(void *cb) { - struct gru_control_block_status *gen = (void *)cb; + struct gru_control_block_status *gen = cb; struct control_block_extended_exc_detail excdet; int retry = EXCEPTION_RETRY_LIMIT; @@ -475,7 +475,7 @@ static int gru_retry_exception(void *cb) int gru_check_status_proc(void *cb) { - struct gru_control_block_status *gen = (void *)cb; + struct gru_control_block_status *gen = cb; int ret; ret = gen->istatus; @@ -488,7 +488,7 @@ int gru_check_status_proc(void *cb) int gru_wait_proc(void *cb) { - struct gru_control_block_status *gen = (void *)cb; + struct gru_control_block_status *gen = cb; int ret; ret = gru_wait_idle_or_exception(gen); diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c index 7f6976a9f508..01d2257deea4 100644 --- a/drivers/misc/ti-st/st_core.c +++ b/drivers/misc/ti-st/st_core.c @@ -338,7 +338,7 @@ void st_int_recv(void *disc_data, ptr++; count--; continue; - /* Unknow packet? */ + /* Unknown packet? */ default: type = *ptr; diff --git a/drivers/misc/uacce/uacce.c b/drivers/misc/uacce/uacce.c index b65ab440a19e..07023397afc7 100644 --- a/drivers/misc/uacce/uacce.c +++ b/drivers/misc/uacce/uacce.c @@ -363,12 +363,52 @@ static ssize_t region_dus_size_show(struct device *dev, uacce->qf_pg_num[UACCE_QFRT_DUS] << PAGE_SHIFT); } +static ssize_t isolate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct uacce_device *uacce = to_uacce_device(dev); + + return sysfs_emit(buf, "%d\n", uacce->ops->get_isolate_state(uacce)); +} + +static ssize_t isolate_strategy_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct uacce_device *uacce = to_uacce_device(dev); + u32 val; + + val = uacce->ops->isolate_err_threshold_read(uacce); + + return sysfs_emit(buf, "%u\n", val); +} + +static ssize_t isolate_strategy_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct uacce_device *uacce = to_uacce_device(dev); + unsigned long val; + int ret; + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + if (val > UACCE_MAX_ERR_THRESHOLD) + return -EINVAL; + + ret = uacce->ops->isolate_err_threshold_write(uacce, val); + if (ret) + return ret; + + return count; +} + static DEVICE_ATTR_RO(api); static DEVICE_ATTR_RO(flags); static DEVICE_ATTR_RO(available_instances); static DEVICE_ATTR_RO(algorithms); static DEVICE_ATTR_RO(region_mmio_size); static DEVICE_ATTR_RO(region_dus_size); +static DEVICE_ATTR_RO(isolate); +static DEVICE_ATTR_RW(isolate_strategy); static struct attribute *uacce_dev_attrs[] = { &dev_attr_api.attr, @@ -377,6 +417,8 @@ static struct attribute *uacce_dev_attrs[] = { &dev_attr_algorithms.attr, &dev_attr_region_mmio_size.attr, &dev_attr_region_dus_size.attr, + &dev_attr_isolate.attr, + &dev_attr_isolate_strategy.attr, NULL, }; @@ -392,6 +434,14 @@ static umode_t uacce_dev_is_visible(struct kobject *kobj, (!uacce->qf_pg_num[UACCE_QFRT_DUS]))) return 0; + if (attr == &dev_attr_isolate_strategy.attr && + (!uacce->ops->isolate_err_threshold_read && + !uacce->ops->isolate_err_threshold_write)) + return 0; + + if (attr == &dev_attr_isolate.attr && !uacce->ops->get_isolate_state) + return 0; + return attr->mode; } diff --git a/drivers/misc/vmw_balloon.c b/drivers/misc/vmw_balloon.c index 61a2be712bf7..9ce9b9e0e9b6 100644 --- a/drivers/misc/vmw_balloon.c +++ b/drivers/misc/vmw_balloon.c @@ -1709,7 +1709,7 @@ static void __init vmballoon_debugfs_init(struct vmballoon *b) static void __exit vmballoon_debugfs_exit(struct vmballoon *b) { static_key_disable(&balloon_stat_enabled.key); - debugfs_remove(debugfs_lookup("vmmemctl", NULL)); + debugfs_lookup_and_remove("vmmemctl", NULL); kfree(b->stats); b->stats = NULL; } diff --git a/drivers/misc/vmw_vmci/vmci_host.c b/drivers/misc/vmw_vmci/vmci_host.c index da1e2a773823..857b9851402a 100644 --- a/drivers/misc/vmw_vmci/vmci_host.c +++ b/drivers/misc/vmw_vmci/vmci_host.c @@ -242,6 +242,8 @@ static int vmci_host_setup_notify(struct vmci_ctx *context, context->notify_page = NULL; return VMCI_ERROR_GENERIC; } + if (context->notify_page == NULL) + return VMCI_ERROR_UNAVAILABLE; /* * Map the locked page and set up notify pointer. diff --git a/drivers/misc/xilinx_tmr_inject.c b/drivers/misc/xilinx_tmr_inject.c new file mode 100644 index 000000000000..d96f6d7cd109 --- /dev/null +++ b/drivers/misc/xilinx_tmr_inject.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Xilinx TMR Inject IP. + * + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Description: + * This driver is developed for TMR Inject IP,The Triple Modular Redundancy(TMR) + * Inject provides fault injection. + */ + +#include +#include +#include +#include + +/* TMR Inject Register offsets */ +#define XTMR_INJECT_CR_OFFSET 0x0 +#define XTMR_INJECT_AIR_OFFSET 0x4 +#define XTMR_INJECT_IIR_OFFSET 0xC +#define XTMR_INJECT_EAIR_OFFSET 0x10 +#define XTMR_INJECT_ERR_OFFSET 0x204 + +/* Register Bitmasks/shifts */ +#define XTMR_INJECT_CR_CPUID_SHIFT 8 +#define XTMR_INJECT_CR_IE_SHIFT 10 +#define XTMR_INJECT_IIR_ADDR_MASK GENMASK(31, 16) + +#define XTMR_INJECT_MAGIC_MAX_VAL 255 + +/** + * struct xtmr_inject_dev - Driver data for TMR Inject + * @regs: device physical base address + * @magic: Magic hardware configuration value + */ +struct xtmr_inject_dev { + void __iomem *regs; + u32 magic; +}; + +static DECLARE_FAULT_ATTR(inject_fault); +static char *inject_request; +module_param(inject_request, charp, 0); +MODULE_PARM_DESC(inject_request, "default fault injection attributes"); +static struct dentry *dbgfs_root; + +/* IO accessors */ +static inline void xtmr_inject_write(struct xtmr_inject_dev *xtmr_inject, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_inject->regs + addr); +} + +static inline u32 xtmr_inject_read(struct xtmr_inject_dev *xtmr_inject, + u32 addr) +{ + return ioread32(xtmr_inject->regs + addr); +} + +static int xtmr_inject_set(void *data, u64 val) +{ + if (val != 1) + return -EINVAL; + + xmb_inject_err(); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(xtmr_inject_fops, NULL, xtmr_inject_set, "%llu\n"); + +static void xtmr_init_debugfs(struct xtmr_inject_dev *xtmr_inject) +{ + struct dentry *dir; + + dbgfs_root = debugfs_create_dir("xtmr_inject", NULL); + dir = fault_create_debugfs_attr("inject_fault", dbgfs_root, + &inject_fault); + debugfs_create_file("inject_fault", 0200, dir, NULL, + &xtmr_inject_fops); +} + +static void xtmr_inject_init(struct xtmr_inject_dev *xtmr_inject) +{ + u32 cr_val; + + if (inject_request) + setup_fault_attr(&inject_fault, inject_request); + /* Allow fault injection */ + cr_val = xtmr_inject->magic | + (1 << XTMR_INJECT_CR_IE_SHIFT) | + (1 << XTMR_INJECT_CR_CPUID_SHIFT); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_CR_OFFSET, + cr_val); + /* Initialize the address inject and instruction inject registers */ + xtmr_inject_write(xtmr_inject, XTMR_INJECT_AIR_OFFSET, + XMB_INJECT_ERR_OFFSET); + xtmr_inject_write(xtmr_inject, XTMR_INJECT_IIR_OFFSET, + XMB_INJECT_ERR_OFFSET & XTMR_INJECT_IIR_ADDR_MASK); +} + +/** + * xtmr_inject_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_inject_probe(struct platform_device *pdev) +{ + struct xtmr_inject_dev *xtmr_inject; + int err; + + xtmr_inject = devm_kzalloc(&pdev->dev, sizeof(*xtmr_inject), + GFP_KERNEL); + if (!xtmr_inject) + return -ENOMEM; + + xtmr_inject->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(xtmr_inject->regs)) + return PTR_ERR(xtmr_inject->regs); + + err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic", + &xtmr_inject->magic); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic property"); + return err; + } + + if (xtmr_inject->magic > XTMR_INJECT_MAGIC_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic property value"); + return -EINVAL; + } + + /* Initialize TMR Inject */ + xtmr_inject_init(xtmr_inject); + + xtmr_init_debugfs(xtmr_inject); + + platform_set_drvdata(pdev, xtmr_inject); + + return 0; +} + +static int xtmr_inject_remove(struct platform_device *pdev) +{ + debugfs_remove_recursive(dbgfs_root); + dbgfs_root = NULL; + return 0; +} + +static const struct of_device_id xtmr_inject_of_match[] = { + { + .compatible = "xlnx,tmr-inject-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_inject_of_match); + +static struct platform_driver xtmr_inject_driver = { + .driver = { + .name = "xilinx-tmr_inject", + .of_match_table = xtmr_inject_of_match, + }, + .probe = xtmr_inject_probe, + .remove = xtmr_inject_remove, +}; +module_platform_driver(xtmr_inject_driver); +MODULE_AUTHOR("Advanced Micro Devices, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Inject Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/xilinx_tmr_manager.c b/drivers/misc/xilinx_tmr_manager.c new file mode 100644 index 000000000000..0ef55e06d3a0 --- /dev/null +++ b/drivers/misc/xilinx_tmr_manager.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Xilinx TMR Manager IP. + * + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Description: + * This driver is developed for TMR Manager,The Triple Modular Redundancy(TMR) + * Manager is responsible for handling the TMR subsystem state, including + * fault detection and error recovery. The core is triplicated in each of + * the sub-blocks in the TMR subsystem, and provides majority voting of + * its internal state provides soft error detection, correction and + * recovery. + */ + +#include +#include +#include + +/* TMR Manager Register offsets */ +#define XTMR_MANAGER_CR_OFFSET 0x0 +#define XTMR_MANAGER_FFR_OFFSET 0x4 +#define XTMR_MANAGER_CMR0_OFFSET 0x8 +#define XTMR_MANAGER_CMR1_OFFSET 0xC +#define XTMR_MANAGER_BDIR_OFFSET 0x10 +#define XTMR_MANAGER_SEMIMR_OFFSET 0x1C + +/* Register Bitmasks/shifts */ +#define XTMR_MANAGER_CR_MAGIC1_MASK GENMASK(7, 0) +#define XTMR_MANAGER_CR_MAGIC2_MASK GENMASK(15, 8) +#define XTMR_MANAGER_CR_RIR_MASK BIT(16) +#define XTMR_MANAGER_FFR_LM12_MASK BIT(0) +#define XTMR_MANAGER_FFR_LM13_MASK BIT(1) +#define XTMR_MANAGER_FFR_LM23_MASK BIT(2) + +#define XTMR_MANAGER_CR_MAGIC2_SHIFT 4 +#define XTMR_MANAGER_CR_RIR_SHIFT 16 +#define XTMR_MANAGER_CR_BB_SHIFT 18 + +#define XTMR_MANAGER_MAGIC1_MAX_VAL 255 + +/** + * struct xtmr_manager_dev - Driver data for TMR Manager + * @regs: device physical base address + * @cr_val: control register value + * @magic1: Magic 1 hardware configuration value + * @err_cnt: error statistics count + * @phys_baseaddr: Physical base address + */ +struct xtmr_manager_dev { + void __iomem *regs; + u32 cr_val; + u32 magic1; + u32 err_cnt; + resource_size_t phys_baseaddr; +}; + +/* IO accessors */ +static inline void xtmr_manager_write(struct xtmr_manager_dev *xtmr_manager, + u32 addr, u32 value) +{ + iowrite32(value, xtmr_manager->regs + addr); +} + +static inline u32 xtmr_manager_read(struct xtmr_manager_dev *xtmr_manager, + u32 addr) +{ + return ioread32(xtmr_manager->regs + addr); +} + +static void xmb_manager_reset_handler(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the FFR Register contents as a part of recovery process. */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_FFR_OFFSET, 0); +} + +static void xmb_manager_update_errcnt(struct xtmr_manager_dev *xtmr_manager) +{ + xtmr_manager->err_cnt++; +} + +static ssize_t errcnt_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%x\n", xtmr_manager->err_cnt); +} +static DEVICE_ATTR_RO(errcnt); + +static ssize_t dis_block_break_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct xtmr_manager_dev *xtmr_manager = dev_get_drvdata(dev); + int ret; + long value; + + ret = kstrtoul(buf, 16, &value); + if (ret) + return ret; + + /* unblock the break signal*/ + xtmr_manager->cr_val &= ~(1 << XTMR_MANAGER_CR_BB_SHIFT); + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + return size; +} +static DEVICE_ATTR_WO(dis_block_break); + +static struct attribute *xtmr_manager_dev_attrs[] = { + &dev_attr_dis_block_break.attr, + &dev_attr_errcnt.attr, + NULL, +}; +ATTRIBUTE_GROUPS(xtmr_manager_dev); + +static void xtmr_manager_init(struct xtmr_manager_dev *xtmr_manager) +{ + /* Clear the SEM interrupt mask register to disable the interrupt */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_SEMIMR_OFFSET, 0); + + /* Allow recovery reset by default */ + xtmr_manager->cr_val = (1 << XTMR_MANAGER_CR_RIR_SHIFT) | + xtmr_manager->magic1; + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_CR_OFFSET, + xtmr_manager->cr_val); + /* + * Configure Break Delay Initialization Register to zero so that + * break occurs immediately + */ + xtmr_manager_write(xtmr_manager, XTMR_MANAGER_BDIR_OFFSET, 0); + + /* + * To come out of break handler need to block the break signal + * in the tmr manager, update the xtmr_manager cr_val for the same + */ + xtmr_manager->cr_val |= (1 << XTMR_MANAGER_CR_BB_SHIFT); + + /* + * When the break vector gets asserted because of error injection, + * the break signal must be blocked before exiting from the + * break handler, Below api updates the TMR manager address and + * control register and error counter callback arguments, + * which will be used by the break handler to block the + * break and call the callback function. + */ + xmb_manager_register(xtmr_manager->phys_baseaddr, xtmr_manager->cr_val, + (void *)xmb_manager_update_errcnt, + xtmr_manager, (void *)xmb_manager_reset_handler); +} + +/** + * xtmr_manager_probe - Driver probe function + * @pdev: Pointer to the platform_device structure + * + * This is the driver probe routine. It does all the memory + * allocation for the device. + * + * Return: 0 on success and failure value on error + */ +static int xtmr_manager_probe(struct platform_device *pdev) +{ + struct xtmr_manager_dev *xtmr_manager; + struct resource *res; + int err; + + xtmr_manager = devm_kzalloc(&pdev->dev, sizeof(*xtmr_manager), + GFP_KERNEL); + if (!xtmr_manager) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + xtmr_manager->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(xtmr_manager->regs)) + return PTR_ERR(xtmr_manager->regs); + + xtmr_manager->phys_baseaddr = res->start; + + err = of_property_read_u32(pdev->dev.of_node, "xlnx,magic1", + &xtmr_manager->magic1); + if (err < 0) { + dev_err(&pdev->dev, "unable to read xlnx,magic1 property"); + return err; + } + + if (xtmr_manager->magic1 > XTMR_MANAGER_MAGIC1_MAX_VAL) { + dev_err(&pdev->dev, "invalid xlnx,magic1 property value"); + return -EINVAL; + } + + /* Initialize TMR Manager */ + xtmr_manager_init(xtmr_manager); + + platform_set_drvdata(pdev, xtmr_manager); + + return 0; +} + +static const struct of_device_id xtmr_manager_of_match[] = { + { + .compatible = "xlnx,tmr-manager-1.0", + }, + { /* end of table */ } +}; +MODULE_DEVICE_TABLE(of, xtmr_manager_of_match); + +static struct platform_driver xtmr_manager_driver = { + .driver = { + .name = "xilinx-tmr_manager", + .of_match_table = xtmr_manager_of_match, + .dev_groups = xtmr_manager_dev_groups, + }, + .probe = xtmr_manager_probe, +}; +module_platform_driver(xtmr_manager_driver); + +MODULE_AUTHOR("Advanced Micro Devices, Inc"); +MODULE_DESCRIPTION("Xilinx TMR Manager Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/core/sdio_uart.c b/drivers/mmc/core/sdio_uart.c index ae7ef2e038be..50536fe59f1a 100644 --- a/drivers/mmc/core/sdio_uart.c +++ b/drivers/mmc/core/sdio_uart.c @@ -526,7 +526,7 @@ static void sdio_uart_irq(struct sdio_func *func) port->in_sdio_uart_irq = NULL; } -static int uart_carrier_raised(struct tty_port *tport) +static bool uart_carrier_raised(struct tty_port *tport) { struct sdio_uart_port *port = container_of(tport, struct sdio_uart_port, port); @@ -535,28 +535,27 @@ static int uart_carrier_raised(struct tty_port *tport) return 1; ret = sdio_uart_get_mctrl(port); sdio_uart_release_func(port); - if (ret & TIOCM_CAR) - return 1; - return 0; + + return ret & TIOCM_CAR; } /** * uart_dtr_rts - port helper to set uart signals * @tport: tty port to be updated - * @onoff: set to turn on DTR/RTS + * @active: set to turn on DTR/RTS * * Called by the tty port helpers when the modem signals need to be * adjusted during an open, close and hangup. */ -static void uart_dtr_rts(struct tty_port *tport, int onoff) +static void uart_dtr_rts(struct tty_port *tport, bool active) { struct sdio_uart_port *port = container_of(tport, struct sdio_uart_port, port); int ret = sdio_uart_claim_func(port); if (ret) return; - if (onoff == 0) + if (!active) sdio_uart_clear_mctrl(port, TIOCM_DTR | TIOCM_RTS); else sdio_uart_set_mctrl(port, TIOCM_DTR | TIOCM_RTS); diff --git a/drivers/most/Kconfig b/drivers/most/Kconfig index 4b8145b9e7ad..69c9e728b7e6 100644 --- a/drivers/most/Kconfig +++ b/drivers/most/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 menuconfig MOST - tristate "MOST support" + tristate "MOST (Media Oriented Systems Transport) support" depends on HAS_DMA && CONFIGFS_FS default n help diff --git a/drivers/most/most_cdev.c b/drivers/most/most_cdev.c index 3722f9abd7b9..4ee536980f71 100644 --- a/drivers/most/most_cdev.c +++ b/drivers/most/most_cdev.c @@ -297,7 +297,7 @@ static __poll_t comp_poll(struct file *filp, poll_table *wait) return mask; } -/** +/* * Initialization of struct file_operations */ static const struct file_operations channel_fops = { @@ -404,8 +404,9 @@ static int comp_tx_completion(struct most_interface *iface, int channel_id) * @channel_id: channel index/ID * @cfg: pointer to actual channel configuration * @name: name of the device to be created + * @args: pointer to array of component parameters (from configfs) * - * This allocates achannel object and creates the device node in /dev + * This allocates a channel object and creates the device node in /dev * * Returns 0 on success or error code otherwise. */ diff --git a/drivers/most/most_snd.c b/drivers/most/most_snd.c index c87f6a037874..45d762804c5e 100644 --- a/drivers/most/most_snd.c +++ b/drivers/most/most_snd.c @@ -27,6 +27,7 @@ static struct most_component comp; /** * struct channel - private structure to keep channel specific data * @substream: stores the substream structure + * @pcm_hardware: low-level hardware description * @iface: interface for which the channel belongs to * @cfg: channel configuration * @card: registered sound card @@ -38,6 +39,7 @@ static struct most_component comp; * @opened: set when the stream is opened * @playback_task: playback thread * @playback_waitq: waitq used by playback thread + * @copy_fn: copy function for PCM-specific format and width */ struct channel { struct snd_pcm_substream *substream; @@ -400,7 +402,7 @@ static snd_pcm_uframes_t pcm_pointer(struct snd_pcm_substream *substream) return channel->buffer_pos; } -/** +/* * Initialization of struct snd_pcm_ops */ static const struct snd_pcm_ops pcm_ops = { @@ -501,8 +503,8 @@ static void release_adapter(struct sound_adapter *adpt) * @iface: pointer to interface instance * @channel_id: channel index/ID * @cfg: pointer to actual channel configuration - * @arg_list: string that provides the name of the device to be created in /dev - * plus the desired audio resolution + * @device_name: name of the device to be created in /dev + * @arg_list: string that provides the desired audio resolution * * Creates sound card, pcm device, sets pcm ops and registers sound card. * @@ -699,7 +701,7 @@ static int audio_tx_completion(struct most_interface *iface, int channel_id) return 0; } -/** +/* * Initialization of the struct most_component */ static struct most_component comp = { diff --git a/drivers/most/most_usb.c b/drivers/most/most_usb.c index 73258b24fea7..485d5ca39951 100644 --- a/drivers/most/most_usb.c +++ b/drivers/most/most_usb.c @@ -660,7 +660,7 @@ static void hdm_request_netinfo(struct most_interface *iface, int channel, /** * link_stat_timer_handler - schedule work obtaining mac address and link status - * @data: pointer to USB device instance + * @t: pointer to timer_list which holds a pointer to the USB device instance * * The handler runs in interrupt context. That's why we need to defer the * tasks to a work queue. @@ -763,14 +763,14 @@ static void wq_clear_halt(struct work_struct *wq_obj) mutex_unlock(&mdev->io_mutex); } -/** +/* * hdm_usb_fops - file operation table for USB driver */ static const struct file_operations hdm_usb_fops = { .owner = THIS_MODULE, }; -/** +/* * usb_device_id - ID table for HCD device probing */ static const struct usb_device_id usbid[] = { diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 755f551426b5..6dec38805041 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -290,9 +290,19 @@ config NVMEM_SPRD_EFUSE This driver can also be built as a module. If so, the module will be called nvmem-sprd-efuse. +config NVMEM_STM32_BSEC_OPTEE_TA + def_bool NVMEM_STM32_ROMEM && OPTEE + help + Say y here to enable the accesses to STM32MP SoC OTPs by the OP-TEE + trusted application STM32MP BSEC. + + This library is a used by stm32-romem driver or included in the module + called nvmem-stm32-romem. + config NVMEM_STM32_ROMEM tristate "STMicroelectronics STM32 factory-programmed memory support" depends on ARCH_STM32 || COMPILE_TEST + depends on OPTEE || !OPTEE help Say y here to enable read-only access for STMicroelectronics STM32 factory-programmed memory area. diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index fa80fe17e567..6a1efffa88f0 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o nvmem_sprd_efuse-y := sprd-efuse.o obj-$(CONFIG_NVMEM_STM32_ROMEM) += nvmem_stm32_romem.o nvmem_stm32_romem-y := stm32-romem.o +nvmem_stm32_romem-$(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA) += stm32-bsec-optee-ta.o obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) += nvmem_sunplus_ocotp.o nvmem_sunplus_ocotp-y := sunplus-ocotp.o obj-$(CONFIG_NVMEM_SUNXI_SID) += nvmem_sunxi_sid.o diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 34ee9d36ee7b..174ef3574e07 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -60,6 +60,7 @@ struct nvmem_cell_entry { struct nvmem_cell { struct nvmem_cell_entry *entry; const char *id; + int index; }; static DEFINE_MUTEX(nvmem_mutex); @@ -500,6 +501,36 @@ static int nvmem_cell_info_to_nvmem_cell_entry(struct nvmem_device *nvmem, return 0; } +/** + * nvmem_add_one_cell() - Add one cell information to an nvmem device + * + * @nvmem: nvmem device to add cells to. + * @info: nvmem cell info to add to the device + * + * Return: 0 or negative error code on failure. + */ +int nvmem_add_one_cell(struct nvmem_device *nvmem, + const struct nvmem_cell_info *info) +{ + struct nvmem_cell_entry *cell; + int rval; + + cell = kzalloc(sizeof(*cell), GFP_KERNEL); + if (!cell) + return -ENOMEM; + + rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, info, cell); + if (rval) { + kfree(cell); + return rval; + } + + nvmem_cell_entry_add(cell); + + return 0; +} +EXPORT_SYMBOL_GPL(nvmem_add_one_cell); + /** * nvmem_add_cells() - Add cell information to an nvmem device * @@ -513,40 +544,15 @@ static int nvmem_add_cells(struct nvmem_device *nvmem, const struct nvmem_cell_info *info, int ncells) { - struct nvmem_cell_entry **cells; int i, rval; - cells = kcalloc(ncells, sizeof(*cells), GFP_KERNEL); - if (!cells) - return -ENOMEM; - for (i = 0; i < ncells; i++) { - cells[i] = kzalloc(sizeof(**cells), GFP_KERNEL); - if (!cells[i]) { - rval = -ENOMEM; - goto err; - } - - rval = nvmem_cell_info_to_nvmem_cell_entry(nvmem, &info[i], cells[i]); - if (rval) { - kfree(cells[i]); - goto err; - } - - nvmem_cell_entry_add(cells[i]); + rval = nvmem_add_one_cell(nvmem, &info[i]); + if (rval) + return rval; } - /* remove tmp array */ - kfree(cells); - return 0; -err: - while (i--) - nvmem_cell_entry_drop(cells[i]); - - kfree(cells); - - return rval; } /** @@ -682,15 +688,14 @@ static int nvmem_validate_keepouts(struct nvmem_device *nvmem) static int nvmem_add_cells_from_of(struct nvmem_device *nvmem) { - struct device_node *parent, *child; struct device *dev = &nvmem->dev; - struct nvmem_cell_entry *cell; + struct device_node *child; const __be32 *addr; - int len; + int len, ret; - parent = dev->of_node; + for_each_child_of_node(dev->of_node, child) { + struct nvmem_cell_info info = {0}; - for_each_child_of_node(parent, child) { addr = of_get_property(child, "reg", &len); if (!addr) continue; @@ -700,40 +705,24 @@ static int nvmem_add_cells_from_of(struct nvmem_device *nvmem) return -EINVAL; } - cell = kzalloc(sizeof(*cell), GFP_KERNEL); - if (!cell) { - of_node_put(child); - return -ENOMEM; - } - - cell->nvmem = nvmem; - cell->offset = be32_to_cpup(addr++); - cell->bytes = be32_to_cpup(addr); - cell->name = kasprintf(GFP_KERNEL, "%pOFn", child); + info.offset = be32_to_cpup(addr++); + info.bytes = be32_to_cpup(addr); + info.name = kasprintf(GFP_KERNEL, "%pOFn", child); addr = of_get_property(child, "bits", &len); if (addr && len == (2 * sizeof(u32))) { - cell->bit_offset = be32_to_cpup(addr++); - cell->nbits = be32_to_cpup(addr); + info.bit_offset = be32_to_cpup(addr++); + info.nbits = be32_to_cpup(addr); } - if (cell->nbits) - cell->bytes = DIV_ROUND_UP( - cell->nbits + cell->bit_offset, - BITS_PER_BYTE); + info.np = of_node_get(child); - if (!IS_ALIGNED(cell->offset, nvmem->stride)) { - dev_err(dev, "cell %s unaligned to nvmem stride %d\n", - cell->name, nvmem->stride); - /* Cells already added will be freed later. */ - kfree_const(cell->name); - kfree(cell); + ret = nvmem_add_one_cell(nvmem, &info); + kfree(info.name); + if (ret) { of_node_put(child); - return -EINVAL; + return ret; } - - cell->np = of_node_get(child); - nvmem_cell_entry_add(cell); } return 0; @@ -764,7 +753,7 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) if (!nvmem) return ERR_PTR(-ENOMEM); - rval = ida_alloc(&nvmem_ida, GFP_KERNEL); + rval = ida_alloc(&nvmem_ida, GFP_KERNEL); if (rval < 0) { kfree(nvmem); return ERR_PTR(rval); @@ -1122,7 +1111,8 @@ struct nvmem_device *devm_nvmem_device_get(struct device *dev, const char *id) } EXPORT_SYMBOL_GPL(devm_nvmem_device_get); -static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, const char *id) +static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, + const char *id, int index) { struct nvmem_cell *cell; const char *name = NULL; @@ -1141,6 +1131,7 @@ static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry, cons cell->id = name; cell->entry = entry; + cell->index = index; return cell; } @@ -1179,7 +1170,7 @@ nvmem_cell_get_from_lookup(struct device *dev, const char *con_id) __nvmem_device_put(nvmem); cell = ERR_PTR(-ENOENT); } else { - cell = nvmem_create_cell(cell_entry, con_id); + cell = nvmem_create_cell(cell_entry, con_id, 0); if (IS_ERR(cell)) __nvmem_device_put(nvmem); } @@ -1227,15 +1218,27 @@ struct nvmem_cell *of_nvmem_cell_get(struct device_node *np, const char *id) struct nvmem_device *nvmem; struct nvmem_cell_entry *cell_entry; struct nvmem_cell *cell; + struct of_phandle_args cell_spec; int index = 0; + int cell_index = 0; + int ret; /* if cell name exists, find index to the name */ if (id) index = of_property_match_string(np, "nvmem-cell-names", id); - cell_np = of_parse_phandle(np, "nvmem-cells", index); - if (!cell_np) - return ERR_PTR(-ENOENT); + ret = of_parse_phandle_with_optional_args(np, "nvmem-cells", + "#nvmem-cell-cells", + index, &cell_spec); + if (ret) + return ERR_PTR(ret); + + if (cell_spec.args_count > 1) + return ERR_PTR(-EINVAL); + + cell_np = cell_spec.np; + if (cell_spec.args_count) + cell_index = cell_spec.args[0]; nvmem_np = of_get_parent(cell_np); if (!nvmem_np) { @@ -1257,7 +1260,7 @@ struct nvmem_cell *of_nvmem_cell_get(struct device_node *np, const char *id) return ERR_PTR(-ENOENT); } - cell = nvmem_create_cell(cell_entry, id); + cell = nvmem_create_cell(cell_entry, id, cell_index); if (IS_ERR(cell)) __nvmem_device_put(nvmem); @@ -1410,8 +1413,8 @@ static void nvmem_shift_read_buffer_in_place(struct nvmem_cell_entry *cell, void } static int __nvmem_cell_read(struct nvmem_device *nvmem, - struct nvmem_cell_entry *cell, - void *buf, size_t *len, const char *id) + struct nvmem_cell_entry *cell, + void *buf, size_t *len, const char *id, int index) { int rc; @@ -1425,7 +1428,7 @@ static int __nvmem_cell_read(struct nvmem_device *nvmem, nvmem_shift_read_buffer_in_place(cell, buf); if (nvmem->cell_post_process) { - rc = nvmem->cell_post_process(nvmem->priv, id, + rc = nvmem->cell_post_process(nvmem->priv, id, index, cell->offset, buf, cell->bytes); if (rc) return rc; @@ -1460,7 +1463,7 @@ void *nvmem_cell_read(struct nvmem_cell *cell, size_t *len) if (!buf) return ERR_PTR(-ENOMEM); - rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id); + rc = __nvmem_cell_read(nvmem, cell->entry, buf, len, cell->id, cell->index); if (rc) { kfree(buf); return ERR_PTR(rc); @@ -1773,7 +1776,7 @@ ssize_t nvmem_device_cell_read(struct nvmem_device *nvmem, if (rc) return rc; - rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL); + rc = __nvmem_cell_read(nvmem, &cell, buf, &len, NULL, 0); if (rc) return rc; diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 14284e866f26..e9b52ecb3f72 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -222,8 +222,8 @@ read_end: return ret; } -static int imx_ocotp_cell_pp(void *context, const char *id, unsigned int offset, - void *data, size_t bytes) +static int imx_ocotp_cell_pp(void *context, const char *id, int index, + unsigned int offset, void *data, size_t bytes) { struct ocotp_priv *priv = context; diff --git a/drivers/nvmem/qcom-spmi-sdam.c b/drivers/nvmem/qcom-spmi-sdam.c index 8499892044b7..f822790db49e 100644 --- a/drivers/nvmem/qcom-spmi-sdam.c +++ b/drivers/nvmem/qcom-spmi-sdam.c @@ -175,18 +175,7 @@ static struct platform_driver sdam_driver = { }, .probe = sdam_probe, }; - -static int __init sdam_init(void) -{ - return platform_driver_register(&sdam_driver); -} -subsys_initcall(sdam_init); - -static void __exit sdam_exit(void) -{ - return platform_driver_unregister(&sdam_driver); -} -module_exit(sdam_exit); +module_platform_driver(sdam_driver); MODULE_DESCRIPTION("QCOM SPMI SDAM driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/nvmem/rave-sp-eeprom.c b/drivers/nvmem/rave-sp-eeprom.c index 66699d44f73d..c456011b75e8 100644 --- a/drivers/nvmem/rave-sp-eeprom.c +++ b/drivers/nvmem/rave-sp-eeprom.c @@ -45,7 +45,7 @@ enum rave_sp_eeprom_header_size { * @type: Access type (see enum rave_sp_eeprom_access_type) * @success: Success flag (Success = 1, Failure = 0) * @data: Read data - + * * Note this structure corresponds to RSP_*_EEPROM payload from RAVE * SP ICD */ diff --git a/drivers/nvmem/stm32-bsec-optee-ta.c b/drivers/nvmem/stm32-bsec-optee-ta.c new file mode 100644 index 000000000000..f89ce791dd12 --- /dev/null +++ b/drivers/nvmem/stm32-bsec-optee-ta.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver + * + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#include + +#include "stm32-bsec-optee-ta.h" + +/* + * Read OTP memory + * + * [in] value[0].a OTP start offset in byte + * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock) + * [out] memref[1].buffer Output buffer to store read values + * [out] memref[1].size Size of OTP to be read + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller + */ +#define PTA_BSEC_READ_MEM 0x0 + +/* + * Write OTP memory + * + * [in] value[0].a OTP start offset in byte + * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock) + * [in] memref[1].buffer Input buffer to read values + * [in] memref[1].size Size of OTP to be written + * + * Return codes: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + * TEE_ERROR_ACCESS_DENIED - OTP not accessible by caller + */ +#define PTA_BSEC_WRITE_MEM 0x1 + +/* value of PTA_BSEC access type = value[in] b */ +#define SHADOW_ACCESS 0 +#define FUSE_ACCESS 1 +#define LOCK_ACCESS 2 + +/* Bitfield definition for LOCK status */ +#define LOCK_PERM BIT(30) + +/* OP-TEE STM32MP BSEC TA UUID */ +static const uuid_t stm32mp_bsec_ta_uuid = + UUID_INIT(0x94cf71ad, 0x80e6, 0x40b5, + 0xa7, 0xc6, 0x3d, 0xc5, 0x01, 0xeb, 0x28, 0x03); + +/* + * Check whether this driver supports the BSEC TA in the TEE instance + * represented by the params (ver/data) to this function. + */ +static int stm32_bsec_optee_ta_match(struct tee_ioctl_version_data *ver, + const void *data) +{ + /* Currently this driver only supports GP compliant, OP-TEE based TA */ + if ((ver->impl_id == TEE_IMPL_ID_OPTEE) && + (ver->gen_caps & TEE_GEN_CAP_GP)) + return 1; + else + return 0; +} + +/* Open a session to OP-TEE for STM32MP BSEC TA */ +static int stm32_bsec_ta_open_session(struct tee_context *ctx, u32 *id) +{ + struct tee_ioctl_open_session_arg sess_arg; + int rc; + + memset(&sess_arg, 0, sizeof(sess_arg)); + export_uuid(sess_arg.uuid, &stm32mp_bsec_ta_uuid); + sess_arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL; + sess_arg.num_params = 0; + + rc = tee_client_open_session(ctx, &sess_arg, NULL); + if ((rc < 0) || (sess_arg.ret != 0)) { + pr_err("%s: tee_client_open_session failed err:%#x, ret:%#x\n", + __func__, sess_arg.ret, rc); + if (!rc) + rc = -EINVAL; + } else { + *id = sess_arg.session; + } + + return rc; +} + +/* close a session to OP-TEE for STM32MP BSEC TA */ +static void stm32_bsec_ta_close_session(void *ctx, u32 id) +{ + tee_client_close_session(ctx, id); +} + +/* stm32_bsec_optee_ta_open() - initialize the STM32MP BSEC TA */ +int stm32_bsec_optee_ta_open(struct tee_context **ctx) +{ + struct tee_context *tee_ctx; + u32 session_id; + int rc; + + /* Open context with TEE driver */ + tee_ctx = tee_client_open_context(NULL, stm32_bsec_optee_ta_match, NULL, NULL); + if (IS_ERR(tee_ctx)) { + rc = PTR_ERR(tee_ctx); + if (rc == -ENOENT) + return -EPROBE_DEFER; + pr_err("%s: tee_client_open_context failed (%d)\n", __func__, rc); + + return rc; + } + + /* Check STM32MP BSEC TA presence */ + rc = stm32_bsec_ta_open_session(tee_ctx, &session_id); + if (rc) { + tee_client_close_context(tee_ctx); + return rc; + } + + stm32_bsec_ta_close_session(tee_ctx, session_id); + + *ctx = tee_ctx; + + return 0; +} + +/* stm32_bsec_optee_ta_open() - release the PTA STM32MP BSEC TA */ +void stm32_bsec_optee_ta_close(void *ctx) +{ + tee_client_close_context(ctx); +} + +/* stm32_bsec_optee_ta_read() - nvmem read access using PTA client driver */ +int stm32_bsec_optee_ta_read(struct tee_context *ctx, unsigned int offset, + void *buf, size_t bytes) +{ + struct tee_shm *shm; + struct tee_ioctl_invoke_arg arg; + struct tee_param param[2]; + u8 *shm_buf; + u32 start, num_bytes; + int ret; + u32 session_id; + + ret = stm32_bsec_ta_open_session(ctx, &session_id); + if (ret) + return ret; + + memset(&arg, 0, sizeof(arg)); + memset(¶m, 0, sizeof(param)); + + arg.func = PTA_BSEC_READ_MEM; + arg.session = session_id; + arg.num_params = 2; + + /* align access on 32bits */ + start = ALIGN_DOWN(offset, 4); + num_bytes = round_up(offset + bytes - start, 4); + param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT; + param[0].u.value.a = start; + param[0].u.value.b = SHADOW_ACCESS; + + shm = tee_shm_alloc_kernel_buf(ctx, num_bytes); + if (IS_ERR(shm)) { + ret = PTR_ERR(shm); + goto out_tee_session; + } + + param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + param[1].u.memref.shm = shm; + param[1].u.memref.size = num_bytes; + + ret = tee_client_invoke_func(ctx, &arg, param); + if (ret < 0 || arg.ret != 0) { + pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", + arg.ret, ret); + if (!ret) + ret = -EIO; + } + if (!ret) { + shm_buf = tee_shm_get_va(shm, 0); + if (IS_ERR(shm_buf)) { + ret = PTR_ERR(shm_buf); + pr_err("tee_shm_get_va failed for transmit (%d)\n", ret); + } else { + /* read data from 32 bits aligned buffer */ + memcpy(buf, &shm_buf[offset % 4], bytes); + } + } + + tee_shm_free(shm); + +out_tee_session: + stm32_bsec_ta_close_session(ctx, session_id); + + return ret; +} + +/* stm32_bsec_optee_ta_write() - nvmem write access using PTA client driver */ +int stm32_bsec_optee_ta_write(struct tee_context *ctx, unsigned int lower, + unsigned int offset, void *buf, size_t bytes) +{ struct tee_shm *shm; + struct tee_ioctl_invoke_arg arg; + struct tee_param param[2]; + u8 *shm_buf; + int ret; + u32 session_id; + + ret = stm32_bsec_ta_open_session(ctx, &session_id); + if (ret) + return ret; + + /* Allow only writing complete 32-bits aligned words */ + if ((bytes % 4) || (offset % 4)) + return -EINVAL; + + memset(&arg, 0, sizeof(arg)); + memset(¶m, 0, sizeof(param)); + + arg.func = PTA_BSEC_WRITE_MEM; + arg.session = session_id; + arg.num_params = 2; + + param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT; + param[0].u.value.a = offset; + param[0].u.value.b = FUSE_ACCESS; + + shm = tee_shm_alloc_kernel_buf(ctx, bytes); + if (IS_ERR(shm)) { + ret = PTR_ERR(shm); + goto out_tee_session; + } + + param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm; + param[1].u.memref.size = bytes; + + shm_buf = tee_shm_get_va(shm, 0); + if (IS_ERR(shm_buf)) { + ret = PTR_ERR(shm_buf); + pr_err("tee_shm_get_va failed for transmit (%d)\n", ret); + tee_shm_free(shm); + + goto out_tee_session; + } + + memcpy(shm_buf, buf, bytes); + + ret = tee_client_invoke_func(ctx, &arg, param); + if (ret < 0 || arg.ret != 0) { + pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", arg.ret, ret); + if (!ret) + ret = -EIO; + } + pr_debug("Write OTPs %d to %zu, ret=%d\n", offset / 4, (offset + bytes) / 4, ret); + + /* Lock the upper OTPs with ECC protection, word programming only */ + if (!ret && ((offset + bytes) >= (lower * 4))) { + u32 start, nb_lock; + u32 *lock = (u32 *)shm_buf; + int i; + + /* + * don't lock the lower OTPs, no ECC protection and incremental + * bit programming, a second write is allowed + */ + start = max_t(u32, offset, lower * 4); + nb_lock = (offset + bytes - start) / 4; + + param[0].u.value.a = start; + param[0].u.value.b = LOCK_ACCESS; + param[1].u.memref.size = nb_lock * 4; + + for (i = 0; i < nb_lock; i++) + lock[i] = LOCK_PERM; + + ret = tee_client_invoke_func(ctx, &arg, param); + if (ret < 0 || arg.ret != 0) { + pr_err("TA_BSEC invoke failed TEE err:%#x, ret:%#x\n", arg.ret, ret); + if (!ret) + ret = -EIO; + } + pr_debug("Lock upper OTPs %d to %d, ret=%d\n", + start / 4, start / 4 + nb_lock, ret); + } + + tee_shm_free(shm); + +out_tee_session: + stm32_bsec_ta_close_session(ctx, session_id); + + return ret; +} diff --git a/drivers/nvmem/stm32-bsec-optee-ta.h b/drivers/nvmem/stm32-bsec-optee-ta.h new file mode 100644 index 000000000000..3966a0535179 --- /dev/null +++ b/drivers/nvmem/stm32-bsec-optee-ta.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver + * + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#if IS_ENABLED(CONFIG_NVMEM_STM32_BSEC_OPTEE_TA) +/** + * stm32_bsec_optee_ta_open() - initialize the STM32 BSEC TA + * @ctx: the OP-TEE context on success + * + * Return: + * On success, 0. On failure, -errno. + */ +int stm32_bsec_optee_ta_open(struct tee_context **ctx); + +/** + * stm32_bsec_optee_ta_close() - release the STM32 BSEC TA + * @ctx: the OP-TEE context + * + * This function used to clean the OP-TEE resources initialized in + * stm32_bsec_optee_ta_open(); it can be used as callback to + * devm_add_action_or_reset() + */ +void stm32_bsec_optee_ta_close(void *ctx); + +/** + * stm32_bsec_optee_ta_read() - nvmem read access using TA client driver + * @ctx: the OP-TEE context provided by stm32_bsec_optee_ta_open + * @offset: nvmem offset + * @buf: buffer to fill with nvem values + * @bytes: number of bytes to read + * + * Return: + * On success, 0. On failure, -errno. + */ +int stm32_bsec_optee_ta_read(struct tee_context *ctx, unsigned int offset, + void *buf, size_t bytes); + +/** + * stm32_bsec_optee_ta_write() - nvmem write access using TA client driver + * @ctx: the OP-TEE context provided by stm32_bsec_optee_ta_open + * @lower: number of lower OTP, not protected by ECC + * @offset: nvmem offset + * @buf: buffer with nvem values + * @bytes: number of bytes to write + * + * Return: + * On success, 0. On failure, -errno. + */ +int stm32_bsec_optee_ta_write(struct tee_context *ctx, unsigned int lower, + unsigned int offset, void *buf, size_t bytes); + +#else + +static inline int stm32_bsec_optee_ta_open(struct tee_context **ctx) +{ + return -EOPNOTSUPP; +} + +static inline void stm32_bsec_optee_ta_close(void *ctx) +{ +} + +static inline int stm32_bsec_optee_ta_read(struct tee_context *ctx, + unsigned int offset, void *buf, + size_t bytes) +{ + return -EOPNOTSUPP; +} + +static inline int stm32_bsec_optee_ta_write(struct tee_context *ctx, + unsigned int lower, + unsigned int offset, void *buf, + size_t bytes) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_NVMEM_STM32_BSEC_OPTEE_TA */ diff --git a/drivers/nvmem/stm32-romem.c b/drivers/nvmem/stm32-romem.c index d1d03c2ad081..ba779e26937a 100644 --- a/drivers/nvmem/stm32-romem.c +++ b/drivers/nvmem/stm32-romem.c @@ -11,6 +11,9 @@ #include #include #include +#include + +#include "stm32-bsec-optee-ta.h" /* BSEC secure service access from non-secure */ #define STM32_SMC_BSEC 0x82001003 @@ -25,12 +28,14 @@ struct stm32_romem_cfg { int size; u8 lower; + bool ta; }; struct stm32_romem_priv { void __iomem *base; struct nvmem_config cfg; u8 lower; + struct tee_context *ctx; }; static int stm32_romem_read(void *context, unsigned int offset, void *buf, @@ -138,12 +143,54 @@ static int stm32_bsec_write(void *context, unsigned int offset, void *buf, return 0; } +static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf, + size_t bytes) +{ + struct stm32_romem_priv *priv = context; + + return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes); +} + +static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf, + size_t bytes) +{ + struct stm32_romem_priv *priv = context; + + return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes); +} + +static bool stm32_bsec_smc_check(void) +{ + u32 val; + int ret; + + /* check that the OP-TEE support the BSEC SMC (legacy mode) */ + ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val); + + return !ret; +} + +static bool optee_presence_check(void) +{ + struct device_node *np; + bool tee_detected = false; + + /* check that the OP-TEE node is present and available. */ + np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz"); + if (np && of_device_is_available(np)) + tee_detected = true; + of_node_put(np); + + return tee_detected; +} + static int stm32_romem_probe(struct platform_device *pdev) { const struct stm32_romem_cfg *cfg; struct device *dev = &pdev->dev; struct stm32_romem_priv *priv; struct resource *res; + int rc; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -173,15 +220,36 @@ static int stm32_romem_probe(struct platform_device *pdev) } else { priv->cfg.size = cfg->size; priv->lower = cfg->lower; - priv->cfg.reg_read = stm32_bsec_read; - priv->cfg.reg_write = stm32_bsec_write; + if (cfg->ta || optee_presence_check()) { + rc = stm32_bsec_optee_ta_open(&priv->ctx); + if (rc) { + /* wait for OP-TEE client driver to be up and ready */ + if (rc == -EPROBE_DEFER) + return -EPROBE_DEFER; + /* BSEC PTA is required or SMC not supported */ + if (cfg->ta || !stm32_bsec_smc_check()) + return rc; + } + } + if (priv->ctx) { + rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx); + if (rc) { + dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc); + return rc; + } + priv->cfg.reg_read = stm32_bsec_pta_read; + priv->cfg.reg_write = stm32_bsec_pta_write; + } else { + priv->cfg.reg_read = stm32_bsec_read; + priv->cfg.reg_write = stm32_bsec_write; + } } return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg)); } /* - * STM32MP15 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits) + * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits) * => 96 x 32-bits data words * - Lower: 1K bits, 2:1 redundancy, incremental bit programming * => 32 (x 32-bits) lower shadow registers = words 0 to 31 @@ -191,6 +259,13 @@ static int stm32_romem_probe(struct platform_device *pdev) static const struct stm32_romem_cfg stm32mp15_bsec_cfg = { .size = 384, .lower = 32, + .ta = false, +}; + +static const struct stm32_romem_cfg stm32mp13_bsec_cfg = { + .size = 384, + .lower = 32, + .ta = true, }; static const struct of_device_id stm32_romem_of_match[] = { @@ -198,7 +273,10 @@ static const struct of_device_id stm32_romem_of_match[] = { .compatible = "st,stm32mp15-bsec", .data = (void *)&stm32mp15_bsec_cfg, }, { + .compatible = "st,stm32mp13-bsec", + .data = (void *)&stm32mp13_bsec_cfg, }, + { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, stm32_romem_of_match); diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index 92dfe4cb10e3..a970f1741cc6 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -197,15 +197,9 @@ static const struct sunxi_sid_cfg sun8i_h3_cfg = { .need_register_readout = true, }; -static const struct sunxi_sid_cfg sun20i_d1_cfg = { - .value_offset = 0x200, - .size = 0x100, -}; - static const struct sunxi_sid_cfg sun50i_a64_cfg = { .value_offset = 0x200, .size = 0x100, - .need_register_readout = true, }; static const struct sunxi_sid_cfg sun50i_h6_cfg = { @@ -218,7 +212,7 @@ static const struct of_device_id sunxi_sid_of_match[] = { { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg }, { .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg }, { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg }, - { .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg }, + { .compatible = "allwinner,sun20i-d1-sid", .data = &sun50i_a64_cfg }, { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg }, { .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg }, { .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg }, diff --git a/drivers/of/property.c b/drivers/of/property.c index 134cfc980b70..95b838185b2f 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1202,8 +1202,8 @@ static struct device_node *parse_prop_cells(struct device_node *np, if (strcmp(prop_name, list_name)) return NULL; - if (of_parse_phandle_with_args(np, list_name, cells_name, index, - &sup_args)) + if (__of_parse_phandle_with_args(np, list_name, cells_name, 0, index, + &sup_args)) return NULL; return sup_args.np; @@ -1307,7 +1307,7 @@ DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-cells") DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells") DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells") DEFINE_SIMPLE_PROP(extcon, "extcon", NULL) -DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", NULL) +DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", "#nvmem-cell-cells") DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells") DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL) DEFINE_SIMPLE_PROP(pinctrl0, "pinctrl-0", NULL) diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c index 5784dc20fb38..88e125e36230 100644 --- a/drivers/parport/parport_pc.c +++ b/drivers/parport/parport_pc.c @@ -106,15 +106,22 @@ static int pnp_registered_parport; static void frob_econtrol(struct parport *pb, unsigned char m, unsigned char v) { + const struct parport_pc_private *priv = pb->physport->private_data; + unsigned char ecr_writable = priv->ecr_writable; unsigned char ectr = 0; + unsigned char new; if (m != 0xff) ectr = inb(ECONTROL(pb)); - pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", - m, v, ectr, (ectr & ~m) ^ v); + new = (ectr & ~m) ^ v; + if (ecr_writable) + /* All known users of the ECR mask require bit 0 to be set. */ + new = (new & ecr_writable) | 1; - outb((ectr & ~m) ^ v, ECONTROL(pb)); + pr_debug("frob_econtrol(%02x,%02x): %02x -> %02x\n", m, v, ectr, new); + + outb(new, ECONTROL(pb)); } static inline void frob_set_mode(struct parport *p, int mode) @@ -1479,22 +1486,25 @@ static int parport_ECR_present(struct parport *pb) struct parport_pc_private *priv = pb->private_data; unsigned char r = 0xc; - outb(r, CONTROL(pb)); - if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { - outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ + if (!priv->ecr_writable) { + outb(r, CONTROL(pb)); + if ((inb(ECONTROL(pb)) & 0x3) == (r & 0x3)) { + outb(r ^ 0x2, CONTROL(pb)); /* Toggle bit 1 */ - r = inb(CONTROL(pb)); - if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) - goto no_reg; /* Sure that no ECR register exists */ + r = inb(CONTROL(pb)); + if ((inb(ECONTROL(pb)) & 0x2) == (r & 0x2)) + /* Sure that no ECR register exists */ + goto no_reg; + } + + if ((inb(ECONTROL(pb)) & 0x3) != 0x1) + goto no_reg; + + ECR_WRITE(pb, 0x34); + if (inb(ECONTROL(pb)) != 0x35) + goto no_reg; } - if ((inb(ECONTROL(pb)) & 0x3) != 0x1) - goto no_reg; - - ECR_WRITE(pb, 0x34); - if (inb(ECONTROL(pb)) != 0x35) - goto no_reg; - priv->ecr = 1; outb(0xc, CONTROL(pb)); @@ -2000,11 +2010,13 @@ static int parport_dma_probe(struct parport *p) static LIST_HEAD(ports_list); static DEFINE_SPINLOCK(ports_lock); -struct parport *parport_pc_probe_port(unsigned long int base, - unsigned long int base_hi, - int irq, int dma, - struct device *dev, - int irqflags) +static struct parport *__parport_pc_probe_port(unsigned long int base, + unsigned long int base_hi, + int irq, int dma, + struct device *dev, + int irqflags, + unsigned int mode_mask, + unsigned char ecr_writable) { struct parport_pc_private *priv; struct parport_operations *ops; @@ -2053,6 +2065,7 @@ struct parport *parport_pc_probe_port(unsigned long int base, priv->ctr = 0xc; priv->ctr_writable = ~0x10; priv->ecr = 0; + priv->ecr_writable = ecr_writable; priv->fifo_depth = 0; priv->dma_buf = NULL; priv->dma_handle = 0; @@ -2116,22 +2129,30 @@ struct parport *parport_pc_probe_port(unsigned long int base, p->dma != PARPORT_DMA_NOFIFO && priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) { p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT; - p->ops->compat_write_data = parport_pc_compat_write_block_pio; -#ifdef CONFIG_PARPORT_1284 - p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; - /* currently broken, but working on it.. (FB) */ - /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */ -#endif /* IEEE 1284 support */ - if (p->dma != PARPORT_DMA_NONE) { - pr_cont(", dma %d", p->dma); + if (p->dma != PARPORT_DMA_NONE) p->modes |= PARPORT_MODE_DMA; - } else - pr_cont(", using FIFO"); } else /* We can't use the DMA channel after all. */ p->dma = PARPORT_DMA_NONE; #endif /* Allowed to use FIFO/DMA */ + p->modes &= ~mode_mask; + +#ifdef CONFIG_PARPORT_PC_FIFO + if ((p->modes & PARPORT_MODE_COMPAT) != 0) + p->ops->compat_write_data = parport_pc_compat_write_block_pio; +#ifdef CONFIG_PARPORT_1284 + if ((p->modes & PARPORT_MODE_ECP) != 0) + p->ops->ecp_write_data = parport_pc_ecp_write_block_pio; +#endif + if ((p->modes & (PARPORT_MODE_ECP | PARPORT_MODE_COMPAT)) != 0) { + if ((p->modes & PARPORT_MODE_DMA) != 0) + pr_cont(", dma %d", p->dma); + else + pr_cont(", using FIFO"); + } +#endif /* Allowed to use FIFO/DMA */ + pr_cont(" ["); #define printmode(x) \ @@ -2239,6 +2260,16 @@ out1: platform_device_unregister(pdev); return NULL; } + +struct parport *parport_pc_probe_port(unsigned long int base, + unsigned long int base_hi, + int irq, int dma, + struct device *dev, + int irqflags) +{ + return __parport_pc_probe_port(base, base_hi, irq, dma, + dev, irqflags, 0, 0); +} EXPORT_SYMBOL(parport_pc_probe_port); void parport_pc_unregister_port(struct parport *p) @@ -2626,7 +2657,14 @@ static struct parport_pc_pci { int lo; int hi; /* -1 if not there, >6 for offset-method (max BAR is 6) */ - } addr[4]; + } addr[2]; + + /* Bit field of parport modes to exclude. */ + unsigned int mode_mask; + + /* If non-zero, sets the bitmask of writable ECR bits. In that + * case additionally bit 0 will be forcibly set on writes. */ + unsigned char ecr_writable; /* If set, this is called immediately after pci_enable_device. * If it returns non-zero, no probing will take place and the @@ -2658,12 +2696,19 @@ static struct parport_pc_pci { /* titan_010l */ { 1, { { 3, -1 }, } }, /* avlab_1p */ { 1, { { 0, 1}, } }, /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} }, - /* The Oxford Semi cards are unusual: 954 doesn't support ECP, - * and 840 locks up if you write 1 to bit 2! */ - /* oxsemi_952 */ { 1, { { 0, 1 }, } }, - /* oxsemi_954 */ { 1, { { 0, -1 }, } }, - /* oxsemi_840 */ { 1, { { 0, 1 }, } }, - /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } }, + /* The Oxford Semi cards are unusual: older variants of 954 don't + * support ECP, and 840 locks up if you write 1 to bit 2! None + * implement nFault or service interrupts and all require 00001 + * bit pattern to be used for bits 4:0 with ECR writes. */ + /* oxsemi_952 */ { 1, { { 0, 1 }, }, + PARPORT_MODE_COMPAT, ECR_MODE_MASK }, + /* oxsemi_954 */ { 1, { { 0, 1 }, }, + PARPORT_MODE_ECP | + PARPORT_MODE_COMPAT, ECR_MODE_MASK }, + /* oxsemi_840 */ { 1, { { 0, 1 }, }, + PARPORT_MODE_COMPAT, ECR_MODE_MASK }, + /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, }, + PARPORT_MODE_COMPAT, ECR_MODE_MASK }, /* aks_0100 */ { 1, { { 0, -1 }, } }, /* mobility_pp */ { 1, { { 0, 1 }, } }, /* netmos_9900 */ { 1, { { 0, -1 }, } }, @@ -2831,9 +2876,11 @@ static int parport_pc_pci_probe(struct pci_dev *dev, id->vendor, id->device, io_lo, io_hi, irq); } data->ports[count] = - parport_pc_probe_port(io_lo, io_hi, irq, - PARPORT_DMA_NONE, &dev->dev, - IRQF_SHARED); + __parport_pc_probe_port(io_lo, io_hi, irq, + PARPORT_DMA_NONE, &dev->dev, + IRQF_SHARED, + cards[i].mode_mask, + cards[i].ecr_writable); if (data->ports[count]) count++; } diff --git a/drivers/pps/clients/pps-ldisc.c b/drivers/pps/clients/pps-ldisc.c index d73c4c2ed4e1..443d6bae19d1 100644 --- a/drivers/pps/clients/pps-ldisc.c +++ b/drivers/pps/clients/pps-ldisc.c @@ -13,7 +13,7 @@ #include #include -static void pps_tty_dcd_change(struct tty_struct *tty, unsigned int status) +static void pps_tty_dcd_change(struct tty_struct *tty, bool active) { struct pps_device *pps; struct pps_event_time ts; @@ -29,11 +29,11 @@ static void pps_tty_dcd_change(struct tty_struct *tty, unsigned int status) return; /* Now do the PPS event report */ - pps_event(pps, &ts, status ? PPS_CAPTUREASSERT : + pps_event(pps, &ts, active ? PPS_CAPTUREASSERT : PPS_CAPTURECLEAR, NULL); dev_dbg(pps->dev, "PPS %s at %lu\n", - status ? "assert" : "clear", jiffies); + active ? "assert" : "clear", jiffies); } static int (*alias_n_tty_open)(struct tty_struct *tty); diff --git a/drivers/s390/char/con3215.c b/drivers/s390/char/con3215.c index 72ba83c1bc79..0b05cd76b7d0 100644 --- a/drivers/s390/char/con3215.c +++ b/drivers/s390/char/con3215.c @@ -629,7 +629,7 @@ static int raw3215_startup(struct raw3215_info *raw) if (tty_port_initialized(&raw->port)) return 0; raw->line_pos = 0; - tty_port_set_initialized(&raw->port, 1); + tty_port_set_initialized(&raw->port, true); spin_lock_irqsave(get_ccwdev_lock(raw->cdev), flags); raw3215_try_io(raw); spin_unlock_irqrestore(get_ccwdev_lock(raw->cdev), flags); @@ -659,7 +659,7 @@ static void raw3215_shutdown(struct raw3215_info *raw) spin_lock_irqsave(get_ccwdev_lock(raw->cdev), flags); remove_wait_queue(&raw->empty_wait, &wait); set_current_state(TASK_RUNNING); - tty_port_set_initialized(&raw->port, 1); + tty_port_set_initialized(&raw->port, true); } spin_unlock_irqrestore(get_ccwdev_lock(raw->cdev), flags); } diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index f0475b93ca73..795a2e1d59b3 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include /** * DOC: Overview diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index e1b2e0b65779..babb039bcb43 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/staging/emxx_udc/emxx_udc.c b/drivers/staging/emxx_udc/emxx_udc.c index b4e19174bef2..f9765841c4aa 100644 --- a/drivers/staging/emxx_udc/emxx_udc.c +++ b/drivers/staging/emxx_udc/emxx_udc.c @@ -2587,10 +2587,15 @@ static int nbu2ss_ep_queue(struct usb_ep *_ep, req->unaligned = false; if (req->unaligned) { - if (!ep->virt_buf) + if (!ep->virt_buf) { ep->virt_buf = dma_alloc_coherent(udc->dev, PAGE_SIZE, &ep->phys_buf, GFP_ATOMIC | GFP_DMA); + if (!ep->virt_buf) { + spin_unlock_irqrestore(&udc->lock, flags); + return -ENOMEM; + } + } if (ep->epnum > 0) { if (ep->direct == USB_DIR_IN) memcpy(ep->virt_buf, req->req.buf, diff --git a/drivers/staging/greybus/gpio.c b/drivers/staging/greybus/gpio.c index 8a7cf1d0e968..d729b922a750 100644 --- a/drivers/staging/greybus/gpio.c +++ b/drivers/staging/greybus/gpio.c @@ -43,7 +43,11 @@ struct gb_gpio_controller { }; #define gpio_chip_to_gb_gpio_controller(chip) \ container_of(chip, struct gb_gpio_controller, chip) -#define irq_data_to_gpio_chip(d) (d->domain->host_data) + +static struct gpio_chip *irq_data_to_gpio_chip(struct irq_data *d) +{ + return d->domain->host_data; +} static int gb_gpio_line_count_operation(struct gb_gpio_controller *ggc) { diff --git a/drivers/staging/greybus/uart.c b/drivers/staging/greybus/uart.c index 90ff07f2cbf7..20a34599859f 100644 --- a/drivers/staging/greybus/uart.c +++ b/drivers/staging/greybus/uart.c @@ -701,7 +701,7 @@ static int gb_tty_ioctl(struct tty_struct *tty, unsigned int cmd, return -ENOIOCTLCMD; } -static void gb_tty_dtr_rts(struct tty_port *port, int on) +static void gb_tty_dtr_rts(struct tty_port *port, bool active) { struct gb_tty *gb_tty; u8 newctrl; @@ -709,7 +709,7 @@ static void gb_tty_dtr_rts(struct tty_port *port, int on) gb_tty = container_of(port, struct gb_tty, port); newctrl = gb_tty->ctrlout; - if (on) + if (active) newctrl |= (GB_UART_CTRL_DTR | GB_UART_CTRL_RTS); else newctrl &= ~(GB_UART_CTRL_DTR | GB_UART_CTRL_RTS); diff --git a/drivers/staging/greybus/usb.c b/drivers/staging/greybus/usb.c index 8e9d9d59a357..b7badf87a3f0 100644 --- a/drivers/staging/greybus/usb.c +++ b/drivers/staging/greybus/usb.c @@ -27,7 +27,7 @@ struct gb_usb_hub_control_request { }; struct gb_usb_hub_control_response { - u8 buf[0]; + DECLARE_FLEX_ARRAY(u8, buf); }; struct gb_usb_device { diff --git a/drivers/staging/ks7010/ks_wlan_net.c b/drivers/staging/ks7010/ks_wlan_net.c index 044c807ca022..e03c87f0bfe7 100644 --- a/drivers/staging/ks7010/ks_wlan_net.c +++ b/drivers/staging/ks7010/ks_wlan_net.c @@ -382,8 +382,7 @@ static int ks_wlan_get_nick(struct net_device *dev, return -EPERM; /* for SLEEP MODE */ - strncpy(extra, priv->nick, 16); - extra[16] = '\0'; + strscpy(extra, priv->nick, 17); dwrq->data.length = strlen(extra) + 1; return 0; diff --git a/drivers/staging/pi433/TODO b/drivers/staging/pi433/TODO index 5cf3fd99d521..23c808fc99de 100644 --- a/drivers/staging/pi433/TODO +++ b/drivers/staging/pi433/TODO @@ -3,3 +3,6 @@ * Some missing data (marked with ###) needs to be added in the documentation * Change (struct pi433_tx_cfg)->bit_rate to be a u32 so that we can support bit rates up to 300kbps per the spec. + -> This configuration needs to be moved to sysfs instead of being done through + IOCTL. Going forward, we need to port userspace tools to use sysfs instead + of IOCTL and then we would delete IOCTL. diff --git a/drivers/staging/pi433/pi433_if.c b/drivers/staging/pi433/pi433_if.c index d4e06a3929f3..b59f6a4cb611 100644 --- a/drivers/staging/pi433/pi433_if.c +++ b/drivers/staging/pi433/pi433_if.c @@ -55,6 +55,7 @@ static dev_t pi433_dev; static DEFINE_IDR(pi433_idr); static DEFINE_MUTEX(minor_lock); /* Protect idr accesses */ +static struct dentry *root_dir; /* debugfs root directory for the driver */ static struct class *pi433_class; /* mainly for udev to create /dev/pi433 */ @@ -1306,8 +1307,7 @@ static int pi433_probe(struct spi_device *spi) /* spi setup */ spi_set_drvdata(spi, device); - entry = debugfs_create_dir(dev_name(device->dev), - debugfs_lookup(KBUILD_MODNAME, NULL)); + entry = debugfs_create_dir(dev_name(device->dev), root_dir); debugfs_create_file("regs", 0400, entry, device, &pi433_debugfs_regs_fops); return 0; @@ -1333,9 +1333,8 @@ RX_failed: static void pi433_remove(struct spi_device *spi) { struct pi433_device *device = spi_get_drvdata(spi); - struct dentry *mod_entry = debugfs_lookup(KBUILD_MODNAME, NULL); - debugfs_remove(debugfs_lookup(dev_name(device->dev), mod_entry)); + debugfs_lookup_and_remove(dev_name(device->dev), root_dir); /* free GPIOs */ free_gpio(device); @@ -1408,7 +1407,7 @@ static int __init pi433_init(void) return PTR_ERR(pi433_class); } - debugfs_create_dir(KBUILD_MODNAME, NULL); + root_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); status = spi_register_driver(&pi433_spi_driver); if (status < 0) { @@ -1427,7 +1426,7 @@ static void __exit pi433_exit(void) spi_unregister_driver(&pi433_spi_driver); class_destroy(pi433_class); unregister_chrdev(MAJOR(pi433_dev), pi433_spi_driver.driver.name); - debugfs_remove_recursive(debugfs_lookup(KBUILD_MODNAME, NULL)); + debugfs_remove(root_dir); } module_exit(pi433_exit); diff --git a/drivers/staging/r8188eu/core/rtw_cmd.c b/drivers/staging/r8188eu/core/rtw_cmd.c index 19b2f73d481d..ca9e3d4ee7f4 100644 --- a/drivers/staging/r8188eu/core/rtw_cmd.c +++ b/drivers/staging/r8188eu/core/rtw_cmd.c @@ -28,32 +28,6 @@ void rtw_free_evt_priv(struct evt_priv *pevtpriv) } } -/* Calling Context: - * - * rtw_enqueue_cmd can only be called between kernel thread, - * since only spin_lock is used. - * - * ISR/Call-Back functions can't call this sub-function. - */ - -static int _rtw_enqueue_cmd(struct __queue *queue, struct cmd_obj *obj) -{ - unsigned long flags; - - if (!obj) - goto exit; - - spin_lock_irqsave(&queue->lock, flags); - - list_add_tail(&obj->list, &queue->queue); - - spin_unlock_irqrestore(&queue->lock, flags); - -exit: - - return _SUCCESS; -} - int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) { init_completion(&pcmdpriv->enqueue_cmd); @@ -65,8 +39,6 @@ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ - pcmdpriv->cmd_seq = 1; - pcmdpriv->cmd_allocated_buf = kzalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ, GFP_KERNEL); @@ -127,28 +99,25 @@ static int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) { - int res = _FAIL; + unsigned long flags; struct adapter *padapter = pcmdpriv->padapter; if (!cmd_obj) - goto exit; + return _FAIL; cmd_obj->padapter = padapter; - res = rtw_cmd_filter(pcmdpriv, cmd_obj); - if (res == _FAIL) { + if (rtw_cmd_filter(pcmdpriv, cmd_obj) == _FAIL) { rtw_free_cmd_obj(cmd_obj); - goto exit; + return _FAIL; } - res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj); + spin_lock_irqsave(&pcmdpriv->cmd_queue.lock, flags); + list_add_tail(&cmd_obj->list, &pcmdpriv->cmd_queue.queue); + spin_unlock_irqrestore(&pcmdpriv->cmd_queue.lock, flags); - if (res == _SUCCESS) - complete(&pcmdpriv->enqueue_cmd); - -exit: - - return res; + complete(&pcmdpriv->enqueue_cmd); + return _SUCCESS; } struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) @@ -233,8 +202,6 @@ _next: ret = cmd_hdl(pcmd->padapter, pcmdbuf); pcmd->res = ret; } - - pcmdpriv->cmd_seq++; } else { pcmd->res = H2C_PARAMETERS_ERROR; } @@ -1201,24 +1168,20 @@ static void rtw_chk_hi_queue_hdl(struct adapter *padapter) } } -u8 rtw_chk_hi_queue_cmd(struct adapter *padapter) +void rtw_chk_hi_queue_cmd(struct adapter *padapter) { struct cmd_obj *ph2c; struct drvextra_cmd_parm *pdrvextra_cmd_parm; struct cmd_priv *pcmdpriv = &padapter->cmdpriv; - u8 res = _SUCCESS; ph2c = kzalloc(sizeof(*ph2c), GFP_ATOMIC); - if (!ph2c) { - res = _FAIL; - goto exit; - } + if (!ph2c) + return; pdrvextra_cmd_parm = kzalloc(sizeof(*pdrvextra_cmd_parm), GFP_ATOMIC); if (!pdrvextra_cmd_parm) { kfree(ph2c); - res = _FAIL; - goto exit; + return; } pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID; @@ -1227,9 +1190,7 @@ u8 rtw_chk_hi_queue_cmd(struct adapter *padapter) init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); - res = rtw_enqueue_cmd(pcmdpriv, ph2c); -exit: - return res; + rtw_enqueue_cmd(pcmdpriv, ph2c); } u8 rtw_c2h_wk_cmd(struct adapter *padapter, u8 *c2h_evt) diff --git a/drivers/staging/r8188eu/core/rtw_fw.c b/drivers/staging/r8188eu/core/rtw_fw.c index 682c65b1e04c..1e4baf74ecd5 100644 --- a/drivers/staging/r8188eu/core/rtw_fw.c +++ b/drivers/staging/r8188eu/core/rtw_fw.c @@ -89,9 +89,8 @@ static int block_write(struct adapter *padapter, u8 *buffer, u32 size) addr = FW_8188E_START_ADDRESS + i * block_size; data = buffer + i * block_size; - ret = rtw_writeN(padapter, addr, block_size, data); - if (ret == _FAIL) - goto exit; + if (rtw_writeN(padapter, addr, block_size, data)) + return _FAIL; } if (remain) { @@ -105,9 +104,8 @@ static int block_write(struct adapter *padapter, u8 *buffer, u32 size) addr = FW_8188E_START_ADDRESS + offset + i * block_size; data = buffer + offset + i * block_size; - ret = rtw_writeN(padapter, addr, block_size, data); - if (ret == _FAIL) - goto exit; + if (rtw_writeN(padapter, addr, block_size, data)) + return _FAIL; } } diff --git a/drivers/staging/r8188eu/core/rtw_mlme.c b/drivers/staging/r8188eu/core/rtw_mlme.c index b272123626ac..fb7d0e161fdd 100644 --- a/drivers/staging/r8188eu/core/rtw_mlme.c +++ b/drivers/staging/r8188eu/core/rtw_mlme.c @@ -444,8 +444,6 @@ static void update_current_network(struct adapter *adapter, struct wlan_bssid_ex if (check_fwstate(pmlmepriv, _FW_LINKED) && is_same_network(&pmlmepriv->cur_network.network, pnetwork)) { update_network(&pmlmepriv->cur_network.network, pnetwork, adapter, true); - rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(struct ndis_802_11_fixed_ie), - pmlmepriv->cur_network.network.IELength); } } @@ -1027,9 +1025,6 @@ static void rtw_joinbss_update_network(struct adapter *padapter, struct wlan_net break; } - rtw_update_protection(padapter, (cur_network->network.IEs) + - sizeof(struct ndis_802_11_fixed_ie), - (cur_network->network.IELength)); rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength); } diff --git a/drivers/staging/r8188eu/core/rtw_mlme_ext.c b/drivers/staging/r8188eu/core/rtw_mlme_ext.c index 1b9cf7596a76..dc181e491b34 100644 --- a/drivers/staging/r8188eu/core/rtw_mlme_ext.c +++ b/drivers/staging/r8188eu/core/rtw_mlme_ext.c @@ -3735,35 +3735,18 @@ static unsigned int on_action_public_p2p(struct recv_frame *precv_frame) return _SUCCESS; } -static void on_action_public_vendor(struct recv_frame *precv_frame) -{ - u8 *pframe = precv_frame->rx_data; - u8 *frame_body = pframe + sizeof(struct ieee80211_hdr_3addr); - - if (!memcmp(frame_body + 2, P2P_OUI, 4)) - on_action_public_p2p(precv_frame); -} - -static void on_action_public_default(struct recv_frame *precv_frame) -{ - u8 *pframe = precv_frame->rx_data; - u8 *frame_body = pframe + sizeof(struct ieee80211_hdr_3addr); - u8 token; - - token = frame_body[2]; - - rtw_action_public_decache(precv_frame, token); -} - static void on_action_public(struct adapter *padapter, struct recv_frame *precv_frame) { struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)precv_frame->rx_data; + u8 *frame_body = (u8 *)&mgmt->u; /* All members of the action enum start with action_code. */ - if (mgmt->u.action.u.s1g.action_code == WLAN_PUB_ACTION_VENDOR_SPECIFIC) - on_action_public_vendor(precv_frame); - else - on_action_public_default(precv_frame); + if (mgmt->u.action.u.s1g.action_code == WLAN_PUB_ACTION_VENDOR_SPECIFIC) { + if (!memcmp(frame_body + 2, P2P_OUI, 4)) + on_action_public_p2p(precv_frame); + } else { + rtw_action_public_decache(precv_frame, frame_body[2]); + } } static void OnAction_p2p(struct adapter *padapter, struct recv_frame *precv_frame) diff --git a/drivers/staging/r8188eu/core/rtw_pwrctrl.c b/drivers/staging/r8188eu/core/rtw_pwrctrl.c index 5290ac36f08c..051cdcb11ff5 100644 --- a/drivers/staging/r8188eu/core/rtw_pwrctrl.c +++ b/drivers/staging/r8188eu/core/rtw_pwrctrl.c @@ -8,7 +8,7 @@ #include "../include/osdep_intf.h" #include "../include/linux/usb.h" -void ips_enter(struct adapter *padapter) +static void ips_enter(struct adapter *padapter) { struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; struct xmit_priv *pxmit_priv = &padapter->xmitpriv; @@ -25,21 +25,20 @@ void ips_enter(struct adapter *padapter) pwrpriv->ips_mode = pwrpriv->ips_mode_req; pwrpriv->ips_enter_cnts++; - if (rf_off == pwrpriv->change_rfpwrstate) { - pwrpriv->bpower_saving = true; + pwrpriv->bpower_saving = true; - if (pwrpriv->ips_mode == IPS_LEVEL_2) - pwrpriv->bkeepfwalive = true; + if (pwrpriv->ips_mode == IPS_LEVEL_2) + pwrpriv->bkeepfwalive = true; + + rtw_ips_pwr_down(padapter); + pwrpriv->rf_pwrstate = rf_off; - rtw_ips_pwr_down(padapter); - pwrpriv->rf_pwrstate = rf_off; - } pwrpriv->bips_processing = false; mutex_unlock(&pwrpriv->lock); } -int ips_leave(struct adapter *padapter) +static int ips_leave(struct adapter *padapter) { struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; struct security_priv *psecuritypriv = &padapter->securitypriv; @@ -51,7 +50,6 @@ int ips_leave(struct adapter *padapter) if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) { pwrpriv->bips_processing = true; - pwrpriv->change_rfpwrstate = rf_on; pwrpriv->ips_leave_cnts++; result = rtw_ips_pwr_up(padapter); @@ -133,10 +131,9 @@ void rtw_ps_processor(struct adapter *padapter) if (!rtw_pwr_unassociated_idle(padapter)) goto exit; - if (pwrpriv->rf_pwrstate == rf_on) { - pwrpriv->change_rfpwrstate = rf_off; + if (pwrpriv->rf_pwrstate == rf_on) ips_enter(padapter); - } + exit: rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv); pwrpriv->ps_processing = false; diff --git a/drivers/staging/r8188eu/core/rtw_recv.c b/drivers/staging/r8188eu/core/rtw_recv.c index 631c500dda42..fc7568cf948b 100644 --- a/drivers/staging/r8188eu/core/rtw_recv.c +++ b/drivers/staging/r8188eu/core/rtw_recv.c @@ -38,7 +38,7 @@ void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) static int rtl8188eu_init_recv_priv(struct adapter *padapter) { struct recv_priv *precvpriv = &padapter->recvpriv; - int i, res = _SUCCESS; + int i, err = 0; struct recv_buf *precvbuf; tasklet_init(&precvpriv->recv_tasklet, @@ -50,10 +50,8 @@ static int rtl8188eu_init_recv_priv(struct adapter *padapter) precvpriv->pallocated_recv_buf = kzalloc(NR_RECVBUFF * sizeof(struct recv_buf) + 4, GFP_KERNEL); - if (!precvpriv->pallocated_recv_buf) { - res = _FAIL; - goto exit; - } + if (!precvpriv->pallocated_recv_buf) + return -ENOMEM; precvpriv->precv_buf = (u8 *)ALIGN((size_t)(precvpriv->pallocated_recv_buf), 4); @@ -64,7 +62,7 @@ static int rtl8188eu_init_recv_priv(struct adapter *padapter) precvbuf->reuse = false; precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL); if (!precvbuf->purb) { - res = _FAIL; + err = -ENOMEM; break; } precvbuf->adapter = padapter; @@ -94,17 +92,15 @@ static int rtl8188eu_init_recv_priv(struct adapter *padapter) pskb = NULL; } } -exit: - return res; + + return err; } int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter) { int i; - struct recv_frame *precvframe; - - int res = _SUCCESS; + int err; spin_lock_init(&precvpriv->lock); @@ -117,11 +113,8 @@ int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter) precvpriv->free_recvframe_cnt = NR_RECVFRAME; precvpriv->pallocated_frame_buf = vzalloc(NR_RECVFRAME * sizeof(struct recv_frame) + RXFRAME_ALIGN_SZ); - - if (!precvpriv->pallocated_frame_buf) { - res = _FAIL; - goto exit; - } + if (!precvpriv->pallocated_frame_buf) + return -ENOMEM; precvpriv->precv_frame_buf = (u8 *)ALIGN((size_t)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ); @@ -141,15 +134,14 @@ int _rtw_init_recv_priv(struct recv_priv *precvpriv, struct adapter *padapter) } precvpriv->rx_pending_cnt = 1; - res = rtl8188eu_init_recv_priv(padapter); + err = rtl8188eu_init_recv_priv(padapter); timer_setup(&precvpriv->signal_stat_timer, rtw_signal_stat_timer_hdl, 0); precvpriv->signal_stat_sampling_interval = 1000; /* ms */ rtw_set_signal_stat_timer(precvpriv); -exit: - return res; + return err; } static void rtl8188eu_free_recv_priv(struct adapter *padapter) diff --git a/drivers/staging/r8188eu/core/rtw_sta_mgt.c b/drivers/staging/r8188eu/core/rtw_sta_mgt.c index b4aee8623099..e1ae1859686e 100644 --- a/drivers/staging/r8188eu/core/rtw_sta_mgt.c +++ b/drivers/staging/r8188eu/core/rtw_sta_mgt.c @@ -260,22 +260,22 @@ void rtw_free_stainfo(struct adapter *padapter, struct sta_info *psta) spin_lock_bh(&pxmitpriv->lock); - rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q); + rtw_free_xmitframe_list(pxmitpriv, get_list_head(&psta->sleep_q)); psta->sleepq_len = 0; - rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); + rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); list_del_init(&pstaxmitpriv->vo_q.tx_pending); - rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); + rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); list_del_init(&pstaxmitpriv->vi_q.tx_pending); - rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); + rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); list_del_init(&pstaxmitpriv->bk_q.tx_pending); - rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending); + rtw_free_xmitframe_list(pxmitpriv, &pstaxmitpriv->be_q.sta_pending); list_del_init(&pstaxmitpriv->be_q.tx_pending); @@ -391,8 +391,7 @@ void rtw_free_all_stainfo(struct adapter *padapter) /* any station allocated can be searched by hash list */ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) { - struct list_head *plist, *phead; - struct sta_info *psta = NULL; + struct sta_info *ploop, *psta = NULL; u32 index; u8 *addr; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; @@ -409,18 +408,11 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) spin_lock_bh(&pstapriv->sta_hash_lock); - phead = &pstapriv->sta_hash[index]; - plist = phead->next; - - while (phead != plist) { - psta = container_of(plist, struct sta_info, hash_list); - - if ((!memcmp(psta->hwaddr, addr, ETH_ALEN))) { - /* if found the matched address */ + list_for_each_entry(ploop, &pstapriv->sta_hash[index], hash_list) { + if (!memcmp(ploop->hwaddr, addr, ETH_ALEN)) { + psta = ploop; break; } - psta = NULL; - plist = plist->next; } spin_unlock_bh(&pstapriv->sta_hash_lock); diff --git a/drivers/staging/r8188eu/core/rtw_xmit.c b/drivers/staging/r8188eu/core/rtw_xmit.c index 34494f08c0cd..df88b3e29e77 100644 --- a/drivers/staging/r8188eu/core/rtw_xmit.c +++ b/drivers/staging/r8188eu/core/rtw_xmit.c @@ -17,7 +17,7 @@ static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; static void _init_txservq(struct tx_servq *ptxservq) { INIT_LIST_HEAD(&ptxservq->tx_pending); - rtw_init_queue(&ptxservq->sta_pending); + INIT_LIST_HEAD(&ptxservq->sta_pending); ptxservq->qcnt = 0; } @@ -29,8 +29,6 @@ void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) _init_txservq(&psta_xmitpriv->bk_q); _init_txservq(&psta_xmitpriv->vi_q); _init_txservq(&psta_xmitpriv->vo_q); - INIT_LIST_HEAD(&psta_xmitpriv->legacy_dz); - INIT_LIST_HEAD(&psta_xmitpriv->apsd); } static int rtw_xmit_resource_alloc(struct adapter *padapter, struct xmit_buf *pxmitbuf, @@ -41,7 +39,6 @@ static int rtw_xmit_resource_alloc(struct adapter *padapter, struct xmit_buf *px return -ENOMEM; pxmitbuf->pbuf = (u8 *)ALIGN((size_t)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); - pxmitbuf->dma_transfer_addr = 0; pxmitbuf->pxmit_urb = usb_alloc_urb(0, GFP_KERNEL); if (!pxmitbuf->pxmit_urb) { @@ -70,7 +67,6 @@ int _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter) /* We don't need to memset padapter->XXX to zero, because adapter is allocated by vzalloc(). */ spin_lock_init(&pxmitpriv->lock); - sema_init(&pxmitpriv->terminate_xmitthread_sema, 0); /* * Please insert all the queue initializaiton using rtw_init_queue below @@ -78,11 +74,10 @@ int _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter) pxmitpriv->adapter = padapter; - rtw_init_queue(&pxmitpriv->be_pending); - rtw_init_queue(&pxmitpriv->bk_pending); - rtw_init_queue(&pxmitpriv->vi_pending); - rtw_init_queue(&pxmitpriv->vo_pending); - rtw_init_queue(&pxmitpriv->bm_pending); + INIT_LIST_HEAD(&pxmitpriv->be_pending); + INIT_LIST_HEAD(&pxmitpriv->bk_pending); + INIT_LIST_HEAD(&pxmitpriv->vi_pending); + INIT_LIST_HEAD(&pxmitpriv->vo_pending); rtw_init_queue(&pxmitpriv->free_xmit_queue); @@ -153,7 +148,7 @@ int _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter) goto free_xmitbuf; } - pxmitbuf->flags = XMIT_VO_QUEUE; + pxmitbuf->high_queue = false; list_add_tail(&pxmitbuf->list, &pxmitpriv->free_xmitbuf_queue.queue); pxmitbuf++; @@ -192,26 +187,14 @@ int _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter) if (rtw_alloc_hwxmits(padapter)) goto free_xmit_extbuf; - rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); - for (i = 0; i < 4; i++) pxmitpriv->wmm_para_seq[i] = i; - pxmitpriv->txirp_cnt = 1; - - sema_init(&pxmitpriv->tx_retevt, 0); - - /* per AC pending irp */ - pxmitpriv->beq_cnt = 0; - pxmitpriv->bkq_cnt = 0; - pxmitpriv->viq_cnt = 0; - pxmitpriv->voq_cnt = 0; - pxmitpriv->ack_tx = false; mutex_init(&pxmitpriv->ack_tx_mutex); rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0); - rtl8188eu_init_xmit_priv(padapter); + tasklet_init(&pxmitpriv->xmit_tasklet, rtl8188eu_xmit_tasklet, (unsigned long)padapter); return 0; @@ -296,7 +279,7 @@ void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) vfree(pxmitpriv->pallocated_xmit_extbuf); - rtw_free_hwxmits(padapter); + kfree(pxmitpriv->hwxmits); mutex_destroy(&pxmitpriv->ack_tx_mutex); } @@ -761,28 +744,27 @@ static s32 xmitframe_addmic(struct adapter *padapter, struct xmit_frame *pxmitfr return _SUCCESS; } -static s32 xmitframe_swencrypt(struct adapter *padapter, struct xmit_frame *pxmitframe) +static void xmitframe_swencrypt(struct adapter *padapter, struct xmit_frame *pxmitframe) { struct pkt_attrib *pattrib = &pxmitframe->attrib; - if (pattrib->bswenc) { - switch (pattrib->encrypt) { - case _WEP40_: - case _WEP104_: - rtw_wep_encrypt(padapter, pxmitframe); - break; - case _TKIP_: - rtw_tkip_encrypt(padapter, pxmitframe); - break; - case _AES_: - rtw_aes_encrypt(padapter, pxmitframe); - break; - default: - break; - } - } + if (!pattrib->bswenc) + return; - return _SUCCESS; + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + rtw_wep_encrypt(padapter, pxmitframe); + break; + case _TKIP_: + rtw_tkip_encrypt(padapter, pxmitframe); + break; + case _AES_: + rtw_aes_encrypt(padapter, pxmitframe); + break; + default: + break; + } } s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib) @@ -792,9 +774,7 @@ s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, struct pkt_attrib *pattr struct ieee80211_hdr *pwlanhdr = (struct ieee80211_hdr *)hdr; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct qos_priv *pqospriv = &pmlmepriv->qospriv; - u8 qos_option = false; - - int res = _SUCCESS; + bool qos_option; __le16 *fctrl = &pwlanhdr->frame_control; struct sta_info *psta; @@ -810,106 +790,99 @@ s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, struct pkt_attrib *pattr SetFrameSubType(fctrl, pattrib->subtype); - if (pattrib->subtype & IEEE80211_FTYPE_DATA) { - if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { - /* to_ds = 1, fr_ds = 0; */ - /* Data transfer to AP */ - SetToDs(fctrl); - memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); - memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + if (!(pattrib->subtype & IEEE80211_FTYPE_DATA)) + return _SUCCESS; - if (pqospriv->qos_option) - qos_option = true; - } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { - /* to_ds = 0, fr_ds = 1; */ - SetFrDs(fctrl); - memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); - memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + /* to_ds = 1, fr_ds = 0; */ + /* Data transfer to AP */ + SetToDs(fctrl); + memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + qos_option = pqospriv->qos_option; + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + /* to_ds = 0, fr_ds = 1; */ + SetFrDs(fctrl); + memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); + memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); + qos_option = psta->qos_option; + } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { + memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + qos_option = psta->qos_option; + } else { + return _FAIL; + } - if (psta->qos_option) - qos_option = true; - } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || - check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { - memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); - memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); - memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + if (pattrib->mdata) + SetMData(fctrl); - if (psta->qos_option) - qos_option = true; - } else { - res = _FAIL; - goto exit; + if (pattrib->encrypt) + SetPrivacy(fctrl); + + if (qos_option) { + qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + } + + /* TODO: fill HT Control Field */ + + /* Update Seq Num will be handled by f/w */ + if (psta) { + psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + + pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; + + SetSeqNum(hdr, pattrib->seqnum); + + /* check if enable ampdu */ + if (pattrib->ht_en && psta->htpriv.ampdu_enable) { + if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) + pattrib->ampdu_en = true; } - if (pattrib->mdata) - SetMData(fctrl); + /* re-check if enable ampdu by BA_starting_seqctrl */ + if (pattrib->ampdu_en) { + u16 tx_seq; - if (pattrib->encrypt) - SetPrivacy(fctrl); + tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; - if (qos_option) { - qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + /* check BA_starting_seqctrl */ + if (SN_LESS(pattrib->seqnum, tx_seq)) { + pattrib->ampdu_en = false;/* AGG BK */ + } else if (SN_EQUAL(pattrib->seqnum, tx_seq)) { + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff; - if (pattrib->priority) - SetPriority(qc, pattrib->priority); - - SetEOSP(qc, pattrib->eosp); - - SetAckpolicy(qc, pattrib->ack_policy); - } - - /* TODO: fill HT Control Field */ - - /* Update Seq Num will be handled by f/w */ - if (psta) { - psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; - psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; - - pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; - - SetSeqNum(hdr, pattrib->seqnum); - - /* check if enable ampdu */ - if (pattrib->ht_en && psta->htpriv.ampdu_enable) { - if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) - pattrib->ampdu_en = true; - } - - /* re-check if enable ampdu by BA_starting_seqctrl */ - if (pattrib->ampdu_en) { - u16 tx_seq; - - tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; - - /* check BA_starting_seqctrl */ - if (SN_LESS(pattrib->seqnum, tx_seq)) { - pattrib->ampdu_en = false;/* AGG BK */ - } else if (SN_EQUAL(pattrib->seqnum, tx_seq)) { - psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff; - - pattrib->ampdu_en = true;/* AGG EN */ - } else { - psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff; - pattrib->ampdu_en = true;/* AGG EN */ - } + pattrib->ampdu_en = true;/* AGG EN */ + } else { + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff; + pattrib->ampdu_en = true;/* AGG EN */ } } } -exit: - return res; + return _SUCCESS; } s32 rtw_txframes_pending(struct adapter *padapter) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - return (!list_empty(&pxmitpriv->be_pending.queue) || - !list_empty(&pxmitpriv->bk_pending.queue) || - !list_empty(&pxmitpriv->vi_pending.queue) || - !list_empty(&pxmitpriv->vo_pending.queue)); + return (!list_empty(&pxmitpriv->be_pending) || + !list_empty(&pxmitpriv->bk_pending) || + !list_empty(&pxmitpriv->vi_pending) || + !list_empty(&pxmitpriv->vo_pending)); } s32 rtw_txframes_sta_ac_pending(struct adapter *padapter, struct pkt_attrib *pattrib) @@ -1010,25 +983,23 @@ s32 rtw_xmitframe_coalesce(struct adapter *padapter, struct sk_buff *pkt, struct /* adding icv, if necessary... */ if (pattrib->iv_len) { - if (psta) { - switch (pattrib->encrypt) { - case _WEP40_: - case _WEP104_: - WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - break; - case _TKIP_: - if (bmcst) - TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - TKIP_IV(pattrib->iv, psta->dot11txpn, 0); - break; - case _AES_: - if (bmcst) - AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); - else - AES_IV(pattrib->iv, psta->dot11txpn, 0); - break; - } + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + case _TKIP_: + if (bmcst) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + break; + case _AES_: + if (bmcst) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + break; } memcpy(pframe, pattrib->iv, pattrib->iv_len); @@ -1126,40 +1097,6 @@ s32 rtw_put_snap(u8 *data, u16 h_proto) return SNAP_SIZE + sizeof(u16); } -void rtw_update_protection(struct adapter *padapter, u8 *ie, uint ie_len) -{ - uint protection; - u8 *perp; - int erp_len; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - struct registry_priv *pregistrypriv = &padapter->registrypriv; - - switch (pxmitpriv->vcs_setting) { - case DISABLE_VCS: - pxmitpriv->vcs = NONE_VCS; - break; - case ENABLE_VCS: - break; - case AUTO_VCS: - default: - perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); - if (!perp) { - pxmitpriv->vcs = NONE_VCS; - } else { - protection = (*(perp + 2)) & BIT(1); - if (protection) { - if (pregistrypriv->vcs_type == RTS_CTS) - pxmitpriv->vcs = RTS_CTS; - else - pxmitpriv->vcs = CTS_TO_SELF; - } else { - pxmitpriv->vcs = NONE_VCS; - } - } - break; - } -} - void rtw_count_tx_stats(struct adapter *padapter, struct xmit_frame *pxmitframe, int sz) { struct sta_info *psta = NULL; @@ -1319,38 +1256,32 @@ struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* _queue *pf spin_lock_bh(&pfree_xmit_queue->lock); - if (list_empty(&pfree_xmit_queue->queue)) { - pxframe = NULL; - } else { - phead = get_list_head(pfree_xmit_queue); + if (list_empty(&pfree_xmit_queue->queue)) + goto out; - plist = phead->next; + phead = get_list_head(pfree_xmit_queue); + plist = phead->next; + pxframe = container_of(plist, struct xmit_frame, list); + list_del_init(&pxframe->list); - pxframe = container_of(plist, struct xmit_frame, list); + pxmitpriv->free_xmitframe_cnt--; - list_del_init(&pxframe->list); - } + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; - if (pxframe) { /* default value setting */ - pxmitpriv->free_xmitframe_cnt--; + memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); + /* pxframe->attrib.psta = NULL; */ - pxframe->buf_addr = NULL; - pxframe->pxmitbuf = NULL; + pxframe->frame_tag = DATA_FRAMETAG; - memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); - /* pxframe->attrib.psta = NULL; */ + pxframe->pkt = NULL; + pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */ - pxframe->frame_tag = DATA_FRAMETAG; - - pxframe->pkt = NULL; - pxframe->pkt_offset = 1;/* default use pkt_offset to fill tx desc */ - - pxframe->agg_num = 1; - pxframe->ack_report = 0; - } + pxframe->agg_num = 1; + pxframe->ack_report = 0; +out: spin_unlock_bh(&pfree_xmit_queue->lock); - return pxframe; } @@ -1386,101 +1317,49 @@ exit: return _SUCCESS; } -void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, struct __queue *pframequeue) +void rtw_free_xmitframe_list(struct xmit_priv *pxmitpriv, struct list_head *xframe_list) { - struct list_head *plist, *phead; - struct xmit_frame *pxmitframe; - - spin_lock_bh(&pframequeue->lock); - - phead = get_list_head(pframequeue); - plist = phead->next; - - while (phead != plist) { - pxmitframe = container_of(plist, struct xmit_frame, list); - - plist = plist->next; + struct xmit_frame *pxmitframe, *tmp_xmitframe; + list_for_each_entry_safe(pxmitframe, tmp_xmitframe, xframe_list, list) rtw_free_xmitframe(pxmitpriv, pxmitframe); - } - spin_unlock_bh(&pframequeue->lock); } -s32 rtw_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe) +struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i) { - if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) { -/* pxmitframe->pkt = NULL; */ - return _FAIL; - } - - return _SUCCESS; -} - -static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, struct __queue *pframe_queue) -{ - struct list_head *xmitframe_plist, *xmitframe_phead; - struct xmit_frame *pxmitframe = NULL; - - xmitframe_phead = get_list_head(pframe_queue); - xmitframe_plist = xmitframe_phead->next; - - if (xmitframe_phead != xmitframe_plist) { - pxmitframe = container_of(xmitframe_plist, struct xmit_frame, list); - - xmitframe_plist = xmitframe_plist->next; - - list_del_init(&pxmitframe->list); - - ptxservq->qcnt--; - } - return pxmitframe; -} - -struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, int entry) -{ - struct list_head *sta_plist, *sta_phead; struct hw_xmit *phwxmit; - struct tx_servq *ptxservq = NULL; - struct __queue *pframe_queue = NULL; + struct tx_servq *ptxservq, *tmp_txservq; + struct list_head *xframe_list; struct xmit_frame *pxmitframe = NULL; struct adapter *padapter = pxmitpriv->adapter; struct registry_priv *pregpriv = &padapter->registrypriv; - int i, inx[4]; - - inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; + int i, inx[] = { 0, 1, 2, 3 }; if (pregpriv->wifi_spec == 1) { - int j; - - for (j = 0; j < 4; j++) - inx[j] = pxmitpriv->wmm_para_seq[j]; + for (i = 0; i < ARRAY_SIZE(inx); i++) + inx[i] = pxmitpriv->wmm_para_seq[i]; } spin_lock_bh(&pxmitpriv->lock); - for (i = 0; i < entry; i++) { + for (i = 0; i < HWXMIT_ENTRY; i++) { phwxmit = phwxmit_i + inx[i]; + list_for_each_entry_safe(ptxservq, tmp_txservq, phwxmit->sta_list, tx_pending) { + xframe_list = &ptxservq->sta_pending; + if (list_empty(xframe_list)) + continue; - sta_phead = get_list_head(phwxmit->sta_queue); - sta_plist = sta_phead->next; + pxmitframe = container_of(xframe_list->next, struct xmit_frame, list); + list_del_init(&pxmitframe->list); - while (sta_phead != sta_plist) { - ptxservq = container_of(sta_plist, struct tx_servq, tx_pending); + phwxmit->accnt--; + ptxservq->qcnt--; - pframe_queue = &ptxservq->sta_pending; + /* Remove sta node when there are no pending packets. */ + if (list_empty(xframe_list)) + list_del_init(&ptxservq->tx_pending); - pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); - - if (pxmitframe) { - phwxmit->accnt--; - - /* Remove sta node when there are no pending packets. */ - if (list_empty(&pframe_queue->queue)) /* must be done after get_next and before break */ - list_del_init(&ptxservq->tx_pending); - goto exit; - } - - sta_plist = sta_plist->next; + goto exit; } } exit: @@ -1547,9 +1426,9 @@ s32 rtw_xmit_classifier(struct adapter *padapter, struct xmit_frame *pxmitframe) ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); if (list_empty(&ptxservq->tx_pending)) - list_add_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); + list_add_tail(&ptxservq->tx_pending, phwxmits[ac_index].sta_list); - list_add_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); + list_add_tail(&pxmitframe->list, &ptxservq->sta_pending); ptxservq->qcnt++; phwxmits[ac_index].accnt++; exit: @@ -1562,39 +1441,20 @@ int rtw_alloc_hwxmits(struct adapter *padapter) struct hw_xmit *hwxmits; struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; - - pxmitpriv->hwxmits = kzalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry, GFP_KERNEL); + pxmitpriv->hwxmits = kcalloc(HWXMIT_ENTRY, sizeof(struct hw_xmit), GFP_KERNEL); if (!pxmitpriv->hwxmits) return -ENOMEM; hwxmits = pxmitpriv->hwxmits; - hwxmits[0].sta_queue = &pxmitpriv->vo_pending; - hwxmits[1].sta_queue = &pxmitpriv->vi_pending; - hwxmits[2].sta_queue = &pxmitpriv->be_pending; - hwxmits[3].sta_queue = &pxmitpriv->bk_pending; + hwxmits[0].sta_list = &pxmitpriv->vo_pending; + hwxmits[1].sta_list = &pxmitpriv->vi_pending; + hwxmits[2].sta_list = &pxmitpriv->be_pending; + hwxmits[3].sta_list = &pxmitpriv->bk_pending; return 0; } -void rtw_free_hwxmits(struct adapter *padapter) -{ - struct hw_xmit *hwxmits; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - - hwxmits = pxmitpriv->hwxmits; - kfree(hwxmits); -} - -void rtw_init_hwxmits(struct hw_xmit *phwxmit, int entry) -{ - int i; - - for (i = 0; i < entry; i++, phwxmit++) - phwxmit->accnt = 0; -} - static int rtw_br_client_tx(struct adapter *padapter, struct sk_buff **pskb) { struct sk_buff *skb = *pskb; @@ -1743,15 +1603,6 @@ u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe) return addr; } -static void do_queue_select(struct adapter *padapter, struct pkt_attrib *pattrib) -{ - u8 qsel; - - qsel = pattrib->priority; - - pattrib->qsel = qsel; -} - /* * The main transmit(tx) entry * @@ -1765,18 +1616,14 @@ s32 rtw_xmit(struct adapter *padapter, struct sk_buff **ppkt) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct xmit_frame *pxmitframe = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - void *br_port = NULL; s32 res; pxmitframe = rtw_alloc_xmitframe(pxmitpriv); if (!pxmitframe) return -1; - rcu_read_lock(); - br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); - rcu_read_unlock(); - - if (br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE)) { + if (rcu_access_pointer(padapter->pnetdev->rx_handler_data) && + check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE)) { res = rtw_br_client_tx(padapter, ppkt); if (res == -1) { rtw_free_xmitframe(pxmitpriv, pxmitframe); @@ -1794,7 +1641,7 @@ s32 rtw_xmit(struct adapter *padapter, struct sk_buff **ppkt) rtw_led_control(padapter, LED_CTL_TX); - do_queue_select(padapter, &pxmitframe->attrib); + pxmitframe->attrib.qsel = pxmitframe->attrib.priority; spin_lock_bh(&pxmitpriv->lock); if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe)) { @@ -1911,16 +1758,15 @@ int xmitframe_enqueue_for_sleeping_sta(struct adapter *padapter, struct xmit_fra return ret; } -static void dequeue_xmitframes_to_sleeping_queue(struct adapter *padapter, struct sta_info *psta, struct __queue *pframequeue) +static void dequeue_xmitframes_to_sleeping_queue(struct adapter *padapter, struct sta_info *psta, struct list_head *phead) { - struct list_head *plist, *phead; + struct list_head *plist; u8 ac_index; struct tx_servq *ptxservq; struct pkt_attrib *pattrib; struct xmit_frame *pxmitframe; struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; - phead = get_list_head(pframequeue); plist = phead->next; while (phead != plist) { diff --git a/drivers/staging/r8188eu/hal/rtl8188e_cmd.c b/drivers/staging/r8188eu/hal/rtl8188e_cmd.c index 8310d7f53982..788904d4655c 100644 --- a/drivers/staging/r8188eu/hal/rtl8188e_cmd.c +++ b/drivers/staging/r8188eu/hal/rtl8188e_cmd.c @@ -193,9 +193,9 @@ void rtl8188e_set_FwPwrMode_cmd(struct adapter *adapt, u8 Mode) } -void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt) +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, u16 mstatus_rpt) { - u16 mst_rpt = le16_to_cpu(mstatus_rpt); + __le16 mst_rpt = cpu_to_le16(mstatus_rpt); FillH2CCmd_88E(adapt, H2C_COM_MEDIA_STATUS_RPT, sizeof(mst_rpt), (u8 *)&mst_rpt); } diff --git a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c index b7f3c7a670fb..f4edf4a8f5c2 100644 --- a/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c +++ b/drivers/staging/r8188eu/hal/rtl8188e_phycfg.c @@ -315,21 +315,20 @@ rtl8188e_PHY_SetRFReg( * 08/12/2008 MHC Create Version 0. * *---------------------------------------------------------------------------*/ -s32 PHY_MACConfig8188E(struct adapter *Adapter) +int PHY_MACConfig8188E(struct adapter *Adapter) { struct hal_data_8188e *pHalData = &Adapter->haldata; - int rtStatus = _SUCCESS; + int err; /* */ /* Config MAC */ /* */ - if (ODM_ReadAndConfig_MAC_REG_8188E(&pHalData->odmpriv)) - rtStatus = _FAIL; + err = ODM_ReadAndConfig_MAC_REG_8188E(&pHalData->odmpriv); /* 2010.07.13 AMPDU aggregation number B */ rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); - return rtStatus; + return err; } /** @@ -450,13 +449,15 @@ static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter) { struct eeprom_priv *pEEPROM = &Adapter->eeprompriv; struct hal_data_8188e *pHalData = &Adapter->haldata; + int err; /* */ /* 1. Read PHY_REG.TXT BB INIT!! */ /* We will separate as 88C / 92C according to chip version */ /* */ - if (ODM_ReadAndConfig_PHY_REG_1T_8188E(&pHalData->odmpriv)) - return _FAIL; + err = ODM_ReadAndConfig_PHY_REG_1T_8188E(&pHalData->odmpriv); + if (err) + return err; /* 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ if (!pEEPROM->bautoload_fail_flag) { @@ -465,10 +466,11 @@ static int phy_BB8188E_Config_ParaFile(struct adapter *Adapter) } /* 3. BB AGC table Initialization */ - if (ODM_ReadAndConfig_AGC_TAB_1T_8188E(&pHalData->odmpriv)) - return _FAIL; + err = ODM_ReadAndConfig_AGC_TAB_1T_8188E(&pHalData->odmpriv); + if (err) + return err; - return _SUCCESS; + return 0; } int @@ -476,18 +478,17 @@ PHY_BBConfig8188E( struct adapter *Adapter ) { - int rtStatus = _SUCCESS; struct hal_data_8188e *pHalData = &Adapter->haldata; u16 RegVal; u8 CrystalCap; - int res; + int err; phy_InitBBRFRegisterDefinition(Adapter); /* Enable BB and RF */ - res = rtw_read16(Adapter, REG_SYS_FUNC_EN, &RegVal); - if (res) - return _FAIL; + err = rtw_read16(Adapter, REG_SYS_FUNC_EN, &RegVal); + if (err) + return err; rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT(13) | BIT(0) | BIT(1))); @@ -498,13 +499,13 @@ PHY_BBConfig8188E( rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); /* Config BB and AGC */ - rtStatus = phy_BB8188E_Config_ParaFile(Adapter); + err = phy_BB8188E_Config_ParaFile(Adapter); /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ CrystalCap = pHalData->CrystalCap & 0x3F; rtl8188e_PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6))); - return rtStatus; + return err; } static void getTxPowerIndex88E(struct adapter *Adapter, u8 channel, u8 *cckPowerLevel, diff --git a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c index e5ec6e563fbd..1988fb6e780a 100644 --- a/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c +++ b/drivers/staging/r8188eu/hal/rtl8188e_rf6052.c @@ -371,7 +371,7 @@ int phy_RF6052_Config_ParaFile(struct adapter *Adapter) struct bb_reg_def *pPhyReg; struct hal_data_8188e *pHalData = &Adapter->haldata; u32 u4RegValue = 0; - int rtStatus = _SUCCESS; + int err; /* Initialize RF */ @@ -396,11 +396,10 @@ int phy_RF6052_Config_ParaFile(struct adapter *Adapter) udelay(1);/* PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ - if (ODM_ReadAndConfig_RadioA_1T_8188E(&pHalData->odmpriv)) - rtStatus = _FAIL; + err = ODM_ReadAndConfig_RadioA_1T_8188E(&pHalData->odmpriv); /*----Restore RFENV control type----*/; rtl8188e_PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); - return rtStatus; + return err; } diff --git a/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c b/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c index 6d1f56d1f9d7..3ffab4953a5c 100644 --- a/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c +++ b/drivers/staging/r8188eu/hal/rtl8188eu_xmit.c @@ -9,16 +9,6 @@ #include "../include/usb_ops.h" #include "../include/rtl8188e_hal.h" -s32 rtl8188eu_init_xmit_priv(struct adapter *adapt) -{ - struct xmit_priv *pxmitpriv = &adapt->xmitpriv; - - tasklet_init(&pxmitpriv->xmit_tasklet, - rtl8188eu_xmit_tasklet, - (unsigned long)adapt); - return _SUCCESS; -} - static void rtl8188eu_cal_txdesc_chksum(struct tx_desc *ptxdesc) { u16 *usptr = (u16 *)ptxdesc; @@ -147,7 +137,7 @@ static void fill_txdesc_phy(struct pkt_attrib *pattrib, __le32 *pdw) } } -static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt) +static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz) { uint qsel; u8 data_rate, pwr_status, offset; @@ -329,7 +319,7 @@ static s32 rtw_dump_xframe(struct adapter *adapt, struct xmit_frame *pxmitframe) sz = pattrib->last_txcmdsz; } - pull = update_txdesc(pxmitframe, mem_addr, sz, false); + pull = update_txdesc(pxmitframe, mem_addr, sz); if (pull) { mem_addr += PACKET_OFFSET_SZ; /* pull txdesc head */ @@ -375,11 +365,13 @@ static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) return len; } -bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +bool rtl8188eu_xmitframe_complete(struct adapter *adapt) { + struct xmit_priv *pxmitpriv = &adapt->xmitpriv; struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapt); struct xmit_frame *pxmitframe = NULL; struct xmit_frame *pfirstframe = NULL; + struct xmit_buf *pxmitbuf; /* aggregate variable */ struct hw_xmit *phwxmit; @@ -403,17 +395,11 @@ bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmit else bulksize = USB_FULL_SPEED_BULK_SIZE; - /* check xmitbuffer is ok */ - if (!pxmitbuf) { - pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); - if (!pxmitbuf) - return false; - } + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (!pxmitbuf) + return false; - /* 3 1. pick up first frame */ - rtw_free_xmitframe(pxmitpriv, pxmitframe); - - pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); + pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits); if (!pxmitframe) { /* no more xmit frame, release xmit buffer */ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); @@ -475,7 +461,7 @@ bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmit } spin_lock_bh(&pxmitpriv->lock); - xmitframe_phead = get_list_head(&ptxservq->sta_pending); + xmitframe_phead = &ptxservq->sta_pending; xmitframe_plist = xmitframe_phead->next; while (xmitframe_phead != xmitframe_plist) { @@ -503,7 +489,7 @@ bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmit rtw_xmit_complete(adapt, pxmitframe); /* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */ - update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz, true); + update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz); /* don't need xmitframe any more */ rtw_free_xmitframe(pxmitpriv, pxmitframe); @@ -526,7 +512,7 @@ bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmit } } /* end while (aggregate same priority and same DA(AP or STA) frames) */ - if (list_empty(&ptxservq->sta_pending.queue)) + if (list_empty(&ptxservq->sta_pending)) list_del_init(&ptxservq->tx_pending); spin_unlock_bh(&pxmitpriv->lock); @@ -543,7 +529,7 @@ bool rtl8188eu_xmitframe_complete(struct adapter *adapt, struct xmit_priv *pxmit pfirstframe->pkt_offset--; } - update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz, true); + update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz); /* 3 4. write xmit buffer to USB FIFO */ ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); @@ -610,7 +596,7 @@ static s32 pre_xmitframe(struct adapter *adapt, struct xmit_frame *pxmitframe) return true; enqueue: - res = rtw_xmitframe_enqueue(adapt, pxmitframe); + res = rtw_xmit_classifier(adapt, pxmitframe); spin_unlock_bh(&pxmitpriv->lock); if (res != _SUCCESS) { diff --git a/drivers/staging/r8188eu/hal/usb_halinit.c b/drivers/staging/r8188eu/hal/usb_halinit.c index d28b4dc2a767..a1051ac1cac4 100644 --- a/drivers/staging/r8188eu/hal/usb_halinit.c +++ b/drivers/staging/r8188eu/hal/usb_halinit.c @@ -600,20 +600,17 @@ u32 rtl8188eu_hal_init(struct adapter *Adapter) Adapter->pwrctrlpriv.bFwCurrentInPSMode = false; haldata->LastHMEBoxNum = 0; - status = PHY_MACConfig8188E(Adapter); - if (status == _FAIL) - goto exit; + if (PHY_MACConfig8188E(Adapter)) + return _FAIL; /* */ /* d. Initialize BB related configurations. */ /* */ - status = PHY_BBConfig8188E(Adapter); - if (status == _FAIL) - goto exit; + if (PHY_BBConfig8188E(Adapter)) + return _FAIL; - status = phy_RF6052_Config_ParaFile(Adapter); - if (status == _FAIL) - goto exit; + if (phy_RF6052_Config_ParaFile(Adapter)) + return _FAIL; status = rtl8188e_iol_efuse_patch(Adapter); if (status == _FAIL) @@ -851,29 +848,25 @@ u32 rtl8188eu_hal_deinit(struct adapter *Adapter) return _SUCCESS; } -unsigned int rtl8188eu_inirp_init(struct adapter *Adapter) +int rtl8188eu_inirp_init(struct adapter *Adapter) { u8 i; struct recv_buf *precvbuf; - uint status; struct recv_priv *precvpriv = &Adapter->recvpriv; - - status = _SUCCESS; + int ret; /* issue Rx irp to receive data */ precvbuf = (struct recv_buf *)precvpriv->precv_buf; for (i = 0; i < NR_RECVBUFF; i++) { - if (!rtw_read_port(Adapter, (unsigned char *)precvbuf)) { - status = _FAIL; - goto exit; - } + ret = rtw_read_port(Adapter, precvbuf); + if (ret) + return ret; precvbuf++; precvpriv->free_recv_buf_queue_cnt--; } -exit: - return status; + return 0; } /* */ diff --git a/drivers/staging/r8188eu/hal/usb_ops_linux.c b/drivers/staging/r8188eu/hal/usb_ops_linux.c index 7c72f5e04d9b..9611b19ab55b 100644 --- a/drivers/staging/r8188eu/hal/usb_ops_linux.c +++ b/drivers/staging/r8188eu/hal/usb_ops_linux.c @@ -7,9 +7,12 @@ #include "../include/usb_ops.h" #include "../include/rtl8188e_hal.h" -static int usb_read(struct intf_hdl *intf, u16 value, void *data, u8 size) +#define VENDOR_CMD_MAX_DATA_LEN 254 + +#define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */ + +static int usb_read(struct adapter *adapt, u16 value, void *data, u8 size) { - struct adapter *adapt = intf->padapter; struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt); struct usb_device *udev = dvobjpriv->pusbdev; int status; @@ -50,9 +53,8 @@ static int usb_read(struct intf_hdl *intf, u16 value, void *data, u8 size) return status; } -static int usb_write(struct intf_hdl *intf, u16 value, void *data, u8 size) +static int usb_write(struct adapter *adapt, u16 value, void *data, u8 size) { - struct adapter *adapt = intf->padapter; struct dvobj_priv *dvobjpriv = adapter_to_dvobj(adapt); struct usb_device *udev = dvobjpriv->pusbdev; int status; @@ -95,22 +97,18 @@ static int usb_write(struct intf_hdl *intf, u16 value, void *data, u8 size) int __must_check rtw_read8(struct adapter *adapter, u32 addr, u8 *data) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; - return usb_read(intf, value, data, 1); + return usb_read(adapter, value, data, 1); } int __must_check rtw_read16(struct adapter *adapter, u32 addr, u16 *data) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; __le16 le_data; int res; - res = usb_read(intf, value, &le_data, 2); + res = usb_read(adapter, value, &le_data, 2); if (res) return res; @@ -121,13 +119,11 @@ int __must_check rtw_read16(struct adapter *adapter, u32 addr, u16 *data) int __must_check rtw_read32(struct adapter *adapter, u32 addr, u32 *data) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; __le32 le_data; int res; - res = usb_read(intf, value, &le_data, 4); + res = usb_read(adapter, value, &le_data, 4); if (res) return res; @@ -138,55 +134,44 @@ int __must_check rtw_read32(struct adapter *adapter, u32 addr, u32 *data) int rtw_write8(struct adapter *adapter, u32 addr, u8 val) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; int ret; - ret = usb_write(intf, value, &val, 1); + ret = usb_write(adapter, value, &val, 1); return RTW_STATUS_CODE(ret); } int rtw_write16(struct adapter *adapter, u32 addr, u16 val) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; __le16 data = cpu_to_le16(val); int ret; - ret = usb_write(intf, value, &data, 2); + ret = usb_write(adapter, value, &data, 2); return RTW_STATUS_CODE(ret); } int rtw_write32(struct adapter *adapter, u32 addr, u32 val) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; __le32 data = cpu_to_le32(val); int ret; - ret = usb_write(intf, value, &data, 4); + ret = usb_write(adapter, value, &data, 4); return RTW_STATUS_CODE(ret); } int rtw_writeN(struct adapter *adapter, u32 addr, u32 length, u8 *data) { - struct io_priv *io_priv = &adapter->iopriv; - struct intf_hdl *intf = &io_priv->intf; u16 value = addr & 0xffff; - int ret; if (length > VENDOR_CMD_MAX_DATA_LEN) - return _FAIL; + return -EINVAL; - ret = usb_write(intf, value, data, length); - - return RTW_STATUS_CODE(ret); + return usb_write(adapter, value, data, length); } static void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf) @@ -363,7 +348,7 @@ void rtl8188eu_recv_tasklet(unsigned long priv) } } -static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) +static void usb_read_port_complete(struct urb *purb) { struct recv_buf *precvbuf = (struct recv_buf *)purb->context; struct adapter *adapt = (struct adapter *)precvbuf->adapter; @@ -379,7 +364,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) if (purb->status == 0) { /* SUCCESS */ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) { precvbuf->reuse = true; - rtw_read_port(adapt, (unsigned char *)precvbuf); + rtw_read_port(adapt, precvbuf); } else { rtw_reset_continual_urb_error(adapter_to_dvobj(adapt)); @@ -391,7 +376,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) precvbuf->pskb = NULL; precvbuf->reuse = false; - rtw_read_port(adapt, (unsigned char *)precvbuf); + rtw_read_port(adapt, precvbuf); } } else { skb_put(precvbuf->pskb, purb->actual_length); @@ -411,7 +396,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) case -EPROTO: case -EOVERFLOW: precvbuf->reuse = true; - rtw_read_port(adapt, (unsigned char *)precvbuf); + rtw_read_port(adapt, precvbuf); break; case -EINPROGRESS: break; @@ -421,10 +406,9 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) } } -u32 rtw_read_port(struct adapter *adapter, u8 *rmem) +int rtw_read_port(struct adapter *adapter, struct recv_buf *precvbuf) { struct urb *purb = NULL; - struct recv_buf *precvbuf = (struct recv_buf *)rmem; struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); struct recv_priv *precvpriv = &adapter->recvpriv; struct usb_device *pusbd = pdvobj->pusbdev; @@ -432,13 +416,12 @@ u32 rtw_read_port(struct adapter *adapter, u8 *rmem) unsigned int pipe; size_t tmpaddr = 0; size_t alignment = 0; - u32 ret = _SUCCESS; if (adapter->bDriverStopped || adapter->bSurpriseRemoved) - return _FAIL; + return -EPERM; if (!precvbuf) - return _FAIL; + return -ENOMEM; if (!precvbuf->reuse || !precvbuf->pskb) { precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue); @@ -450,7 +433,7 @@ u32 rtw_read_port(struct adapter *adapter, u8 *rmem) if (!precvbuf->reuse || !precvbuf->pskb) { precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); if (!precvbuf->pskb) - return _FAIL; + return -ENOMEM; tmpaddr = (size_t)precvbuf->pskb->data; alignment = tmpaddr & (RECVBUFF_ALIGN_SZ - 1); @@ -474,29 +457,20 @@ u32 rtw_read_port(struct adapter *adapter, u8 *rmem) err = usb_submit_urb(purb, GFP_ATOMIC); if ((err) && (err != (-EPERM))) - ret = _FAIL; + return err; - return ret; + return 0; } void rtl8188eu_xmit_tasklet(unsigned long priv) { - int ret = false; struct adapter *adapt = (struct adapter *)priv; - struct xmit_priv *pxmitpriv = &adapt->xmitpriv; if (check_fwstate(&adapt->mlmepriv, _FW_UNDER_SURVEY)) return; - while (1) { - if ((adapt->bDriverStopped) || - (adapt->bSurpriseRemoved) || - (adapt->bWritePortCancel)) + do { + if (adapt->bDriverStopped || adapt->bSurpriseRemoved || adapt->bWritePortCancel) break; - - ret = rtl8188eu_xmitframe_complete(adapt, pxmitpriv, NULL); - - if (!ret) - break; - } + } while (rtl8188eu_xmitframe_complete(adapt)); } diff --git a/drivers/staging/r8188eu/include/drv_types.h b/drivers/staging/r8188eu/include/drv_types.h index 8fef5759c36a..159990facb8a 100644 --- a/drivers/staging/r8188eu/include/drv_types.h +++ b/drivers/staging/r8188eu/include/drv_types.h @@ -152,7 +152,6 @@ struct adapter { struct mlme_ext_priv mlmeextpriv; struct cmd_priv cmdpriv; struct evt_priv evtpriv; - struct io_priv iopriv; struct xmit_priv xmitpriv; struct recv_priv recvpriv; struct sta_priv stapriv; @@ -172,8 +171,6 @@ struct adapter { s8 signal_strength; void *cmdThread; - void (*intf_start)(struct adapter *adapter); - void (*intf_stop)(struct adapter *adapter); struct net_device *pnetdev; /* used by rtw_rereg_nd_name related function */ @@ -187,7 +184,6 @@ struct adapter { int bup; struct net_device_stats stats; struct iw_statistics iwstats; - struct proc_dir_entry *dir_dev;/* for proc directory */ int net_closed; u8 bFWReady; diff --git a/drivers/staging/r8188eu/include/hal_intf.h b/drivers/staging/r8188eu/include/hal_intf.h index ac6e3f95c5b7..296aa5b8268d 100644 --- a/drivers/staging/r8188eu/include/hal_intf.h +++ b/drivers/staging/r8188eu/include/hal_intf.h @@ -26,7 +26,7 @@ void UpdateHalRAMask8188EUsb(struct adapter *adapt, u32 mac_id, u8 rssi_level); int rtl8188e_IOL_exec_cmds_sync(struct adapter *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); -unsigned int rtl8188eu_inirp_init(struct adapter *Adapter); +int rtl8188eu_inirp_init(struct adapter *Adapter); uint rtw_hal_init(struct adapter *padapter); uint rtw_hal_deinit(struct adapter *padapter); diff --git a/drivers/staging/r8188eu/include/osdep_intf.h b/drivers/staging/r8188eu/include/osdep_intf.h index 6d66cb57225e..457fb3852a19 100644 --- a/drivers/staging/r8188eu/include/osdep_intf.h +++ b/drivers/staging/r8188eu/include/osdep_intf.h @@ -7,38 +7,6 @@ #include "osdep_service.h" #include "drv_types.h" -struct intf_priv { - u8 *intf_dev; - u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */ - u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */ - u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */ - - u8 *io_rwmem; - u8 *allocated_io_rwmem; - u32 io_wsz; /* unit: 4bytes */ - u32 io_rsz;/* unit: 4bytes */ - u8 intf_status; - - void (*_bus_io)(u8 *priv); - -/* -Under Sync. IRP (SDIO/USB) -A protection mechanism is necessary for the io_rwmem(read/write protocol) - -Under Async. IRP (SDIO/USB) -The protection mechanism is through the pending queue. -*/ - struct mutex ioctl_mutex; - /* when in USB, IO is through interrupt in/out endpoints */ - struct usb_device *udev; - struct urb *piorw_urb; - u8 io_irp_cnt; - u8 bio_irp_pending; - struct timer_list io_timer; - u8 bio_irp_timeout; - u8 bio_timer_cancel; -}; - int netdev_open(struct net_device *pnetdev); int netdev_close(struct net_device *pnetdev); diff --git a/drivers/staging/r8188eu/include/rtl8188e_cmd.h b/drivers/staging/r8188eu/include/rtl8188e_cmd.h index 1e01c1662f9a..c785cf8ed683 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_cmd.h +++ b/drivers/staging/r8188eu/include/rtl8188e_cmd.h @@ -85,6 +85,6 @@ void rtl8188e_Add_RateATid(struct adapter *padapter, u32 bitmap, u8 arg, void rtl8188e_set_p2p_ps_offload_cmd(struct adapter *adapt, u8 p2p_ps_state); void CheckFwRsvdPageContent(struct adapter *adapt); -void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt); +void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, u16 mstatus_rpt); #endif/* __RTL8188E_CMD_H__ */ diff --git a/drivers/staging/r8188eu/include/rtl8188e_spec.h b/drivers/staging/r8188eu/include/rtl8188e_spec.h index 3fa3b3e5dd64..25b31417cd58 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_spec.h +++ b/drivers/staging/r8188eu/include/rtl8188e_spec.h @@ -510,28 +510,7 @@ Default: 00b. /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ #define BW_OPMODE_20MHZ BIT(2) -/* 8192C CAM Config Setting (offset 0x250, 1 byte) */ -#define CAM_VALID BIT(15) -#define CAM_NOTVALID 0x0000 -#define CAM_USEDK BIT(5) - -#define CAM_CONTENT_COUNT 8 - -#define CAM_NONE 0x0 -#define CAM_WEP40 0x01 -#define CAM_TKIP 0x02 -#define CAM_AES 0x04 -#define CAM_WEP104 0x05 -#define CAM_SMS4 0x6 - -#define TOTAL_CAM_ENTRY 32 -#define HALF_CAM_ENTRY 16 - -#define CAM_CONFIG_USEDK true -#define CAM_CONFIG_NO_USEDK false - #define CAM_WRITE BIT(16) -#define CAM_READ 0x00000000 #define CAM_POLLINIG BIT(31) #define SCR_UseDK 0x01 diff --git a/drivers/staging/r8188eu/include/rtl8188e_xmit.h b/drivers/staging/r8188eu/include/rtl8188e_xmit.h index 6db7fabebea9..a023dd792da7 100644 --- a/drivers/staging/r8188eu/include/rtl8188e_xmit.h +++ b/drivers/staging/r8188eu/include/rtl8188e_xmit.h @@ -5,17 +5,7 @@ #define __RTL8188E_XMIT_H__ #define MAX_TX_AGG_PACKET_NUMBER 0xFF -/* */ -/* Queue Select Value in TxDesc */ -/* */ -#define QSLT_BK 0x2/* 0x01 */ -#define QSLT_BE 0x0 -#define QSLT_VI 0x5/* 0x4 */ -#define QSLT_VO 0x7/* 0x6 */ -#define QSLT_BEACON 0x10 -#define QSLT_HIGH 0x11 #define QSLT_MGNT 0x12 -#define QSLT_CMD 0x13 /* For 88e early mode */ #define SET_EARLYMODE_PKTNUM(__paddr, __value) \ @@ -131,14 +121,10 @@ struct txrpt_ccx_88e { void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull); -s32 rtl8188eu_init_xmit_priv(struct adapter *padapter); s32 rtl8188eu_hal_xmit(struct adapter *padapter, struct xmit_frame *frame); s32 rtl8188eu_mgnt_xmit(struct adapter *padapter, struct xmit_frame *frame); s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter); -#define hal_xmit_handler rtl8188eu_xmit_buf_handler void rtl8188eu_xmit_tasklet(unsigned long priv); -bool rtl8188eu_xmitframe_complete(struct adapter *padapter, - struct xmit_priv *pxmitpriv, - struct xmit_buf *pxmitbuf); +bool rtl8188eu_xmitframe_complete(struct adapter *padapter); #endif /* __RTL8188E_XMIT_H__ */ diff --git a/drivers/staging/r8188eu/include/rtw_cmd.h b/drivers/staging/r8188eu/include/rtw_cmd.h index c330a4435b31..e8eecd52d1d8 100644 --- a/drivers/staging/r8188eu/include/rtw_cmd.h +++ b/drivers/staging/r8188eu/include/rtw_cmd.h @@ -32,7 +32,6 @@ struct cmd_priv { struct completion start_cmd_thread; struct completion stop_cmd_thread; struct __queue cmd_queue; - u8 cmd_seq; u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */ u8 *cmd_allocated_buf; u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */ @@ -744,7 +743,7 @@ u8 rtw_rpt_timer_cfg_cmd(struct adapter *padapter, u16 minRptTime); u8 rtw_antenna_select_cmd(struct adapter *padapter, u8 antenna, u8 enqueue); u8 rtw_ps_cmd(struct adapter *padapter); -u8 rtw_chk_hi_queue_cmd(struct adapter *padapter); +void rtw_chk_hi_queue_cmd(struct adapter *padapter); u8 rtw_set_chplan_cmd(struct adapter *padapter, u8 chplan); diff --git a/drivers/staging/r8188eu/include/rtw_io.h b/drivers/staging/r8188eu/include/rtw_io.h index e9744694204b..e1718f739cc9 100644 --- a/drivers/staging/r8188eu/include/rtw_io.h +++ b/drivers/staging/r8188eu/include/rtw_io.h @@ -16,215 +16,10 @@ #include #include -#define rtw_usb_buffer_alloc(dev, size, dma) \ - usb_alloc_coherent((dev), (size), (in_interrupt() ? \ - GFP_ATOMIC : GFP_KERNEL), (dma)) -#define rtw_usb_buffer_free(dev, size, addr, dma) \ - usb_free_coherent((dev), (size), (addr), (dma)) - -#define NUM_IOREQ 8 - -#define MAX_PROT_SZ (64-16) - -#define _IOREADY 0 -#define _IO_WAIT_COMPLETE 1 -#define _IO_WAIT_RSP 2 - -/* IO COMMAND TYPE */ -#define _IOSZ_MASK_ (0x7F) -#define _IO_WRITE_ BIT(7) -#define _IO_FIXED_ BIT(8) -#define _IO_BURST_ BIT(9) -#define _IO_BYTE_ BIT(10) -#define _IO_HW_ BIT(11) -#define _IO_WORD_ BIT(12) -#define _IO_SYNC_ BIT(13) -#define _IO_CMDMASK_ (0x1F80) - -/* - For prompt mode accessing, caller shall free io_req - Otherwise, io_handler will free io_req -*/ - -/* IO STATUS TYPE */ -#define _IO_ERR_ BIT(2) -#define _IO_SUCCESS_ BIT(1) -#define _IO_DONE_ BIT(0) - -#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) -#define IO_RD16 (_IO_SYNC_ | _IO_HW_) -#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) - -#define IO_RD32_ASYNC (_IO_WORD_) -#define IO_RD16_ASYNC (_IO_HW_) -#define IO_RD8_ASYNC (_IO_BYTE_) - -#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) -#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) -#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) - -#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) -#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) -#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) - -/* - Only Sync. burst accessing is provided. -*/ - -#define IO_WR_BURST(x) \ - (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) -#define IO_RD_BURST(x) \ - (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) - -/* below is for the intf_option bit defition... */ - -#define _INTF_ASYNC_ BIT(0) /* support async io */ - -struct intf_priv; -struct intf_hdl; -struct io_queue; - -struct io_req { - struct list_head list; - u32 addr; - u32 val; - u32 command; - u32 status; - u8 *pbuf; - struct semaphore sema; - - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, u8 *cnxt); - u8 *cnxt; -}; - -struct intf_hdl { - struct adapter *padapter; - struct dvobj_priv *pintf_dev; -}; - -struct reg_protocol_rd { -#ifdef __LITTLE_ENDIAN - /* DW1 */ - u32 NumOfTrans:4; - u32 Reserved1:4; - u32 Reserved2:24; - /* DW2 */ - u32 ByteCount:7; - u32 WriteEnable:1; /* 0:read, 1:write */ - u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ - u32 BurstMode:1; - u32 Byte1Access:1; - u32 Byte2Access:1; - u32 Byte4Access:1; - u32 Reserved3:3; - u32 Reserved4:16; - /* DW3 */ - u32 BusAddress; - /* DW4 */ - /* u32 Value; */ -#else -/* DW1 */ - u32 Reserved1:4; - u32 NumOfTrans:4; - u32 Reserved2:24; - /* DW2 */ - u32 WriteEnable:1; - u32 ByteCount:7; - u32 Reserved3:3; - u32 Byte4Access:1; - - u32 Byte2Access:1; - u32 Byte1Access:1; - u32 BurstMode:1; - u32 FixOrContinuous:1; - u32 Reserved4:16; - /* DW3 */ - u32 BusAddress; - - /* DW4 */ -#endif -}; - -struct reg_protocol_wt { -#ifdef __LITTLE_ENDIAN - /* DW1 */ - u32 NumOfTrans:4; - u32 Reserved1:4; - u32 Reserved2:24; - /* DW2 */ - u32 ByteCount:7; - u32 WriteEnable:1; /* 0:read, 1:write */ - u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ - u32 BurstMode:1; - u32 Byte1Access:1; - u32 Byte2Access:1; - u32 Byte4Access:1; - u32 Reserved3:3; - u32 Reserved4:16; - /* DW3 */ - u32 BusAddress; - /* DW4 */ - u32 Value; -#else - /* DW1 */ - u32 Reserved1 :4; - u32 NumOfTrans:4; - u32 Reserved2:24; - /* DW2 */ - u32 WriteEnable:1; - u32 ByteCount:7; - u32 Reserved3:3; - u32 Byte4Access:1; - u32 Byte2Access:1; - u32 Byte1Access:1; - u32 BurstMode:1; - u32 FixOrContinuous:1; - u32 Reserved4:16; - /* DW3 */ - u32 BusAddress; - /* DW4 */ - u32 Value; -#endif -}; - -/* -Below is the data structure used by _io_handler -*/ - -struct io_queue { - spinlock_t lock; - struct list_head free_ioreqs; - struct list_head pending; /* The io_req list that will be served - * in the single protocol read/write.*/ - struct list_head processing; - u8 *free_ioreqs_buf; /* 4-byte aligned */ - u8 *pallocated_free_ioreqs_buf; - struct intf_hdl intf; -}; - -struct io_priv { - struct adapter *padapter; - struct intf_hdl intf; -}; - -uint ioreq_flush(struct adapter *adapter, struct io_queue *ioqueue); -void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue); -uint sync_ioreq_flush(struct adapter *adapter, struct io_queue *ioqueue); -uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); -struct io_req *alloc_ioreq(struct io_queue *pio_q); - -uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); -void unregister_intf_hdl(struct intf_hdl *pintfhdl); - -void _rtw_attrib_read(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -void _rtw_attrib_write(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); - int __must_check rtw_read8(struct adapter *adapter, u32 addr, u8 *data); int __must_check rtw_read16(struct adapter *adapter, u32 addr, u16 *data); int __must_check rtw_read32(struct adapter *adapter, u32 addr, u32 *data); -void _rtw_read_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -u32 rtw_read_port(struct adapter *adapter, u8 *pmem); +int rtw_read_port(struct adapter *adapter, struct recv_buf *precvbuf); void rtw_read_port_cancel(struct adapter *adapter); int rtw_write8(struct adapter *adapter, u32 addr, u8 val); @@ -232,57 +27,7 @@ int rtw_write16(struct adapter *adapter, u32 addr, u16 val); int rtw_write32(struct adapter *adapter, u32 addr, u32 val); int rtw_writeN(struct adapter *adapter, u32 addr, u32 length, u8 *pdata); -void _rtw_write_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); u32 rtw_write_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); void rtw_write_port_cancel(struct adapter *adapter); -void rtw_write_scsi(struct adapter *adapter, u32 cnt, u8 *pmem); - -/* ioreq */ -void ioreq_read8(struct adapter *adapter, u32 addr, u8 *pval); -void ioreq_read16(struct adapter *adapter, u32 addr, u16 *pval); -void ioreq_read32(struct adapter *adapter, u32 addr, u32 *pval); -void ioreq_write8(struct adapter *adapter, u32 addr, u8 val); -void ioreq_write16(struct adapter *adapter, u32 addr, u16 val); -void ioreq_write32(struct adapter *adapter, u32 addr, u32 val); - -uint async_read8(struct adapter *adapter, u32 addr, u8 *pbuff, - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, - u8 *cnxt), u8 *cnxt); -uint async_read16(struct adapter *adapter, u32 addr, u8 *pbuff, - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, - u8 *cnxt), u8 *cnxt); -uint async_read32(struct adapter *adapter, u32 addr, u8 *pbuff, - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, - u8 *cnxt), u8 *cnxt); - -void async_read_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -void async_read_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); - -void async_write8(struct adapter *adapter, u32 addr, u8 val, - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, - u8 *cnxt), u8 *cnxt); -void async_write16(struct adapter *adapter, u32 addr, u16 val, - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, - u8 *cnxt), u8 *cnxt); -void async_write32(struct adapter *adapter, u32 addr, u32 val, - void (*_async_io_callback)(struct adapter *padater, - struct io_req *pio_req, - u8 *cnxt), u8 *cnxt); - -void async_write_mem(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); -void async_write_port(struct adapter *adapter, u32 addr, u32 cnt, u8 *pmem); - -uint alloc_io_queue(struct adapter *adapter); -void free_io_queue(struct adapter *adapter); -void async_bus_io(struct io_queue *pio_q); -void bus_sync_io(struct io_queue *pio_q); -u32 _ioreq2rwmem(struct io_queue *pio_q); -void dev_power_down(struct adapter *Adapter, u8 bpwrup); - #endif /* _RTL8711_IO_H_ */ diff --git a/drivers/staging/r8188eu/include/rtw_pwrctrl.h b/drivers/staging/r8188eu/include/rtw_pwrctrl.h index 6e9fdd66fad1..9f5cffd8bfb1 100644 --- a/drivers/staging/r8188eu/include/rtw_pwrctrl.h +++ b/drivers/staging/r8188eu/include/rtw_pwrctrl.h @@ -71,7 +71,6 @@ struct pwrctrl_priv { int pwr_state_check_interval; enum rt_rf_power_state rf_pwrstate;/* cur power state */ - enum rt_rf_power_state change_rfpwrstate; u8 bkeepfwalive; }; @@ -99,8 +98,6 @@ void rtw_set_firmware_ps_mode(struct adapter *adapter, u8 mode); void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode); void LeaveAllPowerSaveMode(struct adapter *adapter); -void ips_enter(struct adapter *padapter); -int ips_leave(struct adapter *padapter); void rtw_ps_processor(struct adapter *padapter); diff --git a/drivers/staging/r8188eu/include/rtw_xmit.h b/drivers/staging/r8188eu/include/rtw_xmit.h index 6e7ebea5362d..feeac85aedb0 100644 --- a/drivers/staging/r8188eu/include/rtw_xmit.h +++ b/drivers/staging/r8188eu/include/rtw_xmit.h @@ -97,7 +97,7 @@ union txdesc { }; struct hw_xmit { - struct __queue *sta_queue; + struct list_head *sta_list; int accnt; }; @@ -152,14 +152,7 @@ struct pkt_attrib { #define NULL_FRAMETAG (0x0) #define DATA_FRAMETAG 0x01 -#define L2_FRAMETAG 0x02 #define MGNT_FRAMETAG 0x03 -#define AMSDU_FRAMETAG 0x04 - -#define EII_FRAMETAG 0x05 -#define IEEE8023_FRAMETAG 0x06 - -#define MP_FRAMETAG 0x07 #define TXAGG_FRAMETAG 0x08 @@ -196,14 +189,11 @@ struct xmit_buf { u8 *pbuf; void *priv_data; u16 ext_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf. */ - u16 flags; + bool high_queue; u32 alloc_sz; u32 len; struct submit_ctx *sctx; - u32 ff_hwaddr; struct urb *pxmit_urb; - dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ - u8 bpending[8]; int last[8]; }; @@ -223,21 +213,16 @@ struct xmit_frame { struct tx_servq { struct list_head tx_pending; - struct __queue sta_pending; + struct list_head sta_pending; int qcnt; }; struct sta_xmit_priv { spinlock_t lock; - int option; - int apsd_setting; /* When bit mask is on, the associated edca - * queue supports APSD. */ struct tx_servq be_q; /* priority == 0,3 */ struct tx_servq bk_q; /* priority == 1,2 */ struct tx_servq vi_q; /* priority == 4,5 */ struct tx_servq vo_q; /* priority == 6,7 */ - struct list_head legacy_dz; - struct list_head apsd; u16 txseq_tid[16]; }; @@ -252,46 +237,28 @@ struct hw_txqueue { int ac_tag; }; -struct agg_pkt_info { - u16 offset; - u16 pkt_len; -}; - struct xmit_priv { spinlock_t lock; - struct semaphore terminate_xmitthread_sema; - struct __queue be_pending; - struct __queue bk_pending; - struct __queue vi_pending; - struct __queue vo_pending; - struct __queue bm_pending; + struct list_head be_pending; + struct list_head bk_pending; + struct list_head vi_pending; + struct list_head vo_pending; u8 *pallocated_frame_buf; u8 *pxmit_frame_buf; uint free_xmitframe_cnt; struct __queue free_xmit_queue; uint frag_len; struct adapter *adapter; - u8 vcs_setting; - u8 vcs; - u8 vcs_type; u64 tx_bytes; u64 tx_pkts; u64 tx_drop; u64 last_tx_bytes; u64 last_tx_pkts; struct hw_xmit *hwxmits; - u8 hwxmit_entry; u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength * from large to small. it's value is 0->vo, * 1->vi, 2->be, 3->bk. */ - struct semaphore tx_retevt;/* all tx return event; */ - u8 txirp_cnt;/* */ struct tasklet_struct xmit_tasklet; - /* per AC pending irp */ - int beq_cnt; - int bkq_cnt; - int viq_cnt; - int voq_cnt; struct __queue free_xmitbuf_queue; struct __queue pending_xmitbuf_queue; u8 *pallocated_xmitbuf; @@ -324,7 +291,6 @@ s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); void rtw_count_tx_stats(struct adapter *padapter, struct xmit_frame *pxmitframe, int sz); -void rtw_update_protection(struct adapter *padapter, u8 *ie, uint ie_len); s32 rtw_make_wlanhdr(struct adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); s32 rtw_put_snap(u8 *data, u16 h_proto); @@ -332,14 +298,11 @@ s32 rtw_put_snap(u8 *data, u16 h_proto); struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); -void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, - struct __queue *pframequeue); +void rtw_free_xmitframe_list(struct xmit_priv *pxmitpriv, struct list_head *xframe_list); struct tx_servq *rtw_get_sta_pending(struct adapter *padapter, struct sta_info *psta, int up, u8 *ac); -s32 rtw_xmitframe_enqueue(struct adapter *padapter, - struct xmit_frame *pxmitframe); struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, - struct hw_xmit *phwxmit_i, int entry); + struct hw_xmit *phwxmit_i); s32 rtw_xmit_classifier(struct adapter *padapter, struct xmit_frame *pxmitframe); @@ -350,11 +313,9 @@ void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); s32 rtw_txframes_pending(struct adapter *padapter); s32 rtw_txframes_sta_ac_pending(struct adapter *padapter, struct pkt_attrib *pattrib); -void rtw_init_hwxmits(struct hw_xmit *phwxmit, int entry); int _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, struct adapter *padapter); void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); int rtw_alloc_hwxmits(struct adapter *padapter); -void rtw_free_hwxmits(struct adapter *padapter); s32 rtw_xmit(struct adapter *padapter, struct sk_buff **pkt); int xmitframe_enqueue_for_sleeping_sta(struct adapter *padapter, struct xmit_frame *pxmitframe); diff --git a/drivers/staging/r8188eu/include/usb_ops.h b/drivers/staging/r8188eu/include/usb_ops.h index ddc46cb44358..5bd8ce37aebf 100644 --- a/drivers/staging/r8188eu/include/usb_ops.h +++ b/drivers/staging/r8188eu/include/usb_ops.h @@ -17,8 +17,6 @@ #define MAX_VENDOR_REQ_CMD_SIZE 254 /* 8188cu SIE Support */ #define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE + ALIGNMENT_UNIT) -#include "usb_ops_linux.h" - /* * Increase and check if the continual_urb_error of this @param dvobjprivei * is larger than MAX_CONTINUAL_URB_ERR diff --git a/drivers/staging/r8188eu/include/usb_ops_linux.h b/drivers/staging/r8188eu/include/usb_ops_linux.h deleted file mode 100644 index 966688eedf66..000000000000 --- a/drivers/staging/r8188eu/include/usb_ops_linux.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* Copyright(c) 2007 - 2011 Realtek Corporation. */ - -#ifndef __USB_OPS_LINUX_H__ -#define __USB_OPS_LINUX_H__ - -#define VENDOR_CMD_MAX_DATA_LEN 254 - -#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10/* ms */ -#define RTW_USB_CONTROL_MSG_TIMEOUT 500/* ms */ - -#define MAX_USBCTRL_VENDORREQ_TIMES 10 - -#define RTW_USB_BULKOUT_TIME 5000/* ms */ - -#define _usbctrl_vendorreq_async_callback(urb, regs) \ - _usbctrl_vendorreq_async_callback(urb) -#define usb_bulkout_zero_complete(purb, regs) \ - usb_bulkout_zero_complete(purb) -#define usb_write_mem_complete(purb, regs) \ - usb_write_mem_complete(purb) -#define usb_write_port_complete(purb, regs) \ - usb_write_port_complete(purb) -#define usb_read_port_complete(purb, regs) \ - usb_read_port_complete(purb) -#define usb_read_interrupt_complete(purb, regs) \ - usb_read_interrupt_complete(purb) - -#endif diff --git a/drivers/staging/r8188eu/os_dep/ioctl_linux.c b/drivers/staging/r8188eu/os_dep/ioctl_linux.c index 8e9b7b0664bc..e0a819970546 100644 --- a/drivers/staging/r8188eu/os_dep/ioctl_linux.c +++ b/drivers/staging/r8188eu/os_dep/ioctl_linux.c @@ -3061,8 +3061,7 @@ static int rtw_rereg_nd_name(struct net_device *dev, char *reg_ifname; reg_ifname = padapter->registrypriv.if2name; - strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ); - rereg_priv->old_ifname[IFNAMSIZ - 1] = 0; + strscpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ); } if (wrqu->data.length > IFNAMSIZ) @@ -3084,8 +3083,7 @@ static int rtw_rereg_nd_name(struct net_device *dev, rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); } - strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); - rereg_priv->old_ifname[IFNAMSIZ - 1] = 0; + strscpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); if (!memcmp(new_ifname, "disable%d", 9)) { /* free network queue for Android's timming issue */ diff --git a/drivers/staging/r8188eu/os_dep/os_intfs.c b/drivers/staging/r8188eu/os_dep/os_intfs.c index 2f59bb994796..dc419fd1ffa5 100644 --- a/drivers/staging/r8188eu/os_dep/os_intfs.c +++ b/drivers/staging/r8188eu/os_dep/os_intfs.c @@ -392,9 +392,6 @@ static void rtw_init_default_value(struct adapter *padapter) struct security_priv *psecuritypriv = &padapter->securitypriv; /* xmit_priv */ - pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; - pxmitpriv->vcs = pregistrypriv->vcs_type; - pxmitpriv->vcs_type = pregistrypriv->vcs_type; pxmitpriv->frag_len = pregistrypriv->frag_thresh; /* mlme_priv */ @@ -485,7 +482,7 @@ u8 rtw_init_drv_sw(struct adapter *padapter) goto free_mlme_ext; } - if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) { + if (_rtw_init_recv_priv(&padapter->recvpriv, padapter)) { dev_err(dvobj_to_dev(padapter->dvobj), "_rtw_init_recv_priv failed\n"); goto free_xmit_priv; } @@ -634,8 +631,8 @@ static int _netdev_open(struct net_device *pnetdev) pr_info("can't init mlme_ext_priv\n"); goto netdev_open_error; } - if (padapter->intf_start) - padapter->intf_start(padapter); + if (rtl8188eu_inirp_init(padapter)) + goto netdev_open_error; rtw_led_control(padapter, LED_CTL_NO_LINK); @@ -687,8 +684,8 @@ static int ips_netdrv_open(struct adapter *padapter) if (status == _FAIL) goto netdev_open_error; - if (padapter->intf_start) - padapter->intf_start(padapter); + if (rtl8188eu_inirp_init(padapter)) + goto netdev_open_error; rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv); _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 5000); @@ -764,8 +761,8 @@ void rtw_ips_dev_unload(struct adapter *padapter) { rtw_fifo_cleanup(padapter); - if (padapter->intf_stop) - padapter->intf_stop(padapter); + rtw_read_port_cancel(padapter); + rtw_write_port_cancel(padapter); /* s5. */ if (!padapter->bSurpriseRemoved) diff --git a/drivers/staging/r8188eu/os_dep/usb_intf.c b/drivers/staging/r8188eu/os_dep/usb_intf.c index 5fbfbcd95de2..74a16d1757ce 100644 --- a/drivers/staging/r8188eu/os_dep/usb_intf.c +++ b/drivers/staging/r8188eu/os_dep/usb_intf.c @@ -152,22 +152,6 @@ static void usb_dvobj_deinit(struct usb_interface *usb_intf) } -static void usb_intf_start(struct adapter *padapter) -{ - rtl8188eu_inirp_init(padapter); -} - -static void usb_intf_stop(struct adapter *padapter) -{ - /* cancel in irp */ - rtw_read_port_cancel(padapter); - - /* cancel out irp */ - rtw_write_port_cancel(padapter); - - /* todo:cancel other irps */ -} - static void rtw_dev_unload(struct adapter *padapter) { if (padapter->bup) { @@ -175,8 +159,9 @@ static void rtw_dev_unload(struct adapter *padapter) if (padapter->xmitpriv.ack_tx) rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); /* s3. */ - if (padapter->intf_stop) - padapter->intf_stop(padapter); + rtw_read_port_cancel(padapter); + rtw_write_port_cancel(padapter); + /* s4. */ rtw_stop_drv_threads(padapter); @@ -290,8 +275,6 @@ static int rtw_usb_if1_init(struct dvobj_priv *dvobj, struct usb_interface *pusb { struct adapter *padapter = NULL; struct net_device *pnetdev = NULL; - struct io_priv *piopriv; - struct intf_hdl *pintf; int ret; padapter = vzalloc(sizeof(*padapter)); @@ -315,16 +298,6 @@ static int rtw_usb_if1_init(struct dvobj_priv *dvobj, struct usb_interface *pusb SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj)); padapter = rtw_netdev_priv(pnetdev); - padapter->intf_start = &usb_intf_start; - padapter->intf_stop = &usb_intf_stop; - - /* step init_io_priv */ - piopriv = &padapter->iopriv; - pintf = &piopriv->intf; - piopriv->padapter = padapter; - pintf->padapter = padapter; - pintf->pintf_dev = adapter_to_dvobj(padapter); - /* step read_chip_version */ rtl8188e_read_chip_version(padapter); diff --git a/drivers/staging/r8188eu/os_dep/usb_ops_linux.c b/drivers/staging/r8188eu/os_dep/usb_ops_linux.c index 220e592b757c..ca09f7ed7e4d 100644 --- a/drivers/staging/r8188eu/os_dep/usb_ops_linux.c +++ b/drivers/staging/r8188eu/os_dep/usb_ops_linux.c @@ -4,7 +4,6 @@ #define _USB_OPS_LINUX_C_ #include "../include/drv_types.h" -#include "../include/usb_ops_linux.h" #include "../include/rtl8188e_recv.h" static unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr) @@ -29,68 +28,40 @@ void rtw_read_port_cancel(struct adapter *padapter) for (i = 0; i < NR_RECVBUFF; i++) { precvbuf->reuse = true; - if (precvbuf->purb) - usb_kill_urb(precvbuf->purb); + usb_kill_urb(precvbuf->purb); precvbuf++; } } -static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) +static void usb_write_port_complete(struct urb *purb) { struct xmit_buf *pxmitbuf = (struct xmit_buf *)purb->context; - struct adapter *padapter = pxmitbuf->padapter; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct adapter *padapter = pxmitbuf->padapter; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - switch (pxmitbuf->flags) { - case VO_QUEUE_INX: - pxmitpriv->voq_cnt--; - break; - case VI_QUEUE_INX: - pxmitpriv->viq_cnt--; - break; - case BE_QUEUE_INX: - pxmitpriv->beq_cnt--; - break; - case BK_QUEUE_INX: - pxmitpriv->bkq_cnt--; - break; - case HIGH_QUEUE_INX: + if (pxmitbuf->high_queue) rtw_chk_hi_queue_cmd(padapter); + + switch (purb->status) { + case 0: + case -EINPROGRESS: + case -ENOENT: + case -ECONNRESET: + case -EPIPE: + case -EPROTO: + break; + case -ESHUTDOWN: + padapter->bDriverStopped = true; break; default: + padapter->bSurpriseRemoved = true; break; } - if (padapter->bSurpriseRemoved || padapter->bDriverStopped || - padapter->bWritePortCancel) - goto check_completion; - - if (purb->status) { - if (purb->status == -EINPROGRESS) { - goto check_completion; - } else if (purb->status == -ENOENT) { - goto check_completion; - } else if (purb->status == -ECONNRESET) { - goto check_completion; - } else if (purb->status == -ESHUTDOWN) { - padapter->bDriverStopped = true; - goto check_completion; - } else if ((purb->status != -EPIPE) && (purb->status != -EPROTO)) { - padapter->bSurpriseRemoved = true; - - goto check_completion; - } - } - -check_completion: rtw_sctx_done_err(&pxmitbuf->sctx, - purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : - RTW_SCTX_DONE_SUCCESS); - + purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); rtw_free_xmitbuf(pxmitpriv, pxmitbuf); - tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); - } u32 rtw_write_port(struct adapter *padapter, u32 addr, u32 cnt, u8 *wmem) @@ -112,32 +83,7 @@ u32 rtw_write_port(struct adapter *padapter, u32 addr, u32 cnt, u8 *wmem) } spin_lock_irqsave(&pxmitpriv->lock, irqL); - - switch (addr) { - case VO_QUEUE_INX: - pxmitpriv->voq_cnt++; - pxmitbuf->flags = VO_QUEUE_INX; - break; - case VI_QUEUE_INX: - pxmitpriv->viq_cnt++; - pxmitbuf->flags = VI_QUEUE_INX; - break; - case BE_QUEUE_INX: - pxmitpriv->beq_cnt++; - pxmitbuf->flags = BE_QUEUE_INX; - break; - case BK_QUEUE_INX: - pxmitpriv->bkq_cnt++; - pxmitbuf->flags = BK_QUEUE_INX; - break; - case HIGH_QUEUE_INX: - pxmitbuf->flags = HIGH_QUEUE_INX; - break; - default: - pxmitbuf->flags = MGT_QUEUE_INX; - break; - } - + pxmitbuf->high_queue = (addr == HIGH_QUEUE_INX); spin_unlock_irqrestore(&pxmitpriv->lock, irqL); purb = pxmitbuf->pxmit_urb; @@ -154,14 +100,8 @@ u32 rtw_write_port(struct adapter *padapter, u32 addr, u32 cnt, u8 *wmem) status = usb_submit_urb(purb, GFP_ATOMIC); if (status) { rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR); - - switch (status) { - case -ENODEV: + if (status == -ENODEV) padapter->bDriverStopped = true; - break; - default: - break; - } goto exit; } @@ -184,15 +124,13 @@ void rtw_write_port_cancel(struct adapter *padapter) padapter->bWritePortCancel = true; for (i = 0; i < NR_XMITBUFF; i++) { - if (pxmitbuf->pxmit_urb) - usb_kill_urb(pxmitbuf->pxmit_urb); + usb_kill_urb(pxmitbuf->pxmit_urb); pxmitbuf++; } pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmit_extbuf; for (i = 0; i < NR_XMIT_EXTBUFF; i++) { - if (pxmitbuf->pxmit_urb) - usb_kill_urb(pxmitbuf->pxmit_urb); + usb_kill_urb(pxmitbuf->pxmit_urb); pxmitbuf++; } } diff --git a/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c b/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c index ab2e9b729883..73a86e1d0701 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c @@ -21,7 +21,7 @@ void rtl92e_set_bandwidth(struct net_device *dev, return; } - for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) { + for (eRFPath = 0; eRFPath < priv->num_total_rf_path; eRFPath++) { if (!rtl92e_is_legal_rf_path(dev, eRFPath)) continue; @@ -63,14 +63,14 @@ bool rtl92e_config_rf(struct net_device *dev) u8 ConstRetryTimes = 5, RetryTimes = 5; u8 ret = 0; - priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; + priv->num_total_rf_path = RTL819X_TOTAL_RF_PATH; for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; - eRFPath < priv->NumTotalRFPath; eRFPath++) { + eRFPath < priv->num_total_rf_path; eRFPath++) { if (!rtl92e_is_legal_rf_path(dev, eRFPath)) continue; - pPhyReg = &priv->PHYRegDef[eRFPath]; + pPhyReg = &priv->phy_reg_def[eRFPath]; switch (eRFPath) { case RF90_PATH_A: @@ -150,11 +150,11 @@ void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel) struct r8192_priv *priv = rtllib_priv(dev); TxAGC = powerlevel; - if (priv->bDynamicTxLowPower) { - if (priv->CustomerID == RT_CID_819x_Netcore) + if (priv->dynamic_tx_low_pwr) { + if (priv->customer_id == RT_CID_819X_NETCORE) TxAGC = 0x22; else - TxAGC += priv->CckPwEnl; + TxAGC += priv->cck_pwr_enl; } if (TxAGC > 0x24) TxAGC = 0x24; @@ -169,7 +169,7 @@ void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel) u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; u8 byte0, byte1, byte2, byte3; - powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; + powerBase0 = powerlevel + priv->legacy_ht_tx_pwr_diff; powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | (powerBase0 << 8) | powerBase0; powerBase1 = powerlevel; @@ -177,7 +177,7 @@ void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel) (powerBase1 << 8) | powerBase1; for (index = 0; index < 6; index++) { - writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + + writeVal = (u32)(priv->mcs_tx_pwr_level_org_offset[index] + ((index < 2) ? powerBase0 : powerBase1)); byte0 = writeVal & 0x7f; byte1 = (writeVal & 0x7f00) >> 8; @@ -195,10 +195,10 @@ void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel) if (index == 3) { writeVal_tmp = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; - priv->Pwr_Track = writeVal_tmp; + priv->pwr_track = writeVal_tmp; } - if (priv->bDynamicTxHighPower) + if (priv->dynamic_tx_high_pwr) writeVal = 0x03030303; else writeVal = (byte3 << 24) | (byte2 << 16) | diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c index 8bf06f736ffb..eba8364d0ff2 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_cmdpkt.c @@ -76,7 +76,7 @@ bool rtl92e_send_cmd_pkt(struct net_device *dev, u32 type, const void *data, } while (frag_offset < len); - rtl92e_writeb(dev, TPPoll, TPPoll_CQ); + rtl92e_writeb(dev, TP_POLL, TP_POLL_CQ); Failed: return rt_status; } diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c index f02e67f68e23..0b5b2ae27f9e 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c @@ -54,22 +54,16 @@ static void _rtl92e_update_msr(struct net_device *dev) switch (priv->rtllib->iw_mode) { case IW_MODE_INFRA: if (priv->rtllib->state == RTLLIB_LINKED) - msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); - else - msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + msr |= MSR_LINK_MANAGED; LedAction = LED_CTL_LINK; break; case IW_MODE_ADHOC: if (priv->rtllib->state == RTLLIB_LINKED) - msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); - else - msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + msr |= MSR_LINK_ADHOC; break; case IW_MODE_MASTER: if (priv->rtllib->state == RTLLIB_LINKED) - msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); - else - msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); + msr |= MSR_LINK_MASTER; break; default: break; @@ -127,7 +121,7 @@ void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) Type = val[0]; RegRCR = rtl92e_readl(dev, RCR); - priv->ReceiveConfig = RegRCR; + priv->receive_config = RegRCR; if (Type) RegRCR |= (RCR_CBSSID); @@ -135,7 +129,7 @@ void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) RegRCR &= (~RCR_CBSSID); rtl92e_writel(dev, RCR, RegRCR); - priv->ReceiveConfig = RegRCR; + priv->receive_config = RegRCR; } break; @@ -222,41 +216,41 @@ void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val) union aci_aifsn *pAciAifsn = (union aci_aifsn *)& (qos_parameters->aifs[0]); u8 acm = pAciAifsn->f.acm; - u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl); + u8 AcmCtrl = rtl92e_readb(dev, ACM_HW_CTRL); if (acm) { switch (eACI) { case AC0_BE: - AcmCtrl |= AcmHw_BeqEn; + AcmCtrl |= ACM_HW_BEQ_EN; break; case AC2_VI: - AcmCtrl |= AcmHw_ViqEn; + AcmCtrl |= ACM_HW_VIQ_EN; break; case AC3_VO: - AcmCtrl |= AcmHw_VoqEn; + AcmCtrl |= ACM_HW_VOQ_EN; break; } } else { switch (eACI) { case AC0_BE: - AcmCtrl &= (~AcmHw_BeqEn); + AcmCtrl &= (~ACM_HW_BEQ_EN); break; case AC2_VI: - AcmCtrl &= (~AcmHw_ViqEn); + AcmCtrl &= (~ACM_HW_VIQ_EN); break; case AC3_VO: - AcmCtrl &= (~AcmHw_BeqEn); + AcmCtrl &= (~ACM_HW_BEQ_EN); break; default: break; } } - rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl); + rtl92e_writeb(dev, ACM_HW_CTRL, AcmCtrl); break; } @@ -292,21 +286,21 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev) if (EEPROMId != RTL8190_EEPROM_ID) { netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__, EEPROMId); - priv->AutoloadFailFlag = true; + priv->autoload_fail_flag = true; } else { - priv->AutoloadFailFlag = false; + priv->autoload_fail_flag = false; } - if (!priv->AutoloadFailFlag) { + if (!priv->autoload_fail_flag) { priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1); priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1); usValue = rtl92e_eeprom_read(dev, (EEPROM_Customer_ID >> 1)) >> 8; - priv->eeprom_CustomerID = usValue & 0xff; + priv->eeprom_customer_id = usValue & 0xff; usValue = rtl92e_eeprom_read(dev, EEPROM_ICVersion_ChannelPlan>>1); - priv->eeprom_ChannelPlan = usValue&0xff; + priv->eeprom_chnl_plan = usValue&0xff; IC_Version = (usValue & 0xff00)>>8; ICVer8192 = IC_Version & 0xf; @@ -327,11 +321,11 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev) priv->card_8192_version = VERSION_8190_BD; priv->eeprom_vid = 0; priv->eeprom_did = 0; - priv->eeprom_CustomerID = 0; - priv->eeprom_ChannelPlan = 0; + priv->eeprom_customer_id = 0; + priv->eeprom_chnl_plan = 0; } - if (!priv->AutoloadFailFlag) { + if (!priv->autoload_fail_flag) { u8 addr[ETH_ALEN]; for (i = 0; i < 6; i += 2) { @@ -345,125 +339,94 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev) } if (priv->card_8192_version > VERSION_8190_BD) - priv->bTXPowerDataReadFromEEPORM = true; + priv->tx_pwr_data_read_from_eeprom = true; else - priv->bTXPowerDataReadFromEEPORM = false; + priv->tx_pwr_data_read_from_eeprom = false; priv->rf_type = RTL819X_DEFAULT_RF_TYPE; if (priv->card_8192_version > VERSION_8190_BD) { - if (!priv->AutoloadFailFlag) { + if (!priv->autoload_fail_flag) { tempval = (rtl92e_eeprom_read(dev, (EEPROM_RFInd_PowerDiff >> 1))) & 0xff; - priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf; + priv->eeprom_legacy_ht_tx_pwr_diff = tempval & 0xf; if (tempval&0x80) priv->rf_type = RF_1T2R; else priv->rf_type = RF_2T4R; } else { - priv->EEPROMLegacyHTTxPowerDiff = 0x04; + priv->eeprom_legacy_ht_tx_pwr_diff = 0x04; } - if (!priv->AutoloadFailFlag) - priv->EEPROMThermalMeter = ((rtl92e_eeprom_read(dev, + if (!priv->autoload_fail_flag) + priv->eeprom_thermal_meter = ((rtl92e_eeprom_read(dev, (EEPROM_ThermalMeter>>1))) & 0xff00) >> 8; else - priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter; - priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100; + priv->eeprom_thermal_meter = EEPROM_Default_ThermalMeter; + priv->tssi_13dBm = priv->eeprom_thermal_meter * 100; if (priv->epromtype == EEPROM_93C46) { - if (!priv->AutoloadFailFlag) { + if (!priv->autoload_fail_flag) { usValue = rtl92e_eeprom_read(dev, EEPROM_TxPwDiff_CrystalCap >> 1); - priv->EEPROMAntPwDiff = usValue & 0x0fff; - priv->EEPROMCrystalCap = (usValue & 0xf000) + priv->eeprom_ant_pwr_diff = usValue & 0x0fff; + priv->eeprom_crystal_cap = (usValue & 0xf000) >> 12; } else { - priv->EEPROMAntPwDiff = + priv->eeprom_ant_pwr_diff = EEPROM_Default_AntTxPowerDiff; - priv->EEPROMCrystalCap = + priv->eeprom_crystal_cap = EEPROM_Default_TxPwDiff_CrystalCap; } for (i = 0; i < 14; i += 2) { - if (!priv->AutoloadFailFlag) + if (!priv->autoload_fail_flag) usValue = rtl92e_eeprom_read(dev, (EEPROM_TxPwIndex_CCK + i) >> 1); else usValue = EEPROM_Default_TxPower; - *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) = + *((u16 *)(&priv->eeprom_tx_pwr_level_cck[i])) = usValue; } for (i = 0; i < 14; i += 2) { - if (!priv->AutoloadFailFlag) + if (!priv->autoload_fail_flag) usValue = rtl92e_eeprom_read(dev, (EEPROM_TxPwIndex_OFDM_24G + i) >> 1); else usValue = EEPROM_Default_TxPower; - *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i])) + *((u16 *)(&priv->eeprom_tx_pwr_level_ofdm24g[i])) = usValue; } } if (priv->epromtype == EEPROM_93C46) { for (i = 0; i < 14; i++) { - priv->TxPowerLevelCCK[i] = - priv->EEPROMTxPowerLevelCCK[i]; - priv->TxPowerLevelOFDM24G[i] = - priv->EEPROMTxPowerLevelOFDM24G[i]; + priv->tx_pwr_level_cck[i] = + priv->eeprom_tx_pwr_level_cck[i]; + priv->tx_pwr_level_ofdm_24g[i] = + priv->eeprom_tx_pwr_level_ofdm24g[i]; } - priv->LegacyHTTxPowerDiff = - priv->EEPROMLegacyHTTxPowerDiff; - priv->AntennaTxPwDiff[0] = priv->EEPROMAntPwDiff & 0xf; - priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff & + priv->legacy_ht_tx_pwr_diff = + priv->eeprom_legacy_ht_tx_pwr_diff; + priv->antenna_tx_pwr_diff[0] = priv->eeprom_ant_pwr_diff & 0xf; + priv->antenna_tx_pwr_diff[1] = (priv->eeprom_ant_pwr_diff & 0xf0) >> 4; - priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff & + priv->antenna_tx_pwr_diff[2] = (priv->eeprom_ant_pwr_diff & 0xf00) >> 8; - priv->CrystalCap = priv->EEPROMCrystalCap; - priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf; - priv->ThermalMeter[1] = (priv->EEPROMThermalMeter & + priv->crystal_cap = priv->eeprom_crystal_cap; + priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf; + priv->thermal_meter[1] = (priv->eeprom_thermal_meter & 0xf0) >> 4; } else if (priv->epromtype == EEPROM_93C56) { - - for (i = 0; i < 3; i++) { - priv->TxPowerLevelCCK_A[i] = - priv->EEPROMRfACCKChnl1TxPwLevel[0]; - priv->TxPowerLevelOFDM24G_A[i] = - priv->EEPROMRfAOfdmChnlTxPwLevel[0]; - priv->TxPowerLevelCCK_C[i] = - priv->EEPROMRfCCCKChnl1TxPwLevel[0]; - priv->TxPowerLevelOFDM24G_C[i] = - priv->EEPROMRfCOfdmChnlTxPwLevel[0]; - } - for (i = 3; i < 9; i++) { - priv->TxPowerLevelCCK_A[i] = - priv->EEPROMRfACCKChnl1TxPwLevel[1]; - priv->TxPowerLevelOFDM24G_A[i] = - priv->EEPROMRfAOfdmChnlTxPwLevel[1]; - priv->TxPowerLevelCCK_C[i] = - priv->EEPROMRfCCCKChnl1TxPwLevel[1]; - priv->TxPowerLevelOFDM24G_C[i] = - priv->EEPROMRfCOfdmChnlTxPwLevel[1]; - } - for (i = 9; i < 14; i++) { - priv->TxPowerLevelCCK_A[i] = - priv->EEPROMRfACCKChnl1TxPwLevel[2]; - priv->TxPowerLevelOFDM24G_A[i] = - priv->EEPROMRfAOfdmChnlTxPwLevel[2]; - priv->TxPowerLevelCCK_C[i] = - priv->EEPROMRfCCCKChnl1TxPwLevel[2]; - priv->TxPowerLevelOFDM24G_C[i] = - priv->EEPROMRfCOfdmChnlTxPwLevel[2]; - } - priv->LegacyHTTxPowerDiff = - priv->EEPROMLegacyHTTxPowerDiff; - priv->AntennaTxPwDiff[0] = 0; - priv->AntennaTxPwDiff[1] = 0; - priv->AntennaTxPwDiff[2] = 0; - priv->CrystalCap = priv->EEPROMCrystalCap; - priv->ThermalMeter[0] = priv->EEPROMThermalMeter & 0xf; - priv->ThermalMeter[1] = (priv->EEPROMThermalMeter & + priv->legacy_ht_tx_pwr_diff = + priv->eeprom_legacy_ht_tx_pwr_diff; + priv->antenna_tx_pwr_diff[0] = 0; + priv->antenna_tx_pwr_diff[1] = 0; + priv->antenna_tx_pwr_diff[2] = 0; + priv->crystal_cap = priv->eeprom_crystal_cap; + priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf; + priv->thermal_meter[1] = (priv->eeprom_thermal_meter & 0xf0) >> 4; } } @@ -473,41 +436,41 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev) priv->rf_chip = RF_8256; if (priv->reg_chnl_plan == 0xf) - priv->ChannelPlan = priv->eeprom_ChannelPlan; + priv->chnl_plan = priv->eeprom_chnl_plan; else - priv->ChannelPlan = priv->reg_chnl_plan; + priv->chnl_plan = priv->reg_chnl_plan; if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) - priv->CustomerID = RT_CID_DLINK; + priv->customer_id = RT_CID_DLINK; - switch (priv->eeprom_CustomerID) { + switch (priv->eeprom_customer_id) { case EEPROM_CID_DEFAULT: - priv->CustomerID = RT_CID_DEFAULT; + priv->customer_id = RT_CID_DEFAULT; break; case EEPROM_CID_CAMEO: - priv->CustomerID = RT_CID_819x_CAMEO; + priv->customer_id = RT_CID_819x_CAMEO; break; case EEPROM_CID_RUNTOP: - priv->CustomerID = RT_CID_819x_RUNTOP; + priv->customer_id = RT_CID_819x_RUNTOP; break; case EEPROM_CID_NetCore: - priv->CustomerID = RT_CID_819x_Netcore; + priv->customer_id = RT_CID_819X_NETCORE; break; case EEPROM_CID_TOSHIBA: - priv->CustomerID = RT_CID_TOSHIBA; - if (priv->eeprom_ChannelPlan&0x80) - priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f; + priv->customer_id = RT_CID_TOSHIBA; + if (priv->eeprom_chnl_plan & 0x80) + priv->chnl_plan = priv->eeprom_chnl_plan & 0x7f; else - priv->ChannelPlan = 0x0; + priv->chnl_plan = 0x0; break; case EEPROM_CID_Nettronix: - priv->CustomerID = RT_CID_Nettronix; + priv->customer_id = RT_CID_Nettronix; break; case EEPROM_CID_Pronet: - priv->CustomerID = RT_CID_PRONET; + priv->customer_id = RT_CID_PRONET; break; case EEPROM_CID_DLINK: - priv->CustomerID = RT_CID_DLINK; + priv->customer_id = RT_CID_DLINK; break; case EEPROM_CID_WHQL: @@ -516,9 +479,9 @@ static void _rtl92e_read_eeprom_info(struct net_device *dev) break; } - if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1) - priv->ChannelPlan = 0; - priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13; + if (priv->chnl_plan > CHANNEL_PLAN_LEN - 1) + priv->chnl_plan = 0; + priv->chnl_plan = COUNTRY_CODE_WORLD_WIDE_13; if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304) priv->rtllib->bSupportRemoteWakeUp = true; @@ -594,8 +557,8 @@ static void _rtl92e_hwconfig(struct net_device *dev) rtl92e_writel(dev, RRSR, regRRSR); rtl92e_writew(dev, RETRY_LIMIT, - priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT | - priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT); + priv->short_retry_limit << RETRY_LIMIT_SHORT_SHIFT | + priv->long_retry_limit << RETRY_LIMIT_LONG_SHIFT); } bool rtl92e_start_adapter(struct net_device *dev) @@ -614,21 +577,21 @@ bool rtl92e_start_adapter(struct net_device *dev) start: rtl92e_reset_desc_ring(dev); - priv->Rf_Mode = RF_OP_By_SW_3wire; + priv->rf_mode = RF_OP_By_SW_3wire; if (priv->rst_progress == RESET_TYPE_NORESET) { rtl92e_writeb(dev, ANAPAR, 0x37); mdelay(500); } - priv->pFirmware->status = FW_STATUS_0_INIT; + priv->fw_info->status = FW_STATUS_0_INIT; ulRegRead = rtl92e_readl(dev, CPU_GEN); - if (priv->pFirmware->status == FW_STATUS_0_INIT) + if (priv->fw_info->status == FW_STATUS_0_INIT) ulRegRead |= CPU_GEN_SYSTEM_RESET; - else if (priv->pFirmware->status == FW_STATUS_5_READY) + else if (priv->fw_info->status == FW_STATUS_5_READY) ulRegRead |= CPU_GEN_FIRMWARE_RESET; else netdev_err(dev, "%s(): undefined firmware state: %d.\n", - __func__, priv->pFirmware->status); + __func__, priv->fw_info->status); rtl92e_writel(dev, CPU_GEN, ulRegRead); @@ -647,13 +610,13 @@ start: return rtStatus; } - priv->LoopbackMode = RTL819X_NO_LOOPBACK; + priv->loopback_mode = RTL819X_NO_LOOPBACK; if (priv->rst_progress == RESET_TYPE_NORESET) { ulRegRead = rtl92e_readl(dev, CPU_GEN); - if (priv->LoopbackMode == RTL819X_NO_LOOPBACK) + if (priv->loopback_mode == RTL819X_NO_LOOPBACK) ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) | CPU_GEN_NO_LOOPBACK_SET; - else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK) + else if (priv->loopback_mode == RTL819X_MAC_LOOPBACK) ulRegRead |= CPU_CCK_LOOPBACK; else netdev_err(dev, "%s: Invalid loopback mode setting.\n", @@ -666,11 +629,11 @@ start: _rtl92e_hwconfig(dev); rtl92e_writeb(dev, CMDR, CR_RE | CR_TE); - rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<dev_addr)[0]); rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]); - rtl92e_writel(dev, RCR, priv->ReceiveConfig); + rtl92e_writel(dev, RCR, priv->receive_config); rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK << RSVD_FW_QUEUE_PAGE_BK_SHIFT | @@ -724,7 +687,7 @@ start: } tmpvalue = rtl92e_readb(dev, IC_VERRSION); - priv->IC_Cut = tmpvalue; + priv->ic_cut = tmpvalue; bfirmwareok = rtl92e_init_fw(dev); if (!bfirmwareok) { @@ -760,19 +723,19 @@ start: } if (priv->rtllib->FwRWRF) - priv->Rf_Mode = RF_OP_By_FW; + priv->rf_mode = RF_OP_By_FW; else - priv->Rf_Mode = RF_OP_By_SW_3wire; + priv->rf_mode = RF_OP_By_SW_3wire; if (priv->rst_progress == RESET_TYPE_NORESET) { rtl92e_dm_init_txpower_tracking(dev); - if (priv->IC_Cut >= IC_VersionCut_D) { + if (priv->ic_cut >= IC_VersionCut_D) { tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord); - for (i = 0; i < TxBBGainTableLength; i++) { + for (i = 0; i < TX_BB_GAIN_TABLE_LEN; i++) { if (tmpRegA == dm_tx_bb_gain[i]) { priv->rfa_txpowertrackingindex = i; priv->rfa_txpowertrackingindex_real = i; @@ -785,16 +748,16 @@ start: TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1, bMaskByte2); - for (i = 0; i < CCKTxBBGainTableLength; i++) { + for (i = 0; i < CCK_TX_BB_GAIN_TABLE_LEN; i++) { if (TempCCk == dm_cck_tx_bb_gain[i][0]) { - priv->CCKPresentAttentuation_20Mdefault = i; + priv->cck_present_attn_20m_def = i; break; } } - priv->CCKPresentAttentuation_40Mdefault = 0; - priv->CCKPresentAttentuation_difference = 0; + priv->cck_present_attn_40m_def = 0; + priv->cck_present_attn_diff = 0; priv->cck_present_attn = - priv->CCKPresentAttentuation_20Mdefault; + priv->cck_present_attn_20m_def; priv->btxpower_tracking = false; } } @@ -860,9 +823,9 @@ void rtl92e_link_change(struct net_device *dev) if (ieee->intel_promiscuous_md_info.promiscuous_on) ; else - priv->ReceiveConfig = reg |= RCR_CBSSID; + priv->receive_config = reg |= RCR_CBSSID; } else - priv->ReceiveConfig = reg &= ~RCR_CBSSID; + priv->receive_config = reg &= ~RCR_CBSSID; rtl92e_writel(dev, RCR, reg); } @@ -874,12 +837,12 @@ void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA, struct r8192_priv *priv = rtllib_priv(dev); if (bAllowAllDA) - priv->ReceiveConfig |= RCR_AAP; + priv->receive_config |= RCR_AAP; else - priv->ReceiveConfig &= ~RCR_AAP; + priv->receive_config &= ~RCR_AAP; if (WriteIntoReg) - rtl92e_writel(dev, RCR, priv->ReceiveConfig); + rtl92e_writel(dev, RCR, priv->receive_config); } static u8 _rtl92e_rate_mgn_to_hw(u8 rate) @@ -1068,13 +1031,13 @@ void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc, pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ? (cb_desc->bRTSUseShortPreamble ? 1 : 0) : (cb_desc->bRTSUseShortGI ? 1 : 0); - if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) { + if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20_40) { if (cb_desc->bPacketBW) { pTxFwInfo->TxBandwidth = 1; pTxFwInfo->TxSubCarrier = 0; } else { pTxFwInfo->TxBandwidth = 0; - pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC; + pTxFwInfo->TxSubCarrier = priv->n_cur_40mhz_prime_sc; } } else { pTxFwInfo->TxBandwidth = 0; @@ -1327,11 +1290,10 @@ static void _rtl92e_query_rxphystatus( { struct phy_sts_ofdm_819xpci *pofdm_buf; struct phy_sts_cck_819xpci *pcck_buf; - struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc; u8 *prxpkt; - u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg; + u8 i, max_spatial_stream, tmp_rxevm; s8 rx_pwr[4], rx_pwr_all = 0; - s8 rx_snrX, rx_evmX; + s8 rx_evmX; u8 evm, pwdb_all; u32 RSSI, total_rssi = 0; u8 is_cck_rate = 0; @@ -1339,8 +1301,6 @@ static void _rtl92e_query_rxphystatus( static u8 check_reg824; static u32 reg824_bit9; - priv->stats.numqry_phystatus++; - is_cck_rate = rx_hal_is_cck_rate(pdrvinfo); memset(precord_stats, 0, sizeof(struct rtllib_rx_stats)); pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID = @@ -1372,7 +1332,6 @@ static void _rtl92e_query_rxphystatus( if (is_cck_rate) { u8 report; - priv->stats.numqry_phystatusCCK++; if (!reg824_bit9) { report = pcck_buf->cck_agc_rpt & 0xc0; report >>= 6; @@ -1447,7 +1406,6 @@ static void _rtl92e_query_rxphystatus( precord_stats->RxMIMOSignalQuality[1] = -1; } } else { - priv->stats.numqry_phystatusHT++; for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { if (priv->brfpath_rxenable[i]) rf_rx_num++; @@ -1455,11 +1413,6 @@ static void _rtl92e_query_rxphystatus( rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) * 2) - 110; - tmp_rxsnr = pofdm_buf->rxsnr_X[i]; - rx_snrX = (s8)(tmp_rxsnr); - rx_snrX /= 2; - priv->stats.rxSNRdB[i] = (long)rx_snrX; - RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]); if (priv->brfpath_rxenable[i]) total_rssi += RSSI; @@ -1499,15 +1452,6 @@ static void _rtl92e_query_rxphystatus( precord_stats->RxMIMOSignalQuality[i] = evm & 0xff; } } - - - rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg; - prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *) - &rxsc_sgien_exflg; - if (pdrvinfo->BW) - priv->stats.received_bwtype[1+prxsc->rxsc]++; - else - priv->stats.received_bwtype[0]++; } if (is_cck_rate) { @@ -1570,7 +1514,6 @@ static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer, if (!bcheck) return; - priv->stats.num_process_phyinfo++; if (!prev_st->bIsCCK && prev_st->bPacketToSelf) { for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) { if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath)) @@ -1605,17 +1548,17 @@ static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer, PHY_Beacon_RSSI_SLID_WIN_MAX) { slide_beacon_adc_pwdb_statistics = PHY_Beacon_RSSI_SLID_WIN_MAX; - last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb + last_beacon_adc_pwdb = priv->stats.slide_beacon_pwdb [slide_beacon_adc_pwdb_index]; - priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb; + priv->stats.slide_beacon_total -= last_beacon_adc_pwdb; } - priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll; - priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] = + priv->stats.slide_beacon_total += prev_st->RxPWDBAll; + priv->stats.slide_beacon_pwdb[slide_beacon_adc_pwdb_index] = prev_st->RxPWDBAll; slide_beacon_adc_pwdb_index++; if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX) slide_beacon_adc_pwdb_index = 0; - prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total / + prev_st->RxPWDBAll = priv->stats.slide_beacon_total / slide_beacon_adc_pwdb_statistics; if (prev_st->RxPWDBAll >= 3) prev_st->RxPWDBAll -= 3; @@ -1659,7 +1602,6 @@ static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer, tmp_val = priv->stats.slide_evm_total / slide_evm_statistics; - priv->stats.signal_quality = tmp_val; priv->stats.last_signal_strength_inpercent = tmp_val; } @@ -1716,10 +1658,6 @@ static void _rtl92e_translate_rx_signal_stats(struct net_device *dev, ether_addr_equal(praddr, priv->rtllib->dev->dev_addr); if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON) bPacketBeacon = true; - if (bpacket_match_bssid) - priv->stats.numpacket_matchbssid++; - if (bpacket_toself) - priv->stats.numpacket_toself++; _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats); _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo, &previous_stats, bpacket_match_bssid, @@ -1734,18 +1672,12 @@ static void _rtl92e_update_received_rate_histogram_stats( struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev); u32 rcvType = 1; u32 rateIndex; - u32 preamble_guardinterval; if (pstats->bCRC) rcvType = 2; else if (pstats->bICV) rcvType = 3; - if (pstats->bShortPreamble) - preamble_guardinterval = 1; - else - preamble_guardinterval = 0; - switch (pstats->rate) { case MGN_1M: rateIndex = 0; @@ -1835,7 +1767,6 @@ static void _rtl92e_update_received_rate_histogram_stats( rateIndex = 28; break; } - priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++; priv->stats.received_rate_histogram[0][rateIndex]++; priv->stats.received_rate_histogram[rcvType][rateIndex]++; } @@ -1843,7 +1774,6 @@ static void _rtl92e_update_received_rate_histogram_stats( bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats, struct rx_desc *pdesc, struct sk_buff *skb) { - struct r8192_priv *priv = rtllib_priv(dev); struct rx_fwinfo *pDrvInfo = NULL; stats->bICV = pdesc->ICV; @@ -1856,15 +1786,6 @@ bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats, if (stats->bHwError) { stats->bShift = false; - - if (pdesc->CRC32) { - if (pdesc->Length < 500) - priv->stats.rxcrcerrmin++; - else if (pdesc->Length > 1000) - priv->stats.rxcrcerrmax++; - else - priv->stats.rxcrcerrmid++; - } return false; } @@ -1895,7 +1816,7 @@ bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats, stats->RxIs40MHzPacket = pDrvInfo->BW; _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo); - skb_trim(skb, skb->len - 4/*sCrcLng*/); + skb_trim(skb, skb->len - S_CRC_LEN); stats->packetlength = stats->Length-4; @@ -1940,7 +1861,7 @@ void rtl92e_stop_adapter(struct net_device *dev, bool reset) rtl92e_writeb(dev, PMR, 0x5); - rtl92e_writeb(dev, MacBlkCtrl, 0xa); + rtl92e_writeb(dev, MAC_BLK_CTRL, 0xa); } } @@ -2010,10 +1931,10 @@ rtl92e_init_variables(struct net_device *dev) priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci); - priv->ShortRetryLimit = 0x30; - priv->LongRetryLimit = 0x30; + priv->short_retry_limit = 0x30; + priv->long_retry_limit = 0x30; - priv->ReceiveConfig = RCR_ADD3 | + priv->receive_config = RCR_ADD3 | RCR_AMF | RCR_ADF | RCR_AICV | RCR_AB | RCR_AM | RCR_APM | @@ -2027,8 +1948,6 @@ rtl92e_init_variables(struct net_device *dev) IMR_RDU | IMR_RXFOVW | IMR_TXFOVW | IMR_BcnInt | IMR_TBDOK | IMR_TBDER); - priv->PwrDomainProtect = false; - priv->bfirst_after_down = false; } @@ -2098,21 +2017,21 @@ bool rtl92e_is_rx_stuck(struct net_device *dev) u8 SilentResetRxSoltNum = 4; rx_chk_cnt++; - if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) { + if (priv->undecorated_smoothed_pwdb >= (RATE_ADAPTIVE_TH_HIGH + 5)) { rx_chk_cnt = 0; - } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5)) - && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && - (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M)) - || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && - (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) { + } else if ((priv->undecorated_smoothed_pwdb < (RATE_ADAPTIVE_TH_HIGH + 5)) + && (((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_40M)) + || ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_20M)))) { if (rx_chk_cnt < 2) return bStuck; rx_chk_cnt = 0; - } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) && - (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) || - ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) && - (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) && - priv->undecorated_smoothed_pwdb >= VeryLowRSSI) { + } else if ((((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_40M)) || + ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) && + (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_20M))) && + priv->undecorated_smoothed_pwdb >= VERY_LOW_RSSI) { if (rx_chk_cnt < 4) return bStuck; rx_chk_cnt = 0; @@ -2123,24 +2042,24 @@ bool rtl92e_is_rx_stuck(struct net_device *dev) } - SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum; + SlotIndex = (priv->silent_reset_rx_slot_index++)%SilentResetRxSoltNum; if (priv->rx_ctr == RegRxCounter) { - priv->SilentResetRxStuckEvent[SlotIndex] = 1; + priv->silent_reset_rx_stuck_event[SlotIndex] = 1; for (i = 0; i < SilentResetRxSoltNum; i++) - TotalRxStuckCount += priv->SilentResetRxStuckEvent[i]; + TotalRxStuckCount += priv->silent_reset_rx_stuck_event[i]; if (TotalRxStuckCount == SilentResetRxSoltNum) { bStuck = true; for (i = 0; i < SilentResetRxSoltNum; i++) TotalRxStuckCount += - priv->SilentResetRxStuckEvent[i]; + priv->silent_reset_rx_stuck_event[i]; } } else { - priv->SilentResetRxStuckEvent[SlotIndex] = 0; + priv->silent_reset_rx_stuck_event[SlotIndex] = 0; } priv->rx_ctr = RegRxCounter; @@ -2154,10 +2073,10 @@ bool rtl92e_is_tx_stuck(struct net_device *dev) bool bStuck = false; u16 RegTxCounter = rtl92e_readw(dev, 0x128); - if (priv->TxCounter == RegTxCounter) + if (priv->tx_counter == RegTxCounter) bStuck = true; - priv->TxCounter = RegTxCounter; + priv->tx_counter = RegTxCounter; return bStuck; } diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c index 789d288d7503..b011ec8c8a41 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_firmware.c @@ -51,7 +51,7 @@ static bool _rtl92e_fw_check_ready(struct net_device *dev, u8 load_fw_status) { struct r8192_priv *priv = rtllib_priv(dev); - struct rt_firmware *pfirmware = priv->pFirmware; + struct rt_firmware *pfirmware = priv->fw_info; bool rt_status = true; switch (load_fw_status) { @@ -134,7 +134,7 @@ bool rtl92e_init_fw(struct net_device *dev) enum opt_rst_type rst_opt = OPT_SYSTEM_RESET; enum firmware_init_step starting_state = FW_INIT_STEP0_BOOT; - struct rt_firmware *pfirmware = priv->pFirmware; + struct rt_firmware *pfirmware = priv->fw_info; netdev_dbg(dev, " PlatformInitFirmware()==>\n"); diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h index 3e223151d4b7..99640c4779f7 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_hw.h @@ -8,141 +8,72 @@ #define R8180_HW enum baseband_config { - BaseBand_Config_PHY_REG = 0, - BaseBand_Config_AGC_TAB = 1, + BB_CONFIG_PHY_REG = 0, + BB_CONFIG_AGC_TAB = 1, }; -#define RTL8187_REQT_READ 0xc0 -#define RTL8187_REQT_WRITE 0x40 -#define RTL8187_REQ_GET_REGS 0x05 -#define RTL8187_REQ_SET_REGS 0x05 - -#define MAX_TX_URB 5 -#define MAX_RX_URB 16 -#define RX_URB_SIZE 9100 - -#define BB_ANTATTEN_CHAN14 0x0c -#define BB_ANTENNA_B 0x40 - -#define BB_HOST_BANG (1<<30) -#define BB_HOST_BANG_EN (1<<2) -#define BB_HOST_BANG_CLK (1<<1) -#define BB_HOST_BANG_RW (1<<3) -#define BB_HOST_BANG_DATA 1 - #define RTL8190_EEPROM_ID 0x8129 #define EEPROM_VID 0x02 #define EEPROM_DID 0x04 #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C -#define EEPROM_TxPowerDiff 0x1F - - -#define EEPROM_PwDiff 0x21 -#define EEPROM_CrystalCap 0x22 - - - -#define EEPROM_TxPwIndex_CCK_V1 0x29 -#define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C -#define EEPROM_TxPwIndex_Ver 0x27 - -#define EEPROM_Default_TxPowerDiff 0x0 #define EEPROM_Default_ThermalMeter 0x77 #define EEPROM_Default_AntTxPowerDiff 0x0 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5 -#define EEPROM_Default_PwDiff 0x4 -#define EEPROM_Default_CrystalCap 0x5 #define EEPROM_Default_TxPower 0x1010 #define EEPROM_ICVersion_ChannelPlan 0x7C #define EEPROM_Customer_ID 0x7B #define EEPROM_RFInd_PowerDiff 0x28 + #define EEPROM_ThermalMeter 0x29 #define EEPROM_TxPwDiff_CrystalCap 0x2A #define EEPROM_TxPwIndex_CCK 0x2C #define EEPROM_TxPwIndex_OFDM_24G 0x3A -#define EEPROM_Default_TxPowerLevel 0x10 -#define EEPROM_IC_VER 0x7d -#define EEPROM_CRC 0x7e #define EEPROM_CID_DEFAULT 0x0 #define EEPROM_CID_CAMEO 0x1 #define EEPROM_CID_RUNTOP 0x2 -#define EEPROM_CID_Senao 0x3 #define EEPROM_CID_TOSHIBA 0x4 #define EEPROM_CID_NetCore 0x5 #define EEPROM_CID_Nettronix 0x6 #define EEPROM_CID_Pronet 0x7 #define EEPROM_CID_DLINK 0x8 #define EEPROM_CID_WHQL 0xFE -enum _RTL8192Pci_HW { +enum _RTL8192PCI_HW { MAC0 = 0x000, - MAC1 = 0x001, - MAC2 = 0x002, - MAC3 = 0x003, MAC4 = 0x004, - MAC5 = 0x005, PCIF = 0x009, -#define MXDMA2_16bytes 0x000 -#define MXDMA2_32bytes 0x001 -#define MXDMA2_64bytes 0x010 -#define MXDMA2_128bytes 0x011 -#define MXDMA2_256bytes 0x100 -#define MXDMA2_512bytes 0x101 -#define MXDMA2_1024bytes 0x110 -#define MXDMA2_NoLimit 0x7 +#define MXDMA2_NO_LIMIT 0x7 -#define MULRW_SHIFT 3 #define MXDMA2_RX_SHIFT 4 #define MXDMA2_TX_SHIFT 0 PMR = 0x00c, EPROM_CMD = 0x00e, -#define EPROM_CMD_RESERVED_MASK BIT5 + #define EPROM_CMD_9356SEL BIT4 #define EPROM_CMD_OPERATING_MODE_SHIFT 6 -#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) -#define EPROM_CMD_CONFIG 0x3 #define EPROM_CMD_NORMAL 0 -#define EPROM_CMD_LOAD 1 #define EPROM_CMD_PROGRAM 2 #define EPROM_CS_BIT 3 #define EPROM_CK_BIT 2 #define EPROM_W_BIT 1 #define EPROM_R_BIT 0 - AFR = 0x010, -#define AFR_CardBEn (1<<0) -#define AFR_CLKRUN_SEL (1<<1) -#define AFR_FuncRegEn (1<<2) - ANAPAR = 0x17, #define BB_GLOBAL_RESET_BIT 0x1 BB_GLOBAL_RESET = 0x020, BSSIDR = 0x02E, CMDR = 0x037, -#define CR_RST 0x10 #define CR_RE 0x08 #define CR_TE 0x04 -#define CR_MulRW 0x01 SIFS = 0x03E, - TCR = 0x040, RCR = 0x044, -#define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ - BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23) #define RCR_ONLYERLPKT BIT31 -#define RCR_ENCS2 BIT30 -#define RCR_ENCS1 BIT29 -#define RCR_ENMBID BIT27 -#define RCR_ACKTXBW (BIT24|BIT25) #define RCR_CBSSID BIT23 -#define RCR_APWRMGT BIT22 #define RCR_ADD3 BIT21 #define RCR_AMF BIT20 -#define RCR_ACF BIT19 #define RCR_ADF BIT18 -#define RCR_RXFTH BIT13 #define RCR_AICV BIT12 -#define RCR_ACRC32 BIT5 #define RCR_AB BIT3 #define RCR_AM BIT2 #define RCR_APM BIT1 @@ -151,8 +82,6 @@ enum _RTL8192Pci_HW { #define RCR_FIFO_OFFSET 13 SLOT_TIME = 0x049, ACK_TIMEOUT = 0x04c, - PIFS_TIME = 0x04d, - USTIME = 0x04e, EDCAPARA_BE = 0x050, EDCAPARA_BK = 0x054, EDCAPARA_VO = 0x058, @@ -161,53 +90,25 @@ enum _RTL8192Pci_HW { #define AC_PARAM_ECW_MAX_OFFSET 12 #define AC_PARAM_ECW_MIN_OFFSET 8 #define AC_PARAM_AIFS_OFFSET 0 - RFPC = 0x05F, - CWRR = 0x060, BCN_TCFG = 0x062, #define BCN_TCFG_CW_SHIFT 8 #define BCN_TCFG_IFS 0 BCN_INTERVAL = 0x070, ATIMWND = 0x072, BCN_DRV_EARLY_INT = 0x074, -#define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8 -#define BCN_DRV_EARLY_INT_TIME_SHIFT 0 BCN_DMATIME = 0x076, BCN_ERR_THRESH = 0x078, RWCAM = 0x0A0, -#define CAM_CM_SecCAMPolling BIT31 -#define CAM_CM_SecCAMClr BIT30 -#define CAM_CM_SecCAMWE BIT16 -#define CAM_VALID BIT15 -#define CAM_NOTVALID 0x0000 -#define CAM_USEDK BIT5 - -#define CAM_NONE 0x0 -#define CAM_WEP40 0x01 -#define CAM_TKIP 0x02 -#define CAM_AES 0x04 -#define CAM_WEP104 0x05 - #define TOTAL_CAM_ENTRY 32 - -#define CAM_CONFIG_USEDK true -#define CAM_CONFIG_NO_USEDK false -#define CAM_WRITE BIT16 -#define CAM_READ 0x00000000 -#define CAM_POLLINIG BIT31 -#define SCR_UseDK 0x01 WCAMI = 0x0A4, - RCAMO = 0x0A8, SECR = 0x0B0, #define SCR_TxUseDK BIT0 #define SCR_RxUseDK BIT1 #define SCR_TxEncEnable BIT2 #define SCR_RxDecEnable BIT3 -#define SCR_SKByA2 BIT4 #define SCR_NoSKMC BIT5 SWREGULATOR = 0x0BD, INTA_MASK = 0x0f4, -#define IMR8190_DISABLED 0x0 -#define IMR_ATIMEND BIT28 #define IMR_TBDOK BIT27 #define IMR_TBDER BIT26 #define IMR_TXFOVW BIT15 @@ -227,30 +128,10 @@ enum _RTL8192Pci_HW { #define IMR_VODOK BIT1 #define IMR_ROK BIT0 ISR = 0x0f8, - TPPoll = 0x0fd, -#define TPPoll_BKQ BIT0 -#define TPPoll_BEQ BIT1 -#define TPPoll_VIQ BIT2 -#define TPPoll_VOQ BIT3 -#define TPPoll_BQ BIT4 -#define TPPoll_CQ BIT5 -#define TPPoll_MQ BIT6 -#define TPPoll_HQ BIT7 -#define TPPoll_HCCAQ BIT8 -#define TPPoll_StopBK BIT9 -#define TPPoll_StopBE BIT10 -#define TPPoll_StopVI BIT11 -#define TPPoll_StopVO BIT12 -#define TPPoll_StopMgt BIT13 -#define TPPoll_StopHigh BIT14 -#define TPPoll_StopHCCA BIT15 -#define TPPoll_SHIFT 8 - + TP_POLL = 0x0fd, +#define TP_POLL_CQ BIT5 PSR = 0x0ff, -#define PSR_GEN 0x0 -#define PSR_CPU 0x1 CPU_GEN = 0x100, - BB_RESET = 0x101, #define CPU_CCK_LOOPBACK 0x00030000 #define CPU_GEN_SYSTEM_RESET 0x00000001 #define CPU_GEN_FIRMWARE_RESET 0x00000008 @@ -261,31 +142,13 @@ enum _RTL8192Pci_HW { #define CPU_GEN_PWR_STB_CPU 0x00000004 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 -#define CPU_GEN_GPIO_UART 0x00007000 - - LED1Cfg = 0x154, - LED0Cfg = 0x155, - - AcmAvg = 0x170, - AcmHwCtrl = 0x171, -#define AcmHw_HwEn BIT0 -#define AcmHw_BeqEn BIT1 -#define AcmHw_ViqEn BIT2 -#define AcmHw_VoqEn BIT3 -#define AcmHw_BeqStatus BIT4 -#define AcmHw_ViqStatus BIT5 -#define AcmHw_VoqStatus BIT6 - AcmFwCtrl = 0x172, -#define AcmFw_BeqStatus BIT0 -#define AcmFw_ViqStatus BIT1 -#define AcmFw_VoqStatus BIT2 - VOAdmTime = 0x174, - VIAdmTime = 0x178, - BEAdmTime = 0x17C, + ACM_HW_CTRL = 0x171, +#define ACM_HW_BEQ_EN BIT1 +#define ACM_HW_VIQ_EN BIT2 +#define ACM_HW_VOQ_EN BIT3 RQPN1 = 0x180, RQPN2 = 0x184, RQPN3 = 0x188, - QPRR = 0x1E0, QPNR = 0x1F0, BQDA = 0x200, HQDA = 0x204, @@ -296,51 +159,21 @@ enum _RTL8192Pci_HW { VIQDA = 0x218, BEQDA = 0x21C, BKQDA = 0x220, - RCQDA = 0x224, RDQDA = 0x228, - MAR0 = 0x240, - MAR4 = 0x244, - - CCX_PERIOD = 0x250, - CLM_RESULT = 0x251, - NHM_PERIOD = 0x252, - - NHM_THRESHOLD0 = 0x253, - NHM_THRESHOLD1 = 0x254, - NHM_THRESHOLD2 = 0x255, - NHM_THRESHOLD3 = 0x256, - NHM_THRESHOLD4 = 0x257, - NHM_THRESHOLD5 = 0x258, - NHM_THRESHOLD6 = 0x259, - - MCTRL = 0x25A, - - NHM_RPI_COUNTER0 = 0x264, - NHM_RPI_COUNTER1 = 0x265, - NHM_RPI_COUNTER2 = 0x266, - NHM_RPI_COUNTER3 = 0x267, - NHM_RPI_COUNTER4 = 0x268, - NHM_RPI_COUNTER5 = 0x269, - NHM_RPI_COUNTER6 = 0x26A, - NHM_RPI_COUNTER7 = 0x26B, WFCRC0 = 0x2f0, WFCRC1 = 0x2f4, WFCRC2 = 0x2f8, BW_OPMODE = 0x300, -#define BW_OPMODE_11J BIT0 #define BW_OPMODE_5G BIT1 #define BW_OPMODE_20MHZ BIT2 IC_VERRSION = 0x301, MSR = 0x303, -#define MSR_LINK_MASK ((1<<0)|(1<<1)) +#define MSR_LINK_MASK (BIT(1) | BIT(0)) #define MSR_LINK_MANAGED 2 -#define MSR_LINK_NONE 0 -#define MSR_LINK_SHIFT 0 #define MSR_LINK_ADHOC 1 #define MSR_LINK_MASTER 3 -#define MSR_LINK_ENEDCA (1<<4) #define MSR_NOLINK 0x00 #define MSR_ADHOC 0x01 @@ -352,12 +185,7 @@ enum _RTL8192Pci_HW { #define RETRY_LIMIT_LONG_SHIFT 0 TSFR = 0x308, RRSR = 0x310, -#define RRSR_RSC_OFFSET 21 #define RRSR_SHORT_OFFSET 23 -#define RRSR_RSC_DUPLICATE 0x600000 -#define RRSR_RSC_UPSUBCHNL 0x400000 -#define RRSR_RSC_LOWSUBCHNL 0x200000 -#define RRSR_SHORT 0x800000 #define RRSR_1M BIT0 #define RRSR_2M BIT1 #define RRSR_5_5M BIT2 @@ -370,14 +198,6 @@ enum _RTL8192Pci_HW { #define RRSR_36M BIT9 #define RRSR_48M BIT10 #define RRSR_54M BIT11 -#define RRSR_MCS0 BIT12 -#define RRSR_MCS1 BIT13 -#define RRSR_MCS2 BIT14 -#define RRSR_MCS3 BIT15 -#define RRSR_MCS4 BIT16 -#define RRSR_MCS5 BIT17 -#define RRSR_MCS6 BIT18 -#define RRSR_MCS7 BIT19 #define BRSR_AckShortPmb BIT23 UFWP = 0x318, RATR0 = 0x320, @@ -419,21 +239,14 @@ enum _RTL8192Pci_HW { RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ RATR_MCS14|RATR_MCS15) - DRIVER_RSSI = 0x32c, MCS_TXAGC = 0x340, CCK_TXAGC = 0x348, - MacBlkCtrl = 0x403, - -} -; + MAC_BLK_CTRL = 0x403, +}; #define GPI 0x108 -#define GPO 0x109 -#define GPE 0x10a -#define HWSET_MAX_SIZE_92S 128 - -#define ANAPAR_FOR_8192PciE 0x17 +#define ANAPAR_FOR_8192PCIE 0x17 #endif diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c index a813eded4cb3..c6cbdea6d5b2 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phy.c @@ -94,24 +94,24 @@ static u32 _rtl92e_phy_rf_read(struct net_device *dev, struct r8192_priv *priv = rtllib_priv(dev); u32 ret = 0; u32 NewOffset = 0; - struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; + struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath]; Offset &= 0x3f; if (priv->rf_chip == RF_8256) { rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); if (Offset >= 31) { - priv->RfReg0Value[eRFPath] |= 0x140; + priv->rf_reg_0value[eRFPath] |= 0x140; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath]<<16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset = Offset - 30; } else if (Offset >= 16) { - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); + priv->rf_reg_0value[eRFPath] |= 0x100; + priv->rf_reg_0value[eRFPath] &= (~0x40); rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath]<<16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset = Offset - 15; } else @@ -130,10 +130,10 @@ static u32 _rtl92e_phy_rf_read(struct net_device *dev, bLSSIReadBackData); if (priv->rf_chip == RF_8256) { - priv->RfReg0Value[eRFPath] &= 0xebf; + priv->rf_reg_0value[eRFPath] &= 0xebf; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } @@ -149,24 +149,24 @@ static void _rtl92e_phy_rf_write(struct net_device *dev, { struct r8192_priv *priv = rtllib_priv(dev); u32 DataAndAddr = 0, NewOffset = 0; - struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; + struct bb_reg_definition *pPhyReg = &priv->phy_reg_def[eRFPath]; Offset &= 0x3f; if (priv->rf_chip == RF_8256) { rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); if (Offset >= 31) { - priv->RfReg0Value[eRFPath] |= 0x140; + priv->rf_reg_0value[eRFPath] |= 0x140; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset = Offset - 30; } else if (Offset >= 16) { - priv->RfReg0Value[eRFPath] |= 0x100; - priv->RfReg0Value[eRFPath] &= (~0x40); + priv->rf_reg_0value[eRFPath] |= 0x100; + priv->rf_reg_0value[eRFPath] &= (~0x40); rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); NewOffset = Offset - 15; } else NewOffset = Offset; @@ -179,14 +179,14 @@ static void _rtl92e_phy_rf_write(struct net_device *dev, rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); if (Offset == 0x0) - priv->RfReg0Value[eRFPath] = Data; + priv->rf_reg_0value[eRFPath] = Data; if (priv->rf_chip == RF_8256) { if (Offset != 0) { - priv->RfReg0Value[eRFPath] &= 0xebf; + priv->rf_reg_0value[eRFPath] &= 0xebf; rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, - (priv->RfReg0Value[eRFPath] << 16)); + (priv->rf_reg_0value[eRFPath] << 16)); } rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); } @@ -203,7 +203,7 @@ void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) return; - if (priv->Rf_Mode == RF_OP_By_FW) { + if (priv->rf_mode == RF_OP_By_FW) { if (BitMask != bMask12Bits) { Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); @@ -240,7 +240,7 @@ u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath, if (priv->rtllib->rf_power_state != rf_on && !priv->being_init_adapter) return 0; mutex_lock(&priv->rf_mutex); - if (priv->Rf_Mode == RF_OP_By_FW) { + if (priv->rf_mode == RF_OP_By_FW) { Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr); udelay(200); } else { @@ -306,7 +306,7 @@ void rtl92e_config_mac(struct net_device *dev) u32 *pdwArray = NULL; struct r8192_priv *priv = rtllib_priv(dev); - if (priv->bTXPowerDataReadFromEEPORM) { + if (priv->tx_pwr_data_read_from_eeprom) { dwArrayLen = MACPHY_Array_PGLength; pdwArray = Rtl819XMACPHY_Array_PG; @@ -342,13 +342,13 @@ static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType) Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray; } - if (ConfigType == BaseBand_Config_PHY_REG) { + if (ConfigType == BB_CONFIG_PHY_REG) { for (i = 0; i < PHY_REGArrayLen; i += 2) { rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); } - } else if (ConfigType == BaseBand_Config_AGC_TAB) { + } else if (ConfigType == BB_CONFIG_AGC_TAB) { for (i = 0; i < AGCTAB_ArrayLen; i += 2) { rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, @@ -361,90 +361,90 @@ static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; - priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; - priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; - priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; + priv->phy_reg_def[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + priv->phy_reg_def[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + priv->phy_reg_def[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; + priv->phy_reg_def[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; - priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; - priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; - priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; - priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; + priv->phy_reg_def[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; + priv->phy_reg_def[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; + priv->phy_reg_def[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; + priv->phy_reg_def[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; - priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; + priv->phy_reg_def[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; - priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; - priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; - priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; - priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; + priv->phy_reg_def[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; + priv->phy_reg_def[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; + priv->phy_reg_def[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; + priv->phy_reg_def[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; - priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; - priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; + priv->phy_reg_def[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->phy_reg_def[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; + priv->phy_reg_def[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; + priv->phy_reg_def[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; - priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; - priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; - priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; - priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; + priv->phy_reg_def[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; + priv->phy_reg_def[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; + priv->phy_reg_def[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; + priv->phy_reg_def[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; - priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; - priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; - priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; - priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; + priv->phy_reg_def[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; + priv->phy_reg_def[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; + priv->phy_reg_def[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; + priv->phy_reg_def[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; - priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; - priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; - priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; - priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; + priv->phy_reg_def[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; + priv->phy_reg_def[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; + priv->phy_reg_def[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; + priv->phy_reg_def[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; - priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; - priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; - priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; + priv->phy_reg_def[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->phy_reg_def[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; + priv->phy_reg_def[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; + priv->phy_reg_def[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; - priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; - priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; + priv->phy_reg_def[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; + priv->phy_reg_def[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; + priv->phy_reg_def[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; + priv->phy_reg_def[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; - priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; - priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; + priv->phy_reg_def[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; + priv->phy_reg_def[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; + priv->phy_reg_def[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; + priv->phy_reg_def[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; - priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; - priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; + priv->phy_reg_def[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; + priv->phy_reg_def[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; + priv->phy_reg_def[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; + priv->phy_reg_def[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; - priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; - priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; + priv->phy_reg_def[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; + priv->phy_reg_def[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; + priv->phy_reg_def[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; + priv->phy_reg_def[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; - priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; - priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; + priv->phy_reg_def[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; + priv->phy_reg_def[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; + priv->phy_reg_def[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; + priv->phy_reg_def[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; - priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; - priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; + priv->phy_reg_def[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; + priv->phy_reg_def[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; + priv->phy_reg_def[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; + priv->phy_reg_def[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; - priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; - priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; + priv->phy_reg_def[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + priv->phy_reg_def[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + priv->phy_reg_def[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; + priv->phy_reg_def[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; } @@ -526,25 +526,25 @@ static bool _rtl92e_bb_config_para_file(struct net_device *dev) return rtStatus; } rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); - _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG); + _rtl92e_phy_config_bb(dev, BB_CONFIG_PHY_REG); dwRegValue = rtl92e_readl(dev, CPU_GEN); rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); - _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB); + _rtl92e_phy_config_bb(dev, BB_CONFIG_AGC_TAB); - if (priv->IC_Cut > VERSION_8190_BD) { + if (priv->ic_cut > VERSION_8190_BD) { if (priv->rf_type == RF_2T4R) - dwRegValue = priv->AntennaTxPwDiff[2]<<8 | - priv->AntennaTxPwDiff[1]<<4 | - priv->AntennaTxPwDiff[0]; + dwRegValue = priv->antenna_tx_pwr_diff[2] << 8 | + priv->antenna_tx_pwr_diff[1] << 4 | + priv->antenna_tx_pwr_diff[0]; else dwRegValue = 0x0; rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); - dwRegValue = priv->CrystalCap; + dwRegValue = priv->crystal_cap; rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); } @@ -561,65 +561,43 @@ void rtl92e_get_tx_power(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - priv->MCSTxPowerLevelOriginalOffset[0] = + priv->mcs_tx_pwr_level_org_offset[0] = rtl92e_readl(dev, rTxAGC_Rate18_06); - priv->MCSTxPowerLevelOriginalOffset[1] = + priv->mcs_tx_pwr_level_org_offset[1] = rtl92e_readl(dev, rTxAGC_Rate54_24); - priv->MCSTxPowerLevelOriginalOffset[2] = + priv->mcs_tx_pwr_level_org_offset[2] = rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00); - priv->MCSTxPowerLevelOriginalOffset[3] = + priv->mcs_tx_pwr_level_org_offset[3] = rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04); - priv->MCSTxPowerLevelOriginalOffset[4] = + priv->mcs_tx_pwr_level_org_offset[4] = rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08); - priv->MCSTxPowerLevelOriginalOffset[5] = + priv->mcs_tx_pwr_level_org_offset[5] = rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12); - priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); - priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); - priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); - priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); + priv->def_initial_gain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1); + priv->def_initial_gain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1); + priv->def_initial_gain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1); + priv->def_initial_gain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1); priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3); - priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2); - priv->SifsTime = rtl92e_readw(dev, SIFS); } void rtl92e_set_tx_power(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); u8 powerlevel = 0, powerlevelOFDM24G = 0; - s8 ant_pwr_diff; - u32 u4RegValue; if (priv->epromtype == EEPROM_93C46) { - powerlevel = priv->TxPowerLevelCCK[channel-1]; - powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; + powerlevel = priv->tx_pwr_level_cck[channel - 1]; + powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1]; } else if (priv->epromtype == EEPROM_93C56) { - if (priv->rf_type == RF_1T2R) { - powerlevel = priv->TxPowerLevelCCK_C[channel-1]; - powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; - } else if (priv->rf_type == RF_2T4R) { - powerlevel = priv->TxPowerLevelCCK_A[channel-1]; - powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; - - ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] - - priv->TxPowerLevelOFDM24G_A[channel-1]; - - priv->RF_C_TxPwDiff = ant_pwr_diff; - - ant_pwr_diff &= 0xf; - - priv->AntennaTxPwDiff[2] = 0; - priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); - priv->AntennaTxPwDiff[0] = 0; - - u4RegValue = priv->AntennaTxPwDiff[2]<<8 | - priv->AntennaTxPwDiff[1]<<4 | - priv->AntennaTxPwDiff[0]; + if (priv->rf_type == RF_2T4R) { + priv->antenna_tx_pwr_diff[2] = 0; + priv->antenna_tx_pwr_diff[1] = 0; + priv->antenna_tx_pwr_diff[0] = 0; rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, - (bXBTxAGC|bXCTxAGC|bXDTxAGC), - u4RegValue); + (bXBTxAGC | bXCTxAGC | bXDTxAGC), 0); } } switch (priv->rf_chip) { @@ -726,8 +704,8 @@ u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath) static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel) { struct r8192_priv *priv = rtllib_priv(dev); - u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; - u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; + u8 powerlevel = priv->tx_pwr_level_cck[channel - 1]; + u8 powerlevelOFDM24G = priv->tx_pwr_level_ofdm_24g[channel - 1]; switch (priv->rf_chip) { case RF_8225: @@ -886,7 +864,7 @@ static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, continue; switch (CurrentCmd->CmdID) { case CmdID_SetTxPowerLevel: - if (priv->IC_Cut > VERSION_8190_BD) + if (priv->ic_cut > VERSION_8190_BD) _rtl92e_set_tx_power_level(dev, channel); break; @@ -904,7 +882,7 @@ static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, break; case CmdID_RF_WriteReg: for (eRFPath = 0; eRFPath < - priv->NumTotalRFPath; eRFPath++) + priv->num_total_rf_path; eRFPath++) rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, @@ -929,8 +907,8 @@ static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel) u32 delay = 0; while (!_rtl92e_phy_switch_channel_step(dev, channel, - &priv->SwChnlStage, - &priv->SwChnlStep, &delay)) { + &priv->sw_chnl_stage, + &priv->sw_chnl_step, &delay)) { if (delay > 0) msleep(delay); if (!priv->up) @@ -954,7 +932,7 @@ u8 rtl92e_set_channel(struct net_device *dev, u8 channel) netdev_err(dev, "%s(): Driver is not initialized\n", __func__); return false; } - if (priv->SwChnlInProgress) + if (priv->sw_chnl_in_progress) return false; @@ -987,18 +965,18 @@ u8 rtl92e_set_channel(struct net_device *dev, u8 channel) break; } - priv->SwChnlInProgress = true; + priv->sw_chnl_in_progress = true; if (channel == 0) channel = 1; priv->chan = channel; - priv->SwChnlStage = 0; - priv->SwChnlStep = 0; + priv->sw_chnl_stage = 0; + priv->sw_chnl_step = 0; if (priv->up) _rtl92e_phy_switch_channel_work_item(dev); - priv->SwChnlInProgress = false; + priv->sw_chnl_in_progress = false; return true; } @@ -1006,16 +984,16 @@ static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - switch (priv->CurrentChannelBW) { + switch (priv->current_chnl_bw) { case HT_CHANNEL_WIDTH_20: priv->cck_present_attn = - priv->CCKPresentAttentuation_20Mdefault + - priv->CCKPresentAttentuation_difference; + priv->cck_present_attn_20m_def + + priv->cck_present_attn_diff; if (priv->cck_present_attn > - (CCKTxBBGainTableLength-1)) + (CCK_TX_BB_GAIN_TABLE_LEN - 1)) priv->cck_present_attn = - CCKTxBBGainTableLength-1; + CCK_TX_BB_GAIN_TABLE_LEN - 1; if (priv->cck_present_attn < 0) priv->cck_present_attn = 0; @@ -1034,13 +1012,13 @@ static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev) case HT_CHANNEL_WIDTH_20_40: priv->cck_present_attn = - priv->CCKPresentAttentuation_40Mdefault + - priv->CCKPresentAttentuation_difference; + priv->cck_present_attn_40m_def + + priv->cck_present_attn_diff; if (priv->cck_present_attn > - (CCKTxBBGainTableLength - 1)) + (CCK_TX_BB_GAIN_TABLE_LEN - 1)) priv->cck_present_attn = - CCKTxBBGainTableLength-1; + CCK_TX_BB_GAIN_TABLE_LEN - 1; if (priv->cck_present_attn < 0) priv->cck_present_attn = 0; @@ -1070,15 +1048,15 @@ static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev) priv->bcck_in_ch14) priv->bcck_in_ch14 = false; - switch (priv->CurrentChannelBW) { + switch (priv->current_chnl_bw) { case HT_CHANNEL_WIDTH_20: - if (priv->Record_CCK_20Mindex == 0) - priv->Record_CCK_20Mindex = 6; - priv->CCK_index = priv->Record_CCK_20Mindex; + if (priv->rec_cck_20m_idx == 0) + priv->rec_cck_20m_idx = 6; + priv->cck_index = priv->rec_cck_20m_idx; break; case HT_CHANNEL_WIDTH_20_40: - priv->CCK_index = priv->Record_CCK_40Mindex; + priv->cck_index = priv->rec_cck_40m_idx; break; } rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); @@ -1088,7 +1066,7 @@ static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - if (priv->IC_Cut >= IC_VersionCut_D) + if (priv->ic_cut >= IC_VersionCut_D) _rtl92e_cck_tx_power_track_bw_switch_tssi(dev); else _rtl92e_cck_tx_power_track_bw_switch_thermal(dev); @@ -1101,7 +1079,7 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) u8 regBwOpMode; if (priv->rf_chip == RF_PSEUDO_11N) { - priv->SetBWModeInProgress = false; + priv->set_bw_mode_in_progress = false; return; } if (!priv->up) { @@ -1110,7 +1088,7 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) } regBwOpMode = rtl92e_readb(dev, BW_OPMODE); - switch (priv->CurrentChannelBW) { + switch (priv->current_chnl_bw) { case HT_CHANNEL_WIDTH_20: regBwOpMode |= BW_OPMODE_20MHZ; rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); @@ -1123,11 +1101,11 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) default: netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, - priv->CurrentChannelBW); + priv->current_chnl_bw); break; } - switch (priv->CurrentChannelBW) { + switch (priv->current_chnl_bw) { case HT_CHANNEL_WIDTH_20: rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); @@ -1156,15 +1134,15 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) } rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, - (priv->nCur40MhzPrimeSC>>1)); + (priv->n_cur_40mhz_prime_sc>>1)); rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, - priv->nCur40MhzPrimeSC); + priv->n_cur_40mhz_prime_sc); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); break; default: netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, - priv->CurrentChannelBW); + priv->current_chnl_bw); break; } @@ -1174,7 +1152,7 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) break; case RF_8256: - rtl92e_set_bandwidth(dev, priv->CurrentChannelBW); + rtl92e_set_bandwidth(dev, priv->current_chnl_bw); break; case RF_8258: @@ -1190,7 +1168,7 @@ static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) } atomic_dec(&(priv->rtllib->atm_swbw)); - priv->SetBWModeInProgress = false; + priv->set_bw_mode_in_progress = false; } void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width bandwidth, @@ -1199,20 +1177,20 @@ void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width bandwidth, struct r8192_priv *priv = rtllib_priv(dev); - if (priv->SetBWModeInProgress) + if (priv->set_bw_mode_in_progress) return; atomic_inc(&(priv->rtllib->atm_swbw)); - priv->SetBWModeInProgress = true; + priv->set_bw_mode_in_progress = true; - priv->CurrentChannelBW = bandwidth; + priv->current_chnl_bw = bandwidth; if (Offset == HT_EXTCHNL_OFFSET_LOWER) - priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; + priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_UPPER; else if (Offset == HT_EXTCHNL_OFFSET_UPPER) - priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; + priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_LOWER; else - priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + priv->n_cur_40mhz_prime_sc = HAL_PRIME_CHNL_OFFSET_DONT_CARE; _rtl92e_set_bw_mode_work_item(dev); @@ -1295,7 +1273,7 @@ void rtl92e_set_rf_off(struct net_device *dev) rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); - rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07); + rtl92e_writeb(dev, ANAPAR_FOR_8192PCIE, 0x07); } @@ -1309,9 +1287,9 @@ static bool _rtl92e_set_rf_power_state(struct net_device *dev, u8 i = 0, QueueID = 0; struct rtl8192_tx_ring *ring = NULL; - if (priv->SetRFPowerStateInProgress) + if (priv->set_rf_pwr_state_in_progress) return false; - priv->SetRFPowerStateInProgress = true; + priv->set_rf_pwr_state_in_progress = true; switch (priv->rf_chip) { case RF_8256: @@ -1331,7 +1309,7 @@ static bool _rtl92e_set_rf_power_state(struct net_device *dev, netdev_err(dev, "%s(): Failed to initialize Adapter.\n", __func__); - priv->SetRFPowerStateInProgress = false; + priv->set_rf_pwr_state_in_progress = false; return false; } @@ -1438,7 +1416,7 @@ static bool _rtl92e_set_rf_power_state(struct net_device *dev, } } - priv->SetRFPowerStateInProgress = false; + priv->set_rf_pwr_state_in_progress = false; return bResult; } diff --git a/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h b/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h index 433272a2aae8..f846f109ed98 100644 --- a/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h +++ b/drivers/staging/rtl8192e/rtl8192e/r8192E_phyreg.h @@ -42,8 +42,6 @@ #define CCK_TXAGC 0x348 /* Mac block on/off control register */ -#define MacBlkCtrl 0x403 - #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ #define rFPGA0_TxInfo 0x804 #define rFPGA0_PSDFunction 0x808 diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index f8fbe78ccad9..104b16cfa979 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -692,16 +692,13 @@ static int _rtl92e_sta_up(struct net_device *dev, bool is_silent_reset) priv->rtllib->ieee_up = 1; priv->up_first_time = 0; - priv->bfirst_init = true; init_status = priv->ops->initialize_adapter(dev); if (!init_status) { netdev_err(dev, "%s(): Initialization failed!\n", __func__); - priv->bfirst_init = false; return -1; } RT_CLEAR_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC); - priv->bfirst_init = false; if (priv->polling_timer_on == 0) rtl92e_check_rfctrl_gpio_timer(&priv->gpio_polling_timer); @@ -837,7 +834,6 @@ static void _rtl92e_init_priv_variable(struct net_device *dev) priv->blinked_ingpio = false; priv->being_init_adapter = false; priv->bdisable_nic = false; - priv->bfirst_init = false; priv->txringcount = 64; priv->rxbuffersize = 9100; priv->rxringcount = MAX_RX_COUNT; @@ -862,7 +858,7 @@ static void _rtl92e_init_priv_variable(struct net_device *dev) priv->cck_present_attn = 0; priv->rfa_txpowertrackingindex = 0; priv->rfc_txpowertrackingindex = 0; - priv->CckPwEnl = 6; + priv->cck_pwr_enl = 6; priv->rst_progress = RESET_TYPE_NORESET; priv->force_reset = false; memset(priv->rtllib->swcamtable, 0, sizeof(struct sw_cam_table) * 32); @@ -872,7 +868,7 @@ static void _rtl92e_init_priv_variable(struct net_device *dev) priv->rtllib->rf_off_reason = 0; priv->rf_change_in_progress = false; priv->hw_rf_off_action = 0; - priv->SetRFPowerStateInProgress = false; + priv->set_rf_pwr_state_in_progress = false; priv->rtllib->pwr_save_ctrl.bLeisurePs = true; priv->rtllib->LPSDelayCnt = 0; priv->rtllib->sta_sleep = LPS_IS_WAKE; @@ -891,8 +887,8 @@ static void _rtl92e_init_priv_variable(struct net_device *dev) priv->card_type = PCI; - priv->pFirmware = vzalloc(sizeof(struct rt_firmware)); - if (!priv->pFirmware) + priv->fw_info = vzalloc(sizeof(struct rt_firmware)); + if (!priv->fw_info) netdev_err(dev, "rtl8192e: Unable to allocate space for firmware\n"); @@ -952,13 +948,13 @@ static short _rtl92e_get_channel_map(struct net_device *dev) return -1; } - if (priv->ChannelPlan >= COUNTRY_CODE_MAX) { + if (priv->chnl_plan >= COUNTRY_CODE_MAX) { netdev_info(dev, "rtl819x_init:Error channel plan! Set to default.\n"); - priv->ChannelPlan = COUNTRY_CODE_FCC; + priv->chnl_plan = COUNTRY_CODE_FCC; } dot11d_init(priv->rtllib); - dot11d_channel_map(priv->ChannelPlan, priv->rtllib); + dot11d_channel_map(priv->chnl_plan, priv->rtllib); for (i = 1; i <= 11; i++) (priv->rtllib->active_channel_map)[i] = 1; (priv->rtllib->active_channel_map)[12] = 2; @@ -1138,7 +1134,7 @@ static void _rtl92e_if_silent_reset(struct net_device *dev) goto END; } priv->rf_change_in_progress = true; - priv->bResetInProgress = true; + priv->reset_in_progress = true; spin_unlock_irqrestore(&priv->rf_ps_lock, flag); RESET_START: @@ -1229,7 +1225,7 @@ RESET_START: END: priv->rst_progress = RESET_TYPE_NORESET; priv->reset_count++; - priv->bResetInProgress = false; + priv->reset_in_progress = false; rtl92e_writeb(dev, UFWP, 1); } @@ -1397,7 +1393,7 @@ static void _rtl92e_watchdog_wq_cb(void *data) if ((priv->force_reset || ResetType == RESET_TYPE_SILENT)) _rtl92e_if_silent_reset(dev); priv->force_reset = false; - priv->bResetInProgress = false; + priv->reset_in_progress = false; } static void _rtl92e_watchdog_timer_cb(struct timer_list *t) @@ -1486,7 +1482,7 @@ static void _rtl92e_hard_data_xmit(struct sk_buff *skb, struct net_device *dev, u8 queue_index = tcb_desc->queue_index; if ((priv->rtllib->rf_power_state == rf_off) || !priv->up || - priv->bResetInProgress) { + priv->reset_in_progress) { kfree_skb(skb); return; } @@ -1519,7 +1515,7 @@ static int _rtl92e_hard_start_xmit(struct sk_buff *skb, struct net_device *dev) if (queue_index != TXCMD_QUEUE) { if ((priv->rtllib->rf_power_state == rf_off) || - !priv->up || priv->bResetInProgress) { + !priv->up || priv->reset_in_progress) { kfree_skb(skb); return 0; } @@ -1620,11 +1616,7 @@ static short _rtl92e_tx(struct net_device *dev, struct sk_buff *skb) type = WLAN_FC_GET_TYPE(fc); pda_addr = header->addr1; - if (is_broadcast_ether_addr(pda_addr)) - priv->stats.txbytesbroadcast += skb->len - fwinfo_size; - else if (is_multicast_ether_addr(pda_addr)) - priv->stats.txbytesmulticast += skb->len - fwinfo_size; - else + if (!is_broadcast_ether_addr(pda_addr) && !is_multicast_ether_addr(pda_addr)) priv->stats.txbytesunicast += skb->len - fwinfo_size; spin_lock_irqsave(&priv->irq_th_lock, flags); @@ -1654,7 +1646,7 @@ static short _rtl92e_tx(struct net_device *dev, struct sk_buff *skb) spin_unlock_irqrestore(&priv->irq_th_lock, flags); netif_trans_update(dev); - rtl92e_writew(dev, TPPoll, 0x01 << tcb_desc->queue_index); + rtl92e_writew(dev, TP_POLL, 0x01 << tcb_desc->queue_index); return 0; } @@ -1807,9 +1799,9 @@ void rtl92e_update_rx_pkt_timestamp(struct net_device *dev, struct r8192_priv *priv = rtllib_priv(dev); if (stats->bIsAMPDU && !stats->bFirstMPDU) - stats->mac_time = priv->LastRxDescTSF; + stats->mac_time = priv->last_rx_desc_tsf; else - priv->LastRxDescTSF = stats->mac_time; + priv->last_rx_desc_tsf = stats->mac_time; } long rtl92e_translate_to_dbm(struct r8192_priv *priv, u8 signal_strength_index) @@ -1914,7 +1906,7 @@ static void _rtl92e_rx_normal(struct net_device *dev) skb_put(skb, pdesc->Length); skb_reserve(skb, stats.RxDrvInfoSize + stats.RxBufShift); - skb_trim(skb, skb->len - 4/*sCrcLng*/); + skb_trim(skb, skb->len - S_CRC_LEN); rtllib_hdr = (struct rtllib_hdr_1addr *)skb->data; if (!is_multicast_ether_addr(rtllib_hdr->addr1)) { /* unicast packet */ @@ -1930,19 +1922,11 @@ static void _rtl92e_rx_normal(struct net_device *dev) priv->rtllib->LedControlHandler(dev, LED_CTL_RX); - if (stats.bCRC) { - if (type != RTLLIB_FTYPE_MGMT) - priv->stats.rxdatacrcerr++; - else - priv->stats.rxmgmtcrcerr++; - } - skb_len = skb->len; if (!rtllib_rx(priv->rtllib, skb, &stats)) { dev_kfree_skb_any(skb); } else { - priv->stats.rxok++; if (unicast_packet) priv->stats.rxbytesunicast += skb_len; } @@ -2135,7 +2119,6 @@ static irqreturn_t _rtl92e_irq(int irq, void *netdev) spin_lock_irqsave(&priv->irq_th_lock, flags); priv->ops->interrupt_recognized(dev, &inta, &intb); - priv->stats.shints++; if (!inta) { spin_unlock_irqrestore(&priv->irq_th_lock, flags); @@ -2147,21 +2130,12 @@ static irqreturn_t _rtl92e_irq(int irq, void *netdev) goto done; } - priv->stats.ints++; - if (!netif_running(dev)) { spin_unlock_irqrestore(&priv->irq_th_lock, flags); goto done; } - if (inta & IMR_TBDOK) - priv->stats.txbeaconokint++; - - if (inta & IMR_TBDER) - priv->stats.txbeaconerr++; - if (inta & IMR_MGNTDOK) { - priv->stats.txmanageokint++; _rtl92e_tx_isr(dev, MGNT_QUEUE); spin_unlock_irqrestore(&priv->irq_th_lock, flags); if (priv->rtllib->ack_tx_to_ieee) { @@ -2173,57 +2147,43 @@ static irqreturn_t _rtl92e_irq(int irq, void *netdev) spin_lock_irqsave(&priv->irq_th_lock, flags); } - if (inta & IMR_COMDOK) { - priv->stats.txcmdpktokint++; + if (inta & IMR_COMDOK) _rtl92e_tx_isr(dev, TXCMD_QUEUE); - } if (inta & IMR_HIGHDOK) _rtl92e_tx_isr(dev, HIGH_QUEUE); - if (inta & IMR_ROK) { - priv->stats.rxint++; + if (inta & IMR_ROK) tasklet_schedule(&priv->irq_rx_tasklet); - } if (inta & IMR_BcnInt) tasklet_schedule(&priv->irq_prepare_beacon_tasklet); if (inta & IMR_RDU) { - priv->stats.rxrdu++; rtl92e_writel(dev, INTA_MASK, rtl92e_readl(dev, INTA_MASK) & ~IMR_RDU); tasklet_schedule(&priv->irq_rx_tasklet); } - if (inta & IMR_RXFOVW) { - priv->stats.rxoverflow++; + if (inta & IMR_RXFOVW) tasklet_schedule(&priv->irq_rx_tasklet); - } - - if (inta & IMR_TXFOVW) - priv->stats.txoverflow++; if (inta & IMR_BKDOK) { - priv->stats.txbkokint++; priv->rtllib->link_detect_info.NumTxOkInPeriod++; _rtl92e_tx_isr(dev, BK_QUEUE); } if (inta & IMR_BEDOK) { - priv->stats.txbeokint++; priv->rtllib->link_detect_info.NumTxOkInPeriod++; _rtl92e_tx_isr(dev, BE_QUEUE); } if (inta & IMR_VIDOK) { - priv->stats.txviokint++; priv->rtllib->link_detect_info.NumTxOkInPeriod++; _rtl92e_tx_isr(dev, VI_QUEUE); } if (inta & IMR_VODOK) { - priv->stats.txvookint++; priv->rtllib->link_detect_info.NumTxOkInPeriod++; _rtl92e_tx_isr(dev, VO_QUEUE); } @@ -2386,8 +2346,8 @@ static void _rtl92e_pci_disconnect(struct pci_dev *pdev) priv->polling_timer_on = 0; _rtl92e_down(dev, true); rtl92e_dm_deinit(dev); - vfree(priv->pFirmware); - priv->pFirmware = NULL; + vfree(priv->fw_info); + priv->fw_info = NULL; _rtl92e_free_rx_ring(dev); for (i = 0; i < MAX_TX_QUEUE_COUNT; i++) _rtl92e_free_tx_ring(dev, i); @@ -2423,7 +2383,6 @@ bool rtl92e_enable_nic(struct net_device *dev) return false; } - priv->bfirst_init = true; init_status = priv->ops->initialize_adapter(dev); if (!init_status) { netdev_warn(dev, "%s(): Initialization failed!\n", __func__); @@ -2431,7 +2390,6 @@ bool rtl92e_enable_nic(struct net_device *dev) return false; } RT_CLEAR_PS_LEVEL(psc, RT_RF_OFF_LEVL_HALT_NIC); - priv->bfirst_init = false; rtl92e_irq_enable(dev); priv->bdisable_nic = false; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h index cceb77492363..fd96eef90c7f 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -90,11 +90,11 @@ #define PHY_RSSI_SLID_WIN_MAX 100 -#define TxBBGainTableLength 37 -#define CCKTxBBGainTableLength 23 +#define TX_BB_GAIN_TABLE_LEN 37 +#define CCK_TX_BB_GAIN_TABLE_LEN 23 #define CHANNEL_PLAN_LEN 10 -#define sCrcLng 4 +#define S_CRC_LEN 4 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8 @@ -145,35 +145,13 @@ enum rt_rf_type_819xu { enum rt_customer_id { RT_CID_DEFAULT = 0, - RT_CID_8187_ALPHA0 = 1, - RT_CID_8187_SERCOMM_PS = 2, - RT_CID_8187_HW_LED = 3, - RT_CID_8187_NETGEAR = 4, - RT_CID_WHQL = 5, RT_CID_819x_CAMEO = 6, RT_CID_819x_RUNTOP = 7, - RT_CID_819x_Senao = 8, RT_CID_TOSHIBA = 9, - RT_CID_819x_Netcore = 10, + RT_CID_819X_NETCORE = 10, RT_CID_Nettronix = 11, RT_CID_DLINK = 12, RT_CID_PRONET = 13, - RT_CID_COREGA = 14, - RT_CID_819x_ALPHA = 15, - RT_CID_819x_Sitecom = 16, - RT_CID_CCX = 17, - RT_CID_819x_Lenovo = 18, - RT_CID_819x_QMI = 19, - RT_CID_819x_Edimax_Belkin = 20, - RT_CID_819x_Sercomm_Belkin = 21, - RT_CID_819x_CAMEO1 = 22, - RT_CID_819x_MSI = 23, - RT_CID_819x_Acer = 24, - RT_CID_819x_HP = 27, - RT_CID_819x_CLEVO = 28, - RT_CID_819x_Arcadyan_Belkin = 29, - RT_CID_819x_SAMSUNG = 30, - RT_CID_819x_WNC_COREGA = 31, }; enum reset_type { @@ -183,37 +161,7 @@ enum reset_type { }; struct rt_stats { - unsigned long rxrdu; - unsigned long rxok; - unsigned long rxdatacrcerr; - unsigned long rxmgmtcrcerr; - unsigned long rxcrcerrmin; - unsigned long rxcrcerrmid; - unsigned long rxcrcerrmax; unsigned long received_rate_histogram[4][32]; - unsigned long received_preamble_GI[2][32]; - unsigned long numpacket_matchbssid; - unsigned long numpacket_toself; - unsigned long num_process_phyinfo; - unsigned long numqry_phystatus; - unsigned long numqry_phystatusCCK; - unsigned long numqry_phystatusHT; - unsigned long received_bwtype[5]; - unsigned long rxoverflow; - unsigned long rxint; - unsigned long ints; - unsigned long shints; - unsigned long txoverflow; - unsigned long txbeokint; - unsigned long txbkokint; - unsigned long txviokint; - unsigned long txvookint; - unsigned long txbeaconokint; - unsigned long txbeaconerr; - unsigned long txmanageokint; - unsigned long txcmdpktokint; - unsigned long txbytesmulticast; - unsigned long txbytesbroadcast; unsigned long txbytesunicast; unsigned long rxbytesunicast; unsigned long txretrycount; @@ -223,14 +171,12 @@ struct rt_stats { unsigned long slide_rssi_total; unsigned long slide_evm_total; long signal_strength; - long signal_quality; long last_signal_strength_inpercent; long recv_signal_power; u8 rx_rssi_percentage[4]; u8 rx_evm_percentage[2]; - long rxSNRdB[4]; - u32 Slide_Beacon_pwdb[100]; - u32 Slide_Beacon_Total; + u32 slide_beacon_pwdb[100]; + u32 slide_beacon_total; u32 CurrentShowTxate; }; @@ -257,8 +203,6 @@ struct rtl8192_tx_ring { struct sk_buff_head queue; }; - - struct rtl819x_ops { enum nic_t nic_type; void (*get_eeprom_size)(struct net_device *dev); @@ -298,7 +242,6 @@ struct r8192_priv { struct pci_dev *pdev; struct pci_dev *bridge_pdev; - bool bfirst_init; bool bfirst_after_down; bool being_init_adapter; @@ -317,16 +260,15 @@ struct r8192_priv { struct work_struct reset_wq; - enum rt_customer_id CustomerID; - + enum rt_customer_id customer_id; enum rt_rf_type_819xu rf_chip; - enum ht_channel_width CurrentChannelBW; - struct bb_reg_definition PHYRegDef[4]; + enum ht_channel_width current_chnl_bw; + struct bb_reg_definition phy_reg_def[4]; struct rate_adaptive rate_adaptive; - struct rt_firmware *pFirmware; - enum rtl819x_loopback LoopbackMode; + struct rt_firmware *fw_info; + enum rtl819x_loopback loopback_mode; struct timer_list watch_dog_timer; struct timer_list fsync_timer; @@ -360,9 +302,9 @@ struct r8192_priv { int rxringcount; u16 rxbuffersize; - u64 LastRxDescTSF; + u64 last_rx_desc_tsf; - u32 ReceiveConfig; + u32 receive_config; u8 retry_data; u8 retry_rts; u16 rts; @@ -371,8 +313,8 @@ struct r8192_priv { int txringcount; atomic_t tx_pending[0x10]; - u16 ShortRetryLimit; - u16 LongRetryLimit; + u16 short_retry_limit; + u16 long_retry_limit; bool hw_radio_off; bool blinked_ingpio; @@ -396,94 +338,82 @@ struct r8192_priv { u32 irq_mask[2]; - u8 Rf_Mode; + u8 rf_mode; enum nic_t card_8192; u8 card_8192_version; u8 rf_type; - u8 IC_Cut; + u8 ic_cut; char nick[IW_ESSID_MAX_SIZE + 1]; u8 check_roaming_cnt; - u32 SilentResetRxSlotIndex; - u32 SilentResetRxStuckEvent[MAX_SILENT_RESET_RX_SLOT_NUM]; + u32 silent_reset_rx_slot_index; + u32 silent_reset_rx_stuck_event[MAX_SILENT_RESET_RX_SLOT_NUM]; u16 basic_rate; u8 short_preamble; u8 dot11_current_preamble_mode; u8 slot_time; - u16 SifsTime; - bool AutoloadFailFlag; + bool autoload_fail_flag; short epromtype; u16 eeprom_vid; u16 eeprom_did; - u8 eeprom_CustomerID; - u16 eeprom_ChannelPlan; + u8 eeprom_customer_id; + u16 eeprom_chnl_plan; - u8 EEPROMTxPowerLevelCCK[14]; - u8 EEPROMTxPowerLevelOFDM24G[14]; - u8 EEPROMRfACCKChnl1TxPwLevel[3]; - u8 EEPROMRfAOfdmChnlTxPwLevel[3]; - u8 EEPROMRfCCCKChnl1TxPwLevel[3]; - u8 EEPROMRfCOfdmChnlTxPwLevel[3]; - u16 EEPROMAntPwDiff; - u8 EEPROMThermalMeter; - u8 EEPROMCrystalCap; + u8 eeprom_tx_pwr_level_cck[14]; + u8 eeprom_tx_pwr_level_ofdm24g[14]; + u16 eeprom_ant_pwr_diff; + u8 eeprom_thermal_meter; + u8 eeprom_crystal_cap; - u8 EEPROMLegacyHTTxPowerDiff; + u8 eeprom_legacy_ht_tx_pwr_diff; - u8 CrystalCap; - u8 ThermalMeter[2]; + u8 crystal_cap; + u8 thermal_meter[2]; - u8 SwChnlInProgress; - u8 SwChnlStage; - u8 SwChnlStep; - u8 SetBWModeInProgress; + u8 sw_chnl_in_progress; + u8 sw_chnl_stage; + u8 sw_chnl_step; + u8 set_bw_mode_in_progress; - u8 nCur40MhzPrimeSC; + u8 n_cur_40mhz_prime_sc; - u32 RfReg0Value[4]; - u8 NumTotalRFPath; + u32 rf_reg_0value[4]; + u8 num_total_rf_path; bool brfpath_rxenable[4]; - bool bTXPowerDataReadFromEEPORM; + bool tx_pwr_data_read_from_eeprom; u16 reg_chnl_plan; - u16 ChannelPlan; + u16 chnl_plan; u8 hw_rf_off_action; bool rf_change_in_progress; - bool SetRFPowerStateInProgress; + bool set_rf_pwr_state_in_progress; bool bdisable_nic; - u8 DM_Type; - - u8 CckPwEnl; - u16 TSSI_13dBm; - u32 Pwr_Track; - u8 CCKPresentAttentuation_20Mdefault; - u8 CCKPresentAttentuation_40Mdefault; - s8 CCKPresentAttentuation_difference; + u8 cck_pwr_enl; + u16 tssi_13dBm; + u32 pwr_track; + u8 cck_present_attn_20m_def; + u8 cck_present_attn_40m_def; + s8 cck_present_attn_diff; s8 cck_present_attn; long undecorated_smoothed_pwdb; - u32 MCSTxPowerLevelOriginalOffset[6]; - u8 TxPowerLevelCCK[14]; - u8 TxPowerLevelCCK_A[14]; - u8 TxPowerLevelCCK_C[14]; - u8 TxPowerLevelOFDM24G[14]; - u8 TxPowerLevelOFDM24G_A[14]; - u8 TxPowerLevelOFDM24G_C[14]; - u8 LegacyHTTxPowerDiff; - s8 RF_C_TxPwDiff; - u8 AntennaTxPwDiff[3]; + u32 mcs_tx_pwr_level_org_offset[6]; + u8 tx_pwr_level_cck[14]; + u8 tx_pwr_level_ofdm_24g[14]; + u8 legacy_ht_tx_pwr_diff; + u8 antenna_tx_pwr_diff[3]; - bool bDynamicTxHighPower; - bool bDynamicTxLowPower; - bool bLastDTPFlag_High; - bool bLastDTPFlag_Low; + bool dynamic_tx_high_pwr; + bool dynamic_tx_low_pwr; + bool last_dtp_flag_high; + bool last_dtp_flag_low; u8 rfa_txpowertrackingindex; u8 rfa_txpowertrackingindex_real; @@ -494,42 +424,38 @@ struct r8192_priv { bool bcck_in_ch14; u8 txpower_count; - bool btxpower_trackingInit; + bool tx_pwr_tracking_init; - u8 OFDM_index[2]; - u8 CCK_index; + u8 ofdm_index[2]; + u8 cck_index; - u8 Record_CCK_20Mindex; - u8 Record_CCK_40Mindex; + u8 rec_cck_20m_idx; + u8 rec_cck_40m_idx; struct init_gain initgain_backup; - u8 DefaultInitialGain[4]; + u8 def_initial_gain[4]; bool bis_any_nonbepkts; bool bcurrent_turbo_EDCA; bool bis_cur_rdlstate; bool bfsync_processing; u32 rate_record; - u32 rateCountDiffRecord; - u32 ContinueDiffCount; + u32 rate_count_diff_rec; + u32 continue_diff_count; bool bswitch_fsync; u8 framesync; - u32 framesyncC34; - u8 framesyncMonitor; + u8 frame_sync_monitor; u32 reset_count; enum reset_type rst_progress; - u16 TxCounter; + u16 tx_counter; u16 rx_ctr; - bool bResetInProgress; + bool reset_in_progress; bool force_reset; bool force_lps; bool chan_forced; - - u8 PwrDomainProtect; - u8 H2CTxCmdSeq; }; extern const struct ethtool_ops rtl819x_ethtool_ops; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c index a18393c8a833..d8455b23e555 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -46,7 +46,7 @@ static u32 edca_setting_UL[HT_IOT_PEER_MAX] = { 0x5e4332 }; -const u32 dm_tx_bb_gain[TxBBGainTableLength] = { +const u32 dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN] = { 0x7f8001fe, /* 12 dB */ 0x788001e2, /* 11 dB */ 0x71c001c7, @@ -86,7 +86,7 @@ const u32 dm_tx_bb_gain[TxBBGainTableLength] = { 0x10000040, /* -24 dB */ }; -const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8] = { +const u8 dm_cck_tx_bb_gain[CCK_TX_BB_GAIN_TABLE_LEN][8] = { {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, @@ -112,7 +112,7 @@ const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8] = { {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} }; -const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8] = { +const u8 dm_cck_tx_bb_gain_ch14[CCK_TX_BB_GAIN_TABLE_LEN][8] = { {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, @@ -144,7 +144,7 @@ const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8] = { /*------------------------Define global variable-----------------------------*/ struct dig_t dm_digtable; -struct drx_path_sel DM_RxPathSelTable; +struct drx_path_sel dm_rx_path_sel_table; /*------------------------Define global variable-----------------------------*/ @@ -203,8 +203,6 @@ void rtl92e_dm_init(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - priv->DM_Type = DM_Type_ByDriver; - priv->undecorated_smoothed_pwdb = -1; _rtl92e_dm_init_dynamic_tx_power(dev); @@ -284,15 +282,15 @@ void rtl92e_init_adaptive_rate(struct net_device *dev) struct rate_adaptive *pra = &priv->rate_adaptive; pra->ratr_state = DM_RATR_STA_MAX; - pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High; - pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5; - pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5; + pra->high2low_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH; + pra->low2high_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M + 5; + pra->low2high_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M + 5; - pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5; - pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M; - pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M; + pra->high_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH + 5; + pra->low_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M; + pra->low_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M; - if (priv->CustomerID == RT_CID_819x_Netcore) + if (priv->customer_id == RT_CID_819X_NETCORE) pra->ping_rssi_enable = 1; else pra->ping_rssi_enable = 0; @@ -353,7 +351,7 @@ static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev) (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) { pra->low_rssi_threshold_ratr = (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31 : 0); @@ -368,15 +366,15 @@ static void _rtl92e_dm_check_rate_adaptive(struct net_device *dev) if (pra->ratr_state == DM_RATR_STA_HIGH) { HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra; - LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? + LowRSSIThreshForRA = (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) ? (pra->low_rssi_thresh_for_ra40M) : (pra->low_rssi_thresh_for_ra20M); } else if (pra->ratr_state == DM_RATR_STA_LOW) { HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; - LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? + LowRSSIThreshForRA = (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) ? (pra->low2high_rssi_thresh_for_ra40M) : (pra->low2high_rssi_thresh_for_ra20M); } else { HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra; - LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ? + LowRSSIThreshForRA = (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) ? (pra->low_rssi_thresh_for_ra40M) : (pra->low_rssi_thresh_for_ra20M); } @@ -443,8 +441,8 @@ static void _rtl92e_dm_bandwidth_autoswitch(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || - !priv->rtllib->bandwidth_auto_switch.bautoswitch_enable) + if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20 || + !priv->rtllib->bandwidth_auto_switch.bautoswitch_enable) return; if (!priv->rtllib->bandwidth_auto_switch.bforced_tx20Mhz) { if (priv->undecorated_smoothed_pwdb <= @@ -457,7 +455,7 @@ static void _rtl92e_dm_bandwidth_autoswitch(struct net_device *dev) } } -static u32 OFDMSwingTable[OFDM_Table_Length] = { +static u32 OFDMSwingTable[OFDM_TABLE_LEN] = { 0x7f8001fe, 0x71c001c7, 0x65400195, @@ -479,7 +477,7 @@ static u32 OFDMSwingTable[OFDM_Table_Length] = { 0x10000040 }; -static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { +static u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_LEN][8] = { {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, @@ -494,7 +492,7 @@ static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = { {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} }; -static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = { +static u8 CCKSwingTable_Ch14[CCK_TABLE_LEN][8] = { {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, @@ -570,8 +568,8 @@ static void _rtl92e_dm_tx_update_tssi_strong_signal(struct net_device *dev, struct r8192_priv *p = rtllib_priv(dev); if (RF_Type == RF_2T4R) { - if ((p->rfa_txpowertrackingindex < TxBBGainTableLength - 1) && - (p->rfc_txpowertrackingindex < TxBBGainTableLength - 1)) { + if ((p->rfa_txpowertrackingindex < TX_BB_GAIN_TABLE_LEN - 1) && + (p->rfc_txpowertrackingindex < TX_BB_GAIN_TABLE_LEN - 1)) { p->rfa_txpowertrackingindex++; p->rfa_txpowertrackingindex_real++; rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, @@ -585,13 +583,13 @@ static void _rtl92e_dm_tx_update_tssi_strong_signal(struct net_device *dev, } else { rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, - dm_tx_bb_gain[TxBBGainTableLength - 1]); + dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]); rtl92e_set_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, - dm_tx_bb_gain[TxBBGainTableLength - 1]); + dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]); } } else { - if (p->rfa_txpowertrackingindex < (TxBBGainTableLength - 1)) { + if (p->rfa_txpowertrackingindex < (TX_BB_GAIN_TABLE_LEN - 1)) { p->rfa_txpowertrackingindex++; p->rfa_txpowertrackingindex_real++; rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, @@ -600,7 +598,7 @@ static void _rtl92e_dm_tx_update_tssi_strong_signal(struct net_device *dev, } else { rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, - dm_tx_bb_gain[TxBBGainTableLength - 1]); + dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN - 1]); } } } @@ -615,14 +613,14 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev) u8 RF_Type, tmp_report[5] = {0, 0, 0, 0, 0}; u32 Value; u8 Pwr_Flag; - u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0; + u16 Avg_TSSI_Meas, tssi_13dBm, Avg_TSSI_Meas_from_driver = 0; u32 delta = 0; rtl92e_writeb(dev, Pw_Track_Flag, 0); rtl92e_writeb(dev, FW_Busy_Flag, 0); priv->rtllib->bdynamic_txpower_enable = false; - powerlevelOFDM24G = priv->Pwr_Track >> 24; + powerlevelOFDM24G = priv->pwr_track >> 24; RF_Type = priv->rf_type; Value = (RF_Type<<8) | powerlevelOFDM24G; @@ -640,7 +638,7 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev) if (Pwr_Flag == 0) { mdelay(1); - if (priv->bResetInProgress) { + if (priv->reset_in_progress) { rtl92e_writeb(dev, Pw_Track_Flag, 0); rtl92e_writeb(dev, FW_Busy_Flag, 0); return; @@ -688,12 +686,12 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev) Avg_TSSI_Meas_from_driver += tmp_report[k]; Avg_TSSI_Meas_from_driver *= 100 / 5; - TSSI_13dBm = priv->TSSI_13dBm; + tssi_13dBm = priv->tssi_13dBm; - if (Avg_TSSI_Meas_from_driver > TSSI_13dBm) - delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm; + if (Avg_TSSI_Meas_from_driver > tssi_13dBm) + delta = Avg_TSSI_Meas_from_driver - tssi_13dBm; else - delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver; + delta = tssi_13dBm - Avg_TSSI_Meas_from_driver; if (delta <= E_FOR_TX_POWER_TRACK) { priv->rtllib->bdynamic_txpower_enable = true; @@ -701,36 +699,36 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev) rtl92e_writeb(dev, FW_Busy_Flag, 0); return; } - if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) + if (Avg_TSSI_Meas_from_driver < tssi_13dBm - E_FOR_TX_POWER_TRACK) _rtl92e_dm_tx_update_tssi_weak_signal(dev, RF_Type); else _rtl92e_dm_tx_update_tssi_strong_signal(dev, RF_Type); if (RF_Type == RF_2T4R) { - priv->CCKPresentAttentuation_difference + priv->cck_present_attn_diff = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default; } else { - priv->CCKPresentAttentuation_difference + priv->cck_present_attn_diff = priv->rfa_txpowertrackingindex_real - priv->rfa_txpowertracking_default; } - if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) priv->cck_present_attn = - priv->CCKPresentAttentuation_20Mdefault + - priv->CCKPresentAttentuation_difference; + priv->cck_present_attn_20m_def + + priv->cck_present_attn_diff; else priv->cck_present_attn = - priv->CCKPresentAttentuation_40Mdefault + - priv->CCKPresentAttentuation_difference; + priv->cck_present_attn_40m_def + + priv->cck_present_attn_diff; - if (priv->cck_present_attn > (CCKTxBBGainTableLength-1)) - priv->cck_present_attn = CCKTxBBGainTableLength-1; + if (priv->cck_present_attn > (CCK_TX_BB_GAIN_TABLE_LEN - 1)) + priv->cck_present_attn = CCK_TX_BB_GAIN_TABLE_LEN - 1; if (priv->cck_present_attn < 0) priv->cck_present_attn = 0; if (priv->cck_present_attn > -1 && - priv->cck_present_attn < CCKTxBBGainTableLength) { + priv->cck_present_attn < CCK_TX_BB_GAIN_TABLE_LEN) { if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) { priv->bcck_in_ch14 = true; @@ -742,8 +740,8 @@ static void _rtl92e_dm_tx_power_tracking_callback_tssi(struct net_device *dev) rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); } - if (priv->CCKPresentAttentuation_difference <= -12 || - priv->CCKPresentAttentuation_difference >= 24) { + if (priv->cck_present_attn_diff <= -12 || + priv->cck_present_attn_diff >= 24) { priv->rtllib->bdynamic_txpower_enable = true; rtl92e_writeb(dev, Pw_Track_Flag, 0); rtl92e_writeb(dev, FW_Busy_Flag, 0); @@ -770,22 +768,22 @@ static void _rtl92e_dm_tx_power_tracking_cb_thermal(struct net_device *dev) u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval; int i = 0, CCKSwingNeedUpdate = 0; - if (!priv->btxpower_trackingInit) { + if (!priv->tx_pwr_tracking_init) { tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord); - for (i = 0; i < OFDM_Table_Length; i++) { + for (i = 0; i < OFDM_TABLE_LEN; i++) { if (tmpRegA == OFDMSwingTable[i]) - priv->OFDM_index[0] = i; + priv->ofdm_index[0] = i; } TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1, bMaskByte2); - for (i = 0; i < CCK_Table_length; i++) { + for (i = 0; i < CCK_TABLE_LEN; i++) { if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) { - priv->CCK_index = i; + priv->cck_index = i; break; } } - priv->btxpower_trackingInit = true; + priv->tx_pwr_tracking_init = true; return; } @@ -794,21 +792,21 @@ static void _rtl92e_dm_tx_power_tracking_cb_thermal(struct net_device *dev) return; if (tmpRegA >= 12) tmpRegA = 12; - priv->ThermalMeter[0] = ThermalMeterVal; - priv->ThermalMeter[1] = ThermalMeterVal; + priv->thermal_meter[0] = ThermalMeterVal; + priv->thermal_meter[1] = ThermalMeterVal; - if (priv->ThermalMeter[0] >= (u8)tmpRegA) { - tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0] - + if (priv->thermal_meter[0] >= (u8)tmpRegA) { + tmpOFDMindex = tmpCCK20Mindex = 6+(priv->thermal_meter[0] - (u8)tmpRegA); tmpCCK40Mindex = tmpCCK20Mindex - 6; - if (tmpOFDMindex >= OFDM_Table_Length) - tmpOFDMindex = OFDM_Table_Length-1; - if (tmpCCK20Mindex >= CCK_Table_length) - tmpCCK20Mindex = CCK_Table_length-1; - if (tmpCCK40Mindex >= CCK_Table_length) - tmpCCK40Mindex = CCK_Table_length-1; + if (tmpOFDMindex >= OFDM_TABLE_LEN) + tmpOFDMindex = OFDM_TABLE_LEN - 1; + if (tmpCCK20Mindex >= CCK_TABLE_LEN) + tmpCCK20Mindex = CCK_TABLE_LEN - 1; + if (tmpCCK40Mindex >= CCK_TABLE_LEN) + tmpCCK40Mindex = CCK_TABLE_LEN - 1; } else { - tmpval = (u8)tmpRegA - priv->ThermalMeter[0]; + tmpval = (u8)tmpRegA - priv->thermal_meter[0]; if (tmpval >= 6) { tmpOFDMindex = 0; tmpCCK20Mindex = 0; @@ -818,13 +816,13 @@ static void _rtl92e_dm_tx_power_tracking_cb_thermal(struct net_device *dev) } tmpCCK40Mindex = 0; } - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) tmpCCKindex = tmpCCK40Mindex; else tmpCCKindex = tmpCCK20Mindex; - priv->Record_CCK_20Mindex = tmpCCK20Mindex; - priv->Record_CCK_40Mindex = tmpCCK40Mindex; + priv->rec_cck_20m_idx = tmpCCK20Mindex; + priv->rec_cck_40m_idx = tmpCCK40Mindex; if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) { @@ -836,17 +834,17 @@ static void _rtl92e_dm_tx_power_tracking_cb_thermal(struct net_device *dev) CCKSwingNeedUpdate = 1; } - if (priv->CCK_index != tmpCCKindex) { - priv->CCK_index = tmpCCKindex; + if (priv->cck_index != tmpCCKindex) { + priv->cck_index = tmpCCKindex; CCKSwingNeedUpdate = 1; } if (CCKSwingNeedUpdate) rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); - if (priv->OFDM_index[0] != tmpOFDMindex) { - priv->OFDM_index[0] = tmpOFDMindex; + if (priv->ofdm_index[0] != tmpOFDMindex) { + priv->ofdm_index[0] = tmpOFDMindex; rtl92e_set_bb_reg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, - OFDMSwingTable[priv->OFDM_index[0]]); + OFDMSwingTable[priv->ofdm_index[0]]); } priv->txpower_count = 0; } @@ -857,7 +855,7 @@ void rtl92e_dm_txpower_tracking_wq(void *data) struct r8192_priv, txpower_tracking_wq); struct net_device *dev = priv->rtllib->dev; - if (priv->IC_Cut >= IC_VersionCut_D) + if (priv->ic_cut >= IC_VersionCut_D) _rtl92e_dm_tx_power_tracking_callback_tssi(dev); else _rtl92e_dm_tx_power_tracking_cb_thermal(dev); @@ -870,7 +868,7 @@ static void _rtl92e_dm_initialize_tx_power_tracking_tssi(struct net_device *dev) priv->btxpower_tracking = true; priv->txpower_count = 0; - priv->btxpower_trackingInit = false; + priv->tx_pwr_tracking_init = false; } @@ -884,14 +882,14 @@ static void _rtl92e_dm_init_tx_power_tracking_thermal(struct net_device *dev) else priv->btxpower_tracking = false; priv->txpower_count = 0; - priv->btxpower_trackingInit = false; + priv->tx_pwr_tracking_init = false; } void rtl92e_dm_init_txpower_tracking(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - if (priv->IC_Cut >= IC_VersionCut_D) + if (priv->ic_cut >= IC_VersionCut_D) _rtl92e_dm_initialize_tx_power_tracking_tssi(dev); else _rtl92e_dm_init_tx_power_tracking_thermal(dev); @@ -952,7 +950,7 @@ static void _rtl92e_dm_check_tx_power_tracking(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); - if (priv->IC_Cut >= IC_VersionCut_D) + if (priv->ic_cut >= IC_VersionCut_D) _rtl92e_dm_check_tx_power_tracking_tssi(dev); else _rtl92e_dm_check_tx_power_tracking_thermal(dev); @@ -1005,30 +1003,30 @@ static void _rtl92e_dm_cck_tx_power_adjust_thermal_meter(struct net_device *dev, TempVal = 0; if (!bInCH14) { - TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] + - (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1] << 8); + TempVal = CCKSwingTable_Ch1_Ch13[priv->cck_index][0] + + (CCKSwingTable_Ch1_Ch13[priv->cck_index][1] << 8); rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); - TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] + - (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3] << 8) + - (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4] << 16)+ - (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5] << 24); + TempVal = CCKSwingTable_Ch1_Ch13[priv->cck_index][2] + + (CCKSwingTable_Ch1_Ch13[priv->cck_index][3] << 8) + + (CCKSwingTable_Ch1_Ch13[priv->cck_index][4] << 16)+ + (CCKSwingTable_Ch1_Ch13[priv->cck_index][5] << 24); rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); - TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] + - (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7] << 8); + TempVal = CCKSwingTable_Ch1_Ch13[priv->cck_index][6] + + (CCKSwingTable_Ch1_Ch13[priv->cck_index][7] << 8); rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); } else { - TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] + - (CCKSwingTable_Ch14[priv->CCK_index][1] << 8); + TempVal = CCKSwingTable_Ch14[priv->cck_index][0] + + (CCKSwingTable_Ch14[priv->cck_index][1] << 8); rtl92e_set_bb_reg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal); - TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] + - (CCKSwingTable_Ch14[priv->CCK_index][3] << 8) + - (CCKSwingTable_Ch14[priv->CCK_index][4] << 16)+ - (CCKSwingTable_Ch14[priv->CCK_index][5] << 24); + TempVal = CCKSwingTable_Ch14[priv->cck_index][2] + + (CCKSwingTable_Ch14[priv->cck_index][3] << 8) + + (CCKSwingTable_Ch14[priv->cck_index][4] << 16)+ + (CCKSwingTable_Ch14[priv->cck_index][5] << 24); rtl92e_set_bb_reg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal); - TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] + - (CCKSwingTable_Ch14[priv->CCK_index][7]<<8); + TempVal = CCKSwingTable_Ch14[priv->cck_index][6] + + (CCKSwingTable_Ch14[priv->cck_index][7]<<8); rtl92e_set_bb_reg(dev, rCCK0_DebugPort, bMaskLWord, TempVal); } @@ -1038,7 +1036,7 @@ void rtl92e_dm_cck_txpower_adjust(struct net_device *dev, bool binch14) { struct r8192_priv *priv = rtllib_priv(dev); - if (priv->IC_Cut >= IC_VersionCut_D) + if (priv->ic_cut >= IC_VersionCut_D) _rtl92e_dm_cck_tx_power_adjust_tssi(dev, binch14); else _rtl92e_dm_cck_tx_power_adjust_thermal_meter(dev, binch14); @@ -1075,7 +1073,7 @@ void rtl92e_dm_restore_state(struct net_device *dev) ratr_value &= ~(RATE_ALL_OFDM_2SS); rtl92e_writel(dev, RATR0, ratr_value); rtl92e_writeb(dev, UFWP, 1); - if (priv->btxpower_trackingInit && priv->btxpower_tracking) + if (priv->tx_pwr_tracking_init && priv->btxpower_tracking) _rtl92e_dm_tx_power_reset_recovery(dev); _rtl92e_dm_bb_initialgain_restore(dev); @@ -1150,7 +1148,7 @@ static void _rtl92e_dm_dig_init(struct net_device *dev) dm_digtable.rssi_val = 50; dm_digtable.backoff_val = DM_DIG_BACKOFF; dm_digtable.rx_gain_range_max = DM_DIG_MAX; - if (priv->CustomerID == RT_CID_819x_Netcore) + if (priv->customer_id == RT_CID_819X_NETCORE) dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore; else dm_digtable.rx_gain_range_min = DM_DIG_MIN; @@ -1260,7 +1258,7 @@ static void _rtl92e_dm_ctrl_initgain_byrssi_false_alarm(struct net_device *dev) rtl92e_writeb(dev, rOFDM0_XCAGCCore1, 0x17); rtl92e_writeb(dev, rOFDM0_XDAGCCore1, 0x17); - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x00); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x42); @@ -1297,7 +1295,7 @@ static void _rtl92e_dm_ctrl_initgain_byrssi_false_alarm(struct net_device *dev) rtl92e_writeb(dev, rOFDM0_XDAGCCore1, 0x20); } - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x20); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x44); @@ -1328,7 +1326,7 @@ static void _rtl92e_dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev) return; dm_digtable.dig_highpwr_state = DM_STA_DIG_ON; - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x10); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x43); @@ -1342,7 +1340,7 @@ static void _rtl92e_dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev) dm_digtable.rssi_high_power_lowthresh) && (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)) { - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x20); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x44); @@ -1378,12 +1376,12 @@ static void _rtl92e_dm_initial_gain(struct net_device *dev) dm_digtable.cur_ig_value = gain_range; } else { if (dm_digtable.cur_ig_value == 0) - dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; + dm_digtable.cur_ig_value = priv->def_initial_gain[0]; else dm_digtable.cur_ig_value = dm_digtable.pre_ig_value; } } else { - dm_digtable.cur_ig_value = priv->DefaultInitialGain[0]; + dm_digtable.cur_ig_value = priv->def_initial_gain[0]; dm_digtable.pre_ig_value = 0; } @@ -1453,18 +1451,18 @@ static void _rtl92e_dm_pd_th(struct net_device *dev) if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) || (initialized <= 3) || force_write) { if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) { - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x00); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x42); } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) { - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x20); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x44); } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) { - if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) + if (priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) rtl92e_writeb(dev, (rOFDM0_XATxAFE+3), 0x10); else rtl92e_writeb(dev, rOFDM0_RxDetector1, 0x43); @@ -1651,7 +1649,7 @@ static void _rtl92e_dm_init_wa_broadcom_iot(struct net_device *dev) struct rt_hi_throughput *ht_info = priv->rtllib->ht_info; ht_info->bWAIotBroadcom = false; - ht_info->WAIotTH = WAIotTHVal; + ht_info->WAIotTH = WA_IOT_TH_VAL; } static void _rtl92e_dm_check_rf_ctrl_gpio(void *data) @@ -1722,7 +1720,7 @@ void rtl92e_dm_rf_pathcheck_wq(void *data) else priv->brfpath_rxenable[i] = false; } - if (!DM_RxPathSelTable.Enable) + if (!dm_rx_path_sel_table.enable) return; _rtl92e_dm_rx_path_sel_byrssi(dev); @@ -1733,18 +1731,18 @@ static void _rtl92e_dm_init_rx_path_selection(struct net_device *dev) u8 i; struct r8192_priv *priv = rtllib_priv(dev); - DM_RxPathSelTable.Enable = 1; - DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low; - DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH; - if (priv->CustomerID == RT_CID_819x_Netcore) - DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; + dm_rx_path_sel_table.enable = 1; + dm_rx_path_sel_table.ss_th_low = RX_PATH_SEL_SS_TH_LOW; + dm_rx_path_sel_table.diff_th = RX_PATH_SEL_DIFF_TH; + if (priv->customer_id == RT_CID_819X_NETCORE) + dm_rx_path_sel_table.cck_method = CCK_Rx_Version_2; else - DM_RxPathSelTable.cck_method = CCK_Rx_Version_1; - DM_RxPathSelTable.disabledRF = 0; + dm_rx_path_sel_table.cck_method = CCK_Rx_Version_1; + dm_rx_path_sel_table.disabled_rf = 0; for (i = 0; i < 4; i++) { - DM_RxPathSelTable.rf_rssi[i] = 50; - DM_RxPathSelTable.cck_pwdb_sta[i] = -64; - DM_RxPathSelTable.rf_enable_rssi_th[i] = 100; + dm_rx_path_sel_table.rf_rssi[i] = 50; + dm_rx_path_sel_table.cck_pwdb_sta[i] = -64; + dm_rx_path_sel_table.rf_enable_rssi_th[i] = 100; } } @@ -1771,22 +1769,22 @@ static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev) return; if (!cck_Rx_Path_initialized) { - DM_RxPathSelTable.cck_Rx_path = (rtl92e_readb(dev, 0xa07)&0xf); + dm_rx_path_sel_table.cck_rx_path = (rtl92e_readb(dev, 0xa07)&0xf); cck_Rx_Path_initialized = 1; } - DM_RxPathSelTable.disabledRF = 0xf; - DM_RxPathSelTable.disabledRF &= ~(rtl92e_readb(dev, 0xc04)); + dm_rx_path_sel_table.disabled_rf = 0xf; + dm_rx_path_sel_table.disabled_rf &= ~(rtl92e_readb(dev, 0xc04)); if (priv->rtllib->mode == WIRELESS_MODE_B) - DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; + dm_rx_path_sel_table.cck_method = CCK_Rx_Version_2; for (i = 0; i < RF90_PATH_MAX; i++) { - DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; + dm_rx_path_sel_table.rf_rssi[i] = priv->stats.rx_rssi_percentage[i]; if (priv->brfpath_rxenable[i]) { rf_num++; - cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i]; + cur_rf_rssi = dm_rx_path_sel_table.rf_rssi[i]; if (rf_num == 1) { max_rssi_index = min_rssi_index = sec_rssi_index = i; @@ -1834,12 +1832,12 @@ static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev) } rf_num = 0; - if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) { + if (dm_rx_path_sel_table.cck_method == CCK_Rx_Version_2) { for (i = 0; i < RF90_PATH_MAX; i++) { if (priv->brfpath_rxenable[i]) { rf_num++; cur_cck_pwdb = - DM_RxPathSelTable.cck_pwdb_sta[i]; + dm_rx_path_sel_table.cck_pwdb_sta[i]; if (rf_num == 1) { cck_rx_ver2_max_index = i; @@ -1896,17 +1894,17 @@ static void _rtl92e_dm_rx_path_sel_byrssi(struct net_device *dev) } update_cck_rx_path = 0; - if (DM_RxPathSelTable.cck_method == CCK_Rx_Version_2) { + if (dm_rx_path_sel_table.cck_method == CCK_Rx_Version_2) { cck_default_Rx = cck_rx_ver2_max_index; cck_optional_Rx = cck_rx_ver2_sec_index; if (tmp_cck_max_pwdb != -64) update_cck_rx_path = 1; } - if (tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2) { + if (tmp_min_rssi < dm_rx_path_sel_table.ss_th_low && disabled_rf_cnt < 2) { if ((tmp_max_rssi - tmp_min_rssi) >= - DM_RxPathSelTable.diff_TH) { - DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = + dm_rx_path_sel_table.diff_th) { + dm_rx_path_sel_table.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5; rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0x1<>i) & 0x1) { + if ((dm_rx_path_sel_table.disabled_rf >> i) & 0x1) { if (tmp_max_rssi >= - DM_RxPathSelTable.rf_enable_rssi_th[i]) { + dm_rx_path_sel_table.rf_enable_rssi_th[i]) { rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0x1 << i, 0x1); rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0x1 << i, 0x1); - DM_RxPathSelTable.rf_enable_rssi_th[i] + dm_rx_path_sel_table.rf_enable_rssi_th[i] = 100; disabled_rf_cnt--; } @@ -1969,7 +1967,7 @@ static void _rtl92e_dm_init_fsync(struct net_device *dev) priv->rtllib->fsync_firstdiff_ratethreshold = 100; priv->rtllib->fsync_seconddiff_ratethreshold = 200; priv->rtllib->fsync_state = Default_Fsync; - priv->framesyncMonitor = 1; + priv->frame_sync_monitor = 1; timer_setup(&priv->fsync_timer, _rtl92e_dm_fsync_timer_callback, 0); } @@ -2008,31 +2006,31 @@ static void _rtl92e_dm_fsync_timer_callback(struct timer_list *t) priv->rate_record; else rate_count_diff = rate_count - priv->rate_record; - if (rate_count_diff < priv->rateCountDiffRecord) { + if (rate_count_diff < priv->rate_count_diff_rec) { - u32 DiffNum = priv->rateCountDiffRecord - + u32 DiffNum = priv->rate_count_diff_rec - rate_count_diff; if (DiffNum >= priv->rtllib->fsync_seconddiff_ratethreshold) - priv->ContinueDiffCount++; + priv->continue_diff_count++; else - priv->ContinueDiffCount = 0; + priv->continue_diff_count = 0; - if (priv->ContinueDiffCount >= 2) { + if (priv->continue_diff_count >= 2) { bSwitchFromCountDiff = true; - priv->ContinueDiffCount = 0; + priv->continue_diff_count = 0; } } else { - priv->ContinueDiffCount = 0; + priv->continue_diff_count = 0; } if (rate_count_diff <= priv->rtllib->fsync_firstdiff_ratethreshold) { bSwitchFromCountDiff = true; - priv->ContinueDiffCount = 0; + priv->continue_diff_count = 0; } priv->rate_record = rate_count; - priv->rateCountDiffRecord = rate_count_diff; + priv->rate_count_diff_rec = rate_count_diff; if (priv->undecorated_smoothed_pwdb > priv->rtllib->fsync_rssi_threshold && bSwitchFromCountDiff) { @@ -2073,7 +2071,7 @@ static void _rtl92e_dm_fsync_timer_callback(struct timer_list *t) rtl92e_writeb(dev, 0xC36, 0x5c); rtl92e_writeb(dev, 0xC3e, 0x96); } - priv->ContinueDiffCount = 0; + priv->continue_diff_count = 0; rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c52cd); } } @@ -2114,7 +2112,7 @@ static void _rtl92e_dm_end_sw_fsync(struct net_device *dev) rtl92e_writeb(dev, 0xC3e, 0x96); } - priv->ContinueDiffCount = 0; + priv->continue_diff_count = 0; rtl92e_writel(dev, rOFDM0_RxDetector2, 0x465c52cd); } @@ -2125,8 +2123,8 @@ static void _rtl92e_dm_start_sw_fsync(struct net_device *dev) u32 rate_bitmap; priv->rate_record = 0; - priv->ContinueDiffCount = 0; - priv->rateCountDiffRecord = 0; + priv->continue_diff_count = 0; + priv->rate_count_diff_rec = 0; priv->bswitch_fsync = false; if (priv->rtllib->mode == WIRELESS_MODE_N_24G) { @@ -2196,7 +2194,7 @@ static void _rtl92e_dm_check_fsync(struct net_device *dev) } } - if (priv->framesyncMonitor) { + if (priv->frame_sync_monitor) { if (reg_c38_State != RegC38_Fsync_AP_BCM) { rtl92e_writeb(dev, rOFDM0_RxDetector3, 0x95); @@ -2218,7 +2216,7 @@ static void _rtl92e_dm_check_fsync(struct net_device *dev) break; } - if (priv->framesyncMonitor) { + if (priv->frame_sync_monitor) { if (priv->rtllib->state == RTLLIB_LINKED) { if (priv->undecorated_smoothed_pwdb <= RegC38_TH) { @@ -2249,7 +2247,7 @@ static void _rtl92e_dm_check_fsync(struct net_device *dev) } } } - if (priv->framesyncMonitor) { + if (priv->frame_sync_monitor) { if (priv->reset_count != reset_cnt) { rtl92e_writeb(dev, rOFDM0_RxDetector3, priv->framesync); @@ -2271,10 +2269,10 @@ static void _rtl92e_dm_init_dynamic_tx_power(struct net_device *dev) struct r8192_priv *priv = rtllib_priv(dev); priv->rtllib->bdynamic_txpower_enable = true; - priv->bLastDTPFlag_High = false; - priv->bLastDTPFlag_Low = false; - priv->bDynamicTxHighPower = false; - priv->bDynamicTxLowPower = false; + priv->last_dtp_flag_high = false; + priv->last_dtp_flag_low = false; + priv->dynamic_tx_high_pwr = false; + priv->dynamic_tx_low_pwr = false; } static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev) @@ -2284,8 +2282,8 @@ static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev) unsigned int txlowpower_threshold = 0; if (!priv->rtllib->bdynamic_txpower_enable) { - priv->bDynamicTxHighPower = false; - priv->bDynamicTxLowPower = false; + priv->dynamic_tx_high_pwr = false; + priv->dynamic_tx_low_pwr = false; return; } if ((priv->rtllib->ht_info->IOTPeer == HT_IOT_PEER_ATHEROS) && @@ -2299,28 +2297,28 @@ static void _rtl92e_dm_dynamic_tx_power(struct net_device *dev) if (priv->rtllib->state == RTLLIB_LINKED) { if (priv->undecorated_smoothed_pwdb >= txhipower_threshold) { - priv->bDynamicTxHighPower = true; - priv->bDynamicTxLowPower = false; + priv->dynamic_tx_high_pwr = true; + priv->dynamic_tx_low_pwr = false; } else { if (priv->undecorated_smoothed_pwdb < - txlowpower_threshold && priv->bDynamicTxHighPower) - priv->bDynamicTxHighPower = false; + txlowpower_threshold && priv->dynamic_tx_high_pwr) + priv->dynamic_tx_high_pwr = false; if (priv->undecorated_smoothed_pwdb < 35) - priv->bDynamicTxLowPower = true; + priv->dynamic_tx_low_pwr = true; else if (priv->undecorated_smoothed_pwdb >= 40) - priv->bDynamicTxLowPower = false; + priv->dynamic_tx_low_pwr = false; } } else { - priv->bDynamicTxHighPower = false; - priv->bDynamicTxLowPower = false; + priv->dynamic_tx_high_pwr = false; + priv->dynamic_tx_low_pwr = false; } - if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) || - (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) { + if ((priv->dynamic_tx_high_pwr != priv->last_dtp_flag_high) || + (priv->dynamic_tx_low_pwr != priv->last_dtp_flag_low)) { rtl92e_set_tx_power(dev, priv->rtllib->current_network.channel); } - priv->bLastDTPFlag_High = priv->bDynamicTxHighPower; - priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower; + priv->last_dtp_flag_high = priv->dynamic_tx_high_pwr; + priv->last_dtp_flag_low = priv->dynamic_tx_low_pwr; } diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h index 1d4d7d98a859..01587e2fec65 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.h @@ -7,10 +7,9 @@ #ifndef __R8192UDM_H__ #define __R8192UDM_H__ - /*--------------------------Define Parameters-------------------------------*/ -#define OFDM_Table_Length 19 -#define CCK_Table_length 12 +#define OFDM_TABLE_LEN 19 +#define CCK_TABLE_LEN 12 #define DM_DIG_THRESH_HIGH 40 #define DM_DIG_THRESH_LOW 35 @@ -26,15 +25,15 @@ #define DM_DIG_MIN 0x1c #define DM_DIG_MIN_Netcore 0x12 -#define RxPathSelection_SS_TH_low 30 -#define RxPathSelection_diff_TH 18 +#define RX_PATH_SEL_SS_TH_LOW 30 +#define RX_PATH_SEL_DIFF_TH 18 -#define RateAdaptiveTH_High 50 -#define RateAdaptiveTH_Low_20M 30 -#define RateAdaptiveTH_Low_40M 10 -#define VeryLowRSSI 15 +#define RATE_ADAPTIVE_TH_HIGH 50 +#define RATE_ADAPTIVE_TH_LOW_20M 30 +#define RATE_ADAPTIVE_TH_LOW_40M 10 +#define VERY_LOW_RSSI 15 -#define WAIotTHVal 25 +#define WA_IOT_TH_VAL 25 #define E_FOR_TX_POWER_TRACK 300 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 @@ -47,11 +46,8 @@ #define TX_RETRY_COUNT_REG 0x1ac #define RegC38_TH 20 -#define DM_Type_ByDriver 1 - /*--------------------------Define Parameters-------------------------------*/ - /*------------------------------Define structure----------------------------*/ struct dig_t { u8 dig_enable_flag; @@ -90,7 +86,6 @@ enum dm_dig_sta { DM_STA_DIG_MAX }; - enum dm_ratr_sta { DM_RATR_STA_HIGH = 0, DM_RATR_STA_MIDDLE = 1, @@ -130,13 +125,13 @@ enum dm_dig_cs_ratio { }; struct drx_path_sel { - u8 Enable; + u8 enable; u8 cck_method; - u8 cck_Rx_path; + u8 cck_rx_path; - u8 SS_TH_low; - u8 diff_TH; - u8 disabledRF; + u8 ss_th_low; + u8 diff_th; + u8 disabled_rf; u8 reserved; u8 rf_rssi[4]; @@ -150,29 +145,26 @@ enum dm_cck_rx_path_method { CCK_Rx_Version_MAX }; - struct dcmd_txcmd { u32 op; u32 length; u32 value; }; -/*------------------------------Define structure----------------------------*/ +/*------------------------------Define structure----------------------------*/ /*------------------------Export global variable----------------------------*/ extern struct dig_t dm_digtable; -extern struct drx_path_sel DM_RxPathSelTable; /* Pre-calculated gain tables */ -extern const u32 dm_tx_bb_gain[TxBBGainTableLength]; -extern const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8]; -extern const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8]; +extern const u32 dm_tx_bb_gain[TX_BB_GAIN_TABLE_LEN]; +extern const u8 dm_cck_tx_bb_gain[CCK_TX_BB_GAIN_TABLE_LEN][8]; +extern const u8 dm_cck_tx_bb_gain_ch14[CCK_TX_BB_GAIN_TABLE_LEN][8]; /* Maps table index to iq amplify gain (dB, 12 to -24dB) */ #define dm_tx_bb_gain_idx_to_amplify(idx) (-idx + 12) /*------------------------Export global variable----------------------------*/ - /*--------------------------Exported Function prototype---------------------*/ /*--------------------------Exported Function prototype---------------------*/ @@ -181,7 +173,6 @@ void rtl92e_dm_deinit(struct net_device *dev); void rtl92e_dm_watchdog(struct net_device *dev); - void rtl92e_init_adaptive_rate(struct net_device *dev); void rtl92e_dm_txpower_tracking_wq(void *data); diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c index 82b45c61ac75..9c80dc1b6e12 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_pm.c @@ -41,7 +41,7 @@ int rtl92e_suspend(struct device *dev_d) rtl92e_writel(dev, WFCRC1, 0xffffffff); rtl92e_writel(dev, WFCRC2, 0xffffffff); rtl92e_writeb(dev, PMR, 0x5); - rtl92e_writeb(dev, MacBlkCtrl, 0xa); + rtl92e_writeb(dev, MAC_BLK_CTRL, 0xa); } out_pci_suspend: netdev_info(dev, "WOL is %s\n", priv->rtllib->bSupportRemoteWakeUp ? diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211.h b/drivers/staging/rtl8192u/ieee80211/ieee80211.h index c5c43d2fb93e..694d1b18f81c 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211.h @@ -1823,7 +1823,7 @@ struct ieee80211_device { struct work_struct associate_procedure_wq; struct delayed_work softmac_scan_wq; struct delayed_work associate_retry_wq; - struct delayed_work start_ibss_wq; + struct delayed_work start_ibss_wq; struct work_struct wx_sync_scan_wq; struct workqueue_struct *wq; // Qos related. Added by Annie, 2005-11-01. diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c b/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c index f1fc077ed29c..0fcae6871108 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c @@ -653,7 +653,7 @@ static void Hal_EfusePowerSwitch( if (PwrState) { - /* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */ + /* To avoid cannot access efuse registers after disable/enable several times during DTM test. */ /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */ tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL); if (tempval & BIT(0)) { /* SDIO local register is suspend */ @@ -1693,7 +1693,7 @@ void rtl8723b_InitBeaconParameters(struct adapter *padapter) rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B); /* 2ms */ /* Suggested by designer timchen. Change beacon AIFS to the largest number */ - /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */ + /* because test chip does not contension before sending beacon. by tynli. 2009.11.03 */ rtw_write16(padapter, REG_BCNTCFG, 0x660F); pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL); @@ -2089,7 +2089,7 @@ void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo) u16 EEPROMId; - /* Checl 0x8129 again for making sure autoload status!! */ + /* Check 0x8129 again for making sure autoload status!! */ EEPROMId = le16_to_cpu(*((__le16 *)hwinfo)); if (EEPROMId != RTL_EEPROM_ID) { pEEPROM->bautoload_fail_flag = true; @@ -2510,7 +2510,7 @@ static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc) /* Clear first */ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); - /* checksume is always calculated by first 32 bytes, */ + /* checksum is always calculated by first 32 bytes, */ /* and it doesn't depend on TX DESC length. */ /* Thomas, Lucas@SD4, 20130515 */ count = 16; @@ -2723,7 +2723,7 @@ static void rtl8723b_fill_default_txdesc( * multicast / mgnt frame should be controlled by Hw because Fw * will also send null data which we cannot control when Fw LPS * enable. - * --> default enable non-Qos data sequense number. 2010.06.23. + * --> default enable non-Qos data sequence number. 2010.06.23. * by tynli. * (2) Enable HW SEQ control for beacon packet, because we use * Hw beacon. @@ -2777,7 +2777,7 @@ void rtl8723b_fill_fake_txdesc( SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen); /* Buffer size + command header */ SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ - /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */ + /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error value by Hw. */ if (IsPsPoll) { SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1); } else { @@ -3406,7 +3406,7 @@ void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) /* polling bit, and No Write enable, and address */ ulCommand = CAM_CONTENT_COUNT*ucIndex+i; ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE; - /* write content 0 is equall to mark invalid */ + /* write content 0 is equal to mark as invalid */ rtw_write32(padapter, WCAMI, ulContent); /* mdelay(40); */ rtw_write32(padapter, RWCAM, ulCommand); /* mdelay(40); */ } diff --git a/drivers/staging/rts5208/ms.c b/drivers/staging/rts5208/ms.c index 14449f8afad5..bfeb5873bf3b 100644 --- a/drivers/staging/rts5208/ms.c +++ b/drivers/staging/rts5208/ms.c @@ -1768,6 +1768,8 @@ static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, SYSTEM_PARAM, (6 + MS_EXTRA_SIZE)); + if (retval != STATUS_SUCCESS) + return STATUS_FAIL; ms_set_err_code(chip, MS_NO_ERROR); diff --git a/drivers/staging/vc04_services/Makefile b/drivers/staging/vc04_services/Makefile index 1fd191e2e2a5..44794bdf6173 100644 --- a/drivers/staging/vc04_services/Makefile +++ b/drivers/staging/vc04_services/Makefile @@ -15,5 +15,3 @@ obj-$(CONFIG_SND_BCM2835) += bcm2835-audio/ obj-$(CONFIG_VIDEO_BCM2835) += bcm2835-camera/ obj-$(CONFIG_BCM2835_VCHIQ_MMAL) += vchiq-mmal/ -ccflags-y += -I $(srctree)/$(src)/include - diff --git a/drivers/staging/vc04_services/bcm2835-audio/Makefile b/drivers/staging/vc04_services/bcm2835-audio/Makefile index d59fe4dde615..01ceebdf88e7 100644 --- a/drivers/staging/vc04_services/bcm2835-audio/Makefile +++ b/drivers/staging/vc04_services/bcm2835-audio/Makefile @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o - -ccflags-y += -I $(srctree)/$(src)/../include -D__VCCOREVER__=0x04000000 diff --git a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c index f4c2c9506d86..d74110ca17ab 100644 --- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c +++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-vchiq.c @@ -91,17 +91,17 @@ static int bcm2835_audio_send_simple(struct bcm2835_audio_instance *instance, return bcm2835_audio_send_msg(instance, &m, wait); } -static enum vchiq_status audio_vchi_callback(struct vchiq_instance *vchiq_instance, - enum vchiq_reason reason, - struct vchiq_header *header, - unsigned int handle, void *userdata) +static int audio_vchi_callback(struct vchiq_instance *vchiq_instance, + enum vchiq_reason reason, + struct vchiq_header *header, + unsigned int handle, void *userdata) { struct bcm2835_audio_instance *instance = vchiq_get_service_userdata(vchiq_instance, handle); struct vc_audio_msg *m; if (reason != VCHIQ_MESSAGE_AVAILABLE) - return VCHIQ_SUCCESS; + return 0; m = (void *)header->data; if (m->type == VC_AUDIO_MSG_TYPE_RESULT) { @@ -119,7 +119,7 @@ static enum vchiq_status audio_vchi_callback(struct vchiq_instance *vchiq_instan } vchiq_release_message(vchiq_instance, instance->service_handle, header); - return VCHIQ_SUCCESS; + return 0; } static int diff --git a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h index 38b7451d77b2..0a81383c475a 100644 --- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h +++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h @@ -6,11 +6,12 @@ #include #include -#include #include #include #include +#include "../include/linux/raspberrypi/vchiq.h" + #define MAX_SUBSTREAMS (8) #define AVAIL_SUBSTREAMS_MASK (0xff) diff --git a/drivers/staging/vc04_services/bcm2835-camera/Makefile b/drivers/staging/vc04_services/bcm2835-camera/Makefile index 3a76d6ade428..203b93899b20 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/Makefile +++ b/drivers/staging/vc04_services/bcm2835-camera/Makefile @@ -4,8 +4,3 @@ bcm2835-v4l2-$(CONFIG_VIDEO_BCM2835) := \ controls.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835-v4l2.o - -ccflags-y += \ - -I $(srctree)/$(src)/.. \ - -I $(srctree)/$(src)/../vchiq-mmal/ \ - -D__VCCOREVER__=0x04000000 diff --git a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c index 797ebe2a973a..4f81765912ea 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c +++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c @@ -26,11 +26,11 @@ #include #include -#include "mmal-common.h" -#include "mmal-encodings.h" -#include "mmal-vchiq.h" -#include "mmal-msg.h" -#include "mmal-parameters.h" +#include "../vchiq-mmal/mmal-common.h" +#include "../vchiq-mmal/mmal-encodings.h" +#include "../vchiq-mmal/mmal-vchiq.h" +#include "../vchiq-mmal/mmal-msg.h" +#include "../vchiq-mmal/mmal-parameters.h" #include "bcm2835-camera.h" #define MIN_WIDTH 32 diff --git a/drivers/staging/vc04_services/bcm2835-camera/controls.c b/drivers/staging/vc04_services/bcm2835-camera/controls.c index 5644d1d457b9..6bce45925bf1 100644 --- a/drivers/staging/vc04_services/bcm2835-camera/controls.c +++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c @@ -23,9 +23,9 @@ #include #include -#include "mmal-common.h" -#include "mmal-vchiq.h" -#include "mmal-parameters.h" +#include "../vchiq-mmal/mmal-common.h" +#include "../vchiq-mmal/mmal-vchiq.h" +#include "../vchiq-mmal/mmal-parameters.h" #include "bcm2835-camera.h" /* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0. diff --git a/drivers/staging/vc04_services/include/linux/raspberrypi/vchiq.h b/drivers/staging/vc04_services/include/linux/raspberrypi/vchiq.h index 690ab7165b2c..66965da11443 100644 --- a/drivers/staging/vc04_services/include/linux/raspberrypi/vchiq.h +++ b/drivers/staging/vc04_services/include/linux/raspberrypi/vchiq.h @@ -17,12 +17,6 @@ enum vchiq_reason { VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */ }; -enum vchiq_status { - VCHIQ_ERROR = -1, - VCHIQ_SUCCESS = 0, - VCHIQ_RETRY = 1 -}; - enum vchiq_bulk_mode { VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_MODE_BLOCKING, @@ -57,11 +51,11 @@ struct vchiq_instance; struct vchiq_service_base { int fourcc; - enum vchiq_status (*callback)(struct vchiq_instance *instance, - enum vchiq_reason reason, - struct vchiq_header *header, - unsigned int handle, - void *bulk_userdata); + int (*callback)(struct vchiq_instance *instance, + enum vchiq_reason reason, + struct vchiq_header *header, + unsigned int handle, + void *bulk_userdata); void *userdata; }; @@ -74,11 +68,11 @@ struct vchiq_completion_data_kernel { struct vchiq_service_params_kernel { int fourcc; - enum vchiq_status (*callback)(struct vchiq_instance *instance, - enum vchiq_reason reason, - struct vchiq_header *header, - unsigned int handle, - void *bulk_userdata); + int (*callback)(struct vchiq_instance *instance, + enum vchiq_reason reason, + struct vchiq_header *header, + unsigned int handle, + void *bulk_userdata); void *userdata; short version; /* Increment for non-trivial changes */ short version_min; /* Update for incompatible changes */ @@ -87,32 +81,31 @@ struct vchiq_service_params_kernel { struct vchiq_instance; extern int vchiq_initialise(struct vchiq_instance **pinstance); -extern enum vchiq_status vchiq_shutdown(struct vchiq_instance *instance); -extern enum vchiq_status vchiq_connect(struct vchiq_instance *instance); -extern enum vchiq_status vchiq_open_service(struct vchiq_instance *instance, - const struct vchiq_service_params_kernel *params, - unsigned int *pservice); -extern enum vchiq_status vchiq_close_service(struct vchiq_instance *instance, - unsigned int service); -extern enum vchiq_status vchiq_use_service(struct vchiq_instance *instance, unsigned int service); -extern enum vchiq_status vchiq_release_service(struct vchiq_instance *instance, - unsigned int service); +extern int vchiq_shutdown(struct vchiq_instance *instance); +extern int vchiq_connect(struct vchiq_instance *instance); +extern int vchiq_open_service(struct vchiq_instance *instance, + const struct vchiq_service_params_kernel *params, + unsigned int *pservice); +extern int vchiq_close_service(struct vchiq_instance *instance, + unsigned int service); +extern int vchiq_use_service(struct vchiq_instance *instance, unsigned int service); +extern int vchiq_release_service(struct vchiq_instance *instance, + unsigned int service); extern void vchiq_msg_queue_push(struct vchiq_instance *instance, unsigned int handle, struct vchiq_header *header); extern void vchiq_release_message(struct vchiq_instance *instance, unsigned int service, struct vchiq_header *header); extern int vchiq_queue_kernel_message(struct vchiq_instance *instance, unsigned int handle, void *data, unsigned int size); -extern enum vchiq_status vchiq_bulk_transmit(struct vchiq_instance *instance, unsigned int service, - const void *data, unsigned int size, void *userdata, - enum vchiq_bulk_mode mode); -extern enum vchiq_status vchiq_bulk_receive(struct vchiq_instance *instance, unsigned int service, - void *data, unsigned int size, void *userdata, - enum vchiq_bulk_mode mode); +extern int vchiq_bulk_transmit(struct vchiq_instance *instance, unsigned int service, + const void *data, unsigned int size, void *userdata, + enum vchiq_bulk_mode mode); +extern int vchiq_bulk_receive(struct vchiq_instance *instance, unsigned int service, + void *data, unsigned int size, void *userdata, + enum vchiq_bulk_mode mode); extern void *vchiq_get_service_userdata(struct vchiq_instance *instance, unsigned int service); -extern enum vchiq_status vchiq_get_peer_version(struct vchiq_instance *instance, - unsigned int handle, - short *peer_version); +extern int vchiq_get_peer_version(struct vchiq_instance *instance, unsigned int handle, + short *peer_version); extern struct vchiq_header *vchiq_msg_hold(struct vchiq_instance *instance, unsigned int handle); #endif /* VCHIQ_H */ diff --git a/drivers/staging/vc04_services/interface/TODO b/drivers/staging/vc04_services/interface/TODO index 97085a0b3223..6d9d4a800aa7 100644 --- a/drivers/staging/vc04_services/interface/TODO +++ b/drivers/staging/vc04_services/interface/TODO @@ -40,11 +40,6 @@ beneficial to go over all of them and, if correct, comment on their merits. Extra points to whomever confidently reviews the remote_event_*() family of functions. -* Get rid of custom function return values - -Most functions use a custom set of return values, we should force proper Linux -error numbers. Special care is needed for VCHIQ_RETRY. - * Reformat core code with more sane indentations The code follows the 80 characters limitation yet tends to go 3 or 4 levels of diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c index dc33490ba7fb..cddcd3c596c9 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c @@ -151,7 +151,7 @@ static struct semaphore g_free_fragments_sema; static DEFINE_SEMAPHORE(g_free_fragments_mutex); -static enum vchiq_status +static int vchiq_blocking_bulk_transfer(struct vchiq_instance *instance, unsigned int handle, void *data, unsigned int size, enum vchiq_bulk_dir dir); @@ -501,7 +501,7 @@ int vchiq_platform_init(struct platform_device *pdev, struct vchiq_state *state) vchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size); if (!vchiq_slot_zero) - return -EINVAL; + return -ENOMEM; vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = (int)slot_phys + slot_mem_size; @@ -541,9 +541,15 @@ int vchiq_platform_init(struct platform_device *pdev, struct vchiq_state *state) channelbase = slot_phys; err = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT, &channelbase, sizeof(channelbase)); - if (err || channelbase) { - dev_err(dev, "failed to set channelbase\n"); - return err ? : -ENXIO; + if (err) { + dev_err(dev, "failed to send firmware property: %d\n", err); + return err; + } + + if (channelbase) { + dev_err(dev, "failed to set channelbase (response: %x)\n", + channelbase); + return -ENXIO; } vchiq_log_info(vchiq_arm_log_level, "vchiq_init - done (slots %pK, phys %pad)", @@ -722,13 +728,13 @@ void free_bulk_waiter(struct vchiq_instance *instance) } } -enum vchiq_status vchiq_shutdown(struct vchiq_instance *instance) +int vchiq_shutdown(struct vchiq_instance *instance) { - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; struct vchiq_state *state = instance->state; if (mutex_lock_killable(&state->mutex)) - return VCHIQ_RETRY; + return -EAGAIN; /* Remove all services */ vchiq_shutdown_internal(state, instance); @@ -749,19 +755,19 @@ static int vchiq_is_connected(struct vchiq_instance *instance) return instance->connected; } -enum vchiq_status vchiq_connect(struct vchiq_instance *instance) +int vchiq_connect(struct vchiq_instance *instance) { - enum vchiq_status status; + int status; struct vchiq_state *state = instance->state; if (mutex_lock_killable(&state->mutex)) { vchiq_log_trace(vchiq_core_log_level, "%s: call to mutex_lock failed", __func__); - status = VCHIQ_RETRY; + status = -EAGAIN; goto failed; } status = vchiq_connect_internal(state, instance); - if (status == VCHIQ_SUCCESS) + if (!status) instance->connected = 1; mutex_unlock(&state->mutex); @@ -773,12 +779,12 @@ failed: } EXPORT_SYMBOL(vchiq_connect); -static enum vchiq_status +static int vchiq_add_service(struct vchiq_instance *instance, const struct vchiq_service_params_kernel *params, unsigned int *phandle) { - enum vchiq_status status; + int status; struct vchiq_state *state = instance->state; struct vchiq_service *service = NULL; int srvstate; @@ -793,9 +799,9 @@ vchiq_add_service(struct vchiq_instance *instance, if (service) { *phandle = service->handle; - status = VCHIQ_SUCCESS; + status = 0; } else { - status = VCHIQ_ERROR; + status = -EINVAL; } vchiq_log_trace(vchiq_core_log_level, "%s(%p): returning %d", __func__, instance, status); @@ -803,12 +809,12 @@ vchiq_add_service(struct vchiq_instance *instance, return status; } -enum vchiq_status +int vchiq_open_service(struct vchiq_instance *instance, const struct vchiq_service_params_kernel *params, unsigned int *phandle) { - enum vchiq_status status = VCHIQ_ERROR; + int status = -EINVAL; struct vchiq_state *state = instance->state; struct vchiq_service *service = NULL; @@ -822,7 +828,7 @@ vchiq_open_service(struct vchiq_instance *instance, if (service) { *phandle = service->handle; status = vchiq_open_service_internal(service, current->pid); - if (status != VCHIQ_SUCCESS) { + if (status) { vchiq_remove_service(instance, service->handle); *phandle = VCHIQ_SERVICE_HANDLE_INVALID; } @@ -835,11 +841,11 @@ failed: } EXPORT_SYMBOL(vchiq_open_service); -enum vchiq_status +int vchiq_bulk_transmit(struct vchiq_instance *instance, unsigned int handle, const void *data, unsigned int size, void *userdata, enum vchiq_bulk_mode mode) { - enum vchiq_status status; + int status; while (1) { switch (mode) { @@ -855,15 +861,15 @@ vchiq_bulk_transmit(struct vchiq_instance *instance, unsigned int handle, const VCHIQ_BULK_TRANSMIT); break; default: - return VCHIQ_ERROR; + return -EINVAL; } /* - * vchiq_*_bulk_transfer() may return VCHIQ_RETRY, so we need + * vchiq_*_bulk_transfer() may return -EAGAIN, so we need * to implement a retry mechanism since this function is * supposed to block until queued */ - if (status != VCHIQ_RETRY) + if (status != -EAGAIN) break; msleep(1); @@ -873,11 +879,11 @@ vchiq_bulk_transmit(struct vchiq_instance *instance, unsigned int handle, const } EXPORT_SYMBOL(vchiq_bulk_transmit); -enum vchiq_status vchiq_bulk_receive(struct vchiq_instance *instance, unsigned int handle, - void *data, unsigned int size, void *userdata, - enum vchiq_bulk_mode mode) +int vchiq_bulk_receive(struct vchiq_instance *instance, unsigned int handle, + void *data, unsigned int size, void *userdata, + enum vchiq_bulk_mode mode) { - enum vchiq_status status; + int status; while (1) { switch (mode) { @@ -892,15 +898,15 @@ enum vchiq_status vchiq_bulk_receive(struct vchiq_instance *instance, unsigned i VCHIQ_BULK_RECEIVE); break; default: - return VCHIQ_ERROR; + return -EINVAL; } /* - * vchiq_*_bulk_transfer() may return VCHIQ_RETRY, so we need + * vchiq_*_bulk_transfer() may return -EAGAIN, so we need * to implement a retry mechanism since this function is * supposed to block until queued */ - if (status != VCHIQ_RETRY) + if (status != -EAGAIN) break; msleep(1); @@ -910,17 +916,17 @@ enum vchiq_status vchiq_bulk_receive(struct vchiq_instance *instance, unsigned i } EXPORT_SYMBOL(vchiq_bulk_receive); -static enum vchiq_status +static int vchiq_blocking_bulk_transfer(struct vchiq_instance *instance, unsigned int handle, void *data, unsigned int size, enum vchiq_bulk_dir dir) { struct vchiq_service *service; - enum vchiq_status status; + int status; struct bulk_waiter_node *waiter = NULL, *iter; service = find_service_by_handle(instance, handle); if (!service) - return VCHIQ_ERROR; + return -EINVAL; vchiq_service_put(service); @@ -954,14 +960,14 @@ vchiq_blocking_bulk_transfer(struct vchiq_instance *instance, unsigned int handl waiter = kzalloc(sizeof(*waiter), GFP_KERNEL); if (!waiter) { vchiq_log_error(vchiq_core_log_level, "%s - out of memory", __func__); - return VCHIQ_ERROR; + return -ENOMEM; } } status = vchiq_bulk_transfer(instance, handle, data, NULL, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING, dir); - if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || !waiter->bulk_waiter.bulk) { + if ((status != -EAGAIN) || fatal_signal_pending(current) || !waiter->bulk_waiter.bulk) { struct vchiq_bulk *bulk = waiter->bulk_waiter.bulk; if (bulk) { @@ -983,7 +989,7 @@ vchiq_blocking_bulk_transfer(struct vchiq_instance *instance, unsigned int handl return status; } -static enum vchiq_status +static int add_completion(struct vchiq_instance *instance, enum vchiq_reason reason, struct vchiq_header *header, struct user_service *user_service, void *bulk_userdata) @@ -1001,10 +1007,10 @@ add_completion(struct vchiq_instance *instance, enum vchiq_reason reason, DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); if (wait_for_completion_interruptible(&instance->remove_event)) { vchiq_log_info(vchiq_arm_log_level, "service_callback interrupted"); - return VCHIQ_RETRY; + return -EAGAIN; } else if (instance->closing) { vchiq_log_info(vchiq_arm_log_level, "service_callback closing"); - return VCHIQ_SUCCESS; + return 0; } DEBUG_TRACE(SERVICE_CALLBACK_LINE); } @@ -1041,10 +1047,10 @@ add_completion(struct vchiq_instance *instance, enum vchiq_reason reason, complete(&instance->insert_event); - return VCHIQ_SUCCESS; + return 0; } -enum vchiq_status +int service_callback(struct vchiq_instance *instance, enum vchiq_reason reason, struct vchiq_header *header, unsigned int handle, void *bulk_userdata) { @@ -1066,14 +1072,14 @@ service_callback(struct vchiq_instance *instance, enum vchiq_reason reason, service = handle_to_service(instance, handle); if (WARN_ON(!service)) { rcu_read_unlock(); - return VCHIQ_SUCCESS; + return 0; } user_service = (struct user_service *)service->base.userdata; if (!instance || instance->closing) { rcu_read_unlock(); - return VCHIQ_SUCCESS; + return 0; } /* @@ -1103,14 +1109,14 @@ service_callback(struct vchiq_instance *instance, enum vchiq_reason reason, */ if ((user_service->message_available_pos - instance->completion_remove) < 0) { - enum vchiq_status status; + int status; vchiq_log_info(vchiq_arm_log_level, "Inserting extra MESSAGE_AVAILABLE"); DEBUG_TRACE(SERVICE_CALLBACK_LINE); status = add_completion(instance, reason, NULL, user_service, bulk_userdata); - if (status != VCHIQ_SUCCESS) { + if (status) { DEBUG_TRACE(SERVICE_CALLBACK_LINE); vchiq_service_put(service); return status; @@ -1122,12 +1128,12 @@ service_callback(struct vchiq_instance *instance, enum vchiq_reason reason, vchiq_log_info(vchiq_arm_log_level, "%s interrupted", __func__); DEBUG_TRACE(SERVICE_CALLBACK_LINE); vchiq_service_put(service); - return VCHIQ_RETRY; + return -EAGAIN; } else if (instance->closing) { vchiq_log_info(vchiq_arm_log_level, "%s closing", __func__); DEBUG_TRACE(SERVICE_CALLBACK_LINE); vchiq_service_put(service); - return VCHIQ_ERROR; + return -EINVAL; } DEBUG_TRACE(SERVICE_CALLBACK_LINE); spin_lock(&msg_queue_spinlock); @@ -1158,7 +1164,7 @@ service_callback(struct vchiq_instance *instance, enum vchiq_reason reason, vchiq_service_put(service); if (skip_completion) - return VCHIQ_SUCCESS; + return 0; return add_completion(instance, reason, header, user_service, bulk_userdata); @@ -1314,7 +1320,7 @@ vchiq_get_state(void) * Autosuspend related functionality */ -static enum vchiq_status +static int vchiq_keepalive_vchiq_callback(struct vchiq_instance *instance, enum vchiq_reason reason, struct vchiq_header *header, @@ -1330,7 +1336,7 @@ vchiq_keepalive_thread_func(void *v) struct vchiq_state *state = (struct vchiq_state *)v; struct vchiq_arm_state *arm_state = vchiq_platform_get_arm_state(state); - enum vchiq_status status; + int status; struct vchiq_instance *instance; unsigned int ka_handle; int ret; @@ -1350,14 +1356,14 @@ vchiq_keepalive_thread_func(void *v) } status = vchiq_connect(instance); - if (status != VCHIQ_SUCCESS) { + if (status) { vchiq_log_error(vchiq_susp_log_level, "%s vchiq_connect failed %d", __func__, status); goto shutdown; } status = vchiq_add_service(instance, ¶ms, &ka_handle); - if (status != VCHIQ_SUCCESS) { + if (status) { vchiq_log_error(vchiq_susp_log_level, "%s vchiq_open_service failed %d", __func__, status); goto shutdown; @@ -1386,14 +1392,14 @@ vchiq_keepalive_thread_func(void *v) while (uc--) { atomic_inc(&arm_state->ka_use_ack_count); status = vchiq_use_service(instance, ka_handle); - if (status != VCHIQ_SUCCESS) { + if (status) { vchiq_log_error(vchiq_susp_log_level, "%s vchiq_use_service error %d", __func__, status); } } while (rc--) { status = vchiq_release_service(instance, ka_handle); - if (status != VCHIQ_SUCCESS) { + if (status) { vchiq_log_error(vchiq_susp_log_level, "%s vchiq_release_service error %d", __func__, status); @@ -1446,13 +1452,13 @@ vchiq_use_internal(struct vchiq_state *state, struct vchiq_service *service, write_unlock_bh(&arm_state->susp_res_lock); if (!ret) { - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); - while (ack_cnt && (status == VCHIQ_SUCCESS)) { + while (ack_cnt && !status) { /* Send the use notify to videocore */ status = vchiq_send_remote_use_active(state); - if (status == VCHIQ_SUCCESS) + if (!status) ack_cnt--; else atomic_add(ack_cnt, &arm_state->ka_use_ack_count); @@ -1587,10 +1593,10 @@ vchiq_instance_set_trace(struct vchiq_instance *instance, int trace) instance->trace = (trace != 0); } -enum vchiq_status +int vchiq_use_service(struct vchiq_instance *instance, unsigned int handle) { - enum vchiq_status ret = VCHIQ_ERROR; + int ret = -EINVAL; struct vchiq_service *service = find_service_by_handle(instance, handle); if (service) { @@ -1601,10 +1607,10 @@ vchiq_use_service(struct vchiq_instance *instance, unsigned int handle) } EXPORT_SYMBOL(vchiq_use_service); -enum vchiq_status +int vchiq_release_service(struct vchiq_instance *instance, unsigned int handle) { - enum vchiq_status ret = VCHIQ_ERROR; + int ret = -EINVAL; struct vchiq_service *service = find_service_by_handle(instance, handle); if (service) { @@ -1695,11 +1701,11 @@ vchiq_dump_service_use_state(struct vchiq_state *state) kfree(service_data); } -enum vchiq_status +int vchiq_check_service(struct vchiq_service *service) { struct vchiq_arm_state *arm_state; - enum vchiq_status ret = VCHIQ_ERROR; + int ret = -EINVAL; if (!service || !service->state) goto out; @@ -1708,10 +1714,10 @@ vchiq_check_service(struct vchiq_service *service) read_lock_bh(&arm_state->susp_res_lock); if (service->service_use_count) - ret = VCHIQ_SUCCESS; + ret = 0; read_unlock_bh(&arm_state->susp_res_lock); - if (ret == VCHIQ_ERROR) { + if (ret) { vchiq_log_error(vchiq_susp_log_level, "%s ERROR - %c%c%c%c:%d service count %d, state count %d", __func__, VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id, diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h index cd20eb18f275..2fb31f9b527f 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h @@ -85,13 +85,13 @@ extern struct vchiq_state g_state; extern struct vchiq_state * vchiq_get_state(void); -enum vchiq_status +int vchiq_use_service(struct vchiq_instance *instance, unsigned int handle); -extern enum vchiq_status +extern int vchiq_release_service(struct vchiq_instance *instance, unsigned int handle); -extern enum vchiq_status +extern int vchiq_check_service(struct vchiq_service *service); extern void @@ -137,7 +137,7 @@ static inline int vchiq_register_chrdev(struct device *parent) { return 0; } #endif /* IS_ENABLED(CONFIG_VCHIQ_CDEV) */ -extern enum vchiq_status +extern int service_callback(struct vchiq_instance *vchiq_instance, enum vchiq_reason reason, struct vchiq_header *header, unsigned int handle, void *bulk_userdata); diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c index 45ed30bfdbf5..596894338cb4 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c @@ -463,22 +463,22 @@ mark_service_closing(struct vchiq_service *service) mark_service_closing_internal(service, 0); } -static inline enum vchiq_status +static inline int make_service_callback(struct vchiq_service *service, enum vchiq_reason reason, struct vchiq_header *header, void *bulk_userdata) { - enum vchiq_status status; + int status; vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %pK, %pK)", service->state->id, service->localport, reason_names[reason], header, bulk_userdata); status = service->base.callback(service->instance, reason, header, service->handle, bulk_userdata); - if (status == VCHIQ_ERROR) { + if (status && (status != -EAGAIN)) { vchiq_log_warning(vchiq_core_log_level, "%d: ignoring ERROR from callback to service %x", service->state->id, service->handle); - status = VCHIQ_SUCCESS; + status = 0; } if (reason != VCHIQ_MESSAGE_AVAILABLE) @@ -498,6 +498,7 @@ vchiq_set_conn_state(struct vchiq_state *state, enum vchiq_connstate newstate) vchiq_platform_conn_state_changed(state, oldstate, newstate); } +/* This initialises a single remote_event, and the associated wait_queue. */ static inline void remote_event_create(wait_queue_head_t *wq, struct remote_event *event) { @@ -536,6 +537,10 @@ remote_event_wait(wait_queue_head_t *wq, struct remote_event *event) return 1; } +/* + * Acknowledge that the event has been signalled, and wake any waiters. Usually + * called as a result of the doorbell being rung. + */ static inline void remote_event_signal_local(wait_queue_head_t *wq, struct remote_event *event) { @@ -544,6 +549,7 @@ remote_event_signal_local(wait_queue_head_t *wq, struct remote_event *event) wake_up_all(wq); } +/* Check if a single event has been signalled, waking the waiters if it has. */ static inline void remote_event_poll(wait_queue_head_t *wq, struct remote_event *event) { @@ -551,6 +557,10 @@ remote_event_poll(wait_queue_head_t *wq, struct remote_event *event) remote_event_signal_local(wq, event); } +/* + * VCHIQ used a small, fixed number of remote events. It is simplest to + * enumerate them here for polling. + */ void remote_event_pollall(struct vchiq_state *state) { @@ -900,7 +910,7 @@ copy_message_data(ssize_t (*copy_callback)(void *context, void *dest, size_t off } /* Called by the slot handler and application threads */ -static enum vchiq_status +static int queue_message(struct vchiq_state *state, struct vchiq_service *service, int msgid, ssize_t (*copy_callback)(void *context, void *dest, @@ -922,7 +932,7 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, if (!(flags & QMFLAGS_NO_MUTEX_LOCK) && mutex_lock_killable(&state->slot_mutex)) - return VCHIQ_RETRY; + return -EAGAIN; if (type == VCHIQ_MSG_DATA) { int tx_end_index; @@ -930,7 +940,7 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, if (!service) { WARN(1, "%s: service is NULL\n", __func__); mutex_unlock(&state->slot_mutex); - return VCHIQ_ERROR; + return -EINVAL; } WARN_ON(flags & (QMFLAGS_NO_MUTEX_LOCK | @@ -939,7 +949,7 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, if (service->closing) { /* The service has been closed */ mutex_unlock(&state->slot_mutex); - return VCHIQ_ERROR; + return -EHOSTDOWN; } quota = &state->service_quotas[service->localport]; @@ -963,7 +973,7 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, mutex_unlock(&state->slot_mutex); if (wait_for_completion_interruptible(&state->data_quota_event)) - return VCHIQ_RETRY; + return -EAGAIN; mutex_lock(&state->slot_mutex); spin_lock("a_spinlock); @@ -987,15 +997,15 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, VCHIQ_SERVICE_STATS_INC(service, quota_stalls); mutex_unlock(&state->slot_mutex); if (wait_for_completion_interruptible("a->quota_event)) - return VCHIQ_RETRY; + return -EAGAIN; if (service->closing) - return VCHIQ_ERROR; + return -EHOSTDOWN; if (mutex_lock_killable(&state->slot_mutex)) - return VCHIQ_RETRY; + return -EAGAIN; if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { /* The service has been closed */ mutex_unlock(&state->slot_mutex); - return VCHIQ_ERROR; + return -EHOSTDOWN; } spin_lock("a_spinlock); tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); @@ -1015,7 +1025,7 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, */ if (!(flags & QMFLAGS_NO_MUTEX_LOCK)) mutex_unlock(&state->slot_mutex); - return VCHIQ_RETRY; + return -EAGAIN; } if (type == VCHIQ_MSG_DATA) { @@ -1037,7 +1047,7 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, if (callback_result < 0) { mutex_unlock(&state->slot_mutex); VCHIQ_SERVICE_STATS_INC(service, error_count); - return VCHIQ_ERROR; + return -EINVAL; } if (SRVTRACE_ENABLED(service, @@ -1135,11 +1145,11 @@ queue_message(struct vchiq_state *state, struct vchiq_service *service, remote_event_signal(&state->remote->trigger); - return VCHIQ_SUCCESS; + return 0; } /* Called by the slot handler and application threads */ -static enum vchiq_status +static int queue_message_sync(struct vchiq_state *state, struct vchiq_service *service, int msgid, ssize_t (*copy_callback)(void *context, void *dest, @@ -1154,7 +1164,7 @@ queue_message_sync(struct vchiq_state *state, struct vchiq_service *service, if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME && mutex_lock_killable(&state->sync_mutex)) - return VCHIQ_RETRY; + return -EAGAIN; remote_event_wait(&state->sync_release_event, &local->sync_release); @@ -1185,7 +1195,7 @@ queue_message_sync(struct vchiq_state *state, struct vchiq_service *service, if (callback_result < 0) { mutex_unlock(&state->slot_mutex); VCHIQ_SERVICE_STATS_INC(service, error_count); - return VCHIQ_ERROR; + return -EINVAL; } if (service) { @@ -1223,7 +1233,7 @@ queue_message_sync(struct vchiq_state *state, struct vchiq_service *service, if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) mutex_unlock(&state->sync_mutex); - return VCHIQ_SUCCESS; + return 0; } static inline void @@ -1299,11 +1309,11 @@ get_bulk_reason(struct vchiq_bulk *bulk) } /* Called by the slot handler - don't hold the bulk mutex */ -static enum vchiq_status +static int notify_bulks(struct vchiq_service *service, struct vchiq_bulk_queue *queue, int retry_poll) { - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; vchiq_log_trace(vchiq_core_log_level, "%d: nb:%d %cx - p=%x rn=%x r=%x", service->state->id, service->localport, (queue == &service->bulk_tx) ? 't' : 'r', @@ -1348,7 +1358,7 @@ notify_bulks(struct vchiq_service *service, struct vchiq_bulk_queue *queue, get_bulk_reason(bulk); status = make_service_callback(service, reason, NULL, bulk->userdata); - if (status == VCHIQ_RETRY) + if (status == -EAGAIN) break; } } @@ -1357,9 +1367,9 @@ notify_bulks(struct vchiq_service *service, struct vchiq_bulk_queue *queue, complete(&service->bulk_remove_event); } if (!retry_poll) - status = VCHIQ_SUCCESS; + status = 0; - if (status == VCHIQ_RETRY) + if (status == -EAGAIN) request_poll(service->state, service, (queue == &service->bulk_tx) ? VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); @@ -1398,13 +1408,12 @@ poll_services_of_group(struct vchiq_state *state, int group) */ service->public_fourcc = VCHIQ_FOURCC_INVALID; - if (vchiq_close_service_internal(service, NO_CLOSE_RECVD) != - VCHIQ_SUCCESS) + if (vchiq_close_service_internal(service, NO_CLOSE_RECVD)) request_poll(state, service, VCHIQ_POLL_REMOVE); } else if (service_flags & BIT(VCHIQ_POLL_TERMINATE)) { vchiq_log_info(vchiq_core_log_level, "%d: ps - terminate %d<->%d", state->id, service->localport, service->remoteport); - if (vchiq_close_service_internal(service, NO_CLOSE_RECVD) != VCHIQ_SUCCESS) + if (vchiq_close_service_internal(service, NO_CLOSE_RECVD)) request_poll(state, service, VCHIQ_POLL_TERMINATE); } if (service_flags & BIT(VCHIQ_POLL_TXNOTIFY)) @@ -1527,14 +1536,14 @@ parse_open(struct vchiq_state *state, struct vchiq_header *header) /* Acknowledge the OPEN */ if (service->sync) { if (queue_message_sync(state, NULL, openack_id, memcpy_copy_callback, - &ack_payload, sizeof(ack_payload), 0) == VCHIQ_RETRY) + &ack_payload, sizeof(ack_payload), 0) == -EAGAIN) goto bail_not_ready; /* The service is now open */ set_service_state(service, VCHIQ_SRVSTATE_OPENSYNC); } else { if (queue_message(state, NULL, openack_id, memcpy_copy_callback, - &ack_payload, sizeof(ack_payload), 0) == VCHIQ_RETRY) + &ack_payload, sizeof(ack_payload), 0) == -EAGAIN) goto bail_not_ready; /* The service is now open */ @@ -1549,7 +1558,7 @@ parse_open(struct vchiq_state *state, struct vchiq_header *header) fail_open: /* No available service, or an invalid request - send a CLOSE */ if (queue_message(state, NULL, MAKE_CLOSE(0, VCHIQ_MSG_SRCPORT(msgid)), - NULL, NULL, 0, 0) == VCHIQ_RETRY) + NULL, NULL, 0, 0) == -EAGAIN) goto bail_not_ready; return 1; @@ -1688,7 +1697,7 @@ parse_message(struct vchiq_state *state, struct vchiq_header *header) mark_service_closing_internal(service, 1); - if (vchiq_close_service_internal(service, CLOSE_RECVD) == VCHIQ_RETRY) + if (vchiq_close_service_internal(service, CLOSE_RECVD) == -EAGAIN) goto bail_not_ready; vchiq_log_info(vchiq_core_log_level, "Close Service %c%c%c%c s:%u d:%d", @@ -1705,7 +1714,7 @@ parse_message(struct vchiq_state *state, struct vchiq_header *header) claim_slot(state->rx_info); DEBUG_TRACE(PARSE_LINE); if (make_service_callback(service, VCHIQ_MESSAGE_AVAILABLE, header, - NULL) == VCHIQ_RETRY) { + NULL) == -EAGAIN) { DEBUG_TRACE(PARSE_LINE); goto bail_not_ready; } @@ -1803,7 +1812,7 @@ parse_message(struct vchiq_state *state, struct vchiq_header *header) if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) { /* Send a PAUSE in response */ if (queue_message(state, NULL, MAKE_PAUSE, NULL, NULL, 0, - QMFLAGS_NO_MUTEX_UNLOCK) == VCHIQ_RETRY) + QMFLAGS_NO_MUTEX_UNLOCK) == -EAGAIN) goto bail_not_ready; } /* At this point slot_mutex is held */ @@ -1920,7 +1929,7 @@ handle_poll(struct vchiq_state *state) case VCHIQ_CONNSTATE_PAUSING: if (queue_message(state, NULL, MAKE_PAUSE, NULL, NULL, 0, - QMFLAGS_NO_MUTEX_UNLOCK) != VCHIQ_RETRY) { + QMFLAGS_NO_MUTEX_UNLOCK) != -EAGAIN) { vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSE_SENT); } else { /* Retry later */ @@ -1930,7 +1939,7 @@ handle_poll(struct vchiq_state *state) case VCHIQ_CONNSTATE_RESUMING: if (queue_message(state, NULL, MAKE_RESUME, NULL, NULL, 0, - QMFLAGS_NO_MUTEX_LOCK) != VCHIQ_RETRY) { + QMFLAGS_NO_MUTEX_LOCK) != -EAGAIN) { vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); } else { /* @@ -2086,9 +2095,9 @@ sync_func(void *v) if ((service->remoteport == remoteport) && (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC)) { if (make_service_callback(service, VCHIQ_MESSAGE_AVAILABLE, header, - NULL) == VCHIQ_RETRY) + NULL) == -EAGAIN) vchiq_log_error(vchiq_sync_log_level, - "synchronous callback to service %d returns VCHIQ_RETRY", + "synchronous callback to service %d returns -EAGAIN", localport); } break; @@ -2486,7 +2495,7 @@ vchiq_add_service_internal(struct vchiq_state *state, return service; } -enum vchiq_status +int vchiq_open_service_internal(struct vchiq_service *service, int client_id) { struct vchiq_open_payload payload = { @@ -2495,7 +2504,7 @@ vchiq_open_service_internal(struct vchiq_service *service, int client_id) service->version, service->version_min }; - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; service->client_id = client_id; vchiq_use_service_internal(service); @@ -2506,12 +2515,12 @@ vchiq_open_service_internal(struct vchiq_service *service, int client_id) sizeof(payload), QMFLAGS_IS_BLOCKING); - if (status != VCHIQ_SUCCESS) + if (status) return status; /* Wait for the ACK/NAK */ if (wait_for_completion_interruptible(&service->remove_event)) { - status = VCHIQ_RETRY; + status = -EAGAIN; vchiq_release_service_internal(service); } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) && (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) { @@ -2521,7 +2530,7 @@ vchiq_open_service_internal(struct vchiq_service *service, int client_id) service->state->id, srvstate_names[service->srvstate], kref_read(&service->ref_count)); - status = VCHIQ_ERROR; + status = -EINVAL; VCHIQ_SERVICE_STATS_INC(service, error_count); vchiq_release_service_internal(service); } @@ -2592,7 +2601,7 @@ release_service_messages(struct vchiq_service *service) static int do_abort_bulks(struct vchiq_service *service) { - enum vchiq_status status; + int status; /* Abort any outstanding bulk transfers */ if (mutex_lock_killable(&service->bulk_mutex)) @@ -2602,17 +2611,17 @@ do_abort_bulks(struct vchiq_service *service) mutex_unlock(&service->bulk_mutex); status = notify_bulks(service, &service->bulk_tx, NO_RETRY_POLL); - if (status != VCHIQ_SUCCESS) + if (status) return 0; status = notify_bulks(service, &service->bulk_rx, NO_RETRY_POLL); - return (status == VCHIQ_SUCCESS); + return !status; } -static enum vchiq_status +static int close_service_complete(struct vchiq_service *service, int failstate) { - enum vchiq_status status; + int status; int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); int newstate; @@ -2639,12 +2648,12 @@ close_service_complete(struct vchiq_service *service, int failstate) vchiq_log_error(vchiq_core_log_level, "%s(%x) called in state %s", __func__, service->handle, srvstate_names[service->srvstate]); WARN(1, "%s in unexpected state\n", __func__); - return VCHIQ_ERROR; + return -EINVAL; } status = make_service_callback(service, VCHIQ_SERVICE_CLOSED, NULL, NULL); - if (status != VCHIQ_RETRY) { + if (status != -EAGAIN) { int uc = service->service_use_count; int i; /* Complete the close process */ @@ -2674,11 +2683,11 @@ close_service_complete(struct vchiq_service *service, int failstate) } /* Called by the slot handler */ -enum vchiq_status +int vchiq_close_service_internal(struct vchiq_service *service, int close_recvd) { struct vchiq_state *state = service->state; - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); int close_id = MAKE_CLOSE(service->localport, VCHIQ_MSG_DSTPORT(service->remoteport)); @@ -2696,7 +2705,7 @@ vchiq_close_service_internal(struct vchiq_service *service, int close_recvd) __func__, srvstate_names[service->srvstate]); } else if (is_server) { if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { - status = VCHIQ_ERROR; + status = -EINVAL; } else { service->client_id = 0; service->remoteport = VCHIQ_PORT_FREE; @@ -2725,16 +2734,16 @@ vchiq_close_service_internal(struct vchiq_service *service, int close_recvd) case VCHIQ_SRVSTATE_OPEN: if (close_recvd) { if (!do_abort_bulks(service)) - status = VCHIQ_RETRY; + status = -EAGAIN; } release_service_messages(service); - if (status == VCHIQ_SUCCESS) + if (!status) status = queue_message(state, service, close_id, NULL, NULL, 0, QMFLAGS_NO_MUTEX_UNLOCK); - if (status != VCHIQ_SUCCESS) { + if (status) { if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) mutex_unlock(&state->sync_mutex); break; @@ -2764,11 +2773,11 @@ vchiq_close_service_internal(struct vchiq_service *service, int close_recvd) break; if (!do_abort_bulks(service)) { - status = VCHIQ_RETRY; + status = -EAGAIN; break; } - if (status == VCHIQ_SUCCESS) + if (!status) status = close_service_complete(service, VCHIQ_SRVSTATE_CLOSERECVD); break; @@ -2832,7 +2841,7 @@ vchiq_free_service_internal(struct vchiq_service *service) vchiq_service_put(service); } -enum vchiq_status +int vchiq_connect_internal(struct vchiq_state *state, struct vchiq_instance *instance) { struct vchiq_service *service; @@ -2848,21 +2857,21 @@ vchiq_connect_internal(struct vchiq_state *state, struct vchiq_instance *instanc if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { if (queue_message(state, NULL, MAKE_CONNECT, NULL, NULL, 0, - QMFLAGS_IS_BLOCKING) == VCHIQ_RETRY) - return VCHIQ_RETRY; + QMFLAGS_IS_BLOCKING) == -EAGAIN) + return -EAGAIN; vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING); } if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) { if (wait_for_completion_interruptible(&state->connect)) - return VCHIQ_RETRY; + return -EAGAIN; vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); complete(&state->connect); } - return VCHIQ_SUCCESS; + return 0; } void @@ -2879,15 +2888,15 @@ vchiq_shutdown_internal(struct vchiq_state *state, struct vchiq_instance *instan } } -enum vchiq_status +int vchiq_close_service(struct vchiq_instance *instance, unsigned int handle) { /* Unregister the service */ struct vchiq_service *service = find_service_by_handle(instance, handle); - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; if (!service) - return VCHIQ_ERROR; + return -EINVAL; vchiq_log_info(vchiq_core_log_level, "%d: close_service:%d", service->state->id, service->localport); @@ -2896,14 +2905,14 @@ vchiq_close_service(struct vchiq_instance *instance, unsigned int handle) (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) { vchiq_service_put(service); - return VCHIQ_ERROR; + return -EINVAL; } mark_service_closing(service); if (current == service->state->slot_handler_thread) { status = vchiq_close_service_internal(service, NO_CLOSE_RECVD); - WARN_ON(status == VCHIQ_RETRY); + WARN_ON(status == -EAGAIN); } else { /* Mark the service for termination by the slot handler */ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); @@ -2911,7 +2920,7 @@ vchiq_close_service(struct vchiq_instance *instance, unsigned int handle) while (1) { if (wait_for_completion_interruptible(&service->remove_event)) { - status = VCHIQ_RETRY; + status = -EAGAIN; break; } @@ -2926,10 +2935,10 @@ vchiq_close_service(struct vchiq_instance *instance, unsigned int handle) srvstate_names[service->srvstate]); } - if ((status == VCHIQ_SUCCESS) && + if (!status && (service->srvstate != VCHIQ_SRVSTATE_FREE) && (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) - status = VCHIQ_ERROR; + status = -EINVAL; vchiq_service_put(service); @@ -2937,22 +2946,22 @@ vchiq_close_service(struct vchiq_instance *instance, unsigned int handle) } EXPORT_SYMBOL(vchiq_close_service); -enum vchiq_status +int vchiq_remove_service(struct vchiq_instance *instance, unsigned int handle) { /* Unregister the service */ struct vchiq_service *service = find_service_by_handle(instance, handle); - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; if (!service) - return VCHIQ_ERROR; + return -EINVAL; vchiq_log_info(vchiq_core_log_level, "%d: remove_service:%d", service->state->id, service->localport); if (service->srvstate == VCHIQ_SRVSTATE_FREE) { vchiq_service_put(service); - return VCHIQ_ERROR; + return -EINVAL; } mark_service_closing(service); @@ -2966,14 +2975,14 @@ vchiq_remove_service(struct vchiq_instance *instance, unsigned int handle) service->public_fourcc = VCHIQ_FOURCC_INVALID; status = vchiq_close_service_internal(service, NO_CLOSE_RECVD); - WARN_ON(status == VCHIQ_RETRY); + WARN_ON(status == -EAGAIN); } else { /* Mark the service for removal by the slot handler */ request_poll(service->state, service, VCHIQ_POLL_REMOVE); } while (1) { if (wait_for_completion_interruptible(&service->remove_event)) { - status = VCHIQ_RETRY; + status = -EAGAIN; break; } @@ -2987,9 +2996,8 @@ vchiq_remove_service(struct vchiq_instance *instance, unsigned int handle) srvstate_names[service->srvstate]); } - if ((status == VCHIQ_SUCCESS) && - (service->srvstate != VCHIQ_SRVSTATE_FREE)) - status = VCHIQ_ERROR; + if (!status && (service->srvstate != VCHIQ_SRVSTATE_FREE)) + status = -EINVAL; vchiq_service_put(service); @@ -2998,15 +3006,15 @@ vchiq_remove_service(struct vchiq_instance *instance, unsigned int handle) /* * This function may be called by kernel threads or user threads. - * User threads may receive VCHIQ_RETRY to indicate that a signal has been + * User threads may receive -EAGAIN to indicate that a signal has been * received and the call should be retried after being returned to user * context. * When called in blocking mode, the userdata field points to a bulk_waiter * structure. */ -enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned int handle, - void *offset, void __user *uoffset, int size, void *userdata, - enum vchiq_bulk_mode mode, enum vchiq_bulk_dir dir) +int vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned int handle, + void *offset, void __user *uoffset, int size, void *userdata, + enum vchiq_bulk_mode mode, enum vchiq_bulk_dir dir) { struct vchiq_service *service = find_service_by_handle(instance, handle); struct vchiq_bulk_queue *queue; @@ -3016,7 +3024,7 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; - enum vchiq_status status = VCHIQ_ERROR; + int status = -EINVAL; int payload[2]; if (!service) @@ -3028,7 +3036,7 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned if (!offset && !uoffset) goto error_exit; - if (vchiq_check_service(service) != VCHIQ_SUCCESS) + if (vchiq_check_service(service)) goto error_exit; switch (mode) { @@ -3055,7 +3063,7 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned &service->bulk_tx : &service->bulk_rx; if (mutex_lock_killable(&service->bulk_mutex)) { - status = VCHIQ_RETRY; + status = -EAGAIN; goto error_exit; } @@ -3064,11 +3072,11 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned do { mutex_unlock(&service->bulk_mutex); if (wait_for_completion_interruptible(&service->bulk_remove_event)) { - status = VCHIQ_RETRY; + status = -EAGAIN; goto error_exit; } if (mutex_lock_killable(&service->bulk_mutex)) { - status = VCHIQ_RETRY; + status = -EAGAIN; goto error_exit; } } while (queue->local_insert == queue->remove + @@ -3101,7 +3109,7 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned * claim it here to ensure that isn't happening */ if (mutex_lock_killable(&state->slot_mutex)) { - status = VCHIQ_RETRY; + status = -EAGAIN; goto cancel_bulk_error_exit; } @@ -3121,7 +3129,7 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned QMFLAGS_IS_BLOCKING | QMFLAGS_NO_MUTEX_LOCK | QMFLAGS_NO_MUTEX_UNLOCK); - if (status != VCHIQ_SUCCESS) + if (status) goto unlock_both_error_exit; queue->local_insert++; @@ -3136,14 +3144,14 @@ enum vchiq_status vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned waiting: vchiq_service_put(service); - status = VCHIQ_SUCCESS; + status = 0; if (bulk_waiter) { bulk_waiter->bulk = bulk; if (wait_for_completion_interruptible(&bulk_waiter->event)) - status = VCHIQ_RETRY; + status = -EAGAIN; else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED) - status = VCHIQ_ERROR; + status = -EINVAL; } return status; @@ -3161,7 +3169,7 @@ error_exit: return status; } -enum vchiq_status +int vchiq_queue_message(struct vchiq_instance *instance, unsigned int handle, ssize_t (*copy_callback)(void *context, void *dest, size_t offset, size_t maxsize), @@ -3169,13 +3177,13 @@ vchiq_queue_message(struct vchiq_instance *instance, unsigned int handle, size_t size) { struct vchiq_service *service = find_service_by_handle(instance, handle); - enum vchiq_status status = VCHIQ_ERROR; + int status = -EINVAL; int data_id; if (!service) goto error_exit; - if (vchiq_check_service(service) != VCHIQ_SUCCESS) + if (vchiq_check_service(service)) goto error_exit; if (!size) { @@ -3200,7 +3208,7 @@ vchiq_queue_message(struct vchiq_instance *instance, unsigned int handle, copy_callback, context, size, 1); break; default: - status = VCHIQ_ERROR; + status = -EINVAL; break; } @@ -3214,18 +3222,18 @@ error_exit: int vchiq_queue_kernel_message(struct vchiq_instance *instance, unsigned int handle, void *data, unsigned int size) { - enum vchiq_status status; + int status; while (1) { status = vchiq_queue_message(instance, handle, memcpy_copy_callback, data, size); /* - * vchiq_queue_message() may return VCHIQ_RETRY, so we need to + * vchiq_queue_message() may return -EAGAIN, so we need to * implement a retry mechanism since this function is supposed * to block until queued */ - if (status != VCHIQ_RETRY) + if (status != -EAGAIN) break; msleep(1); @@ -3277,23 +3285,23 @@ release_message_sync(struct vchiq_state *state, struct vchiq_header *header) remote_event_signal(&state->remote->sync_release); } -enum vchiq_status +int vchiq_get_peer_version(struct vchiq_instance *instance, unsigned int handle, short *peer_version) { - enum vchiq_status status = VCHIQ_ERROR; + int status = -EINVAL; struct vchiq_service *service = find_service_by_handle(instance, handle); if (!service) goto exit; - if (vchiq_check_service(service) != VCHIQ_SUCCESS) + if (vchiq_check_service(service)) goto exit; if (!peer_version) goto exit; *peer_version = service->peer_version; - status = VCHIQ_SUCCESS; + status = 0; exit: if (service) @@ -3640,18 +3648,18 @@ vchiq_loud_error_footer(void) "============================================================================"); } -enum vchiq_status vchiq_send_remote_use(struct vchiq_state *state) +int vchiq_send_remote_use(struct vchiq_state *state) { if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) - return VCHIQ_RETRY; + return -ENOTCONN; return queue_message(state, NULL, MAKE_REMOTE_USE, NULL, NULL, 0, 0); } -enum vchiq_status vchiq_send_remote_use_active(struct vchiq_state *state) +int vchiq_send_remote_use_active(struct vchiq_state *state) { if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) - return VCHIQ_RETRY; + return -ENOTCONN; return queue_message(state, NULL, MAKE_REMOTE_USE_ACTIVE, NULL, NULL, 0, 0); diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h index 8b4a38f5b3f2..ec1a3caefaea 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.h @@ -10,8 +10,8 @@ #include #include #include -#include +#include "../../include/linux/raspberrypi/vchiq.h" #include "vchiq_cfg.h" /* Do this so that we can test-build the code on non-rpi systems */ @@ -166,6 +166,24 @@ struct vchiq_bulk_queue { struct vchiq_bulk bulks[VCHIQ_NUM_SERVICE_BULKS]; }; +/* + * Remote events provide a way of presenting several virtual doorbells to a + * peer (ARM host to VPU) using only one physical doorbell. They can be thought + * of as a way for the peer to signal a semaphore, in this case implemented as + * a workqueue. + * + * Remote events remain signalled until acknowledged by the receiver, and they + * are non-counting. They are designed in such a way as to minimise the number + * of interrupts and avoid unnecessary waiting. + * + * A remote_event is as small data structures that live in shared memory. It + * comprises two booleans - armed and fired: + * + * The sender sets fired when they signal the receiver. + * If fired is set, the receiver has been signalled and need not wait. + * The receiver sets the armed field before they begin to wait. + * If armed is set, the receiver is waiting and wishes to be woken by interrupt. + */ struct remote_event { int armed; int fired; @@ -458,7 +476,7 @@ vchiq_init_slots(void *mem_base, int mem_size); extern int vchiq_init_state(struct vchiq_state *state, struct vchiq_slot_zero *slot_zero, struct device *dev); -extern enum vchiq_status +extern int vchiq_connect_internal(struct vchiq_state *state, struct vchiq_instance *instance); struct vchiq_service * @@ -467,10 +485,10 @@ vchiq_add_service_internal(struct vchiq_state *state, int srvstate, struct vchiq_instance *instance, void (*userdata_term)(void *userdata)); -extern enum vchiq_status +extern int vchiq_open_service_internal(struct vchiq_service *service, int client_id); -extern enum vchiq_status +extern int vchiq_close_service_internal(struct vchiq_service *service, int close_recvd); extern void @@ -485,7 +503,7 @@ vchiq_shutdown_internal(struct vchiq_state *state, struct vchiq_instance *instan extern void remote_event_pollall(struct vchiq_state *state); -extern enum vchiq_status +extern int vchiq_bulk_transfer(struct vchiq_instance *instance, unsigned int handle, void *offset, void __user *uoffset, int size, void *userdata, enum vchiq_bulk_mode mode, enum vchiq_bulk_dir dir); @@ -536,7 +554,7 @@ vchiq_service_get(struct vchiq_service *service); extern void vchiq_service_put(struct vchiq_service *service); -extern enum vchiq_status +extern int vchiq_queue_message(struct vchiq_instance *instance, unsigned int handle, ssize_t (*copy_callback)(void *context, void *dest, size_t offset, size_t maxsize), @@ -568,13 +586,13 @@ void vchiq_on_remote_release(struct vchiq_state *state); int vchiq_platform_init_state(struct vchiq_state *state); -enum vchiq_status vchiq_check_service(struct vchiq_service *service); +int vchiq_check_service(struct vchiq_service *service); void vchiq_on_remote_use_active(struct vchiq_state *state); -enum vchiq_status vchiq_send_remote_use(struct vchiq_state *state); +int vchiq_send_remote_use(struct vchiq_state *state); -enum vchiq_status vchiq_send_remote_use_active(struct vchiq_state *state); +int vchiq_send_remote_use_active(struct vchiq_state *state); void vchiq_platform_conn_state_changed(struct vchiq_state *state, enum vchiq_connstate oldstate, @@ -584,7 +602,7 @@ void vchiq_set_conn_state(struct vchiq_state *state, enum vchiq_connstate newsta void vchiq_log_dump_mem(const char *label, u32 addr, const void *void_mem, size_t num_bytes); -enum vchiq_status vchiq_remove_service(struct vchiq_instance *instance, unsigned int service); +int vchiq_remove_service(struct vchiq_instance *instance, unsigned int service); int vchiq_get_client_id(struct vchiq_instance *instance, unsigned int service); diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c index 7e297494437e..841e1a535642 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_dev.c @@ -112,7 +112,7 @@ vchiq_ioc_queue_message(struct vchiq_instance *instance, unsigned int handle, struct vchiq_element *elements, unsigned long count) { struct vchiq_io_copy_callback_context context; - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; unsigned long i; size_t total_size = 0; @@ -130,9 +130,9 @@ vchiq_ioc_queue_message(struct vchiq_instance *instance, unsigned int handle, status = vchiq_queue_message(instance, handle, vchiq_ioc_copy_element_data, &context, total_size); - if (status == VCHIQ_ERROR) + if (status == -EINVAL) return -EIO; - else if (status == VCHIQ_RETRY) + else if (status == -EAGAIN) return -EINTR; return 0; } @@ -142,7 +142,7 @@ static int vchiq_ioc_create_service(struct vchiq_instance *instance, { struct user_service *user_service = NULL; struct vchiq_service *service; - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; struct vchiq_service_params_kernel params; int srvstate; @@ -190,9 +190,9 @@ static int vchiq_ioc_create_service(struct vchiq_instance *instance, if (args->is_open) { status = vchiq_open_service_internal(service, instance->pid); - if (status != VCHIQ_SUCCESS) { + if (status) { vchiq_remove_service(instance, service->handle); - return (status == VCHIQ_RETRY) ? + return (status == -EAGAIN) ? -EINTR : -EIO; } } @@ -338,7 +338,7 @@ static int vchiq_irq_queue_bulk_tx_rx(struct vchiq_instance *instance, goto out; } - if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || + if ((status != -EAGAIN) || fatal_signal_pending(current) || !waiter->bulk_waiter.bulk) { if (waiter->bulk_waiter.bulk) { /* Cancel the signal when the transfer completes. */ @@ -364,9 +364,9 @@ out: vchiq_service_put(service); if (ret) return ret; - else if (status == VCHIQ_ERROR) + else if (status == -EINVAL) return -EIO; - else if (status == VCHIQ_RETRY) + else if (status == -EAGAIN) return -EINTR; return 0; } @@ -577,7 +577,7 @@ static long vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { struct vchiq_instance *instance = file->private_data; - enum vchiq_status status = VCHIQ_SUCCESS; + int status = 0; struct vchiq_service *service = NULL; long ret = 0; int i, rc; @@ -598,12 +598,12 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) instance, &i))) { status = vchiq_remove_service(instance, service->handle); vchiq_service_put(service); - if (status != VCHIQ_SUCCESS) + if (status) break; } service = NULL; - if (status == VCHIQ_SUCCESS) { + if (!status) { /* Wake the completion thread and ask it to exit */ instance->closing = 1; complete(&instance->insert_event); @@ -627,7 +627,7 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) status = vchiq_connect_internal(instance->state, instance); mutex_unlock(&instance->state->mutex); - if (status == VCHIQ_SUCCESS) + if (!status) instance->connected = 1; else vchiq_log_error(vchiq_arm_log_level, @@ -675,7 +675,7 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) status = (cmd == VCHIQ_IOC_CLOSE_SERVICE) ? vchiq_close_service(instance, service->handle) : vchiq_remove_service(instance, service->handle); - if (status != VCHIQ_SUCCESS) + if (status) break; } @@ -686,7 +686,7 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) */ if (user_service->close_pending && wait_for_completion_interruptible(&user_service->close_event)) - status = VCHIQ_RETRY; + status = -EAGAIN; break; } @@ -862,13 +862,13 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) vchiq_service_put(service); if (ret == 0) { - if (status == VCHIQ_ERROR) + if (status == -EINVAL) ret = -EIO; - else if (status == VCHIQ_RETRY) + else if (status == -EAGAIN) ret = -EINTR; } - if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) && (ret != -EWOULDBLOCK)) + if (!status && (ret < 0) && (ret != -EINTR) && (ret != -EWOULDBLOCK)) vchiq_log_info(vchiq_arm_log_level, " ioctl instance %pK, cmd %s -> status %d, %ld", instance, (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_ioctl.h b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_ioctl.h index 86d77f2eeea5..17550831f86c 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_ioctl.h @@ -5,17 +5,18 @@ #define VCHIQ_IOCTLS_H #include -#include + +#include "../../include/linux/raspberrypi/vchiq.h" #define VCHIQ_IOC_MAGIC 0xc4 #define VCHIQ_INVALID_HANDLE (~0) struct vchiq_service_params { int fourcc; - enum vchiq_status __user (*callback)(enum vchiq_reason reason, - struct vchiq_header *header, - unsigned int handle, - void *bulk_userdata); + int __user (*callback)(enum vchiq_reason reason, + struct vchiq_header *header, + unsigned int handle, + void *bulk_userdata); void __user *userdata; short version; /* Increment for non-trivial changes */ short version_min; /* Update for incompatible changes */ diff --git a/drivers/staging/vc04_services/vchiq-mmal/Makefile b/drivers/staging/vc04_services/vchiq-mmal/Makefile index b2a830f48acc..6937f6534c26 100644 --- a/drivers/staging/vc04_services/vchiq-mmal/Makefile +++ b/drivers/staging/vc04_services/vchiq-mmal/Makefile @@ -2,8 +2,3 @@ bcm2835-mmal-vchiq-objs := mmal-vchiq.o obj-$(CONFIG_BCM2835_VCHIQ_MMAL) += bcm2835-mmal-vchiq.o - -ccflags-y += \ - -I$(srctree)/$(src)/.. \ - -I$(srctree)/$(src)/../include \ - -D__VCCOREVER__=0x04000000 diff --git a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c index 294b184d4a49..258aa0e37f55 100644 --- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c +++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c @@ -23,9 +23,9 @@ #include #include #include -#include #include +#include "../include/linux/raspberrypi/vchiq.h" #include "mmal-common.h" #include "mmal-vchiq.h" #include "mmal-msg.h" @@ -245,7 +245,7 @@ static void event_to_host_cb(struct vchiq_mmal_instance *instance, /* workqueue scheduled callback * * we do this because it is important we do not call any other vchiq - * sync calls from witin the message delivery thread + * sync calls from within the message delivery thread */ static void buffer_work_cb(struct work_struct *work) { @@ -548,10 +548,9 @@ static void bulk_abort_cb(struct vchiq_mmal_instance *instance, } /* incoming event service callback */ -static enum vchiq_status service_callback(struct vchiq_instance *vchiq_instance, - enum vchiq_reason reason, - struct vchiq_header *header, - unsigned int handle, void *bulk_ctx) +static int service_callback(struct vchiq_instance *vchiq_instance, + enum vchiq_reason reason, struct vchiq_header *header, + unsigned int handle, void *bulk_ctx) { struct vchiq_mmal_instance *instance = vchiq_get_service_userdata(vchiq_instance, handle); u32 msg_len; @@ -560,7 +559,7 @@ static enum vchiq_status service_callback(struct vchiq_instance *vchiq_instance, if (!instance) { pr_err("Message callback passed NULL instance\n"); - return VCHIQ_SUCCESS; + return 0; } switch (reason) { @@ -644,7 +643,7 @@ static enum vchiq_status service_callback(struct vchiq_instance *vchiq_instance, break; } - return VCHIQ_SUCCESS; + return 0; } static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance, diff --git a/drivers/staging/vme_user/vme.h b/drivers/staging/vme_user/vme.h index 98da8d039d60..faa9816046a9 100644 --- a/drivers/staging/vme_user/vme.h +++ b/drivers/staging/vme_user/vme.h @@ -2,6 +2,8 @@ #ifndef _VME_H_ #define _VME_H_ +#include + /* Resource Type */ enum vme_resource_type { VME_MASTER, @@ -54,20 +56,20 @@ enum vme_resource_type { #define VME_R_ROBIN_MODE 0x1 #define VME_PRIORITY_MODE 0x2 -#define VME_DMA_PATTERN (1<<0) -#define VME_DMA_PCI (1<<1) -#define VME_DMA_VME (1<<2) +#define VME_DMA_PATTERN BIT(0) +#define VME_DMA_PCI BIT(1) +#define VME_DMA_VME BIT(2) -#define VME_DMA_PATTERN_BYTE (1<<0) -#define VME_DMA_PATTERN_WORD (1<<1) -#define VME_DMA_PATTERN_INCREMENT (1<<2) +#define VME_DMA_PATTERN_BYTE BIT(0) +#define VME_DMA_PATTERN_WORD BIT(1) +#define VME_DMA_PATTERN_INCREMENT BIT(2) -#define VME_DMA_VME_TO_MEM (1<<0) -#define VME_DMA_MEM_TO_VME (1<<1) -#define VME_DMA_VME_TO_VME (1<<2) -#define VME_DMA_MEM_TO_MEM (1<<3) -#define VME_DMA_PATTERN_TO_VME (1<<4) -#define VME_DMA_PATTERN_TO_MEM (1<<5) +#define VME_DMA_VME_TO_MEM BIT(0) +#define VME_DMA_MEM_TO_VME BIT(1) +#define VME_DMA_VME_TO_VME BIT(2) +#define VME_DMA_MEM_TO_MEM BIT(3) +#define VME_DMA_PATTERN_TO_VME BIT(4) +#define VME_DMA_PATTERN_TO_MEM BIT(5) struct vme_dma_attr { u32 type; diff --git a/drivers/staging/vme_user/vme_bridge.h b/drivers/staging/vme_user/vme_bridge.h index 0bbefe9851d7..11df0a5e7f7b 100644 --- a/drivers/staging/vme_user/vme_bridge.h +++ b/drivers/staging/vme_user/vme_bridge.h @@ -4,7 +4,7 @@ #include "vme.h" -#define VME_CRCSR_BUF_SIZE (508*1024) +#define VME_CRCSR_BUF_SIZE (508 * 1024) /* * Resource structures */ @@ -84,7 +84,7 @@ struct vme_error_handler { unsigned long long end; /* End of error window */ unsigned long long first_error; /* Address of the first error */ u32 aspace; /* Address space of error window*/ - unsigned num_errors; /* Number of errors */ + unsigned int num_errors; /* Number of errors */ }; struct vme_callback { @@ -128,45 +128,45 @@ struct vme_bridge { struct mutex irq_mtx; /* Slave Functions */ - int (*slave_get) (struct vme_slave_resource *, int *, + int (*slave_get)(struct vme_slave_resource *, int *, unsigned long long *, unsigned long long *, dma_addr_t *, u32 *, u32 *); - int (*slave_set) (struct vme_slave_resource *, int, unsigned long long, + int (*slave_set)(struct vme_slave_resource *, int, unsigned long long, unsigned long long, dma_addr_t, u32, u32); /* Master Functions */ - int (*master_get) (struct vme_master_resource *, int *, + int (*master_get)(struct vme_master_resource *, int *, unsigned long long *, unsigned long long *, u32 *, u32 *, u32 *); - int (*master_set) (struct vme_master_resource *, int, + int (*master_set)(struct vme_master_resource *, int, unsigned long long, unsigned long long, u32, u32, u32); - ssize_t (*master_read) (struct vme_master_resource *, void *, size_t, + ssize_t (*master_read)(struct vme_master_resource *, void *, size_t, loff_t); - ssize_t (*master_write) (struct vme_master_resource *, void *, size_t, + ssize_t (*master_write)(struct vme_master_resource *, void *, size_t, loff_t); - unsigned int (*master_rmw) (struct vme_master_resource *, unsigned int, + unsigned int (*master_rmw)(struct vme_master_resource *, unsigned int, unsigned int, unsigned int, loff_t); /* DMA Functions */ - int (*dma_list_add) (struct vme_dma_list *, struct vme_dma_attr *, + int (*dma_list_add)(struct vme_dma_list *, struct vme_dma_attr *, struct vme_dma_attr *, size_t); - int (*dma_list_exec) (struct vme_dma_list *); - int (*dma_list_empty) (struct vme_dma_list *); + int (*dma_list_exec)(struct vme_dma_list *); + int (*dma_list_empty)(struct vme_dma_list *); /* Interrupt Functions */ - void (*irq_set) (struct vme_bridge *, int, int, int); - int (*irq_generate) (struct vme_bridge *, int, int); + void (*irq_set)(struct vme_bridge *, int, int, int); + int (*irq_generate)(struct vme_bridge *, int, int); /* Location monitor functions */ - int (*lm_set) (struct vme_lm_resource *, unsigned long long, u32, u32); - int (*lm_get) (struct vme_lm_resource *, unsigned long long *, u32 *, + int (*lm_set)(struct vme_lm_resource *, unsigned long long, u32, u32); + int (*lm_get)(struct vme_lm_resource *, unsigned long long *, u32 *, u32 *); int (*lm_attach)(struct vme_lm_resource *, int, void (*callback)(void *), void *); - int (*lm_detach) (struct vme_lm_resource *, int); + int (*lm_detach)(struct vme_lm_resource *, int); /* CR/CSR space functions */ - int (*slot_get) (struct vme_bridge *); + int (*slot_get)(struct vme_bridge *); /* Bridge parent interface */ void *(*alloc_consistent)(struct device *dev, size_t size, diff --git a/drivers/staging/wlan-ng/hfa384x.h b/drivers/staging/wlan-ng/hfa384x.h index 0611e37df6ac..e33dd1b9c40e 100644 --- a/drivers/staging/wlan-ng/hfa384x.h +++ b/drivers/staging/wlan-ng/hfa384x.h @@ -904,40 +904,6 @@ union hfa384x_usbin { *-------------------------------------------------------------------- */ -struct hfa384x_pdr_pcb_partnum { - u8 num[8]; -} __packed; - -struct hfa384x_pdr_pcb_tracenum { - u8 num[8]; -} __packed; - -struct hfa384x_pdr_nic_serial { - u8 num[12]; -} __packed; - -struct hfa384x_pdr_mkk_measurements { - double carrier_freq; - double occupied_band; - double power_density; - double tx_spur_f1; - double tx_spur_f2; - double tx_spur_f3; - double tx_spur_f4; - double tx_spur_l1; - double tx_spur_l2; - double tx_spur_l3; - double tx_spur_l4; - double rx_spur_f1; - double rx_spur_f2; - double rx_spur_l1; - double rx_spur_l2; -} __packed; - -struct hfa384x_pdr_nic_ramsize { - u8 size[12]; /* units of KB */ -} __packed; - struct hfa384x_pdr_mfisuprange { u16 id; u16 variant; @@ -959,150 +925,13 @@ struct hfa384x_pdr_nicid { u16 minor; } __packed; -struct hfa384x_pdr_refdac_measurements { - u16 value[0]; -} __packed; - -struct hfa384x_pdr_vgdac_measurements { - u16 value[0]; -} __packed; - -struct hfa384x_pdr_level_comp_measurements { - u16 value[0]; -} __packed; - -struct hfa384x_pdr_mac_address { - u8 addr[6]; -} __packed; - -struct hfa384x_pdr_mkk_callname { - u8 callname[8]; -} __packed; - -struct hfa384x_pdr_regdomain { - u16 numdomains; - u16 domain[5]; -} __packed; - -struct hfa384x_pdr_allowed_channel { - u16 ch_bitmap; -} __packed; - -struct hfa384x_pdr_default_channel { - u16 channel; -} __packed; - -struct hfa384x_pdr_privacy_option { - u16 available; -} __packed; - -struct hfa384x_pdr_temptype { - u16 type; -} __packed; - -struct hfa384x_pdr_refdac_setup { - u16 ch_value[14]; -} __packed; - -struct hfa384x_pdr_vgdac_setup { - u16 ch_value[14]; -} __packed; - -struct hfa384x_pdr_level_comp_setup { - u16 ch_value[14]; -} __packed; - -struct hfa384x_pdr_trimdac_setup { - u16 trimidac; - u16 trimqdac; -} __packed; - -struct hfa384x_pdr_ifr_setting { - u16 value[3]; -} __packed; - -struct hfa384x_pdr_rfr_setting { - u16 value[3]; -} __packed; - -struct hfa384x_pdr_hfa3861_baseline { - u16 value[50]; -} __packed; - -struct hfa384x_pdr_hfa3861_shadow { - u32 value[32]; -} __packed; - -struct hfa384x_pdr_hfa3861_ifrf { - u32 value[20]; -} __packed; - -struct hfa384x_pdr_hfa3861_chcalsp { - u16 value[14]; -} __packed; - -struct hfa384x_pdr_hfa3861_chcali { - u16 value[17]; -} __packed; - -struct hfa384x_pdr_hfa3861_nic_config { - u16 config_bitmap; -} __packed; - -struct hfa384x_pdr_hfo_delay { - u8 hfo_delay; -} __packed; - -struct hfa384x_pdr_hfa3861_manf_testsp { - u16 value[30]; -} __packed; - -struct hfa384x_pdr_hfa3861_manf_testi { - u16 value[30]; -} __packed; - -struct hfa384x_pdr_end_of_pda { - u16 crc; -} __packed; - struct hfa384x_pdrec { __le16 len; /* in words */ __le16 code; union pdr { - struct hfa384x_pdr_pcb_partnum pcb_partnum; - struct hfa384x_pdr_pcb_tracenum pcb_tracenum; - struct hfa384x_pdr_nic_serial nic_serial; - struct hfa384x_pdr_mkk_measurements mkk_measurements; - struct hfa384x_pdr_nic_ramsize nic_ramsize; struct hfa384x_pdr_mfisuprange mfisuprange; struct hfa384x_pdr_cfisuprange cfisuprange; struct hfa384x_pdr_nicid nicid; - struct hfa384x_pdr_refdac_measurements refdac_measurements; - struct hfa384x_pdr_vgdac_measurements vgdac_measurements; - struct hfa384x_pdr_level_comp_measurements level_compc_measurements; - struct hfa384x_pdr_mac_address mac_address; - struct hfa384x_pdr_mkk_callname mkk_callname; - struct hfa384x_pdr_regdomain regdomain; - struct hfa384x_pdr_allowed_channel allowed_channel; - struct hfa384x_pdr_default_channel default_channel; - struct hfa384x_pdr_privacy_option privacy_option; - struct hfa384x_pdr_temptype temptype; - struct hfa384x_pdr_refdac_setup refdac_setup; - struct hfa384x_pdr_vgdac_setup vgdac_setup; - struct hfa384x_pdr_level_comp_setup level_comp_setup; - struct hfa384x_pdr_trimdac_setup trimdac_setup; - struct hfa384x_pdr_ifr_setting ifr_setting; - struct hfa384x_pdr_rfr_setting rfr_setting; - struct hfa384x_pdr_hfa3861_baseline hfa3861_baseline; - struct hfa384x_pdr_hfa3861_shadow hfa3861_shadow; - struct hfa384x_pdr_hfa3861_ifrf hfa3861_ifrf; - struct hfa384x_pdr_hfa3861_chcalsp hfa3861_chcalsp; - struct hfa384x_pdr_hfa3861_chcali hfa3861_chcali; - struct hfa384x_pdr_hfa3861_nic_config nic_config; - struct hfa384x_pdr_hfo_delay hfo_delay; - struct hfa384x_pdr_hfa3861_manf_testsp hfa3861_manf_testsp; - struct hfa384x_pdr_hfa3861_manf_testi hfa3861_manf_testi; - struct hfa384x_pdr_end_of_pda end_of_pda; } data; } __packed; diff --git a/drivers/tty/amiserial.c b/drivers/tty/amiserial.c index f52266766df9..d7515d61659e 100644 --- a/drivers/tty/amiserial.c +++ b/drivers/tty/amiserial.c @@ -502,7 +502,7 @@ static int startup(struct tty_struct *tty, struct serial_state *info) */ change_speed(tty, info, NULL); - tty_port_set_initialized(port, 1); + tty_port_set_initialized(port, true); local_irq_restore(flags); return 0; @@ -556,7 +556,7 @@ static void shutdown(struct tty_struct *tty, struct serial_state *info) set_bit(TTY_IO_ERROR, &tty->flags); - tty_port_set_initialized(&info->tport, 0); + tty_port_set_initialized(&info->tport, false); local_irq_restore(flags); } @@ -1329,7 +1329,7 @@ static void rs_hangup(struct tty_struct *tty) rs_flush_buffer(tty); shutdown(tty, info); info->tport.count = 0; - tty_port_set_active(&info->tport, 0); + tty_port_set_active(&info->tport, false); info->tport.tty = NULL; wake_up_interruptible(&info->tport.open_wait); } @@ -1454,18 +1454,18 @@ static const struct tty_operations serial_ops = { .proc_show = rs_proc_show, }; -static int amiga_carrier_raised(struct tty_port *port) +static bool amiga_carrier_raised(struct tty_port *port) { return !(ciab.pra & SER_DCD); } -static void amiga_dtr_rts(struct tty_port *port, int raise) +static void amiga_dtr_rts(struct tty_port *port, bool active) { struct serial_state *info = container_of(port, struct serial_state, tport); unsigned long flags; - if (raise) + if (active) info->MCR |= SER_DTR|SER_RTS; else info->MCR &= ~(SER_DTR|SER_RTS); diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c index a683e21df19c..10c10cfdf92a 100644 --- a/drivers/tty/hvc/hvc_console.c +++ b/drivers/tty/hvc/hvc_console.c @@ -376,7 +376,7 @@ static int hvc_open(struct tty_struct *tty, struct file * filp) /* We are ready... raise DTR/RTS */ if (C_BAUD(tty)) if (hp->ops->dtr_rts) - hp->ops->dtr_rts(hp, 1); + hp->ops->dtr_rts(hp, true); tty_port_set_initialized(&hp->port, true); } @@ -406,7 +406,7 @@ static void hvc_close(struct tty_struct *tty, struct file * filp) if (C_HUPCL(tty)) if (hp->ops->dtr_rts) - hp->ops->dtr_rts(hp, 0); + hp->ops->dtr_rts(hp, false); if (hp->ops->notifier_del) hp->ops->notifier_del(hp, hp->data); diff --git a/drivers/tty/hvc/hvc_console.h b/drivers/tty/hvc/hvc_console.h index 97200fbeeae8..f990c5094d20 100644 --- a/drivers/tty/hvc/hvc_console.h +++ b/drivers/tty/hvc/hvc_console.h @@ -66,7 +66,7 @@ struct hv_ops { int (*tiocmset)(struct hvc_struct *hp, unsigned int set, unsigned int clear); /* Callbacks to handle tty ports */ - void (*dtr_rts)(struct hvc_struct *hp, int raise); + void (*dtr_rts)(struct hvc_struct *hp, bool active); }; /* Register a vterm and a slot index for use as a console (console_init) */ diff --git a/drivers/tty/hvc/hvc_iucv.c b/drivers/tty/hvc/hvc_iucv.c index 7d49a872de48..543f35ddf523 100644 --- a/drivers/tty/hvc/hvc_iucv.c +++ b/drivers/tty/hvc/hvc_iucv.c @@ -658,13 +658,13 @@ static void hvc_iucv_notifier_hangup(struct hvc_struct *hp, int id) /** * hvc_iucv_dtr_rts() - HVC notifier for handling DTR/RTS * @hp: Pointer the HVC device (struct hvc_struct) - * @raise: Non-zero to raise or zero to lower DTR/RTS lines + * @active: True to raise or false to lower DTR/RTS lines * * This routine notifies the HVC back-end to raise or lower DTR/RTS * lines. Raising DTR/RTS is ignored. Lowering DTR/RTS indicates to * drop the IUCV connection (similar to hang up the modem). */ -static void hvc_iucv_dtr_rts(struct hvc_struct *hp, int raise) +static void hvc_iucv_dtr_rts(struct hvc_struct *hp, bool active) { struct hvc_iucv_private *priv; struct iucv_path *path; @@ -672,7 +672,7 @@ static void hvc_iucv_dtr_rts(struct hvc_struct *hp, int raise) /* Raising the DTR/RTS is ignored as IUCV connections can be * established at any times. */ - if (raise) + if (active) return; priv = hvc_iucv_get_private(hp->vtermno); diff --git a/drivers/tty/hvc/hvcs.c b/drivers/tty/hvc/hvcs.c index 4ba24963685e..1de1a09bf82d 100644 --- a/drivers/tty/hvc/hvcs.c +++ b/drivers/tty/hvc/hvcs.c @@ -52,6 +52,7 @@ #include #include +#include #include #include #include @@ -285,6 +286,7 @@ struct hvcs_struct { char p_location_code[HVCS_CLC_LENGTH + 1]; /* CLC + Null Term */ struct list_head next; /* list management */ struct vio_dev *vdev; + struct completion *destroyed; }; static LIST_HEAD(hvcs_structs); @@ -432,7 +434,7 @@ static ssize_t hvcs_index_show(struct device *dev, struct device_attribute *attr static DEVICE_ATTR(index, S_IRUGO, hvcs_index_show, NULL); -static struct attribute *hvcs_attrs[] = { +static struct attribute *hvcs_dev_attrs[] = { &dev_attr_partner_vtys.attr, &dev_attr_partner_clcs.attr, &dev_attr_current_vty.attr, @@ -441,9 +443,7 @@ static struct attribute *hvcs_attrs[] = { NULL, }; -static struct attribute_group hvcs_attr_group = { - .attrs = hvcs_attrs, -}; +ATTRIBUTE_GROUPS(hvcs_dev); static ssize_t rescan_show(struct device_driver *ddp, char *buf) { @@ -468,6 +468,13 @@ static ssize_t rescan_store(struct device_driver *ddp, const char * buf, static DRIVER_ATTR_RW(rescan); +static struct attribute *hvcs_attrs[] = { + &driver_attr_rescan.attr, + NULL, +}; + +ATTRIBUTE_GROUPS(hvcs); + static void hvcs_kick(void) { hvcs_kicked = 1; @@ -658,11 +665,13 @@ static void hvcs_destruct_port(struct tty_port *p) { struct hvcs_struct *hvcsd = container_of(p, struct hvcs_struct, port); struct vio_dev *vdev; + struct completion *comp; unsigned long flags; spin_lock(&hvcs_structs_lock); spin_lock_irqsave(&hvcsd->lock, flags); + comp = hvcsd->destroyed; /* the list_del poisons the pointers */ list_del(&(hvcsd->next)); @@ -682,15 +691,16 @@ static void hvcs_destruct_port(struct tty_port *p) hvcsd->p_unit_address = 0; hvcsd->p_partition_ID = 0; + hvcsd->destroyed = NULL; hvcs_return_index(hvcsd->index); memset(&hvcsd->p_location_code[0], 0x00, HVCS_CLC_LENGTH + 1); spin_unlock_irqrestore(&hvcsd->lock, flags); spin_unlock(&hvcs_structs_lock); - sysfs_remove_group(&vdev->dev.kobj, &hvcs_attr_group); - kfree(hvcsd); + if (comp) + complete(comp); } static const struct tty_port_operations hvcs_port_ops = { @@ -721,7 +731,6 @@ static int hvcs_probe( { struct hvcs_struct *hvcsd; int index, rc; - int retval; if (!dev || !id) { printk(KERN_ERR "HVCS: probed with invalid parameter.\n"); @@ -778,13 +787,6 @@ static int hvcs_probe( list_add_tail(&(hvcsd->next), &hvcs_structs); spin_unlock(&hvcs_structs_lock); - retval = sysfs_create_group(&dev->dev.kobj, &hvcs_attr_group); - if (retval) { - printk(KERN_ERR "HVCS: Can't create sysfs attrs for vty-server@%X\n", - hvcsd->vdev->unit_address); - return retval; - } - printk(KERN_INFO "HVCS: vty-server@%X added to the vio bus.\n", dev->unit_address); /* @@ -797,6 +799,7 @@ static int hvcs_probe( static void hvcs_remove(struct vio_dev *dev) { struct hvcs_struct *hvcsd = dev_get_drvdata(&dev->dev); + DECLARE_COMPLETION_ONSTACK(comp); unsigned long flags; struct tty_struct *tty; @@ -804,24 +807,22 @@ static void hvcs_remove(struct vio_dev *dev) spin_lock_irqsave(&hvcsd->lock, flags); - tty = hvcsd->port.tty; + hvcsd->destroyed = ∁ + tty = tty_port_tty_get(&hvcsd->port); spin_unlock_irqrestore(&hvcsd->lock, flags); /* - * Let the last holder of this object cause it to be removed, which - * would probably be tty_hangup below. - */ - tty_port_put(&hvcsd->port); - - /* - * The hangup is a scheduled function which will auto chain call - * hvcs_hangup. The tty should always be valid at this time unless a + * The tty should always be valid at this time unless a * simultaneous tty close already cleaned up the hvcs_struct. */ - if (tty) - tty_hangup(tty); + if (tty) { + tty_vhangup(tty); + tty_kref_put(tty); + } + tty_port_put(&hvcsd->port); + wait_for_completion(&comp); printk(KERN_INFO "HVCS: vty-server@%X removed from the" " vio bus.\n", dev->unit_address); }; @@ -831,6 +832,10 @@ static struct vio_driver hvcs_vio_driver = { .probe = hvcs_probe, .remove = hvcs_remove, .name = hvcs_driver_name, + .driver = { + .groups = hvcs_groups, + .dev_groups = hvcs_dev_groups, + }, }; /* Only called from hvcs_get_pi please */ @@ -1171,7 +1176,10 @@ static void hvcs_close(struct tty_struct *tty, struct file *filp) hvcsd = tty->driver_data; spin_lock_irqsave(&hvcsd->lock, flags); - if (--hvcsd->port.count == 0) { + if (hvcsd->port.count == 0) { + spin_unlock_irqrestore(&hvcsd->lock, flags); + return; + } else if (--hvcsd->port.count == 0) { vio_disable_interrupts(hvcsd->vdev); @@ -1215,12 +1223,9 @@ static void hvcs_hangup(struct tty_struct * tty) { struct hvcs_struct *hvcsd = tty->driver_data; unsigned long flags; - int temp_open_count; int irq; spin_lock_irqsave(&hvcsd->lock, flags); - /* Preserve this so that we know how many kref refs to put */ - temp_open_count = hvcsd->port.count; /* * Don't kref put inside the spinlock because the destruction @@ -1230,11 +1235,7 @@ static void hvcs_hangup(struct tty_struct * tty) vio_disable_interrupts(hvcsd->vdev); hvcsd->todo_mask = 0; - - /* I don't think the tty needs the hvcs_struct pointer after a hangup */ - tty->driver_data = NULL; hvcsd->port.tty = NULL; - hvcsd->port.count = 0; /* This will drop any buffered data on the floor which is OK in a hangup @@ -1247,21 +1248,6 @@ static void hvcs_hangup(struct tty_struct * tty) spin_unlock_irqrestore(&hvcsd->lock, flags); free_irq(irq, hvcsd); - - /* - * We need to kref_put() for every open_count we have since the - * tty_hangup() function doesn't invoke a close per open connection on a - * non-console device. - */ - while(temp_open_count) { - --temp_open_count; - /* - * The final put will trigger destruction of the hvcs_struct. - * NOTE: If this hangup was signaled from user space then the - * final put will never happen. - */ - tty_port_put(&hvcsd->port); - } } /* @@ -1525,13 +1511,6 @@ static int __init hvcs_module_init(void) pr_info("HVCS: Driver registered.\n"); - /* This needs to be done AFTER the vio_register_driver() call or else - * the kobjects won't be initialized properly. - */ - rc = driver_create_file(&(hvcs_vio_driver.driver), &driver_attr_rescan); - if (rc) - pr_warn("HVCS: Failed to create rescan file (err %d)\n", rc); - return 0; } @@ -1556,8 +1535,6 @@ static void __exit hvcs_module_exit(void) hvcs_pi_buff = NULL; spin_unlock(&hvcs_pi_lock); - driver_remove_file(&hvcs_vio_driver.driver, &driver_attr_rescan); - tty_unregister_driver(hvcs_tty_driver); hvcs_free_index_list(); diff --git a/drivers/tty/moxa.c b/drivers/tty/moxa.c index 35b6fddf0341..42fa4c878b2e 100644 --- a/drivers/tty/moxa.c +++ b/drivers/tty/moxa.c @@ -501,16 +501,16 @@ static int moxa_tiocmset(struct tty_struct *tty, static void moxa_poll(struct timer_list *); static void moxa_set_tty_param(struct tty_struct *, const struct ktermios *); static void moxa_shutdown(struct tty_port *); -static int moxa_carrier_raised(struct tty_port *); -static void moxa_dtr_rts(struct tty_port *, int); +static bool moxa_carrier_raised(struct tty_port *); +static void moxa_dtr_rts(struct tty_port *, bool); /* * moxa board interface functions: */ static void MoxaPortEnable(struct moxa_port *); static void MoxaPortDisable(struct moxa_port *); static int MoxaPortSetTermio(struct moxa_port *, struct ktermios *, speed_t); -static int MoxaPortGetLineOut(struct moxa_port *, int *, int *); -static void MoxaPortLineCtrl(struct moxa_port *, int, int); +static int MoxaPortGetLineOut(struct moxa_port *, bool *, bool *); +static void MoxaPortLineCtrl(struct moxa_port *, bool, bool); static void MoxaPortFlowCtrl(struct moxa_port *, int, int, int, int, int); static int MoxaPortLineStatus(struct moxa_port *); static void MoxaPortFlushData(struct moxa_port *, int); @@ -1432,7 +1432,7 @@ static void moxa_shutdown(struct tty_port *port) MoxaPortFlushData(ch, 2); } -static int moxa_carrier_raised(struct tty_port *port) +static bool moxa_carrier_raised(struct tty_port *port) { struct moxa_port *ch = container_of(port, struct moxa_port, port); int dcd; @@ -1443,10 +1443,10 @@ static int moxa_carrier_raised(struct tty_port *port) return dcd; } -static void moxa_dtr_rts(struct tty_port *port, int onoff) +static void moxa_dtr_rts(struct tty_port *port, bool active) { struct moxa_port *ch = container_of(port, struct moxa_port, port); - MoxaPortLineCtrl(ch, onoff, onoff); + MoxaPortLineCtrl(ch, active, active); } @@ -1481,10 +1481,10 @@ static int moxa_open(struct tty_struct *tty, struct file *filp) if (!tty_port_initialized(&ch->port)) { ch->statusflags = 0; moxa_set_tty_param(tty, &tty->termios); - MoxaPortLineCtrl(ch, 1, 1); + MoxaPortLineCtrl(ch, true, true); MoxaPortEnable(ch); MoxaSetFifo(ch, ch->type == PORT_16550A); - tty_port_set_initialized(&ch->port, 1); + tty_port_set_initialized(&ch->port, true); } mutex_unlock(&ch->port.mutex); mutex_unlock(&moxa_openlock); @@ -1557,19 +1557,21 @@ static unsigned int moxa_chars_in_buffer(struct tty_struct *tty) static int moxa_tiocmget(struct tty_struct *tty) { struct moxa_port *ch = tty->driver_data; - int flag = 0, dtr, rts; + bool dtr_active, rts_active; + int flag = 0; + int status; - MoxaPortGetLineOut(ch, &dtr, &rts); - if (dtr) + MoxaPortGetLineOut(ch, &dtr_active, &rts_active); + if (dtr_active) flag |= TIOCM_DTR; - if (rts) + if (rts_active) flag |= TIOCM_RTS; - dtr = MoxaPortLineStatus(ch); - if (dtr & 1) + status = MoxaPortLineStatus(ch); + if (status & 1) flag |= TIOCM_CTS; - if (dtr & 2) + if (status & 2) flag |= TIOCM_DSR; - if (dtr & 4) + if (status & 4) flag |= TIOCM_CD; return flag; } @@ -1577,8 +1579,8 @@ static int moxa_tiocmget(struct tty_struct *tty) static int moxa_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) { + bool dtr_active, rts_active; struct moxa_port *ch; - int dtr, rts; mutex_lock(&moxa_openlock); ch = tty->driver_data; @@ -1587,16 +1589,16 @@ static int moxa_tiocmset(struct tty_struct *tty, return -EINVAL; } - MoxaPortGetLineOut(ch, &dtr, &rts); + MoxaPortGetLineOut(ch, &dtr_active, &rts_active); if (set & TIOCM_RTS) - rts = 1; + rts_active = true; if (set & TIOCM_DTR) - dtr = 1; + dtr_active = true; if (clear & TIOCM_RTS) - rts = 0; + rts_active = false; if (clear & TIOCM_DTR) - dtr = 0; - MoxaPortLineCtrl(ch, dtr, rts); + dtr_active = false; + MoxaPortLineCtrl(ch, dtr_active, rts_active); mutex_unlock(&moxa_openlock); return 0; } @@ -1664,8 +1666,8 @@ static int moxa_poll_port(struct moxa_port *p, unsigned int handle, u16 __iomem *ip) { struct tty_struct *tty = tty_port_tty_get(&p->port); + bool inited = tty_port_initialized(&p->port); void __iomem *ofsAddr; - unsigned int inited = tty_port_initialized(&p->port); u16 intr; if (tty) { @@ -1877,12 +1879,12 @@ static void MoxaPortFlushData(struct moxa_port *port, int mode) * * Function 13: Get the DTR/RTS state of this port. * Syntax: - * int MoxaPortGetLineOut(int port, int *dtrState, int *rtsState); + * int MoxaPortGetLineOut(int port, bool *dtrState, bool *rtsState); * int port : port number (0 - 127) - * int * dtrState : pointer to INT to receive the current DTR + * bool * dtr_active : pointer to bool to receive the current DTR * state. (if NULL, this function will not * write to this address) - * int * rtsState : pointer to INT to receive the current RTS + * bool * rts_active : pointer to bool to receive the current RTS * state. (if NULL, this function will not * write to this address) * @@ -1892,10 +1894,10 @@ static void MoxaPortFlushData(struct moxa_port *port, int mode) * * Function 14: Setting the DTR/RTS output state of this port. * Syntax: - * void MoxaPortLineCtrl(int port, int dtrState, int rtsState); + * void MoxaPortLineCtrl(int port, bool dtrState, bool rtsState); * int port : port number (0 - 127) - * int dtrState : DTR output state (0: off, 1: on) - * int rtsState : RTS output state (0: off, 1: on) + * bool dtr_active : DTR output state + * bool rts_active : RTS output state * * * Function 15: Setting the flow control of this port. @@ -2103,24 +2105,24 @@ static int MoxaPortSetTermio(struct moxa_port *port, struct ktermios *termio, return baud; } -static int MoxaPortGetLineOut(struct moxa_port *port, int *dtrState, - int *rtsState) +static int MoxaPortGetLineOut(struct moxa_port *port, bool *dtr_active, + bool *rts_active) { - if (dtrState) - *dtrState = !!(port->lineCtrl & DTR_ON); - if (rtsState) - *rtsState = !!(port->lineCtrl & RTS_ON); + if (dtr_active) + *dtr_active = port->lineCtrl & DTR_ON; + if (rts_active) + *rts_active = port->lineCtrl & RTS_ON; return 0; } -static void MoxaPortLineCtrl(struct moxa_port *port, int dtr, int rts) +static void MoxaPortLineCtrl(struct moxa_port *port, bool dtr_active, bool rts_active) { u8 mode = 0; - if (dtr) + if (dtr_active) mode |= DTR_ON; - if (rts) + if (rts_active) mode |= RTS_ON; port->lineCtrl = mode; moxafunc(port->tableAddr, FC_LineControl, mode); diff --git a/drivers/tty/mxser.c b/drivers/tty/mxser.c index 2436e0b10f9a..ef3116e87975 100644 --- a/drivers/tty/mxser.c +++ b/drivers/tty/mxser.c @@ -458,13 +458,14 @@ static void __mxser_stop_tx(struct mxser_port *info) outb(info->IER, info->ioaddr + UART_IER); } -static int mxser_carrier_raised(struct tty_port *port) +static bool mxser_carrier_raised(struct tty_port *port) { struct mxser_port *mp = container_of(port, struct mxser_port, port); - return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; + + return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD; } -static void mxser_dtr_rts(struct tty_port *port, int on) +static void mxser_dtr_rts(struct tty_port *port, bool active) { struct mxser_port *mp = container_of(port, struct mxser_port, port); unsigned long flags; @@ -472,7 +473,7 @@ static void mxser_dtr_rts(struct tty_port *port, int on) spin_lock_irqsave(&mp->slock, flags); mcr = inb(mp->ioaddr + UART_MCR); - if (on) + if (active) mcr |= UART_MCR_DTR | UART_MCR_RTS; else mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); @@ -1063,7 +1064,7 @@ static int mxser_set_serial_info(struct tty_struct *tty, } else { retval = mxser_activate(port, tty); if (retval == 0) - tty_port_set_initialized(port, 1); + tty_port_set_initialized(port, true); } mutex_unlock(&port->mutex); return retval; diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c index 348d85c13f91..7aa05ebed8e1 100644 --- a/drivers/tty/n_gsm.c +++ b/drivers/tty/n_gsm.c @@ -318,6 +318,11 @@ struct gsm_mux { struct gsm_control *pending_cmd;/* Our current pending command */ spinlock_t control_lock; /* Protects the pending command */ + /* Keep-alive */ + struct timer_list ka_timer; /* Keep-alive response timer */ + u8 ka_num; /* Keep-alive match pattern */ + signed int ka_retries; /* Keep-alive retry counter, -1 if not yet initialized */ + /* Configuration */ int adaption; /* 1 or 2 supported */ u8 ftype; /* UI or UIH */ @@ -325,6 +330,7 @@ struct gsm_mux { unsigned int t3; /* Power wake-up timer in seconds. */ int n2; /* Retry count */ u8 k; /* Window size */ + u32 keep_alive; /* Control channel keep-alive in 10ms */ /* Statistics (not currently exposed) */ unsigned long bad_fcs; @@ -540,6 +546,11 @@ static u8 gsm_encode_modem(const struct gsm_dlci *dlci) modembits |= MDM_IC; if (dlci->modem_tx & TIOCM_CD || dlci->gsm->initiator) modembits |= MDM_DV; + /* special mappings for passive side to operate as UE */ + if (dlci->modem_tx & TIOCM_OUT1) + modembits |= MDM_IC; + if (dlci->modem_tx & TIOCM_OUT2) + modembits |= MDM_DV; return modembits; } @@ -1531,6 +1542,7 @@ static void gsm_process_modem(struct tty_struct *tty, struct gsm_dlci *dlci, if (brk & 0x01) tty_insert_flip_char(&dlci->port, 0, TTY_BREAK); dlci->modem_rx = mlines; + wake_up_interruptible(&dlci->gsm->event); } /** @@ -1897,11 +1909,13 @@ static void gsm_control_response(struct gsm_mux *gsm, unsigned int command, const u8 *data, int clen) { struct gsm_control *ctrl; + struct gsm_dlci *dlci; unsigned long flags; spin_lock_irqsave(&gsm->control_lock, flags); ctrl = gsm->pending_cmd; + dlci = gsm->dlci[0]; command |= 1; /* Does the reply match our command */ if (ctrl != NULL && (command == ctrl->cmd || command == CMD_NSC)) { @@ -1916,6 +1930,53 @@ static void gsm_control_response(struct gsm_mux *gsm, unsigned int command, /* Or did we receive the PN response to our PN command */ } else if (command == CMD_PN) { gsm_control_negotiation(gsm, 0, data, clen); + /* Or did we receive the TEST response to our TEST command */ + } else if (command == CMD_TEST && clen == 1 && *data == gsm->ka_num) { + gsm->ka_retries = -1; /* trigger new keep-alive message */ + if (dlci && !dlci->dead) + mod_timer(&gsm->ka_timer, jiffies + gsm->keep_alive * HZ / 100); + } + spin_unlock_irqrestore(&gsm->control_lock, flags); +} + +/** + * gsm_control_keep_alive - check timeout or start keep-alive + * @t: timer contained in our gsm object + * + * Called off the keep-alive timer expiry signaling that our link + * partner is not responding anymore. Link will be closed. + * This is also called to startup our timer. + */ + +static void gsm_control_keep_alive(struct timer_list *t) +{ + struct gsm_mux *gsm = from_timer(gsm, t, ka_timer); + unsigned long flags; + + spin_lock_irqsave(&gsm->control_lock, flags); + if (gsm->ka_num && gsm->ka_retries == 0) { + /* Keep-alive expired -> close the link */ + if (debug & DBG_ERRORS) + pr_debug("%s keep-alive timed out\n", __func__); + spin_unlock_irqrestore(&gsm->control_lock, flags); + if (gsm->dlci[0]) + gsm_dlci_begin_close(gsm->dlci[0]); + return; + } else if (gsm->keep_alive && gsm->dlci[0] && !gsm->dlci[0]->dead) { + if (gsm->ka_retries > 0) { + /* T2 expired for keep-alive -> resend */ + gsm->ka_retries--; + } else { + /* Start keep-alive timer */ + gsm->ka_num++; + if (!gsm->ka_num) + gsm->ka_num++; + gsm->ka_retries = (signed int)gsm->n2; + } + gsm_control_command(gsm, CMD_TEST, &gsm->ka_num, + sizeof(gsm->ka_num)); + mod_timer(&gsm->ka_timer, + jiffies + gsm->t2 * HZ / 100); } spin_unlock_irqrestore(&gsm->control_lock, flags); } @@ -2059,14 +2120,16 @@ static void gsm_dlci_close(struct gsm_dlci *dlci) tty_port_tty_hangup(&dlci->port, false); gsm_dlci_clear_queues(dlci->gsm, dlci); /* Ensure that gsmtty_open() can return. */ - tty_port_set_initialized(&dlci->port, 0); + tty_port_set_initialized(&dlci->port, false); wake_up_interruptible(&dlci->port.open_wait); - } else + } else { + del_timer(&dlci->gsm->ka_timer); dlci->gsm->dead = true; + } /* A DLCI 0 close is a MUX termination so we need to kick that back to userspace somehow */ gsm_dlci_data_kick(dlci); - wake_up(&dlci->gsm->event); + wake_up_all(&dlci->gsm->event); } /** @@ -2078,6 +2141,8 @@ static void gsm_dlci_close(struct gsm_dlci *dlci) static void gsm_dlci_open(struct gsm_dlci *dlci) { + struct gsm_mux *gsm = dlci->gsm; + /* Note that SABM UA .. SABM UA first UA lost can mean that we go open -> open */ del_timer(&dlci->t1); @@ -2087,8 +2152,15 @@ static void gsm_dlci_open(struct gsm_dlci *dlci) if (debug & DBG_ERRORS) pr_debug("DLCI %d goes open.\n", dlci->addr); /* Send current modem state */ - if (dlci->addr) + if (dlci->addr) { gsm_modem_update(dlci, 0); + } else { + /* Start keep-alive control */ + gsm->ka_num = 0; + gsm->ka_retries = -1; + mod_timer(&gsm->ka_timer, + jiffies + gsm->keep_alive * HZ / 100); + } gsm_dlci_data_kick(dlci); wake_up(&dlci->gsm->event); } @@ -2267,6 +2339,7 @@ static void gsm_dlci_begin_close(struct gsm_dlci *dlci) dlci->state = DLCI_CLOSING; gsm_command(dlci->gsm, dlci->addr, DISC|PF); mod_timer(&dlci->t1, jiffies + gsm->t1 * HZ / 100); + wake_up_interruptible(&gsm->event); } /** @@ -2840,6 +2913,7 @@ static void gsm_cleanup_mux(struct gsm_mux *gsm, bool disc) /* Finish outstanding timers, making sure they are done */ del_timer_sync(&gsm->kick_timer); del_timer_sync(&gsm->t2_timer); + del_timer_sync(&gsm->ka_timer); /* Finish writing to ldisc */ flush_work(&gsm->tx_work); @@ -2987,6 +3061,7 @@ static struct gsm_mux *gsm_alloc_mux(void) INIT_LIST_HEAD(&gsm->tx_data_list); timer_setup(&gsm->kick_timer, gsm_kick_timer, 0); timer_setup(&gsm->t2_timer, gsm_control_retransmit, 0); + timer_setup(&gsm->ka_timer, gsm_control_keep_alive, 0); INIT_WORK(&gsm->tx_work, gsmld_write_task); init_waitqueue_head(&gsm->event); spin_lock_init(&gsm->control_lock); @@ -3003,6 +3078,7 @@ static struct gsm_mux *gsm_alloc_mux(void) gsm->mru = 64; /* Default to encoding 1 so these should be 64 */ gsm->mtu = 64; gsm->dead = true; /* Avoid early tty opens */ + gsm->keep_alive = 0; /* Disabled */ /* Store the instance to the mux array or abort if no space is * available. @@ -3138,6 +3214,29 @@ static int gsm_config(struct gsm_mux *gsm, struct gsm_config *c) return 0; } +static void gsm_copy_config_ext_values(struct gsm_mux *gsm, + struct gsm_config_ext *ce) +{ + memset(ce, 0, sizeof(*ce)); + ce->keep_alive = gsm->keep_alive; +} + +static int gsm_config_ext(struct gsm_mux *gsm, struct gsm_config_ext *ce) +{ + unsigned int i; + + /* + * Check that userspace doesn't put stuff in here to prevent breakages + * in the future. + */ + for (i = 0; i < ARRAY_SIZE(ce->reserved); i++) + if (ce->reserved[i]) + return -EINVAL; + + gsm->keep_alive = ce->keep_alive; + return 0; +} + /** * gsmld_output - write to link * @gsm: our mux @@ -3456,6 +3555,7 @@ static int gsmld_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg) { struct gsm_config c; + struct gsm_config_ext ce; struct gsm_mux *gsm = tty->disc_data; unsigned int base; @@ -3472,6 +3572,15 @@ static int gsmld_ioctl(struct tty_struct *tty, unsigned int cmd, case GSMIOC_GETFIRST: base = mux_num_to_base(gsm); return put_user(base + 1, (__u32 __user *)arg); + case GSMIOC_GETCONF_EXT: + gsm_copy_config_ext_values(gsm, &ce); + if (copy_to_user((void __user *)arg, &ce, sizeof(ce))) + return -EFAULT; + return 0; + case GSMIOC_SETCONF_EXT: + if (copy_from_user(&ce, (void __user *)arg, sizeof(ce))) + return -EFAULT; + return gsm_config_ext(gsm, &ce); default: return n_tty_ioctl_helper(tty, cmd, arg); } @@ -3770,16 +3879,43 @@ static int gsm_modem_update(struct gsm_dlci *dlci, u8 brk) return -EPROTONOSUPPORT; } -static int gsm_carrier_raised(struct tty_port *port) +/** + * gsm_wait_modem_change - wait for modem status line change + * @dlci: channel + * @mask: modem status line bits + * + * The function returns if: + * - any given modem status line bit changed + * - the wait event function got interrupted (e.g. by a signal) + * - the underlying DLCI was closed + * - the underlying ldisc device was removed + */ +static int gsm_wait_modem_change(struct gsm_dlci *dlci, u32 mask) +{ + struct gsm_mux *gsm = dlci->gsm; + u32 old = dlci->modem_rx; + int ret; + + ret = wait_event_interruptible(gsm->event, gsm->dead || + dlci->state != DLCI_OPEN || + (old ^ dlci->modem_rx) & mask); + if (gsm->dead) + return -ENODEV; + if (dlci->state != DLCI_OPEN) + return -EL2NSYNC; + return ret; +} + +static bool gsm_carrier_raised(struct tty_port *port) { struct gsm_dlci *dlci = container_of(port, struct gsm_dlci, port); struct gsm_mux *gsm = dlci->gsm; /* Not yet open so no carrier info */ if (dlci->state != DLCI_OPEN) - return 0; + return false; if (debug & DBG_CD_ON) - return 1; + return true; /* * Basic mode with control channel in ADM mode may not respond @@ -3787,16 +3923,16 @@ static int gsm_carrier_raised(struct tty_port *port) */ if (gsm->encoding == GSM_BASIC_OPT && gsm->dlci[0]->mode == DLCI_MODE_ADM && !dlci->modem_rx) - return 1; + return true; return dlci->modem_rx & TIOCM_CD; } -static void gsm_dtr_rts(struct tty_port *port, int onoff) +static void gsm_dtr_rts(struct tty_port *port, bool active) { struct gsm_dlci *dlci = container_of(port, struct gsm_dlci, port); unsigned int modem_tx = dlci->modem_tx; - if (onoff) + if (active) modem_tx |= TIOCM_DTR | TIOCM_RTS; else modem_tx &= ~(TIOCM_DTR | TIOCM_RTS); @@ -3880,7 +4016,7 @@ static int gsmtty_open(struct tty_struct *tty, struct file *filp) dlci->modem_rx = 0; /* We could in theory open and close before we wait - eg if we get a DM straight back. This is ok as that will have caused a hangup */ - tty_port_set_initialized(port, 1); + tty_port_set_initialized(port, true); /* Start sending off SABM messages */ if (gsm->initiator) gsm_dlci_begin_open(dlci); @@ -4029,6 +4165,8 @@ static int gsmtty_ioctl(struct tty_struct *tty, gsm_destroy_network(dlci); mutex_unlock(&dlci->mutex); return 0; + case TIOCMIWAIT: + return gsm_wait_modem_change(dlci, (u32)arg); default: return -ENOIOCTLCMD; } diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c new file mode 100644 index 000000000000..6c5ff019df4b --- /dev/null +++ b/drivers/tty/serial/8250/8250_dfl.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA UART + * + * Copyright (C) 2022 Intel Corporation. + * + * Authors: + * Ananda Ravuri + * Matthew Gerlach + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 + +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 +#define DFHv1_PARAM_REG_LAYOUT_WIDTH GENMASK_ULL(63, 32) +#define DFHv1_PARAM_REG_LAYOUT_SHIFT GENMASK_ULL(31, 0) + +struct dfl_uart { + int line; +}; + +static int dfh_get_u64_param_val(struct dfl_device *dfl_dev, int param_id, u64 *pval) +{ + size_t psize; + u64 *p; + + p = dfh_find_param(dfl_dev, param_id, &psize); + if (IS_ERR(p)) + return PTR_ERR(p); + + if (psize != sizeof(*pval)) + return -EINVAL; + + *pval = *p; + + return 0; +} + +static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) +{ + struct device *dev = &dfl_dev->dev; + u64 fifo_len, clk_freq, reg_layout; + u32 reg_width; + int ret; + + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ, &clk_freq); + if (ret) + return dev_err_probe(dev, ret, "missing CLK_FRQ param\n"); + + uart->port.uartclk = clk_freq; + + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN, &fifo_len); + if (ret) + return dev_err_probe(dev, ret, "missing FIFO_LEN param\n"); + + switch (fifo_len) { + case 32: + uart->port.type = PORT_ALTR_16550_F32; + break; + + case 64: + uart->port.type = PORT_ALTR_16550_F64; + break; + + case 128: + uart->port.type = PORT_ALTR_16550_F128; + break; + + default: + return dev_err_probe(dev, -EINVAL, "unsupported FIFO_LEN %llu\n", fifo_len); + } + + ret = dfh_get_u64_param_val(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT, ®_layout); + if (ret) + return dev_err_probe(dev, ret, "missing REG_LAYOUT param\n"); + + uart->port.regshift = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_SHIFT, reg_layout); + reg_width = FIELD_GET(DFHv1_PARAM_REG_LAYOUT_WIDTH, reg_layout); + switch (reg_width) { + case 4: + uart->port.iotype = UPIO_MEM32; + break; + + case 2: + uart->port.iotype = UPIO_MEM16; + break; + + default: + return dev_err_probe(dev, -EINVAL, "unsupported reg-width %u\n", reg_width); + + } + + return 0; +} + +static int dfl_uart_probe(struct dfl_device *dfl_dev) +{ + struct device *dev = &dfl_dev->dev; + struct uart_8250_port uart = { }; + struct dfl_uart *dfluart; + int ret; + + uart.port.flags = UPF_IOREMAP; + uart.port.mapbase = dfl_dev->mmio_res.start; + uart.port.mapsize = resource_size(&dfl_dev->mmio_res); + + ret = dfl_uart_get_params(dfl_dev, &uart); + if (ret < 0) + return dev_err_probe(dev, ret, "failed uart feature walk\n"); + + if (dfl_dev->num_irqs == 1) + uart.port.irq = dfl_dev->irqs[0]; + + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); + if (!dfluart) + return -ENOMEM; + + dfluart->line = serial8250_register_8250_port(&uart); + if (dfluart->line < 0) + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n"); + + dev_set_drvdata(dev, dfluart); + + return 0; +} + +static void dfl_uart_remove(struct dfl_device *dfl_dev) +{ + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); + + serial8250_unregister_port(dfluart->line); +} + +#define FME_FEATURE_ID_UART 0x24 + +static const struct dfl_device_id dfl_uart_ids[] = { + { FME_ID, FME_FEATURE_ID_UART }, + { } +}; +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); + +static struct dfl_driver dfl_uart_driver = { + .drv = { + .name = "dfl-uart", + }, + .id_table = dfl_uart_ids, + .probe = dfl_uart_probe, + .remove = dfl_uart_remove, +}; +module_dfl_driver(dfl_uart_driver); + +MODULE_DESCRIPTION("DFL Intel UART driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index f271becfc46c..0ebde0ab8167 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c @@ -136,11 +136,11 @@ static void __init init_port(struct earlycon_device *device) unsigned char c; unsigned int ier; - serial8250_early_out(port, UART_LCR, 0x3); /* 8n1 */ + serial8250_early_out(port, UART_LCR, UART_LCR_WLEN8); /* 8n1 */ ier = serial8250_early_in(port, UART_IER); serial8250_early_out(port, UART_IER, ier & UART_IER_UUE); /* no interrupt */ serial8250_early_out(port, UART_FCR, 0); /* no fifo */ - serial8250_early_out(port, UART_MCR, 0x3); /* DTR + RTS */ + serial8250_early_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS); if (port->uartclk) { divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud); diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 8e9f247590bd..c55be6fda0ca 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -24,6 +24,7 @@ #include #include "8250.h" +#include "8250_pcilib.h" /* * init function returns: @@ -89,28 +90,7 @@ static int setup_port(struct serial_private *priv, struct uart_8250_port *port, u8 bar, unsigned int offset, int regshift) { - struct pci_dev *dev = priv->dev; - - if (bar >= PCI_STD_NUM_BARS) - return -EINVAL; - - if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { - if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) - return -ENOMEM; - - port->port.iotype = UPIO_MEM; - port->port.iobase = 0; - port->port.mapbase = pci_resource_start(dev, bar) + offset; - port->port.membase = pcim_iomap_table(dev)[bar] + offset; - port->port.regshift = regshift; - } else { - port->port.iotype = UPIO_PORT; - port->port.iobase = pci_resource_start(dev, bar) + offset; - port->port.mapbase = 0; - port->port.membase = NULL; - port->port.regshift = 0; - } - return 0; + return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); } /* @@ -5757,3 +5737,4 @@ module_pci_driver(serial_pci_driver); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); MODULE_DEVICE_TABLE(pci, serial_pci_tbl); +MODULE_IMPORT_NS(SERIAL_8250_PCI); diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c new file mode 100644 index 000000000000..a3b25779d921 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Probe module for 8250/16550-type MCHP PCI serial ports. + * + * Based on drivers/tty/serial/8250/8250_pci.c, + * + * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "8250.h" +#include "8250_pcilib.h" + +#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 +#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 +#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 +#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 +#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 + +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f + +#define PCI_SUBDEVICE_ID_EFAR_PCI12000 PCI_DEVICE_ID_EFAR_PCI12000 +#define PCI_SUBDEVICE_ID_EFAR_PCI11010 PCI_DEVICE_ID_EFAR_PCI11010 +#define PCI_SUBDEVICE_ID_EFAR_PCI11101 PCI_DEVICE_ID_EFAR_PCI11101 +#define PCI_SUBDEVICE_ID_EFAR_PCI11400 PCI_DEVICE_ID_EFAR_PCI11400 +#define PCI_SUBDEVICE_ID_EFAR_PCI11414 PCI_DEVICE_ID_EFAR_PCI11414 + +#define UART_ACTV_REG 0x11 +#define UART_BLOCK_SET_ACTIVE BIT(0) + +#define UART_PCI_CTRL_REG 0x80 +#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) +#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) + +#define ADCL_CFG_REG 0x40 +#define ADCL_CFG_POL_SEL BIT(2) +#define ADCL_CFG_PIN_SEL BIT(1) +#define ADCL_CFG_EN BIT(0) + +#define UART_BIT_SAMPLE_CNT 16 +#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) +#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) +#define UART_CLOCK_DEFAULT (62500 * HZ_PER_KHZ) + +#define UART_WAKE_REG 0x8C +#define UART_WAKE_MASK_REG 0x90 +#define UART_WAKE_N_PIN BIT(2) +#define UART_WAKE_NCTS BIT(1) +#define UART_WAKE_INT BIT(0) +#define UART_WAKE_SRCS \ + (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) + +#define UART_BAUD_CLK_DIVISOR_REG 0x54 + +#define UART_RESET_REG 0x94 +#define UART_RESET_D3_RESET_DISABLE BIT(16) + +#define MAX_PORTS 4 +#define PORT_OFFSET 0x100 + +static const int logical_to_physical_port_idx[][MAX_PORTS] = { + {0, 1, 2, 3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */ + {0, 1, 2, 3}, /* PCI4p */ + {0, 1, 2, -1}, /* PCI3p012 */ + {0, 1, 3, -1}, /* PCI3p013 */ + {0, 2, 3, -1}, /* PCI3p023 */ + {1, 2, 3, -1}, /* PCI3p123 */ + {0, 1, -1, -1}, /* PCI2p01 */ + {0, 2, -1, -1}, /* PCI2p02 */ + {0, 3, -1, -1}, /* PCI2p03 */ + {1, 2, -1, -1}, /* PCI2p12 */ + {1, 3, -1, -1}, /* PCI2p13 */ + {2, 3, -1, -1}, /* PCI2p23 */ + {0, -1, -1, -1}, /* PCI1p0 */ + {1, -1, -1, -1}, /* PCI1p1 */ + {2, -1, -1, -1}, /* PCI1p2 */ + {3, -1, -1, -1}, /* PCI1p3 */ +}; + +struct pci1xxxx_8250 { + unsigned int nr; + void __iomem *membase; + int line[]; +}; + +static int pci1xxxx_get_num_ports(struct pci_dev *dev) +{ + switch (dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + case PCI_SUBDEVICE_ID_EFAR_PCI12000: + case PCI_SUBDEVICE_ID_EFAR_PCI11010: + case PCI_SUBDEVICE_ID_EFAR_PCI11101: + case PCI_SUBDEVICE_ID_EFAR_PCI11400: + default: + return 1; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + return 2; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + return 3; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: + case PCI_SUBDEVICE_ID_EFAR_PCI11414: + return 4; + } +} + +static unsigned int pci1xxxx_get_divisor(struct uart_port *port, + unsigned int baud, unsigned int *frac) +{ + unsigned int quot; + + /* + * Calculate baud rate sampling period in nanoseconds. + * Fractional part x denotes x/255 parts of a nanosecond. + */ + quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT); + *frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) * + 255 / UART_BIT_SAMPLE_CNT / baud; + + return quot; +} + +static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, + unsigned int quot, unsigned int frac) +{ + writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, + port->membase + UART_BAUD_CLK_DIVISOR_REG); +} + +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 delay_in_baud_periods; + u32 baud_period_in_ns; + u32 mode_cfg = 0; + u32 clock_div; + + /* + * pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + mode_cfg |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + rs485->delay_rts_after_send * NSEC_PER_MSEC / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u32, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + baud_period_in_ns * delay_in_baud_periods / + NSEC_PER_MSEC; + } + } + writel(mode_cfg, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + +static bool pci1xxxx_port_suspend(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + bool ret = false; + u8 wakeup_mask; + + mutex_lock(&tport->mutex); + if (port->suspended == 0 && port->dev) { + wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); + + spin_lock_irqsave(&port->lock, flags); + port->mctrl &= ~TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + + ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; + } + + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + mutex_unlock(&tport->mutex); + + return ret; +} + +static void pci1xxxx_port_resume(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + + mutex_lock(&tport->mutex); + writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + + if (port->suspended == 0) { + spin_lock_irqsave(&port->lock, flags); + port->mctrl |= TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + } + mutex_unlock(&tport->mutex); +} + +static int pci1xxxx_suspend(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + bool wakeup = false; + unsigned int data; + void __iomem *p; + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + serial8250_suspend_port(priv->line[i]); + wakeup |= pci1xxxx_port_suspend(priv->line[i]); + } + } + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + + if (wakeup) + writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); + + iounmap(p); + device_set_wakeup_enable(dev, true); + pci_wake_from_d3(pcidev, true); + + return 0; +} + +static int pci1xxxx_resume(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + unsigned int data; + void __iomem *p; + int i; + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + iounmap(p); + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + pci1xxxx_port_resume(priv->line[i]); + serial8250_resume_port(priv->line[i]); + } + } + + return 0; +} + +static int pci1xxxx_setup(struct pci_dev *pdev, + struct uart_8250_port *port, int port_idx) +{ + int ret; + + port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; + port->port.type = PORT_MCHP16550A; + port->port.set_termios = serial8250_do_set_termios; + port->port.get_divisor = pci1xxxx_get_divisor; + port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; + + ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); + if (ret < 0) + return ret; + + writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); + writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); + + return 0; +} + +static unsigned int pci1xxxx_get_max_port(int subsys_dev) +{ + unsigned int i = MAX_PORTS; + + if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) + while (i--) { + if (logical_to_physical_port_idx[subsys_dev][i] != -1) + return logical_to_physical_port_idx[subsys_dev][i] + 1; + } + + if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414) + return 4; + + return 1; +} + +static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port) +{ + if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx)) + return logical_to_physical_port_idx[subsys_dev][port]; + + return logical_to_physical_port_idx[0][port]; +} + +static int pci1xxxx_serial_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct device *dev = &pdev->dev; + struct pci1xxxx_8250 *priv; + struct uart_8250_port uart; + unsigned int max_vec_reqd; + unsigned int nr_ports, i; + int num_vectors; + int subsys_dev; + int port_idx; + int rc; + + rc = pcim_enable_device(pdev); + if (rc) + return rc; + + nr_ports = pci1xxxx_get_num_ports(pdev); + + priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->membase = pci_ioremap_bar(pdev, 0); + if (!priv->membase) + return -ENOMEM; + + pci_set_master(pdev); + + priv->nr = nr_ports; + + subsys_dev = pdev->subsystem_device; + max_vec_reqd = pci1xxxx_get_max_port(subsys_dev); + + num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES); + if (num_vectors < 0) { + pci_iounmap(pdev, priv->membase); + return num_vectors; + } + + memset(&uart, 0, sizeof(uart)); + uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; + uart.port.uartclk = UART_CLOCK_DEFAULT; + uart.port.dev = dev; + + if (num_vectors == max_vec_reqd) + writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); + + for (i = 0; i < nr_ports; i++) { + priv->line[i] = -ENODEV; + + port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i); + + if (num_vectors == max_vec_reqd) + uart.port.irq = pci_irq_vector(pdev, port_idx); + else + uart.port.irq = pci_irq_vector(pdev, 0); + + rc = pci1xxxx_setup(pdev, &uart, port_idx); + if (rc) { + dev_warn(dev, "Failed to setup port %u\n", i); + continue; + } + + priv->line[i] = serial8250_register_8250_port(&uart); + if (priv->line[i] < 0) { + dev_warn(dev, + "Couldn't register serial port %lx, irq %d, type %d, error %d\n", + uart.port.iobase, uart.port.irq, uart.port.iotype, + priv->line[i]); + } + } + + pci_set_drvdata(pdev, priv); + + return 0; +} + +static void pci1xxxx_serial_remove(struct pci_dev *dev) +{ + struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); + unsigned int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) + serial8250_unregister_port(priv->line[i]); + } + + pci_free_irq_vectors(dev); + pci_iounmap(dev, priv->membase); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume); + +static const struct pci_device_id pci1xxxx_pci_tbl[] = { + { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, + { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, + { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, + { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, + { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, + {} +}; +MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); + +static struct pci_driver pci1xxxx_pci_driver = { + .name = "pci1xxxx serial", + .probe = pci1xxxx_serial_probe, + .remove = pci1xxxx_serial_remove, + .driver = { + .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), + }, + .id_table = pci1xxxx_pci_tbl, +}; +module_pci_driver(pci1xxxx_pci_driver); + +static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1)); + +MODULE_IMPORT_NS(SERIAL_8250_PCI); +MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); +MODULE_AUTHOR("Kumaravel Thiagarajan "); +MODULE_AUTHOR("Tharun Kumar P "); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/8250_pcilib.c b/drivers/tty/serial/8250/8250_pcilib.c new file mode 100644 index 000000000000..d234e9194feb --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * 8250 PCI library. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ +#include +#include +#include +#include + +#include "8250.h" +#include "8250_pcilib.h" + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, + u8 bar, unsigned int offset, int regshift) +{ + if (bar >= PCI_STD_NUM_BARS) + return -EINVAL; + + if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { + if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) + return -ENOMEM; + + port->port.iotype = UPIO_MEM; + port->port.iobase = 0; + port->port.mapbase = pci_resource_start(dev, bar) + offset; + port->port.membase = pcim_iomap_table(dev)[bar] + offset; + port->port.regshift = regshift; + } else { + port->port.iotype = UPIO_PORT; + port->port.iobase = pci_resource_start(dev, bar) + offset; + port->port.mapbase = 0; + port->port.membase = NULL; + port->port.regshift = 0; + } + return 0; +} +EXPORT_SYMBOL_NS_GPL(serial8250_pci_setup_port, SERIAL_8250_PCI); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/8250_pcilib.h b/drivers/tty/serial/8250/8250_pcilib.h new file mode 100644 index 000000000000..1aaf1b50ce9c --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * 8250 PCI library header file. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ + +#include + +struct pci_dev; + +struct uart_8250_port; + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, u8 bar, + unsigned int offset, int regshift); diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index beba8f38b3dc..fa43df05342b 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -313,6 +313,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 4, 8, 14}, .flags = UART_CAP_FIFO, }, + [PORT_MCHP16550A] = { + .name = "MCHP16550A", + .fifo_size = 256, + .tx_loadsz = 256, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, + .rxtrig_bytes = {2, 66, 130, 194}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ @@ -1050,11 +1058,12 @@ static void autoconfig_16550a(struct uart_8250_port *up) serial_out(up, UART_LCR, 0); serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); - status1 = serial_in(up, UART_IIR) >> 5; + status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | + UART_IIR_FIFO_ENABLED); serial_out(up, UART_FCR, 0); serial_out(up, UART_LCR, 0); - if (status1 == 7) + if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED)) up->port.type = PORT_16550A_FSL64; else DEBUG_AUTOCONF("Motorola 8xxx DUART "); @@ -1122,17 +1131,20 @@ static void autoconfig_16550a(struct uart_8250_port *up) */ serial_out(up, UART_LCR, 0); serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); - status1 = serial_in(up, UART_IIR) >> 5; + status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED); serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); - status2 = serial_in(up, UART_IIR) >> 5; + status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED); serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); + serial_out(up, UART_LCR, 0); DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); - if (status1 == 6 && status2 == 7) { + if (status1 == UART_IIR_FIFO_ENABLED_16550A && + status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) { up->port.type = PORT_16750; up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; return; @@ -1236,14 +1248,14 @@ static void autoconfig(struct uart_8250_port *up) * Mask out IER[7:4] bits for test as some UARTs (e.g. TL * 16C754B) allow only to modify them if an EFR bit is set. */ - scratch2 = serial_in(up, UART_IER) & 0x0f; - serial_out(up, UART_IER, 0x0F); + scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR; + serial_out(up, UART_IER, UART_IER_ALL_INTR); #ifdef __i386__ outb(0, 0x080); #endif - scratch3 = serial_in(up, UART_IER) & 0x0f; + scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR; serial_out(up, UART_IER, scratch); - if (scratch2 != 0 || scratch3 != 0x0F) { + if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) { /* * We failed; there's nothing here */ @@ -1267,10 +1279,10 @@ static void autoconfig(struct uart_8250_port *up) * that conflicts with COM 1-4 --- we hope! */ if (!(port->flags & UPF_SKIP_TEST)) { - serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A); - status1 = serial_in(up, UART_MSR) & 0xF0; + serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS); + status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS; serial8250_out_MCR(up, save_mcr); - if (status1 != 0x90) { + if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) { spin_unlock_irqrestore(&port->lock, flags); DEBUG_AUTOCONF("LOOP test failed (%02x) ", status1); @@ -1293,22 +1305,19 @@ static void autoconfig(struct uart_8250_port *up) serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); - /* Assign this as it is to truncate any bits above 7. */ - scratch = serial_in(up, UART_IIR); - - switch (scratch >> 6) { - case 0: + switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) { + case UART_IIR_FIFO_ENABLED_8250: autoconfig_8250(up); break; - case 1: - port->type = PORT_UNKNOWN; - break; - case 2: + case UART_IIR_FIFO_ENABLED_16550: port->type = PORT_16550; break; - case 3: + case UART_IIR_FIFO_ENABLED_16550A: autoconfig_16550a(up); break; + default: + port->type = PORT_UNKNOWN; + break; } #ifdef CONFIG_SERIAL_8250_RSA @@ -1394,7 +1403,7 @@ static void autoconfig_irq(struct uart_8250_port *up) serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); } - serial_out(up, UART_IER, 0x0f); /* enable all intrs */ + serial_out(up, UART_IER, UART_IER_ALL_INTR); serial_in(up, UART_LSR); serial_in(up, UART_RX); serial_in(up, UART_IIR); @@ -1511,8 +1520,6 @@ static inline void __stop_tx(struct uart_8250_port *p) u16 lsr = serial_lsr_in(p); u64 stop_delay = 0; - p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; - if (!(lsr & UART_LSR_THRE)) return; /* diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index b0f62345bc84..978dc196c29b 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -129,9 +129,13 @@ config SERIAL_8250_DMA This builds DMA support that can be used with 8250/16650 compatible UART controllers that support DMA signaling. +config SERIAL_8250_PCILIB + bool + config SERIAL_8250_PCI tristate "8250/16550 PCI device support" depends on SERIAL_8250 && PCI + select SERIAL_8250_PCILIB default SERIAL_8250 help This builds standard PCI serial support. You may be able to @@ -291,6 +295,17 @@ config SERIAL_8250_HUB6 To compile this driver as a module, choose M here: the module will be called 8250_hub6. +config SERIAL_8250_PCI1XXXX + tristate "Microchip 8250 based serial port" + depends on SERIAL_8250 && PCI + select SERIAL_8250_PCILIB + default SERIAL_8250 + help + Select this option if you have a setup with Microchip PCIe + Switch with serial port enabled and wish to enable 8250 + serial driver for the serial interface. This driver support + will ensure to support baud rates upto 1.5Mpbs. + # # Misc. options/drivers. # @@ -370,6 +385,18 @@ config SERIAL_8250_FSL erratum for Freescale 16550 UARTs in the 8250 driver. It also enables support for ACPI enumeration. +config SERIAL_8250_DFL + tristate "DFL bus driver for Altera 16550 UART" + depends on SERIAL_8250 && FPGA_DFL + help + This option enables support for a Device Feature List (DFL) bus + driver for the Altera 16550 UART. One or more Altera 16550 UARTs + can be instantiated in a FPGA and then be discovered during + enumeration of the DFL bus. + + To compile this driver as a module, chose M here: the + module will be called 8250_dfl. + config SERIAL_8250_DW tristate "Support for Synopsys DesignWare 8250 quirks" depends on SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index 1615bfdde2a0..4fc2fc1f41b6 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o 8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o +8250_base-$(CONFIG_SERIAL_8250_PCILIB) += 8250_pcilib.o obj-$(CONFIG_SERIAL_8250_PARISC) += 8250_parisc.o obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o @@ -26,8 +27,10 @@ obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o +obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 659cab64d94e..dd3f43fbb7f6 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -73,17 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE your boot loader (lilo or loadlin) about how to pass options to the kernel at boot time.) -config SERIAL_EARLYCON_ARM_SEMIHOST - bool "Early console using ARM semihosting" - depends on ARM64 || ARM +config SERIAL_EARLYCON_SEMIHOST + bool "Early console using Arm compatible semihosting" + depends on ARM64 || ARM || RISCV select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON help - Support for early debug console using ARM semihosting. This enables - the console before standard serial driver is probed. This is enabled - with "earlycon=smh" on the kernel command line. The console is - enabled when early_param is processed. + Support for early debug console using Arm compatible semihosting. + This enables the console before standard serial driver is probed. + This is enabled with "earlycon=smh" on the kernel command line. + The console is enabled when early_param is processed. config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" @@ -1506,7 +1506,7 @@ config SERIAL_MILBEAUT_USIO_CONSOLE config SERIAL_LITEUART tristate "LiteUART serial port support" depends on HAS_IOMEM - depends on OF || COMPILE_TEST + depends on OF depends on LITEX || COMPILE_TEST select SERIAL_CORE help diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 238a9557b487..cd9afd9e3018 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_SERIAL_CORE) += serial_core.o obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o -obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o +obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o # These Sparc drivers have to appear before others such as 8250 diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-semihost.c similarity index 57% rename from drivers/tty/serial/earlycon-arm-semihost.c rename to drivers/tty/serial/earlycon-semihost.c index fcdec5f42376..e4692a8433f9 100644 --- a/drivers/tty/serial/earlycon-arm-semihost.c +++ b/drivers/tty/serial/earlycon-semihost.c @@ -11,30 +11,7 @@ #include #include #include - -#ifdef CONFIG_THUMB2_KERNEL -#define SEMIHOST_SWI "0xab" -#else -#define SEMIHOST_SWI "0x123456" -#endif - -/* - * Semihosting-based debug console - */ -static void smh_putc(struct uart_port *port, unsigned char c) -{ -#ifdef CONFIG_ARM64 - asm volatile("mov x1, %0\n" - "mov x0, #3\n" - "hlt 0xf000\n" - : : "r" (&c) : "x0", "x1", "memory"); -#else - asm volatile("mov r1, %0\n" - "mov r0, #3\n" - "svc " SEMIHOST_SWI "\n" - : : "r" (&c) : "r0", "r1", "memory"); -#endif -} +#include static void smh_write(struct console *con, const char *s, unsigned n) { diff --git a/drivers/tty/serial/earlycon.c b/drivers/tty/serial/earlycon.c index 4f6e9bf57169..a5fbb6ed38ae 100644 --- a/drivers/tty/serial/earlycon.c +++ b/drivers/tty/serial/earlycon.c @@ -120,7 +120,13 @@ static int __init parse_options(struct earlycon_device *device, char *options) } if (options) { + char *uartclk; + device->baud = simple_strtoul(options, NULL, 0); + uartclk = strchr(options, ','); + if (uartclk && kstrtouint(uartclk + 1, 0, &port->uartclk) < 0) + pr_warn("[%s] unsupported earlycon uart clkrate option\n", + options); length = min(strcspn(options, " ") + 1, (size_t)(sizeof(device->options))); strscpy(device->options, options, length); @@ -139,7 +145,8 @@ static int __init register_earlycon(char *buf, const struct earlycon_id *match) buf = NULL; spin_lock_init(&port->lock); - port->uartclk = BASE_BAUD * 16; + if (!port->uartclk) + port->uartclk = BASE_BAUD * 16; if (port->mapbase) port->membase = earlycon_map(port->mapbase, 64); diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 5e69fb73f570..e945f41b93d4 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -5,6 +5,8 @@ * Copyright 2012-2014 Freescale Semiconductor, Inc. */ +#include +#include #include #include #include @@ -181,7 +183,7 @@ #define UARTCTRL_SBK 0x00010000 #define UARTCTRL_MA1IE 0x00008000 #define UARTCTRL_MA2IE 0x00004000 -#define UARTCTRL_IDLECFG 0x00000100 +#define UARTCTRL_IDLECFG GENMASK(10, 8) #define UARTCTRL_LOOPS 0x00000080 #define UARTCTRL_DOZEEN 0x00000040 #define UARTCTRL_RSRC 0x00000020 @@ -199,6 +201,7 @@ #define UARTDATA_MASK 0x3ff #define UARTMODIR_IREN 0x00020000 +#define UARTMODIR_RTSWATER GENMASK(10, 8) #define UARTMODIR_TXCTSSRC 0x00000020 #define UARTMODIR_TXCTSC 0x00000010 #define UARTMODIR_RXRTSE 0x00000008 @@ -212,6 +215,7 @@ #define UARTFIFO_RXUF 0x00010000 #define UARTFIFO_TXFLUSH 0x00008000 #define UARTFIFO_RXFLUSH 0x00004000 +#define UARTFIFO_RXIDEN GENMASK(12, 10) #define UARTFIFO_TXOFE 0x00000200 #define UARTFIFO_RXUFE 0x00000100 #define UARTFIFO_TXFE 0x00000080 @@ -238,7 +242,7 @@ #define DRIVER_NAME "fsl-lpuart" #define DEV_NAME "ttyLP" -#define UART_NR 6 +#define UART_NR 8 /* IMX lpuart has four extra unused regs located at the beginning */ #define IMX_REG_OFF 0x10 @@ -248,6 +252,7 @@ enum lpuart_type { LS1021A_LPUART, LS1028A_LPUART, IMX7ULP_LPUART, + IMX8ULP_LPUART, IMX8QXP_LPUART, IMXRT1050_LPUART, }; @@ -260,6 +265,7 @@ struct lpuart_port { unsigned int txfifo_size; unsigned int rxfifo_size; + u8 rx_watermark; bool lpuart_dma_tx_use; bool lpuart_dma_rx_use; struct dma_chan *dma_tx_chan; @@ -286,38 +292,52 @@ struct lpuart_soc_data { enum lpuart_type devtype; char iotype; u8 reg_off; + u8 rx_watermark; }; static const struct lpuart_soc_data vf_data = { .devtype = VF610_LPUART, .iotype = UPIO_MEM, + .rx_watermark = 1, }; static const struct lpuart_soc_data ls1021a_data = { .devtype = LS1021A_LPUART, .iotype = UPIO_MEM32BE, + .rx_watermark = 1, }; static const struct lpuart_soc_data ls1028a_data = { .devtype = LS1028A_LPUART, .iotype = UPIO_MEM32, + .rx_watermark = 1, }; static struct lpuart_soc_data imx7ulp_data = { .devtype = IMX7ULP_LPUART, .iotype = UPIO_MEM32, .reg_off = IMX_REG_OFF, + .rx_watermark = 1, +}; + +static struct lpuart_soc_data imx8ulp_data = { + .devtype = IMX8ULP_LPUART, + .iotype = UPIO_MEM32, + .reg_off = IMX_REG_OFF, + .rx_watermark = 3, }; static struct lpuart_soc_data imx8qxp_data = { .devtype = IMX8QXP_LPUART, .iotype = UPIO_MEM32, .reg_off = IMX_REG_OFF, + .rx_watermark = 31, }; static struct lpuart_soc_data imxrt1050_data = { .devtype = IMXRT1050_LPUART, .iotype = UPIO_MEM32, .reg_off = IMX_REG_OFF, + .rx_watermark = 1, }; static const struct of_device_id lpuart_dt_ids[] = { @@ -325,6 +345,7 @@ static const struct of_device_id lpuart_dt_ids[] = { { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, + { .compatible = "fsl,imx8ulp-lpuart", .data = &imx8ulp_data, }, { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data}, { /* sentinel */ } @@ -345,6 +366,11 @@ static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport) return sport->devtype == IMX7ULP_LPUART; } +static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport) +{ + return sport->devtype == IMX8ULP_LPUART; +} + static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) { return sport->devtype == IMX8QXP_LPUART; @@ -1387,9 +1413,9 @@ static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termio * Note: UART is assumed to be active high. */ if (rs485->flags & SER_RS485_RTS_ON_SEND) - modem &= ~UARTMODEM_TXRTSPOL; - else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) modem |= UARTMODEM_TXRTSPOL; + else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) + modem &= ~UARTMODEM_TXRTSPOL; } lpuart32_write(&sport->port, modem, UARTMODIR); @@ -1462,12 +1488,32 @@ static void lpuart_break_ctl(struct uart_port *port, int break_state) static void lpuart32_break_ctl(struct uart_port *port, int break_state) { - unsigned long temp; + unsigned long temp, modem; + struct tty_struct *tty; + unsigned int cflag = 0; + + tty = tty_port_tty_get(&port->state->port); + if (tty) { + cflag = tty->termios.c_cflag; + tty_kref_put(tty); + } temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; + modem = lpuart32_read(port, UARTMODIR); - if (break_state != 0) + if (break_state != 0) { temp |= UARTCTRL_SBK; + /* + * LPUART CTS has higher priority than SBK, need to disable CTS before + * asserting SBK to avoid any interference if flow control is enabled. + */ + if (cflag & CRTSCTS && modem & UARTMODIR_TXCTSE) + lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); + } else { + /* Re-enable the CTS when break off. */ + if (cflag & CRTSCTS && !(modem & UARTMODIR_TXCTSE)) + lpuart32_write(port, modem | UARTMODIR_TXCTSE, UARTMODIR); + } lpuart32_write(port, temp, UARTCTRL); } @@ -1497,8 +1543,10 @@ static void lpuart_setup_watermark(struct lpuart_port *sport) writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); } + if (uart_console(&sport->port)) + sport->rx_watermark = 1; writeb(0, sport->port.membase + UARTTWFIFO); - writeb(1, sport->port.membase + UARTRWFIFO); + writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO); /* Restore cr2 */ writeb(cr2_saved, sport->port.membase + UARTCR2); @@ -1523,19 +1571,30 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport) ctrl = lpuart32_read(&sport->port, UARTCTRL); ctrl_saved = ctrl; ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | - UARTCTRL_RIE | UARTCTRL_RE); + UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE); lpuart32_write(&sport->port, ctrl, UARTCTRL); /* enable FIFO mode */ val = lpuart32_read(&sport->port, UARTFIFO); val |= UARTFIFO_TXFE | UARTFIFO_RXFE; val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; + val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3); lpuart32_write(&sport->port, val, UARTFIFO); /* set the watermark */ - val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); + if (uart_console(&sport->port)) + sport->rx_watermark = 1; + val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) | + (0x0 << UARTWATER_TXWATER_OFF); lpuart32_write(&sport->port, val, UARTWATER); + /* set RTS watermark */ + if (!uart_console(&sport->port)) { + val = lpuart32_read(&sport->port, UARTMODIR); + val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1); + lpuart32_write(&sport->port, val, UARTMODIR); + } + /* Restore cr2 */ lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); } @@ -1547,7 +1606,8 @@ static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) lpuart32_setup_watermark(sport); temp = lpuart32_read(&sport->port, UARTCTRL); - temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; + temp |= UARTCTRL_RE | UARTCTRL_TE; + temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7); lpuart32_write(&sport->port, temp, UARTCTRL); } @@ -1679,19 +1739,23 @@ static int lpuart_startup(struct uart_port *port) return 0; } +static void lpuart32_hw_disable(struct lpuart_port *sport) +{ + unsigned long temp; + + temp = lpuart32_read(&sport->port, UARTCTRL); + temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE | + UARTCTRL_TIE | UARTCTRL_TE); + lpuart32_write(&sport->port, temp, UARTCTRL); +} + static void lpuart32_configure(struct lpuart_port *sport) { unsigned long temp; - if (sport->lpuart_dma_rx_use) { - /* RXWATER must be 0 */ - temp = lpuart32_read(&sport->port, UARTWATER); - temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); - lpuart32_write(&sport->port, temp, UARTWATER); - } temp = lpuart32_read(&sport->port, UARTCTRL); if (!sport->lpuart_dma_rx_use) - temp |= UARTCTRL_RIE; + temp |= UARTCTRL_RIE | UARTCTRL_ILIE; if (!sport->lpuart_dma_tx_use) temp |= UARTCTRL_TIE; lpuart32_write(&sport->port, temp, UARTCTRL); @@ -1703,11 +1767,12 @@ static void lpuart32_hw_setup(struct lpuart_port *sport) spin_lock_irqsave(&sport->port.lock, flags); - lpuart32_setup_watermark_enable(sport); + lpuart32_hw_disable(sport); lpuart_rx_dma_startup(sport); lpuart_tx_dma_startup(sport); + lpuart32_setup_watermark_enable(sport); lpuart32_configure(sport); spin_unlock_irqrestore(&sport->port.lock, flags); @@ -1796,10 +1861,19 @@ static void lpuart32_shutdown(struct uart_port *port) spin_lock_irqsave(&port->lock, flags); - /* disable Rx/Tx and interrupts */ + /* clear status */ + temp = lpuart32_read(&sport->port, UARTSTAT); + lpuart32_write(&sport->port, temp, UARTSTAT); + + /* disable Rx/Tx DMA */ + temp = lpuart32_read(port, UARTBAUD); + temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); + lpuart32_write(port, temp, UARTBAUD); + + /* disable Rx/Tx and interrupts and break condition */ temp = lpuart32_read(port, UARTCTRL); - temp &= ~(UARTCTRL_TE | UARTCTRL_RE | - UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); + temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE | + UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); lpuart32_write(port, temp, UARTCTRL); spin_unlock_irqrestore(&port->lock, flags); @@ -2631,7 +2705,7 @@ static int lpuart_global_reset(struct lpuart_port *sport) return ret; } - if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { + if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) { /* * If the transmitter is used by earlycon, wait for transmit engine to * complete and then reset. @@ -2688,6 +2762,7 @@ static int lpuart_probe(struct platform_device *pdev) sport->port.dev = &pdev->dev; sport->port.type = PORT_LPUART; sport->devtype = sdata->devtype; + sport->rx_watermark = sdata->rx_watermark; ret = platform_get_irq(pdev, 0); if (ret < 0) return ret; diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 757825edb0cd..523f296d5747 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -210,12 +210,8 @@ struct imx_port { struct mctrl_gpios *gpios; - /* shadow registers */ - unsigned int ucr1; - unsigned int ucr2; - unsigned int ucr3; - unsigned int ucr4; - unsigned int ufcr; + /* counter to stop 0xff flood */ + int idle_counter; /* DMA fields */ unsigned int dma_is_enabled:1; @@ -273,59 +269,14 @@ static const struct of_device_id imx_uart_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); -static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) +static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) { - switch (offset) { - case UCR1: - sport->ucr1 = val; - break; - case UCR2: - sport->ucr2 = val; - break; - case UCR3: - sport->ucr3 = val; - break; - case UCR4: - sport->ucr4 = val; - break; - case UFCR: - sport->ufcr = val; - break; - default: - break; - } writel(val, sport->port.membase + offset); } -static u32 imx_uart_readl(struct imx_port *sport, u32 offset) +static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset) { - switch (offset) { - case UCR1: - return sport->ucr1; - break; - case UCR2: - /* - * UCR2_SRST is the only bit in the cached registers that might - * differ from the value that was last written. As it only - * automatically becomes one after being cleared, reread - * conditionally. - */ - if (!(sport->ucr2 & UCR2_SRST)) - sport->ucr2 = readl(sport->port.membase + offset); - return sport->ucr2; - break; - case UCR3: - return sport->ucr3; - break; - case UCR4: - return sport->ucr4; - break; - case UFCR: - return sport->ufcr; - break; - default: - return readl(sport->port.membase + offset); - } + return readl(sport->port.membase + offset); } static inline unsigned imx_uart_uts_reg(struct imx_port *sport) @@ -397,6 +348,41 @@ static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec) hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL); } +/* called with port.lock taken and irqs off */ +static void imx_uart_soft_reset(struct imx_port *sport) +{ + int i = 10; + u32 ucr2, ubir, ubmr, uts; + + /* + * According to the Reference Manual description of the UART SRST bit: + * + * "Reset the transmit and receive state machines, + * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD + * and UTS[6-3]". + * + * We don't need to restore the old values from USR1, USR2, URXD and + * UTXD. UBRC is read only, so only save/restore the other three + * registers. + */ + ubir = imx_uart_readl(sport, UBIR); + ubmr = imx_uart_readl(sport, UBMR); + uts = imx_uart_readl(sport, IMX21_UTS); + + ucr2 = imx_uart_readl(sport, UCR2); + imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2); + + while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) + udelay(1); + + /* Restore the registers */ + imx_uart_writel(sport, ubir, UBIR); + imx_uart_writel(sport, ubmr, UBMR); + imx_uart_writel(sport, uts, IMX21_UTS); + + sport->idle_counter = 0; +} + /* called with port.lock taken and irqs off */ static void imx_uart_start_rx(struct uart_port *port) { @@ -476,7 +462,8 @@ static void imx_uart_stop_tx(struct uart_port *port) imx_uart_rts_inactive(sport, &ucr2); imx_uart_writel(sport, ucr2, UCR2); - imx_uart_start_rx(port); + if (!port->rs485_rx_during_tx_gpio) + imx_uart_start_rx(port); sport->tx_state = OFF; } @@ -705,7 +692,8 @@ static void imx_uart_start_tx(struct uart_port *port) imx_uart_rts_inactive(sport, &ucr2); imx_uart_writel(sport, ucr2, UCR2); - if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) + if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) && + !port->rs485_rx_during_tx_gpio) imx_uart_stop_rx(port); sport->tx_state = WAIT_AFTER_RTS; @@ -771,7 +759,7 @@ static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id) imx_uart_writel(sport, USR1_RTSD, USR1); usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; - uart_handle_cts_change(&sport->port, !!usr1); + uart_handle_cts_change(&sport->port, usr1); wake_up_interruptible(&sport->port.state->port.delta_msr_wait); return IRQ_HANDLED; @@ -801,33 +789,73 @@ static irqreturn_t imx_uart_txint(int irq, void *dev_id) return IRQ_HANDLED; } +/* Check if hardware Rx flood is in progress, and issue soft reset to stop it. + * This is to be called from Rx ISRs only when some bytes were actually + * received. + * + * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600 + * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of + * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART + * that is terminated by any activity on RxD line, or could be stopped by + * issuing soft reset to the UART (just stop/start of RX does not help). Note + * that what we do here is sending isolated start bit about 2.4 times shorter + * than it is to be on UART configured baud rate. + */ +static void imx_uart_check_flood(struct imx_port *sport, u32 usr2) +{ + /* To detect hardware 0xff flood we monitor RxD line between RX + * interrupts to isolate "receiving" of char(s) with no activity + * on RxD line, that'd never happen on actual data transfers. + * + * We use USR2_WAKE bit to check for activity on RxD line, but we have a + * race here if we clear USR2_WAKE when receiving of a char is in + * progress, so we might get RX interrupt later with USR2_WAKE bit + * cleared. Note though that as we don't try to clear USR2_WAKE when we + * detected no activity, this race may hide actual activity only once. + * + * Yet another case where receive interrupt may occur without RxD + * activity is expiration of aging timer, so we consider this as well. + * + * We use 'idle_counter' to ensure that we got at least so many RX + * interrupts without any detected activity on RxD line. 2 cases + * described plus 1 to be on the safe side gives us a margin of 3, + * below. In practice I was not able to produce a false positive to + * induce soft reset at regular data transfers even using 1 as the + * margin, so 3 is actually very strong. + * + * We count interrupts, not chars in 'idle-counter' for simplicity. + */ + + if (usr2 & USR2_WAKE) { + imx_uart_writel(sport, USR2_WAKE, USR2); + sport->idle_counter = 0; + } else if (++sport->idle_counter > 3) { + dev_warn(sport->port.dev, "RX flood detected: soft reset."); + imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */ + } +} + static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) { struct imx_port *sport = dev_id; - unsigned int rx, flg, ignored = 0; struct tty_port *port = &sport->port.state->port; + u32 usr2, rx; - while (imx_uart_readl(sport, USR2) & USR2_RDR) { - u32 usr2; + /* If we received something, check for 0xff flood */ + usr2 = imx_uart_readl(sport, USR2); + if (usr2 & USR2_RDR) + imx_uart_check_flood(sport, usr2); - flg = TTY_NORMAL; + while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) { + unsigned int flg = TTY_NORMAL; sport->port.icount.rx++; - rx = imx_uart_readl(sport, URXD0); - - usr2 = imx_uart_readl(sport, USR2); - if (usr2 & USR2_BRCD) { - imx_uart_writel(sport, USR2_BRCD, USR2); - if (uart_handle_break(&sport->port)) - continue; - } - - if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) - continue; - if (unlikely(rx & URXD_ERR)) { - if (rx & URXD_BRK) + if (rx & URXD_BRK) { sport->port.icount.brk++; + if (uart_handle_break(&sport->port)) + continue; + } else if (rx & URXD_PRERR) sport->port.icount.parity++; else if (rx & URXD_FRMERR) @@ -835,11 +863,8 @@ static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) if (rx & URXD_OVRRUN) sport->port.icount.overrun++; - if (rx & sport->port.ignore_status_mask) { - if (++ignored > 100) - goto out; + if (rx & sport->port.ignore_status_mask) continue; - } rx &= (sport->port.read_status_mask | 0xFF); @@ -853,16 +878,17 @@ static irqreturn_t __imx_uart_rxint(int irq, void *dev_id) flg = TTY_OVERRUN; sport->port.sysrq = 0; + } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) { + continue; } if (sport->port.ignore_status_mask & URXD_DUMMY_READ) - goto out; + continue; if (tty_insert_flip_char(port, rx, flg) == 0) sport->port.icount.buf_overrun++; } -out: tty_flip_buffer_push(port); return IRQ_HANDLED; @@ -1147,55 +1173,62 @@ static void imx_uart_dma_rx_callback(void *data) status = dmaengine_tx_status(chan, sport->rx_cookie, &state); if (status == DMA_ERROR) { + spin_lock(&sport->port.lock); imx_uart_clear_rx_errors(sport); + spin_unlock(&sport->port.lock); return; } - if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { + /* + * The state-residue variable represents the empty space + * relative to the entire buffer. Taking this in consideration + * the head is always calculated base on the buffer total + * length - DMA transaction residue. The UART script from the + * SDMA firmware will jump to the next buffer descriptor, + * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). + * Taking this in consideration the tail is always at the + * beginning of the buffer descriptor that contains the head. + */ - /* - * The state-residue variable represents the empty space - * relative to the entire buffer. Taking this in consideration - * the head is always calculated base on the buffer total - * length - DMA transaction residue. The UART script from the - * SDMA firmware will jump to the next buffer descriptor, - * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). - * Taking this in consideration the tail is always at the - * beginning of the buffer descriptor that contains the head. - */ + /* Calculate the head */ + rx_ring->head = sg_dma_len(sgl) - state.residue; - /* Calculate the head */ - rx_ring->head = sg_dma_len(sgl) - state.residue; + /* Calculate the tail. */ + bd_size = sg_dma_len(sgl) / sport->rx_periods; + rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; - /* Calculate the tail. */ - bd_size = sg_dma_len(sgl) / sport->rx_periods; - rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; + if (rx_ring->head <= sg_dma_len(sgl) && + rx_ring->head > rx_ring->tail) { - if (rx_ring->head <= sg_dma_len(sgl) && - rx_ring->head > rx_ring->tail) { + /* Move data from tail to head */ + r_bytes = rx_ring->head - rx_ring->tail; - /* Move data from tail to head */ - r_bytes = rx_ring->head - rx_ring->tail; + /* If we received something, check for 0xff flood */ + spin_lock(&sport->port.lock); + imx_uart_check_flood(sport, imx_uart_readl(sport, USR2)); + spin_unlock(&sport->port.lock); + + if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { /* CPU claims ownership of RX DMA buffer */ dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, - DMA_FROM_DEVICE); + DMA_FROM_DEVICE); w_bytes = tty_insert_flip_string(port, - sport->rx_buf + rx_ring->tail, r_bytes); + sport->rx_buf + rx_ring->tail, r_bytes); /* UART retrieves ownership of RX DMA buffer */ dma_sync_sg_for_device(sport->port.dev, sgl, 1, - DMA_FROM_DEVICE); + DMA_FROM_DEVICE); if (w_bytes != r_bytes) sport->port.icount.buf_overrun++; sport->port.icount.rx += w_bytes; - } else { - WARN_ON(rx_ring->head > sg_dma_len(sgl)); - WARN_ON(rx_ring->head <= rx_ring->tail); } + } else { + WARN_ON(rx_ring->head > sg_dma_len(sgl)); + WARN_ON(rx_ring->head <= rx_ring->tail); } if (w_bytes) { @@ -1271,6 +1304,8 @@ static void imx_uart_clear_rx_errors(struct imx_port *sport) imx_uart_writel(sport, USR2_ORE, USR2); } + sport->idle_counter = 0; + } #define TXTL_DEFAULT 2 /* reset default */ @@ -1398,7 +1433,7 @@ static void imx_uart_disable_dma(struct imx_port *sport) static int imx_uart_startup(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; - int retval, i; + int retval; unsigned long flags; int dma_is_inited = 0; u32 ucr1, ucr2, ucr3, ucr4, uts; @@ -1430,15 +1465,9 @@ static int imx_uart_startup(struct uart_port *port) dma_is_inited = 1; spin_lock_irqsave(&sport->port.lock, flags); + /* Reset fifo's and state machines */ - i = 100; - - ucr2 = imx_uart_readl(sport, UCR2); - ucr2 &= ~UCR2_SRST; - imx_uart_writel(sport, ucr2, UCR2); - - while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) - udelay(1); + imx_uart_soft_reset(sport); /* * Finally, clear and enable interrupts @@ -1564,7 +1593,8 @@ static void imx_uart_shutdown(struct uart_port *port) spin_lock_irqsave(&sport->port.lock, flags); ucr1 = imx_uart_readl(sport, UCR1); - ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | UCR1_ATDMAEN); + ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | + UCR1_ATDMAEN | UCR1_SNDBRK); /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */ if (port->rs485.flags & SER_RS485_ENABLED && port->rs485.flags & SER_RS485_RTS_ON_SEND && @@ -1593,8 +1623,6 @@ static void imx_uart_flush_buffer(struct uart_port *port) { struct imx_port *sport = (struct imx_port *)port; struct scatterlist *sgl = &sport->tx_sgl[0]; - u32 ucr2; - int i = 100, ubir, ubmr, uts; if (!sport->dma_chan_tx) return; @@ -1612,32 +1640,8 @@ static void imx_uart_flush_buffer(struct uart_port *port) sport->dma_is_txing = 0; } - /* - * According to the Reference Manual description of the UART SRST bit: - * - * "Reset the transmit and receive state machines, - * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD - * and UTS[6-3]". - * - * We don't need to restore the old values from USR1, USR2, URXD and - * UTXD. UBRC is read only, so only save/restore the other three - * registers. - */ - ubir = imx_uart_readl(sport, UBIR); - ubmr = imx_uart_readl(sport, UBMR); - uts = imx_uart_readl(sport, IMX21_UTS); + imx_uart_soft_reset(sport); - ucr2 = imx_uart_readl(sport, UCR2); - ucr2 &= ~UCR2_SRST; - imx_uart_writel(sport, ucr2, UCR2); - - while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) - udelay(1); - - /* Restore the registers */ - imx_uart_writel(sport, ubir, UBIR); - imx_uart_writel(sport, ubmr, UBMR); - imx_uart_writel(sport, uts, IMX21_UTS); } static void @@ -1955,6 +1959,10 @@ static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termio rs485conf->flags & SER_RS485_RX_DURING_TX) imx_uart_start_rx(port); + if (port->rs485_rx_during_tx_gpio) + gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, + !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); + return 0; } @@ -2340,13 +2348,6 @@ static int imx_uart_probe(struct platform_device *pdev) return ret; } - /* initialize shadow register values */ - sport->ucr1 = readl(sport->port.membase + UCR1); - sport->ucr2 = readl(sport->port.membase + UCR2); - sport->ucr3 = readl(sport->port.membase + UCR3); - sport->ucr4 = readl(sport->port.membase + UCR4); - sport->ufcr = readl(sport->port.membase + UFCR); - ret = uart_get_rs485_mode(&sport->port); if (ret) { clk_disable_unprepare(sport->clk_ipg); @@ -2374,6 +2375,11 @@ static int imx_uart_probe(struct platform_device *pdev) ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); imx_uart_writel(sport, ucr1, UCR1); + /* Disable Ageing Timer interrupt */ + ucr2 = imx_uart_readl(sport, UCR2); + ucr2 &= ~UCR2_ATEN; + imx_uart_writel(sport, ucr2, UCR2); + /* * In case RS485 is enabled without GPIO RTS control, the UART IP * is used to control CTS signal. Keep both the UART and Receiver diff --git a/drivers/tty/serial/liteuart.c b/drivers/tty/serial/liteuart.c index 062812fe1b09..80de3a42b67b 100644 --- a/drivers/tty/serial/liteuart.c +++ b/drivers/tty/serial/liteuart.c @@ -5,7 +5,9 @@ * Copyright (C) 2019-2020 Antmicro */ +#include #include +#include #include #include #include @@ -38,13 +40,13 @@ #define OFF_EV_ENABLE 0x14 /* events */ -#define EV_TX 0x1 -#define EV_RX 0x2 +#define EV_TX BIT(0) +#define EV_RX BIT(1) struct liteuart_port { struct uart_port port; struct timer_list timer; - u32 id; + u8 irq_reg; }; #define to_liteuart_port(port) container_of(port, struct liteuart_port, port) @@ -57,7 +59,7 @@ static struct console liteuart_console; static struct uart_driver liteuart_driver = { .owner = THIS_MODULE, - .driver_name = "liteuart", + .driver_name = KBUILD_MODNAME, .dev_name = "ttyLXU", .major = 0, .minor = 0, @@ -67,38 +69,95 @@ static struct uart_driver liteuart_driver = { #endif }; -static void liteuart_timer(struct timer_list *t) +static void liteuart_update_irq_reg(struct uart_port *port, bool set, u8 mask) { - struct liteuart_port *uart = from_timer(uart, t, timer); - struct uart_port *port = &uart->port; - unsigned char __iomem *membase = port->membase; - unsigned int flg = TTY_NORMAL; - int ch; - unsigned long status; + struct liteuart_port *uart = to_liteuart_port(port); - while ((status = !litex_read8(membase + OFF_RXEMPTY)) == 1) { + if (set) + uart->irq_reg |= mask; + else + uart->irq_reg &= ~mask; + + if (port->irq) + litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); +} + +static void liteuart_stop_tx(struct uart_port *port) +{ + liteuart_update_irq_reg(port, false, EV_TX); +} + +static void liteuart_start_tx(struct uart_port *port) +{ + liteuart_update_irq_reg(port, true, EV_TX); +} + +static void liteuart_stop_rx(struct uart_port *port) +{ + struct liteuart_port *uart = to_liteuart_port(port); + + /* just delete timer */ + del_timer(&uart->timer); +} + +static void liteuart_rx_chars(struct uart_port *port) +{ + unsigned char __iomem *membase = port->membase; + u8 ch; + + while (!litex_read8(membase + OFF_RXEMPTY)) { ch = litex_read8(membase + OFF_RXTX); port->icount.rx++; /* necessary for RXEMPTY to refresh its value */ - litex_write8(membase + OFF_EV_PENDING, EV_TX | EV_RX); + litex_write8(membase + OFF_EV_PENDING, EV_RX); /* no overflow bits in status */ if (!(uart_handle_sysrq_char(port, ch))) - uart_insert_char(port, status, 0, ch, flg); - - tty_flip_buffer_push(&port->state->port); + uart_insert_char(port, 1, 0, ch, TTY_NORMAL); } - mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); + tty_flip_buffer_push(&port->state->port); } -static void liteuart_putchar(struct uart_port *port, unsigned char ch) +static void liteuart_tx_chars(struct uart_port *port) { - while (litex_read8(port->membase + OFF_TXFULL)) - cpu_relax(); + u8 ch; - litex_write8(port->membase + OFF_RXTX, ch); + uart_port_tx(port, ch, + !litex_read8(port->membase + OFF_TXFULL), + litex_write8(port->membase + OFF_RXTX, ch)); +} + +static irqreturn_t liteuart_interrupt(int irq, void *data) +{ + struct liteuart_port *uart = data; + struct uart_port *port = &uart->port; + unsigned long flags; + u8 isr; + + /* + * if polling, the context would be "in_serving_softirq", so use + * irq[save|restore] spin_lock variants to cover all possibilities + */ + spin_lock_irqsave(&port->lock, flags); + isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg; + if (isr & EV_RX) + liteuart_rx_chars(port); + if (isr & EV_TX) + liteuart_tx_chars(port); + spin_unlock_irqrestore(&port->lock, flags); + + return IRQ_RETVAL(isr); +} + +static void liteuart_timer(struct timer_list *t) +{ + struct liteuart_port *uart = from_timer(uart, t, timer); + struct uart_port *port = &uart->port; + + liteuart_interrupt(0, port); + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); } static unsigned int liteuart_tx_empty(struct uart_port *port) @@ -120,60 +179,49 @@ static unsigned int liteuart_get_mctrl(struct uart_port *port) return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; } -static void liteuart_stop_tx(struct uart_port *port) -{ -} - -static void liteuart_start_tx(struct uart_port *port) -{ - struct circ_buf *xmit = &port->state->xmit; - unsigned char ch; - - if (unlikely(port->x_char)) { - litex_write8(port->membase + OFF_RXTX, port->x_char); - port->icount.tx++; - port->x_char = 0; - } else if (!uart_circ_empty(xmit)) { - while (xmit->head != xmit->tail) { - ch = xmit->buf[xmit->tail]; - uart_xmit_advance(port, 1); - liteuart_putchar(port, ch); - } - } - - if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) - uart_write_wakeup(port); -} - -static void liteuart_stop_rx(struct uart_port *port) -{ - struct liteuart_port *uart = to_liteuart_port(port); - - /* just delete timer */ - del_timer(&uart->timer); -} - -static void liteuart_break_ctl(struct uart_port *port, int break_state) -{ - /* LiteUART doesn't support sending break signal */ -} - static int liteuart_startup(struct uart_port *port) { struct liteuart_port *uart = to_liteuart_port(port); + unsigned long flags; + int ret; - /* disable events */ - litex_write8(port->membase + OFF_EV_ENABLE, 0); + if (port->irq) { + ret = request_irq(port->irq, liteuart_interrupt, 0, + KBUILD_MODNAME, uart); + if (ret) { + dev_warn(port->dev, + "line %d irq %d failed: switch to polling\n", + port->line, port->irq); + port->irq = 0; + } + } - /* prepare timer for polling */ - timer_setup(&uart->timer, liteuart_timer, 0); - mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); + spin_lock_irqsave(&port->lock, flags); + /* only enabling rx irqs during startup */ + liteuart_update_irq_reg(port, true, EV_RX); + spin_unlock_irqrestore(&port->lock, flags); + + if (!port->irq) { + timer_setup(&uart->timer, liteuart_timer, 0); + mod_timer(&uart->timer, jiffies + uart_poll_timeout(port)); + } return 0; } static void liteuart_shutdown(struct uart_port *port) { + struct liteuart_port *uart = to_liteuart_port(port); + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + liteuart_update_irq_reg(port, false, EV_RX | EV_TX); + spin_unlock_irqrestore(&port->lock, flags); + + if (port->irq) + free_irq(port->irq, port); + else + del_timer_sync(&uart->timer); } static void liteuart_set_termios(struct uart_port *port, struct ktermios *new, @@ -196,15 +244,6 @@ static const char *liteuart_type(struct uart_port *port) return "liteuart"; } -static void liteuart_release_port(struct uart_port *port) -{ -} - -static int liteuart_request_port(struct uart_port *port) -{ - return 0; -} - static void liteuart_config_port(struct uart_port *port, int flags) { /* @@ -231,13 +270,10 @@ static const struct uart_ops liteuart_ops = { .stop_tx = liteuart_stop_tx, .start_tx = liteuart_start_tx, .stop_rx = liteuart_stop_rx, - .break_ctl = liteuart_break_ctl, .startup = liteuart_startup, .shutdown = liteuart_shutdown, .set_termios = liteuart_set_termios, .type = liteuart_type, - .release_port = liteuart_release_port, - .request_port = liteuart_request_port, .config_port = liteuart_config_port, .verify_port = liteuart_verify_port, }; @@ -249,6 +285,23 @@ static int liteuart_probe(struct platform_device *pdev) struct xa_limit limit; int dev_id, ret; + uart = devm_kzalloc(&pdev->dev, sizeof(struct liteuart_port), GFP_KERNEL); + if (!uart) + return -ENOMEM; + + port = &uart->port; + + /* get membase */ + port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(port->membase)) + return PTR_ERR(port->membase); + + ret = platform_get_irq_optional(pdev, 0); + if (ret < 0 && ret != -ENXIO) + return ret; + if (ret > 0) + port->irq = ret; + /* look for aliases; auto-enumerate for free index if not found */ dev_id = of_alias_get_id(pdev->dev.of_node, "serial"); if (dev_id < 0) @@ -256,32 +309,16 @@ static int liteuart_probe(struct platform_device *pdev) else limit = XA_LIMIT(dev_id, dev_id); - uart = devm_kzalloc(&pdev->dev, sizeof(struct liteuart_port), GFP_KERNEL); - if (!uart) - return -ENOMEM; - ret = xa_alloc(&liteuart_array, &dev_id, uart, limit, GFP_KERNEL); if (ret) return ret; - uart->id = dev_id; - port = &uart->port; - - /* get membase */ - port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(port->membase)) { - ret = PTR_ERR(port->membase); - goto err_erase_id; - } - /* values not from device tree */ port->dev = &pdev->dev; port->iotype = UPIO_MEM; port->flags = UPF_BOOT_AUTOCONF; port->ops = &liteuart_ops; - port->regshift = 2; port->fifosize = 16; - port->iobase = 1; port->type = PORT_UNKNOWN; port->line = dev_id; spin_lock_init(&port->lock); @@ -295,7 +332,7 @@ static int liteuart_probe(struct platform_device *pdev) return 0; err_erase_id: - xa_erase(&liteuart_array, uart->id); + xa_erase(&liteuart_array, dev_id); return ret; } @@ -303,10 +340,10 @@ err_erase_id: static int liteuart_remove(struct platform_device *pdev) { struct uart_port *port = platform_get_drvdata(pdev); - struct liteuart_port *uart = to_liteuart_port(port); + unsigned int line = port->line; uart_remove_one_port(&liteuart_driver, port); - xa_erase(&liteuart_array, uart->id); + xa_erase(&liteuart_array, line); return 0; } @@ -321,13 +358,21 @@ static struct platform_driver liteuart_platform_driver = { .probe = liteuart_probe, .remove = liteuart_remove, .driver = { - .name = "liteuart", + .name = KBUILD_MODNAME, .of_match_table = liteuart_of_match, }, }; #ifdef CONFIG_SERIAL_LITEUART_CONSOLE +static void liteuart_putchar(struct uart_port *port, unsigned char ch) +{ + while (litex_read8(port->membase + OFF_TXFULL)) + cpu_relax(); + + litex_write8(port->membase + OFF_RXTX, ch); +} + static void liteuart_console_write(struct console *co, const char *s, unsigned int count) { @@ -367,7 +412,7 @@ static int liteuart_console_setup(struct console *co, char *options) } static struct console liteuart_console = { - .name = "liteuart", + .name = KBUILD_MODNAME, .write = liteuart_console_write, .device = uart_console_device, .setup = liteuart_console_setup, @@ -415,12 +460,10 @@ static int __init liteuart_init(void) return res; res = platform_driver_register(&liteuart_platform_driver); - if (res) { + if (res) uart_unregister_driver(&liteuart_driver); - return res; - } - return 0; + return res; } static void __exit liteuart_exit(void) diff --git a/drivers/tty/serial/max3100.c b/drivers/tty/serial/max3100.c index bb74f23251fe..86dcbff8faa3 100644 --- a/drivers/tty/serial/max3100.c +++ b/drivers/tty/serial/max3100.c @@ -247,7 +247,7 @@ static int max3100_handlerx(struct max3100_port *s, u16 rx) cts = (rx & MAX3100_CTS) > 0; if (s->cts != cts) { s->cts = cts; - uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0); + uart_handle_cts_change(&s->port, cts); } return ret; diff --git a/drivers/tty/serial/max310x.c b/drivers/tty/serial/max310x.c index 4eb24e3407f8..e9cacfe7e032 100644 --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c @@ -819,8 +819,7 @@ static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) if (ists & MAX310X_IRQ_CTS_BIT) { lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); - uart_handle_cts_change(port, - !!(lsr & MAX310X_LSR_CTS_BIT)); + uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); } if (rxlen) max310x_handle_rx(port, rxlen); diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c index 843798e63084..90953e679e38 100644 --- a/drivers/tty/serial/msm_serial.c +++ b/drivers/tty/serial/msm_serial.c @@ -1120,6 +1120,7 @@ msm_find_best_baud(struct uart_port *port, unsigned int baud, static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, unsigned long *saved_flags) + __must_hold(&port->lock) { unsigned int rxstale, watermark, mask; struct msm_port *msm_port = to_msm_port(port); diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c index 9576ba8bbc40..cc83b772b7ca 100644 --- a/drivers/tty/serial/pch_uart.c +++ b/drivers/tty/serial/pch_uart.c @@ -1775,7 +1775,7 @@ static void pch_uart_exit_port(struct eg20t_port *priv) char name[32]; snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); - debugfs_remove(debugfs_lookup(name, NULL)); + debugfs_lookup_and_remove(name, NULL); uart_remove_one_port(&pch_uart_driver, &priv->port); free_page((unsigned long)priv->rxbuf.buf); } diff --git a/drivers/tty/serial/pic32_uart.c b/drivers/tty/serial/pic32_uart.c index ba3435263c1f..196a4e678451 100644 --- a/drivers/tty/serial/pic32_uart.c +++ b/drivers/tty/serial/pic32_uart.c @@ -889,6 +889,8 @@ static int pic32_uart_probe(struct platform_device *pdev) sport->irq_rx = irq_of_parse_and_map(np, 1); sport->irq_tx = irq_of_parse_and_map(np, 2); sport->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sport->clk)) + return PTR_ERR(sport->clk); sport->dev = &pdev->dev; /* Hardware flow control: gpios diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 57f04f8bf504..d69592e5e2ec 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -39,76 +39,70 @@ #define SE_UART_MANUAL_RFR 0x2ac /* SE_UART_TRANS_CFG */ -#define UART_TX_PAR_EN BIT(0) -#define UART_CTS_MASK BIT(1) - -/* SE_UART_TX_WORD_LEN */ -#define TX_WORD_LEN_MSK GENMASK(9, 0) +#define UART_TX_PAR_EN BIT(0) +#define UART_CTS_MASK BIT(1) /* SE_UART_TX_STOP_BIT_LEN */ -#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) -#define TX_STOP_BIT_LEN_1 0 -#define TX_STOP_BIT_LEN_1_5 1 -#define TX_STOP_BIT_LEN_2 2 - -/* SE_UART_TX_TRANS_LEN */ -#define TX_TRANS_LEN_MSK GENMASK(23, 0) +#define TX_STOP_BIT_LEN_1 0 +#define TX_STOP_BIT_LEN_2 2 /* SE_UART_RX_TRANS_CFG */ -#define UART_RX_INS_STATUS_BIT BIT(2) -#define UART_RX_PAR_EN BIT(3) +#define UART_RX_PAR_EN BIT(3) /* SE_UART_RX_WORD_LEN */ -#define RX_WORD_LEN_MASK GENMASK(9, 0) +#define RX_WORD_LEN_MASK GENMASK(9, 0) /* SE_UART_RX_STALE_CNT */ -#define RX_STALE_CNT GENMASK(23, 0) +#define RX_STALE_CNT GENMASK(23, 0) /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ -#define PAR_CALC_EN BIT(0) -#define PAR_MODE_MSK GENMASK(2, 1) -#define PAR_MODE_SHFT 1 -#define PAR_EVEN 0x00 -#define PAR_ODD 0x01 -#define PAR_SPACE 0x10 -#define PAR_MARK 0x11 +#define PAR_CALC_EN BIT(0) +#define PAR_EVEN 0x00 +#define PAR_ODD 0x01 +#define PAR_SPACE 0x10 /* SE_UART_MANUAL_RFR register fields */ -#define UART_MANUAL_RFR_EN BIT(31) -#define UART_RFR_NOT_READY BIT(1) -#define UART_RFR_READY BIT(0) +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) /* UART M_CMD OP codes */ -#define UART_START_TX 0x1 -#define UART_START_BREAK 0x4 -#define UART_STOP_BREAK 0x5 +#define UART_START_TX 0x1 /* UART S_CMD OP codes */ -#define UART_START_READ 0x1 -#define UART_PARAM 0x1 +#define UART_START_READ 0x1 +#define UART_PARAM 0x1 +#define UART_PARAM_RFR_OPEN BIT(7) -#define UART_OVERSAMPLING 32 -#define STALE_TIMEOUT 16 -#define DEFAULT_BITS_PER_CHAR 10 -#define GENI_UART_CONS_PORTS 1 -#define GENI_UART_PORTS 3 -#define DEF_FIFO_DEPTH_WORDS 16 -#define DEF_TX_WM 2 -#define DEF_FIFO_WIDTH_BITS 32 -#define UART_RX_WM 2 +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 16 +#define DEFAULT_BITS_PER_CHAR 10 +#define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 +#define DEF_FIFO_DEPTH_WORDS 16 +#define DEF_TX_WM 2 +#define DEF_FIFO_WIDTH_BITS 32 +#define UART_RX_WM 2 /* SE_UART_LOOPBACK_CFG */ -#define RX_TX_SORTED BIT(0) -#define CTS_RTS_SORTED BIT(1) -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) +#define RX_TX_SORTED BIT(0) +#define CTS_RTS_SORTED BIT(1) +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) /* UART pin swap value */ -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define IO_MACRO_IO0_SEL 0x3 -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define IO_MACRO_IO2_IO3_SWAP 0x4640 /* We always configure 4 bytes per FIFO word */ -#define BYTES_PER_FIFO_WORD 4 +#define BYTES_PER_FIFO_WORD 4U + +#define DMA_RX_BUF_SIZE 2048 + +struct qcom_geni_device_data { + bool console; + enum geni_se_xfer_mode mode; +}; struct qcom_geni_private_data { /* NOTE: earlycon port will have NULL here */ @@ -128,10 +122,11 @@ struct qcom_geni_serial_port { u32 tx_fifo_depth; u32 tx_fifo_width; u32 rx_fifo_depth; + dma_addr_t tx_dma_addr; + dma_addr_t rx_dma_addr; bool setup; - int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); unsigned int baud; - void *rx_fifo; + void *rx_buf; u32 loopback; bool brk; @@ -141,44 +136,42 @@ struct qcom_geni_serial_port { bool cts_rts_swap; struct qcom_geni_private_data private_data; + const struct qcom_geni_device_data *dev_data; }; static const struct uart_ops qcom_geni_console_pops; static const struct uart_ops qcom_geni_uart_pops; static struct uart_driver qcom_geni_console_driver; static struct uart_driver qcom_geni_uart_driver; -static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); -static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); -static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); -static void qcom_geni_serial_stop_rx(struct uart_port *uport); -static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); -#define to_dev_port(ptr, member) \ - container_of(ptr, struct qcom_geni_serial_port, member) +static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) +{ + return container_of(uport, struct qcom_geni_serial_port, uport); +} static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { [0] = { .uport = { - .iotype = UPIO_MEM, - .ops = &qcom_geni_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .line = 0, + .iotype = UPIO_MEM, + .ops = &qcom_geni_uart_pops, + .flags = UPF_BOOT_AUTOCONF, + .line = 0, }, }, [1] = { .uport = { - .iotype = UPIO_MEM, - .ops = &qcom_geni_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .line = 1, + .iotype = UPIO_MEM, + .ops = &qcom_geni_uart_pops, + .flags = UPF_BOOT_AUTOCONF, + .line = 1, }, }, [2] = { .uport = { - .iotype = UPIO_MEM, - .ops = &qcom_geni_uart_pops, - .flags = UPF_BOOT_AUTOCONF, - .line = 2, + .iotype = UPIO_MEM, + .ops = &qcom_geni_uart_pops, + .flags = UPF_BOOT_AUTOCONF, + .line = 2, }, }, }; @@ -195,7 +188,7 @@ static struct qcom_geni_serial_port qcom_geni_console_port = { static int qcom_geni_serial_request_port(struct uart_port *uport) { struct platform_device *pdev = to_platform_device(uport->dev); - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); uport->membase = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(uport->membase)) @@ -232,7 +225,7 @@ static void qcom_geni_serial_set_mctrl(struct uart_port *uport, unsigned int mctrl) { u32 uart_manual_rfr = 0; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); if (uart_console(uport)) return; @@ -262,6 +255,16 @@ static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) return port; } +static bool qcom_geni_serial_main_active(struct uart_port *uport) +{ + return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; +} + +static bool qcom_geni_serial_secondary_active(struct uart_port *uport) +{ + return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; +} + static bool qcom_geni_serial_poll_bit(struct uart_port *uport, int offset, int field, bool set) { @@ -273,7 +276,7 @@ static bool qcom_geni_serial_poll_bit(struct uart_port *uport, struct qcom_geni_private_data *private_data = uport->private_data; if (private_data->drv) { - port = to_dev_port(uport, uport); + port = to_dev_port(uport); baud = port->baud; if (!baud) baud = 115200; @@ -338,7 +341,6 @@ static void qcom_geni_serial_abort_rx(struct uart_port *uport) } #ifdef CONFIG_CONSOLE_POLL - static int qcom_geni_serial_get_char(struct uart_port *uport) { struct qcom_geni_private_data *private_data = uport->private_data; @@ -521,12 +523,12 @@ static void qcom_geni_serial_console_write(struct console *co, const char *s, spin_unlock_irqrestore(&uport->lock, flags); } -static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) +static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) { u32 i; unsigned char buf[sizeof(u32)]; struct tty_port *tport; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); tport = &uport->state->port; for (i = 0; i < bytes; ) { @@ -556,30 +558,21 @@ static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) } if (!drop) tty_flip_buffer_push(tport); - return 0; } #else -static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) +static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) { - return -EPERM; -} +} #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ -static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) +static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) { - struct tty_port *tport; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); - u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; - u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; + struct qcom_geni_serial_port *port = to_dev_port(uport); + struct tty_port *tport = &uport->state->port; int ret; - tport = &uport->state->port; - ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); - if (drop) - return 0; - - ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); + ret = tty_insert_flip_string(tport, port->rx_buf, bytes); if (ret != bytes) { dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", __func__, ret, bytes); @@ -587,19 +580,82 @@ static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) } uport->icount.rx += ret; tty_flip_buffer_push(tport); - return ret; } -static void qcom_geni_serial_start_tx(struct uart_port *uport) +static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) { - u32 irq_en; - u32 status; + return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); +} - status = readl(uport->membase + SE_GENI_STATUS); - if (status & M_GENI_CMD_ACTIVE) +static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + bool done; + u32 m_irq_en; + + if (!qcom_geni_serial_main_active(uport)) return; - if (!qcom_geni_serial_tx_empty(uport)) + if (port->rx_dma_addr) { + geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, + port->tx_remaining); + port->tx_dma_addr = 0; + port->tx_remaining = 0; + } + + m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); + writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); + geni_se_cancel_m_cmd(&port->se); + + done = qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, + S_CMD_CANCEL_EN, true); + if (!done) { + geni_se_abort_m_cmd(&port->se); + done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, + M_CMD_ABORT_EN, true); + if (!done) + dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); + writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); + } + + writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); +} + +static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + struct circ_buf *xmit = &uport->state->xmit; + unsigned int xmit_size; + int ret; + + if (port->tx_dma_addr) + return; + + xmit_size = uart_circ_chars_pending(xmit); + if (xmit_size < WAKEUP_CHARS) + uart_write_wakeup(uport); + + xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); + + qcom_geni_serial_setup_tx(uport, xmit_size); + + ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], + xmit_size, &port->tx_dma_addr); + if (ret) { + dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); + qcom_geni_serial_stop_tx_dma(uport); + return; + } + + port->tx_remaining = xmit_size; +} + +static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) +{ + u32 irq_en; + + if (qcom_geni_serial_main_active(uport) || + !qcom_geni_serial_tx_empty(uport)) return; irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); @@ -609,19 +665,17 @@ static void qcom_geni_serial_start_tx(struct uart_port *uport) writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); } -static void qcom_geni_serial_stop_tx(struct uart_port *uport) +static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) { u32 irq_en; - u32 status; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); - status = readl(uport->membase + SE_GENI_STATUS); /* Possible stop tx is called multiple times. */ - if (!(status & M_GENI_CMD_ACTIVE)) + if (!qcom_geni_serial_main_active(uport)) return; geni_se_cancel_m_cmd(&port->se); @@ -635,73 +689,13 @@ static void qcom_geni_serial_stop_tx(struct uart_port *uport) writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); } -static void qcom_geni_serial_start_rx(struct uart_port *uport) -{ - u32 irq_en; - u32 status; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); - - status = readl(uport->membase + SE_GENI_STATUS); - if (status & S_GENI_CMD_ACTIVE) - qcom_geni_serial_stop_rx(uport); - - geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); - - irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); - irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; - writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); - - irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); - irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; - writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); -} - -static void qcom_geni_serial_stop_rx(struct uart_port *uport) -{ - u32 irq_en; - u32 status; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); - u32 s_irq_status; - - irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); - irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); - writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); - - irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); - irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); - writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); - - status = readl(uport->membase + SE_GENI_STATUS); - /* Possible stop rx is called multiple times. */ - if (!(status & S_GENI_CMD_ACTIVE)) - return; - - geni_se_cancel_s_cmd(&port->se); - qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, - S_CMD_CANCEL_EN, true); - /* - * If timeout occurs secondary engine remains active - * and Abort sequence is executed. - */ - s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); - /* Flush the Rx buffer */ - if (s_irq_status & S_RX_FIFO_LAST_EN) - qcom_geni_serial_handle_rx(uport, true); - writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); - - status = readl(uport->membase + SE_GENI_STATUS); - if (status & S_GENI_CMD_ACTIVE) - qcom_geni_serial_abort_rx(uport); -} - -static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) +static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) { u32 status; u32 word_cnt; u32 last_word_byte_cnt; u32 last_word_partial; u32 total_bytes; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); word_cnt = status & RX_FIFO_WC_MSK; @@ -716,22 +710,184 @@ static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) total_bytes += last_word_byte_cnt; else total_bytes += BYTES_PER_FIFO_WORD; - port->handle_rx(uport, total_bytes, drop); + handle_rx_console(uport, total_bytes, drop); } -static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, - bool active) +static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) { - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + u32 irq_en; + struct qcom_geni_serial_port *port = to_dev_port(uport); + u32 s_irq_status; + + irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); + irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); + writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); + + irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); + irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); + writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); + + if (!qcom_geni_serial_secondary_active(uport)) + return; + + geni_se_cancel_s_cmd(&port->se); + qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, + S_CMD_CANCEL_EN, true); + /* + * If timeout occurs secondary engine remains active + * and Abort sequence is executed. + */ + s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); + /* Flush the Rx buffer */ + if (s_irq_status & S_RX_FIFO_LAST_EN) + qcom_geni_serial_handle_rx_fifo(uport, true); + writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); + + if (qcom_geni_serial_secondary_active(uport)) + qcom_geni_serial_abort_rx(uport); +} + +static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) +{ + u32 irq_en; + struct qcom_geni_serial_port *port = to_dev_port(uport); + + if (qcom_geni_serial_secondary_active(uport)) + qcom_geni_serial_stop_rx_fifo(uport); + + geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); + + irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); + irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; + writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); + + irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); + irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; + writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); +} + +static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + + if (!qcom_geni_serial_secondary_active(uport)) + return; + + geni_se_cancel_s_cmd(&port->se); + qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, + S_CMD_CANCEL_EN, true); + + if (qcom_geni_serial_secondary_active(uport)) + qcom_geni_serial_abort_rx(uport); + + if (port->rx_dma_addr) { + geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, + DMA_RX_BUF_SIZE); + port->rx_dma_addr = 0; + } +} + +static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + int ret; + + if (qcom_geni_serial_secondary_active(uport)) + qcom_geni_serial_stop_rx_dma(uport); + + geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); + + ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, + DMA_RX_BUF_SIZE, + &port->rx_dma_addr); + if (ret) { + dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); + qcom_geni_serial_stop_rx_dma(uport); + } +} + +static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + u32 rx_in; + int ret; + + if (!qcom_geni_serial_secondary_active(uport)) + return; + + if (!port->rx_dma_addr) + return; + + geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); + port->rx_dma_addr = 0; + + rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); + if (!rx_in) { + dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); + return; + } + + if (!drop) + handle_rx_uart(uport, rx_in, drop); + + ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, + DMA_RX_BUF_SIZE, + &port->rx_dma_addr); + if (ret) { + dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); + qcom_geni_serial_stop_rx_dma(uport); + } +} + +static void qcom_geni_serial_start_rx(struct uart_port *uport) +{ + uport->ops->start_rx(uport); +} + +static void qcom_geni_serial_stop_rx(struct uart_port *uport) +{ + uport->ops->stop_rx(uport); +} + +static void qcom_geni_serial_stop_tx(struct uart_port *uport) +{ + uport->ops->stop_tx(uport); +} + +static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, + unsigned int chunk) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + struct circ_buf *xmit = &uport->state->xmit; + unsigned int tx_bytes, c, remaining = chunk; + u8 buf[BYTES_PER_FIFO_WORD]; + + while (remaining) { + memset(buf, 0, sizeof(buf)); + tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); + + for (c = 0; c < tx_bytes ; c++) { + buf[c] = xmit->buf[xmit->tail]; + uart_xmit_advance(uport, 1); + } + + iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); + + remaining -= tx_bytes; + port->tx_remaining -= tx_bytes; + } +} + +static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, + bool done, bool active) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); struct circ_buf *xmit = &uport->state->xmit; size_t avail; - size_t remaining; size_t pending; - int i; u32 status; u32 irq_en; unsigned int chunk; - int tail; status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); @@ -743,14 +899,13 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, /* All data has been transmitted and acknowledged as received */ if (!pending && !status && done) { - qcom_geni_serial_stop_tx(uport); + qcom_geni_serial_stop_tx_fifo(uport); goto out_write_wakeup; } avail = port->tx_fifo_depth - (status & TX_FIFO_WC); avail *= BYTES_PER_FIFO_WORD; - tail = xmit->tail; chunk = min(avail, pending); if (!chunk) goto out_write_wakeup; @@ -765,29 +920,7 @@ static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, uport->membase + SE_GENI_M_IRQ_EN); } - remaining = chunk; - for (i = 0; i < chunk; ) { - unsigned int tx_bytes; - u8 buf[sizeof(u32)]; - int c; - - memset(buf, 0, sizeof(buf)); - tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD); - - for (c = 0; c < tx_bytes ; c++) { - buf[c] = xmit->buf[tail++]; - tail &= UART_XMIT_SIZE - 1; - } - - iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); - - i += tx_bytes; - uport->icount.tx += tx_bytes; - remaining -= tx_bytes; - port->tx_remaining -= tx_bytes; - } - - xmit->tail = tail; + qcom_geni_serial_send_chunk_fifo(uport, chunk); /* * The tx fifo watermark is level triggered and latched. Though we had @@ -809,16 +942,36 @@ out_write_wakeup: uart_write_wakeup(uport); } +static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) +{ + struct qcom_geni_serial_port *port = to_dev_port(uport); + struct circ_buf *xmit = &uport->state->xmit; + + uart_xmit_advance(uport, port->tx_remaining); + geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); + port->tx_dma_addr = 0; + port->tx_remaining = 0; + + if (!uart_circ_empty(xmit)) + qcom_geni_serial_start_tx_dma(uport); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(uport); +} + static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) { u32 m_irq_en; u32 m_irq_status; u32 s_irq_status; u32 geni_status; + u32 dma; + u32 dma_tx_status; + u32 dma_rx_status; struct uart_port *uport = dev; bool drop_rx = false; struct tty_port *tport = &uport->state->port; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); if (uport->suspended) return IRQ_NONE; @@ -827,10 +980,15 @@ static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); + dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); + dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); geni_status = readl(uport->membase + SE_GENI_STATUS); + dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); + writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); + writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) goto out_unlock; @@ -840,23 +998,44 @@ static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) tty_insert_flip_char(tport, 0, TTY_OVERRUN); } - if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) - qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, - geni_status & M_GENI_CMD_ACTIVE); - - if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { + if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { if (s_irq_status & S_GP_IRQ_0_EN) uport->icount.parity++; drop_rx = true; - } else if (s_irq_status & S_GP_IRQ_2_EN || - s_irq_status & S_GP_IRQ_3_EN) { + } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { uport->icount.brk++; port->brk = true; } - if (s_irq_status & S_RX_FIFO_WATERMARK_EN || - s_irq_status & S_RX_FIFO_LAST_EN) - qcom_geni_serial_handle_rx(uport, drop_rx); + if (dma) { + if (dma_tx_status & TX_DMA_DONE) + qcom_geni_serial_handle_tx_dma(uport); + + if (dma_rx_status) { + if (dma_rx_status & RX_RESET_DONE) + goto out_unlock; + + if (dma_rx_status & RX_DMA_PARITY_ERR) { + uport->icount.parity++; + drop_rx = true; + } + + if (dma_rx_status & RX_DMA_BREAK) + uport->icount.brk++; + + if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) + qcom_geni_serial_handle_rx_dma(uport, drop_rx); + } + } else { + if (m_irq_status & m_irq_en & + (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) + qcom_geni_serial_handle_tx_fifo(uport, + m_irq_status & M_CMD_DONE_EN, + geni_status & M_GENI_CMD_ACTIVE); + + if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) + qcom_geni_serial_handle_rx_fifo(uport, drop_rx); + } out_unlock: uart_unlock_and_check_sysrq(uport); @@ -876,11 +1055,11 @@ static int setup_fifos(struct qcom_geni_serial_port *port) uport->fifosize = (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; - if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { - port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo, - port->rx_fifo_depth * sizeof(u32), - GFP_KERNEL); - if (!port->rx_fifo) + if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { + port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, + port->rx_fifo_depth * sizeof(u32), + GFP_KERNEL); + if (!port->rx_buf) return -ENOMEM; } @@ -891,11 +1070,13 @@ static int setup_fifos(struct qcom_geni_serial_port *port) static void qcom_geni_serial_shutdown(struct uart_port *uport) { disable_irq(uport->irq); + qcom_geni_serial_stop_tx(uport); + qcom_geni_serial_stop_rx(uport); } static int qcom_geni_serial_port_setup(struct uart_port *uport) { - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; u32 proto; u32 pin_swap; @@ -937,7 +1118,7 @@ static int qcom_geni_serial_port_setup(struct uart_port *uport) geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, false, true, true); geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); - geni_se_select_mode(&port->se, GENI_SE_FIFO); + geni_se_select_mode(&port->se, port->dev_data->mode); qcom_geni_serial_start_rx(uport); port->setup = true; @@ -947,7 +1128,7 @@ static int qcom_geni_serial_port_setup(struct uart_port *uport) static int qcom_geni_serial_startup(struct uart_port *uport) { int ret; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); if (!port->setup) { ret = qcom_geni_serial_port_setup(uport); @@ -1033,7 +1214,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, u32 stop_bit_len; unsigned int clk_div; u32 ser_clk_cfg; - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); unsigned long clk_rate; u32 ver, sampling_rate; unsigned int avg_bw_core; @@ -1137,11 +1318,6 @@ out_restart_rx: qcom_geni_serial_start_rx(uport); } -static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) -{ - return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); -} - #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE static int qcom_geni_console_setup(struct console *co, char *options) { @@ -1323,7 +1499,7 @@ static struct uart_driver qcom_geni_uart_driver = { static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { - struct qcom_geni_serial_port *port = to_dev_port(uport, uport); + struct qcom_geni_serial_port *port = to_dev_port(uport); /* If we've never been called, treat it as off */ if (old_state == UART_PM_STATE_UNDEFINED) @@ -1341,10 +1517,10 @@ static void qcom_geni_serial_pm(struct uart_port *uport, static const struct uart_ops qcom_geni_console_pops = { .tx_empty = qcom_geni_serial_tx_empty, - .stop_tx = qcom_geni_serial_stop_tx, - .start_tx = qcom_geni_serial_start_tx, - .stop_rx = qcom_geni_serial_stop_rx, - .start_rx = qcom_geni_serial_start_rx, + .stop_tx = qcom_geni_serial_stop_tx_fifo, + .start_tx = qcom_geni_serial_start_tx_fifo, + .stop_rx = qcom_geni_serial_stop_rx_fifo, + .start_rx = qcom_geni_serial_start_rx_fifo, .set_termios = qcom_geni_serial_set_termios, .startup = qcom_geni_serial_startup, .request_port = qcom_geni_serial_request_port, @@ -1362,9 +1538,10 @@ static const struct uart_ops qcom_geni_console_pops = { static const struct uart_ops qcom_geni_uart_pops = { .tx_empty = qcom_geni_serial_tx_empty, - .stop_tx = qcom_geni_serial_stop_tx, - .start_tx = qcom_geni_serial_start_tx, - .stop_rx = qcom_geni_serial_stop_rx, + .stop_tx = qcom_geni_serial_stop_tx_dma, + .start_tx = qcom_geni_serial_start_tx_dma, + .start_rx = qcom_geni_serial_start_rx_dma, + .stop_rx = qcom_geni_serial_stop_rx_dma, .set_termios = qcom_geni_serial_set_termios, .startup = qcom_geni_serial_startup, .request_port = qcom_geni_serial_request_port, @@ -1384,13 +1561,14 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) struct uart_port *uport; struct resource *res; int irq; - bool console = false; struct uart_driver *drv; + const struct qcom_geni_device_data *data; - if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) - console = true; + data = of_device_get_match_data(&pdev->dev); + if (!data) + return -EINVAL; - if (console) { + if (data->console) { drv = &qcom_geni_console_driver; line = of_alias_get_id(pdev->dev.of_node, "serial"); } else { @@ -1400,7 +1578,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) line = of_alias_get_id(pdev->dev.of_node, "hsuart"); } - port = get_port_from_line(line, console); + port = get_port_from_line(line, data->console); if (IS_ERR(port)) { dev_err(&pdev->dev, "Invalid line %d\n", line); return PTR_ERR(port); @@ -1412,6 +1590,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -ENODEV; uport->dev = &pdev->dev; + port->dev_data = data; port->se.dev = &pdev->dev; port->se.wrapper = dev_get_drvdata(pdev->dev.parent); port->se.clk = devm_clk_get(&pdev->dev, "se"); @@ -1430,10 +1609,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; - if (!console) { - port->rx_fifo = devm_kcalloc(uport->dev, - port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); - if (!port->rx_fifo) + if (!data->console) { + port->rx_buf = devm_kzalloc(uport->dev, + DMA_RX_BUF_SIZE, GFP_KERNEL); + if (!port->rx_buf) return -ENOMEM; } @@ -1460,7 +1639,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) uport->irq = irq; uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); - if (!console) + if (!data->console) port->wakeup_irq = platform_get_irq_optional(pdev, 1); if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) @@ -1482,7 +1661,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->private_data.drv = drv; uport->private_data = &port->private_data; platform_set_drvdata(pdev, port); - port->handle_rx = console ? handle_rx_console : handle_rx_uart; ret = uart_add_one_port(drv, uport); if (ret) @@ -1594,6 +1772,16 @@ static int qcom_geni_serial_sys_hib_resume(struct device *dev) return ret; } +static const struct qcom_geni_device_data qcom_geni_console_data = { + .console = true, + .mode = GENI_SE_FIFO, +}; + +static const struct qcom_geni_device_data qcom_geni_uart_data = { + .console = false, + .mode = GENI_SE_DMA, +}; + static const struct dev_pm_ops qcom_geni_serial_pm_ops = { .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), @@ -1604,8 +1792,14 @@ static const struct dev_pm_ops qcom_geni_serial_pm_ops = { }; static const struct of_device_id qcom_geni_serial_match_table[] = { - { .compatible = "qcom,geni-debug-uart", }, - { .compatible = "qcom,geni-uart", }, + { + .compatible = "qcom,geni-debug-uart", + .data = &qcom_geni_console_data, + }, + { + .compatible = "qcom,geni-uart", + .data = &qcom_geni_uart_data, + }, {} }; MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 39f92eb1e698..29c94be09159 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1423,25 +1423,6 @@ static int sc16is7xx_probe(struct device *dev, } sched_set_fifo(s->kworker_task); -#ifdef CONFIG_GPIOLIB - if (devtype->nr_gpio) { - /* Setup GPIO cotroller */ - s->gpio.owner = THIS_MODULE; - s->gpio.parent = dev; - s->gpio.label = dev_name(dev); - s->gpio.direction_input = sc16is7xx_gpio_direction_input; - s->gpio.get = sc16is7xx_gpio_get; - s->gpio.direction_output = sc16is7xx_gpio_direction_output; - s->gpio.set = sc16is7xx_gpio_set; - s->gpio.base = -1; - s->gpio.ngpio = devtype->nr_gpio; - s->gpio.can_sleep = 1; - ret = gpiochip_add_data(&s->gpio, s); - if (ret) - goto out_thread; - } -#endif - /* reset device, purging any pending irq / data */ regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, SC16IS7XX_IOCONTROL_SRESET_BIT); @@ -1518,6 +1499,25 @@ static int sc16is7xx_probe(struct device *dev, s->p[u].irda_mode = true; } +#ifdef CONFIG_GPIOLIB + if (devtype->nr_gpio) { + /* Setup GPIO cotroller */ + s->gpio.owner = THIS_MODULE; + s->gpio.parent = dev; + s->gpio.label = dev_name(dev); + s->gpio.direction_input = sc16is7xx_gpio_direction_input; + s->gpio.get = sc16is7xx_gpio_get; + s->gpio.direction_output = sc16is7xx_gpio_direction_output; + s->gpio.set = sc16is7xx_gpio_set; + s->gpio.base = -1; + s->gpio.ngpio = devtype->nr_gpio; + s->gpio.can_sleep = 1; + ret = gpiochip_add_data(&s->gpio, s); + if (ret) + goto out_thread; + } +#endif + /* * Setup interrupt. We first try to acquire the IRQ line as level IRQ. * If that succeeds, we can allow sharing the interrupt as well. @@ -1537,18 +1537,19 @@ static int sc16is7xx_probe(struct device *dev, if (!ret) return 0; -out_ports: - for (i--; i >= 0; i--) { - uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); - clear_bit(s->p[i].port.line, &sc16is7xx_lines); - } - #ifdef CONFIG_GPIOLIB if (devtype->nr_gpio) gpiochip_remove(&s->gpio); out_thread: #endif + +out_ports: + for (i--; i >= 0; i--) { + uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); + clear_bit(s->p[i].port.line, &sc16is7xx_lines); + } + kthread_stop(s->kworker_task); out_clk: diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c index 7df687822634..4f2fc5f7bb19 100644 --- a/drivers/tty/serial/sccnxp.c +++ b/drivers/tty/serial/sccnxp.c @@ -913,23 +913,13 @@ static int sccnxp_probe(struct platform_device *pdev) } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) return -EPROBE_DEFER; - clk = devm_clk_get(&pdev->dev, NULL); + clk = devm_clk_get_enabled(&pdev->dev, NULL); if (IS_ERR(clk)) { ret = PTR_ERR(clk); if (ret == -EPROBE_DEFER) goto err_out; uartclk = 0; } else { - ret = clk_prepare_enable(clk); - if (ret) - goto err_out; - - ret = devm_add_action_or_reset(&pdev->dev, - (void(*)(void *))clk_disable_unprepare, - clk); - if (ret) - goto err_out; - uartclk = clk_get_rate(clk); } diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index e5b9773db5e3..1cf08b33456c 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -1046,6 +1046,7 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) if (tup->cdata->fifo_mode_enable_status) { ret = tegra_uart_wait_fifo_mode_enabled(tup); if (ret < 0) { + clk_disable_unprepare(tup->uart_clk); dev_err(tup->uport.dev, "Failed to enable FIFO mode: %d\n", ret); return ret; @@ -1067,6 +1068,7 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) */ ret = tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); if (ret < 0) { + clk_disable_unprepare(tup->uart_clk); dev_err(tup->uport.dev, "Failed to set baud rate\n"); return ret; } @@ -1226,10 +1228,13 @@ static int tegra_uart_startup(struct uart_port *u) dev_name(u->dev), tup); if (ret < 0) { dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq); - goto fail_hw_init; + goto fail_request_irq; } return 0; +fail_request_irq: + /* tup->uart_clk is already enabled in tegra_uart_hw_init */ + clk_disable_unprepare(tup->uart_clk); fail_hw_init: if (!tup->use_rx_pio) tegra_uart_dma_channel_free(tup, true); diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index ec874f3a567c..2bd32c8ece39 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c @@ -169,9 +169,9 @@ uart_update_mctrl(struct uart_port *port, unsigned int set, unsigned int clear) #define uart_set_mctrl(port, set) uart_update_mctrl(port, set, 0) #define uart_clear_mctrl(port, clear) uart_update_mctrl(port, 0, clear) -static void uart_port_dtr_rts(struct uart_port *uport, int raise) +static void uart_port_dtr_rts(struct uart_port *uport, bool active) { - if (raise) + if (active) uart_set_mctrl(uport, TIOCM_DTR | TIOCM_RTS); else uart_clear_mctrl(uport, TIOCM_DTR | TIOCM_RTS); @@ -182,7 +182,7 @@ static void uart_port_dtr_rts(struct uart_port *uport, int raise) * will be serialised by the per-port mutex. */ static int uart_port_startup(struct tty_struct *tty, struct uart_state *state, - int init_hw) + bool init_hw) { struct uart_port *uport = uart_port_check(state); unsigned long flags; @@ -239,7 +239,7 @@ static int uart_port_startup(struct tty_struct *tty, struct uart_state *state, * port is open and ready to respond. */ if (init_hw && C_BAUD(tty)) - uart_port_dtr_rts(uport, 1); + uart_port_dtr_rts(uport, true); } /* @@ -254,7 +254,7 @@ static int uart_port_startup(struct tty_struct *tty, struct uart_state *state, } static int uart_startup(struct tty_struct *tty, struct uart_state *state, - int init_hw) + bool init_hw) { struct tty_port *port = &state->port; int retval; @@ -290,7 +290,7 @@ static void uart_shutdown(struct tty_struct *tty, struct uart_state *state) set_bit(TTY_IO_ERROR, &tty->flags); if (tty_port_initialized(port)) { - tty_port_set_initialized(port, 0); + tty_port_set_initialized(port, false); /* * Turn off DTR and RTS early. @@ -302,7 +302,7 @@ static void uart_shutdown(struct tty_struct *tty, struct uart_state *state) } if (!tty || C_HUPCL(tty)) - uart_port_dtr_rts(uport, 0); + uart_port_dtr_rts(uport, false); uart_port_shutdown(port); } @@ -312,7 +312,7 @@ static void uart_shutdown(struct tty_struct *tty, struct uart_state *state) * a DCD drop (hangup) at just the right time. Clear suspended bit so * we don't try to resume a port that has been shutdown. */ - tty_port_set_suspended(port, 0); + tty_port_set_suspended(port, false); /* * Do not free() the transmit buffer page under the port lock since @@ -997,7 +997,7 @@ static int uart_set_info(struct tty_struct *tty, struct tty_port *port, uart_change_speed(tty, state, NULL); } } else { - retval = uart_startup(tty, state, 1); + retval = uart_startup(tty, state, true); if (retval == 0) tty_port_set_initialized(port, true); if (retval > 0) @@ -1165,7 +1165,7 @@ static int uart_do_autoconfig(struct tty_struct *tty, struct uart_state *state) */ uport->ops->config_port(uport, flags); - ret = uart_startup(tty, state, 1); + ret = uart_startup(tty, state, true); if (ret == 0) tty_port_set_initialized(port, true); if (ret > 0) @@ -1725,7 +1725,7 @@ static void uart_tty_port_shutdown(struct tty_port *port) * a DCD drop (hangup) at just the right time. Clear suspended bit so * we don't try to resume a port that has been shutdown. */ - tty_port_set_suspended(port, 0); + tty_port_set_suspended(port, false); /* * Free the transmit buffer. @@ -1827,7 +1827,7 @@ static void uart_hangup(struct tty_struct *tty) spin_lock_irqsave(&port->lock, flags); port->count = 0; spin_unlock_irqrestore(&port->lock, flags); - tty_port_set_active(port, 0); + tty_port_set_active(port, false); tty_port_tty_set(port, NULL); if (uport && !uart_console(uport)) uart_change_pm(state, UART_PM_STATE_OFF); @@ -1861,7 +1861,7 @@ static void uart_port_shutdown(struct tty_port *port) } } -static int uart_carrier_raised(struct tty_port *port) +static bool uart_carrier_raised(struct tty_port *port) { struct uart_state *state = container_of(port, struct uart_state, port); struct uart_port *uport; @@ -1875,18 +1875,17 @@ static int uart_carrier_raised(struct tty_port *port) * continue and not sleep */ if (WARN_ON(!uport)) - return 1; + return true; spin_lock_irq(&uport->lock); uart_enable_ms(uport); mctrl = uport->ops->get_mctrl(uport); spin_unlock_irq(&uport->lock); uart_port_deref(uport); - if (mctrl & TIOCM_CAR) - return 1; - return 0; + + return mctrl & TIOCM_CAR; } -static void uart_dtr_rts(struct tty_port *port, int raise) +static void uart_dtr_rts(struct tty_port *port, bool active) { struct uart_state *state = container_of(port, struct uart_state, port); struct uart_port *uport; @@ -1894,7 +1893,7 @@ static void uart_dtr_rts(struct tty_port *port, int raise) uport = uart_port_ref(state); if (!uport) return; - uart_port_dtr_rts(uport, raise); + uart_port_dtr_rts(uport, active); uart_port_deref(uport); } @@ -1943,9 +1942,9 @@ static int uart_port_activate(struct tty_port *port, struct tty_struct *tty) /* * Start up the serial port. */ - ret = uart_startup(tty, state, 0); + ret = uart_startup(tty, state, false); if (ret > 0) - tty_port_set_active(port, 1); + tty_port_set_active(port, true); return ret; } @@ -2349,8 +2348,8 @@ int uart_suspend_port(struct uart_driver *drv, struct uart_port *uport) int tries; unsigned int mctrl; - tty_port_set_suspended(port, 1); - tty_port_set_initialized(port, 0); + tty_port_set_suspended(port, true); + tty_port_set_initialized(port, false); spin_lock_irq(&uport->lock); ops->stop_tx(uport); @@ -2461,7 +2460,7 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport) uart_rs485_config(uport); ops->start_tx(uport); spin_unlock_irq(&uport->lock); - tty_port_set_initialized(port, 1); + tty_port_set_initialized(port, true); } else { /* * Failed to resume - maybe hardware went away? @@ -2472,7 +2471,7 @@ int uart_resume_port(struct uart_driver *drv, struct uart_port *uport) } } - tty_port_set_suspended(port, 0); + tty_port_set_suspended(port, false); } mutex_unlock(&port->mutex); @@ -3258,11 +3257,11 @@ EXPORT_SYMBOL(uart_match_port); /** * uart_handle_dcd_change - handle a change of carrier detect state * @uport: uart_port structure for the open port - * @status: new carrier detect status, nonzero if active + * @active: new carrier detect status * * Caller must hold uport->lock. */ -void uart_handle_dcd_change(struct uart_port *uport, unsigned int status) +void uart_handle_dcd_change(struct uart_port *uport, bool active) { struct tty_port *port = &uport->state->port; struct tty_struct *tty = port->tty; @@ -3274,7 +3273,7 @@ void uart_handle_dcd_change(struct uart_port *uport, unsigned int status) ld = tty_ldisc_ref(tty); if (ld) { if (ld->ops->dcd_change) - ld->ops->dcd_change(tty, status); + ld->ops->dcd_change(tty, active); tty_ldisc_deref(ld); } } @@ -3282,7 +3281,7 @@ void uart_handle_dcd_change(struct uart_port *uport, unsigned int status) uport->icount.dcd++; if (uart_dcd_enabled(uport)) { - if (status) + if (active) wake_up_interruptible(&port->open_wait); else if (tty) tty_hangup(tty); @@ -3293,11 +3292,11 @@ EXPORT_SYMBOL_GPL(uart_handle_dcd_change); /** * uart_handle_cts_change - handle a change of clear-to-send state * @uport: uart_port structure for the open port - * @status: new clear to send status, nonzero if active + * @active: new clear-to-send status * * Caller must hold uport->lock. */ -void uart_handle_cts_change(struct uart_port *uport, unsigned int status) +void uart_handle_cts_change(struct uart_port *uport, bool active) { lockdep_assert_held_once(&uport->lock); @@ -3305,13 +3304,13 @@ void uart_handle_cts_change(struct uart_port *uport, unsigned int status) if (uart_softcts_mode(uport)) { if (uport->hw_stopped) { - if (status) { + if (active) { uport->hw_stopped = 0; uport->ops->start_tx(uport); uart_write_wakeup(uport); } } else { - if (!status) { + if (!active) { uport->hw_stopped = 1; uport->ops->stop_tx(uport); } @@ -3415,6 +3414,7 @@ int uart_get_rs485_mode(struct uart_port *port) struct device *dev = port->dev; u32 rs485_delay[2]; int ret; + int rx_during_tx_gpio_flag; ret = device_property_read_u32_array(dev, "rs485-rts-delay", rs485_delay, 2); @@ -3463,6 +3463,17 @@ int uart_get_rs485_mode(struct uart_port *port) if (port->rs485_term_gpio) port->rs485_supported.flags |= SER_RS485_TERMINATE_BUS; + rx_during_tx_gpio_flag = (rs485conf->flags & SER_RS485_RX_DURING_TX) ? + GPIOD_OUT_HIGH : GPIOD_OUT_LOW; + port->rs485_rx_during_tx_gpio = devm_gpiod_get_optional(dev, + "rs485-rx-during-tx", + rx_during_tx_gpio_flag); + if (IS_ERR(port->rs485_rx_during_tx_gpio)) { + ret = PTR_ERR(port->rs485_rx_during_tx_gpio); + port->rs485_rx_during_tx_gpio = NULL; + return dev_err_probe(dev, ret, "Cannot get rs485-rx-during-tx-gpios\n"); + } + return 0; } EXPORT_SYMBOL_GPL(uart_get_rs485_mode); diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 409e91d6829a..767ff9fdb2e5 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -226,7 +226,11 @@ static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *ter stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); - rs485conf->flags |= SER_RS485_RX_DURING_TX; + if (port->rs485_rx_during_tx_gpio) + gpiod_set_value_cansleep(port->rs485_rx_during_tx_gpio, + !!(rs485conf->flags & SER_RS485_RX_DURING_TX)); + else + rs485conf->flags |= SER_RS485_RX_DURING_TX; if (rs485conf->flags & SER_RS485_ENABLED) { cr1 = readl_relaxed(port->membase + ofs->cr1); diff --git a/drivers/tty/serial/sunhv.c b/drivers/tty/serial/sunhv.c index 16c746a63258..7d38c33ef506 100644 --- a/drivers/tty/serial/sunhv.c +++ b/drivers/tty/serial/sunhv.c @@ -87,10 +87,10 @@ static int receive_chars_getchar(struct uart_port *port) if (c == CON_HUP) { hung_up = 1; - uart_handle_dcd_change(port, 0); + uart_handle_dcd_change(port, false); } else if (hung_up) { hung_up = 0; - uart_handle_dcd_change(port, 1); + uart_handle_dcd_change(port, true); } if (port->state == NULL) { @@ -133,7 +133,7 @@ static int receive_chars_read(struct uart_port *port) bytes_read = 1; } else if (stat == CON_HUP) { hung_up = 1; - uart_handle_dcd_change(port, 0); + uart_handle_dcd_change(port, false); continue; } else { /* HV_EWOULDBLOCK, etc. */ @@ -143,7 +143,7 @@ static int receive_chars_read(struct uart_port *port) if (hung_up) { hung_up = 0; - uart_handle_dcd_change(port, 1); + uart_handle_dcd_change(port, true); } if (port->sysrq != 0 && *con_read_page) { diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c index b09b6496ee3e..32c7a5b43f8e 100644 --- a/drivers/tty/serial/ucc_uart.c +++ b/drivers/tty/serial/ucc_uart.c @@ -1468,6 +1468,8 @@ static int ucc_uart_remove(struct platform_device *ofdev) uart_remove_one_port(&ucc_uart_driver, &qe_port->port); + of_node_put(qe_port->np); + kfree(qe_port); return 0; diff --git a/drivers/tty/synclink_gt.c b/drivers/tty/synclink_gt.c index 72b76cdde534..33f258d6fef9 100644 --- a/drivers/tty/synclink_gt.c +++ b/drivers/tty/synclink_gt.c @@ -694,7 +694,7 @@ static void hangup(struct tty_struct *tty) info->port.count = 0; info->port.tty = NULL; spin_unlock_irqrestore(&info->port.lock, flags); - tty_port_set_active(&info->port, 0); + tty_port_set_active(&info->port, false); mutex_unlock(&info->port.mutex); wake_up_interruptible(&info->port.open_wait); @@ -2354,7 +2354,7 @@ static int startup(struct slgt_info *info) if (info->port.tty) clear_bit(TTY_IO_ERROR, &info->port.tty->flags); - tty_port_set_initialized(&info->port, 1); + tty_port_set_initialized(&info->port, true); return 0; } @@ -2401,7 +2401,7 @@ static void shutdown(struct slgt_info *info) if (info->port.tty) set_bit(TTY_IO_ERROR, &info->port.tty->flags); - tty_port_set_initialized(&info->port, 0); + tty_port_set_initialized(&info->port, false); } static void program_hw(struct slgt_info *info) @@ -3126,7 +3126,7 @@ static int tiocmset(struct tty_struct *tty, return 0; } -static int carrier_raised(struct tty_port *port) +static bool carrier_raised(struct tty_port *port) { unsigned long flags; struct slgt_info *info = container_of(port, struct slgt_info, port); @@ -3134,16 +3134,17 @@ static int carrier_raised(struct tty_port *port) spin_lock_irqsave(&info->lock,flags); get_gtsignals(info); spin_unlock_irqrestore(&info->lock,flags); - return (info->signals & SerialSignal_DCD) ? 1 : 0; + + return info->signals & SerialSignal_DCD; } -static void dtr_rts(struct tty_port *port, int on) +static void dtr_rts(struct tty_port *port, bool active) { unsigned long flags; struct slgt_info *info = container_of(port, struct slgt_info, port); spin_lock_irqsave(&info->lock,flags); - if (on) + if (active) info->signals |= SerialSignal_RTS | SerialSignal_DTR; else info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR); @@ -3162,14 +3163,14 @@ static int block_til_ready(struct tty_struct *tty, struct file *filp, int retval; bool do_clocal = false; unsigned long flags; - int cd; + bool cd; struct tty_port *port = &info->port; DBGINFO(("%s block_til_ready\n", tty->driver->name)); if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) { /* nonblock mode is set or port is not enabled */ - tty_port_set_active(port, 1); + tty_port_set_active(port, true); return 0; } @@ -3226,7 +3227,7 @@ static int block_til_ready(struct tty_struct *tty, struct file *filp, port->blocked_open--; if (!retval) - tty_port_set_active(port, 1); + tty_port_set_active(port, true); DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval)); return retval; diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index 3149114bf130..36fb945fdad4 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -1224,14 +1224,16 @@ static struct tty_struct *tty_driver_lookup_tty(struct tty_driver *driver, { struct tty_struct *tty; - if (driver->ops->lookup) + if (driver->ops->lookup) { if (!file) tty = ERR_PTR(-EIO); else tty = driver->ops->lookup(driver, file, idx); - else + } else { + if (idx >= driver->num) + return ERR_PTR(-EINVAL); tty = driver->ttys[idx]; - + } if (!IS_ERR(tty)) tty_kref_get(tty); return tty; diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c index ce511557b98b..12983ce4e43e 100644 --- a/drivers/tty/tty_ioctl.c +++ b/drivers/tty/tty_ioctl.c @@ -270,13 +270,13 @@ EXPORT_SYMBOL(tty_termios_copy_hw); * between the two termios structures, or a speed change is needed. */ -int tty_termios_hw_change(const struct ktermios *a, const struct ktermios *b) +bool tty_termios_hw_change(const struct ktermios *a, const struct ktermios *b) { if (a->c_ispeed != b->c_ispeed || a->c_ospeed != b->c_ospeed) - return 1; + return true; if ((a->c_cflag ^ b->c_cflag) & ~(HUPCL | CREAD | CLOCAL)) - return 1; - return 0; + return true; + return false; } EXPORT_SYMBOL(tty_termios_hw_change); diff --git a/drivers/tty/tty_port.c b/drivers/tty/tty_port.c index dce08a6d7b5e..a788a6bf487d 100644 --- a/drivers/tty/tty_port.c +++ b/drivers/tty/tty_port.c @@ -367,7 +367,7 @@ static void tty_port_shutdown(struct tty_port *port, struct tty_struct *tty) goto out; if (tty_port_initialized(port)) { - tty_port_set_initialized(port, 0); + tty_port_set_initialized(port, false); /* * Drop DTR/RTS if HUPCL is set. This causes any attached * modem to hang up the line. @@ -403,7 +403,7 @@ void tty_port_hangup(struct tty_port *port) set_bit(TTY_IO_ERROR, &tty->flags); port->tty = NULL; spin_unlock_irqrestore(&port->lock, flags); - tty_port_set_active(port, 0); + tty_port_set_active(port, false); tty_port_shutdown(port, tty); tty_kref_put(tty); wake_up_interruptible(&port->open_wait); @@ -444,10 +444,10 @@ EXPORT_SYMBOL_GPL(tty_port_tty_wakeup); * to hide some internal details. This will eventually become entirely * internal to the tty port. */ -int tty_port_carrier_raised(struct tty_port *port) +bool tty_port_carrier_raised(struct tty_port *port) { if (port->ops->carrier_raised == NULL) - return 1; + return true; return port->ops->carrier_raised(port); } EXPORT_SYMBOL(tty_port_carrier_raised); @@ -463,7 +463,7 @@ EXPORT_SYMBOL(tty_port_carrier_raised); void tty_port_raise_dtr_rts(struct tty_port *port) { if (port->ops->dtr_rts) - port->ops->dtr_rts(port, 1); + port->ops->dtr_rts(port, true); } EXPORT_SYMBOL(tty_port_raise_dtr_rts); @@ -478,7 +478,7 @@ EXPORT_SYMBOL(tty_port_raise_dtr_rts); void tty_port_lower_dtr_rts(struct tty_port *port) { if (port->ops->dtr_rts) - port->ops->dtr_rts(port, 0); + port->ops->dtr_rts(port, false); } EXPORT_SYMBOL(tty_port_lower_dtr_rts); @@ -518,14 +518,14 @@ int tty_port_block_til_ready(struct tty_port *port, * the port has just hung up or is in another error state. */ if (tty_io_error(tty)) { - tty_port_set_active(port, 1); + tty_port_set_active(port, true); return 0; } if (filp == NULL || (filp->f_flags & O_NONBLOCK)) { /* Indicate we are open */ if (C_BAUD(tty)) tty_port_raise_dtr_rts(port); - tty_port_set_active(port, 1); + tty_port_set_active(port, true); return 0; } @@ -588,7 +588,7 @@ int tty_port_block_til_ready(struct tty_port *port, port->blocked_open--; spin_unlock_irqrestore(&port->lock, flags); if (retval == 0) - tty_port_set_active(port, 1); + tty_port_set_active(port, true); return retval; } EXPORT_SYMBOL(tty_port_block_til_ready); @@ -695,7 +695,7 @@ void tty_port_close_end(struct tty_port *port, struct tty_struct *tty) wake_up_interruptible(&port->open_wait); } spin_unlock_irqrestore(&port->lock, flags); - tty_port_set_active(port, 0); + tty_port_set_active(port, false); } EXPORT_SYMBOL(tty_port_close_end); @@ -788,7 +788,7 @@ int tty_port_open(struct tty_port *port, struct tty_struct *tty, return retval; } } - tty_port_set_initialized(port, 1); + tty_port_set_initialized(port, true); } mutex_unlock(&port->mutex); return tty_port_block_til_ready(port, tty, filp); diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c index 981d2bfcf9a5..57a5c23b51d4 100644 --- a/drivers/tty/vt/vt.c +++ b/drivers/tty/vt/vt.c @@ -316,73 +316,55 @@ void schedule_console_callback(void) * Code to manage unicode-based screen buffers */ -#ifdef NO_VC_UNI_SCREEN -/* this disables and optimizes related code away at compile time */ -#define get_vc_uniscr(vc) NULL -#else -#define get_vc_uniscr(vc) vc->vc_uni_screen -#endif - -#define VC_UNI_SCREEN_DEBUG 0 - -typedef uint32_t char32_t; - /* * Our screen buffer is preceded by an array of line pointers so that * scrolling only implies some pointer shuffling. */ -struct uni_screen { - char32_t *lines[0]; -}; -static struct uni_screen *vc_uniscr_alloc(unsigned int cols, unsigned int rows) +static u32 **vc_uniscr_alloc(unsigned int cols, unsigned int rows) { - struct uni_screen *uniscr; + u32 **uni_lines; void *p; - unsigned int memsize, i; + unsigned int memsize, i, col_size = cols * sizeof(**uni_lines); /* allocate everything in one go */ - memsize = cols * rows * sizeof(char32_t); - memsize += rows * sizeof(char32_t *); - p = vzalloc(memsize); - if (!p) + memsize = col_size * rows; + memsize += rows * sizeof(*uni_lines); + uni_lines = vzalloc(memsize); + if (!uni_lines) return NULL; /* initial line pointers */ - uniscr = p; - p = uniscr->lines + rows; + p = uni_lines + rows; for (i = 0; i < rows; i++) { - uniscr->lines[i] = p; - p += cols * sizeof(char32_t); + uni_lines[i] = p; + p += col_size; } - return uniscr; + + return uni_lines; } -static void vc_uniscr_free(struct uni_screen *uniscr) +static void vc_uniscr_free(u32 **uni_lines) { - vfree(uniscr); + vfree(uni_lines); } -static void vc_uniscr_set(struct vc_data *vc, struct uni_screen *new_uniscr) +static void vc_uniscr_set(struct vc_data *vc, u32 **new_uni_lines) { - vc_uniscr_free(vc->vc_uni_screen); - vc->vc_uni_screen = new_uniscr; + vc_uniscr_free(vc->vc_uni_lines); + vc->vc_uni_lines = new_uni_lines; } -static void vc_uniscr_putc(struct vc_data *vc, char32_t uc) +static void vc_uniscr_putc(struct vc_data *vc, u32 uc) { - struct uni_screen *uniscr = get_vc_uniscr(vc); - - if (uniscr) - uniscr->lines[vc->state.y][vc->state.x] = uc; + if (vc->vc_uni_lines) + vc->vc_uni_lines[vc->state.y][vc->state.x] = uc; } static void vc_uniscr_insert(struct vc_data *vc, unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); - - if (uniscr) { - char32_t *ln = uniscr->lines[vc->state.y]; + if (vc->vc_uni_lines) { + u32 *ln = vc->vc_uni_lines[vc->state.y]; unsigned int x = vc->state.x, cols = vc->vc_cols; memmove(&ln[x + nr], &ln[x], (cols - x - nr) * sizeof(*ln)); @@ -392,10 +374,8 @@ static void vc_uniscr_insert(struct vc_data *vc, unsigned int nr) static void vc_uniscr_delete(struct vc_data *vc, unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); - - if (uniscr) { - char32_t *ln = uniscr->lines[vc->state.y]; + if (vc->vc_uni_lines) { + u32 *ln = vc->vc_uni_lines[vc->state.y]; unsigned int x = vc->state.x, cols = vc->vc_cols; memcpy(&ln[x], &ln[x + nr], (cols - x - nr) * sizeof(*ln)); @@ -406,86 +386,84 @@ static void vc_uniscr_delete(struct vc_data *vc, unsigned int nr) static void vc_uniscr_clear_line(struct vc_data *vc, unsigned int x, unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); - - if (uniscr) { - char32_t *ln = uniscr->lines[vc->state.y]; - - memset32(&ln[x], ' ', nr); - } + if (vc->vc_uni_lines) + memset32(&vc->vc_uni_lines[vc->state.y][x], ' ', nr); } static void vc_uniscr_clear_lines(struct vc_data *vc, unsigned int y, unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); - - if (uniscr) { - unsigned int cols = vc->vc_cols; - + if (vc->vc_uni_lines) while (nr--) - memset32(uniscr->lines[y++], ' ', cols); - } + memset32(vc->vc_uni_lines[y++], ' ', vc->vc_cols); } -static void vc_uniscr_scroll(struct vc_data *vc, unsigned int t, unsigned int b, - enum con_scroll dir, unsigned int nr) +/* juggling array rotation algorithm (complexity O(N), size complexity O(1)) */ +static void juggle_array(u32 **array, unsigned int size, unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); + unsigned int gcd_idx; - if (uniscr) { - unsigned int i, j, k, sz, d, clear; + for (gcd_idx = 0; gcd_idx < gcd(nr, size); gcd_idx++) { + u32 *gcd_idx_val = array[gcd_idx]; + unsigned int dst_idx = gcd_idx; - sz = b - t; - clear = b - nr; - d = nr; - if (dir == SM_DOWN) { - clear = t; - d = sz - nr; + while (1) { + unsigned int src_idx = (dst_idx + nr) % size; + if (src_idx == gcd_idx) + break; + + array[dst_idx] = array[src_idx]; + dst_idx = src_idx; } - for (i = 0; i < gcd(d, sz); i++) { - char32_t *tmp = uniscr->lines[t + i]; - j = i; - while (1) { - k = j + d; - if (k >= sz) - k -= sz; - if (k == i) - break; - uniscr->lines[t + j] = uniscr->lines[t + k]; - j = k; - } - uniscr->lines[t + j] = tmp; - } - vc_uniscr_clear_lines(vc, clear, nr); + + array[dst_idx] = gcd_idx_val; } } -static void vc_uniscr_copy_area(struct uni_screen *dst, +static void vc_uniscr_scroll(struct vc_data *vc, unsigned int top, + unsigned int bottom, enum con_scroll dir, + unsigned int nr) +{ + u32 **uni_lines = vc->vc_uni_lines; + unsigned int size = bottom - top; + + if (!uni_lines) + return; + + if (dir == SM_DOWN) { + juggle_array(&uni_lines[top], size, size - nr); + vc_uniscr_clear_lines(vc, top, nr); + } else { + juggle_array(&uni_lines[top], size, nr); + vc_uniscr_clear_lines(vc, bottom - nr, nr); + } +} + +static void vc_uniscr_copy_area(u32 **dst_lines, unsigned int dst_cols, unsigned int dst_rows, - struct uni_screen *src, + u32 **src_lines, unsigned int src_cols, unsigned int src_top_row, unsigned int src_bot_row) { unsigned int dst_row = 0; - if (!dst) + if (!dst_lines) return; while (src_top_row < src_bot_row) { - char32_t *src_line = src->lines[src_top_row]; - char32_t *dst_line = dst->lines[dst_row]; + u32 *src_line = src_lines[src_top_row]; + u32 *dst_line = dst_lines[dst_row]; - memcpy(dst_line, src_line, src_cols * sizeof(char32_t)); + memcpy(dst_line, src_line, src_cols * sizeof(*src_line)); if (dst_cols - src_cols) memset32(dst_line + src_cols, ' ', dst_cols - src_cols); src_top_row++; dst_row++; } while (dst_row < dst_rows) { - char32_t *dst_line = dst->lines[dst_row]; + u32 *dst_line = dst_lines[dst_row]; memset32(dst_line, ' ', dst_cols); dst_row++; @@ -500,23 +478,20 @@ static void vc_uniscr_copy_area(struct uni_screen *dst, */ int vc_uniscr_check(struct vc_data *vc) { - struct uni_screen *uniscr; + u32 **uni_lines; unsigned short *p; int x, y, mask; - if (__is_defined(NO_VC_UNI_SCREEN)) - return -EOPNOTSUPP; - WARN_CONSOLE_UNLOCKED(); if (!vc->vc_utf) return -ENODATA; - if (vc->vc_uni_screen) + if (vc->vc_uni_lines) return 0; - uniscr = vc_uniscr_alloc(vc->vc_cols, vc->vc_rows); - if (!uniscr) + uni_lines = vc_uniscr_alloc(vc->vc_cols, vc->vc_rows); + if (!uni_lines) return -ENOMEM; /* @@ -528,14 +503,15 @@ int vc_uniscr_check(struct vc_data *vc) p = (unsigned short *)vc->vc_origin; mask = vc->vc_hi_font_mask | 0xff; for (y = 0; y < vc->vc_rows; y++) { - char32_t *line = uniscr->lines[y]; + u32 *line = uni_lines[y]; for (x = 0; x < vc->vc_cols; x++) { u16 glyph = scr_readw(p++) & mask; line[x] = inverse_translate(vc, glyph, true); } } - vc->vc_uni_screen = uniscr; + vc->vc_uni_lines = uni_lines; + return 0; } @@ -547,11 +523,12 @@ int vc_uniscr_check(struct vc_data *vc) void vc_uniscr_copy_line(const struct vc_data *vc, void *dest, bool viewed, unsigned int row, unsigned int col, unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); + u32 **uni_lines = vc->vc_uni_lines; int offset = row * vc->vc_size_row + col * 2; unsigned long pos; - BUG_ON(!uniscr); + if (WARN_ON_ONCE(!uni_lines)) + return; pos = (unsigned long)screenpos(vc, offset, viewed); if (pos >= vc->vc_origin && pos < vc->vc_scr_end) { @@ -562,7 +539,7 @@ void vc_uniscr_copy_line(const struct vc_data *vc, void *dest, bool viewed, */ row = (pos - vc->vc_origin) / vc->vc_size_row; col = ((pos - vc->vc_origin) % vc->vc_size_row) / 2; - memcpy(dest, &uniscr->lines[row][col], nr * sizeof(char32_t)); + memcpy(dest, &uni_lines[row][col], nr * sizeof(u32)); } else { /* * Scrollback is active. For now let's simply backtranslate @@ -572,7 +549,7 @@ void vc_uniscr_copy_line(const struct vc_data *vc, void *dest, bool viewed, */ u16 *p = (u16 *)pos; int mask = vc->vc_hi_font_mask | 0xff; - char32_t *uni_buf = dest; + u32 *uni_buf = dest; while (nr--) { u16 glyph = scr_readw(p++) & mask; *uni_buf++ = inverse_translate(vc, glyph, true); @@ -580,64 +557,31 @@ void vc_uniscr_copy_line(const struct vc_data *vc, void *dest, bool viewed, } } -/* this is for validation and debugging only */ -static void vc_uniscr_debug_check(struct vc_data *vc) +static void con_scroll(struct vc_data *vc, unsigned int top, + unsigned int bottom, enum con_scroll dir, + unsigned int nr) { - struct uni_screen *uniscr = get_vc_uniscr(vc); - unsigned short *p; - int x, y, mask; + unsigned int rows = bottom - top; + u16 *clear, *dst, *src; - if (!VC_UNI_SCREEN_DEBUG || !uniscr) + if (top + nr >= bottom) + nr = rows - 1; + if (bottom > vc->vc_rows || top >= bottom || nr < 1) return; - WARN_CONSOLE_UNLOCKED(); - - /* - * Make sure our unicode screen translates into the same glyphs - * as the actual screen. This is brutal indeed. - */ - p = (unsigned short *)vc->vc_origin; - mask = vc->vc_hi_font_mask | 0xff; - for (y = 0; y < vc->vc_rows; y++) { - char32_t *line = uniscr->lines[y]; - for (x = 0; x < vc->vc_cols; x++) { - u16 glyph = scr_readw(p++) & mask; - char32_t uc = line[x]; - int tc = conv_uni_to_pc(vc, uc); - if (tc == -4) - tc = conv_uni_to_pc(vc, 0xfffd); - if (tc == -4) - tc = conv_uni_to_pc(vc, '?'); - if (tc != glyph) - pr_err_ratelimited( - "%s: mismatch at %d,%d: glyph=%#x tc=%#x\n", - __func__, x, y, glyph, tc); - } - } -} - - -static void con_scroll(struct vc_data *vc, unsigned int t, unsigned int b, - enum con_scroll dir, unsigned int nr) -{ - u16 *clear, *d, *s; - - if (t + nr >= b) - nr = b - t - 1; - if (b > vc->vc_rows || t >= b || nr < 1) - return; - vc_uniscr_scroll(vc, t, b, dir, nr); - if (con_is_visible(vc) && vc->vc_sw->con_scroll(vc, t, b, dir, nr)) + vc_uniscr_scroll(vc, top, bottom, dir, nr); + if (con_is_visible(vc) && + vc->vc_sw->con_scroll(vc, top, bottom, dir, nr)) return; - s = clear = (u16 *)(vc->vc_origin + vc->vc_size_row * t); - d = (u16 *)(vc->vc_origin + vc->vc_size_row * (t + nr)); + src = clear = (u16 *)(vc->vc_origin + vc->vc_size_row * top); + dst = (u16 *)(vc->vc_origin + vc->vc_size_row * (top + nr)); if (dir == SM_UP) { - clear = s + (b - t - nr) * vc->vc_cols; - swap(s, d); + clear = src + (rows - nr) * vc->vc_cols; + swap(src, dst); } - scr_memmovew(d, s, (b - t - nr) * vc->vc_size_row); + scr_memmovew(dst, src, (rows - nr) * vc->vc_size_row); scr_memsetw(clear, vc->vc_video_erase_char, vc->vc_size_row * nr); } @@ -1201,7 +1145,7 @@ static int vc_do_resize(struct tty_struct *tty, struct vc_data *vc, unsigned int new_cols, new_rows, new_row_size, new_screen_size; unsigned int user; unsigned short *oldscreen, *newscreen; - struct uni_screen *new_uniscr = NULL; + u32 **new_uniscr = NULL; WARN_CONSOLE_UNLOCKED(); @@ -1245,7 +1189,7 @@ static int vc_do_resize(struct tty_struct *tty, struct vc_data *vc, if (!newscreen) return -ENOMEM; - if (get_vc_uniscr(vc)) { + if (vc->vc_uni_lines) { new_uniscr = vc_uniscr_alloc(new_cols, new_rows); if (!new_uniscr) { kfree(newscreen); @@ -1297,7 +1241,7 @@ static int vc_do_resize(struct tty_struct *tty, struct vc_data *vc, end = old_origin + old_row_size * min(old_rows, new_rows); vc_uniscr_copy_area(new_uniscr, new_cols, new_rows, - get_vc_uniscr(vc), rlth/2, first_copied_row, + vc->vc_uni_lines, rlth/2, first_copied_row, min(old_rows, new_rows)); vc_uniscr_set(vc, new_uniscr); @@ -2959,7 +2903,6 @@ rescan_last_byte: goto rescan_last_byte; } con_flush(vc, &draw); - vc_uniscr_debug_check(vc); console_conditional_schedule(); notify_update(vc); console_unlock(); @@ -3156,8 +3099,14 @@ static struct tty_driver *vt_console_device(struct console *c, int *index) return console_driver; } +static int vt_console_setup(struct console *co, char *options) +{ + return co->index >= MAX_NR_CONSOLES ? -EINVAL : 0; +} + static struct console vt_console_driver = { .name = "tty", + .setup = vt_console_setup, .write = vt_console_print, .device = vt_console_device, .unblank = unblank_screen, @@ -4574,26 +4523,30 @@ void reset_palette(struct vc_data *vc) /* * Font switching * - * Currently we only support fonts up to 32 pixels wide, at a maximum height - * of 32 pixels. Userspace fontdata is stored with 32 bytes (shorts/ints, - * depending on width) reserved for each character which is kinda wasty, but - * this is done in order to maintain compatibility with the EGA/VGA fonts. It - * is up to the actual low-level console-driver convert data into its favorite - * format (maybe we should add a `fontoffset' field to the `display' - * structure so we won't have to convert the fontdata all the time. + * Currently we only support fonts up to 128 pixels wide, at a maximum height + * of 128 pixels. Userspace fontdata may have to be stored with 32 bytes + * (shorts/ints, depending on width) reserved for each character which is + * kinda wasty, but this is done in order to maintain compatibility with the + * EGA/VGA fonts. It is up to the actual low-level console-driver convert data + * into its favorite format (maybe we should add a `fontoffset' field to the + * `display' structure so we won't have to convert the fontdata all the time. * /Jes */ -#define max_font_size 65536 +#define max_font_width 64 +#define max_font_height 128 +#define max_font_glyphs 512 +#define max_font_size (max_font_glyphs*max_font_width*max_font_height) static int con_font_get(struct vc_data *vc, struct console_font_op *op) { struct console_font font; int rc = -EINVAL; int c; + unsigned int vpitch = op->op == KD_FONT_OP_GET_TALL ? op->height : 32; if (op->data) { - font.data = kmalloc(max_font_size, GFP_KERNEL); + font.data = kvmalloc(max_font_size, GFP_KERNEL); if (!font.data) return -ENOMEM; } else @@ -4603,7 +4556,7 @@ static int con_font_get(struct vc_data *vc, struct console_font_op *op) if (vc->vc_mode != KD_TEXT) rc = -EINVAL; else if (vc->vc_sw->con_font_get) - rc = vc->vc_sw->con_font_get(vc, &font); + rc = vc->vc_sw->con_font_get(vc, &font, vpitch); else rc = -ENOSYS; console_unlock(); @@ -4611,7 +4564,7 @@ static int con_font_get(struct vc_data *vc, struct console_font_op *op) if (rc) goto out; - c = (font.width+7)/8 * 32 * font.charcount; + c = (font.width+7)/8 * vpitch * font.charcount; if (op->data && font.charcount > op->charcount) rc = -ENOSPC; @@ -4628,7 +4581,7 @@ static int con_font_get(struct vc_data *vc, struct console_font_op *op) rc = -EFAULT; out: - kfree(font.data); + kvfree(font.data); return rc; } @@ -4637,16 +4590,20 @@ static int con_font_set(struct vc_data *vc, struct console_font_op *op) struct console_font font; int rc = -EINVAL; int size; + unsigned int vpitch = op->op == KD_FONT_OP_SET_TALL ? op->height : 32; if (vc->vc_mode != KD_TEXT) return -EINVAL; if (!op->data) return -EINVAL; - if (op->charcount > 512) + if (op->charcount > max_font_glyphs) return -EINVAL; - if (op->width <= 0 || op->width > 32 || !op->height || op->height > 32) + if (op->width <= 0 || op->width > max_font_width || !op->height || + op->height > max_font_height) return -EINVAL; - size = (op->width+7)/8 * 32 * op->charcount; + if (vpitch < op->height) + return -EINVAL; + size = (op->width+7)/8 * vpitch * op->charcount; if (size > max_font_size) return -ENOSPC; @@ -4664,7 +4621,7 @@ static int con_font_set(struct vc_data *vc, struct console_font_op *op) else if (vc->vc_sw->con_font_set) { if (vc_is_sel(vc)) clear_selection(); - rc = vc->vc_sw->con_font_set(vc, &font, op->flags); + rc = vc->vc_sw->con_font_set(vc, &font, vpitch, op->flags); } else rc = -ENOSYS; console_unlock(); @@ -4710,8 +4667,10 @@ int con_font_op(struct vc_data *vc, struct console_font_op *op) { switch (op->op) { case KD_FONT_OP_SET: + case KD_FONT_OP_SET_TALL: return con_font_set(vc, op); case KD_FONT_OP_GET: + case KD_FONT_OP_GET_TALL: return con_font_get(vc, op); case KD_FONT_OP_SET_DEFAULT: return con_font_default(vc, op); @@ -4740,10 +4699,11 @@ EXPORT_SYMBOL_GPL(screen_glyph); u32 screen_glyph_unicode(const struct vc_data *vc, int n) { - struct uni_screen *uniscr = get_vc_uniscr(vc); + u32 **uni_lines = vc->vc_uni_lines; + + if (uni_lines) + return uni_lines[n / vc->vc_cols][n % vc->vc_cols]; - if (uniscr) - return uniscr->lines[n / vc->vc_cols][n % vc->vc_cols]; return inverse_translate(vc, screen_glyph(vc, n * 2), true); } EXPORT_SYMBOL_GPL(screen_glyph_unicode); diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c index 36bf051b345b..11da5fb284d0 100644 --- a/drivers/usb/class/cdc-acm.c +++ b/drivers/usb/class/cdc-acm.c @@ -651,13 +651,13 @@ static int acm_tty_open(struct tty_struct *tty, struct file *filp) return tty_port_open(&acm->port, tty, filp); } -static void acm_port_dtr_rts(struct tty_port *port, int raise) +static void acm_port_dtr_rts(struct tty_port *port, bool active) { struct acm *acm = container_of(port, struct acm, port); int val; int res; - if (raise) + if (active) val = USB_CDC_CTRL_DTR | USB_CDC_CTRL_RTS; else val = 0; diff --git a/drivers/usb/serial/console.c b/drivers/usb/serial/console.c index da19a5fa414f..c3ea3a46ed76 100644 --- a/drivers/usb/serial/console.c +++ b/drivers/usb/serial/console.c @@ -169,7 +169,7 @@ static int usb_console_setup(struct console *co, char *options) tty_save_termios(tty); tty_kref_put(tty); } - tty_port_set_initialized(&port->port, 1); + tty_port_set_initialized(&port->port, true); } /* Now that any required fake tty operations are completed restore * the tty port count */ diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c index 164521ee10c6..f8404073558b 100644 --- a/drivers/usb/serial/usb-serial.c +++ b/drivers/usb/serial/usb-serial.c @@ -754,7 +754,7 @@ static struct usb_serial_driver *search_serial_device( return NULL; } -static int serial_port_carrier_raised(struct tty_port *port) +static bool serial_port_carrier_raised(struct tty_port *port) { struct usb_serial_port *p = container_of(port, struct usb_serial_port, port); struct usb_serial_driver *drv = p->serial->type; @@ -762,10 +762,10 @@ static int serial_port_carrier_raised(struct tty_port *port) if (drv->carrier_raised) return drv->carrier_raised(p); /* No carrier control - don't block */ - return 1; + return true; } -static void serial_port_dtr_rts(struct tty_port *port, int on) +static void serial_port_dtr_rts(struct tty_port *port, bool on) { struct usb_serial_port *p = container_of(port, struct usb_serial_port, port); struct usb_serial_driver *drv = p->serial->type; diff --git a/drivers/video/console/newport_con.c b/drivers/video/console/newport_con.c index d9c682ae0392..e8e4f82cd4a1 100644 --- a/drivers/video/console/newport_con.c +++ b/drivers/video/console/newport_con.c @@ -497,7 +497,7 @@ static int newport_blank(struct vc_data *c, int blank, int mode_switch) return 1; } -static int newport_set_font(int unit, struct console_font *op) +static int newport_set_font(int unit, struct console_font *op, unsigned int vpitch) { int w = op->width; int h = op->height; @@ -507,7 +507,7 @@ static int newport_set_font(int unit, struct console_font *op) /* ladis: when I grow up, there will be a day... and more sizes will * be supported ;-) */ - if ((w != 8) || (h != 16) + if ((w != 8) || (h != 16) || (vpitch != 32) || (op->charcount != 256 && op->charcount != 512)) return -EINVAL; @@ -569,9 +569,10 @@ static int newport_font_default(struct vc_data *vc, struct console_font *op, cha return newport_set_def_font(vc->vc_num, op); } -static int newport_font_set(struct vc_data *vc, struct console_font *font, unsigned flags) +static int newport_font_set(struct vc_data *vc, struct console_font *font, + unsigned int vpitch, unsigned int flags) { - return newport_set_font(vc->vc_num, font); + return newport_set_font(vc->vc_num, font, vpitch); } static bool newport_scroll(struct vc_data *vc, unsigned int t, unsigned int b, diff --git a/drivers/video/console/sticon.c b/drivers/video/console/sticon.c index f304163e87e9..2cea69418a83 100644 --- a/drivers/video/console/sticon.c +++ b/drivers/video/console/sticon.c @@ -169,7 +169,8 @@ static int sticon_set_def_font(int unit, struct console_font *op) return 0; } -static int sticon_set_font(struct vc_data *vc, struct console_font *op) +static int sticon_set_font(struct vc_data *vc, struct console_font *op, + unsigned int vpitch) { struct sti_struct *sti = sticon_sti; int vc_cols, vc_rows, vc_old_cols, vc_old_rows; @@ -181,7 +182,7 @@ static int sticon_set_font(struct vc_data *vc, struct console_font *op) struct sti_cooked_font *cooked_font; unsigned char *data = op->data, *p; - if ((w < 6) || (h < 6) || (w > 32) || (h > 32) + if ((w < 6) || (h < 6) || (w > 32) || (h > 32) || (vpitch != 32) || (op->charcount != 256 && op->charcount != 512)) return -EINVAL; pitch = ALIGN(w, 8) / 8; @@ -267,9 +268,9 @@ static int sticon_font_default(struct vc_data *vc, struct console_font *op, char } static int sticon_font_set(struct vc_data *vc, struct console_font *font, - unsigned int flags) + unsigned int vpitch, unsigned int flags) { - return sticon_set_font(vc, font); + return sticon_set_font(vc, font, vpitch); } static void sticon_init(struct vc_data *c, int init) diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c index fcdf017e2665..e25ba523892e 100644 --- a/drivers/video/console/vgacon.c +++ b/drivers/video/console/vgacon.c @@ -1029,7 +1029,7 @@ static int vgacon_adjust_height(struct vc_data *vc, unsigned fontheight) } static int vgacon_font_set(struct vc_data *c, struct console_font *font, - unsigned int flags) + unsigned int vpitch, unsigned int flags) { unsigned charcount = font->charcount; int rc; @@ -1037,7 +1037,7 @@ static int vgacon_font_set(struct vc_data *c, struct console_font *font, if (vga_video_type < VIDEO_TYPE_EGAM) return -EINVAL; - if (font->width != VGA_FONTWIDTH || + if (font->width != VGA_FONTWIDTH || font->height > 32 || vpitch != 32 || (charcount != 256 && charcount != 512)) return -EINVAL; @@ -1050,9 +1050,9 @@ static int vgacon_font_set(struct vc_data *c, struct console_font *font, return rc; } -static int vgacon_font_get(struct vc_data *c, struct console_font *font) +static int vgacon_font_get(struct vc_data *c, struct console_font *font, unsigned int vpitch) { - if (vga_video_type < VIDEO_TYPE_EGAM) + if (vga_video_type < VIDEO_TYPE_EGAM || vpitch != 32) return -EINVAL; font->width = VGA_FONTWIDTH; diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c index 94d4ed0331c9..0a2c47df01f4 100644 --- a/drivers/video/fbdev/core/fbcon.c +++ b/drivers/video/fbdev/core/fbcon.c @@ -2266,7 +2266,7 @@ static int fbcon_debug_leave(struct vc_data *vc) return 0; } -static int fbcon_get_font(struct vc_data *vc, struct console_font *font) +static int fbcon_get_font(struct vc_data *vc, struct console_font *font, unsigned int vpitch) { u8 *fontdata = vc->vc_font.data; u8 *data = font->data; @@ -2274,6 +2274,8 @@ static int fbcon_get_font(struct vc_data *vc, struct console_font *font) font->width = vc->vc_font.width; font->height = vc->vc_font.height; + if (font->height > vpitch) + return -ENOSPC; font->charcount = vc->vc_hi_font_mask ? 512 : 256; if (!font->data) return 0; @@ -2285,8 +2287,8 @@ static int fbcon_get_font(struct vc_data *vc, struct console_font *font) for (i = 0; i < font->charcount; i++) { memcpy(data, fontdata, j); - memset(data + j, 0, 32 - j); - data += 32; + memset(data + j, 0, vpitch - j); + data += vpitch; fontdata += j; } } else if (font->width <= 16) { @@ -2296,8 +2298,8 @@ static int fbcon_get_font(struct vc_data *vc, struct console_font *font) for (i = 0; i < font->charcount; i++) { memcpy(data, fontdata, j); - memset(data + j, 0, 64 - j); - data += 64; + memset(data + j, 0, 2*vpitch - j); + data += 2*vpitch; fontdata += j; } } else if (font->width <= 24) { @@ -2311,8 +2313,8 @@ static int fbcon_get_font(struct vc_data *vc, struct console_font *font) *data++ = fontdata[2]; fontdata += sizeof(u32); } - memset(data, 0, 3 * (32 - j)); - data += 3 * (32 - j); + memset(data, 0, 3 * (vpitch - j)); + data += 3 * (vpitch - j); } } else { j = vc->vc_font.height * 4; @@ -2321,8 +2323,8 @@ static int fbcon_get_font(struct vc_data *vc, struct console_font *font) for (i = 0; i < font->charcount; i++) { memcpy(data, fontdata, j); - memset(data + j, 0, 128 - j); - data += 128; + memset(data + j, 0, 4 * vpitch - j); + data += 4 * vpitch; fontdata += j; } } @@ -2457,19 +2459,12 @@ err_out: } /* - * User asked to set font; we are guaranteed that - * a) width and height are in range 1..32 - * b) charcount does not exceed 512 - * but lets not assume that, since someone might someday want to use larger - * fonts. And charcount of 512 is small for unicode support. - * - * However, user space gives the font in 32 rows , regardless of - * actual font height. So a new API is needed if support for larger fonts - * is ever implemented. + * User asked to set font; we are guaranteed that charcount does not exceed 512 + * but lets not assume that, since charcount of 512 is small for unicode support. */ static int fbcon_set_font(struct vc_data *vc, struct console_font *font, - unsigned int flags) + unsigned int vpitch, unsigned int flags) { struct fb_info *info = fbcon_info_from_console(vc->vc_num); unsigned charcount = font->charcount; @@ -2515,7 +2510,7 @@ static int fbcon_set_font(struct vc_data *vc, struct console_font *font, FNTSIZE(new_data) = size; REFCOUNT(new_data) = 0; /* usage counter */ for (i=0; i< charcount; i++) { - memcpy(new_data + i*h*pitch, data + i*32*pitch, h*pitch); + memcpy(new_data + i*h*pitch, data + i*vpitch*pitch, h*pitch); } /* Since linux has a nice crc32 function use it for counting font diff --git a/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h b/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h new file mode 100644 index 000000000000..f21c39d0928e --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sa8775p-rpmh.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H + +/* aggre1_noc */ +#define MASTER_QUP_3 0 +#define MASTER_EMAC 1 +#define MASTER_EMAC_1 2 +#define MASTER_SDC 3 +#define MASTER_UFS_MEM 4 +#define MASTER_USB2 5 +#define MASTER_USB3_0 6 +#define MASTER_USB3_1 7 +#define SLAVE_A1NOC_SNOC 8 + +/* aggre2_noc */ +#define MASTER_QDSS_BAM 0 +#define MASTER_QUP_0 1 +#define MASTER_QUP_1 2 +#define MASTER_QUP_2 3 +#define MASTER_CNOC_A2NOC 4 +#define MASTER_CRYPTO_CORE0 5 +#define MASTER_CRYPTO_CORE1 6 +#define MASTER_IPA 7 +#define MASTER_QDSS_ETR_0 8 +#define MASTER_QDSS_ETR_1 9 +#define MASTER_UFS_CARD 10 +#define SLAVE_A2NOC_SNOC 11 + +/* clk_virt */ +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define SLAVE_QUP_CORE_0 4 +#define SLAVE_QUP_CORE_1 5 +#define SLAVE_QUP_CORE_2 6 +#define SLAVE_QUP_CORE_3 7 + +/* config_noc */ +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AHB2PHY_0 2 +#define SLAVE_AHB2PHY_1 3 +#define SLAVE_AHB2PHY_2 4 +#define SLAVE_AHB2PHY_3 5 +#define SLAVE_ANOC_THROTTLE_CFG 6 +#define SLAVE_AOSS 7 +#define SLAVE_APPSS 8 +#define SLAVE_BOOT_ROM 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 11 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 12 +#define SLAVE_CLK_CTL 13 +#define SLAVE_CDSP_CFG 14 +#define SLAVE_CDSP1_CFG 15 +#define SLAVE_RBCPR_CX_CFG 16 +#define SLAVE_RBCPR_MMCX_CFG 17 +#define SLAVE_RBCPR_MX_CFG 18 +#define SLAVE_CPR_NSPCX 19 +#define SLAVE_CRYPTO_0_CFG 20 +#define SLAVE_CX_RDPM 21 +#define SLAVE_DISPLAY_CFG 22 +#define SLAVE_DISPLAY_RT_THROTTLE_CFG 23 +#define SLAVE_DISPLAY1_CFG 24 +#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 25 +#define SLAVE_EMAC_CFG 26 +#define SLAVE_EMAC1_CFG 27 +#define SLAVE_GP_DSP0_CFG 28 +#define SLAVE_GP_DSP1_CFG 29 +#define SLAVE_GPDSP0_THROTTLE_CFG 30 +#define SLAVE_GPDSP1_THROTTLE_CFG 31 +#define SLAVE_GPU_TCU_THROTTLE_CFG 32 +#define SLAVE_GFX3D_CFG 33 +#define SLAVE_HWKM 34 +#define SLAVE_IMEM_CFG 35 +#define SLAVE_IPA_CFG 36 +#define SLAVE_IPC_ROUTER_CFG 37 +#define SLAVE_LPASS 38 +#define SLAVE_LPASS_THROTTLE_CFG 39 +#define SLAVE_MX_RDPM 40 +#define SLAVE_MXC_RDPM 41 +#define SLAVE_PCIE_0_CFG 42 +#define SLAVE_PCIE_1_CFG 43 +#define SLAVE_PCIE_RSC_CFG 44 +#define SLAVE_PCIE_TCU_THROTTLE_CFG 45 +#define SLAVE_PCIE_THROTTLE_CFG 46 +#define SLAVE_PDM 47 +#define SLAVE_PIMEM_CFG 48 +#define SLAVE_PKA_WRAPPER_CFG 49 +#define SLAVE_QDSS_CFG 50 +#define SLAVE_QM_CFG 51 +#define SLAVE_QM_MPU_CFG 52 +#define SLAVE_QUP_0 53 +#define SLAVE_QUP_1 54 +#define SLAVE_QUP_2 55 +#define SLAVE_QUP_3 56 +#define SLAVE_SAIL_THROTTLE_CFG 57 +#define SLAVE_SDC1 58 +#define SLAVE_SECURITY 59 +#define SLAVE_SNOC_THROTTLE_CFG 60 +#define SLAVE_TCSR 61 +#define SLAVE_TLMM 62 +#define SLAVE_TSC_CFG 63 +#define SLAVE_UFS_CARD_CFG 64 +#define SLAVE_UFS_MEM_CFG 65 +#define SLAVE_USB2 66 +#define SLAVE_USB3_0 67 +#define SLAVE_USB3_1 68 +#define SLAVE_VENUS_CFG 69 +#define SLAVE_VENUS_CVP_THROTTLE_CFG 70 +#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 71 +#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 72 +#define SLAVE_DDRSS_CFG 73 +#define SLAVE_GPDSP_NOC_CFG 74 +#define SLAVE_CNOC_MNOC_HF_CFG 75 +#define SLAVE_CNOC_MNOC_SF_CFG 76 +#define SLAVE_PCIE_ANOC_CFG 77 +#define SLAVE_SNOC_CFG 78 +#define SLAVE_BOOT_IMEM 79 +#define SLAVE_IMEM 80 +#define SLAVE_PIMEM 81 +#define SLAVE_PCIE_0 82 +#define SLAVE_PCIE_1 83 +#define SLAVE_QDSS_STM 84 +#define SLAVE_TCU 85 + +/* dc_noc */ +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_GEM_NOC_CFG 2 + +/* gem_noc */ +#define MASTER_GPU_TCU 0 +#define MASTER_PCIE_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_APPSS_PROC 3 +#define MASTER_COMPUTE_NOC 4 +#define MASTER_COMPUTE_NOC_1 5 +#define MASTER_GEM_NOC_CFG 6 +#define MASTER_GPDSP_SAIL 7 +#define MASTER_GFX3D 8 +#define MASTER_MNOC_HF_MEM_NOC 9 +#define MASTER_MNOC_SF_MEM_NOC 10 +#define MASTER_ANOC_PCIE_GEM_NOC 11 +#define MASTER_SNOC_GC_MEM_NOC 12 +#define MASTER_SNOC_SF_MEM_NOC 13 +#define SLAVE_GEM_NOC_CNOC 14 +#define SLAVE_LLCC 15 +#define SLAVE_GEM_NOC_PCIE_CNOC 16 +#define SLAVE_SERVICE_GEM_NOC_1 17 +#define SLAVE_SERVICE_GEM_NOC_2 18 +#define SLAVE_SERVICE_GEM_NOC 19 +#define SLAVE_SERVICE_GEM_NOC2 20 + +/* gpdsp_anoc */ +#define MASTER_DSP0 0 +#define MASTER_DSP1 1 +#define SLAVE_GP_DSP_SAIL_NOC 2 + +/* lpass_ag_noc */ +#define MASTER_CNOC_LPASS_AG_NOC 0 +#define MASTER_LPASS_PROC 1 +#define SLAVE_LPASS_CORE_CFG 2 +#define SLAVE_LPASS_LPI_CFG 3 +#define SLAVE_LPASS_MPU_CFG 4 +#define SLAVE_LPASS_TOP_CFG 5 +#define SLAVE_LPASS_SNOC 6 +#define SLAVE_SERVICES_LPASS_AML_NOC 7 +#define SLAVE_SERVICE_LPASS_AG_NOC 8 + +/* mc_virt */ +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +/*mmss_noc */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_ICP 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_MDP0 3 +#define MASTER_MDP1 4 +#define MASTER_MDP_CORE1_0 5 +#define MASTER_MDP_CORE1_1 6 +#define MASTER_CNOC_MNOC_HF_CFG 7 +#define MASTER_CNOC_MNOC_SF_CFG 8 +#define MASTER_VIDEO_P0 9 +#define MASTER_VIDEO_P1 10 +#define MASTER_VIDEO_PROC 11 +#define MASTER_VIDEO_V_PROC 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 +#define SLAVE_SERVICE_MNOC_HF 15 +#define SLAVE_SERVICE_MNOC_SF 16 + +/* nspa_noc */ +#define MASTER_CDSP_NOC_CFG 0 +#define MASTER_CDSP_PROC 1 +#define SLAVE_HCP_A 2 +#define SLAVE_CDSP_MEM_NOC 3 +#define SLAVE_SERVICE_NSP_NOC 4 + +/* nspb_noc */ +#define MASTER_CDSPB_NOC_CFG 0 +#define MASTER_CDSP_PROC_B 1 +#define SLAVE_CDSPB_MEM_NOC 2 +#define SLAVE_HCP_B 3 +#define SLAVE_SERVICE_NSPB_NOC 4 + +/* pcie_anoc */ +#define MASTER_PCIE_0 0 +#define MASTER_PCIE_1 1 +#define SLAVE_ANOC_PCIE_GEM_NOC 2 + +/* system_noc */ +#define MASTER_GIC_AHB 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_LPASS_ANOC 3 +#define MASTER_SNOC_CFG 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_SNOC_GEM_NOC_GC 7 +#define SLAVE_SNOC_GEM_NOC_SF 8 +#define SLAVE_SERVICE_SNOC 9 + +#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_SA8775P_H */ diff --git a/include/dt-bindings/interconnect/qcom,sc7180.h b/include/dt-bindings/interconnect/qcom,sc7180.h index f9970f6032eb..de5d5867bd67 100644 --- a/include/dt-bindings/interconnect/qcom,sc7180.h +++ b/include/dt-bindings/interconnect/qcom,sc7180.h @@ -108,9 +108,6 @@ #define SLAVE_LLCC 11 #define SLAVE_SERVICE_GEM_NOC 12 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI1 1 diff --git a/include/dt-bindings/interconnect/qcom,sc8180x.h b/include/dt-bindings/interconnect/qcom,sc8180x.h index e84cfec5afdd..0bdc8d6cb401 100644 --- a/include/dt-bindings/interconnect/qcom,sc8180x.h +++ b/include/dt-bindings/interconnect/qcom,sc8180x.h @@ -129,9 +129,6 @@ #define SLAVE_SERVICE_GEM_NOC 16 #define SLAVE_SERVICE_GEM_NOC_1 17 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sc8280xp.h b/include/dt-bindings/interconnect/qcom,sc8280xp.h index a3e5fda7c127..f89f47e99c6d 100644 --- a/include/dt-bindings/interconnect/qcom,sc8280xp.h +++ b/include/dt-bindings/interconnect/qcom,sc8280xp.h @@ -48,11 +48,11 @@ #define SLAVE_SERVICE_A2NOC 19 /* clk_virt */ -#define MASTER_IPA_CORE 0 +/* 0 was used by MASTER_IPA_CORE, now represented as RPMh clock */ #define MASTER_QUP_CORE_0 1 #define MASTER_QUP_CORE_1 2 #define MASTER_QUP_CORE_2 3 -#define SLAVE_IPA_CORE 4 +/* 4 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ #define SLAVE_QUP_CORE_0 5 #define SLAVE_QUP_CORE_1 6 #define SLAVE_QUP_CORE_2 7 diff --git a/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h b/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h new file mode 100644 index 000000000000..9b516cc360bb --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sdm670-rpmh.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Qualcomm SDM670 interconnect IDs + * + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SDM670_H + +#define MASTER_A1NOC_CFG 0 +#define MASTER_BLSP_1 1 +#define MASTER_TSIF 2 +#define MASTER_EMMC 3 +#define MASTER_SDCC_2 4 +#define MASTER_SDCC_4 5 +#define MASTER_UFS_MEM 6 +#define SLAVE_A1NOC_SNOC 7 +#define SLAVE_SERVICE_A1NOC 8 + +#define MASTER_A2NOC_CFG 0 +#define MASTER_QDSS_BAM 1 +#define MASTER_BLSP_2 2 +#define MASTER_CNOC_A2NOC 3 +#define MASTER_CRYPTO_CORE_0 4 +#define MASTER_IPA 5 +#define MASTER_QDSS_ETR 6 +#define MASTER_USB3 7 +#define SLAVE_A2NOC_SNOC 8 +#define SLAVE_SERVICE_A2NOC 9 + + +#define MASTER_SPDM 0 +#define MASTER_SNOC_CNOC 1 +#define SLAVE_A1NOC_CFG 2 +#define SLAVE_A2NOC_CFG 3 +#define SLAVE_AOP 4 +#define SLAVE_AOSS 5 +#define SLAVE_CAMERA_CFG 6 +#define SLAVE_CLK_CTL 7 +#define SLAVE_CDSP_CFG 8 +#define SLAVE_RBCPR_CX_CFG 9 +#define SLAVE_CRYPTO_0_CFG 10 +#define SLAVE_DCC_CFG 11 +#define SLAVE_CNOC_DDRSS 12 +#define SLAVE_DISPLAY_CFG 13 +#define SLAVE_EMMC_CFG 14 +#define SLAVE_GLM 15 +#define SLAVE_GRAPHICS_3D_CFG 16 +#define SLAVE_IMEM_CFG 17 +#define SLAVE_IPA_CFG 18 +#define SLAVE_CNOC_MNOC_CFG 19 +#define SLAVE_PDM 20 +#define SLAVE_SOUTH_PHY_CFG 21 +#define SLAVE_PIMEM_CFG 22 +#define SLAVE_PRNG 23 +#define SLAVE_QDSS_CFG 24 +#define SLAVE_BLSP_2 25 +#define SLAVE_BLSP_1 26 +#define SLAVE_SDCC_2 27 +#define SLAVE_SDCC_4 28 +#define SLAVE_SNOC_CFG 29 +#define SLAVE_SPDM_WRAPPER 30 +#define SLAVE_TCSR 31 +#define SLAVE_TLMM_NORTH 32 +#define SLAVE_TLMM_SOUTH 33 +#define SLAVE_TSIF 34 +#define SLAVE_UFS_MEM_CFG 35 +#define SLAVE_USB3 36 +#define SLAVE_VENUS_CFG 37 +#define SLAVE_VSENSE_CTRL_CFG 38 +#define SLAVE_CNOC_A2NOC 39 +#define SLAVE_SERVICE_CNOC 40 + +#define MASTER_CNOC_DC_NOC 0 +#define SLAVE_LLCC_CFG 1 +#define SLAVE_MEM_NOC_CFG 2 + +#define MASTER_AMPSS_M0 0 +#define MASTER_GNOC_CFG 1 +#define SLAVE_GNOC_SNOC 2 +#define SLAVE_GNOC_MEM_NOC 3 +#define SLAVE_SERVICE_GNOC 4 + +#define MASTER_TCU_0 0 +#define MASTER_MEM_NOC_CFG 1 +#define MASTER_GNOC_MEM_NOC 2 +#define MASTER_MNOC_HF_MEM_NOC 3 +#define MASTER_MNOC_SF_MEM_NOC 4 +#define MASTER_SNOC_GC_MEM_NOC 5 +#define MASTER_SNOC_SF_MEM_NOC 6 +#define MASTER_GRAPHICS_3D 7 +#define SLAVE_MSS_PROC_MS_MPU_CFG 8 +#define SLAVE_MEM_NOC_GNOC 9 +#define SLAVE_LLCC 10 +#define SLAVE_MEM_NOC_SNOC 11 +#define SLAVE_SERVICE_MEM_NOC 12 +#define MASTER_LLCC 13 +#define SLAVE_EBI_CH0 14 + +#define MASTER_CNOC_MNOC_CFG 0 +#define MASTER_CAMNOC_HF0 1 +#define MASTER_CAMNOC_HF1 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_MDP_PORT0 4 +#define MASTER_MDP_PORT1 5 +#define MASTER_ROTATOR 6 +#define MASTER_VIDEO_P0 7 +#define MASTER_VIDEO_P1 8 +#define MASTER_VIDEO_PROC 9 +#define SLAVE_MNOC_SF_MEM_NOC 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC 12 + +#define MASTER_SNOC_CFG 0 +#define MASTER_A1NOC_SNOC 1 +#define MASTER_A2NOC_SNOC 2 +#define MASTER_GNOC_SNOC 3 +#define MASTER_MEM_NOC_SNOC 4 +#define MASTER_PIMEM 5 +#define MASTER_GIC 6 +#define SLAVE_APPSS 7 +#define SLAVE_SNOC_CNOC 8 +#define SLAVE_SNOC_MEM_NOC_GC 9 +#define SLAVE_SNOC_MEM_NOC_SF 10 +#define SLAVE_OCIMEM 11 +#define SLAVE_PIMEM 12 +#define SLAVE_SERVICE_SNOC 13 +#define SLAVE_QDSS_STM 14 +#define SLAVE_TCU 15 +#define MASTER_CAMNOC_HF0_UNCOMP 16 +#define MASTER_CAMNOC_HF1_UNCOMP 17 +#define MASTER_CAMNOC_SF_UNCOMP 18 +#define SLAVE_CAMNOC_UNCOMP 19 + +#endif diff --git a/include/dt-bindings/interconnect/qcom,sdx55.h b/include/dt-bindings/interconnect/qcom,sdx55.h index bfb6524a2d90..1925f0784ab2 100644 --- a/include/dt-bindings/interconnect/qcom,sdx55.h +++ b/include/dt-bindings/interconnect/qcom,sdx55.h @@ -70,7 +70,5 @@ #define SLAVE_QDSS_STM 48 #define SLAVE_TCU 49 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 #endif diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h index a25684680c42..ef292791f52e 100644 --- a/include/dt-bindings/interconnect/qcom,sm8150.h +++ b/include/dt-bindings/interconnect/qcom,sm8150.h @@ -121,9 +121,6 @@ #define SLAVE_LLCC 15 #define SLAVE_SERVICE_GEM_NOC 16 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h index 1b4d9fbe888d..a4af5cc19271 100644 --- a/include/dt-bindings/interconnect/qcom,sm8250.h +++ b/include/dt-bindings/interconnect/qcom,sm8250.h @@ -115,9 +115,6 @@ #define SLAVE_SERVICE_GEM_NOC_2 15 #define SLAVE_SERVICE_GEM_NOC 16 -#define MASTER_IPA_CORE 0 -#define SLAVE_IPA_CORE 1 - #define MASTER_LLCC 0 #define SLAVE_EBI_CH0 1 diff --git a/include/linux/console.h b/include/linux/console.h index 1e36958aa656..d3195664baa5 100644 --- a/include/linux/console.h +++ b/include/linux/console.h @@ -60,8 +60,9 @@ struct consw { int (*con_switch)(struct vc_data *vc); int (*con_blank)(struct vc_data *vc, int blank, int mode_switch); int (*con_font_set)(struct vc_data *vc, struct console_font *font, - unsigned int flags); - int (*con_font_get)(struct vc_data *vc, struct console_font *font); + unsigned int vpitch, unsigned int flags); + int (*con_font_get)(struct vc_data *vc, struct console_font *font, + unsigned int vpitch); int (*con_font_default)(struct vc_data *vc, struct console_font *font, char *name); int (*con_resize)(struct vc_data *vc, unsigned int width, diff --git a/include/linux/console_struct.h b/include/linux/console_struct.h index 1518568aaf0f..539f1cd45309 100644 --- a/include/linux/console_struct.h +++ b/include/linux/console_struct.h @@ -18,7 +18,6 @@ #include struct uni_pagedict; -struct uni_screen; #define NPAR 16 #define VC_TABSTOPS_COUNT 256U @@ -159,7 +158,7 @@ struct vc_data { struct vc_data **vc_display_fg; /* [!] Ptr to var holding fg console for this display */ struct uni_pagedict *uni_pagedict; struct uni_pagedict **uni_pagedict_loc; /* [!] Location of uni_pagedict variable for this console */ - struct uni_screen *vc_uni_screen; /* unicode screen content */ + u32 **vc_uni_lines; /* unicode screen content */ /* additional information is in vt_kern.h */ }; diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 6c2fd6cc5a98..51ac441a37c3 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -7,8 +7,19 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools that may not update at the same time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) /* * Below are the definition of bit offsets for perf option, and works as @@ -34,15 +45,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 #endif diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 1554021231f9..f19a47b9bb5a 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source { CORESIGHT_DEV_SUBTYPE_SOURCE_PROC, CORESIGHT_DEV_SUBTYPE_SOURCE_BUS, CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE, + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS, }; enum coresight_dev_subtype_helper { @@ -314,14 +315,11 @@ struct coresight_ops_link { * Operations available for sources. * @cpu_id: returns the value of the CPU number this component * is associated to. - * @trace_id: returns the value of the component's trace ID as known - * to the HW. * @enable: enables tracing for a source. * @disable: disables tracing for a source. */ struct coresight_ops_source { int (*cpu_id)(struct coresight_device *csdev); - int (*trace_id)(struct coresight_device *csdev); int (*enable)(struct coresight_device *csdev, struct perf_event *event, u32 mode); void (*disable)(struct coresight_device *csdev, diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 431636a0dc78..0a7a00a0ee7f 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -27,11 +27,15 @@ enum dfl_id_type { * @id: id of the dfl device. * @type: type of DFL FIU of the device. See enum dfl_id_type. * @feature_id: feature identifier local to its DFL FIU type. + * @revision: revision of this dfl device feature. * @mmio_res: mmio resource of this dfl device. * @irqs: list of Linux IRQ numbers of this dfl device. * @num_irqs: number of IRQs supported by this dfl device. * @cdev: pointer to DFL FPGA container device this dfl device belongs to. * @id_entry: matched id entry in dfl driver's id table. + * @dfh_version: version of DFH for the device + * @param_size: size of the block parameters in bytes + * @params: pointer to block of parameters copied memory */ struct dfl_device { struct device dev; @@ -44,6 +48,9 @@ struct dfl_device { unsigned int num_irqs; struct dfl_fpga_cdev *cdev; const struct dfl_device_id *id_entry; + u8 dfh_version; + unsigned int param_size; + void *params; }; /** @@ -84,4 +91,5 @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv); module_driver(__dfl_driver, dfl_driver_register, \ dfl_driver_unregister) +void *dfh_find_param(struct dfl_device *dfl_dev, int param_id, size_t *pcount); #endif /* __LINUX_DFL_H */ diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index a541f0c4f146..224645f17c33 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -507,6 +507,20 @@ static inline void eth_addr_inc(u8 *addr) u64_to_ether_addr(u, addr); } +/** + * eth_addr_add() - Add (or subtract) an offset to/from the given MAC address. + * + * @offset: Offset to add. + * @addr: Pointer to a six-byte array containing Ethernet address to increment. + */ +static inline void eth_addr_add(u8 *addr, long offset) +{ + u64 u = ether_addr_to_u64(addr); + + u += offset; + u64_to_ether_addr(u, addr); +} + /** * is_etherdev_addr - Tell if given Ethernet address belongs to the device. * @dev: Pointer to a device structure diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index a59fbffa238f..a7d54d4d41fd 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -271,6 +271,20 @@ struct hisi_qm_poll_data { u16 *qp_finish_id; }; +/** + * struct qm_err_isolate + * @isolate_lock: protects device error log + * @err_threshold: user config error threshold which triggers isolation + * @is_isolate: device isolation state + * @uacce_hw_errs: index into qm device error list + */ +struct qm_err_isolate { + struct mutex isolate_lock; + u32 err_threshold; + bool is_isolate; + struct list_head qm_hw_errs; +}; + struct hisi_qm { enum qm_hw_ver ver; enum qm_fun_type fun_type; @@ -340,6 +354,7 @@ struct hisi_qm { struct qm_shaper_factor *factor; u32 mb_qos; u32 type_rate; + struct qm_err_isolate isolate_data; }; struct hisi_qp_status { diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 8e0afaaa3f75..81413cd3a3e7 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -381,6 +381,11 @@ s64 iio_get_time_ns(const struct iio_dev *indio_dev); #define INDIO_MAX_RAW_ELEMENTS 4 +struct iio_val_int_plus_micro { + int integer; + int micro; +}; + struct iio_trigger; /* forward declaration */ /** diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 478aece17046..f198a8ac7ee7 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -70,8 +70,8 @@ struct mhi_ep_db_info { * @cmd_ctx_cache_phys: Physical address of the host command context cache * @chdb: Array of channel doorbell interrupt info * @event_lock: Lock for protecting event rings - * @list_lock: Lock for protecting state transition and channel doorbell lists * @state_lock: Lock for protecting state transitions + * @list_lock: Lock for protecting state transition and channel doorbell lists * @st_transition_list: List of state transitions * @ch_db_list: List of queued channel doorbells * @wq: Dedicated workqueue for handling rings and state changes @@ -117,8 +117,8 @@ struct mhi_ep_cntrl { struct mhi_ep_db_info chdb[4]; struct mutex event_lock; + struct mutex state_lock; spinlock_t list_lock; - spinlock_t state_lock; struct list_head st_transition_list; struct list_head ch_db_list; diff --git a/include/linux/nvmem-consumer.h b/include/linux/nvmem-consumer.h index 980f9c9ac0bc..1f62f7ba71ca 100644 --- a/include/linux/nvmem-consumer.h +++ b/include/linux/nvmem-consumer.h @@ -18,15 +18,7 @@ struct device_node; /* consumer cookie */ struct nvmem_cell; struct nvmem_device; - -struct nvmem_cell_info { - const char *name; - unsigned int offset; - unsigned int bytes; - unsigned int bit_offset; - unsigned int nbits; - struct device_node *np; -}; +struct nvmem_cell_info; /** * struct nvmem_cell_lookup - cell lookup entry diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index bb15c9234e21..0262b86194eb 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -14,14 +14,13 @@ #include struct nvmem_device; -struct nvmem_cell_info; typedef int (*nvmem_reg_read_t)(void *priv, unsigned int offset, void *val, size_t bytes); typedef int (*nvmem_reg_write_t)(void *priv, unsigned int offset, void *val, size_t bytes); /* used for vendor specific post processing of cell data */ -typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, unsigned int offset, - void *buf, size_t bytes); +typedef int (*nvmem_cell_post_process_t)(void *priv, const char *id, int index, + unsigned int offset, void *buf, size_t bytes); enum nvmem_type { NVMEM_TYPE_UNKNOWN = 0, @@ -47,6 +46,24 @@ struct nvmem_keepout { unsigned char value; }; +/** + * struct nvmem_cell_info - NVMEM cell description + * @name: Name. + * @offset: Offset within the NVMEM device. + * @bytes: Length of the cell. + * @bit_offset: Bit offset if cell is smaller than a byte. + * @nbits: Number of bits. + * @np: Optional device_node pointer. + */ +struct nvmem_cell_info { + const char *name; + unsigned int offset; + unsigned int bytes; + unsigned int bit_offset; + unsigned int nbits; + struct device_node *np; +}; + /** * struct nvmem_config - NVMEM device configuration * @@ -136,6 +153,9 @@ struct nvmem_device *devm_nvmem_register(struct device *dev, void nvmem_add_cell_table(struct nvmem_cell_table *table); void nvmem_del_cell_table(struct nvmem_cell_table *table); +int nvmem_add_one_cell(struct nvmem_device *nvmem, + const struct nvmem_cell_info *info); + #else static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c) @@ -153,6 +173,11 @@ devm_nvmem_register(struct device *dev, const struct nvmem_config *c) static inline void nvmem_add_cell_table(struct nvmem_cell_table *table) {} static inline void nvmem_del_cell_table(struct nvmem_cell_table *table) {} +static inline int nvmem_add_one_cell(struct nvmem_device *nvmem, + const struct nvmem_cell_info *info) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_NVMEM */ #endif /* ifndef _LINUX_NVMEM_PROVIDER_H */ diff --git a/include/linux/of.h b/include/linux/of.h index 8b9f94386dc3..98c252d2d851 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1008,6 +1008,31 @@ static inline int of_parse_phandle_with_fixed_args(const struct device_node *np, index, out_args); } +/** + * of_parse_phandle_with_optional_args() - Find a node pointed by phandle in a list + * @np: pointer to a device tree node containing a list + * @list_name: property name that contains a list + * @cells_name: property name that specifies phandles' arguments count + * @index: index of a phandle to parse out + * @out_args: optional pointer to output arguments structure (will be filled) + * + * Same as of_parse_phandle_with_args() except that if the cells_name property + * is not found, cell_count of 0 is assumed. + * + * This is used to useful, if you have a phandle which didn't have arguments + * before and thus doesn't have a '#*-cells' property but is now migrated to + * having arguments while retaining backwards compatibility. + */ +static inline int of_parse_phandle_with_optional_args(const struct device_node *np, + const char *list_name, + const char *cells_name, + int index, + struct of_phandle_args *out_args) +{ + return __of_parse_phandle_with_args(np, list_name, cells_name, + 0, index, out_args); +} + /** * of_property_count_u8_elems - Count the number of u8 elements in a property * diff --git a/include/linux/parport_pc.h b/include/linux/parport_pc.h index 3d6fc576d6a1..f1ec5c10c3b3 100644 --- a/include/linux/parport_pc.h +++ b/include/linux/parport_pc.h @@ -26,6 +26,9 @@ struct parport_pc_private { /* Whether or not there's an ECR. */ int ecr; + /* Bitmask of writable ECR bits. */ + unsigned char ecr_writable; + /* Number of PWords that FIFO will hold. */ int fifo_depth; diff --git a/include/linux/platform_data/tsl2563.h b/include/linux/platform_data/tsl2563.h deleted file mode 100644 index 9cf9309c3f24..000000000000 --- a/include/linux/platform_data/tsl2563.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __LINUX_TSL2563_H -#define __LINUX_TSL2563_H - -struct tsl2563_platform_data { - int cover_comp_gain; -}; - -#endif /* __LINUX_TSL2563_H */ diff --git a/include/linux/serial.h b/include/linux/serial.h index 3d6fe3ef92cf..bfda927dde15 100644 --- a/include/linux/serial.h +++ b/include/linux/serial.h @@ -12,6 +12,11 @@ #include #include +#define UART_IER_ALL_INTR (UART_IER_MSI | \ + UART_IER_RLSI | \ + UART_IER_THRI | \ + UART_IER_RDI) + /* Helper for dealing with UART_LCR_WLEN* defines */ #define UART_LCR_WLEN(x) ((x) - 5) @@ -23,6 +28,11 @@ static inline bool uart_lsr_tx_empty(u16 lsr) return (lsr & UART_LSR_BOTH_EMPTY) == UART_LSR_BOTH_EMPTY; } +#define UART_MSR_STATUS_BITS (UART_MSR_DCD | \ + UART_MSR_RI | \ + UART_MSR_DSR | \ + UART_MSR_CTS) + /* * Counters of the input lines (CTS, DSR, RI, CD) interrupts */ diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index fd59f600094a..9e3e5e0d11b2 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -579,6 +579,7 @@ struct uart_port { struct serial_rs485 rs485; struct serial_rs485 rs485_supported; /* Supported mask for serial_rs485 */ struct gpio_desc *rs485_term_gpio; /* enable RS485 bus termination */ + struct gpio_desc *rs485_rx_during_tx_gpio; /* Output GPIO that sets the state of RS485 RX during TX */ struct serial_iso7816 iso7816; void *private_data; /* generic platform data pointer */ }; @@ -781,7 +782,7 @@ static inline int uart_poll_timeout(struct uart_port *port) struct earlycon_device { struct console *con; struct uart_port port; - char options[16]; /* e.g., 115200n8 */ + char options[32]; /* e.g., 115200n8 */ unsigned int baud; }; @@ -896,10 +897,8 @@ static inline bool uart_softcts_mode(struct uart_port *uport) * The following are helper functions for the low level drivers. */ -extern void uart_handle_dcd_change(struct uart_port *uport, - unsigned int status); -extern void uart_handle_cts_change(struct uart_port *uport, - unsigned int status); +extern void uart_handle_dcd_change(struct uart_port *uport, bool active); +extern void uart_handle_cts_change(struct uart_port *uport, bool active); extern void uart_insert_char(struct uart_port *port, unsigned int status, unsigned int overrun, unsigned int ch, unsigned int flag); diff --git a/include/linux/qcom-geni-se.h b/include/linux/soc/qcom/geni-se.h similarity index 99% rename from include/linux/qcom-geni-se.h rename to include/linux/soc/qcom/geni-se.h index f5672785c0c4..400213daa461 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -103,6 +103,7 @@ struct geni_se { #define SE_DMA_TX_FSM_RST 0xc58 #define SE_DMA_RX_IRQ_STAT 0xd40 #define SE_DMA_RX_IRQ_CLR 0xd44 +#define SE_DMA_RX_LEN_IN 0xd54 #define SE_DMA_RX_FSM_RST 0xd58 #define SE_HW_PARAM_0 0xe24 #define SE_HW_PARAM_1 0xe28 @@ -235,6 +236,8 @@ struct geni_se { #define RX_SBE BIT(2) #define RX_RESET_DONE BIT(3) #define RX_FLUSH_DONE BIT(4) +#define RX_DMA_PARITY_ERR BIT(5) +#define RX_DMA_BREAK GENMASK(8, 7) #define RX_GENI_GP_IRQ GENMASK(10, 5) #define RX_GENI_CANCEL_IRQ BIT(11) #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) diff --git a/include/linux/tty.h b/include/linux/tty.h index 730c3301d710..093935e97f42 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -453,7 +453,7 @@ unsigned char tty_get_char_size(unsigned int cflag); unsigned char tty_get_frame_size(unsigned int cflag); void tty_termios_copy_hw(struct ktermios *new, const struct ktermios *old); -int tty_termios_hw_change(const struct ktermios *a, const struct ktermios *b); +bool tty_termios_hw_change(const struct ktermios *a, const struct ktermios *b); int tty_set_termios(struct tty_struct *tty, struct ktermios *kt); void tty_wakeup(struct tty_struct *tty); diff --git a/include/linux/tty_ldisc.h b/include/linux/tty_ldisc.h index dcb61ec11424..49dc172dedc7 100644 --- a/include/linux/tty_ldisc.h +++ b/include/linux/tty_ldisc.h @@ -170,7 +170,7 @@ int ldsem_down_write_nested(struct ld_semaphore *sem, int subclass, * send, please arise a tasklet or workqueue to do the real data transfer. * Do not send data in this hook, it may lead to a deadlock. * - * @dcd_change: [DRV] ``void ()(struct tty_struct *tty, unsigned int status)`` + * @dcd_change: [DRV] ``void ()(struct tty_struct *tty, bool active)`` * * Tells the discipline that the DCD pin has changed its status. Used * exclusively by the %N_PPS (Pulse-Per-Second) line discipline. @@ -238,7 +238,7 @@ struct tty_ldisc_ops { void (*receive_buf)(struct tty_struct *tty, const unsigned char *cp, const char *fp, int count); void (*write_wakeup)(struct tty_struct *tty); - void (*dcd_change)(struct tty_struct *tty, unsigned int status); + void (*dcd_change)(struct tty_struct *tty, bool active); int (*receive_buf2)(struct tty_struct *tty, const unsigned char *cp, const char *fp, int count); void (*lookahead_buf)(struct tty_struct *tty, const unsigned char *cp, diff --git a/include/linux/tty_port.h b/include/linux/tty_port.h index fa3c3bdaa234..edf685a24f7c 100644 --- a/include/linux/tty_port.h +++ b/include/linux/tty_port.h @@ -15,8 +15,8 @@ struct tty_struct; /** * struct tty_port_operations -- operations on tty_port - * @carrier_raised: return 1 if the carrier is raised on @port - * @dtr_rts: raise the DTR line if @raise is nonzero, otherwise lower DTR + * @carrier_raised: return true if the carrier is raised on @port + * @dtr_rts: raise the DTR line if @active is true, otherwise lower DTR * @shutdown: called when the last close completes or a hangup finishes IFF the * port was initialized. Do not use to free resources. Turn off the device * only. Called under the port mutex to serialize against @activate and @@ -31,8 +31,8 @@ struct tty_struct; * the port itself. */ struct tty_port_operations { - int (*carrier_raised)(struct tty_port *port); - void (*dtr_rts)(struct tty_port *port, int raise); + bool (*carrier_raised)(struct tty_port *port); + void (*dtr_rts)(struct tty_port *port, bool active); void (*shutdown)(struct tty_port *port); int (*activate)(struct tty_port *port, struct tty_struct *tty); void (*destruct)(struct tty_port *port); @@ -230,7 +230,7 @@ static inline void tty_port_set_kopened(struct tty_port *port, bool val) struct tty_struct *tty_port_tty_get(struct tty_port *port); void tty_port_tty_set(struct tty_port *port, struct tty_struct *tty); -int tty_port_carrier_raised(struct tty_port *port); +bool tty_port_carrier_raised(struct tty_port *port); void tty_port_raise_dtr_rts(struct tty_port *port); void tty_port_lower_dtr_rts(struct tty_port *port); void tty_port_hangup(struct tty_port *port); diff --git a/include/linux/uacce.h b/include/linux/uacce.h index 9ce88c28b0a8..0a81c3dfd26c 100644 --- a/include/linux/uacce.h +++ b/include/linux/uacce.h @@ -8,6 +8,7 @@ #define UACCE_NAME "uacce" #define UACCE_MAX_REGION 2 #define UACCE_MAX_NAME_SIZE 64 +#define UACCE_MAX_ERR_THRESHOLD 65535 struct uacce_queue; struct uacce_device; @@ -30,6 +31,9 @@ struct uacce_qfile_region { * @is_q_updated: check whether the task is finished * @mmap: mmap addresses of queue to user space * @ioctl: ioctl for user space users of the queue + * @get_isolate_state: get the device state after set the isolate strategy + * @isolate_err_threshold_write: stored the isolate error threshold to the device + * @isolate_err_threshold_read: read the isolate error threshold value from the device */ struct uacce_ops { int (*get_available_instances)(struct uacce_device *uacce); @@ -43,6 +47,9 @@ struct uacce_ops { struct uacce_qfile_region *qfr); long (*ioctl)(struct uacce_queue *q, unsigned int cmd, unsigned long arg); + enum uacce_dev_state (*get_isolate_state)(struct uacce_device *uacce); + int (*isolate_err_threshold_write)(struct uacce_device *uacce, u32 num); + u32 (*isolate_err_threshold_read)(struct uacce_device *uacce); }; /** @@ -57,6 +64,11 @@ struct uacce_interface { const struct uacce_ops *ops; }; +enum uacce_dev_state { + UACCE_DEV_NORMAL, + UACCE_DEV_ISOLATE, +}; + enum uacce_q_state { UACCE_Q_ZOMBIE = 0, UACCE_Q_INIT, diff --git a/include/linux/uuid.h b/include/linux/uuid.h index 8cdc0d3567cd..6b1a3efa1e0b 100644 --- a/include/linux/uuid.h +++ b/include/linux/uuid.h @@ -8,15 +8,25 @@ #ifndef _LINUX_UUID_H_ #define _LINUX_UUID_H_ -#include #include #define UUID_SIZE 16 +typedef struct { + __u8 b[UUID_SIZE]; +} guid_t; + typedef struct { __u8 b[UUID_SIZE]; } uuid_t; +#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ +((guid_t) \ +{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ + (b) & 0xff, ((b) >> 8) & 0xff, \ + (c) & 0xff, ((c) >> 8) & 0xff, \ + (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) + #define UUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ ((uuid_t) \ {{ ((a) >> 24) & 0xff, ((a) >> 16) & 0xff, ((a) >> 8) & 0xff, (a) & 0xff, \ @@ -97,10 +107,7 @@ extern const u8 uuid_index[16]; int guid_parse(const char *uuid, guid_t *u); int uuid_parse(const char *uuid, uuid_t *u); -/* backwards compatibility, don't use in new code */ -static inline int uuid_le_cmp(const guid_t u1, const guid_t u2) -{ - return memcmp(&u1, &u2, sizeof(guid_t)); -} +/* MEI UUID type, don't use anywhere else */ +#include #endif diff --git a/include/uapi/linux/android/binder.h b/include/uapi/linux/android/binder.h index 7fa36a8ad30d..f068f622d257 100644 --- a/include/uapi/linux/android/binder.h +++ b/include/uapi/linux/android/binder.h @@ -498,7 +498,7 @@ enum binder_driver_return_protocol { BR_FROZEN_REPLY = _IO('r', 18), /* - * The target of the last transaction (either a bcTRANSACTION or + * The target of the last sync transaction (either a bcTRANSACTION or * a bcATTEMPT_ACQUIRE) is frozen. No parameters. */ @@ -508,6 +508,11 @@ enum binder_driver_return_protocol { * asynchronous transaction makes the allocated async buffer size exceed * detection threshold. No parameters. */ + + BR_TRANSACTION_PENDING_FROZEN = _IO('r', 20), + /* + * The target of the last async transaction is frozen. No parameters. + */ }; enum binder_driver_command_protocol { diff --git a/include/uapi/linux/gsmmux.h b/include/uapi/linux/gsmmux.h index cb8693b39cb7..a703780aa095 100644 --- a/include/uapi/linux/gsmmux.h +++ b/include/uapi/linux/gsmmux.h @@ -19,8 +19,7 @@ struct gsm_config unsigned int mtu; unsigned int k; unsigned int i; - unsigned int unused[8]; /* Padding for expansion without - breaking stuff */ + unsigned int unused[8]; /* Can not be used */ }; #define GSMIOC_GETCONF _IOR('G', 0, struct gsm_config) @@ -29,9 +28,9 @@ struct gsm_config struct gsm_netconfig { unsigned int adaption; /* Adaption to use in network mode */ unsigned short protocol;/* Protocol to use - only ETH_P_IP supported */ - unsigned short unused2; + unsigned short unused2; /* Can not be used */ char if_name[IFNAMSIZ]; /* interface name format string */ - __u8 unused[28]; /* For future use */ + __u8 unused[28]; /* Can not be used */ }; #define GSMIOC_ENABLE_NET _IOW('G', 2, struct gsm_netconfig) @@ -40,4 +39,14 @@ struct gsm_netconfig { /* get the base tty number for a configured gsmmux tty */ #define GSMIOC_GETFIRST _IOR('G', 4, __u32) +struct gsm_config_ext { + __u32 keep_alive; /* Control channel keep-alive in 1/100th of a + * second (0 to disable) + */ + __u32 reserved[7]; /* For future use, must be initialized to zero */ +}; + +#define GSMIOC_GETCONF_EXT _IOR('G', 5, struct gsm_config_ext) +#define GSMIOC_SETCONF_EXT _IOW('G', 6, struct gsm_config_ext) + #endif diff --git a/include/uapi/linux/kd.h b/include/uapi/linux/kd.h index ee929ece4112..6b384065c013 100644 --- a/include/uapi/linux/kd.h +++ b/include/uapi/linux/kd.h @@ -161,19 +161,25 @@ struct console_font_op { unsigned int flags; /* KD_FONT_FLAG_* */ unsigned int width, height; /* font size */ unsigned int charcount; - unsigned char __user *data; /* font data with height fixed to 32 */ + unsigned char __user *data; /* font data with vpitch fixed to 32 for + * KD_FONT_OP_SET/GET + */ }; struct console_font { unsigned int width, height; /* font size */ unsigned int charcount; - unsigned char *data; /* font data with height fixed to 32 */ + unsigned char *data; /* font data with vpitch fixed to 32 for + * KD_FONT_OP_SET/GET + */ }; #define KD_FONT_OP_SET 0 /* Set font */ #define KD_FONT_OP_GET 1 /* Get font */ #define KD_FONT_OP_SET_DEFAULT 2 /* Set font to default, data points to name / NULL */ #define KD_FONT_OP_COPY 3 /* Obsolete, do not use */ +#define KD_FONT_OP_SET_TALL 4 /* Set font with vpitch = height */ +#define KD_FONT_OP_GET_TALL 5 /* Get font with vpitch = height */ #define KD_FONT_FLAG_DONT_RECALC 1 /* Don't recalculate hw charcell size [compat] */ diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 3ba34d8378bd..281fa286555c 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -207,6 +207,9 @@ /* Atheros AR933X SoC */ #define PORT_AR933X 99 +/* MCHP 16550A UART with 256 byte FIFOs */ +#define PORT_MCHP16550A 100 + /* ARC (Synopsys) on-chip UART */ #define PORT_ARC 101 diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index bab3b39266cc..08b3527e1b93 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -44,6 +44,11 @@ #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ #define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ +#define UART_IIR_64BYTE_FIFO 0x20 /* 16750 64 bytes FIFO */ +#define UART_IIR_FIFO_ENABLED 0xc0 /* FIFOs enabled / port type identification */ +#define UART_IIR_FIFO_ENABLED_8250 0x00 /* 8250: no FIFO */ +#define UART_IIR_FIFO_ENABLED_16550 0x80 /* 16550: (broken/unusable) FIFO */ +#define UART_IIR_FIFO_ENABLED_16550A 0xc0 /* 16550A: FIFO enabled */ #define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ diff --git a/include/uapi/linux/uuid.h b/include/uapi/linux/uuid.h index c0f4bd9b040e..96ac684a4b2f 100644 --- a/include/uapi/linux/uuid.h +++ b/include/uapi/linux/uuid.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* DO NOT USE in new code! This is solely for MEI due to legacy reasons */ /* - * UUID/GUID definition + * MEI UUID definition * * Copyright (C) 2010, Intel Corp. * Huang Ying @@ -14,19 +14,15 @@ typedef struct { __u8 b[16]; -} guid_t; +} uuid_le; -#define GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ -((guid_t) \ +#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ +((uuid_le) \ {{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \ (b) & 0xff, ((b) >> 8) & 0xff, \ (c) & 0xff, ((c) >> 8) & 0xff, \ (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) -/* backwards compatibility, don't use in new code */ -typedef guid_t uuid_le; -#define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ - GUID_INIT(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) #define NULL_UUID_LE \ UUID_LE(0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, \ 0x00, 0x00, 0x00, 0x00) diff --git a/kernel/events/core.c b/kernel/events/core.c index 76eb503d5f62..286403e48a25 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -9404,6 +9404,7 @@ void perf_report_aux_output_id(struct perf_event *event, u64 hw_id) perf_output_end(&handle); } +EXPORT_SYMBOL_GPL(perf_report_aux_output_id); static int __perf_event_account_interrupt(struct perf_event *event, int throttle) diff --git a/net/bluetooth/rfcomm/tty.c b/net/bluetooth/rfcomm/tty.c index 8009e0e93216..5697df9d4394 100644 --- a/net/bluetooth/rfcomm/tty.c +++ b/net/bluetooth/rfcomm/tty.c @@ -119,7 +119,7 @@ static int rfcomm_dev_activate(struct tty_port *port, struct tty_struct *tty) } /* we block the open until the dlc->state becomes BT_CONNECTED */ -static int rfcomm_dev_carrier_raised(struct tty_port *port) +static bool rfcomm_dev_carrier_raised(struct tty_port *port) { struct rfcomm_dev *dev = container_of(port, struct rfcomm_dev, port); diff --git a/scripts/tags.sh b/scripts/tags.sh index 84775f08260f..faf214bcf233 100755 --- a/scripts/tags.sh +++ b/scripts/tags.sh @@ -17,6 +17,13 @@ ignore="$(echo "$RCS_FIND_IGNORE" | sed 's|\\||g' )" # tags and cscope files should also ignore MODVERSION *.mod.c files ignore="$ignore ( -name *.mod.c ) -prune -o" +# ignore arbitrary directories +if [ -n "${IGNORE_DIRS}" ]; then + for i in ${IGNORE_DIRS}; do + ignore="${ignore} ( -path $i ) -prune -o" + done +fi + # Use make KBUILD_ABS_SRCTREE=1 {tags|cscope} # to force full paths for a non-O= build if [ "${srctree}" = "." -o -z "${srctree}" ]; then @@ -91,7 +98,7 @@ all_compiled_sources() { echo include/generated/autoconf.h find $ignore -name "*.cmd" -exec \ - grep -Poh '(?(?=^source_.* \K).*|(?=^ \K\S).*(?= \\))' {} \+ | + sed -n -E 's/^source_.* (.*)/\1/p; s/^ (\S.*) \\/\1/p' {} \+ | awk '!a[$0]++' } | xargs realpath -esq $([ -z "$KBUILD_ABS_SRCTREE" ] && echo --relative-to=.) | sort -u diff --git a/tools/iio/iio_utils.c b/tools/iio/iio_utils.c index 8d35893b2fa8..6a00a6eecaef 100644 --- a/tools/iio/iio_utils.c +++ b/tools/iio/iio_utils.c @@ -264,6 +264,7 @@ int iioutils_get_param_float(float *output, const char *param_name, if (fscanf(sysfsfp, "%f", output) != 1) ret = errno ? -errno : -ENODATA; + fclose(sysfsfp); break; } error_free_filename: @@ -345,9 +346,9 @@ int build_channel_array(const char *device_dir, int buffer_idx, } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - free(filename); goto error_close_dir; } @@ -357,7 +358,6 @@ int build_channel_array(const char *device_dir, int buffer_idx, if (fclose(sysfsfp)) perror("build_channel_array(): Failed to close file"); - free(filename); goto error_close_dir; } if (ret == 1) @@ -365,11 +365,9 @@ int build_channel_array(const char *device_dir, int buffer_idx, if (fclose(sysfsfp)) { ret = -errno; - free(filename); goto error_close_dir; } - free(filename); } *ci_array = malloc(sizeof(**ci_array) * (*counter)); @@ -395,9 +393,9 @@ int build_channel_array(const char *device_dir, int buffer_idx, } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - free(filename); count--; goto error_cleanup_array; } @@ -405,20 +403,17 @@ int build_channel_array(const char *device_dir, int buffer_idx, errno = 0; if (fscanf(sysfsfp, "%i", ¤t_enabled) != 1) { ret = errno ? -errno : -ENODATA; - free(filename); count--; goto error_cleanup_array; } if (fclose(sysfsfp)) { ret = -errno; - free(filename); count--; goto error_cleanup_array; } if (!current_enabled) { - free(filename); count--; continue; } @@ -429,7 +424,6 @@ int build_channel_array(const char *device_dir, int buffer_idx, strlen(ent->d_name) - strlen("_en")); if (!current->name) { - free(filename); ret = -ENOMEM; count--; goto error_cleanup_array; @@ -439,7 +433,6 @@ int build_channel_array(const char *device_dir, int buffer_idx, ret = iioutils_break_up_name(current->name, ¤t->generic_name); if (ret) { - free(filename); free(current->name); count--; goto error_cleanup_array; @@ -450,17 +443,16 @@ int build_channel_array(const char *device_dir, int buffer_idx, scan_el_dir, current->name); if (ret < 0) { - free(filename); ret = -ENOMEM; goto error_cleanup_array; } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - fprintf(stderr, "failed to open %s\n", - filename); - free(filename); + fprintf(stderr, "failed to open %s/%s_index\n", + scan_el_dir, current->name); goto error_cleanup_array; } @@ -470,17 +462,14 @@ int build_channel_array(const char *device_dir, int buffer_idx, if (fclose(sysfsfp)) perror("build_channel_array(): Failed to close file"); - free(filename); goto error_cleanup_array; } if (fclose(sysfsfp)) { ret = -errno; - free(filename); goto error_cleanup_array; } - free(filename); /* Find the scale */ ret = iioutils_get_param_float(¤t->scale, "scale",