iommufd: Extend IOMMU_GET_HW_INFO to report PASID capability
[ Upstream commit 803f97298e7de9242eb677a1351dcafbbcc9117e ] PASID usage requires PASID support in both device and IOMMU. Since the iommu drivers always enable the PASID capability for the device if it is supported, this extends the IOMMU_GET_HW_INFO to report the PASID capability to userspace. Also, enhances the selftest accordingly. Link: https://patch.msgid.link/r/20250321180143.8468-5-yi.l.liu@intel.com Cc: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Tested-by: Zhangfei Gao <zhangfei.gao@linaro.org> #aarch64 platform Tested-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
e506751b7d
commit
b4c11dd41c
@@ -3,6 +3,7 @@
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*/
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#include <linux/iommu.h>
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#include <linux/iommufd.h>
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#include <linux/pci-ats.h>
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#include <linux/slab.h>
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#include <uapi/linux/iommufd.h>
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@@ -1304,7 +1305,8 @@ int iommufd_get_hw_info(struct iommufd_ucmd *ucmd)
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void *data;
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int rc;
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if (cmd->flags || cmd->__reserved)
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if (cmd->flags || cmd->__reserved[0] || cmd->__reserved[1] ||
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cmd->__reserved[2])
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return -EOPNOTSUPP;
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idev = iommufd_get_device(ucmd, cmd->dev_id);
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@@ -1361,6 +1363,36 @@ int iommufd_get_hw_info(struct iommufd_ucmd *ucmd)
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if (device_iommu_capable(idev->dev, IOMMU_CAP_DIRTY_TRACKING))
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cmd->out_capabilities |= IOMMU_HW_CAP_DIRTY_TRACKING;
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cmd->out_max_pasid_log2 = 0;
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/*
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* Currently, all iommu drivers enable PASID in the probe_device()
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* op if iommu and device supports it. So the max_pasids stored in
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* dev->iommu indicates both PASID support and enable status. A
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* non-zero dev->iommu->max_pasids means PASID is supported and
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* enabled. The iommufd only reports PASID capability to userspace
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* if it's enabled.
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*/
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if (idev->dev->iommu->max_pasids) {
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cmd->out_max_pasid_log2 = ilog2(idev->dev->iommu->max_pasids);
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if (dev_is_pci(idev->dev)) {
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struct pci_dev *pdev = to_pci_dev(idev->dev);
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int ctrl;
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ctrl = pci_pasid_status(pdev);
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WARN_ON_ONCE(ctrl < 0 ||
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!(ctrl & PCI_PASID_CTRL_ENABLE));
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if (ctrl & PCI_PASID_CTRL_EXEC)
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cmd->out_capabilities |=
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IOMMU_HW_CAP_PCI_PASID_EXEC;
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if (ctrl & PCI_PASID_CTRL_PRIV)
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cmd->out_capabilities |=
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IOMMU_HW_CAP_PCI_PASID_PRIV;
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}
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}
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rc = iommufd_ucmd_respond(ucmd, sizeof(*cmd));
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out_free:
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kfree(data);
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@@ -538,4 +538,37 @@ int pci_max_pasids(struct pci_dev *pdev)
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return (1 << FIELD_GET(PCI_PASID_CAP_WIDTH, supported));
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}
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EXPORT_SYMBOL_GPL(pci_max_pasids);
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/**
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* pci_pasid_status - Check the PASID status
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* @pdev: PCI device structure
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*
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* Returns a negative value when no PASID capability is present.
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* Otherwise the value of the control register is returned.
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* Status reported are:
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*
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* PCI_PASID_CTRL_ENABLE - PASID enabled
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* PCI_PASID_CTRL_EXEC - Execute permission enabled
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* PCI_PASID_CTRL_PRIV - Privileged mode enabled
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*/
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int pci_pasid_status(struct pci_dev *pdev)
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{
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int pasid;
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u16 ctrl;
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if (pdev->is_virtfn)
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pdev = pci_physfn(pdev);
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pasid = pdev->pasid_cap;
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if (!pasid)
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return -EINVAL;
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pci_read_config_word(pdev, pasid + PCI_PASID_CTRL, &ctrl);
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ctrl &= PCI_PASID_CTRL_ENABLE | PCI_PASID_CTRL_EXEC |
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PCI_PASID_CTRL_PRIV;
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return ctrl;
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}
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EXPORT_SYMBOL_GPL(pci_pasid_status);
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#endif /* CONFIG_PCI_PASID */
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@@ -42,6 +42,7 @@ int pci_enable_pasid(struct pci_dev *pdev, int features);
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void pci_disable_pasid(struct pci_dev *pdev);
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int pci_pasid_features(struct pci_dev *pdev);
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int pci_max_pasids(struct pci_dev *pdev);
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int pci_pasid_status(struct pci_dev *pdev);
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#else /* CONFIG_PCI_PASID */
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static inline int pci_enable_pasid(struct pci_dev *pdev, int features)
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{ return -EINVAL; }
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@@ -50,6 +51,8 @@ static inline int pci_pasid_features(struct pci_dev *pdev)
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{ return -EINVAL; }
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static inline int pci_max_pasids(struct pci_dev *pdev)
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{ return -EINVAL; }
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static inline int pci_pasid_status(struct pci_dev *pdev)
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{ return -EINVAL; }
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#endif /* CONFIG_PCI_PASID */
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#endif /* LINUX_PCI_ATS_H */
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@@ -504,9 +504,17 @@ enum iommu_hw_info_type {
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* IOMMU_HWPT_GET_DIRTY_BITMAP
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* IOMMU_HWPT_SET_DIRTY_TRACKING
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*
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* @IOMMU_HW_CAP_PCI_PASID_EXEC: Execute Permission Supported, user ignores it
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* when the struct
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* iommu_hw_info::out_max_pasid_log2 is zero.
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* @IOMMU_HW_CAP_PCI_PASID_PRIV: Privileged Mode Supported, user ignores it
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* when the struct
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* iommu_hw_info::out_max_pasid_log2 is zero.
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*/
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enum iommufd_hw_capabilities {
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IOMMU_HW_CAP_DIRTY_TRACKING = 1 << 0,
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IOMMU_HW_CAP_PCI_PASID_EXEC = 1 << 1,
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IOMMU_HW_CAP_PCI_PASID_PRIV = 1 << 2,
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};
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/**
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@@ -522,6 +530,9 @@ enum iommufd_hw_capabilities {
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* iommu_hw_info_type.
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* @out_capabilities: Output the generic iommu capability info type as defined
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* in the enum iommu_hw_capabilities.
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* @out_max_pasid_log2: Output the width of PASIDs. 0 means no PASID support.
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* PCI devices turn to out_capabilities to check if the
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* specific capabilities is supported or not.
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* @__reserved: Must be 0
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*
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* Query an iommu type specific hardware information data from an iommu behind
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@@ -545,7 +556,8 @@ struct iommu_hw_info {
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__u32 data_len;
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__aligned_u64 data_uptr;
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__u32 out_data_type;
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__u32 __reserved;
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__u8 out_max_pasid_log2;
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__u8 __reserved[3];
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__aligned_u64 out_capabilities;
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};
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#define IOMMU_GET_HW_INFO _IO(IOMMUFD_TYPE, IOMMUFD_CMD_GET_HW_INFO)
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