Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (27 commits) sh: Fix up L2 cache probe. sh: Fix up SH-4A part probe. sh: Add support for SH7723 CPU subtype. sh: Fix up SH7763 build. sh: Add migor_ts support to MigoR sh: Add rs5c732b RTC support to MigoR sh: Add I2C support to MigoR sh: Add I2C platform data to sh7722 sh: MigoR NAND flash support using gen_flash sh: MigoR NOR flash support using physmap-flash sh: Fix up mach-types formatting from merge damage. sh: r7780rp: Hook up the I2C and SMBus platform devices. sh: Use phyical addresses for MigoR smc91x resources sh: Use physical addresses for sh7722 USBF resources sh: Add MigoR header file Fix sh_keysc double free sh: Fix up __access_ok() check for nommu. sh: Allow optimized clear/copy page routines to be used on SH-2. sh: Hook up the rest of the SH7770 serial ports. sh: Add support for Solution Engine SH7721 board ...
This commit is contained in:
Linus Torvalds
@@ -25,7 +25,7 @@ static void __init check_bugs(void)
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case CPU_SH7619:
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*p++ = '2';
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break;
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case CPU_SH7203 ... CPU_SH7263:
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case CPU_SH7203 ... CPU_MXG:
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*p++ = '2';
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*p++ = 'a';
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break;
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@@ -10,14 +10,14 @@
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#ifndef __ASM_CPU_SH4_FREQ_H
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#define __ASM_CPU_SH4_FREQ_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
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#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
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defined(CONFIG_CPU_SUBTYPE_SH7723) || \
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defined(CONFIG_CPU_SUBTYPE_SH7366)
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#define FRQCR 0xa4150000
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#define VCLKCR 0xa4150004
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#define SCLKACR 0xa4150008
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#define SCLKBCR 0xa415000c
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#if defined(CONFIG_CPU_SUBTYPE_SH7722)
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#define IrDACLKCR 0xa4150010
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#endif
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780)
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#define FRQCR 0xffc80000
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@@ -1,7 +1,12 @@
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#ifndef __ASM_SH_CPU_SH4_RTC_H
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#define __ASM_SH_CPU_SH4_RTC_H
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#ifdef CONFIG_CPU_SUBTYPE_SH7723
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#define rtc_reg_size sizeof(u16)
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#else
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#define rtc_reg_size sizeof(u32)
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#endif
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#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
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#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
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@@ -0,0 +1,58 @@
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#ifndef __ASM_SH_MIGOR_H
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#define __ASM_SH_MIGOR_H
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/*
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* linux/include/asm-sh/migor.h
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*
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* Copyright (C) 2008 Renesas Solutions
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*
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* Portions Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <asm/addrspace.h>
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/* GPIO */
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#define MSTPCR0 0xa4150030
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#define MSTPCR1 0xa4150034
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#define MSTPCR2 0xa4150038
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#define PORT_PACR 0xa4050100
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#define PORT_PDCR 0xa4050106
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#define PORT_PECR 0xa4050108
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#define PORT_PHCR 0xa405010e
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#define PORT_PJCR 0xa4050110
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#define PORT_PKCR 0xa4050112
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#define PORT_PLCR 0xa4050114
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#define PORT_PMCR 0xa4050116
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#define PORT_PRCR 0xa405011c
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#define PORT_PWCR 0xa4050146
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#define PORT_PXCR 0xa4050148
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#define PORT_PYCR 0xa405014a
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#define PORT_PZCR 0xa405014c
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#define PORT_PADR 0xa4050120
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#define PORT_PWDR 0xa4050166
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#define PORT_HIZCRA 0xa4050158
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#define PORT_HIZCRC 0xa405015c
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#define PORT_MSELCRB 0xa4050182
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#define MSTPCR1 0xa4150034
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#define MSTPCR2 0xa4150038
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#define PORT_PSELA 0xa405014e
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#define PORT_PSELB 0xa4050150
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#define PORT_PSELC 0xa4050152
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#define PORT_PSELD 0xa4050154
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#define PORT_HIZCRA 0xa4050158
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#define PORT_HIZCRB 0xa405015a
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#define PORT_HIZCRC 0xa405015c
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#define BSC_CS6ABCR 0xfec1001c
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#endif /* __ASM_SH_MIGOR_H */
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@@ -16,7 +16,7 @@ enum cpu_type {
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CPU_SH7619,
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/* SH-2A types */
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CPU_SH7203, CPU_SH7206, CPU_SH7263,
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CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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@@ -29,7 +29,8 @@ enum cpu_type {
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CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
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/* SH-4A types */
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CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
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CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
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CPU_SH7723, CPU_SHX3,
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/* SH4AL-DSP types */
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CPU_SH7343, CPU_SH7722, CPU_SH7366,
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+12
-10
@@ -55,11 +55,11 @@
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#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
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#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
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#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
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#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
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#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
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#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
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#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
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#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
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#define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */
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#define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */
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#define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */
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#define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
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#define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
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#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
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#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
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#define PA_PMR (PA_BCR+0x0900) /* */
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@@ -107,11 +107,11 @@
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#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
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#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
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#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
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#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
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#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
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#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
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#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
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#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
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#define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */
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#define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */
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#define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */
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#define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */
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#define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
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#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
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#define PA_AX88796L 0xa5800400 /* AX88796L Area */
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@@ -190,6 +190,8 @@
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#define IRQ_TP (HL_FPGA_IRQ_BASE + 12)
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#define IRQ_RTC (HL_FPGA_IRQ_BASE + 13)
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#define IRQ_TH_ALERT (HL_FPGA_IRQ_BASE + 14)
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#define IRQ_SCIF0 (HL_FPGA_IRQ_BASE + 15)
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#define IRQ_SCIF1 (HL_FPGA_IRQ_BASE + 16)
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unsigned char *highlander_init_irq_r7780mp(void);
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unsigned char *highlander_init_irq_r7780rp(void);
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@@ -0,0 +1,70 @@
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/*
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* Hitachi UL SolutionEngine 7721 Support.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#ifndef __ASM_SH_SE7721_H
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#define __ASM_SH_SE7721_H
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#include <asm/addrspace.h>
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/* Box specific addresses. */
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#define SE_AREA0_WIDTH 2 /* Area0: 32bit */
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#define PA_ROM 0xa0000000 /* EPROM */
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#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */
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#define PA_FROM 0xa1000000 /* Flash-ROM */
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#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
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#define PA_EXT1 0xa4000000
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#define PA_EXT1_SIZE 0x04000000
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#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */
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#define PA_SDRAM_SIZE 0x04000000
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#define PA_EXT4 0xb0000000
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#define PA_EXT4_SIZE 0x04000000
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#define PA_PERIPHERAL 0xB8000000
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#define PA_PCIC PA_PERIPHERAL
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#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0)
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#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000)
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#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000)
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#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000)
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define PA_LED 0xB6800000 /* 8bit LED */
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#define PA_FPGA 0xB7000000 /* FPGA base address */
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#define MRSHPC_IRQ0 10
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#define FPGA_ILSR1 (PA_FPGA + 0x02)
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#define FPGA_ILSR2 (PA_FPGA + 0x03)
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#define FPGA_ILSR3 (PA_FPGA + 0x04)
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#define FPGA_ILSR4 (PA_FPGA + 0x05)
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#define FPGA_ILSR5 (PA_FPGA + 0x06)
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#define FPGA_ILSR6 (PA_FPGA + 0x07)
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#define FPGA_ILSR7 (PA_FPGA + 0x08)
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#define FPGA_ILSR8 (PA_FPGA + 0x09)
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void init_se7721_IRQ(void);
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#define __IO_PREFIX se7721
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_SE7721_H */
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@@ -77,6 +77,8 @@
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#define PORT_PSELA 0xA405014EUL
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#define PORT_PYCR 0xA405014AUL
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#define PORT_PZCR 0xA405014CUL
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#define PORT_HIZCRA 0xA4050158UL
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#define PORT_HIZCRC 0xA405015CUL
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/* IRQ */
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#define IRQ0_IRQ 32
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@@ -0,0 +1,13 @@
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#ifndef __ASM_KEYSC_H__
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#define __ASM_KEYSC_H__
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#define SH_KEYSC_MAXKEYS 30
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struct sh_keysc_info {
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enum { SH_KEYSC_MODE_1, SH_KEYSC_MODE_2, SH_KEYSC_MODE_3 } mode;
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int scan_timing; /* 0 -> 7, see KYCR1, SCN[2:0] */
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int delay;
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int keycodes[SH_KEYSC_MAXKEYS];
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};
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#endif /* __ASM_KEYSC_H__ */
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@@ -146,6 +146,8 @@ extern unsigned int instruction_size(unsigned int insn);
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extern unsigned long cached_to_uncached;
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extern struct dentry *sh_debugfs_root;
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/* XXX
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* disable hlt during certain critical i/o operations
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*/
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@@ -55,13 +55,10 @@ static inline void set_fs(mm_segment_t s)
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* If we don't have an MMU (or if its disabled) the only thing we really have
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* to look out for is if the address resides somewhere outside of what
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* available RAM we have.
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*
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* TODO: This check could probably also stand to be restricted somewhat more..
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* though it still does the Right Thing(tm) for the time being.
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*/
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static inline int __access_ok(unsigned long addr, unsigned long size)
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{
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return ((addr >= memory_start) && ((addr + size) < memory_end));
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return 1;
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}
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#else /* CONFIG_MMU */
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#define __addr_ok(addr) \
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