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net/mlx4_core: Dynamic VST to VST vlan/qos changes

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Within VST mode, enable modifying the vlan and/or qos
for a VF without requiring unbind/rebind.

This requires firmware which supports the UPDATE_QP command.
(If the command is not available, we fall back to requiring
unbind/bind to activate these changes).

To avoid race conditions with modify-qp on QPs that are affected
by update-qp, this operation is performed on the comm_wq.

If the update operation succeeds for all the necessary QPs, a
vlan_unregister is performed for the abandoned vlan id.

Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jack Morgenstein
2013-06-27 19:05:21 +03:00
committed by David S. Miller
parent 4e144d3a80
commit b01978cacf
7 changed files with 319 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/linux/mlx4/cmd.h
+1
View File
@@ -111,6 +111,7 @@ enum {
MLX4_CMD_INIT2INIT_QP = 0x2d,
MLX4_CMD_SUSPEND_QP = 0x32,
MLX4_CMD_UNSUSPEND_QP = 0x33,
MLX4_CMD_UPDATE_QP = 0x61,
/* special QP and management commands */
MLX4_CMD_CONF_SPECIAL_QP = 0x23,
MLX4_CMD_MAD_IFC = 0x24,
include/linux/mlx4/device.h
+2 -1
View File
@@ -157,7 +157,8 @@ enum {
MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7
MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8
};
enum {
include/linux/mlx4/qp.h
+34
View File
@@ -206,6 +206,40 @@ struct mlx4_qp_context {
u32 reserved5[10];
};
struct mlx4_update_qp_context {
__be64 qp_mask;
__be64 primary_addr_path_mask;
__be64 secondary_addr_path_mask;
u64 reserved1;
struct mlx4_qp_context qp_context;
u64 reserved2[58];
};
enum {
MLX4_UPD_QP_MASK_PM_STATE = 32,
MLX4_UPD_QP_MASK_VSD = 33,
};
enum {
MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
};
enum { /* param3 */
MLX4_STRIP_VLAN = 1 << 30
};