From d2805601988fb0b41247c95dcb4b8b8455921978 Mon Sep 17 00:00:00 2001 From: Mark Tseng Date: Fri, 18 Aug 2023 10:17:41 +0800 Subject: [PATCH 01/26] PM / devfreq: mediatek: protect oop in critical session mtk_ccifreq_opp_notifier is reenter function when policy0 / policy6 change freq, so mutex_lock should protect all OPP event. Link: https://lore.kernel.org/lkml/20230818021741.6173-1-chun-jen.tseng@mediatek.com/T/ Signed-off-by: Mark Tseng Signed-off-by: Chanwoo Choi --- drivers/devfreq/mtk-cci-devfreq.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c index 83a73f0ccd80..b0ed25e33f2b 100644 --- a/drivers/devfreq/mtk-cci-devfreq.c +++ b/drivers/devfreq/mtk-cci-devfreq.c @@ -137,6 +137,8 @@ static int mtk_ccifreq_target(struct device *dev, unsigned long *freq, if (drv->pre_freq == *freq) return 0; + mutex_lock(&drv->reg_lock); + inter_voltage = drv->inter_voltage; cci_pll = clk_get_parent(drv->cci_clk); @@ -147,8 +149,6 @@ static int mtk_ccifreq_target(struct device *dev, unsigned long *freq, return PTR_ERR(opp); } - mutex_lock(&drv->reg_lock); - voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -227,9 +227,9 @@ static int mtk_ccifreq_opp_notifier(struct notifier_block *nb, drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb); if (event == OPP_EVENT_ADJUST_VOLTAGE) { + mutex_lock(&drv->reg_lock); freq = dev_pm_opp_get_freq(opp); - mutex_lock(&drv->reg_lock); /* current opp item is changed */ if (freq == drv->pre_freq) { volt = dev_pm_opp_get_voltage(opp); From 8b3bd6ffbc6475a7dc92c6d6021d49b555301c01 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 3 Oct 2023 16:42:28 +0530 Subject: [PATCH 02/26] PM / devfreq: Switch to dev_pm_opp_find_freq_{ceil/floor}_indexed() APIs Some devfreq consumers like UFS driver need to work with multiple clocks through the OPP framework. For this reason, OPP framework exposes the _indexed() APIs for finding the floor/ceil of the supplied frequency of the indexed clock. So let's use them in the devfreq driver. Currently, the clock index of 0 is used which works fine for multiple as well as single clock. Link: https://lore.kernel.org/all/20231003111232.42663-3-manivannan.sadhasivam@linaro.org/ Acked-by: Chanwoo Choi Signed-off-by: Manivannan Sadhasivam Signed-off-by: Chanwoo Choi --- drivers/devfreq/devfreq.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 474d81831ad3..b3a68d5833bd 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -88,7 +88,7 @@ static unsigned long find_available_min_freq(struct devfreq *devfreq) struct dev_pm_opp *opp; unsigned long min_freq = 0; - opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &min_freq); + opp = dev_pm_opp_find_freq_ceil_indexed(devfreq->dev.parent, &min_freq, 0); if (IS_ERR(opp)) min_freq = 0; else @@ -102,7 +102,7 @@ static unsigned long find_available_max_freq(struct devfreq *devfreq) struct dev_pm_opp *opp; unsigned long max_freq = ULONG_MAX; - opp = dev_pm_opp_find_freq_floor(devfreq->dev.parent, &max_freq); + opp = dev_pm_opp_find_freq_floor_indexed(devfreq->dev.parent, &max_freq, 0); if (IS_ERR(opp)) max_freq = 0; else @@ -196,7 +196,7 @@ static int set_freq_table(struct devfreq *devfreq) return -ENOMEM; for (i = 0, freq = 0; i < devfreq->max_state; i++, freq++) { - opp = dev_pm_opp_find_freq_ceil(devfreq->dev.parent, &freq); + opp = dev_pm_opp_find_freq_ceil_indexed(devfreq->dev.parent, &freq, 0); if (IS_ERR(opp)) { devm_kfree(devfreq->dev.parent, devfreq->freq_table); return PTR_ERR(opp); @@ -2036,18 +2036,18 @@ struct dev_pm_opp *devfreq_recommended_opp(struct device *dev, if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND) { /* The freq is an upper bound. opp should be lower */ - opp = dev_pm_opp_find_freq_floor(dev, freq); + opp = dev_pm_opp_find_freq_floor_indexed(dev, freq, 0); /* If not available, use the closest opp */ if (opp == ERR_PTR(-ERANGE)) - opp = dev_pm_opp_find_freq_ceil(dev, freq); + opp = dev_pm_opp_find_freq_ceil_indexed(dev, freq, 0); } else { /* The freq is an lower bound. opp should be higher */ - opp = dev_pm_opp_find_freq_ceil(dev, freq); + opp = dev_pm_opp_find_freq_ceil_indexed(dev, freq, 0); /* If not available, use the closest opp */ if (opp == ERR_PTR(-ERANGE)) - opp = dev_pm_opp_find_freq_floor(dev, freq); + opp = dev_pm_opp_find_freq_floor_indexed(dev, freq, 0); } return opp; From 1e0731c05c985deb68a97fa44c1adcd3305dda90 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 4 Jul 2023 11:32:17 +0200 Subject: [PATCH 03/26] PM / devfreq: rockchip-dfi: Make pmu regmap mandatory As a matter of fact the regmap_pmu already is mandatory because it is used unconditionally in the driver. Bail out gracefully in probe() rather than crashing later. Link: https://lore.kernel.org/lkml/20230704093242.583575-2-s.hauer@pengutronix.de/ Fixes: b9d1262bca0af ("PM / devfreq: event: support rockchip dfi controller") Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 39ac069cabc7..74893c06aa08 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -193,14 +193,15 @@ static int rockchip_dfi_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(data->clk), "Cannot get the clk pclk_ddr_mon\n"); - /* try to find the optional reference to the pmu syscon */ node = of_parse_phandle(np, "rockchip,pmu", 0); - if (node) { - data->regmap_pmu = syscon_node_to_regmap(node); - of_node_put(node); - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); - } + if (!node) + return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n"); + + data->regmap_pmu = syscon_node_to_regmap(node); + of_node_put(node); + if (IS_ERR(data->regmap_pmu)) + return PTR_ERR(data->regmap_pmu); + data->dev = dev; desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); From bbf479005436d5e33eea25e077bb724358fe8848 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 4 Jul 2023 11:32:18 +0200 Subject: [PATCH 04/26] PM / devfreq: rockchip-dfi: Embed desc into private data struct No need for an extra allocation, just embed the struct devfreq_event_desc into the private data struct. Link: https://lore.kernel.org/lkml/20230704093242.583575-3-s.hauer@pengutronix.de/ Reviewed-by: Heiko Stuebner Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 74893c06aa08..467f9f42d38f 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -49,7 +49,7 @@ struct dmc_usage { */ struct rockchip_dfi { struct devfreq_event_dev *edev; - struct devfreq_event_desc *desc; + struct devfreq_event_desc desc; struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; struct device *dev; void __iomem *regs; @@ -204,14 +204,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev) data->dev = dev; - desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); - if (!desc) - return -ENOMEM; - + desc = &data->desc; desc->ops = &rockchip_dfi_ops; desc->driver_data = data; desc->name = np->name; - data->desc = desc; data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); if (IS_ERR(data->edev)) { From 9325b3ec923ee42799879cb4d4c5aaffa49e7829 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 4 Jul 2023 11:32:19 +0200 Subject: [PATCH 05/26] PM / devfreq: rockchip-dfi: use consistent name for private data struct The variable name for the private data struct is 'info' in some functions and 'data' in others. Both names do not give a clue what type the variable has, so consistently use 'dfi'. Link: https://lore.kernel.org/lkml/20230704093242.583575-4-s.hauer@pengutronix.de/ Reviewed-by: Heiko Stuebner Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++-------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 467f9f42d38f..e19e5acaa362 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -59,13 +59,13 @@ struct rockchip_dfi { static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - void __iomem *dfi_regs = info->regs; + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); + void __iomem *dfi_regs = dfi->regs; u32 val; u32 ddr_type; /* get ddr type */ - regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); + regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & RK3399_PMUGRF_DDRTYPE_MASK; @@ -84,28 +84,28 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); - void __iomem *dfi_regs = info->regs; + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); + void __iomem *dfi_regs = dfi->regs; writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL); } static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); u32 tmp, max = 0; u32 i, busier_ch = 0; - void __iomem *dfi_regs = info->regs; + void __iomem *dfi_regs = dfi->regs; rockchip_dfi_stop_hardware_counter(edev); /* Find out which channel is busier */ for (i = 0; i < RK3399_DMC_NUM_CH; i++) { - info->ch_usage[i].access = readl_relaxed(dfi_regs + + dfi->ch_usage[i].access = readl_relaxed(dfi_regs + DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4; - info->ch_usage[i].total = readl_relaxed(dfi_regs + + dfi->ch_usage[i].total = readl_relaxed(dfi_regs + DDRMON_CH0_COUNT_NUM + i * 20); - tmp = info->ch_usage[i].access; + tmp = dfi->ch_usage[i].access; if (tmp > max) { busier_ch = i; max = tmp; @@ -118,20 +118,20 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) static int rockchip_dfi_disable(struct devfreq_event_dev *edev) { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); rockchip_dfi_stop_hardware_counter(edev); - clk_disable_unprepare(info->clk); + clk_disable_unprepare(dfi->clk); return 0; } static int rockchip_dfi_enable(struct devfreq_event_dev *edev) { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); int ret; - ret = clk_prepare_enable(info->clk); + ret = clk_prepare_enable(dfi->clk); if (ret) { dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret); return ret; @@ -149,13 +149,13 @@ static int rockchip_dfi_set_event(struct devfreq_event_dev *edev) static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, struct devfreq_event_data *edata) { - struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); + struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); int busier_ch; busier_ch = rockchip_dfi_get_busier_ch(edev); - edata->load_count = info->ch_usage[busier_ch].access; - edata->total_count = info->ch_usage[busier_ch].total; + edata->load_count = dfi->ch_usage[busier_ch].access; + edata->total_count = dfi->ch_usage[busier_ch].total; return 0; } @@ -176,47 +176,47 @@ MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match); static int rockchip_dfi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct rockchip_dfi *data; + struct rockchip_dfi *dfi; struct devfreq_event_desc *desc; struct device_node *np = pdev->dev.of_node, *node; - data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); - if (!data) + dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL); + if (!dfi) return -ENOMEM; - data->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(data->regs)) - return PTR_ERR(data->regs); + dfi->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dfi->regs)) + return PTR_ERR(dfi->regs); - data->clk = devm_clk_get(dev, "pclk_ddr_mon"); - if (IS_ERR(data->clk)) - return dev_err_probe(dev, PTR_ERR(data->clk), + dfi->clk = devm_clk_get(dev, "pclk_ddr_mon"); + if (IS_ERR(dfi->clk)) + return dev_err_probe(dev, PTR_ERR(dfi->clk), "Cannot get the clk pclk_ddr_mon\n"); node = of_parse_phandle(np, "rockchip,pmu", 0); if (!node) return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n"); - data->regmap_pmu = syscon_node_to_regmap(node); + dfi->regmap_pmu = syscon_node_to_regmap(node); of_node_put(node); - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); + if (IS_ERR(dfi->regmap_pmu)) + return PTR_ERR(dfi->regmap_pmu); - data->dev = dev; + dfi->dev = dev; - desc = &data->desc; + desc = &dfi->desc; desc->ops = &rockchip_dfi_ops; - desc->driver_data = data; + desc->driver_data = dfi; desc->name = np->name; - data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); - if (IS_ERR(data->edev)) { + dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); + if (IS_ERR(dfi->edev)) { dev_err(&pdev->dev, "failed to add devfreq-event device\n"); - return PTR_ERR(data->edev); + return PTR_ERR(dfi->edev); } - platform_set_drvdata(pdev, data); + platform_set_drvdata(pdev, dfi); return 0; } From 559dc2876c0c46850dfed5c2a810d17b259e4bd9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 4 Jul 2023 11:32:20 +0200 Subject: [PATCH 06/26] PM / devfreq: rockchip-dfi: Add SoC specific init function Move the RK3399 specifics to a SoC specific init function to make the way free for supporting other SoCs later. Link: https://lore.kernel.org/lkml/20230704093242.583575-5-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 48 +++++++++++++++++++--------- 1 file changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index e19e5acaa362..6b1ef29df704 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -55,27 +56,21 @@ struct rockchip_dfi { void __iomem *regs; struct regmap *regmap_pmu; struct clk *clk; + u32 ddr_type; }; static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) { struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); void __iomem *dfi_regs = dfi->regs; - u32 val; - u32 ddr_type; - - /* get ddr type */ - regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & - RK3399_PMUGRF_DDRTYPE_MASK; /* clear DDRMON_CTRL setting */ writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); /* set ddr type to dfi */ - if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) + if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); - else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) + else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); /* enable count, use software mode */ @@ -167,8 +162,26 @@ static const struct devfreq_event_ops rockchip_dfi_ops = { .set_event = rockchip_dfi_set_event, }; +static int rk3399_dfi_init(struct rockchip_dfi *dfi) +{ + struct regmap *regmap_pmu = dfi->regmap_pmu; + u32 val; + + dfi->clk = devm_clk_get(dfi->dev, "pclk_ddr_mon"); + if (IS_ERR(dfi->clk)) + return dev_err_probe(dfi->dev, PTR_ERR(dfi->clk), + "Cannot get the clk pclk_ddr_mon\n"); + + /* get ddr type */ + regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); + dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & + RK3399_PMUGRF_DDRTYPE_MASK; + + return 0; +}; + static const struct of_device_id rockchip_dfi_id_match[] = { - { .compatible = "rockchip,rk3399-dfi" }, + { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init }, { }, }; MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match); @@ -179,6 +192,12 @@ static int rockchip_dfi_probe(struct platform_device *pdev) struct rockchip_dfi *dfi; struct devfreq_event_desc *desc; struct device_node *np = pdev->dev.of_node, *node; + int (*soc_init)(struct rockchip_dfi *dfi); + int ret; + + soc_init = of_device_get_match_data(&pdev->dev); + if (!soc_init) + return -EINVAL; dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL); if (!dfi) @@ -188,11 +207,6 @@ static int rockchip_dfi_probe(struct platform_device *pdev) if (IS_ERR(dfi->regs)) return PTR_ERR(dfi->regs); - dfi->clk = devm_clk_get(dev, "pclk_ddr_mon"); - if (IS_ERR(dfi->clk)) - return dev_err_probe(dev, PTR_ERR(dfi->clk), - "Cannot get the clk pclk_ddr_mon\n"); - node = of_parse_phandle(np, "rockchip,pmu", 0); if (!node) return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n"); @@ -209,6 +223,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev) desc->driver_data = dfi; desc->name = np->name; + ret = soc_init(dfi); + if (ret) + return ret; + dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); if (IS_ERR(dfi->edev)) { dev_err(&pdev->dev, From 419827409834f4e6602456ae23d4557d541adcbf Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 4 Jul 2023 11:32:21 +0200 Subject: [PATCH 07/26] PM / devfreq: rockchip-dfi: dfi store raw values in counter struct When adding perf support to the DFI driver the perf part will need the raw counter values, so move the fixed * 4 factor to rockchip_dfi_get_event(). Link: https://lore.kernel.org/lkml/20230704093242.583575-6-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 6b1ef29df704..680f629da64f 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -97,7 +97,7 @@ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) /* Find out which channel is busier */ for (i = 0; i < RK3399_DMC_NUM_CH; i++) { dfi->ch_usage[i].access = readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4; + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); dfi->ch_usage[i].total = readl_relaxed(dfi_regs + DDRMON_CH0_COUNT_NUM + i * 20); tmp = dfi->ch_usage[i].access; @@ -149,7 +149,7 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, busier_ch = rockchip_dfi_get_busier_ch(edev); - edata->load_count = dfi->ch_usage[busier_ch].access; + edata->load_count = dfi->ch_usage[busier_ch].access * 4; edata->total_count = dfi->ch_usage[busier_ch].total; return 0; From e50fa1a5ac52e2a2ec09b8028bdb1c4bf9166cbc Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 6 Oct 2023 16:38:54 -0500 Subject: [PATCH 08/26] PM / devfreq: exynos-ppmu: Use device_get_match_data() Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Link: https://lore.kernel.org/all/20231006213854.333261-1-robh@kernel.org/ Signed-off-by: Rob Herring Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/exynos-ppmu.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c index 896a6cc93b00..56bac4702006 100644 --- a/drivers/devfreq/event/exynos-ppmu.c +++ b/drivers/devfreq/event/exynos-ppmu.c @@ -12,9 +12,9 @@ #include #include #include -#include -#include +#include #include +#include #include #include #include @@ -507,7 +507,6 @@ static int of_get_devfreq_events(struct device_node *np, struct device *dev = info->dev; struct device_node *events_np, *node; int i, j, count; - const struct of_device_id *of_id; int ret; events_np = of_get_child_by_name(np, "events"); @@ -525,13 +524,7 @@ static int of_get_devfreq_events(struct device_node *np, } info->num_events = count; - of_id = of_match_device(exynos_ppmu_id_match, dev); - if (of_id) - info->ppmu_type = (enum exynos_ppmu_type)of_id->data; - else { - of_node_put(events_np); - return -EINVAL; - } + info->ppmu_type = (enum exynos_ppmu_type)device_get_match_data(dev); j = 0; for_each_child_of_node(events_np, node) { From 6c29e29e4d7f29348a9e051ad5bdb833c5a1bbb6 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 12 Oct 2023 12:41:12 +0300 Subject: [PATCH 09/26] PM / devfreq: mediatek: unlock on error in mtk_ccifreq_target() Call mutex_unlock(&drv->reg_lock) before returning the error code. Link: https://lore.kernel.org/all/1bada9b2-d276-4123-bfdf-03d165569543@moroto.mountain/ Fixes: d2805601988f ("PM / devfreq: mediatek: protect oop in critical session") Signed-off-by: Dan Carpenter Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chanwoo Choi --- drivers/devfreq/mtk-cci-devfreq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c index b0ed25e33f2b..11bc3d03494c 100644 --- a/drivers/devfreq/mtk-cci-devfreq.c +++ b/drivers/devfreq/mtk-cci-devfreq.c @@ -146,7 +146,8 @@ static int mtk_ccifreq_target(struct device *dev, unsigned long *freq, opp = devfreq_recommended_opp(dev, &opp_rate, 1); if (IS_ERR(opp)) { dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate); - return PTR_ERR(opp); + ret = PTR_ERR(opp); + goto out_unlock; } voltage = dev_pm_opp_get_voltage(opp); From 9991166494f11569ce22ba1ba32dba789cf8b4ac Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:16:54 +0200 Subject: [PATCH 10/26] PM / devfreq: rockchip-dfi: Use free running counter The DDR_MON counters are free running counters. These are resetted to 0 when starting them over like currently done when reading the current counter values. Resetting the counters becomes a problem with perf support we want to add later, because perf needs counters that are not modified elsewhere. This patch removes resetting the counters and keeps them running instead. That means we no longer use the absolute counter values but instead compare them with the counter values we read last time. Not stopping the counters also has the impact that they are running while we are reading them. We cannot read multiple timers atomically, so the values do not exactly fit together. The effect should be negligible though as the time between two measurements is some orders of magnitude bigger than the time we need to read multiple registers. Link: https://lore.kernel.org/all/20231018061714.3553817-7-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 52 ++++++++++++++++------------ 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 680f629da64f..126bb744645b 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -38,11 +38,15 @@ #define DDRMON_CH1_COUNT_NUM 0x3c #define DDRMON_CH1_DFI_ACCESS_NUM 0x40 -struct dmc_usage { +struct dmc_count_channel { u32 access; u32 total; }; +struct dmc_count { + struct dmc_count_channel c[RK3399_DMC_NUM_CH]; +}; + /* * The dfi controller can monitor DDR load. It has an upper and lower threshold * for the operating points. Whenever the usage leaves these bounds an event is @@ -51,7 +55,7 @@ struct dmc_usage { struct rockchip_dfi { struct devfreq_event_dev *edev; struct devfreq_event_desc desc; - struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; + struct dmc_count last_event_count; struct device *dev; void __iomem *regs; struct regmap *regmap_pmu; @@ -85,30 +89,18 @@ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL); } -static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) +static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count) { struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); - u32 tmp, max = 0; - u32 i, busier_ch = 0; + u32 i; void __iomem *dfi_regs = dfi->regs; - rockchip_dfi_stop_hardware_counter(edev); - - /* Find out which channel is busier */ for (i = 0; i < RK3399_DMC_NUM_CH; i++) { - dfi->ch_usage[i].access = readl_relaxed(dfi_regs + + count->c[i].access = readl_relaxed(dfi_regs + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); - dfi->ch_usage[i].total = readl_relaxed(dfi_regs + + count->c[i].total = readl_relaxed(dfi_regs + DDRMON_CH0_COUNT_NUM + i * 20); - tmp = dfi->ch_usage[i].access; - if (tmp > max) { - busier_ch = i; - max = tmp; - } } - rockchip_dfi_start_hardware_counter(edev); - - return busier_ch; } static int rockchip_dfi_disable(struct devfreq_event_dev *edev) @@ -145,12 +137,28 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, struct devfreq_event_data *edata) { struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); - int busier_ch; + struct dmc_count count; + struct dmc_count *last = &dfi->last_event_count; + u32 access = 0, total = 0; + int i; - busier_ch = rockchip_dfi_get_busier_ch(edev); + rockchip_dfi_read_counters(edev, &count); - edata->load_count = dfi->ch_usage[busier_ch].access * 4; - edata->total_count = dfi->ch_usage[busier_ch].total; + /* We can only report one channel, so find the busiest one */ + for (i = 0; i < RK3399_DMC_NUM_CH; i++) { + u32 a = count.c[i].access - last->c[i].access; + u32 t = count.c[i].total - last->c[i].total; + + if (a > access) { + access = a; + total = t; + } + } + + edata->load_count = access * 4; + edata->total_count = total; + + dfi->last_event_count = count; return 0; } From 63dcf38eb57dcd19f9cadab12f7f9690f353b86d Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:16:55 +0200 Subject: [PATCH 11/26] PM / devfreq: rockchip-dfi: introduce channel mask Different Rockchip SoC variants have a different number of channels. Introduce a channel mask to make the number of channels configurable from SoC initialization code. Link: https://lore.kernel.org/all/20231018061714.3553817-8-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 126bb744645b..28c18bbf6baa 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -18,10 +18,11 @@ #include #include #include +#include #include -#define RK3399_DMC_NUM_CH 2 +#define DMC_MAX_CHANNELS 2 /* DDRMON_CTRL */ #define DDRMON_CTRL 0x04 @@ -44,7 +45,7 @@ struct dmc_count_channel { }; struct dmc_count { - struct dmc_count_channel c[RK3399_DMC_NUM_CH]; + struct dmc_count_channel c[DMC_MAX_CHANNELS]; }; /* @@ -61,6 +62,8 @@ struct rockchip_dfi { struct regmap *regmap_pmu; struct clk *clk; u32 ddr_type; + unsigned int channel_mask; + unsigned int max_channels; }; static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) @@ -95,7 +98,9 @@ static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm u32 i; void __iomem *dfi_regs = dfi->regs; - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { + for (i = 0; i < dfi->max_channels; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; count->c[i].access = readl_relaxed(dfi_regs + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); count->c[i].total = readl_relaxed(dfi_regs + @@ -145,9 +150,14 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, rockchip_dfi_read_counters(edev, &count); /* We can only report one channel, so find the busiest one */ - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { - u32 a = count.c[i].access - last->c[i].access; - u32 t = count.c[i].total - last->c[i].total; + for (i = 0; i < dfi->max_channels; i++) { + u32 a, t; + + if (!(dfi->channel_mask & BIT(i))) + continue; + + a = count.c[i].access - last->c[i].access; + t = count.c[i].total - last->c[i].total; if (a > access) { access = a; @@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & RK3399_PMUGRF_DDRTYPE_MASK; + dfi->channel_mask = GENMASK(1, 0); + dfi->max_channels = 2; + return 0; }; From 74002e668d0948d12eb2283891cfbd71be9d53c6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:16:56 +0200 Subject: [PATCH 12/26] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines The DDRTYPE defines are named to be RK3399 specific, but they can be used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_ prefix with ROCKCHIP_. They are defined in a SoC specific header file, so when generalizing the prefix also move the new defines to a SoC agnostic header file. While at it use GENMASK to define the DDRTYPE bitfield and give it a name including the full register name. Link: https://lore.kernel.org/all/20231018061714.3553817-9-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Acked-by: Heiko Stuebner Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 9 +++++---- drivers/devfreq/rk3399_dmc.c | 10 +++++----- include/soc/rockchip/rk3399_grf.h | 7 +------ include/soc/rockchip/rockchip_grf.h | 17 +++++++++++++++++ 4 files changed, 28 insertions(+), 15 deletions(-) create mode 100644 include/soc/rockchip/rockchip_grf.h diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 28c18bbf6baa..82d18c60538a 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -18,8 +18,10 @@ #include #include #include +#include #include +#include #include #define DMC_MAX_CHANNELS 2 @@ -75,9 +77,9 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); /* set ddr type to dfi */ - if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3) + if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); - else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4) + else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); /* enable count, use software mode */ @@ -192,8 +194,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) /* get ddr type */ regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); - dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & - RK3399_PMUGRF_DDRTYPE_MASK; + dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); dfi->channel_mask = GENMASK(1, 0); dfi->max_channels = 2; diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c index daff40702615..fd2c5ffedf41 100644 --- a/drivers/devfreq/rk3399_dmc.c +++ b/drivers/devfreq/rk3399_dmc.c @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) } regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); - ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & - RK3399_PMUGRF_DDRTYPE_MASK; + ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val); switch (ddr_type) { - case RK3399_PMUGRF_DDRTYPE_DDR3: + case ROCKCHIP_DDRTYPE_DDR3: data->odt_dis_freq = data->ddr3_odt_dis_freq; break; - case RK3399_PMUGRF_DDRTYPE_LPDDR3: + case ROCKCHIP_DDRTYPE_LPDDR3: data->odt_dis_freq = data->lpddr3_odt_dis_freq; break; - case RK3399_PMUGRF_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4: data->odt_dis_freq = data->lpddr4_odt_dis_freq; break; default: diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h index 3eebabcb2812..775f8444bea8 100644 --- a/include/soc/rockchip/rk3399_grf.h +++ b/include/soc/rockchip/rk3399_grf.h @@ -11,11 +11,6 @@ /* PMU GRF Registers */ #define RK3399_PMUGRF_OS_REG2 0x308 -#define RK3399_PMUGRF_DDRTYPE_SHIFT 13 -#define RK3399_PMUGRF_DDRTYPE_MASK 7 -#define RK3399_PMUGRF_DDRTYPE_DDR3 3 -#define RK3399_PMUGRF_DDRTYPE_LPDDR2 5 -#define RK3399_PMUGRF_DDRTYPE_LPDDR3 6 -#define RK3399_PMUGRF_DDRTYPE_LPDDR4 7 +#define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13) #endif diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h new file mode 100644 index 000000000000..dde1a9796ccb --- /dev/null +++ b/include/soc/rockchip/rockchip_grf.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Rockchip General Register Files definitions + */ + +#ifndef __SOC_ROCKCHIP_GRF_H +#define __SOC_ROCKCHIP_GRF_H + +/* Rockchip DDRTYPE defines */ +enum { + ROCKCHIP_DDRTYPE_DDR3 = 3, + ROCKCHIP_DDRTYPE_LPDDR2 = 5, + ROCKCHIP_DDRTYPE_LPDDR3 = 6, + ROCKCHIP_DDRTYPE_LPDDR4 = 7, +}; + +#endif /* __SOC_ROCKCHIP_GRF_H */ From d3b0f6ab0e3374820b7ab7f755a28e7a65ebf2b4 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:16:57 +0200 Subject: [PATCH 13/26] PM / devfreq: rockchip-dfi: Clean up DDR type register defines Use the HIWORD_UPDATE() define known from other rockchip drivers to make the defines look less odd to the readers who've seen other rockchip drivers. The HIWORD registers have their functional bits in the lower 16 bits whereas the upper 16 bits contain a mask. Only the functional bits that have the corresponding mask bit set are modified during a write. Although the register writes look different, the end result should be the same, at least there's no functional change intended with this patch. Link: https://lore.kernel.org/all/20231018061714.3553817-10-s.hauer@pengutronix.de/ Signed-off-by: Sascha Hauer Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 33 ++++++++++++++++++---------- 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 82d18c60538a..12f909687923 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -26,15 +26,19 @@ #define DMC_MAX_CHANNELS 2 +#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) + /* DDRMON_CTRL */ #define DDRMON_CTRL 0x04 -#define CLR_DDRMON_CTRL (0x1f0000 << 0) -#define LPDDR4_EN (0x10001 << 4) -#define HARDWARE_EN (0x10001 << 3) -#define LPDDR3_EN (0x10001 << 2) -#define SOFTWARE_EN (0x10001 << 1) -#define SOFTWARE_DIS (0x10000 << 1) -#define TIME_CNT_EN (0x10001 << 0) +#define DDRMON_CTRL_DDR4 BIT(5) +#define DDRMON_CTRL_LPDDR4 BIT(4) +#define DDRMON_CTRL_HARDWARE_EN BIT(3) +#define DDRMON_CTRL_LPDDR23 BIT(2) +#define DDRMON_CTRL_SOFTWARE_EN BIT(1) +#define DDRMON_CTRL_TIMER_CNT_EN BIT(0) +#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \ + DDRMON_CTRL_LPDDR4 | \ + DDRMON_CTRL_LPDDR23) #define DDRMON_CH0_COUNT_NUM 0x28 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c @@ -74,16 +78,20 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) void __iomem *dfi_regs = dfi->regs; /* clear DDRMON_CTRL setting */ - writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN | + DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL); /* set ddr type to dfi */ if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) - writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + DDRMON_CTRL); else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) - writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + DDRMON_CTRL); /* enable count, use software mode */ - writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + DDRMON_CTRL); } static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) @@ -91,7 +99,8 @@ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); void __iomem *dfi_regs = dfi->regs; - writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL); + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + DDRMON_CTRL); } static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count) From 076b0597f5b6fbec47cddedf9b39d864938a365c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:16:58 +0200 Subject: [PATCH 14/26] PM / devfreq: rockchip-dfi: Add RK3568 support This adds RK3568 support to the DFI driver. Only iniitialization differs from the currently supported RK3399. Link: https://lore.kernel.org/all/20231018061714.3553817-11-s.hauer@pengutronix.de/ Signed-off-by: Sascha Hauer Acked-by: Heiko Stuebner Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 27 +++++++++++++++++++++++++++ include/soc/rockchip/rk3568_grf.h | 12 ++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 include/soc/rockchip/rk3568_grf.h diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 12f909687923..571d72d1abd1 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -23,6 +23,7 @@ #include #include +#include #define DMC_MAX_CHANNELS 2 @@ -211,10 +212,36 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) return 0; }; +static int rk3568_dfi_init(struct rockchip_dfi *dfi) +{ + struct regmap *regmap_pmu = dfi->regmap_pmu; + u32 reg2, reg3; + + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, ®2); + regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, ®3); + + /* lower 3 bits of the DDR type */ + dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); + + /* + * For version three and higher the upper two bits of the DDR type are + * in RK3568_PMUGRF_OS_REG3 + */ + if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3) + dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3; + + dfi->channel_mask = BIT(0); + dfi->max_channels = 1; + + return 0; +}; + static const struct of_device_id rockchip_dfi_id_match[] = { { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init }, + { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init }, { }, }; + MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match); static int rockchip_dfi_probe(struct platform_device *pdev) diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h new file mode 100644 index 000000000000..575584e9d883 --- /dev/null +++ b/include/soc/rockchip/rk3568_grf.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __SOC_RK3568_GRF_H +#define __SOC_RK3568_GRF_H + +#define RK3568_PMUGRF_OS_REG2 0x208 +#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13) + +#define RK3568_PMUGRF_OS_REG3 0x20c +#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) +#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28) + +#endif /* __SOC_RK3568_GRF_H */ From 038ff6f53da07971a9df636bcc9bf1344c468dd5 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:16:59 +0200 Subject: [PATCH 15/26] PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while at it turn the if/else if/else into switch/case which makes it easier to read. Link: https://lore.kernel.org/all/20231018061714.3553817-12-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 571d72d1abd1..8ce0191552ef 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -83,12 +83,19 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL); /* set ddr type to dfi */ - if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3) + switch (dfi->ddr_type) { + case ROCKCHIP_DDRTYPE_LPDDR2: + case ROCKCHIP_DDRTYPE_LPDDR3: writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), dfi_regs + DDRMON_CTRL); - else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4) + break; + case ROCKCHIP_DDRTYPE_LPDDR4: writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), dfi_regs + DDRMON_CTRL); + break; + default: + break; + } /* enable count, use software mode */ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), From d8c6e337e71d3aa05414d8a06a4ff19d45c7be36 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:00 +0200 Subject: [PATCH 16/26] PM / devfreq: rockchip-dfi: Handle LPDDR4X In the DFI driver LPDDR4X can be handled in the same way as LPDDR4. Add the missing case. Link: https://lore.kernel.org/all/20231018061714.3553817-13-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Acked-by: Heiko Stuebner Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 1 + include/soc/rockchip/rockchip_grf.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 8ce0191552ef..bdf421b248df 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -90,6 +90,7 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) dfi_regs + DDRMON_CTRL); break; case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), dfi_regs + DDRMON_CTRL); break; diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h index dde1a9796ccb..e46fd72aea8d 100644 --- a/include/soc/rockchip/rockchip_grf.h +++ b/include/soc/rockchip/rockchip_grf.h @@ -12,6 +12,7 @@ enum { ROCKCHIP_DDRTYPE_LPDDR2 = 5, ROCKCHIP_DDRTYPE_LPDDR3 = 6, ROCKCHIP_DDRTYPE_LPDDR4 = 7, + ROCKCHIP_DDRTYPE_LPDDR4X = 8, }; #endif /* __SOC_ROCKCHIP_GRF_H */ From b82932fbd870b64fd71a999f9b61fbdcf2924ee6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:01 +0200 Subject: [PATCH 17/26] PM / devfreq: rockchip-dfi: Pass private data struct to internal functions The internal functions do not need the struct devfreq_event_dev *, so pass them the struct rockchip_dfi *. This is a preparation for adding perf support later which doesn't have a struct devfreq_event_dev *. Link: https://lore.kernel.org/all/20231018061714.3553817-14-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index bdf421b248df..d56a33d03db4 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -73,9 +73,8 @@ struct rockchip_dfi { unsigned int max_channels; }; -static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) +static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi *dfi) { - struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); void __iomem *dfi_regs = dfi->regs; /* clear DDRMON_CTRL setting */ @@ -103,18 +102,16 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) dfi_regs + DDRMON_CTRL); } -static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) +static void rockchip_dfi_stop_hardware_counter(struct rockchip_dfi *dfi) { - struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); void __iomem *dfi_regs = dfi->regs; writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), dfi_regs + DDRMON_CTRL); } -static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count) +static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count) { - struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); u32 i; void __iomem *dfi_regs = dfi->regs; @@ -132,7 +129,7 @@ static int rockchip_dfi_disable(struct devfreq_event_dev *edev) { struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); - rockchip_dfi_stop_hardware_counter(edev); + rockchip_dfi_stop_hardware_counter(dfi); clk_disable_unprepare(dfi->clk); return 0; @@ -149,7 +146,7 @@ static int rockchip_dfi_enable(struct devfreq_event_dev *edev) return ret; } - rockchip_dfi_start_hardware_counter(edev); + rockchip_dfi_start_hardware_counter(dfi); return 0; } @@ -167,7 +164,7 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, u32 access = 0, total = 0; int i; - rockchip_dfi_read_counters(edev, &count); + rockchip_dfi_read_counters(dfi, &count); /* We can only report one channel, so find the busiest one */ for (i = 0; i < dfi->max_channels; i++) { From d724f4a4581b2910ce79b45bd353ee66e7cf9d7f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:02 +0200 Subject: [PATCH 18/26] PM / devfreq: rockchip-dfi: Prepare for multiple users When adding perf support later the DFI must be enabled when either of devfreq-event or perf is active. Prepare for that by adding a usage counter for the DFI. Also move enabling and disabling of the clock away from the devfreq-event specific functions to which the perf specific part won't have access. Link: https://lore.kernel.org/all/20231018061714.3553817-15-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 57 +++++++++++++++++++--------- 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index d56a33d03db4..7a4f1901314d 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -68,14 +68,29 @@ struct rockchip_dfi { void __iomem *regs; struct regmap *regmap_pmu; struct clk *clk; + int usecount; + struct mutex mutex; u32 ddr_type; unsigned int channel_mask; unsigned int max_channels; }; -static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi *dfi) +static int rockchip_dfi_enable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; + int ret = 0; + + mutex_lock(&dfi->mutex); + + dfi->usecount++; + if (dfi->usecount > 1) + goto out; + + ret = clk_prepare_enable(dfi->clk); + if (ret) { + dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret); + goto out; + } /* clear DDRMON_CTRL setting */ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN | @@ -100,14 +115,30 @@ static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi *dfi) /* enable count, use software mode */ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), dfi_regs + DDRMON_CTRL); +out: + mutex_unlock(&dfi->mutex); + + return ret; } -static void rockchip_dfi_stop_hardware_counter(struct rockchip_dfi *dfi) +static void rockchip_dfi_disable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; + mutex_lock(&dfi->mutex); + + dfi->usecount--; + + WARN_ON_ONCE(dfi->usecount < 0); + + if (dfi->usecount > 0) + goto out; + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), dfi_regs + DDRMON_CTRL); + clk_disable_unprepare(dfi->clk); +out: + mutex_unlock(&dfi->mutex); } static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count) @@ -125,29 +156,20 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun } } -static int rockchip_dfi_disable(struct devfreq_event_dev *edev) +static int rockchip_dfi_event_disable(struct devfreq_event_dev *edev) { struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); - rockchip_dfi_stop_hardware_counter(dfi); - clk_disable_unprepare(dfi->clk); + rockchip_dfi_disable(dfi); return 0; } -static int rockchip_dfi_enable(struct devfreq_event_dev *edev) +static int rockchip_dfi_event_enable(struct devfreq_event_dev *edev) { struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); - int ret; - ret = clk_prepare_enable(dfi->clk); - if (ret) { - dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret); - return ret; - } - - rockchip_dfi_start_hardware_counter(dfi); - return 0; + return rockchip_dfi_enable(dfi); } static int rockchip_dfi_set_event(struct devfreq_event_dev *edev) @@ -191,8 +213,8 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, } static const struct devfreq_event_ops rockchip_dfi_ops = { - .disable = rockchip_dfi_disable, - .enable = rockchip_dfi_enable, + .disable = rockchip_dfi_event_disable, + .enable = rockchip_dfi_event_enable, .get_event = rockchip_dfi_get_event, .set_event = rockchip_dfi_set_event, }; @@ -280,6 +302,7 @@ static int rockchip_dfi_probe(struct platform_device *pdev) return PTR_ERR(dfi->regmap_pmu); dfi->dev = dev; + mutex_init(&dfi->mutex); desc = &dfi->desc; desc->ops = &rockchip_dfi_ops; From 2785cc00f6fa4e5ebd0927679ade6df367ac1f24 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:03 +0200 Subject: [PATCH 19/26] PM / devfreq: rockchip-dfi: give variable a better name struct dmc_count_channel::total counts the clock cycles of the DDR controller. Rename it accordingly to give the reader a better idea what this is about. While at it, at some documentation to struct dmc_count_channel. Link: https://lore.kernel.org/all/20231018061714.3553817-16-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 7a4f1901314d..3d5c6d737ccd 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -46,9 +46,14 @@ #define DDRMON_CH1_COUNT_NUM 0x3c #define DDRMON_CH1_DFI_ACCESS_NUM 0x40 +/** + * struct dmc_count_channel - structure to hold counter values from the DDR controller + * @access: Number of read and write accesses + * @clock_cycles: DDR clock cycles + */ struct dmc_count_channel { u32 access; - u32 total; + u32 clock_cycles; }; struct dmc_count { @@ -151,7 +156,7 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun continue; count->c[i].access = readl_relaxed(dfi_regs + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); - count->c[i].total = readl_relaxed(dfi_regs + + count->c[i].clock_cycles = readl_relaxed(dfi_regs + DDRMON_CH0_COUNT_NUM + i * 20); } } @@ -183,29 +188,29 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev); struct dmc_count count; struct dmc_count *last = &dfi->last_event_count; - u32 access = 0, total = 0; + u32 access = 0, clock_cycles = 0; int i; rockchip_dfi_read_counters(dfi, &count); /* We can only report one channel, so find the busiest one */ for (i = 0; i < dfi->max_channels; i++) { - u32 a, t; + u32 a, c; if (!(dfi->channel_mask & BIT(i))) continue; a = count.c[i].access - last->c[i].access; - t = count.c[i].total - last->c[i].total; + c = count.c[i].clock_cycles - last->c[i].clock_cycles; if (a > access) { access = a; - total = t; + clock_cycles = c; } } edata->load_count = access * 4; - edata->total_count = total; + edata->total_count = clock_cycles; dfi->last_event_count = count; From 4d586b5724d3233a73603000de7b8a035b493138 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 19 Oct 2023 08:48:19 +0200 Subject: [PATCH 20/26] PM / devfreq: rockchip-dfi: Add perf support The DFI is a unit which is suitable for measuring DDR utilization, but so far it could only be used as an event driver for the DDR frequency scaling driver. This adds perf support to the DFI driver. Usage with the 'perf' tool can look like: perf stat -a -e rockchip_ddr/cycles/,\ rockchip_ddr/read-bytes/,\ rockchip_ddr/write-bytes/,\ rockchip_ddr/bytes/ sleep 1 Performance counter stats for 'system wide': 1582524826 rockchip_ddr/cycles/ 1802.25 MB rockchip_ddr/read-bytes/ 1793.72 MB rockchip_ddr/write-bytes/ 3595.90 MB rockchip_ddr/bytes/ 1.014369709 seconds time elapsed perf support has been tested on a RK3568 and a RK3399, the latter with dual channel DDR. Link: https://lore.kernel.org/all/20231019064819.3496740-1-s.hauer@pengutronix.de/ Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Acked-by: Heiko Stuebner Signed-off-by: Sascha Hauer [cw00.choi: Fix typo from 'write_acccess' to 'write_access'] Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 440 ++++++++++++++++++++++++++- include/soc/rockchip/rk3399_grf.h | 2 + include/soc/rockchip/rk3568_grf.h | 1 + 3 files changed, 438 insertions(+), 5 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 3d5c6d737ccd..31303f753e48 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -16,10 +16,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include @@ -41,19 +43,39 @@ DDRMON_CTRL_LPDDR4 | \ DDRMON_CTRL_LPDDR23) +#define DDRMON_CH0_WR_NUM 0x20 +#define DDRMON_CH0_RD_NUM 0x24 #define DDRMON_CH0_COUNT_NUM 0x28 #define DDRMON_CH0_DFI_ACCESS_NUM 0x2c #define DDRMON_CH1_COUNT_NUM 0x3c #define DDRMON_CH1_DFI_ACCESS_NUM 0x40 +#define PERF_EVENT_CYCLES 0x0 +#define PERF_EVENT_READ_BYTES 0x1 +#define PERF_EVENT_WRITE_BYTES 0x2 +#define PERF_EVENT_READ_BYTES0 0x3 +#define PERF_EVENT_WRITE_BYTES0 0x4 +#define PERF_EVENT_READ_BYTES1 0x5 +#define PERF_EVENT_WRITE_BYTES1 0x6 +#define PERF_EVENT_READ_BYTES2 0x7 +#define PERF_EVENT_WRITE_BYTES2 0x8 +#define PERF_EVENT_READ_BYTES3 0x9 +#define PERF_EVENT_WRITE_BYTES3 0xa +#define PERF_EVENT_BYTES 0xb +#define PERF_ACCESS_TYPE_MAX 0xc + /** * struct dmc_count_channel - structure to hold counter values from the DDR controller * @access: Number of read and write accesses * @clock_cycles: DDR clock cycles + * @read_access: number of read accesses + * @write_access: number of write accesses */ struct dmc_count_channel { - u32 access; - u32 clock_cycles; + u64 access; + u64 clock_cycles; + u64 read_access; + u64 write_access; }; struct dmc_count { @@ -69,6 +91,11 @@ struct rockchip_dfi { struct devfreq_event_dev *edev; struct devfreq_event_desc desc; struct dmc_count last_event_count; + + struct dmc_count last_perf_count; + struct dmc_count total_count; + seqlock_t count_seqlock; /* protects last_perf_count and total_count */ + struct device *dev; void __iomem *regs; struct regmap *regmap_pmu; @@ -78,6 +105,14 @@ struct rockchip_dfi { u32 ddr_type; unsigned int channel_mask; unsigned int max_channels; + enum cpuhp_state cpuhp_state; + struct hlist_node node; + struct pmu pmu; + struct hrtimer timer; + unsigned int cpu; + int active_events; + int burst_len; + int buswidth[DMC_MAX_CHANNELS]; }; static int rockchip_dfi_enable(struct rockchip_dfi *dfi) @@ -146,7 +181,7 @@ out: mutex_unlock(&dfi->mutex); } -static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count) +static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *res) { u32 i; void __iomem *dfi_regs = dfi->regs; @@ -154,9 +189,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun for (i = 0; i < dfi->max_channels; i++) { if (!(dfi->channel_mask & BIT(i))) continue; - count->c[i].access = readl_relaxed(dfi_regs + + res->c[i].read_access = readl_relaxed(dfi_regs + + DDRMON_CH0_RD_NUM + i * 20); + res->c[i].write_access = readl_relaxed(dfi_regs + + DDRMON_CH0_WR_NUM + i * 20); + res->c[i].access = readl_relaxed(dfi_regs + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); - count->c[i].clock_cycles = readl_relaxed(dfi_regs + + res->c[i].clock_cycles = readl_relaxed(dfi_regs + DDRMON_CH0_COUNT_NUM + i * 20); } } @@ -224,6 +263,387 @@ static const struct devfreq_event_ops rockchip_dfi_ops = { .set_event = rockchip_dfi_set_event, }; +#ifdef CONFIG_PERF_EVENTS + +static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi, + const struct dmc_count *now, + struct dmc_count *res) +{ + const struct dmc_count *last = &dfi->last_perf_count; + int i; + + for (i = 0; i < dfi->max_channels; i++) { + res->c[i].read_access = dfi->total_count.c[i].read_access + + (u32)(now->c[i].read_access - last->c[i].read_access); + res->c[i].write_access = dfi->total_count.c[i].write_access + + (u32)(now->c[i].write_access - last->c[i].write_access); + res->c[i].access = dfi->total_count.c[i].access + + (u32)(now->c[i].access - last->c[i].access); + res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles + + (u32)(now->c[i].clock_cycles - last->c[i].clock_cycles); + } +} + +static ssize_t ddr_perf_cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pmu *pmu = dev_get_drvdata(dev); + struct rockchip_dfi *dfi = container_of(pmu, struct rockchip_dfi, pmu); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(dfi->cpu)); +} + +static struct device_attribute ddr_perf_cpumask_attr = + __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL); + +static struct attribute *ddr_perf_cpumask_attrs[] = { + &ddr_perf_cpumask_attr.attr, + NULL, +}; + +static const struct attribute_group ddr_perf_cpumask_attr_group = { + .attrs = ddr_perf_cpumask_attrs, +}; + +PMU_EVENT_ATTR_STRING(cycles, ddr_pmu_cycles, "event="__stringify(PERF_EVENT_CYCLES)) + +#define DFI_PMU_EVENT_ATTR(_name, _var, _str) \ + PMU_EVENT_ATTR_STRING(_name, _var, _str); \ + PMU_EVENT_ATTR_STRING(_name.unit, _var##_unit, "MB"); \ + PMU_EVENT_ATTR_STRING(_name.scale, _var##_scale, "9.536743164e-07") + +DFI_PMU_EVENT_ATTR(read-bytes0, ddr_pmu_read_bytes0, "event="__stringify(PERF_EVENT_READ_BYTES0)); +DFI_PMU_EVENT_ATTR(write-bytes0, ddr_pmu_write_bytes0, "event="__stringify(PERF_EVENT_WRITE_BYTES0)); + +DFI_PMU_EVENT_ATTR(read-bytes1, ddr_pmu_read_bytes1, "event="__stringify(PERF_EVENT_READ_BYTES1)); +DFI_PMU_EVENT_ATTR(write-bytes1, ddr_pmu_write_bytes1, "event="__stringify(PERF_EVENT_WRITE_BYTES1)); + +DFI_PMU_EVENT_ATTR(read-bytes2, ddr_pmu_read_bytes2, "event="__stringify(PERF_EVENT_READ_BYTES2)); +DFI_PMU_EVENT_ATTR(write-bytes2, ddr_pmu_write_bytes2, "event="__stringify(PERF_EVENT_WRITE_BYTES2)); + +DFI_PMU_EVENT_ATTR(read-bytes3, ddr_pmu_read_bytes3, "event="__stringify(PERF_EVENT_READ_BYTES3)); +DFI_PMU_EVENT_ATTR(write-bytes3, ddr_pmu_write_bytes3, "event="__stringify(PERF_EVENT_WRITE_BYTES3)); + +DFI_PMU_EVENT_ATTR(read-bytes, ddr_pmu_read_bytes, "event="__stringify(PERF_EVENT_READ_BYTES)); +DFI_PMU_EVENT_ATTR(write-bytes, ddr_pmu_write_bytes, "event="__stringify(PERF_EVENT_WRITE_BYTES)); + +DFI_PMU_EVENT_ATTR(bytes, ddr_pmu_bytes, "event="__stringify(PERF_EVENT_BYTES)); + +#define DFI_ATTR_MB(_name) \ + &_name.attr.attr, \ + &_name##_unit.attr.attr, \ + &_name##_scale.attr.attr + +static struct attribute *ddr_perf_events_attrs[] = { + &ddr_pmu_cycles.attr.attr, + DFI_ATTR_MB(ddr_pmu_read_bytes), + DFI_ATTR_MB(ddr_pmu_write_bytes), + DFI_ATTR_MB(ddr_pmu_read_bytes0), + DFI_ATTR_MB(ddr_pmu_write_bytes0), + DFI_ATTR_MB(ddr_pmu_read_bytes1), + DFI_ATTR_MB(ddr_pmu_write_bytes1), + DFI_ATTR_MB(ddr_pmu_read_bytes2), + DFI_ATTR_MB(ddr_pmu_write_bytes2), + DFI_ATTR_MB(ddr_pmu_read_bytes3), + DFI_ATTR_MB(ddr_pmu_write_bytes3), + DFI_ATTR_MB(ddr_pmu_bytes), + NULL, +}; + +static const struct attribute_group ddr_perf_events_attr_group = { + .name = "events", + .attrs = ddr_perf_events_attrs, +}; + +PMU_FORMAT_ATTR(event, "config:0-7"); + +static struct attribute *ddr_perf_format_attrs[] = { + &format_attr_event.attr, + NULL, +}; + +static const struct attribute_group ddr_perf_format_attr_group = { + .name = "format", + .attrs = ddr_perf_format_attrs, +}; + +static const struct attribute_group *attr_groups[] = { + &ddr_perf_events_attr_group, + &ddr_perf_cpumask_attr_group, + &ddr_perf_format_attr_group, + NULL, +}; + +static int rockchip_ddr_perf_event_init(struct perf_event *event) +{ + struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu); + + if (event->attr.type != event->pmu->type) + return -ENOENT; + + if (event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + if (event->cpu < 0) { + dev_warn(dfi->dev, "Can't provide per-task data!\n"); + return -EINVAL; + } + + return 0; +} + +static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event) +{ + struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu); + int blen = dfi->burst_len; + struct dmc_count total, now; + unsigned int seq; + u64 count = 0; + int i; + + rockchip_dfi_read_counters(dfi, &now); + + do { + seq = read_seqbegin(&dfi->count_seqlock); + rockchip_ddr_perf_counters_add(dfi, &now, &total); + } while (read_seqretry(&dfi->count_seqlock, seq)); + + switch (event->attr.config) { + case PERF_EVENT_CYCLES: + count = total.c[0].clock_cycles; + break; + case PERF_EVENT_READ_BYTES: + for (i = 0; i < dfi->max_channels; i++) + count += total.c[i].read_access * blen * dfi->buswidth[i]; + break; + case PERF_EVENT_WRITE_BYTES: + for (i = 0; i < dfi->max_channels; i++) + count += total.c[i].write_access * blen * dfi->buswidth[i]; + break; + case PERF_EVENT_READ_BYTES0: + count = total.c[0].read_access * blen * dfi->buswidth[0]; + break; + case PERF_EVENT_WRITE_BYTES0: + count = total.c[0].write_access * blen * dfi->buswidth[0]; + break; + case PERF_EVENT_READ_BYTES1: + count = total.c[1].read_access * blen * dfi->buswidth[1]; + break; + case PERF_EVENT_WRITE_BYTES1: + count = total.c[1].write_access * blen * dfi->buswidth[1]; + break; + case PERF_EVENT_READ_BYTES2: + count = total.c[2].read_access * blen * dfi->buswidth[2]; + break; + case PERF_EVENT_WRITE_BYTES2: + count = total.c[2].write_access * blen * dfi->buswidth[2]; + break; + case PERF_EVENT_READ_BYTES3: + count = total.c[3].read_access * blen * dfi->buswidth[3]; + break; + case PERF_EVENT_WRITE_BYTES3: + count = total.c[3].write_access * blen * dfi->buswidth[3]; + break; + case PERF_EVENT_BYTES: + for (i = 0; i < dfi->max_channels; i++) + count += total.c[i].access * blen * dfi->buswidth[i]; + break; + } + + return count; +} + +static void rockchip_ddr_perf_event_update(struct perf_event *event) +{ + u64 now; + s64 prev; + + if (event->attr.config >= PERF_ACCESS_TYPE_MAX) + return; + + now = rockchip_ddr_perf_event_get_count(event); + prev = local64_xchg(&event->hw.prev_count, now); + local64_add(now - prev, &event->count); +} + +static void rockchip_ddr_perf_event_start(struct perf_event *event, int flags) +{ + u64 now = rockchip_ddr_perf_event_get_count(event); + + local64_set(&event->hw.prev_count, now); +} + +static int rockchip_ddr_perf_event_add(struct perf_event *event, int flags) +{ + struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu); + + dfi->active_events++; + + if (dfi->active_events == 1) { + dfi->total_count = (struct dmc_count){}; + rockchip_dfi_read_counters(dfi, &dfi->last_perf_count); + hrtimer_start(&dfi->timer, ns_to_ktime(NSEC_PER_SEC), HRTIMER_MODE_REL); + } + + if (flags & PERF_EF_START) + rockchip_ddr_perf_event_start(event, flags); + + return 0; +} + +static void rockchip_ddr_perf_event_stop(struct perf_event *event, int flags) +{ + rockchip_ddr_perf_event_update(event); +} + +static void rockchip_ddr_perf_event_del(struct perf_event *event, int flags) +{ + struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu); + + rockchip_ddr_perf_event_stop(event, PERF_EF_UPDATE); + + dfi->active_events--; + + if (dfi->active_events == 0) + hrtimer_cancel(&dfi->timer); +} + +static enum hrtimer_restart rockchip_dfi_timer(struct hrtimer *timer) +{ + struct rockchip_dfi *dfi = container_of(timer, struct rockchip_dfi, timer); + struct dmc_count now, total; + + rockchip_dfi_read_counters(dfi, &now); + + write_seqlock(&dfi->count_seqlock); + + rockchip_ddr_perf_counters_add(dfi, &now, &total); + dfi->total_count = total; + dfi->last_perf_count = now; + + write_sequnlock(&dfi->count_seqlock); + + hrtimer_forward_now(&dfi->timer, ns_to_ktime(NSEC_PER_SEC)); + + return HRTIMER_RESTART; +}; + +static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct rockchip_dfi *dfi = hlist_entry_safe(node, struct rockchip_dfi, node); + int target; + + if (cpu != dfi->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + perf_pmu_migrate_context(&dfi->pmu, cpu, target); + dfi->cpu = target; + + return 0; +} + +static void rockchip_ddr_cpuhp_remove_state(void *data) +{ + struct rockchip_dfi *dfi = data; + + cpuhp_remove_multi_state(dfi->cpuhp_state); + + rockchip_dfi_disable(dfi); +} + +static void rockchip_ddr_cpuhp_remove_instance(void *data) +{ + struct rockchip_dfi *dfi = data; + + cpuhp_state_remove_instance_nocalls(dfi->cpuhp_state, &dfi->node); +} + +static void rockchip_ddr_perf_remove(void *data) +{ + struct rockchip_dfi *dfi = data; + + perf_pmu_unregister(&dfi->pmu); +} + +static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi) +{ + struct pmu *pmu = &dfi->pmu; + int ret; + + seqlock_init(&dfi->count_seqlock); + + pmu->module = THIS_MODULE; + pmu->capabilities = PERF_PMU_CAP_NO_EXCLUDE; + pmu->task_ctx_nr = perf_invalid_context; + pmu->attr_groups = attr_groups; + pmu->event_init = rockchip_ddr_perf_event_init; + pmu->add = rockchip_ddr_perf_event_add; + pmu->del = rockchip_ddr_perf_event_del; + pmu->start = rockchip_ddr_perf_event_start; + pmu->stop = rockchip_ddr_perf_event_stop; + pmu->read = rockchip_ddr_perf_event_update; + + dfi->cpu = raw_smp_processor_id(); + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "rockchip_ddr_perf_pmu", + NULL, + ddr_perf_offline_cpu); + + if (ret < 0) { + dev_err(dfi->dev, "cpuhp_setup_state_multi failed: %d\n", ret); + return ret; + } + + dfi->cpuhp_state = ret; + + rockchip_dfi_enable(dfi); + + ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_state, dfi); + if (ret) + return ret; + + ret = cpuhp_state_add_instance_nocalls(dfi->cpuhp_state, &dfi->node); + if (ret) { + dev_err(dfi->dev, "Error %d registering hotplug\n", ret); + return ret; + } + + ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_instance, dfi); + if (ret) + return ret; + + hrtimer_init(&dfi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + dfi->timer.function = rockchip_dfi_timer; + + switch (dfi->ddr_type) { + case ROCKCHIP_DDRTYPE_LPDDR2: + case ROCKCHIP_DDRTYPE_LPDDR3: + dfi->burst_len = 8; + break; + case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: + dfi->burst_len = 16; + break; + } + + ret = perf_pmu_register(pmu, "rockchip_ddr", -1); + if (ret) + return ret; + + return devm_add_action_or_reset(dfi->dev, rockchip_ddr_perf_remove, dfi); +} +#else +static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi) +{ + return 0; +} +#endif + static int rk3399_dfi_init(struct rockchip_dfi *dfi) { struct regmap *regmap_pmu = dfi->regmap_pmu; @@ -241,6 +661,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->channel_mask = GENMASK(1, 0); dfi->max_channels = 2; + dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2; + dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2; + return 0; }; @@ -265,6 +688,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) dfi->channel_mask = BIT(0); dfi->max_channels = 1; + dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; + return 0; }; @@ -325,6 +750,10 @@ static int rockchip_dfi_probe(struct platform_device *pdev) return PTR_ERR(dfi->edev); } + ret = rockchip_ddr_perf_init(dfi); + if (ret) + return ret; + platform_set_drvdata(pdev, dfi); return 0; @@ -335,6 +764,7 @@ static struct platform_driver rockchip_dfi_driver = { .driver = { .name = "rockchip-dfi", .of_match_table = rockchip_dfi_id_match, + .suppress_bind_attrs = true, }, }; module_platform_driver(rockchip_dfi_driver); diff --git a/include/soc/rockchip/rk3399_grf.h b/include/soc/rockchip/rk3399_grf.h index 775f8444bea8..39cd44cec982 100644 --- a/include/soc/rockchip/rk3399_grf.h +++ b/include/soc/rockchip/rk3399_grf.h @@ -12,5 +12,7 @@ /* PMU GRF Registers */ #define RK3399_PMUGRF_OS_REG2 0x308 #define RK3399_PMUGRF_OS_REG2_DDRTYPE GENMASK(15, 13) +#define RK3399_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2) +#define RK3399_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18) #endif diff --git a/include/soc/rockchip/rk3568_grf.h b/include/soc/rockchip/rk3568_grf.h index 575584e9d883..52853efd6720 100644 --- a/include/soc/rockchip/rk3568_grf.h +++ b/include/soc/rockchip/rk3568_grf.h @@ -4,6 +4,7 @@ #define RK3568_PMUGRF_OS_REG2 0x208 #define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13) +#define RK3568_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2) #define RK3568_PMUGRF_OS_REG3 0x20c #define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) From d1d0b3fe95d888f1ae82a0cf6a594fa0c3cbfa79 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:05 +0200 Subject: [PATCH 21/26] PM / devfreq: rockchip-dfi: make register stride SoC specific The currently supported RK3399 has a stride of 20 between the channel specific registers. Upcoming RK3588 has a different stride, so put the stride into driver data to make it configurable. While at it convert decimal 20 to hex 0x14 for consistency with RK3588 which has a register stride 0x4000 and we want to write that in hex as well. Link: https://lore.kernel.org/all/20231018061714.3553817-18-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 31303f753e48..8ab97aba6334 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -113,6 +113,7 @@ struct rockchip_dfi { int active_events; int burst_len; int buswidth[DMC_MAX_CHANNELS]; + int ddrmon_stride; }; static int rockchip_dfi_enable(struct rockchip_dfi *dfi) @@ -190,13 +191,13 @@ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_coun if (!(dfi->channel_mask & BIT(i))) continue; res->c[i].read_access = readl_relaxed(dfi_regs + - DDRMON_CH0_RD_NUM + i * 20); + DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride); res->c[i].write_access = readl_relaxed(dfi_regs + - DDRMON_CH0_WR_NUM + i * 20); + DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride); res->c[i].access = readl_relaxed(dfi_regs + - DDRMON_CH0_DFI_ACCESS_NUM + i * 20); + DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride); res->c[i].clock_cycles = readl_relaxed(dfi_regs + - DDRMON_CH0_COUNT_NUM + i * 20); + DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride); } } @@ -664,6 +665,8 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2; dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2; + dfi->ddrmon_stride = 0x14; + return 0; }; @@ -690,6 +693,8 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; + dfi->ddrmon_stride = 0x0; /* not relevant, we only have a single channel on this SoC */ + return 0; }; From bbe7cbd07406b75ec845eb261f25373bf88b276a Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:06 +0200 Subject: [PATCH 22/26] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers The currently supported RK3399 has a set of registers per channel, but it has only a single DDRMON_CTRL register. With upcoming RK3588 this will be different, the RK3588 has a DDRMON_CTRL register per channel. Instead of expecting a single DDRMON_CTRL register, loop over the channels and write the channel specific DDRMON_CTRL register. Break out early out of the loop when there is only a single DDRMON_CTRL register like on the RK3399. Link: https://lore.kernel.org/all/20231018061714.3553817-19-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 73 +++++++++++++++++++--------- 1 file changed, 49 insertions(+), 24 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 8ab97aba6334..f292031e30a6 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -114,12 +114,13 @@ struct rockchip_dfi { int burst_len; int buswidth[DMC_MAX_CHANNELS]; int ddrmon_stride; + bool ddrmon_ctrl_single; }; static int rockchip_dfi_enable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; - int ret = 0; + int i, ret = 0; mutex_lock(&dfi->mutex); @@ -133,29 +134,41 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) goto out; } - /* clear DDRMON_CTRL setting */ - writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN | - DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL); + for (i = 0; i < dfi->max_channels; i++) { + u32 ctrl = 0; - /* set ddr type to dfi */ - switch (dfi->ddr_type) { - case ROCKCHIP_DDRTYPE_LPDDR2: - case ROCKCHIP_DDRTYPE_LPDDR3: - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), - dfi_regs + DDRMON_CTRL); - break; - case ROCKCHIP_DDRTYPE_LPDDR4: - case ROCKCHIP_DDRTYPE_LPDDR4X: - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), - dfi_regs + DDRMON_CTRL); - break; - default: - break; + if (!(dfi->channel_mask & BIT(i))) + continue; + + /* clear DDRMON_CTRL setting */ + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | + DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + /* set ddr type to dfi */ + switch (dfi->ddr_type) { + case ROCKCHIP_DDRTYPE_LPDDR2: + case ROCKCHIP_DDRTYPE_LPDDR3: + ctrl = DDRMON_CTRL_LPDDR23; + break; + case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: + ctrl = DDRMON_CTRL_LPDDR4; + break; + default: + break; + } + + writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + /* enable count, use software mode */ + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + if (dfi->ddrmon_ctrl_single) + break; } - - /* enable count, use software mode */ - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), - dfi_regs + DDRMON_CTRL); out: mutex_unlock(&dfi->mutex); @@ -165,6 +178,7 @@ out: static void rockchip_dfi_disable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; + int i; mutex_lock(&dfi->mutex); @@ -175,8 +189,17 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi) if (dfi->usecount > 0) goto out; - writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), - dfi_regs + DDRMON_CTRL); + for (i = 0; i < dfi->max_channels; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; + + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + if (dfi->ddrmon_ctrl_single) + break; + } + clk_disable_unprepare(dfi->clk); out: mutex_unlock(&dfi->mutex); @@ -666,6 +689,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2; dfi->ddrmon_stride = 0x14; + dfi->ddrmon_ctrl_single = true; return 0; }; @@ -694,6 +718,7 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; dfi->ddrmon_stride = 0x0; /* not relevant, we only have a single channel on this SoC */ + dfi->ddrmon_ctrl_single = true; return 0; }; From 481d97ba61e12f34acc59b6632de1aed7c93b824 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:07 +0200 Subject: [PATCH 23/26] PM / devfreq: rockchip-dfi: add support for RK3588 Add support for the RK3588 to the driver. The RK3588 has four DDR channels with a register stride of 0x4000 between the channel registers, also it has a DDRMON_CTRL register per channel. Link: https://lore.kernel.org/all/20231018061714.3553817-20-s.hauer@pengutronix.de/ Reviewed-by: Jonathan Cameron Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Acked-by: Heiko Stuebner Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- drivers/devfreq/event/rockchip-dfi.c | 36 +++++++++++++++++++++++++++- include/soc/rockchip/rk3588_grf.h | 18 ++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 include/soc/rockchip/rk3588_grf.h diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index f292031e30a6..e2a1e4463b6f 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -26,8 +26,9 @@ #include #include #include +#include -#define DMC_MAX_CHANNELS 2 +#define DMC_MAX_CHANNELS 4 #define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16) @@ -723,9 +724,42 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi) return 0; }; +static int rk3588_dfi_init(struct rockchip_dfi *dfi) +{ + struct regmap *regmap_pmu = dfi->regmap_pmu; + u32 reg2, reg3, reg4; + + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, ®2); + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, ®3); + regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, ®4); + + /* lower 3 bits of the DDR type */ + dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); + + /* + * For version three and higher the upper two bits of the DDR type are + * in RK3588_PMUGRF_OS_REG3 + */ + if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3) + dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3; + + dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; + dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2; + dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2; + dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2; + dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) | + FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2; + dfi->max_channels = 4; + + dfi->ddrmon_stride = 0x4000; + + return 0; +}; + static const struct of_device_id rockchip_dfi_id_match[] = { { .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init }, { .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init }, + { .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init }, { }, }; diff --git a/include/soc/rockchip/rk3588_grf.h b/include/soc/rockchip/rk3588_grf.h new file mode 100644 index 000000000000..630b35a55064 --- /dev/null +++ b/include/soc/rockchip/rk3588_grf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __SOC_RK3588_GRF_H +#define __SOC_RK3588_GRF_H + +#define RK3588_PMUGRF_OS_REG2 0x208 +#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO GENMASK(15, 13) +#define RK3588_PMUGRF_OS_REG2_BW_CH0 GENMASK(3, 2) +#define RK3588_PMUGRF_OS_REG2_BW_CH1 GENMASK(19, 18) +#define RK3588_PMUGRF_OS_REG2_CH_INFO GENMASK(29, 28) + +#define RK3588_PMUGRF_OS_REG3 0x20c +#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12) +#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28) + +#define RK3588_PMUGRF_OS_REG4 0x210 +#define RK3588_PMUGRF_OS_REG5 0x214 + +#endif /* __SOC_RK3588_GRF_H */ From 7fd696076e0f441c1a6415619c3c96afecb513aa Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:08 +0200 Subject: [PATCH 24/26] dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml Convert the Rockchip DFI binding to yaml. Link: https://lore.kernel.org/all/20231018061714.3553817-21-s.hauer@pengutronix.de/ Reviewed-by: Rob Herring Reviewed-by: Sebastian Reichel Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- .../bindings/devfreq/event/rockchip,dfi.yaml | 61 +++++++++++++++++++ .../bindings/devfreq/event/rockchip-dfi.txt | 18 ------ .../rockchip,rk3399-dmc.yaml | 2 +- 3 files changed, 62 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml new file mode 100644 index 000000000000..7a82f6ae0701 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/event/rockchip,dfi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DFI + +maintainers: + - Sascha Hauer + +properties: + compatible: + enum: + - rockchip,rk3399-dfi + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk_ddr_mon + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "PMU general register files". + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + dfi: dfi@ff630000 { + compatible = "rockchip,rk3399-dfi"; + reg = <0x00 0xff630000 0x00 0x4000>; + interrupts = ; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + }; + }; diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt deleted file mode 100644 index 148191b0fc15..000000000000 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt +++ /dev/null @@ -1,18 +0,0 @@ - -* Rockchip rk3399 DFI device - -Required properties: -- compatible: Must be "rockchip,rk3399-dfi". -- reg: physical base address of each DFI and length of memory mapped region -- rockchip,pmu: phandle to the syscon managing the "pmu general register files" -- clocks: phandles for clock specified in "clock-names" property -- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon"; - -Example: - dfi: dfi@ff630000 { - compatible = "rockchip,rk3399-dfi"; - reg = <0x00 0xff630000 0x00 0x4000>; - rockchip,pmu = <&pmugrf>; - clocks = <&cru PCLK_DDR_MON>; - clock-names = "pclk_ddr_mon"; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml index 4e4af3cfc0fe..1f58ee99be28 100644 --- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml @@ -18,7 +18,7 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: Node to get DDR loading. Refer to - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt. + Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml. clocks: maxItems: 1 From 97cfa4ae843ebfb2ba541e78ce190e2d1481cf3f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:09 +0200 Subject: [PATCH 25/26] dt-bindings: devfreq: event: rockchip,dfi: Add rk3568 support This adds the rockchip,rk3568-dfi compatible to the binding. Make clocks optional for this SoC as the RK3568 doesn't have a kernel controllable PCLK. Link: https://lore.kernel.org/all/20231018061714.3553817-22-s.hauer@pengutronix.de/ Reviewed-by: Conor Dooley Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- .../bindings/devfreq/event/rockchip,dfi.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml index 7a82f6ae0701..e8b64494ee8b 100644 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml @@ -13,6 +13,7 @@ properties: compatible: enum: - rockchip,rk3399-dfi + - rockchip,rk3568-dfi clocks: maxItems: 1 @@ -34,11 +35,21 @@ properties: required: - compatible - - clocks - - clock-names - interrupts - reg +if: + properties: + compatible: + contains: + enum: + - rockchip,rk3399-dfi + +then: + required: + - clocks + - clock-names + additionalProperties: false examples: From 8f0cd531ee18c70f4655112c49f3c3e329636e7f Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Oct 2023 08:17:10 +0200 Subject: [PATCH 26/26] dt-bindings: devfreq: event: rockchip,dfi: Add rk3588 support This adds rockchip,rk3588-dfi to the list of compatibles. Unlike ealier SoCs the rk3588 has four interrupts (one for each channel) instead of only one, so increase the number of allowed interrupts to four. Link: https://lore.kernel.org/all/20231018061714.3553817-23-s.hauer@pengutronix.de/ Acked-by: Conor Dooley Acked-by: Chanwoo Choi Signed-off-by: Sascha Hauer Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/devfreq/event/rockchip,dfi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml index e8b64494ee8b..50d3fabe958d 100644 --- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml @@ -14,6 +14,7 @@ properties: enum: - rockchip,rk3399-dfi - rockchip,rk3568-dfi + - rockchip,rk3588-dfi clocks: maxItems: 1 @@ -23,7 +24,8 @@ properties: - const: pclk_ddr_mon interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 reg: maxItems: 1