From 611cd69fe4c737c37a79ef7b99a2f15aff252d1d Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Thu, 25 Jul 2024 10:25:18 +0100 Subject: [PATCH 01/14] ARM: dts: qcom: pma8084: add pon node Wrap existing pwrkey node inside a pon node, to conform to dt schema. Reviewed-by: Konrad Dybcio Signed-off-by: Rayyan Ansari Link: https://lore.kernel.org/r/20240725-pmic-bindings-v3-3-d7f6007b530d@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/pma8084.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/pma8084.dtsi b/arch/arm/boot/dts/qcom/pma8084.dtsi index 2985f4805b93..309f5256754b 100644 --- a/arch/arm/boot/dts/qcom/pma8084.dtsi +++ b/arch/arm/boot/dts/qcom/pma8084.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include @@ -19,12 +20,17 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; + pon@800 { + compatible = "qcom,pm8941-pon"; reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; }; pma8084_gpios: gpio@c000 { From 046301eafc3296efe7266832b47c9cc93ff0ad38 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Thu, 11 Jul 2024 12:01:38 +0100 Subject: [PATCH 02/14] ARM: dts: qcom: apq8064-pins: correct error in drive-strength property The "drive-strength" property was incorrectly spelt as "drive-strengh". Correct this. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240711110545.31641-3-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi index 7c545c50847b..107fc19f1331 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -11,19 +11,19 @@ sdcc1_pins: sdcc1-pin-active { clk { pins = "sdc1_clk"; - drive-strengh = <16>; + drive-strength = <16>; bias-disable; }; cmd { pins = "sdc1_cmd"; - drive-strengh = <10>; + drive-strength = <10>; bias-pull-up; }; data { pins = "sdc1_data"; - drive-strengh = <10>; + drive-strength = <10>; bias-pull-up; }; }; @@ -31,19 +31,19 @@ sdcc3_pins: sdcc3-pin-active { clk { pins = "sdc3_clk"; - drive-strengh = <8>; + drive-strength = <8>; bias-disable; }; cmd { pins = "sdc3_cmd"; - drive-strengh = <8>; + drive-strength = <8>; bias-pull-up; }; data { pins = "sdc3_data"; - drive-strengh = <8>; + drive-strength = <8>; bias-pull-up; }; }; From 6dbec1c39d3ff53e24e434862c7b7da3552b1ffe Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Thu, 11 Jul 2024 12:01:39 +0100 Subject: [PATCH 03/14] ARM: dts: qcom: asus,nexus7-flo: remove duplicate pinctrl handle in i2c nodes Remove duplicate handle to i2c pins in the device tree, as they are already set in qcom-apq8064.dtsi. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240711110545.31641-4-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts index d460743fbb94..947183992850 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-asus-nexus7-flo.dts @@ -125,8 +125,6 @@ &gsbi1_i2c { status = "okay"; clock-frequency = <200000>; - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; eeprom@52 { compatible = "atmel,24c128"; @@ -148,8 +146,6 @@ &gsbi3_i2c { clock-frequency = <200000>; - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; status = "okay"; trackpad@10 { From c9c8f449c8a27791bd8540cbcb538a19568608cc Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Thu, 11 Jul 2024 12:01:40 +0100 Subject: [PATCH 04/14] ARM: dts: qcom: apq8064: adhere to pinctrl dtschema Pass dtbs_check for qcom,apq8064-pinctrl.yaml. Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240711110545.31641-5-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-apq8064-cm-qs600.dts | 25 +- .../boot/dts/qcom/qcom-apq8064-ifc6410.dts | 25 +- arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 382 +++++++----------- .../qcom-apq8064-sony-xperia-lagan-yuga.dts | 10 +- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 34 +- 5 files changed, 182 insertions(+), 294 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts index 671d58cc2741..178c55c1efeb 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-cm-qs600.dts @@ -188,24 +188,17 @@ }; &tlmm_pinmux { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; + card_detect: card-detect-state { + pins = "gpio26"; + function = "gpio"; + bias-disable; }; - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; + pcie_pins: pcie-state { + pins = "gpio27"; + function = "gpio"; + drive-strength = <12>; + bias-disable; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts index ed86b24119c9..b3ff8010b149 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-ifc6410.dts @@ -321,24 +321,17 @@ }; &tlmm_pinmux { - card_detect: card_detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; + card_detect: card-detect-state { + pins = "gpio26"; + function = "gpio"; + bias-disable; }; - pcie_pins: pcie_pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; + pcie_pins: pcie-state { + pins = "gpio27"; + function = "gpio"; + drive-strength = <12>; + bias-disable; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi index 107fc19f1331..e53de709e9d1 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -1,236 +1,59 @@ // SPDX-License-Identifier: GPL-2.0 &tlmm_pinmux { - sdc4_gpios: sdc4-gpios { - pios { - pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; - function = "sdc4"; - }; - }; - - sdcc1_pins: sdcc1-pin-active { - clk { + sdcc1_default_state: sdcc1-default-state { + clk-pins { pins = "sdc1_clk"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { pins = "sdc1_data"; drive-strength = <10>; bias-pull-up; }; }; - sdcc3_pins: sdcc3-pin-active { - clk { + sdcc3_default_state: sdcc3-default-state { + clk-pins { pins = "sdc3_clk"; drive-strength = <8>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc3_cmd"; drive-strength = <8>; bias-pull-up; }; - data { + data-pins { pins = "sdc3_data"; drive-strength = <8>; bias-pull-up; }; }; - ps_hold: ps_hold { - mux { - pins = "gpio78"; - function = "ps_hold"; - }; + sdc4_default_state: sdc4-default-state { + pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; + function = "sdc4"; }; - i2c1_pins: i2c1 { - mux { - pins = "gpio20", "gpio21"; - function = "gsbi1"; - }; - - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <16>; - bias-disable; - }; + gsbi1_uart_2pins: gsbi1-uart-2pins-state { + pins = "gpio18", "gpio19"; + function = "gsbi1"; }; - i2c1_pins_sleep: i2c1_pins_sleep { - mux { - pins = "gpio20", "gpio21"; - function = "gpio"; - }; - pinconf { - pins = "gpio20", "gpio21"; - drive-strength = <2>; - bias-disable; - }; - }; - - gsbi1_uart_2pins: gsbi1_uart_2pins { - mux { - pins = "gpio18", "gpio19"; - function = "gsbi1"; - }; - }; - - gsbi1_uart_4pins: gsbi1_uart_4pins { - mux { - pins = "gpio18", "gpio19", "gpio20", "gpio21"; - function = "gsbi1"; - }; - }; - - i2c2_pins: i2c2 { - mux { - pins = "gpio24", "gpio25"; - function = "gsbi2"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c2_pins_sleep: i2c2_pins_sleep { - mux { - pins = "gpio24", "gpio25"; - function = "gpio"; - }; - - pinconf { - pins = "gpio24", "gpio25"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c3_pins: i2c3 { - mux { - pins = "gpio8", "gpio9"; - function = "gsbi3"; - }; - - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c3_pins_sleep: i2c3_pins_sleep { - mux { - pins = "gpio8", "gpio9"; - function = "gpio"; - }; - pinconf { - pins = "gpio8", "gpio9"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c4_pins: i2c4 { - mux { - pins = "gpio12", "gpio13"; - function = "gsbi4"; - }; - - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c4_pins_sleep: i2c4_pins_sleep { - mux { - pins = "gpio12", "gpio13"; - function = "gpio"; - }; - pinconf { - pins = "gpio12", "gpio13"; - drive-strength = <2>; - bias-disable; - }; - }; - - spi5_default: spi5_default { - pinmux { - pins = "gpio51", "gpio52", "gpio54"; - function = "gsbi5"; - }; - - pinmux_cs { - function = "gpio"; - pins = "gpio53"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio54"; - drive-strength = <16>; - bias-disable; - }; - - pinconf_cs { - pins = "gpio53"; - drive-strength = <16>; - bias-disable; - output-high; - }; - }; - - spi5_sleep: spi5_sleep { - pinmux { - function = "gpio"; - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - }; - - pinconf { - pins = "gpio51", "gpio52", "gpio53", "gpio54"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - i2c6_pins: i2c6 { - mux { - pins = "gpio16", "gpio17"; - function = "gsbi6"; - }; - - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <16>; - bias-disable; - }; - }; - - i2c6_pins_sleep: i2c6_pins_sleep { - mux { - pins = "gpio16", "gpio17"; - function = "gpio"; - }; - pinconf { - pins = "gpio16", "gpio17"; - drive-strength = <2>; - bias-disable; - }; + gsbi1_uart_4pins: gsbi1-uart-4pins-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gsbi1"; }; gsbi4_uart_pin_a: gsbi4-uart-pin-active-state { @@ -249,70 +72,147 @@ }; }; - gsbi6_uart_2pins: gsbi6_uart_2pins { - mux { - pins = "gpio14", "gpio15"; - function = "gsbi6"; - }; + gsbi6_uart_2pins: gsbi6-uart-2pins-state { + pins = "gpio14", "gpio15"; + function = "gsbi6"; }; - gsbi6_uart_4pins: gsbi6_uart_4pins { - mux { - pins = "gpio14", "gpio15", "gpio16", "gpio17"; - function = "gsbi6"; - }; + gsbi6_uart_4pins: gsbi6-uart-4pins-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "gsbi6"; }; - gsbi7_uart_2pins: gsbi7_uart_2pins { - mux { - pins = "gpio82", "gpio83"; - function = "gsbi7"; - }; + gsbi7_uart_2pins: gsbi7-uart-2pins-state { + pins = "gpio82", "gpio83"; + function = "gsbi7"; }; - gsbi7_uart_4pins: gsbi7_uart_4pins { - mux { - pins = "gpio82", "gpio83", "gpio84", "gpio85"; - function = "gsbi7"; - }; + gsbi7_uart_4pins: gsbi7_uart_4pins-state { + pins = "gpio82", "gpio83", "gpio84", "gpio85"; + function = "gsbi7"; }; - i2c7_pins: i2c7 { - mux { - pins = "gpio84", "gpio85"; - function = "gsbi7"; - }; + i2c1_default_state: i2c1-default-state { + pins = "gpio20", "gpio21"; + function = "gsbi1"; + drive-strength = <16>; + bias-disable; + }; - pinconf { - pins = "gpio84", "gpio85"; + i2c1_sleep_state: i2c1-sleep-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c2_default_state: i2c2-default-state { + pins = "gpio24", "gpio25"; + function = "gsbi2"; + drive-strength = <16>; + bias-disable; + }; + + i2c2_sleep_state: i2c2-sleep-state { + pins = "gpio24", "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c3_default_state: i2c3-default-state { + pins = "gpio8", "gpio9"; + function = "gsbi3"; + drive-strength = <16>; + bias-disable; + }; + + i2c3_sleep_state: i2c3-sleep-state { + pins = "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c4_default_state: i2c4-default-state { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <16>; + bias-disable; + }; + + i2c4_sleep_state: i2c4-sleep-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c6_default_state: i2c6-default-state { + pins = "gpio16", "gpio17"; + function = "gsbi6"; + drive-strength = <16>; + bias-disable; + }; + + i2c6_sleep_state: i2c6-sleep-state { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c7_default_state: i2c7-default-state { + pins = "gpio84", "gpio85"; + function = "gsbi7"; + drive-strength = <16>; + bias-disable; + }; + + i2c7_sleep_state: i2c7-sleep-state { + pins = "gpio84", "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi5_default_state: spi5-default-state { + spi5-pins { + pins = "gpio51", "gpio52", "gpio54"; + function = "gsbi5"; drive-strength = <16>; bias-disable; }; - }; - i2c7_pins_sleep: i2c7_pins_sleep { - mux { - pins = "gpio84", "gpio85"; + spi5-cs-pins { + pins = "gpio53"; function = "gpio"; - }; - pinconf { - pins = "gpio84", "gpio85"; - drive-strength = <2>; + drive-strength = <16>; bias-disable; + output-high; }; }; - riva_fm_pin_a: riva-fm-active { + spi5_sleep_state: spi5-sleep-state { + spi5-pins { + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + riva_fm_pin_a: riva-fm-active-state { pins = "gpio14", "gpio15"; function = "riva_fm"; }; - riva_bt_pin_a: riva-bt-active { + riva_bt_pin_a: riva-bt-active-state { pins = "gpio16", "gpio17"; function = "riva_bt"; }; - riva_wlan_pin_a: riva-wlan-active { + riva_wlan_pin_a: riva-wlan-active-state { pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; function = "riva_wlan"; @@ -320,22 +220,24 @@ bias-pull-down; }; - hdmi_pinctrl: hdmi-pinctrl { - mux { - pins = "gpio70", "gpio71", "gpio72"; - function = "hdmi"; - }; - - pinconf_ddc { + hdmi_pinctrl: hdmi-pinctrl-state { + ddc-pins { pins = "gpio70", "gpio71"; + function = "hdmi"; bias-pull-up; drive-strength = <2>; }; - pinconf_hpd { + hpd-pins { pins = "gpio72"; + function = "hdmi"; bias-pull-down; drive-strength = <16>; }; }; + + ps_hold_default_state: ps-hold-default-state { + pins = "gpio78"; + function = "ps_hold"; + }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts index 2412aa3e3e8d..7752f07973f9 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -373,21 +373,21 @@ cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>; + pinctrl-0 = <&sdcc3_default_state>, <&sdcc3_cd_pin_a>; status = "okay"; }; &tlmm_pinmux { - gsbi5_uart_pin_a: gsbi5-uart-pin-active { - rx { + gsbi5_uart_pin_a: gsbi5-uart-pin-active-state { + rx-pins { pins = "gpio52"; function = "gsbi5"; drive-strength = <2>; bias-pull-up; }; - tx { + tx-pins { pins = "gpio51"; function = "gsbi5"; drive-strength = <4>; @@ -396,7 +396,7 @@ }; - sdcc3_cd_pin_a: sdcc3-cd-pin-active { + sdcc3_cd_pin_a: sdcc3-cd-pin-active-state { pins = "gpio26"; function = "gpio"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 769e151747c3..00f273ffea9c 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -302,7 +302,7 @@ interrupts = ; pinctrl-names = "default"; - pinctrl-0 = <&ps_hold>; + pinctrl-0 = <&ps_hold_default_state>; }; sfpb_wrapper_mutex: syscon@1200000 { @@ -435,8 +435,8 @@ gsbi1_i2c: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c1_pins>; - pinctrl-1 = <&i2c1_pins_sleep>; + pinctrl-0 = <&i2c1_default_state>; + pinctrl-1 = <&i2c1_sleep_state>; pinctrl-names = "default", "sleep"; reg = <0x12460000 0x1000>; interrupts = ; @@ -465,8 +465,8 @@ gsbi2_i2c: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; - pinctrl-0 = <&i2c2_pins>; - pinctrl-1 = <&i2c2_pins_sleep>; + pinctrl-0 = <&i2c2_default_state>; + pinctrl-1 = <&i2c2_sleep_state>; pinctrl-names = "default", "sleep"; interrupts = ; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; @@ -489,8 +489,8 @@ ranges; gsbi3_i2c: i2c@16280000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c3_pins>; - pinctrl-1 = <&i2c3_pins_sleep>; + pinctrl-0 = <&i2c3_default_state>; + pinctrl-1 = <&i2c3_sleep_state>; pinctrl-names = "default", "sleep"; reg = <0x16280000 0x1000>; interrupts = ; @@ -528,8 +528,8 @@ gsbi4_i2c: i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c4_pins>; - pinctrl-1 = <&i2c4_pins_sleep>; + pinctrl-0 = <&i2c4_default_state>; + pinctrl-1 = <&i2c4_sleep_state>; pinctrl-names = "default", "sleep"; reg = <0x16380000 0x1000>; interrupts = ; @@ -565,8 +565,8 @@ compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; interrupts = ; - pinctrl-0 = <&spi5_default>; - pinctrl-1 = <&spi5_sleep>; + pinctrl-0 = <&spi5_default_state>; + pinctrl-1 = <&spi5_sleep_state>; pinctrl-names = "default", "sleep"; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -599,8 +599,8 @@ gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c6_pins>; - pinctrl-1 = <&i2c6_pins_sleep>; + pinctrl-0 = <&i2c6_default_state>; + pinctrl-1 = <&i2c6_sleep_state>; pinctrl-names = "default", "sleep"; reg = <0x16580000 0x1000>; interrupts = ; @@ -635,8 +635,8 @@ gsbi7_i2c: i2c@16680000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c7_pins>; - pinctrl-1 = <&i2c7_pins_sleep>; + pinctrl-0 = <&i2c7_default_state>; + pinctrl-1 = <&i2c7_sleep_state>; pinctrl-names = "default", "sleep"; reg = <0x16680000 0x1000>; interrupts = ; @@ -945,7 +945,7 @@ dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; - pinctrl-0 = <&sdc4_gpios>; + pinctrl-0 = <&sdc4_default_state>; }; sdcc4bam: dma-controller@121c2000 { @@ -962,7 +962,7 @@ status = "disabled"; compatible = "arm,pl18x", "arm,primecell"; pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; + pinctrl-0 = <&sdcc1_default_state>; arm,primecell-periphid = <0x00051180>; reg = <0x12400000 0x2000>; interrupts = ; From de52c020e1a9c3313d88405a4545020b1f5ab24d Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Thu, 11 Jul 2024 12:01:41 +0100 Subject: [PATCH 05/14] ARM: dts: qcom: ipq8064: adhere to pinctrl dtschema Pass dtbs_check for qcom,ipq8064-pinctrl.yaml. Also remove invalid "bias-none" property, which I have assumed to mean "bias-disable". Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240711110545.31641-6-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts | 11 +- .../arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts | 76 +++++------- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 114 ++++++++---------- 3 files changed, 87 insertions(+), 114 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts index a654d3c22c4f..5a8bf1a6f559 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts @@ -7,12 +7,11 @@ soc { pinmux@800000 { - buttons_pins: buttons_pins { - mux { - pins = "gpio54", "gpio65"; - drive-strength = <2>; - bias-pull-up; - }; + buttons_pins: buttons-state { + pins = "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts index 12e806adcda8..f09da9460c86 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -404,59 +404,49 @@ }; &qcom_pinmux { - buttons_pins: buttons_pins { - mux { - pins = "gpio66"; - drive-strength = <16>; - bias-disable; - }; + buttons_pins: buttons-state { + pins = "gpio66"; + function = "gpio"; + drive-strength = <16>; + bias-disable; }; - leds_pins: leds_pins { - mux { - pins = "gpio33"; - drive-strength = <16>; - bias-disable; - }; + leds_pins: leds-state { + pins = "gpio33"; + function = "gpio"; + drive-strength = <16>; + bias-disable; }; - mdio1_pins: mdio1_pins { - mux { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; + mdio1_pins: mdio1-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <8>; + bias-disable; }; - sw0_reset_pin: sw0_reset_pin { - mux { - pins = "gpio16"; - drive-strength = <16>; - function = "gpio"; - bias-disable; - input-disable; - }; + sw0_reset_pin: sw0-reset-state { + pins = "gpio16"; + drive-strength = <16>; + function = "gpio"; + bias-disable; + input-disable; }; - sw1_reset_pin: sw1_reset_pin { - mux { - pins = "gpio17"; - drive-strength = <16>; - function = "gpio"; - bias-disable; - input-disable; - }; + sw1_reset_pin: sw1-reset-state { + pins = "gpio17"; + drive-strength = <16>; + function = "gpio"; + bias-disable; + input-disable; }; - usb1_pwr_en_pins: usb1_pwr_en_pins { - mux { - pins = "gpio4"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-high; - }; + usb1_pwr_en_pins: usb1-pwr-en-state { + pins = "gpio4"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index da0fd75f4711..9adefc88c5b4 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -399,70 +399,58 @@ #interrupt-cells = <2>; interrupts = ; - pcie0_pins: pcie0_pinmux { - mux { - pins = "gpio3"; - function = "pcie1_rst"; - drive-strength = <12>; - bias-disable; - }; + pcie0_pins: pcie0-state { + pins = "gpio3"; + function = "pcie1_rst"; + drive-strength = <12>; + bias-disable; }; - pcie1_pins: pcie1_pinmux { - mux { - pins = "gpio48"; - function = "pcie2_rst"; - drive-strength = <12>; - bias-disable; - }; + pcie1_pins: pcie1-state { + pins = "gpio48"; + function = "pcie2_rst"; + drive-strength = <12>; + bias-disable; }; - pcie2_pins: pcie2_pinmux { - mux { - pins = "gpio63"; - function = "pcie3_rst"; - drive-strength = <12>; - bias-disable; - }; + pcie2_pins: pcie2-state { + pins = "gpio63"; + function = "pcie3_rst"; + drive-strength = <12>; + bias-disable; }; - i2c4_pins: i2c4-default { + i2c4_pins: i2c4-state { pins = "gpio12", "gpio13"; function = "gsbi4"; drive-strength = <12>; bias-disable; }; - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; - function = "gsbi5"; - drive-strength = <10>; - bias-none; - }; + spi_pins: spi-state { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-disable; }; - leds_pins: leds_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", - "gpio26", "gpio53"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; + leds_pins: leds-state { + pins = "gpio7", "gpio8", "gpio9", + "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; }; - buttons_pins: buttons_pins { - mux { - pins = "gpio54"; - drive-strength = <2>; - bias-pull-up; - }; + buttons_pins: buttons-state { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; }; - nand_pins: nand_pins { - mux { + nand_pins: nand-state { + nand-pins { pins = "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", @@ -473,14 +461,14 @@ bias-disable; }; - pullups { + nand-pullup-pins { pins = "gpio39"; function = "nand"; drive-strength = <10>; bias-pull-up; }; - hold { + nand-hold-pins { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47"; @@ -490,25 +478,21 @@ }; }; - mdio0_pins: mdio0-pins { - mux { - pins = "gpio0", "gpio1"; - function = "mdio"; - drive-strength = <8>; - bias-disable; - }; + mdio0_pins: mdio0-state { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <8>; + bias-disable; }; - rgmii2_pins: rgmii2-pins { - mux { - pins = "gpio27", "gpio28", "gpio29", - "gpio30", "gpio31", "gpio32", - "gpio51", "gpio52", "gpio59", - "gpio60", "gpio61", "gpio62"; - function = "rgmii2"; - drive-strength = <8>; - bias-disable; - }; + rgmii2_pins: rgmii2-state { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; }; }; From 268a968ef946ccce45be7c01bf915dddce7208c9 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Thu, 11 Jul 2024 12:01:42 +0100 Subject: [PATCH 06/14] ARM: dts: qcom: ipq4019: adhere to pinctrl dtschema Pass dtbs_check for qcom,ipq4019-pinctrl.yaml. Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240711110545.31641-7-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 34 ++++++++----------- .../boot/dts/qcom/qcom-ipq4018-jalapeno.dts | 27 ++++++--------- .../boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi | 26 +++++--------- .../boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 14 ++++---- .../dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts | 8 ++--- .../dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts | 2 +- .../boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi | 6 ++-- 7 files changed, 50 insertions(+), 67 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index da67d55fa557..0d23c03fae33 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -28,46 +28,42 @@ }; &tlmm { - i2c0_pins: i2c0_pinmux { - mux_i2c { - function = "blsp_i2c0"; - pins = "gpio58", "gpio59"; - drive-strength = <16>; - bias-disable; - }; + i2c0_pins: i2c0-state { + function = "blsp_i2c0"; + pins = "gpio58", "gpio59"; + drive-strength = <16>; + bias-disable; }; - mdio_pins: mdio_pinmux { - mux_mdio { + mdio_pins: mdio-state { + mdio-pins { pins = "gpio53"; function = "mdio"; bias-pull-up; }; - mux_mdc { + mdc-pins { pins = "gpio52"; function = "mdc"; bias-pull-up; }; }; - serial0_pins: serial0_pinmux { - mux_uart { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; + serial0_pins: serial0-state { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; }; - spi0_pins: spi0_pinmux { - mux_spi { + spi0_pins: spi0-state { + spi0-pins { function = "blsp_spi0"; pins = "gpio55", "gpio56", "gpio57"; drive-strength = <12>; bias-disable; }; - mux_cs { + spi0-cs-pins { function = "gpio"; pins = "gpio54", "gpio4"; drive-strength = <2>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts index 365fbac417fd..ac3b30072a22 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -11,40 +11,35 @@ }; &tlmm { - mdio_pins: mdio_pinmux { - pinmux_1 { + mdio_pins: mdio-state { + mdio-pins { pins = "gpio53"; function = "mdio"; + bias-pull-up; }; - pinmux_2 { + mdc-pins { pins = "gpio52"; function = "mdc"; - }; - - pinconf { - pins = "gpio52", "gpio53"; bias-pull-up; }; }; - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; + serial_pins: serial-state{ + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; }; - spi_0_pins: spi_0_pinmux { - pin { + spi_0_pins: spi-0-state { + spi0-pins { function = "blsp_spi0"; pins = "gpio55", "gpio56", "gpio57"; drive-strength = <2>; bias-disable; }; - pin_cs { + spi0-cs-pins { function = "gpio"; pins = "gpio54", "gpio59"; drive-strength = <2>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi index f7ac8f9d0b6f..efbe89dd4793 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk01.1.dtsi @@ -34,30 +34,22 @@ }; &tlmm { - serial_pins: serial_pinmux { - mux { - pins = "gpio60", "gpio61"; - function = "blsp_uart0"; - bias-disable; - }; + serial_pins: serial-state { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; }; - spi_0_pins: spi_0_pinmux { - pinmux { + spi_0_pins: spi-0-state { + spi0-pins { + pins = "gpio55", "gpio56", "gpio57"; function = "blsp_spi0"; - pins = "gpio55", "gpio56", "gpio57"; - }; - pinmux_cs { - function = "gpio"; - pins = "gpio54"; - }; - pinconf { - pins = "gpio55", "gpio56", "gpio57"; drive-strength = <12>; bias-disable; }; - pinconf_cs { + spi0-cs-pins { pins = "gpio54"; + function = "gpio"; drive-strength = <2>; bias-disable; output-high; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi index 374af6dd360a..91e296d2ea82 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi @@ -24,26 +24,26 @@ soc { pinctrl@1000000 { - serial_0_pins: serial0-pinmux { + serial_0_pins: serial0-state { pins = "gpio16", "gpio17"; function = "blsp_uart0"; bias-disable; }; - serial_1_pins: serial1-pinmux { + serial_1_pins: serial1-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "blsp_uart1"; bias-disable; }; - spi_0_pins: spi-0-pinmux { - pinmux { + spi_0_pins: spi-0-state { + spi0-pins { function = "blsp_spi0"; pins = "gpio13", "gpio14", "gpio15"; bias-disable; }; - pinmux_cs { + spi0-cs-pins { function = "gpio"; pins = "gpio12"; bias-disable; @@ -51,13 +51,13 @@ }; }; - i2c_0_pins: i2c-0-pinmux { + i2c_0_pins: i2c-0-state { pins = "gpio20", "gpio21"; function = "blsp_i2c0"; bias-disable; }; - nand_pins: nand-pins { + nand_pins: nand-state { pins = "gpio53", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio62", "gpio63", diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts index ea2987fcbff8..41c5874f6f97 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c1.dts @@ -19,20 +19,20 @@ }; pinctrl@1000000 { - serial_1_pins: serial1-pinmux { + serial_1_pins: serial1-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "blsp_uart1"; bias-disable; }; - spi_0_pins: spi-0-pinmux { - pinmux { + spi_0_pins: spi-0-state { + spi0-pins { function = "blsp_spi0"; pins = "gpio13", "gpio14", "gpio15"; bias-disable; }; - pinmux_cs { + spio-cs-pins { function = "gpio"; pins = "gpio12"; bias-disable; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts index bd3553dd2070..67ee99d69757 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1-c2.dts @@ -9,7 +9,7 @@ soc { pinctrl@1000000 { - serial_1_pins: serial1-pinmux { + serial_1_pins: serial1-state { pins = "gpio8", "gpio9"; function = "blsp_uart1"; bias-disable; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi index 7ef635997efa..cc88cf5f0d9b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk07.1.dtsi @@ -24,19 +24,19 @@ soc { pinctrl@1000000 { - serial_0_pins: serial0-pinmux { + serial_0_pins: serial0-state { pins = "gpio16", "gpio17"; function = "blsp_uart0"; bias-disable; }; - i2c_0_pins: i2c-0-pinmux { + i2c_0_pins: i2c-0-state { pins = "gpio20", "gpio21"; function = "blsp_i2c0"; bias-disable; }; - nand_pins: nand-pins { + nand_pins: nand-state { pins = "gpio53", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio62", "gpio63", From 56080a49773935fb899c6559c390a5f8439b5632 Mon Sep 17 00:00:00 2001 From: Bingwu Zhang Date: Mon, 15 Jul 2024 20:22:01 +0800 Subject: [PATCH 07/14] ARM: dts: qcom: msm8974pro-samsung-klte: Add pstore node Add pstore node to allow for retrieving crash logs. Signed-off-by: Bingwu Zhang Link: https://lore.kernel.org/r/20240715122201.345426-2-xtex@envs.net Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +- .../qcom/qcom-msm8974pro-samsung-klte-common.dtsi | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 15568579459a..19c12686831b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -149,7 +149,7 @@ }; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi index b5443fd5b425..d3959741d2ea 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi @@ -438,6 +438,19 @@ }; }; +&reserved_memory { + ramoops@3e8e0000 { + compatible = "ramoops"; + reg = <0x3e8e0000 0x200000>; + + console-size = <0x100000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x80000>; + ecc-size = <8>; + }; +}; + &remoteproc_adsp { status = "okay"; cx-supply = <&pma8084_s2>; From 89721c0e5bf14e06dea2b42ab5efdff4bf035f83 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Mon, 15 Jul 2024 14:01:07 +0100 Subject: [PATCH 08/14] ARM: dts: qcom: apq8064: drop reg-names on sata-phy node Remove the reg-names property in the sata-phy node as it is not present in the bindings and is not required by the driver. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240715130854.53501-3-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 00f273ffea9c..0d45ecfc5ba7 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -871,7 +871,6 @@ compatible = "qcom,apq8064-sata-phy"; status = "disabled"; reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; clocks = <&gcc SATA_PHY_CFG_CLK>; clock-names = "cfg"; #phy-cells = <0>; From 440c3fdbfa7d9a244351a66595d844e64d171640 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Wed, 17 Jul 2024 10:49:14 +0100 Subject: [PATCH 09/14] ARM: dts: qcom: {a,i}pq8064: correct clock-names in sata node Correct the clock-names in the AHCI SATA controller node to adhere to the bindings. Signed-off-by: Rayyan Ansari Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240717094914.17931-2-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 0d45ecfc5ba7..ac7494ed633e 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -889,9 +889,9 @@ <&gcc SATA_PMALIVE_CLK>; clock-names = "slave_iface", "iface", - "bus", + "core", "rxoob", - "core_pmalive"; + "pmalive"; assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 9adefc88c5b4..759a59c2bdbc 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -1276,7 +1276,7 @@ <&gcc SATA_A_CLK>, <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_face", "iface", "core", + clock-names = "slave_iface", "iface", "core", "rxoob", "pmalive"; assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; From 02f2ddaa1a78cbebd4255f78260781b404225170 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 23:02:49 +0200 Subject: [PATCH 10/14] ARM: dts: qcom: msm8226: Add CPU frequency scaling support Add a node for the a7pll with its frequencies. With this we can use the apcs-kpss-global driver for the apcs node and use the apcs to scale the CPU frequency according to the opp-table. At the same time unfortunately we need to provide the gcc node xo_board instead of the XO via rpmcc since otherwise we'll have a circular dependency between apcs, gcc and the rpm. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-5-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 103 ++++++++++++++++++++++- 1 file changed, 100 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index b2f92ad6499a..f0086000be3c 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -44,6 +44,8 @@ device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; }; @@ -54,6 +56,8 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; }; @@ -64,6 +68,8 @@ device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; }; @@ -74,6 +80,8 @@ device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + clocks = <&apcs>; + operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; }; @@ -98,6 +106,29 @@ reg = <0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + }; + + /* Higher CPU frequencies need speedbin support */ + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = ; }; - apcs: syscon@f9011000 { - compatible = "syscon"; + apcs: mailbox@f9011000 { + compatible = "qcom,msm8226-apcs-kpss-global", + "qcom,msm8916-apcs-kpss-global", "syscon"; reg = <0xf9011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a7pll>, <&gcc GPLL0_VOTE>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; + + a7pll: clock@f9016000 { + compatible = "qcom,msm8226-a7pll"; + reg = <0xf9016000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + operating-points-v2 = <&a7pll_opp_table>; + + a7pll_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + }; + + opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + }; + + opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + }; + + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; + }; + + opp-1689600000 { + opp-hz = /bits/ 64 <1689600000>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + }; + }; }; saw_l2: power-manager@f9012000 { @@ -571,7 +668,7 @@ #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + clocks = <&xo_board>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; From 807dfab845209062e4d268157cfbf0ba46652df7 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 23:02:50 +0200 Subject: [PATCH 11/14] ARM: dts: qcom: msm8226: Hook up CPU cooling Add cooling-maps for the CPU thermal zones so the driver can actually do something when the CPU temperature rises too much. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-6-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index f0086000be3c..73eb280b7865 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -48,6 +49,7 @@ operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -60,6 +62,7 @@ operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -72,6 +75,7 @@ operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -84,6 +88,7 @@ operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + #cooling-cells = <2>; }; L2: l2-cache { @@ -1256,6 +1261,16 @@ thermal-sensors = <&tsens 5>; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu_alert0: trip0 { temperature = <75000>; @@ -1277,6 +1292,16 @@ thermal-sensors = <&tsens 2>; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { cpu_alert1: trip0 { temperature = <75000>; From c47dd4a87160fd604577aca41ca8b3391b5c5d3e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 19 Jun 2024 23:02:51 +0200 Subject: [PATCH 12/14] ARM: dts: qcom: msm8226: Convert APCS usages to mbox interface Since we now have the apcs set up as a mailbox provider, let's use the interface for all drivers where possible. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-7-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 73eb280b7865..4b820ccda64b 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -157,7 +157,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -235,7 +235,7 @@ interrupt-parent = <&intc>; interrupts = ; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -1232,7 +1232,7 @@ smd-edge { interrupts = ; - qcom,ipc = <&apcs 8 8>; + mboxes = <&apcs 8>; qcom,smd-edge = <1>; label = "lpass"; From 18042ad9dfd01d247407bb0721c6338eb8a9a2ac Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Sun, 14 Jul 2024 18:33:05 +0100 Subject: [PATCH 13/14] ARM: dts: qcom: msm8226-microsoft-common: Add inertial sensors Add nodes for the Asahi Kasei AK09911 magnetometer and the Kionix KX022-1020 accelerometer, both of which are connected over i2c2, in the common device tree for msm8x26 Lumias. Moneypenny (Lumia 630) does not have a magnetometer, and so the node is deleted. Tesla's (Lumia 830's) magnetometer is currently unknown. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240714173431.54332-4-rayyan@ansari.sh Signed-off-by: Bjorn Andersson --- .../qcom/qcom-msm8226-microsoft-common.dtsi | 26 +++++++++++++++++++ .../qcom-msm8226-microsoft-moneypenny.dts | 3 +++ .../dts/qcom/qcom-msm8926-microsoft-tesla.dts | 3 +++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi index 8839b23fc693..ca76bf8af75e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-common.dtsi @@ -84,6 +84,32 @@ }; }; +&blsp1_i2c2 { + status = "okay"; + + magnetometer: magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + + vdd-supply = <&pm8226_l15>; + vid-supply = <&pm8226_l6>; + }; + + accelerometer: accelerometer@1e { + compatible = "kionix,kx022-1020"; + reg = <0x1e>; + + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8226_l15>; + vddio-supply = <&pm8226_l6>; + + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; +}; + &blsp1_i2c5 { status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts index 992b7115b5f8..a28a83cb5340 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-microsoft-moneypenny.dts @@ -10,6 +10,9 @@ #include "qcom-msm8226-microsoft-common.dtsi" +/* This device has no magnetometer */ +/delete-node/ &magnetometer; + / { model = "Nokia Lumia 630"; compatible = "microsoft,moneypenny", "qcom,msm8226"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts index 53a6d4e85959..55077a5f2e34 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-microsoft-tesla.dts @@ -13,6 +13,9 @@ /* This device has touchscreen on i2c1 instead */ /delete-node/ &touchscreen; +/* The magnetometer used on this device is currently unknown */ +/delete-node/ &magnetometer; + / { model = "Nokia Lumia 830"; compatible = "microsoft,tesla", "qcom,msm8926", "qcom,msm8226"; From a11a87a9a66e5ec1213c712ae681dbda37c2b1b8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 29 Jul 2024 22:52:17 +0300 Subject: [PATCH 14/14] ARM: dts: qcom: add generic compat string to RPM glink channels Add the generic qcom,smd-rpm compatible to RPM nodes to follow the schema. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240729-fix-smd-rpm-v2-4-0776408a94c5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 2b52e5d5eb51..014e6c5ee889 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -792,7 +792,7 @@ qcom,smd-edge = <15>; rpm-requests { - compatible = "qcom,rpm-apq8084"; + compatible = "qcom,rpm-apq8084", "qcom,smd-rpm"; qcom,smd-channels = "rpm_requests"; regulators-0 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 4b820ccda64b..3a685ff7e8cc 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -161,7 +161,7 @@ qcom,smd-edge = <15>; rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8226"; + compatible = "qcom,rpm-msm8226", "qcom,smd-rpm"; qcom,smd-channels = "rpm_requests"; rpmcc: clock-controller { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 19c12686831b..1bd87170252d 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -136,7 +136,7 @@ qcom,smd-edge = <15>; rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8974"; + compatible = "qcom,rpm-msm8974", "qcom,smd-rpm"; qcom,smd-channels = "rpm_requests"; rpmcc: clock-controller {