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Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6

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This commit is contained in:
Roland Dreier
2005-10-28 15:50:51 -07:00
parent 70a30e16a8 20731945ae
commit a4da0628ef
1055 changed files with 36394 additions and 19510 deletions
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include/asm-alpha/atomic.h
+2
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@@ -1,6 +1,8 @@
#ifndef _ALPHA_ATOMIC_H
#define _ALPHA_ATOMIC_H
#include <asm/barrier.h>
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc...
include/asm-alpha/barrier.h
+34
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@@ -0,0 +1,34 @@
#ifndef __BARRIER_H
#define __BARRIER_H
#define mb() \
__asm__ __volatile__("mb": : :"memory")
#define rmb() \
__asm__ __volatile__("mb": : :"memory")
#define wmb() \
__asm__ __volatile__("wmb": : :"memory")
#define read_barrier_depends() \
__asm__ __volatile__("mb": : :"memory")
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#endif
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
#define set_wmb(var, value) \
do { var = value; wmb(); } while (0)
#endif /* __BARRIER_H */
include/asm-alpha/dma-mapping.h
+1 -1
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@@ -31,7 +31,7 @@
#else /* no PCI - no IOMMU. */
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int gfp);
dma_addr_t *dma_handle, gfp_t gfp);
int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction);
include/asm-alpha/system.h
+1 -30
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@@ -4,6 +4,7 @@
#include <linux/config.h>
#include <asm/pal.h>
#include <asm/page.h>
#include <asm/barrier.h>
/*
* System defines.. Note that this is included both from .c and .S
@@ -139,36 +140,6 @@ extern void halt(void) __attribute__((noreturn));
struct task_struct;
extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*);
#define mb() \
__asm__ __volatile__("mb": : :"memory")
#define rmb() \
__asm__ __volatile__("mb": : :"memory")
#define wmb() \
__asm__ __volatile__("wmb": : :"memory")
#define read_barrier_depends() \
__asm__ __volatile__("mb": : :"memory")
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() barrier()
#endif
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
#define set_wmb(var, value) \
do { var = value; wmb(); } while (0)
#define imb() \
__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
include/asm-arm/arch-aaec2000/aaec2000.h
+56
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@@ -17,6 +17,16 @@
#error You must include hardware.h not this file
#endif /* __ASM_ARCH_HARDWARE_H */
/* Chip selects */
#define AAEC_CS0 0x00000000
#define AAEC_CS1 0x10000000
#define AAEC_CS2 0x20000000
#define AAEC_CS3 0x30000000
/* Flash */
#define AAEC_FLASH_BASE AAEC_CS0
#define AAEC_FLASH_SIZE SZ_64M
/* Interrupt controller */
#define IRQ_BASE __REG(0x80000500)
#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
@@ -148,4 +158,50 @@
#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
/* GPIO Registers */
#define AAEC_GPIO_PHYS 0x80000e00
#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)
#define AAEC_GPIO_PINMUX_PE0CON (1 << 0)
#define AAEC_GPIO_PINMUX_PD0CON (1 << 1)
#define AAEC_GPIO_PINMUX_CODECON (1 << 2)
#define AAEC_GPIO_PINMUX_UART3CON (1 << 3)
/* LCD Controller */
#define AAEC_CLCD_PHYS 0x80003000
#endif /* __ARM_ARCH_AAEC2000_H */
include/asm-arm/arch-aaec2000/aaed2000.h
+40
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@@ -0,0 +1,40 @@
/*
* linux/include/asm-arm/arch-aaec2000/aaed2000.h
*
* AAED-2000 specific bits definition
*
* Copyright (c) 2005 Nicolas Bellido Y Ortega
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_AAED2000_H
#define __ASM_ARCH_AAED2000_H
/* External GPIOs. */
#define EXT_GPIO_PBASE AAEC_CS3
#define EXT_GPIO_VBASE 0xf8100000
#define EXT_GPIO_LENGTH 0x00001000
#define __ext_gpio_p2v(x) ((x) - EXT_GPIO_PBASE + EXT_GPIO_VBASE)
#define __ext_gpio_v2p(x) ((x) + EXT_GPIO_PBASE - EXT_GPIO_VBASE)
#define __EXT_GPIO_REG(x) (*((volatile u32 *)__ext_gpio_p2v(x)))
#define __EXT_GPIO_PREG(x) (__ext_gpio_v2p((u32)&(x)))
#define AAED_EXT_GPIO __EXT_GPIO_REG(EXT_GPIO_PBASE)
#define AAED_EGPIO_KBD_SCAN 0x00003fff /* Keyboard scan data */
#define AAED_EGPIO_PWR_INT 0x00008fff /* Smart battery charger interrupt */
#define AAED_EGPIO_SWITCHED 0x000f0000 /* DIP Switches */
#define AAED_EGPIO_USB_VBUS 0x00400000 /* USB Vbus sense */
#define AAED_EGPIO_LCD_PWR_EN 0x02000000 /* LCD and backlight PWR enable */
#define AAED_EGPIO_nLED0 0x20000000 /* LED 0 */
#define AAED_EGPIO_nLED1 0x20000000 /* LED 1 */
#define AAED_EGPIO_nLED2 0x20000000 /* LED 2 */
#endif /* __ARM_ARCH_AAED2000_H */
include/asm-arm/arch-aaec2000/hardware.h
+2 -1
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@@ -11,7 +11,8 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <linux/config.h>
#include <asm/sizes.h>
#include <asm/arch/aaec2000.h>
/* The kernel is loaded at physical address 0xf8000000.
* We map the IO space a bit after
include/asm-arm/arch-aaec2000/io.h
+2
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@@ -6,6 +6,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-cl7500/io.h
+2
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@@ -10,6 +10,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-clps711x/hardware.h
+117
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@@ -235,4 +235,121 @@
#define CEIVA_PB0_BLK_BTN (1<<0)
#endif // #if defined (CONFIG_ARCH_CEIVA)
#if defined (CONFIG_MACH_MP1000)
/* NOR FLASH */
#define MP1000_NIO_BASE 0xf9000000 /* virtual */
#define MP1000_NIO_START CS0_PHYS_BASE /* physical */
#define MP1000_NIO_SIZE 0x00400000
/* DSP Interface */
#define MP1000_DSP_BASE 0xfa000000 /* virtual */
#define MP1000_DSP_START CS1_PHYS_BASE /* physical */
#define MP1000_DSP_SIZE 0x00100000
/* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
#define MP1000_LIO_BASE 0xfb000000 /* virtual */
#define MP1000_LIO_START CS2_PHYS_BASE /* physical */
#define MP1000_LIO_SIZE 0x00100000
/* NAND FLASH */
#define MP1000_FIO_BASE 0xfc000000 /* virtual */
#define MP1000_FIO_START CS3_PHYS_BASE /* physical */
#define MP1000_FIO_SIZE 0x00800000
/* Ethernet */
#define MP1000_EIO_BASE 0xfd000000 /* virtual */
#define MP1000_EIO_START CS4_PHYS_BASE /* physical */
#define MP1000_EIO_SIZE 0x00100000
#define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
#define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
#define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
#define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
/* IDE */
#define MP1000_IDE_BASE 0xfe000000 /* virtual */
#define MP1000_IDE_START CS5_PHYS_BASE /* physical */
#define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
#define IRQ_HARDDISK IRQ_EINT2
/*
* IDE registers definition
*/
#define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
#define IDE_BASE_OFF (MP1000_IDE_BASE)
#define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
#define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
#define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
#define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
#define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
#define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
#define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
#define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
#define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
#define IDE_IRQ IRQ_EINT2
#define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
#define RTC_ALWAYS_BCD 0
/*
// Definitions of the bit fields in the HwPortA register for the
// MP1000 board.
*/
#define HwPortAKeyboardRow1 0x00000001
#define HwPortAKeyboardRow2 0x00000002
#define HwPortAKeyboardRow3 0x00000004
#define HwPortAKeyboardRow4 0x00000008
#define HwPortAKeyboardRow5 0x00000010
#define HwPortAKeyboardRow6 0x00000020
#define HwPortALCDEnable 0x00000040
#define HwPortAOffhook 0x00000080
/*
// Definitions of the bit fields in the HwPortB register for the
// MP1000 board.
*/
#define HwPortBL3Mode 0x00000001
#define HwPortBL3Clk 0x00000002
#define HwPortBSClk 0x00000001
#define HwPortBSData 0x00000002
#define HwPortBL3Data 0x00000004
#define HwPortBMute 0x00000008
#define HwPortBQD0 0x00000010
#define HwPortBQD1 0x00000020
#define HwPortBQD2 0x00000040
#define HwPortBQD3 0x00000080
/*
// Definitions of the bit fields in the HwPortD register for the
// MP1000 board.
*/
#define HwPortDLED1 0x00000001
#define HwPortDLED2 0x00000002
#define HwPortDLED3 0x00000004
#define HwPortDLED4 0x00000008
#define HwPortDLED5 0x00000010
#define HwPortDEECS 0x00000020
#define HwPortBRTS 0x00000040
#define HwPortBRI 0x00000080
/*
// Definitions of the bit fields in the HwPortE register for the
// MP1000 board.
*/
#define HwPortECLE 0x00000001
#define HwPortESepromDOut 0x00000001
#define HwPortEALE 0x00000002
#define HwPortESepromDIn 0x00000002
#define HwPortENANDCS 0x00000004
#define HwPortESepromCLK 0x00000004
#endif // #if defined (CONFIG_MACH_MP1000)
#endif
include/asm-arm/arch-clps711x/io.h
+2
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@@ -20,6 +20,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(a))
include/asm-arm/arch-clps711x/mp1000-seprom.h
+77
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@@ -0,0 +1,77 @@
#ifndef MP1000_SEPROM_H
#define MP1000_SEPROM_H
/*
* mp1000-seprom.h
*
*
* This file contains the Serial EEPROM definitions for the MP1000 board
*
* Copyright (C) 2005 Comdial Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define COMMAND_ERASE (0x1C0)
#define COMMAND_ERASE_ALL (0x120)
#define COMMAND_WRITE_DISABLE (0x100)
#define COMMAND_WRITE_ENABLE (0x130)
#define COMMAND_READ (0x180)
#define COMMAND_WRITE (0x140)
#define COMMAND_WRITE_ALL (0x110)
//
// Serial EEPROM data format
//
#define PACKED __attribute__ ((packed))
typedef struct _EEPROM {
union {
unsigned char eprom_byte_data[128];
unsigned short eprom_short_data[64];
struct {
unsigned char version PACKED; // EEPROM Version "1" for now
unsigned char box_id PACKED; // Box ID (Standalone, SOHO, embedded, etc)
unsigned char major_hw_version PACKED; // Major Hardware version (Hex)
unsigned char minor_hw_version PACKED; // Minor Hardware Version (Hex)
unsigned char mfg_id[3] PACKED; // Manufacturer ID (3 character Alphabetic)
unsigned char mfg_serial_number[10] PACKED; // Manufacturer Serial number
unsigned char mfg_date[3] PACKED; // Date of Mfg (Formatted YY:MM:DD)
unsigned char country PACKED; // Country of deployment
unsigned char mac_Address[6] PACKED; // MAC Address
unsigned char oem_string[20] PACKED; // OEM ID string
unsigned short feature_bits1 PACKED; // Feature Bits 1
unsigned short feature_bits2 PACKED; // Feature Bits 2
unsigned char filler[75] PACKED; // Unused/Undefined “0” initialized
unsigned short checksum PACKED; // byte accumulated short checksum
} eprom_struct;
} variant;
} eeprom_struct;
/* These settings must be mutually exclusive */
#define FEATURE_BITS1_DRAMSIZE_16MEG 0x0001 /* 0 signifies 4 MEG system */
#define FEATURE_BITS1_DRAMSIZE_8MEG 0x0002 /* 1 in bit 1 = 8MEG system */
#define FEATURE_BITS1_DRAMSIZE_64MEG 0x0004 /* 1 in bit 2 = 64MEG system */
#define FEATURE_BITS1_CPUIS90MEG 0x0010
extern void seprom_init(void);
extern eeprom_struct* get_seprom_ptr(void);
extern unsigned char* get_eeprom_mac_address(void);
#endif /* MP1000_SEPROM_H */
include/asm-arm/arch-ebsa285/io.h
+2
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@@ -14,6 +14,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff
/*
include/asm-arm/arch-epxa10db/io.h
+2
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@@ -20,6 +20,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffff
include/asm-arm/arch-h720x/io.h
+1 -1
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@@ -14,7 +14,7 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/arch/hardware.h>
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
include/asm-arm/arch-imx/io.h
+2
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@@ -20,6 +20,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) ((void __iomem *)(a))
include/asm-arm/arch-integrator/hardware.h
-9
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@@ -33,15 +33,6 @@
#define IO_SIZE 0x0B000000 // How much?
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
/*
* Similar to above, but for PCI addresses (memory, IO, Config and the
* V3 chip itself). WARNING: this has to mirror definitions in platform.h
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define PCIO_BASE PCI_IO_VADDR
#define PCIMEM_BASE PCI_MEMORY_VADDR
include/asm-arm/arch-integrator/io.h
+8
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@@ -22,6 +22,14 @@
#define IO_SPACE_LIMIT 0xffff
/*
* WARNING: this has to mirror definitions in platform.h
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_pci(a) (a)
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
include/asm-arm/arch-iop3xx/io.h
+2
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@@ -11,6 +11,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)(p))
include/asm-arm/arch-ixp2000/io.h
+2
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@@ -15,6 +15,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __mem_pci(a) (a)
include/asm-arm/arch-ixp2000/ixp2000-regs.h
+43
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@@ -392,4 +392,47 @@
#define WDT_RESET_ENABLE 0x01000000
/*
* MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
* units, but the registers that differ between the two don't overlap,
* so we can have one register list for both.
*/
#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
#endif /* _IXP2000_H_ */
include/asm-arm/arch-l7200/io.h
+1 -1
View File
@@ -10,7 +10,7 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/arch/hardware.h>
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
include/asm-arm/arch-lh7a40x/io.h
+2
View File
@@ -11,6 +11,8 @@
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/* No ISA or PCI bus on this machine. */
include/asm-arm/arch-omap/io.h
+2
View File
@@ -34,6 +34,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-pxa/hardware.h
+2 -2
View File
@@ -44,12 +44,12 @@
#ifndef __ASSEMBLY__
# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
/* With indexed regs we don't want to feed the index through io_p2v()
especially if it is a variable, otherwise horrible code will result. */
# define __REG2(x,y) \
(*(volatile unsigned long *)((unsigned long)&__REG(x) + (y)))
(*(volatile u32 *)((u32)&__REG(x) + (y)))
# define __PREG(x) (io_v2p((u32)&(x)))
include/asm-arm/arch-pxa/io.h
+2
View File
@@ -6,6 +6,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-pxa/irda.h
+17
View File
@@ -0,0 +1,17 @@
#ifndef ASMARM_ARCH_IRDA_H
#define ASMARM_ARCH_IRDA_H
/* board specific transceiver capabilities */
#define IR_OFF 1
#define IR_SIRMODE 2
#define IR_FIRMODE 4
struct pxaficp_platform_data {
int transceiver_cap;
void (*transceiver_mode)(struct device *dev, int mode);
};
extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
#endif
include/asm-arm/arch-pxa/pxa-regs.h
+40 -2
View File
@@ -326,6 +326,25 @@
#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Hardware UART (HWUART) */
#define HWUART HWRBR
#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
@@ -1013,14 +1032,12 @@
#define ICCR0_LBM (1 << 1) /* Loopback mode */
#define ICCR0_ITR (1 << 0) /* IrDA transmission */
#ifdef CONFIG_PXA27x
#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
#endif
#ifdef CONFIG_PXA27x
#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
@@ -1250,9 +1267,13 @@
#define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
#define GPIO41_FFRTS 41 /* FFUART request to send */
#define GPIO42_BTRXD 42 /* BTUART receive data */
#define GPIO42_HWRXD 42 /* HWUART receive data */
#define GPIO43_BTTXD 43 /* BTUART transmit data */
#define GPIO43_HWTXD 43 /* HWUART transmit data */
#define GPIO44_BTCTS 44 /* BTUART clear to send */
#define GPIO44_HWCTS 44 /* HWUART clear to send */
#define GPIO45_BTRTS 45 /* BTUART request to send */
#define GPIO45_HWRTS 45 /* HWUART request to send */
#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
#define GPIO46_ICPRXD 46 /* ICP receive data */
#define GPIO46_STRXD 46 /* STD_UART receive data */
@@ -1378,17 +1399,26 @@
#define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
#define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
#define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
#define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
@@ -1763,6 +1793,7 @@
#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */
#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */
@@ -2282,4 +2313,11 @@
#endif
/* PWRMODE register M field values */
#define PWRMODE_IDLE 0x1
#define PWRMODE_STANDBY 0x2
#define PWRMODE_SLEEP 0x3
#define PWRMODE_DEEPSLEEP 0x7
#endif
include/asm-arm/arch-pxa/uncompress.h
+1
View File
@@ -12,6 +12,7 @@
#define FFUART ((volatile unsigned long *)0x40100000)
#define BTUART ((volatile unsigned long *)0x40200000)
#define STUART ((volatile unsigned long *)0x40700000)
#define HWUART ((volatile unsigned long *)0x41600000)
#define UART FFUART
include/asm-arm/arch-rpc/io.h
+2
View File
@@ -13,6 +13,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-s3c2410/fb.h
+2 -1
View File
@@ -13,6 +13,7 @@
* 07-Sep-2004 RTP Created file
* 03-Nov-2004 BJD Updated and minor cleanups
* 03-Aug-2005 RTP Renamed to fb.h
* 26-Oct-2005 BJD Changed name of platdata init
*/
#ifndef __ASM_ARM_FB_H
@@ -64,6 +65,6 @@ struct s3c2410fb_mach_info {
unsigned long lpcsel;
};
void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
#endif /* __ASM_ARM_FB_H */
include/asm-arm/arch-s3c2410/io.h
+2
View File
@@ -15,6 +15,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/arch-s3c2410/regs-gpio.h
+6
View File
@@ -20,6 +20,7 @@
* 18-11-2004 BJD Added S3C2440 AC97 controls
* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
* 28-Mar-2005 LCVR Fixed definition of GPB10
* 26-Oct-2005 BJD Added generic configuration types
*/
@@ -43,6 +44,11 @@
/* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
#define S3C2410_GPIO_INPUT (0xFFFFFFF0)
#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
/* configure GPIO ports A..G */
include/asm-arm/arch-sa1100/hardware.h
-7
View File
@@ -21,13 +21,6 @@
#define UNCACHEABLE_ADDR 0xfa050000
/*
* We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for
* in*()/out*() macros to be usable for all cases.
*/
#define PCIO_BASE 0
/*
* SA1100 internal I/O mappings
*
include/asm-arm/arch-sa1100/io.h
+7 -1
View File
@@ -10,13 +10,19 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
* We don't actually have real ISA nor PCI buses, but there is so many
* drivers out there that might just work if we fake them...
*/
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)addr;
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
include/asm-arm/arch-sa1100/system.h
+1
View File
@@ -4,6 +4,7 @@
* Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
*/
#include <linux/config.h>
#include <asm/hardware.h>
static inline void arch_idle(void)
{
include/asm-arm/arch-shark/io.h
+2
View File
@@ -11,6 +11,8 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
/*
include/asm-arm/bitops.h
-1
View File
@@ -347,7 +347,6 @@ static inline unsigned long __ffs(unsigned long word)
* the clz instruction for much better code efficiency.
*/
static __inline__ int generic_fls(int x);
#define fls(x) \
( __builtin_constant_p(x) ? generic_fls(x) : \
({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
include/asm-arm/dma-mapping.h
+2 -2
View File
@@ -70,7 +70,7 @@ static inline int dma_mapping_error(dma_addr_t dma_addr)
* device-viewed address.
*/
extern void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
/**
* dma_free_coherent - free memory allocated by dma_alloc_coherent
@@ -117,7 +117,7 @@ int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
* device-viewed address.
*/
extern void *
dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp);
#define dma_free_writecombine(dev,size,cpu_addr,handle) \
dma_free_coherent(dev,size,cpu_addr,handle)
include/asm-arm/io.h
-1
View File
@@ -26,7 +26,6 @@
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/memory.h>
#include <asm/arch/hardware.h>
/*
* ISA I/O bus memory addresses are 1:1 with the physical address.
include/asm-arm/mach/arch.h
+3 -3
View File
@@ -48,10 +48,10 @@ struct machine_desc {
* Set of macros to define architecture features. This is built into
* a table by the linker.
*/
#define MACHINE_START(_type,_name) \
const struct machine_desc __mach_desc_##_type \
#define MACHINE_START(_type,_name) \
static const struct machine_desc __mach_desc_##_type \
__attribute__((__section__(".arch.info.init"))) = { \
.nr = MACH_TYPE_##_type, \
.nr = MACH_TYPE_##_type, \
.name = _name,
#define MACHINE_END \
include/asm-arm/mach/map.h
+4 -1
View File
@@ -11,7 +11,7 @@
*/
struct map_desc {
unsigned long virtual;
unsigned long physical;
unsigned long pfn;
unsigned long length;
unsigned int type;
};
@@ -27,6 +27,9 @@ struct meminfo;
#define MT_ROM 6
#define MT_IXP2000_DEVICE 7
#define __phys_to_pfn(paddr) (paddr >> PAGE_SHIFT)
#define __pfn_to_phys(pfn) (pfn << PAGE_SHIFT)
extern void create_memmap_holes(struct meminfo *);
extern void memtable_init(struct meminfo *);
extern void iotable_init(struct map_desc *, int);
include/asm-cris/dma-mapping.h
+2 -2
View File
@@ -15,14 +15,14 @@
#ifdef CONFIG_PCI
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
#else
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
BUG();
return NULL;
include/asm-frv/dma-mapping.h
+1 -1
View File
@@ -13,7 +13,7 @@
extern unsigned long __nongprelbss dma_coherent_mem_start;
extern unsigned long __nongprelbss dma_coherent_mem_end;
void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, int gfp);
void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp);
void dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle);
/*
include/asm-frv/pci.h
+1 -1
View File
@@ -32,7 +32,7 @@ extern void pcibios_set_master(struct pci_dev *dev);
extern void pcibios_penalize_isa_irq(int irq);
#ifdef CONFIG_MMU
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *dma_handle);
extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle);
extern void consistent_free(void *vaddr);
extern void consistent_sync(void *vaddr, size_t size, int direction);
extern void consistent_sync_page(struct page *page, unsigned long offset,
include/asm-generic/dma-mapping-broken.h
+1 -1
View File
@@ -6,7 +6,7 @@
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
BUG();
return NULL;
include/asm-ia64/machvec.h
+1 -1
View File
@@ -37,7 +37,7 @@ typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
/* DMA-mapping interface: */
typedef void ia64_mv_dma_init (void);
typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, int);
typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, gfp_t);
typedef void ia64_mv_dma_free_coherent (struct device *, size_t, void *, dma_addr_t);
typedef dma_addr_t ia64_mv_dma_map_single (struct device *, void *, size_t, int);
typedef void ia64_mv_dma_unmap_single (struct device *, dma_addr_t, size_t, int);
include/asm-m32r/dma-mapping.h
+1 -1
View File
@@ -8,7 +8,7 @@
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
return (void *)NULL;
}
include/asm-mips/dma-mapping.h
+2 -2
View File
@@ -5,13 +5,13 @@
#include <asm/cache.h>
void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_noncoherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
include/asm-mips/sgi/hpc3.h
+18 -18
View File
@@ -128,26 +128,26 @@ struct hpc3_ethregs {
volatile u32 rx_gfptr; /* current GIO fifo ptr */
volatile u32 rx_dfptr; /* current device fifo ptr */
u32 _unused1; /* padding */
volatile u32 rx_reset; /* reset register */
#define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
volatile u32 reset; /* reset register */
#define HPC3_ERST_CRESET 0x1 /* Reset dma channel and external controller */
#define HPC3_ERST_CLRIRQ 0x2 /* Clear channel interrupt */
#define HPC3_ERST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */
volatile u32 rx_dconfig; /* DMA configuration register */
#define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_ERXDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */
volatile u32 dconfig; /* DMA configuration register */
#define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_EDCFG_FEOP 0x04000 /* Bad packet marker timeout enable */
#define HPC3_EDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */
#define HPC3_EDCFG_PTO 0x30000 /* Programmed timeout value for above two */
volatile u32 rx_pconfig; /* PIO configuration register */
#define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
volatile u32 pconfig; /* PIO configuration register */
#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
u32 _unused2[0x1000/4 - 8]; /* padding */
include/asm-parisc/assembly.h
+63 -8
View File
@@ -21,7 +21,9 @@
#ifndef _PARISC_ASSEMBLY_H
#define _PARISC_ASSEMBLY_H
#ifdef __LP64__
#define CALLEE_FLOAT_FRAME_SIZE 80
#ifdef CONFIG_64BIT
#define LDREG ldd
#define STREG std
#define LDREGX ldd,s
@@ -30,8 +32,8 @@
#define SHRREG shrd
#define RP_OFFSET 16
#define FRAME_SIZE 128
#define CALLEE_SAVE_FRAME_SIZE 144
#else
#define CALLEE_REG_FRAME_SIZE 144
#else /* CONFIG_64BIT */
#define LDREG ldw
#define STREG stw
#define LDREGX ldwx,s
@@ -40,9 +42,11 @@
#define SHRREG shr
#define RP_OFFSET 20
#define FRAME_SIZE 64
#define CALLEE_SAVE_FRAME_SIZE 128
#define CALLEE_REG_FRAME_SIZE 128
#endif
#define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
#ifdef CONFIG_PA20
#define BL b,l
# ifdef CONFIG_64BIT
@@ -300,9 +304,35 @@
fldd,mb -8(\regs), %fr0
.endm
.macro callee_save_float
fstd,ma %fr12, 8(%r30)
fstd,ma %fr13, 8(%r30)
fstd,ma %fr14, 8(%r30)
fstd,ma %fr15, 8(%r30)
fstd,ma %fr16, 8(%r30)
fstd,ma %fr17, 8(%r30)
fstd,ma %fr18, 8(%r30)
fstd,ma %fr19, 8(%r30)
fstd,ma %fr20, 8(%r30)
fstd,ma %fr21, 8(%r30)
.endm
.macro callee_rest_float
fldd,mb -8(%r30), %fr21
fldd,mb -8(%r30), %fr20
fldd,mb -8(%r30), %fr19
fldd,mb -8(%r30), %fr18
fldd,mb -8(%r30), %fr17
fldd,mb -8(%r30), %fr16
fldd,mb -8(%r30), %fr15
fldd,mb -8(%r30), %fr14
fldd,mb -8(%r30), %fr13
fldd,mb -8(%r30), %fr12
.endm
#ifdef __LP64__
.macro callee_save
std,ma %r3, CALLEE_SAVE_FRAME_SIZE(%r30)
std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
mfctl %cr27, %r3
std %r4, -136(%r30)
std %r5, -128(%r30)
@@ -340,13 +370,13 @@
ldd -128(%r30), %r5
ldd -136(%r30), %r4
mtctl %r3, %cr27
ldd,mb -CALLEE_SAVE_FRAME_SIZE(%r30), %r3
ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
.endm
#else /* ! __LP64__ */
.macro callee_save
stw,ma %r3, CALLEE_SAVE_FRAME_SIZE(%r30)
stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
mfctl %cr27, %r3
stw %r4, -124(%r30)
stw %r5, -120(%r30)
@@ -384,7 +414,7 @@
ldw -120(%r30), %r5
ldw -124(%r30), %r4
mtctl %r3, %cr27
ldw,mb -CALLEE_SAVE_FRAME_SIZE(%r30), %r3
ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
.endm
#endif /* ! __LP64__ */
@@ -450,5 +480,30 @@
REST_CR (%cr22, PT_PSW (\regs))
.endm
/* First step to create a "relied upon translation"
* See PA 2.0 Arch. page F-4 and F-5.
*
* The ssm was originally necessary due to a "PCxT bug".
* But someone decided it needed to be added to the architecture
* and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
* It's been carried forward into PA 2.0 Arch as well. :^(
*
* "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
* rsm/ssm prevents the ifetch unit from speculatively fetching
* instructions past this line in the code stream.
* PA 2.0 processor will single step all insn in the same QUAD (4 insn).
*/
.macro pcxt_ssm_bug
rsm PSW_SM_I,%r0
nop /* 1 */
nop /* 2 */
nop /* 3 */
nop /* 4 */
nop /* 5 */
nop /* 6 */
nop /* 7 */
.endm
#endif /* __ASSEMBLY__ */
#endif
include/asm-parisc/bitops.h
+133 -159
View File
@@ -2,7 +2,7 @@
#define _PARISC_BITOPS_H
#include <linux/compiler.h>
#include <asm/spinlock.h>
#include <asm/types.h> /* for BITS_PER_LONG/SHIFT_PER_LONG */
#include <asm/byteorder.h>
#include <asm/atomic.h>
@@ -12,193 +12,157 @@
* to include/asm-i386/bitops.h or kerneldoc
*/
#ifdef __LP64__
# define SHIFT_PER_LONG 6
#ifndef BITS_PER_LONG
# define BITS_PER_LONG 64
#endif
#else
# define SHIFT_PER_LONG 5
#ifndef BITS_PER_LONG
# define BITS_PER_LONG 32
#endif
#endif
#define CHOP_SHIFTCOUNT(x) ((x) & (BITS_PER_LONG - 1))
#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
static __inline__ void set_bit(int nr, volatile unsigned long * address)
/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
* on use of volatile and __*_bit() (set/clear/change):
* *_bit() want use of volatile.
* __*_bit() are "relaxed" and don't use spinlock or volatile.
*/
static __inline__ void set_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long flags;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr |= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}
static __inline__ void __set_bit(int nr, volatile unsigned long * address)
static __inline__ void __set_bit(unsigned long nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
*addr |= mask;
*m |= 1UL << CHOP_SHIFTCOUNT(nr);
}
static __inline__ void clear_bit(int nr, volatile unsigned long * address)
static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
unsigned long flags;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr &= ~mask;
*addr &= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}
static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long * address)
static __inline__ void __clear_bit(unsigned long nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
*addr &= ~mask;
*m &= ~(1UL << CHOP_SHIFTCOUNT(nr));
}
static __inline__ void change_bit(int nr, volatile unsigned long * address)
static __inline__ void change_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long flags;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
_atomic_spin_lock_irqsave(addr, flags);
*addr ^= mask;
_atomic_spin_unlock_irqrestore(addr, flags);
}
static __inline__ void __change_bit(int nr, volatile unsigned long * address)
static __inline__ void __change_bit(unsigned long nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
unsigned long *m = (unsigned long *) addr + (nr >> SHIFT_PER_LONG);
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
*addr ^= mask;
*m ^= 1UL << CHOP_SHIFTCOUNT(nr);
}
static __inline__ int test_and_set_bit(int nr, volatile unsigned long * address)
static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
int oldbit;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long oldbit;
unsigned long flags;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
_atomic_spin_lock_irqsave(addr, flags);
oldbit = (*addr & mask) ? 1 : 0;
*addr |= mask;
oldbit = *addr;
*addr = oldbit | mask;
_atomic_spin_unlock_irqrestore(addr, flags);
return oldbit;
return (oldbit & mask) ? 1 : 0;
}
static __inline__ int __test_and_set_bit(int nr, volatile unsigned long * address)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
int oldbit;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long oldbit;
unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
oldbit = (*addr & mask) ? 1 : 0;
*addr |= mask;
oldbit = *addr;
*addr = oldbit | mask;
return oldbit;
return (oldbit & mask) ? 1 : 0;
}
static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * address)
static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
int oldbit;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long oldbit;
unsigned long flags;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
_atomic_spin_lock_irqsave(addr, flags);
oldbit = (*addr & mask) ? 1 : 0;
*addr &= ~mask;
oldbit = *addr;
*addr = oldbit & ~mask;
_atomic_spin_unlock_irqrestore(addr, flags);
return oldbit;
return (oldbit & mask) ? 1 : 0;
}
static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long * address)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
int oldbit;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
unsigned long oldbit;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
oldbit = (*addr & mask) ? 1 : 0;
*addr &= ~mask;
oldbit = *addr;
*addr = oldbit & ~mask;
return oldbit;
return (oldbit & mask) ? 1 : 0;
}
static __inline__ int test_and_change_bit(int nr, volatile unsigned long * address)
static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
int oldbit;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long oldbit;
unsigned long flags;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
_atomic_spin_lock_irqsave(addr, flags);
oldbit = (*addr & mask) ? 1 : 0;
*addr ^= mask;
oldbit = *addr;
*addr = oldbit ^ mask;
_atomic_spin_unlock_irqrestore(addr, flags);
return oldbit;
return (oldbit & mask) ? 1 : 0;
}
static __inline__ int __test_and_change_bit(int nr, volatile unsigned long * address)
{
unsigned long mask;
unsigned long *addr = (unsigned long *) address;
int oldbit;
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
unsigned long *addr = (unsigned long *)address + (nr >> SHIFT_PER_LONG);
unsigned long oldbit;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
oldbit = (*addr & mask) ? 1 : 0;
*addr ^= mask;
oldbit = *addr;
*addr = oldbit ^ mask;
return oldbit;
return (oldbit & mask) ? 1 : 0;
}
static __inline__ int test_bit(int nr, const volatile unsigned long *address)
{
unsigned long mask;
const unsigned long *addr = (const unsigned long *)address;
addr += (nr >> SHIFT_PER_LONG);
mask = 1L << CHOP_SHIFTCOUNT(nr);
unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
const unsigned long *addr = (const unsigned long *)address + (nr >> SHIFT_PER_LONG);
return !!(*addr & mask);
}
@@ -229,7 +193,7 @@ static __inline__ unsigned long __ffs(unsigned long x)
unsigned long ret;
__asm__(
#if BITS_PER_LONG > 32
#ifdef __LP64__
" ldi 63,%1\n"
" extrd,u,*<> %0,63,32,%%r0\n"
" extrd,u,*TR %0,31,32,%0\n" /* move top 32-bits down */
@@ -304,14 +268,7 @@ static __inline__ int fls(int x)
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight64(x) \
({ \
unsigned long __x = (x); \
unsigned int __w; \
__w = generic_hweight32((unsigned int) __x); \
__w += generic_hweight32((unsigned int) (__x>>32)); \
__w; \
})
#define hweight64(x) generic_hweight64(x)
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
@@ -324,7 +281,13 @@ static __inline__ int fls(int x)
*/
static inline int sched_find_first_bit(const unsigned long *b)
{
#ifndef __LP64__
#ifdef __LP64__
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 64;
return __ffs(b[2]) + 128;
#else
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
@@ -334,14 +297,6 @@ static inline int sched_find_first_bit(const unsigned long *b)
if (b[3])
return __ffs(b[3]) + 96;
return __ffs(b[4]) + 128;
#else
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(((unsigned int)b[1])))
return __ffs(b[1]) + 64;
if (b[1] >> 32)
return __ffs(b[1] >> 32) + 96;
return __ffs(b[2]) + 128;
#endif
}
@@ -391,7 +346,7 @@ found_middle:
static __inline__ unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset)
{
const unsigned long *p = addr + (offset >> 6);
const unsigned long *p = addr + (offset >> SHIFT_PER_LONG);
unsigned long result = offset & ~(BITS_PER_LONG-1);
unsigned long tmp;
@@ -445,71 +400,90 @@ found_middle:
* test_and_{set,clear}_bit guarantee atomicity without
* disabling interrupts.
*/
#ifdef __LP64__
#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 0x38, (unsigned long *)addr)
#define ext2_set_bit_atomic(l,nr,addr) test_and_set_bit((nr) ^ 0x38, (unsigned long *)addr)
#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x38, (unsigned long *)addr)
#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit((nr) ^ 0x38, (unsigned long *)addr)
#else
#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 0x18, (unsigned long *)addr)
#define ext2_set_bit_atomic(l,nr,addr) test_and_set_bit((nr) ^ 0x18, (unsigned long *)addr)
#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)addr)
#define ext2_clear_bit_atomic(l,nr,addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)addr)
#endif
/* '3' is bits per byte */
#define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
#define ext2_test_bit(nr, addr) \
test_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
#define ext2_set_bit(nr, addr) \
__test_and_set_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
#define ext2_clear_bit(nr, addr) \
__test_and_clear_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
#define ext2_set_bit_atomic(l,nr,addr) \
test_and_set_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
#define ext2_clear_bit_atomic(l,nr,addr) \
test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
#endif /* __KERNEL__ */
static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
{
__const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
return (ADDR[nr >> 3] >> (nr & 7)) & 1;
}
/*
* This implementation of ext2_find_{first,next}_zero_bit was stolen from
* Linus' asm-alpha/bitops.h and modified for a big-endian machine.
*/
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
ext2_find_next_zero_bit((addr), (size), 0)
extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size, unsigned long offset)
/* include/linux/byteorder does not support "unsigned long" type */
static inline unsigned long ext2_swabp(unsigned long * x)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
#ifdef __LP64__
return (unsigned long) __swab64p((u64 *) x);
#else
return (unsigned long) __swab32p((u32 *) x);
#endif
}
/* include/linux/byteorder doesn't support "unsigned long" type */
static inline unsigned long ext2_swab(unsigned long y)
{
#ifdef __LP64__
return (unsigned long) __swab64((u64) y);
#else
return (unsigned long) __swab32((u32) y);
#endif
}
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
{
unsigned long *p = (unsigned long *) addr + (offset >> SHIFT_PER_LONG);
unsigned long result = offset & ~(BITS_PER_LONG - 1);
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
offset &= (BITS_PER_LONG - 1UL);
if (offset) {
tmp = cpu_to_le32p(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
tmp = ext2_swabp(p++);
tmp |= (~0UL >> (BITS_PER_LONG - offset));
if (size < BITS_PER_LONG)
goto found_first;
if (tmp != ~0U)
if (~tmp)
goto found_middle;
size -= 32;
result += 32;
size -= BITS_PER_LONG;
result += BITS_PER_LONG;
}
while (size >= 32) {
if ((tmp = cpu_to_le32p(p++)) != ~0U)
goto found_middle;
result += 32;
size -= 32;
while (size & ~(BITS_PER_LONG - 1)) {
if (~(tmp = *(p++)))
goto found_middle_swap;
result += BITS_PER_LONG;
size -= BITS_PER_LONG;
}
if (!size)
return result;
tmp = cpu_to_le32p(p);
tmp = ext2_swabp(p);
found_first:
tmp |= ~0U << size;
tmp |= ~0UL << size;
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. Skip ffz */
found_middle:
return result + ffz(tmp);
found_middle_swap:
return result + ffz(ext2_swab(tmp));
}
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
include/asm-parisc/dma-mapping.h
+4 -4
View File
@@ -9,8 +9,8 @@
/* See Documentation/DMA-mapping.txt */
struct hppa_dma_ops {
int (*dma_supported)(struct device *dev, u64 mask);
void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, int flag);
void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, int flag);
void *(*alloc_consistent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag);
void *(*alloc_noncoherent)(struct device *dev, size_t size, dma_addr_t *iova, gfp_t flag);
void (*free_consistent)(struct device *dev, size_t size, void *vaddr, dma_addr_t iova);
dma_addr_t (*map_single)(struct device *dev, void *addr, size_t size, enum dma_data_direction direction);
void (*unmap_single)(struct device *dev, dma_addr_t iova, size_t size, enum dma_data_direction direction);
@@ -49,14 +49,14 @@ extern struct hppa_dma_ops *hppa_dma_ops;
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
return hppa_dma_ops->alloc_consistent(dev, size, dma_handle, flag);
}
static inline void *
dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
return hppa_dma_ops->alloc_noncoherent(dev, size, dma_handle, flag);
}
include/asm-parisc/errno.h
+1
View File
@@ -114,6 +114,7 @@
#define ENOTSUP 252 /* Function not implemented (POSIX.4 / HPUX) */
#define ECANCELLED 253 /* aio request was canceled before complete (POSIX.4 / HPUX) */
#define ECANCELED ECANCELLED /* SuSv3 and Solaris wants one 'L' */
/* for robust mutexes */
#define EOWNERDEAD 254 /* Owner died */
include/asm-parisc/grfioctl.h
+2
View File
@@ -69,6 +69,8 @@
#define CRT_ID_TVRX S9000_ID_98765 /* TVRX (gto/falcon) */
#define CRT_ID_ARTIST S9000_ID_ARTIST /* Artist */
#define CRT_ID_SUMMIT 0x2FC1066B /* Summit FX2, FX4, FX6 ... */
#define CRT_ID_LEGO 0x35ACDA30 /* Lego FX5, FX10 ... */
#define CRT_ID_PINNACLE 0x35ACDA16 /* Pinnacle FXe */
/* structure for ioctl(GCDESCRIBE) */
include/asm-parisc/led.h
-3
View File
@@ -23,9 +23,6 @@
#define LED_CMD_REG_NONE 0 /* NULL == no addr for the cmd register */
/* led tasklet struct */
extern struct tasklet_struct led_tasklet;
/* register_led_driver() */
int __init register_led_driver(int model, unsigned long cmd_reg, unsigned long data_reg);
include/asm-parisc/parisc-device.h
+6 -1
View File
@@ -1,7 +1,7 @@
#include <linux/device.h>
struct parisc_device {
unsigned long hpa; /* Hard Physical Address */
struct resource hpa; /* Hard Physical Address */
struct parisc_device_id id;
struct parisc_driver *driver; /* Driver for this device */
char name[80]; /* The hardware description */
@@ -39,6 +39,11 @@ struct parisc_driver {
#define to_parisc_driver(d) container_of(d, struct parisc_driver, drv)
#define parisc_parent(d) to_parisc_device(d->dev.parent)
static inline char *parisc_pathname(struct parisc_device *d)
{
return d->dev.bus_id;
}
static inline void
parisc_set_drvdata(struct parisc_device *d, void *p)
{
include/asm-parisc/pci.h
+1 -1
View File
@@ -69,7 +69,7 @@ struct pci_hba_data {
#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
#if CONFIG_64BIT
#ifdef CONFIG_64BIT
#define PCI_F_EXTEND 0xffffffff00000000UL
#define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a)
include/asm-parisc/pgtable.h
+2
View File
@@ -501,6 +501,8 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
remap_pfn_range(vma, vaddr, pfn, size, prot)
#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
#define MK_IOSPACE_PFN(space, pfn) (pfn)
#define GET_IOSPACE(pfn) 0
#define GET_PFN(pfn) (pfn)
include/asm-parisc/processor.h
+19
View File
@@ -122,8 +122,27 @@ struct thread_struct {
};
/* Thread struct flags. */
#define PARISC_UAC_NOPRINT (1UL << 0) /* see prctl and unaligned.c */
#define PARISC_UAC_SIGBUS (1UL << 1)
#define PARISC_KERNEL_DEATH (1UL << 31) /* see die_if_kernel()... */
#define PARISC_UAC_SHIFT 0
#define PARISC_UAC_MASK (PARISC_UAC_NOPRINT|PARISC_UAC_SIGBUS)
#define SET_UNALIGN_CTL(task,value) \
({ \
(task)->thread.flags = (((task)->thread.flags & ~PARISC_UAC_MASK) \
| (((value) << PARISC_UAC_SHIFT) & \
PARISC_UAC_MASK)); \
0; \
})
#define GET_UNALIGN_CTL(task,addr) \
({ \
put_user(((task)->thread.flags & PARISC_UAC_MASK) \
>> PARISC_UAC_SHIFT, (int __user *) (addr)); \
})
#define INIT_THREAD { \
regs: { gr: { 0, }, \
fr: { 0, }, \
include/asm-parisc/psw.h
+26 -25
View File
@@ -1,4 +1,7 @@
#ifndef _PARISC_PSW_H
#include <linux/config.h>
#define PSW_I 0x00000001
#define PSW_D 0x00000002
#define PSW_P 0x00000004
@@ -9,6 +12,16 @@
#define PSW_G 0x00000040 /* PA1.x only */
#define PSW_O 0x00000080 /* PA2.0 only */
/* ssm/rsm instructions number PSW_W and PSW_E differently */
#define PSW_SM_I PSW_I /* Enable External Interrupts */
#define PSW_SM_D PSW_D
#define PSW_SM_P PSW_P
#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
#define PSW_SM_QUIET PSW_SM_R+PSW_SM_Q+PSW_SM_P+PSW_SM_D+PSW_SM_I
#define PSW_CB 0x0000ff00
#define PSW_M 0x00010000
@@ -30,33 +43,21 @@
#define PSW_Z 0x40000000 /* PA1.x only */
#define PSW_Y 0x80000000 /* PA1.x only */
#ifdef __LP64__
#define PSW_HI_CB 0x000000ff /* PA2.0 only */
#ifdef CONFIG_64BIT
# define PSW_HI_CB 0x000000ff /* PA2.0 only */
#endif
/* PSW bits to be used with ssm/rsm */
#define PSW_SM_I 0x1
#define PSW_SM_D 0x2
#define PSW_SM_P 0x4
#define PSW_SM_Q 0x8
#define PSW_SM_R 0x10
#define PSW_SM_F 0x20
#define PSW_SM_G 0x40
#define PSW_SM_O 0x80
#define PSW_SM_E 0x100
#define PSW_SM_W 0x200
#ifdef __LP64__
# define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
# define KERNEL_PSW (PSW_W | PSW_C | PSW_Q | PSW_P | PSW_D)
# define REAL_MODE_PSW (PSW_W | PSW_Q)
# define USER_PSW_MASK (PSW_W | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
# define USER_PSW_HI_MASK (PSW_HI_CB)
#else
# define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
# define KERNEL_PSW (PSW_C | PSW_Q | PSW_P | PSW_D)
# define REAL_MODE_PSW (PSW_Q)
# define USER_PSW_MASK (PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
#ifdef CONFIG_64BIT
# define USER_PSW_HI_MASK PSW_HI_CB
# define WIDE_PSW PSW_W
#else
# define WIDE_PSW 0
#endif
/* Used when setting up for rfi */
#define KERNEL_PSW (WIDE_PSW | PSW_C | PSW_Q | PSW_P | PSW_D)
#define REAL_MODE_PSW (WIDE_PSW | PSW_Q)
#define USER_PSW_MASK (WIDE_PSW | PSW_T | PSW_N | PSW_X | PSW_B | PSW_V | PSW_CB)
#define USER_PSW (PSW_C | PSW_Q | PSW_P | PSW_D | PSW_I)
#endif
include/asm-parisc/ptrace.h
+1 -1
View File
@@ -49,7 +49,7 @@ struct pt_regs {
#define user_mode(regs) (((regs)->iaoq[0] & 3) ? 1 : 0)
#define user_space(regs) (((regs)->iasq[1] != 0) ? 1 : 0)
#define instruction_pointer(regs) ((regs)->iaoq[0] & ~3)
#define profile_pc(regs) instruction_pointer(regs)
unsigned long profile_pc(struct pt_regs *);
extern void show_regs(struct pt_regs *);
#endif
include/asm-parisc/spinlock.h
-5
View File
@@ -5,11 +5,6 @@
#include <asm/processor.h>
#include <asm/spinlock_types.h>
/* Note that PA-RISC has to use `1' to mean unlocked and `0' to mean locked
* since it only has load-and-zero. Moreover, at least on some PA processors,
* the semaphore address has to be 16-byte aligned.
*/
static inline int __raw_spin_is_locked(raw_spinlock_t *x)
{
volatile unsigned int *a = __ldcw_align(x);
include/asm-parisc/spinlock_types.h
+6 -2
View File
@@ -6,11 +6,15 @@
#endif
typedef struct {
#ifdef CONFIG_PA20
volatile unsigned int slock;
# define __RAW_SPIN_LOCK_UNLOCKED { 1 }
#else
volatile unsigned int lock[4];
# define __RAW_SPIN_LOCK_UNLOCKED { { 1, 1, 1, 1 } }
#endif
} raw_spinlock_t;
#define __RAW_SPIN_LOCK_UNLOCKED { { 1, 1, 1, 1 } }
typedef struct {
raw_spinlock_t lock;
volatile int counter;
include/asm-parisc/system.h
+24 -26
View File
@@ -138,13 +138,7 @@ static inline void set_eiem(unsigned long val)
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
#define __ldcw(a) ({ \
unsigned __ret; \
__asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \
__ret; \
})
#ifndef CONFIG_PA20
/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
and GCC only guarantees 8-byte alignment for stack locals, we can't
be assured of 16-byte alignment for atomic lock data even if we
@@ -152,37 +146,41 @@ static inline void set_eiem(unsigned long val)
we use a struct containing an array of four ints for the atomic lock
type and dynamically select the 16-byte aligned int from the array
for the semaphore. */
#define __PA_LDCW_ALIGNMENT 16
#define __ldcw_align(a) ({ \
unsigned long __ret = (unsigned long) &(a)->lock[0]; \
__ret = (__ret + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); \
(volatile unsigned int *) __ret; \
})
#define LDCW "ldcw"
#else /*CONFIG_PA20*/
/* From: "Jim Hull" <jim.hull of hp.com>
I've attached a summary of the change, but basically, for PA 2.0, as
long as the ",CO" (coherent operation) completer is specified, then the
16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
they only require "natural" alignment (4-byte for ldcw, 8-byte for
ldcd). */
#define __PA_LDCW_ALIGNMENT 4
#define __ldcw_align(a) ((volatile unsigned int *)a)
#define LDCW "ldcw,co"
#endif /*!CONFIG_PA20*/
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
#define __ldcw(a) ({ \
unsigned __ret; \
__asm__ __volatile__(LDCW " 0(%1),%0" : "=r" (__ret) : "r" (a)); \
__ret; \
})
#ifdef CONFIG_SMP
# define __lock_aligned __attribute__((__section__(".data.lock_aligned")))
#endif
#define KERNEL_START (0x10100000 - 0x1000)
/* This is for the serialisation of PxTLB broadcasts. At least on the
* N class systems, only one PxTLB inter processor broadcast can be
* active at any one time on the Merced bus. This tlb purge
* synchronisation is fairly lightweight and harmless so we activate
* it on all SMP systems not just the N class. */
#ifdef CONFIG_SMP
extern spinlock_t pa_tlb_lock;
#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
#else
#define purge_tlb_start(x) do { } while(0)
#define purge_tlb_end(x) do { } while (0)
#endif
#define arch_align_stack(x) (x)
#endif
include/asm-parisc/tlbflush.h
+23 -6
View File
@@ -7,6 +7,26 @@
#include <linux/mm.h>
#include <asm/mmu_context.h>
/* This is for the serialisation of PxTLB broadcasts. At least on the
* N class systems, only one PxTLB inter processor broadcast can be
* active at any one time on the Merced bus. This tlb purge
* synchronisation is fairly lightweight and harmless so we activate
* it on all SMP systems not just the N class. */
#ifdef CONFIG_SMP
extern spinlock_t pa_tlb_lock;
#define purge_tlb_start(x) spin_lock(&pa_tlb_lock)
#define purge_tlb_end(x) spin_unlock(&pa_tlb_lock)
#else
#define purge_tlb_start(x) do { } while(0)
#define purge_tlb_end(x) do { } while (0)
#endif
extern void flush_tlb_all(void);
/*
@@ -64,29 +84,26 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
{
unsigned long npages;
npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
if (npages >= 512) /* XXX arbitrary, should be tuned */
if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
flush_tlb_all();
else {
mtsp(vma->vm_mm->context,1);
purge_tlb_start();
if (split_tlb) {
purge_tlb_start();
while (npages--) {
pdtlb(start);
pitlb(start);
start += PAGE_SIZE;
}
purge_tlb_end();
} else {
purge_tlb_start();
while (npages--) {
pdtlb(start);
start += PAGE_SIZE;
}
purge_tlb_end();
}
purge_tlb_end();
}
}
include/asm-parisc/types.h
+2
View File
@@ -33,8 +33,10 @@ typedef unsigned long long __u64;
#ifdef __LP64__
#define BITS_PER_LONG 64
#define SHIFT_PER_LONG 6
#else
#define BITS_PER_LONG 32
#define SHIFT_PER_LONG 5
#endif
#ifndef __ASSEMBLY__
include/asm-parisc/unistd.h
+11 -5
View File
@@ -687,8 +687,8 @@
#define __NR_shmget (__NR_Linux + 194)
#define __NR_shmctl (__NR_Linux + 195)
#define __NR_getpmsg (__NR_Linux + 196) /* some people actually want streams */
#define __NR_putpmsg (__NR_Linux + 197) /* some people actually want streams */
#define __NR_getpmsg (__NR_Linux + 196) /* Somebody *wants* streams? */
#define __NR_putpmsg (__NR_Linux + 197)
#define __NR_lstat64 (__NR_Linux + 198)
#define __NR_truncate64 (__NR_Linux + 199)
@@ -755,8 +755,14 @@
#define __NR_mbind (__NR_Linux + 260)
#define __NR_get_mempolicy (__NR_Linux + 261)
#define __NR_set_mempolicy (__NR_Linux + 262)
#define __NR_vserver (__NR_Linux + 263)
#define __NR_add_key (__NR_Linux + 264)
#define __NR_request_key (__NR_Linux + 265)
#define __NR_keyctl (__NR_Linux + 266)
#define __NR_ioprio_set (__NR_Linux + 267)
#define __NR_ioprio_get (__NR_Linux + 268)
#define __NR_Linux_syscalls 263
#define __NR_Linux_syscalls 269
#define HPUX_GATEWAY_ADDR 0xC0000004
#define LINUX_GATEWAY_ADDR 0x100
@@ -807,10 +813,10 @@
#define K_INLINE_SYSCALL(name, nr, args...) ({ \
long __sys_res; \
{ \
register unsigned long __res asm("r28"); \
register unsigned long __res __asm__("r28"); \
K_LOAD_ARGS_##nr(args) \
/* FIXME: HACK stw/ldw r19 around syscall */ \
asm volatile( \
__asm__ volatile( \
K_STW_ASM_PIC \
" ble 0x100(%%sr2, %%r0)\n" \
" ldi %1, %%r20\n" \
include/asm-ppc/dma-mapping.h
+1 -1
View File
@@ -19,7 +19,7 @@
* allocate the space "normally" and use the cache management functions
* to ensure it is consistent.
*/
extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, int gfp);
extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
extern void __dma_free_coherent(size_t size, void *vaddr);
extern void __dma_sync(void *vaddr, size_t size, int direction);
extern void __dma_sync_page(struct page *page, unsigned long offset,
include/asm-sh/dma-mapping.h
+2 -2
View File
@@ -9,7 +9,7 @@
extern struct bus_type pci_bus_type;
/* arch/sh/mm/consistent.c */
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size);
extern void consistent_sync(void *vaddr, size_t size, int direction);
@@ -26,7 +26,7 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
}
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag)
dma_addr_t *dma_handle, gfp_t flag)
{
if (sh_mv.mv_consistent_alloc) {
void *ret;
include/asm-sh/machvec.h
+1 -1
View File
@@ -64,7 +64,7 @@ struct sh_machine_vector
void (*mv_heartbeat)(void);
void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, int);
void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, gfp_t);
int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t);
};
include/asm-sh64/dma-mapping.h
+1 -1
View File
@@ -25,7 +25,7 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
}
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag)
dma_addr_t *dma_handle, gfp_t flag)
{
return consistent_alloc(NULL, size, dma_handle);
}
include/asm-sparc/dma-mapping.h
+1 -1
View File
@@ -8,7 +8,7 @@
#else
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag)
dma_addr_t *dma_handle, gfp_t flag)
{
BUG();
return NULL;
include/asm-sparc64/dma-mapping.h
+1 -1
View File
@@ -10,7 +10,7 @@
struct device;
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag)
dma_addr_t *dma_handle, gfp_t flag)
{
BUG();
return NULL;
include/asm-um/dma-mapping.h
+1 -1
View File
@@ -19,7 +19,7 @@ dma_set_mask(struct device *dev, u64 dma_mask)
static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
int flag)
gfp_t flag)
{
BUG();
return((void *) 0);
include/asm-um/page.h
+1 -1
View File
@@ -115,7 +115,7 @@ extern unsigned long uml_physmem;
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#define virt_addr_valid(v) pfn_valid(phys_to_pfn(__pa(v)))
extern struct page *arch_validate(struct page *page, int mask, int order);
extern struct page *arch_validate(struct page *page, gfp_t mask, int order);
#define HAVE_ARCH_VALIDATE
extern void arch_free_page(struct page *page, int order);
include/asm-x86_64/dma-mapping.h
+1 -1
View File
@@ -17,7 +17,7 @@ extern dma_addr_t bad_dma_address;
(swiotlb ? swiotlb_dma_mapping_error(x) : ((x) == bad_dma_address))
void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
unsigned gfp);
gfp_t gfp);
void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle);
include/asm-x86_64/pci.h
+3 -3
View File
@@ -50,10 +50,10 @@ extern int iommu_setup(char *opt);
* address space. The networking and block device layers use
* this boolean for bounce buffer decisions
*
* On x86-64 it mostly equals, but we set it to zero to tell some subsystems
* that an hard or soft IOMMU is available.
* On AMD64 it mostly equals, but we set it to zero to tell some subsystems
* that an IOMMU is available.
*/
#define PCI_DMA_BUS_IS_PHYS 0
#define PCI_DMA_BUS_IS_PHYS (no_iommu ? 1 : 0)
/*
* x86-64 always supports DAC, but sometimes it is useful to force
include/asm-x86_64/swiotlb.h
+1 -1
View File
@@ -27,7 +27,7 @@ extern void swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg,
int nents, int direction);
extern int swiotlb_dma_mapping_error(dma_addr_t dma_addr);
extern void *swiotlb_alloc_coherent (struct device *hwdev, size_t size,
dma_addr_t *dma_handle, int flags);
dma_addr_t *dma_handle, gfp_t flags);
extern void swiotlb_free_coherent (struct device *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle);
include/asm-xtensa/dma-mapping.h
+1 -1
View File
@@ -28,7 +28,7 @@ extern void consistent_sync(void*, size_t, int);
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
include/linux/ata.h
+32 -9
View File
@@ -42,13 +42,18 @@ enum {
ATA_SECT_SIZE = 512,
ATA_ID_WORDS = 256,
ATA_ID_PROD_OFS = 27,
ATA_ID_FW_REV_OFS = 23,
ATA_ID_SERNO_OFS = 10,
ATA_ID_MAJOR_VER = 80,
ATA_ID_PIO_MODES = 64,
ATA_ID_FW_REV_OFS = 23,
ATA_ID_PROD_OFS = 27,
ATA_ID_OLD_PIO_MODES = 51,
ATA_ID_FIELD_VALID = 53,
ATA_ID_MWDMA_MODES = 63,
ATA_ID_PIO_MODES = 64,
ATA_ID_EIDE_DMA_MIN = 65,
ATA_ID_EIDE_PIO = 67,
ATA_ID_EIDE_PIO_IORDY = 68,
ATA_ID_UDMA_MODES = 88,
ATA_ID_MAJOR_VER = 80,
ATA_ID_PIO4 = (1 << 1),
ATA_PCI_CTL_OFS = 2,
@@ -128,10 +133,15 @@ enum {
ATA_CMD_PIO_READ_EXT = 0x24,
ATA_CMD_PIO_WRITE = 0x30,
ATA_CMD_PIO_WRITE_EXT = 0x34,
ATA_CMD_READ_MULTI = 0xC4,
ATA_CMD_READ_MULTI_EXT = 0x29,
ATA_CMD_WRITE_MULTI = 0xC5,
ATA_CMD_WRITE_MULTI_EXT = 0x39,
ATA_CMD_SET_FEATURES = 0xEF,
ATA_CMD_PACKET = 0xA0,
ATA_CMD_VERIFY = 0x40,
ATA_CMD_VERIFY_EXT = 0x42,
ATA_CMD_INIT_DEV_PARAMS = 0x91,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
@@ -146,14 +156,14 @@ enum {
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_SLOW = 0x00,
/* ATAPI stuff */
@@ -181,6 +191,7 @@ enum {
ATA_TFLAG_ISADDR = (1 << 1), /* enable r/w to nsect/lba regs */
ATA_TFLAG_DEVICE = (1 << 2), /* enable r/w to device reg */
ATA_TFLAG_WRITE = (1 << 3), /* data dir: host->dev==1 (write) */
ATA_TFLAG_LBA = (1 << 4), /* enable LBA */
};
enum ata_tf_protocols {
@@ -250,7 +261,19 @@ struct ata_taskfile {
((u64) (id)[(n) + 1] << 16) | \
((u64) (id)[(n) + 0]) )
static inline int atapi_cdb_len(u16 *dev_id)
static inline int ata_id_current_chs_valid(const u16 *id)
{
/* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
has not been issued to the device then the values of
id[54] to id[56] are vendor specific. */
return (id[53] & 0x01) && /* Current translation valid */
id[54] && /* cylinders in current translation */
id[55] && /* heads in current translation */
id[55] <= 16 &&
id[56]; /* sectors in current translation */
}
static inline int atapi_cdb_len(const u16 *dev_id)
{
u16 tmp = dev_id[0] & 0x3;
switch (tmp) {
@@ -260,7 +283,7 @@ static inline int atapi_cdb_len(u16 *dev_id)
}
}
static inline int is_atapi_taskfile(struct ata_taskfile *tf)
static inline int is_atapi_taskfile(const struct ata_taskfile *tf)
{
return (tf->protocol == ATA_PROT_ATAPI) ||
(tf->protocol == ATA_PROT_ATAPI_NODATA) ||
include/linux/audit.h
+2 -2
View File
@@ -260,11 +260,11 @@ extern int audit_filter_user(struct netlink_skb_parms *cb, int type);
#ifdef CONFIG_AUDIT
/* These are defined in audit.c */
/* Public API */
extern void audit_log(struct audit_context *ctx, int gfp_mask,
extern void audit_log(struct audit_context *ctx, gfp_t gfp_mask,
int type, const char *fmt, ...)
__attribute__((format(printf,4,5)));
extern struct audit_buffer *audit_log_start(struct audit_context *ctx, int gfp_mask, int type);
extern struct audit_buffer *audit_log_start(struct audit_context *ctx, gfp_t gfp_mask, int type);
extern void audit_log_format(struct audit_buffer *ab,
const char *fmt, ...)
__attribute__((format(printf,2,3)));
include/linux/bio.h
+1 -1
View File
@@ -301,7 +301,7 @@ extern struct bio *bio_map_user_iov(struct request_queue *,
struct sg_iovec *, int, int);
extern void bio_unmap_user(struct bio *);
extern struct bio *bio_map_kern(struct request_queue *, void *, unsigned int,
unsigned int);
gfp_t);
extern void bio_set_pages_dirty(struct bio *bio);
extern void bio_check_pages_dirty(struct bio *bio);
extern struct bio *bio_copy_user(struct request_queue *, unsigned long, unsigned int, int);
include/linux/blkdev.h
+33 -17
View File
@@ -96,8 +96,8 @@ struct io_context {
void put_io_context(struct io_context *ioc);
void exit_io_context(void);
struct io_context *current_io_context(int gfp_flags);
struct io_context *get_io_context(int gfp_flags);
struct io_context *current_io_context(gfp_t gfp_flags);
struct io_context *get_io_context(gfp_t gfp_flags);
void copy_io_context(struct io_context **pdst, struct io_context **psrc);
void swap_io_context(struct io_context **ioc1, struct io_context **ioc2);
@@ -107,9 +107,9 @@ typedef void (rq_end_io_fn)(struct request *);
struct request_list {
int count[2];
int starved[2];
int elvpriv;
mempool_t *rq_pool;
wait_queue_head_t wait[2];
wait_queue_head_t drain;
};
#define BLK_MAX_CDB 16
@@ -203,6 +203,7 @@ struct request {
enum rq_flag_bits {
__REQ_RW, /* not set, read. set, write */
__REQ_FAILFAST, /* no low level driver retries */
__REQ_SORTED, /* elevator knows about this request */
__REQ_SOFTBARRIER, /* may not be passed by ioscheduler */
__REQ_HARDBARRIER, /* may not be passed by drive either */
__REQ_CMD, /* is a regular fs rw request */
@@ -210,6 +211,7 @@ enum rq_flag_bits {
__REQ_STARTED, /* drive already may have started this one */
__REQ_DONTPREP, /* don't call prep for this one */
__REQ_QUEUED, /* uses queueing */
__REQ_ELVPRIV, /* elevator private data attached */
/*
* for ATA/ATAPI devices
*/
@@ -235,6 +237,7 @@ enum rq_flag_bits {
#define REQ_RW (1 << __REQ_RW)
#define REQ_FAILFAST (1 << __REQ_FAILFAST)
#define REQ_SORTED (1 << __REQ_SORTED)
#define REQ_SOFTBARRIER (1 << __REQ_SOFTBARRIER)
#define REQ_HARDBARRIER (1 << __REQ_HARDBARRIER)
#define REQ_CMD (1 << __REQ_CMD)
@@ -242,6 +245,7 @@ enum rq_flag_bits {
#define REQ_STARTED (1 << __REQ_STARTED)
#define REQ_DONTPREP (1 << __REQ_DONTPREP)
#define REQ_QUEUED (1 << __REQ_QUEUED)
#define REQ_ELVPRIV (1 << __REQ_ELVPRIV)
#define REQ_PC (1 << __REQ_PC)
#define REQ_BLOCK_PC (1 << __REQ_BLOCK_PC)
#define REQ_SENSE (1 << __REQ_SENSE)
@@ -332,6 +336,12 @@ struct request_queue
prepare_flush_fn *prepare_flush_fn;
end_flush_fn *end_flush_fn;
/*
* Dispatch queue sorting
*/
sector_t end_sector;
struct request *boundary_rq;
/*
* Auto-unplugging state
*/
@@ -354,7 +364,7 @@ struct request_queue
* queue needs bounce pages for pages above this limit
*/
unsigned long bounce_pfn;
unsigned int bounce_gfp;
gfp_t bounce_gfp;
/*
* various queue flags, see QUEUE_* below
@@ -405,8 +415,6 @@ struct request_queue
unsigned int sg_reserved_size;
int node;
struct list_head drain_list;
/*
* reserved for flush operations
*/
@@ -434,7 +442,7 @@ enum {
#define QUEUE_FLAG_DEAD 5 /* queue being torn down */
#define QUEUE_FLAG_REENTER 6 /* Re-entrancy avoidance */
#define QUEUE_FLAG_PLUGGED 7 /* queue is plugged */
#define QUEUE_FLAG_DRAIN 8 /* draining queue for sched switch */
#define QUEUE_FLAG_ELVSWITCH 8 /* don't use elevator, just do FIFO */
#define QUEUE_FLAG_FLUSH 9 /* doing barrier flush sequence */
#define blk_queue_plugged(q) test_bit(QUEUE_FLAG_PLUGGED, &(q)->queue_flags)
@@ -454,6 +462,7 @@ enum {
#define blk_pm_request(rq) \
((rq)->flags & (REQ_PM_SUSPEND | REQ_PM_RESUME))
#define blk_sorted_rq(rq) ((rq)->flags & REQ_SORTED)
#define blk_barrier_rq(rq) ((rq)->flags & REQ_HARDBARRIER)
#define blk_barrier_preflush(rq) ((rq)->flags & REQ_BAR_PREFLUSH)
#define blk_barrier_postflush(rq) ((rq)->flags & REQ_BAR_POSTFLUSH)
@@ -550,7 +559,7 @@ extern void generic_make_request(struct bio *bio);
extern void blk_put_request(struct request *);
extern void blk_end_sync_rq(struct request *rq);
extern void blk_attempt_remerge(request_queue_t *, struct request *);
extern struct request *blk_get_request(request_queue_t *, int, int);
extern struct request *blk_get_request(request_queue_t *, int, gfp_t);
extern void blk_insert_request(request_queue_t *, struct request *, int, void *);
extern void blk_requeue_request(request_queue_t *, struct request *);
extern void blk_plug_device(request_queue_t *);
@@ -565,7 +574,7 @@ extern void blk_run_queue(request_queue_t *);
extern void blk_queue_activity_fn(request_queue_t *, activity_fn *, void *);
extern int blk_rq_map_user(request_queue_t *, struct request *, void __user *, unsigned int);
extern int blk_rq_unmap_user(struct bio *, unsigned int);
extern int blk_rq_map_kern(request_queue_t *, struct request *, void *, unsigned int, unsigned int);
extern int blk_rq_map_kern(request_queue_t *, struct request *, void *, unsigned int, gfp_t);
extern int blk_rq_map_user_iov(request_queue_t *, struct request *, struct sg_iovec *, int);
extern int blk_execute_rq(request_queue_t *, struct gendisk *,
struct request *, int);
@@ -611,12 +620,21 @@ extern void end_request(struct request *req, int uptodate);
static inline void blkdev_dequeue_request(struct request *req)
{
BUG_ON(list_empty(&req->queuelist));
elv_dequeue_request(req->q, req);
}
list_del_init(&req->queuelist);
/*
* This should be in elevator.h, but that requires pulling in rq and q
*/
static inline void elv_dispatch_add_tail(struct request_queue *q,
struct request *rq)
{
if (q->last_merge == rq)
q->last_merge = NULL;
if (req->rl)
elv_remove_request(req->q, req);
q->end_sector = rq_end_sector(rq);
q->boundary_rq = rq;
list_add_tail(&rq->queuelist, &q->queue_head);
}
/*
@@ -650,12 +668,10 @@ extern void blk_dump_rq_flags(struct request *, char *);
extern void generic_unplug_device(request_queue_t *);
extern void __generic_unplug_device(request_queue_t *);
extern long nr_blockdev_pages(void);
extern void blk_wait_queue_drained(request_queue_t *, int);
extern void blk_finish_queue_drain(request_queue_t *);
int blk_get_queue(request_queue_t *);
request_queue_t *blk_alloc_queue(int gfp_mask);
request_queue_t *blk_alloc_queue_node(int,int);
request_queue_t *blk_alloc_queue(gfp_t);
request_queue_t *blk_alloc_queue_node(gfp_t, int);
#define blk_put_queue(q) blk_cleanup_queue((q))
/*
include/linux/buffer_head.h
+1 -1
View File
@@ -188,7 +188,7 @@ extern int buffer_heads_over_limit;
* Generic address_space_operations implementations for buffer_head-backed
* address_spaces.
*/
int try_to_release_page(struct page * page, int gfp_mask);
int try_to_release_page(struct page * page, gfp_t gfp_mask);
int block_invalidatepage(struct page *page, unsigned long offset);
int block_write_full_page(struct page *page, get_block_t *get_block,
struct writeback_control *wbc);
include/linux/cyclomx.h
-2
View File
@@ -37,8 +37,6 @@
#include <linux/cycx_x25.h>
#endif
#define is_digit(ch) (((ch)>=(unsigned)'0'&&(ch)<=(unsigned)'9')?1:0)
/* Adapter Data Space.
* This structure is needed because we handle multiple cards, otherwise
* static data would do it.
include/linux/cycx_drv.h
-1
View File
@@ -60,6 +60,5 @@ extern int cycx_peek(struct cycx_hw *hw, u32 addr, void *buf, u32 len);
extern int cycx_poke(struct cycx_hw *hw, u32 addr, void *buf, u32 len);
extern int cycx_exec(void __iomem *addr);
extern void cycx_inten(struct cycx_hw *hw);
extern void cycx_intr(struct cycx_hw *hw);
#endif /* _CYCX_DRV_H */
include/linux/device.h
+66 -49
View File
@@ -28,19 +28,6 @@
#define BUS_ID_SIZE KOBJ_NAME_LEN
enum {
SUSPEND_NOTIFY,
SUSPEND_SAVE_STATE,
SUSPEND_DISABLE,
SUSPEND_POWER_DOWN,
};
enum {
RESUME_POWER_ON,
RESUME_RESTORE_STATE,
RESUME_ENABLE,
};
struct device;
struct device_driver;
struct class;
@@ -115,8 +102,8 @@ struct device_driver {
int (*probe) (struct device * dev);
int (*remove) (struct device * dev);
void (*shutdown) (struct device * dev);
int (*suspend) (struct device * dev, pm_message_t state, u32 level);
int (*resume) (struct device * dev, u32 level);
int (*suspend) (struct device * dev, pm_message_t state);
int (*resume) (struct device * dev);
};
@@ -190,7 +177,43 @@ struct class_attribute class_attr_##_name = __ATTR(_name,_mode,_show,_store)
extern int class_create_file(struct class *, const struct class_attribute *);
extern void class_remove_file(struct class *, const struct class_attribute *);
struct class_device_attribute {
struct attribute attr;
ssize_t (*show)(struct class_device *, char * buf);
ssize_t (*store)(struct class_device *, const char * buf, size_t count);
};
#define CLASS_DEVICE_ATTR(_name,_mode,_show,_store) \
struct class_device_attribute class_device_attr_##_name = \
__ATTR(_name,_mode,_show,_store)
extern int class_device_create_file(struct class_device *,
const struct class_device_attribute *);
/**
* struct class_device - class devices
* @class: pointer to the parent class for this class device. This is required.
* @devt: for internal use by the driver core only.
* @node: for internal use by the driver core only.
* @kobj: for internal use by the driver core only.
* @devt_attr: for internal use by the driver core only.
* @dev: if set, a symlink to the struct device is created in the sysfs
* directory for this struct class device.
* @class_data: pointer to whatever you want to store here for this struct
* class_device. Use class_get_devdata() and class_set_devdata() to get and
* set this pointer.
* @parent: pointer to a struct class_device that is the parent of this struct
* class_device. If NULL, this class_device will show up at the root of the
* struct class in sysfs (which is probably what you want to have happen.)
* @release: pointer to a release function for this struct class_device. If
* set, this will be called instead of the class specific release function.
* Only use this if you want to override the default release function, like
* when you are nesting class_device structures.
* @hotplug: pointer to a hotplug function for this struct class_device. If
* set, this will be called instead of the class specific hotplug function.
* Only use this if you want to override the default hotplug function, like
* when you are nesting class_device structures.
*/
struct class_device {
struct list_head node;
@@ -198,9 +221,14 @@ struct class_device {
struct class * class; /* required */
dev_t devt; /* dev_t, creates the sysfs "dev" */
struct class_device_attribute *devt_attr;
struct class_device_attribute uevent_attr;
struct device * dev; /* not necessary, but nice to have */
void * class_data; /* class-specific data */
struct class_device *parent; /* parent of this child device, if there is one */
void (*release)(struct class_device *dev);
int (*hotplug)(struct class_device *dev, char **envp,
int num_envp, char *buffer, int buffer_size);
char class_id[BUS_ID_SIZE]; /* unique to this class */
};
@@ -228,18 +256,6 @@ extern int class_device_rename(struct class_device *, char *);
extern struct class_device * class_device_get(struct class_device *);
extern void class_device_put(struct class_device *);
struct class_device_attribute {
struct attribute attr;
ssize_t (*show)(struct class_device *, char * buf);
ssize_t (*store)(struct class_device *, const char * buf, size_t count);
};
#define CLASS_DEVICE_ATTR(_name,_mode,_show,_store) \
struct class_device_attribute class_device_attr_##_name = \
__ATTR(_name,_mode,_show,_store)
extern int class_device_create_file(struct class_device *,
const struct class_device_attribute *);
extern void class_device_remove_file(struct class_device *,
const struct class_device_attribute *);
extern int class_device_create_bin_file(struct class_device *,
@@ -251,8 +267,8 @@ struct class_interface {
struct list_head node;
struct class *class;
int (*add) (struct class_device *);
void (*remove) (struct class_device *);
int (*add) (struct class_device *, struct class_interface *);
void (*remove) (struct class_device *, struct class_interface *);
};
extern int class_interface_register(struct class_interface *);
@@ -260,12 +276,29 @@ extern void class_interface_unregister(struct class_interface *);
extern struct class *class_create(struct module *owner, char *name);
extern void class_destroy(struct class *cls);
extern struct class_device *class_device_create(struct class *cls, dev_t devt,
struct device *device, char *fmt, ...)
__attribute__((format(printf,4,5)));
extern struct class_device *class_device_create(struct class *cls,
struct class_device *parent,
dev_t devt,
struct device *device,
char *fmt, ...)
__attribute__((format(printf,5,6)));
extern void class_device_destroy(struct class *cls, dev_t devt);
/* interface for exporting device attributes */
struct device_attribute {
struct attribute attr;
ssize_t (*show)(struct device *dev, struct device_attribute *attr,
char *buf);
ssize_t (*store)(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count);
};
#define DEVICE_ATTR(_name,_mode,_show,_store) \
struct device_attribute dev_attr_##_name = __ATTR(_name,_mode,_show,_store)
extern int device_create_file(struct device *device, struct device_attribute * entry);
extern void device_remove_file(struct device * dev, struct device_attribute * attr);
struct device {
struct klist klist_children;
struct klist_node knode_parent; /* node in sibling list */
@@ -275,6 +308,7 @@ struct device {
struct kobject kobj;
char bus_id[BUS_ID_SIZE]; /* position on parent bus */
struct device_attribute uevent_attr;
struct semaphore sem; /* semaphore to synchronize calls to
* its driver.
@@ -343,23 +377,6 @@ extern int device_attach(struct device * dev);
extern void driver_attach(struct device_driver * drv);
/* driverfs interface for exporting device attributes */
struct device_attribute {
struct attribute attr;
ssize_t (*show)(struct device *dev, struct device_attribute *attr,
char *buf);
ssize_t (*store)(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count);
};
#define DEVICE_ATTR(_name,_mode,_show,_store) \
struct device_attribute dev_attr_##_name = __ATTR(_name,_mode,_show,_store)
extern int device_create_file(struct device *device, struct device_attribute * entry);
extern void device_remove_file(struct device * dev, struct device_attribute * attr);
/*
* Platform "fixup" functions - allow the platform to have their say
* about devices and actions that the general device layer doesn't
include/linux/elevator.h
+11 -11
View File
@@ -8,18 +8,17 @@ typedef void (elevator_merge_req_fn) (request_queue_t *, struct request *, struc
typedef void (elevator_merged_fn) (request_queue_t *, struct request *);
typedef struct request *(elevator_next_req_fn) (request_queue_t *);
typedef int (elevator_dispatch_fn) (request_queue_t *, int);
typedef void (elevator_add_req_fn) (request_queue_t *, struct request *, int);
typedef void (elevator_add_req_fn) (request_queue_t *, struct request *);
typedef int (elevator_queue_empty_fn) (request_queue_t *);
typedef void (elevator_remove_req_fn) (request_queue_t *, struct request *);
typedef void (elevator_requeue_req_fn) (request_queue_t *, struct request *);
typedef struct request *(elevator_request_list_fn) (request_queue_t *, struct request *);
typedef void (elevator_completed_req_fn) (request_queue_t *, struct request *);
typedef int (elevator_may_queue_fn) (request_queue_t *, int, struct bio *);
typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, struct bio *, int);
typedef int (elevator_set_req_fn) (request_queue_t *, struct request *, struct bio *, gfp_t);
typedef void (elevator_put_req_fn) (request_queue_t *, struct request *);
typedef void (elevator_activate_req_fn) (request_queue_t *, struct request *);
typedef void (elevator_deactivate_req_fn) (request_queue_t *, struct request *);
typedef int (elevator_init_fn) (request_queue_t *, elevator_t *);
@@ -31,10 +30,9 @@ struct elevator_ops
elevator_merged_fn *elevator_merged_fn;
elevator_merge_req_fn *elevator_merge_req_fn;
elevator_next_req_fn *elevator_next_req_fn;
elevator_dispatch_fn *elevator_dispatch_fn;
elevator_add_req_fn *elevator_add_req_fn;
elevator_remove_req_fn *elevator_remove_req_fn;
elevator_requeue_req_fn *elevator_requeue_req_fn;
elevator_activate_req_fn *elevator_activate_req_fn;
elevator_deactivate_req_fn *elevator_deactivate_req_fn;
elevator_queue_empty_fn *elevator_queue_empty_fn;
@@ -81,15 +79,15 @@ struct elevator_queue
/*
* block elevator interface
*/
extern void elv_dispatch_sort(request_queue_t *, struct request *);
extern void elv_add_request(request_queue_t *, struct request *, int, int);
extern void __elv_add_request(request_queue_t *, struct request *, int, int);
extern int elv_merge(request_queue_t *, struct request **, struct bio *);
extern void elv_merge_requests(request_queue_t *, struct request *,
struct request *);
extern void elv_merged_request(request_queue_t *, struct request *);
extern void elv_remove_request(request_queue_t *, struct request *);
extern void elv_dequeue_request(request_queue_t *, struct request *);
extern void elv_requeue_request(request_queue_t *, struct request *);
extern void elv_deactivate_request(request_queue_t *, struct request *);
extern int elv_queue_empty(request_queue_t *);
extern struct request *elv_next_request(struct request_queue *q);
extern struct request *elv_former_request(request_queue_t *, struct request *);
@@ -98,7 +96,7 @@ extern int elv_register_queue(request_queue_t *q);
extern void elv_unregister_queue(request_queue_t *q);
extern int elv_may_queue(request_queue_t *, int, struct bio *);
extern void elv_completed_request(request_queue_t *, struct request *);
extern int elv_set_request(request_queue_t *, struct request *, struct bio *, int);
extern int elv_set_request(request_queue_t *, struct request *, struct bio *, gfp_t);
extern void elv_put_request(request_queue_t *, struct request *);
/*
@@ -142,4 +140,6 @@ enum {
ELV_MQUEUE_MUST,
};
#define rq_end_sector(rq) ((rq)->sector + (rq)->nr_sectors)
#endif
include/linux/ethtool.h
+8
View File
@@ -269,6 +269,8 @@ u32 ethtool_op_get_tso(struct net_device *dev);
int ethtool_op_set_tso(struct net_device *dev, u32 data);
int ethtool_op_get_perm_addr(struct net_device *dev,
struct ethtool_perm_addr *addr, u8 *data);
u32 ethtool_op_get_ufo(struct net_device *dev);
int ethtool_op_set_ufo(struct net_device *dev, u32 data);
/**
* &ethtool_ops - Alter and report network device settings
@@ -298,6 +300,8 @@ int ethtool_op_get_perm_addr(struct net_device *dev,
* set_sg: Turn scatter-gather on or off
* get_tso: Report whether TCP segmentation offload is enabled
* set_tso: Turn TCP segmentation offload on or off
* get_ufo: Report whether UDP fragmentation offload is enabled
* set_ufo: Turn UDP fragmentation offload on or off
* self_test: Run specified self-tests
* get_strings: Return a set of strings that describe the requested objects
* phys_id: Identify the device
@@ -364,6 +368,8 @@ struct ethtool_ops {
int (*get_perm_addr)(struct net_device *, struct ethtool_perm_addr *, u8 *);
int (*begin)(struct net_device *);
void (*complete)(struct net_device *);
u32 (*get_ufo)(struct net_device *);
int (*set_ufo)(struct net_device *, u32);
};
/* CMDs currently supported */
@@ -400,6 +406,8 @@ struct ethtool_ops {
#define ETHTOOL_GTSO 0x0000001e /* Get TSO enable (ethtool_value) */
#define ETHTOOL_STSO 0x0000001f /* Set TSO enable (ethtool_value) */
#define ETHTOOL_GPERMADDR 0x00000020 /* Get permanent hardware address */
#define ETHTOOL_GUFO 0x00000021 /* Get UFO enable (ethtool_value) */
#define ETHTOOL_SUFO 0x00000022 /* Set UFO enable (ethtool_value) */
/* compatibility with older code */
#define SPARC_ETH_GSET ETHTOOL_GSET
include/linux/fs.h
+1 -1
View File
@@ -320,7 +320,7 @@ struct address_space_operations {
/* Unfortunately this kludge is needed for FIBMAP. Don't use it */
sector_t (*bmap)(struct address_space *, sector_t);
int (*invalidatepage) (struct page *, unsigned long);
int (*releasepage) (struct page *, int);
int (*releasepage) (struct page *, gfp_t);
ssize_t (*direct_IO)(int, struct kiocb *, const struct iovec *iov,
loff_t offset, unsigned long nr_segs);
struct page* (*get_xip_page)(struct address_space *, sector_t,
include/linux/genhd.h
+2 -1
View File
@@ -119,7 +119,7 @@ struct gendisk {
int policy;
atomic_t sync_io; /* RAID */
unsigned long stamp, stamp_idle;
unsigned long stamp;
int in_flight;
#ifdef CONFIG_SMP
struct disk_stats *dkstats;
@@ -132,6 +132,7 @@ struct gendisk {
struct disk_attribute {
struct attribute attr;
ssize_t (*show)(struct gendisk *, char *);
ssize_t (*store)(struct gendisk *, const char *, size_t);
};
/*
include/linux/gfp.h
+20 -19
View File
@@ -12,8 +12,8 @@ struct vm_area_struct;
* GFP bitmasks..
*/
/* Zone modifiers in GFP_ZONEMASK (see linux/mmzone.h - low two bits) */
#define __GFP_DMA 0x01u
#define __GFP_HIGHMEM 0x02u
#define __GFP_DMA ((__force gfp_t)0x01u)
#define __GFP_HIGHMEM ((__force gfp_t)0x02u)
/*
* Action modifiers - doesn't change the zoning
@@ -26,24 +26,24 @@ struct vm_area_struct;
*
* __GFP_NORETRY: The VM implementation must not retry indefinitely.
*/
#define __GFP_WAIT 0x10u /* Can wait and reschedule? */
#define __GFP_HIGH 0x20u /* Should access emergency pools? */
#define __GFP_IO 0x40u /* Can start physical IO? */
#define __GFP_FS 0x80u /* Can call down to low-level FS? */
#define __GFP_COLD 0x100u /* Cache-cold page required */
#define __GFP_NOWARN 0x200u /* Suppress page allocation failure warning */
#define __GFP_REPEAT 0x400u /* Retry the allocation. Might fail */
#define __GFP_NOFAIL 0x800u /* Retry for ever. Cannot fail */
#define __GFP_NORETRY 0x1000u /* Do not retry. Might fail */
#define __GFP_NO_GROW 0x2000u /* Slab internal usage */
#define __GFP_COMP 0x4000u /* Add compound page metadata */
#define __GFP_ZERO 0x8000u /* Return zeroed page on success */
#define __GFP_NOMEMALLOC 0x10000u /* Don't use emergency reserves */
#define __GFP_NORECLAIM 0x20000u /* No realy zone reclaim during allocation */
#define __GFP_HARDWALL 0x40000u /* Enforce hardwall cpuset memory allocs */
#define __GFP_WAIT ((__force gfp_t)0x10u) /* Can wait and reschedule? */
#define __GFP_HIGH ((__force gfp_t)0x20u) /* Should access emergency pools? */
#define __GFP_IO ((__force gfp_t)0x40u) /* Can start physical IO? */
#define __GFP_FS ((__force gfp_t)0x80u) /* Can call down to low-level FS? */
#define __GFP_COLD ((__force gfp_t)0x100u) /* Cache-cold page required */
#define __GFP_NOWARN ((__force gfp_t)0x200u) /* Suppress page allocation failure warning */
#define __GFP_REPEAT ((__force gfp_t)0x400u) /* Retry the allocation. Might fail */
#define __GFP_NOFAIL ((__force gfp_t)0x800u) /* Retry for ever. Cannot fail */
#define __GFP_NORETRY ((__force gfp_t)0x1000u)/* Do not retry. Might fail */
#define __GFP_NO_GROW ((__force gfp_t)0x2000u)/* Slab internal usage */
#define __GFP_COMP ((__force gfp_t)0x4000u)/* Add compound page metadata */
#define __GFP_ZERO ((__force gfp_t)0x8000u)/* Return zeroed page on success */
#define __GFP_NOMEMALLOC ((__force gfp_t)0x10000u) /* Don't use emergency reserves */
#define __GFP_NORECLAIM ((__force gfp_t)0x20000u) /* No realy zone reclaim during allocation */
#define __GFP_HARDWALL ((__force gfp_t)0x40000u) /* Enforce hardwall cpuset memory allocs */
#define __GFP_BITS_SHIFT 20 /* Room for 20 __GFP_FOO bits */
#define __GFP_BITS_MASK ((1 << __GFP_BITS_SHIFT) - 1)
#define __GFP_BITS_MASK ((__force gfp_t)((1 << __GFP_BITS_SHIFT) - 1))
/* if you forget to add the bitmask here kernel will crash, period */
#define GFP_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_FS| \
@@ -64,6 +64,7 @@ struct vm_area_struct;
#define GFP_DMA __GFP_DMA
#define gfp_zone(mask) ((__force int)((mask) & (__force gfp_t)GFP_ZONEMASK))
/*
* There is only one page-allocator function, and two main namespaces to
@@ -94,7 +95,7 @@ static inline struct page *alloc_pages_node(int nid, gfp_t gfp_mask,
return NULL;
return __alloc_pages(gfp_mask, order,
NODE_DATA(nid)->node_zonelists + (gfp_mask & GFP_ZONEMASK));
NODE_DATA(nid)->node_zonelists + gfp_zone(gfp_mask));
}
#ifdef CONFIG_NUMA
include/linux/hil.h
+483
View File
@@ -0,0 +1,483 @@
#ifndef _HIL_H_
#define _HIL_H_
/*
* Hewlett Packard Human Interface Loop (HP-HIL) Protocol -- header.
*
* Copyright (c) 2001 Brian S. Julin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
*
* References:
* HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
*
* A note of thanks to HP for providing and shipping reference materials
* free of charge to help in the development of HIL support for Linux.
*
*/
#include <asm/types.h>
/* Physical constants relevant to raw loop/device timing.
*/
#define HIL_CLOCK 8MHZ
#define HIL_EK1_CLOCK 30HZ
#define HIL_EK2_CLOCK 60HZ
#define HIL_TIMEOUT_DEV 5 /* ms */
#define HIL_TIMEOUT_DEVS 10 /* ms */
#define HIL_TIMEOUT_NORESP 10 /* ms */
#define HIL_TIMEOUT_DEVS_DATA 16 /* ms */
#define HIL_TIMEOUT_SELFTEST 200 /* ms */
/* Actual wire line coding. These will only be useful if someone is
* implementing a software MLC to run HIL devices on a non-parisc machine.
*/
#define HIL_WIRE_PACKET_LEN 15
enum hil_wire_bitpos {
HIL_WIRE_START = 0,
HIL_WIRE_ADDR2,
HIL_WIRE_ADDR1,
HIL_WIRE_ADDR0,
HIL_WIRE_COMMAND,
HIL_WIRE_DATA7,
HIL_WIRE_DATA6,
HIL_WIRE_DATA5,
HIL_WIRE_DATA4,
HIL_WIRE_DATA3,
HIL_WIRE_DATA2,
HIL_WIRE_DATA1,
HIL_WIRE_DATA0,
HIL_WIRE_PARITY,
HIL_WIRE_STOP
};
/* HP documentation uses these bit positions to refer to commands;
* we will call these "packets".
*/
enum hil_pkt_bitpos {
HIL_PKT_CMD = 0x00000800,
HIL_PKT_ADDR2 = 0x00000400,
HIL_PKT_ADDR1 = 0x00000200,
HIL_PKT_ADDR0 = 0x00000100,
HIL_PKT_ADDR_MASK = 0x00000700,
HIL_PKT_ADDR_SHIFT = 8,
HIL_PKT_DATA7 = 0x00000080,
HIL_PKT_DATA6 = 0x00000040,
HIL_PKT_DATA5 = 0x00000020,
HIL_PKT_DATA4 = 0x00000010,
HIL_PKT_DATA3 = 0x00000008,
HIL_PKT_DATA2 = 0x00000004,
HIL_PKT_DATA1 = 0x00000002,
HIL_PKT_DATA0 = 0x00000001,
HIL_PKT_DATA_MASK = 0x000000FF,
HIL_PKT_DATA_SHIFT = 0
};
/* The HIL MLC also has several error/status/control bits. We extend the
* "packet" to include these when direct access to the MLC is available,
* or emulate them in cases where they are not available.
*
* This way the device driver knows that the underlying MLC driver
* has had to deal with loop errors.
*/
enum hil_error_bitpos {
HIL_ERR_OB = 0x00000800, /* MLC is busy sending an auto-poll,
or we have filled up the output
buffer and must wait. */
HIL_ERR_INT = 0x00010000, /* A normal interrupt has occurred. */
HIL_ERR_NMI = 0x00020000, /* An NMI has occurred. */
HIL_ERR_LERR = 0x00040000, /* A poll didn't come back. */
HIL_ERR_PERR = 0x01000000, /* There was a Parity Error. */
HIL_ERR_FERR = 0x02000000, /* There was a Framing Error. */
HIL_ERR_FOF = 0x04000000 /* Input FIFO Overflowed. */
};
enum hil_control_bitpos {
HIL_CTRL_TEST = 0x00010000,
HIL_CTRL_IPF = 0x00040000,
HIL_CTRL_APE = 0x02000000
};
/* Bits 30,31 are unused, we use them to control write behavior. */
#define HIL_DO_ALTER_CTRL 0x40000000 /* Write MSW of packet to control
before writing LSW to loop */
#define HIL_CTRL_ONLY 0xc0000000 /* *Only* alter the control registers */
/* This gives us a 32-bit "packet"
*/
typedef u32 hil_packet;
/* HIL Loop commands
*/
enum hil_command {
HIL_CMD_IFC = 0x00, /* Interface Clear */
HIL_CMD_EPT = 0x01, /* Enter Pass-Thru Mode */
HIL_CMD_ELB = 0x02, /* Enter Loop-Back Mode */
HIL_CMD_IDD = 0x03, /* Identify and Describe */
HIL_CMD_DSR = 0x04, /* Device Soft Reset */
HIL_CMD_PST = 0x05, /* Perform Self Test */
HIL_CMD_RRG = 0x06, /* Read Register */
HIL_CMD_WRG = 0x07, /* Write Register */
HIL_CMD_ACF = 0x08, /* Auto Configure */
HIL_CMDID_ACF = 0x07, /* Auto Configure bits with incremented ID */
HIL_CMD_POL = 0x10, /* Poll */
HIL_CMDCT_POL = 0x0f, /* Poll command bits with item count */
HIL_CMD_RPL = 0x20, /* RePoll */
HIL_CMDCT_RPL = 0x0f, /* RePoll command bits with item count */
HIL_CMD_RNM = 0x30, /* Report Name */
HIL_CMD_RST = 0x31, /* Report Status */
HIL_CMD_EXD = 0x32, /* Extended Describe */
HIL_CMD_RSC = 0x33, /* Report Security Code */
/* 0x34 to 0x3c reserved for future use */
HIL_CMD_DKA = 0x3d, /* Disable Keyswitch Autorepeat */
HIL_CMD_EK1 = 0x3e, /* Enable Keyswitch Autorepeat 1 */
HIL_CMD_EK2 = 0x3f, /* Enable Keyswitch Autorepeat 2 */
HIL_CMD_PR1 = 0x40, /* Prompt1 */
HIL_CMD_PR2 = 0x41, /* Prompt2 */
HIL_CMD_PR3 = 0x42, /* Prompt3 */
HIL_CMD_PR4 = 0x43, /* Prompt4 */
HIL_CMD_PR5 = 0x44, /* Prompt5 */
HIL_CMD_PR6 = 0x45, /* Prompt6 */
HIL_CMD_PR7 = 0x46, /* Prompt7 */
HIL_CMD_PRM = 0x47, /* Prompt (General Purpose) */
HIL_CMD_AK1 = 0x48, /* Acknowlege1 */
HIL_CMD_AK2 = 0x49, /* Acknowlege2 */
HIL_CMD_AK3 = 0x4a, /* Acknowlege3 */
HIL_CMD_AK4 = 0x4b, /* Acknowlege4 */
HIL_CMD_AK5 = 0x4c, /* Acknowlege5 */
HIL_CMD_AK6 = 0x4d, /* Acknowlege6 */
HIL_CMD_AK7 = 0x4e, /* Acknowlege7 */
HIL_CMD_ACK = 0x4f, /* Acknowlege (General Purpose) */
/* 0x50 to 0x78 reserved for future use */
/* 0x80 to 0xEF device-specific commands */
/* 0xf0 to 0xf9 reserved for future use */
HIL_CMD_RIO = 0xfa, /* Register I/O Error */
HIL_CMD_SHR = 0xfb, /* System Hard Reset */
HIL_CMD_TER = 0xfc, /* Transmission Error */
HIL_CMD_CAE = 0xfd, /* Configuration Address Error */
HIL_CMD_DHR = 0xfe, /* Device Hard Reset */
/* 0xff is prohibited from use. */
};
/*
* Response "records" to HIL commands
*/
/* Device ID byte
*/
#define HIL_IDD_DID_TYPE_MASK 0xe0 /* Primary type bits */
#define HIL_IDD_DID_TYPE_KB_INTEGRAL 0xa0 /* Integral keyboard */
#define HIL_IDD_DID_TYPE_KB_ITF 0xc0 /* ITD keyboard */
#define HIL_IDD_DID_TYPE_KB_RSVD 0xe0 /* Reserved keyboard type */
#define HIL_IDD_DID_TYPE_KB_LANG_MASK 0x1f /* Keyboard locale bits */
#define HIL_IDD_DID_KBLANG_USE_ESD 0x00 /* Use ESD Locale instead */
#define HIL_IDD_DID_TYPE_ABS 0x80 /* Absolute Positioners */
#define HIL_IDD_DID_ABS_RSVD1_MASK 0xf8 /* Reserved */
#define HIL_IDD_DID_ABS_RSVD1 0x98
#define HIL_IDD_DID_ABS_TABLET_MASK 0xf8 /* Tablets and digitizers */
#define HIL_IDD_DID_ABS_TABLET 0x90
#define HIL_IDD_DID_ABS_TSCREEN_MASK 0xfc /* Touch screens */
#define HIL_IDD_DID_ABS_TSCREEN 0x8c
#define HIL_IDD_DID_ABS_RSVD2_MASK 0xfc /* Reserved */
#define HIL_IDD_DID_ABS_RSVD2 0x88
#define HIL_IDD_DID_ABS_RSVD3_MASK 0xfc /* Reserved */
#define HIL_IDD_DID_ABS_RSVD3 0x80
#define HIL_IDD_DID_TYPE_REL 0x60 /* Relative Positioners */
#define HIL_IDD_DID_REL_RSVD1_MASK 0xf0 /* Reserved */
#define HIL_IDD_DID_REL_RSVD1 0x70
#define HIL_IDD_DID_REL_RSVD2_MASK 0xfc /* Reserved */
#define HIL_IDD_DID_REL_RSVD2 0x6c
#define HIL_IDD_DID_REL_MOUSE_MASK 0xfc /* Mouse */
#define HIL_IDD_DID_REL_MOUSE 0x68
#define HIL_IDD_DID_REL_QUAD_MASK 0xf8 /* Other Quadrature Devices */
#define HIL_IDD_DID_REL_QUAD 0x60
#define HIL_IDD_DID_TYPE_CHAR 0x40 /* Character Entry */
#define HIL_IDD_DID_CHAR_BARCODE_MASK 0xfc /* Barcode Reader */
#define HIL_IDD_DID_CHAR_BARCODE 0x5c
#define HIL_IDD_DID_CHAR_RSVD1_MASK 0xfc /* Reserved */
#define HIL_IDD_DID_CHAR_RSVD1 0x58
#define HIL_IDD_DID_CHAR_RSVD2_MASK 0xf8 /* Reserved */
#define HIL_IDD_DID_CHAR_RSVD2 0x50
#define HIL_IDD_DID_CHAR_RSVD3_MASK 0xf0 /* Reserved */
#define HIL_IDD_DID_CHAR_RSVD3 0x40
#define HIL_IDD_DID_TYPE_OTHER 0x20 /* Miscellaneous */
#define HIL_IDD_DID_OTHER_RSVD1_MASK 0xf0 /* Reserved */
#define HIL_IDD_DID_OTHER_RSVD1 0x30
#define HIL_IDD_DID_OTHER_BARCODE_MASK 0xfc /* Tone Generator */
#define HIL_IDD_DID_OTHER_BARCODE 0x2c
#define HIL_IDD_DID_OTHER_RSVD2_MASK 0xfc /* Reserved */
#define HIL_IDD_DID_OTHER_RSVD2 0x28
#define HIL_IDD_DID_OTHER_RSVD3_MASK 0xf8 /* Reserved */
#define HIL_IDD_DID_OTHER_RSVD3 0x20
#define HIL_IDD_DID_TYPE_KEYPAD 0x00 /* Vectra Keyboard */
/* IDD record header
*/
#define HIL_IDD_HEADER_AXSET_MASK 0x03 /* Number of axis in a set */
#define HIL_IDD_HEADER_RSC 0x04 /* Supports RSC command */
#define HIL_IDD_HEADER_EXD 0x08 /* Supports EXD command */
#define HIL_IDD_HEADER_IOD 0x10 /* IOD byte to follow */
#define HIL_IDD_HEADER_16BIT 0x20 /* 16 (vs. 8) bit resolution */
#define HIL_IDD_HEADER_ABS 0x40 /* Reports Absolute Position */
#define HIL_IDD_HEADER_2X_AXIS 0x80 /* Two sets of 1-3 axis */
/* I/O Descriptor
*/
#define HIL_IDD_IOD_NBUTTON_MASK 0x07 /* Number of buttons */
#define HIL_IDD_IOD_PROXIMITY 0x08 /* Proximity in/out events */
#define HIL_IDD_IOD_PROMPT_MASK 0x70 /* Number of prompts/acks */
#define HIL_IDD_IOD_PROMPT_SHIFT 4
#define HIL_IDD_IOD_PROMPT 0x80 /* Generic prompt/ack */
#define HIL_IDD_NUM_AXES_PER_SET(header_packet) \
((header_packet) & HIL_IDD_HEADER_AXSET_MASK)
#define HIL_IDD_NUM_AXSETS(header_packet) \
(2 - !((header_packet) & HIL_IDD_HEADER_2X_AXIS))
#define HIL_IDD_LEN(header_packet) \
((4 - !(header_packet & HIL_IDD_HEADER_IOD) - \
2 * !(HIL_IDD_NUM_AXES_PER_SET(header_packet))) + \
2 * HIL_IDD_NUM_AXES_PER_SET(header_packet) * \
!!((header_packet) & HIL_IDD_HEADER_ABS))
/* The following HIL_IDD_* macros assume you have an array of
* packets and/or unpacked 8-bit data in the order that they
* were received.
*/
#define HIL_IDD_AXIS_COUNTS_PER_M(header_ptr) \
(!(HIL_IDD_NUM_AXSETS(*(header_ptr))) ? -1 : \
(((*(header_ptr + 1) & HIL_PKT_DATA_MASK) + \
((*(header_ptr + 2) & HIL_PKT_DATA_MASK)) << 8) \
* ((*(header_ptr) & HIL_IDD_HEADER_16BIT) ? 100 : 1)))
#define HIL_IDD_AXIS_MAX(header_ptr, __axnum) \
((!(*(header_ptr) & HIL_IDD_HEADER_ABS) || \
(HIL_IDD_NUM_AXES_PER_SET(*(header_ptr)) <= __axnum)) ? 0 : \
((HIL_PKT_DATA_MASK & *((header_ptr) + 3 + 2 * __axnum)) + \
((HIL_PKT_DATA_MASK & *((header_ptr) + 4 + 2 * __axnum)) << 8)))
#define HIL_IDD_IOD(header_ptr) \
(*(header_ptr + HIL_IDD_LEN((*header_ptr)) - 1))
#define HIL_IDD_HAS_GEN_PROMPT(header_ptr) \
((*header_ptr & HIL_IDD_HEADER_IOD) && \
(HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROMPT))
#define HIL_IDD_HAS_GEN_PROXIMITY(header_ptr) \
((*header_ptr & HIL_IDD_HEADER_IOD) && \
(HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_PROXIMITY))
#define HIL_IDD_NUM_BUTTONS(header_ptr) \
((*header_ptr & HIL_IDD_HEADER_IOD) ? \
(HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NBUTTON_MASK) : 0)
#define HIL_IDD_NUM_PROMPTS(header_ptr) \
((*header_ptr & HIL_IDD_HEADER_IOD) ? \
((HIL_IDD_IOD(header_ptr) & HIL_IDD_IOD_NPROMPT_MASK) \
>> HIL_IDD_IOD_PROMPT_SHIFT) : 0)
/* The response to HIL EXD commands -- the "extended describe record" */
#define HIL_EXD_HEADER_WRG 0x03 /* Supports type2 WRG */
#define HIL_EXD_HEADER_WRG_TYPE1 0x01 /* Supports type1 WRG */
#define HIL_EXD_HEADER_WRG_TYPE2 0x02 /* Supports type2 WRG */
#define HIL_EXD_HEADER_RRG 0x04 /* Supports RRG command */
#define HIL_EXD_HEADER_RNM 0x10 /* Supports RNM command */
#define HIL_EXD_HEADER_RST 0x20 /* Supports RST command */
#define HIL_EXD_HEADER_LOCALE 0x40 /* Contains locale code */
#define HIL_EXD_NUM_RRG(header_ptr) \
((*header_ptr & HIL_EXD_HEADER_RRG) ? \
(*(header_ptr + 1) & HIL_PKT_DATA_MASK) : 0)
#define HIL_EXD_NUM_WWG(header_ptr) \
((*header_ptr & HIL_EXD_HEADER_WRG) ? \
(*(header_ptr + 2 - !(*header_ptr & HIL_EXD_HEADER_RRG)) & \
HIL_PKT_DATA_MASK) : 0)
#define HIL_EXD_LEN(header_ptr) \
(!!(*header_ptr & HIL_EXD_HEADER_RRG) + \
!!(*header_ptr & HIL_EXD_HEADER_WRG) + \
!!(*header_ptr & HIL_EXD_HEADER_LOCALE) + \
2 * !!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) + 1)
#define HIL_EXD_LOCALE(header_ptr) \
(!(*header_ptr & HIL_EXD_HEADER_LOCALE) ? -1 : \
(*(header_ptr + HIL_EXD_LEN(header_ptr) - 1) & HIL_PKT_DATA_MASK))
#define HIL_EXD_WRG_TYPE2_LEN(header_ptr) \
(!(*header_ptr & HIL_EXD_HEADER_WRG_TYPE2) ? -1 : \
(*(header_ptr + HIL_EXD_LEN(header_ptr) - 2 - \
!!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) + \
((*(header_ptr + HIL_EXD_LEN(header_ptr) - 1 - \
!!(*header_ptr & HIL_EXD_HEADER_LOCALE)) & HIL_PKT_DATA_MASK) << 8))
/* Device locale codes. */
/* Last defined locale code. Everything above this is "Reserved",
and note that this same table applies to the Device ID Byte where
keyboards may have a nationality code which is only 5 bits. */
#define HIL_LOCALE_MAX 0x1f
/* Map to hopefully useful strings. I was trying to make these look
like locale.aliases strings do; maybe that isn't the right table to
emulate. In either case, I didn't have much to work on. */
#define HIL_LOCALE_MAP \
"", /* 0x00 Reserved */ \
"", /* 0x01 Reserved */ \
"", /* 0x02 Reserved */ \
"swiss.french", /* 0x03 Swiss/French */ \
"portuguese", /* 0x04 Portuguese */ \
"arabic", /* 0x05 Arabic */ \
"hebrew", /* 0x06 Hebrew */ \
"english.canadian", /* 0x07 Canadian English */ \
"turkish", /* 0x08 Turkish */ \
"greek", /* 0x09 Greek */ \
"thai", /* 0x0a Thai (Thailand) */ \
"italian", /* 0x0b Italian */ \
"korean", /* 0x0c Hangul (Korea) */ \
"dutch", /* 0x0d Dutch */ \
"swedish", /* 0x0e Swedish */ \
"german", /* 0x0f German */ \
"chinese", /* 0x10 Chinese-PRC */ \
"chinese", /* 0x11 Chinese-ROC */ \
"swiss.french", /* 0x12 Swiss/French II */ \
"spanish", /* 0x13 Spanish */ \
"swiss.german", /* 0x14 Swiss/German II */ \
"flemish", /* 0x15 Belgian (Flemish) */ \
"finnish", /* 0x16 Finnish */ \
"english.uk", /* 0x17 United Kingdom */ \
"french.canadian", /* 0x18 French/Canadian */ \
"swiss.german", /* 0x19 Swiss/German */ \
"norwegian", /* 0x1a Norwegian */ \
"french", /* 0x1b French */ \
"danish", /* 0x1c Danish */ \
"japanese", /* 0x1d Katakana */ \
"spanish", /* 0x1e Latin American/Spanish*/\
"english.us" /* 0x1f United States */ \
/* HIL keycodes */
#define HIL_KEYCODES_SET1_TBLSIZE 128
#define HIL_KEYCODES_SET1 \
KEY_5, KEY_RESERVED, KEY_RIGHTALT, KEY_LEFTALT, \
KEY_RIGHTSHIFT, KEY_LEFTSHIFT, KEY_LEFTCTRL, KEY_SYSRQ, \
KEY_KP4, KEY_KP8, KEY_KP5, KEY_KP9, \
KEY_KP6, KEY_KP7, KEY_KPCOMMA, KEY_KPENTER, \
KEY_KP1, KEY_KPSLASH, KEY_KP2, KEY_KPPLUS, \
KEY_KP3, KEY_KPASTERISK, KEY_KP0, KEY_KPMINUS, \
KEY_B, KEY_V, KEY_C, KEY_X, \
KEY_Z, KEY_RESERVED, KEY_RESERVED, KEY_ESC, \
KEY_6, KEY_F10, KEY_3, KEY_F11, \
KEY_KPDOT, KEY_F9, KEY_TAB /*KP*/, KEY_F12, \
KEY_H, KEY_G, KEY_F, KEY_D, \
KEY_S, KEY_A, KEY_RESERVED, KEY_CAPSLOCK, \
KEY_U, KEY_Y, KEY_T, KEY_R, \
KEY_E, KEY_W, KEY_Q, KEY_TAB, \
KEY_7, KEY_6, KEY_5, KEY_4, \
KEY_3, KEY_2, KEY_1, KEY_GRAVE, \
KEY_F13, KEY_F14, KEY_F15, KEY_F16, \
KEY_F17, KEY_F18, KEY_F19, KEY_F20, \
KEY_MENU, KEY_F4, KEY_F3, KEY_F2, \
KEY_F1, KEY_VOLUMEUP, KEY_STOP, KEY_SENDFILE, \
KEY_SYSRQ, KEY_F5, KEY_F6, KEY_F7, \
KEY_F8, KEY_VOLUMEDOWN, KEY_DEL_EOL, KEY_DEL_EOS, \
KEY_8, KEY_9, KEY_0, KEY_MINUS, \
KEY_EQUAL, KEY_BACKSPACE, KEY_INS_LINE, KEY_DEL_LINE, \
KEY_I, KEY_O, KEY_P, KEY_LEFTBRACE, \
KEY_RIGHTBRACE, KEY_BACKSLASH, KEY_INSERT, KEY_DELETE, \
KEY_J, KEY_K, KEY_L, KEY_SEMICOLON, \
KEY_APOSTROPHE, KEY_ENTER, KEY_HOME, KEY_PAGEUP, \
KEY_M, KEY_COMMA, KEY_DOT, KEY_SLASH, \
KEY_BACKSLASH, KEY_SELECT, KEY_102ND, KEY_PAGEDOWN, \
KEY_N, KEY_SPACE, KEY_NEXT, KEY_RESERVED, \
KEY_LEFT, KEY_DOWN, KEY_UP, KEY_RIGHT
#define HIL_KEYCODES_SET3_TBLSIZE 128
#define HIL_KEYCODES_SET3 \
KEY_RESERVED, KEY_ESC, KEY_1, KEY_2, \
KEY_3, KEY_4, KEY_5, KEY_6, \
KEY_7, KEY_8, KEY_9, KEY_0, \
KEY_MINUS, KEY_EQUAL, KEY_BACKSPACE, KEY_TAB, \
KEY_Q, KEY_W, KEY_E, KEY_R, \
KEY_T, KEY_Y, KEY_U, KEY_I, \
KEY_O, KEY_P, KEY_LEFTBRACE, KEY_RIGHTBRACE, \
KEY_ENTER, KEY_LEFTCTRL, KEY_A, KEY_S, \
KEY_D, KEY_F, KEY_G, KEY_H, \
KEY_J, KEY_K, KEY_L, KEY_SEMICOLON, \
KEY_APOSTROPHE,KEY_GRAVE, KEY_LEFTSHIFT, KEY_BACKSLASH, \
KEY_Z, KEY_X, KEY_C, KEY_V, \
KEY_B, KEY_N, KEY_M, KEY_COMMA, \
KEY_DOT, KEY_SLASH, KEY_RIGHTSHIFT, KEY_KPASTERISK, \
KEY_LEFTALT, KEY_SPACE, KEY_CAPSLOCK, KEY_F1, \
KEY_F2, KEY_F3, KEY_F4, KEY_F5, \
KEY_F6, KEY_F7, KEY_F8, KEY_F9, \
KEY_F10, KEY_NUMLOCK, KEY_SCROLLLOCK, KEY_KP7, \
KEY_KP8, KEY_KP9, KEY_KPMINUS, KEY_KP4, \
KEY_KP5, KEY_KP6, KEY_KPPLUS, KEY_KP1, \
KEY_KP2, KEY_KP3, KEY_KP0, KEY_KPDOT, \
KEY_SYSRQ, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
KEY_UP, KEY_LEFT, KEY_DOWN, KEY_RIGHT, \
KEY_HOME, KEY_PAGEUP, KEY_END, KEY_PAGEDOWN, \
KEY_INSERT, KEY_DELETE, KEY_102ND, KEY_RESERVED, \
KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
KEY_F1, KEY_F2, KEY_F3, KEY_F4, \
KEY_F5, KEY_F6, KEY_F7, KEY_F8, \
KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, \
KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED
/* Response to POL command, the "poll record header" */
#define HIL_POL_NUM_AXES_MASK 0x03 /* Number of axis reported */
#define HIL_POL_CTS 0x04 /* Device ready to receive data */
#define HIL_POL_STATUS_PENDING 0x08 /* Device has status to report */
#define HIL_POL_CHARTYPE_MASK 0x70 /* Type of character data to follow */
#define HIL_POL_CHARTYPE_NONE 0x00 /* No character data to follow */
#define HIL_POL_CHARTYPE_RSVD1 0x10 /* Reserved Set 1 */
#define HIL_POL_CHARTYPE_ASCII 0x20 /* U.S. ASCII */
#define HIL_POL_CHARTYPE_BINARY 0x30 /* Binary data */
#define HIL_POL_CHARTYPE_SET1 0x40 /* Keycode Set 1 */
#define HIL_POL_CHARTYPE_RSVD2 0x50 /* Reserved Set 2 */
#define HIL_POL_CHARTYPE_SET2 0x60 /* Keycode Set 2 */
#define HIL_POL_CHARTYPE_SET3 0x70 /* Keycode Set 3 */
#define HIL_POL_AXIS_ALT 0x80 /* Data is from axis set 2 */
#endif /* _HIL_H_ */
include/linux/hil_mlc.h
+168
View File
@@ -0,0 +1,168 @@
/*
* HP Human Interface Loop Master Link Controller driver.
*
* Copyright (c) 2001 Brian S. Julin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
*
* References:
* HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
*
*/
#include <linux/hil.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <asm/semaphore.h>
#include <linux/serio.h>
#include <linux/list.h>
typedef struct hil_mlc hil_mlc;
/* The HIL has a complicated state engine.
* We define the structure of nodes in the state engine here.
*/
enum hilse_act {
/* HILSE_OUT prepares to receive input if the next node
* is an IN or EXPECT, and then sends the given packet.
*/
HILSE_OUT = 0,
/* HILSE_CTS checks if the loop is busy. */
HILSE_CTS,
/* HILSE_OUT_LAST sends the given command packet to
* the last configured/running device on the loop.
*/
HILSE_OUT_LAST,
/* HILSE_OUT_DISC sends the given command packet to
* the next device past the last configured/running one.
*/
HILSE_OUT_DISC,
/* HILSE_FUNC runs a callback function with given arguments.
* a positive return value causes the "ugly" branch to be taken.
*/
HILSE_FUNC,
/* HILSE_IN simply expects any non-errored packet to arrive
* within arg usecs.
*/
HILSE_IN = 0x100,
/* HILSE_EXPECT expects a particular packet to arrive
* within arg usecs, any other packet is considered an error.
*/
HILSE_EXPECT,
/* HILSE_EXPECT_LAST as above but dev field should be last
* discovered/operational device.
*/
HILSE_EXPECT_LAST,
/* HILSE_EXPECT_LAST as above but dev field should be first
* undiscovered/inoperational device.
*/
HILSE_EXPECT_DISC
};
typedef int (hilse_func) (hil_mlc *mlc, int arg);
struct hilse_node {
enum hilse_act act; /* How to process this node */
union {
hilse_func *func; /* Function to call if HILSE_FUNC */
hil_packet packet; /* Packet to send or to compare */
} object;
int arg; /* Timeout in usec or parm for func */
int good; /* Node to jump to on success */
int bad; /* Node to jump to on error */
int ugly; /* Node to jump to on timeout */
};
/* Methods for back-end drivers, e.g. hp_sdc_mlc */
typedef int (hil_mlc_cts) (hil_mlc *mlc);
typedef void (hil_mlc_out) (hil_mlc *mlc);
typedef int (hil_mlc_in) (hil_mlc *mlc, suseconds_t timeout);
struct hil_mlc_devinfo {
uint8_t idd[16]; /* Device ID Byte and Describe Record */
uint8_t rsc[16]; /* Security Code Header and Record */
uint8_t exd[16]; /* Extended Describe Record */
uint8_t rnm[16]; /* Device name as returned by RNM command */
};
struct hil_mlc_serio_map {
hil_mlc *mlc;
int di_revmap;
int didx;
};
/* How many (possibly old/detached) devices the we try to keep track of */
#define HIL_MLC_DEVMEM 16
struct hil_mlc {
struct list_head list; /* hil_mlc is organized as linked list */
rwlock_t lock;
void *priv; /* Data specific to a particular type of MLC */
int seidx; /* Current node in state engine */
int istarted, ostarted;
hil_mlc_cts *cts;
struct semaphore csem; /* Raised when loop idle */
hil_mlc_out *out;
struct semaphore osem; /* Raised when outpacket dispatched */
hil_packet opacket;
hil_mlc_in *in;
struct semaphore isem; /* Raised when a packet arrives */
hil_packet ipacket[16];
hil_packet imatch;
int icount;
struct timeval instart;
suseconds_t intimeout;
int ddi; /* Last operational device id */
int lcv; /* LCV to throttle loops */
struct timeval lcv_tv; /* Time loop was started */
int di_map[7]; /* Maps below items to live devs */
struct hil_mlc_devinfo di[HIL_MLC_DEVMEM];
struct serio *serio[HIL_MLC_DEVMEM];
struct hil_mlc_serio_map serio_map[HIL_MLC_DEVMEM];
hil_packet serio_opacket[HIL_MLC_DEVMEM];
int serio_oidx[HIL_MLC_DEVMEM];
struct hil_mlc_devinfo di_scratch; /* Temporary area */
int opercnt;
struct tasklet_struct *tasklet;
};
int hil_mlc_register(hil_mlc *mlc);
int hil_mlc_unregister(hil_mlc *mlc);
include/linux/hp_sdc.h
+300
View File
@@ -0,0 +1,300 @@
/*
* HP i8042 System Device Controller -- header
*
* Copyright (c) 2001 Brian S. Julin
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL").
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
*
* References:
*
* HP-HIL Technical Reference Manual. Hewlett Packard Product No. 45918A
*
* System Device Controller Microprocessor Firmware Theory of Operation
* for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
*
*/
#ifndef _LINUX_HP_SDC_H
#define _LINUX_HP_SDC_H
#include <linux/interrupt.h>
#include <linux/types.h>
#include <linux/time.h>
#include <linux/timer.h>
#if defined(__hppa__)
#include <asm/hardware.h>
#endif
/* No 4X status reads take longer than this (in usec).
*/
#define HP_SDC_MAX_REG_DELAY 20000
typedef void (hp_sdc_irqhook) (int irq, void *dev_id,
uint8_t status, uint8_t data);
int hp_sdc_request_timer_irq(hp_sdc_irqhook *callback);
int hp_sdc_request_hil_irq(hp_sdc_irqhook *callback);
int hp_sdc_request_cooked_irq(hp_sdc_irqhook *callback);
int hp_sdc_release_timer_irq(hp_sdc_irqhook *callback);
int hp_sdc_release_hil_irq(hp_sdc_irqhook *callback);
int hp_sdc_release_cooked_irq(hp_sdc_irqhook *callback);
typedef struct {
int actidx; /* Start of act. Acts are atomic WRT I/O to SDC */
int idx; /* Index within the act */
int endidx; /* transaction is over and done if idx == endidx */
uint8_t *seq; /* commands/data for the transaction */
union {
hp_sdc_irqhook *irqhook; /* Callback, isr or tasklet context */
struct semaphore *semaphore; /* Semaphore to sleep on. */
} act;
} hp_sdc_transaction;
int hp_sdc_enqueue_transaction(hp_sdc_transaction *this);
int hp_sdc_dequeue_transaction(hp_sdc_transaction *this);
/* The HP_SDC_ACT* values are peculiar to this driver.
* Nuance: never HP_SDC_ACT_DATAIN | HP_SDC_ACT_DEALLOC, use another
* act to perform the dealloc.
*/
#define HP_SDC_ACT_PRECMD 0x01 /* Send a command first */
#define HP_SDC_ACT_DATAREG 0x02 /* Set data registers */
#define HP_SDC_ACT_DATAOUT 0x04 /* Send data bytes */
#define HP_SDC_ACT_POSTCMD 0x08 /* Send command after */
#define HP_SDC_ACT_DATAIN 0x10 /* Collect data after */
#define HP_SDC_ACT_DURING 0x1f
#define HP_SDC_ACT_SEMAPHORE 0x20 /* Raise semaphore after */
#define HP_SDC_ACT_CALLBACK 0x40 /* Pass data to IRQ handler */
#define HP_SDC_ACT_DEALLOC 0x80 /* Destroy transaction after */
#define HP_SDC_ACT_AFTER 0xe0
#define HP_SDC_ACT_DEAD 0x60 /* Act timed out. */
/* Rest of the flags are straightforward representation of the SDC interface */
#define HP_SDC_STATUS_IBF 0x02 /* Input buffer full */
#define HP_SDC_STATUS_IRQMASK 0xf0 /* Bits containing "level 1" irq */
#define HP_SDC_STATUS_PERIODIC 0x10 /* Periodic 10ms timer */
#define HP_SDC_STATUS_USERTIMER 0x20 /* "Special purpose" timer */
#define HP_SDC_STATUS_TIMER 0x30 /* Both PERIODIC and USERTIMER */
#define HP_SDC_STATUS_REG 0x40 /* Data from an i8042 register */
#define HP_SDC_STATUS_HILCMD 0x50 /* Command from HIL MLC */
#define HP_SDC_STATUS_HILDATA 0x60 /* Data from HIL MLC */
#define HP_SDC_STATUS_PUP 0x70 /* Sucessful power-up self test */
#define HP_SDC_STATUS_KCOOKED 0x80 /* Key from cooked kbd */
#define HP_SDC_STATUS_KRPG 0xc0 /* Key from Repeat Gen */
#define HP_SDC_STATUS_KMOD_SUP 0x10 /* Shift key is up */
#define HP_SDC_STATUS_KMOD_CUP 0x20 /* Control key is up */
#define HP_SDC_NMISTATUS_FHS 0x40 /* NMI is a fast handshake irq */
/* Internal i8042 registers (there are more, but they are not too useful). */
#define HP_SDC_USE 0x02 /* Resource usage (including OB bit) */
#define HP_SDC_IM 0x04 /* Interrupt mask */
#define HP_SDC_CFG 0x11 /* Configuration register */
#define HP_SDC_KBLANGUAGE 0x12 /* Keyboard language */
#define HP_SDC_D0 0x70 /* General purpose data buffer 0 */
#define HP_SDC_D1 0x71 /* General purpose data buffer 1 */
#define HP_SDC_D2 0x72 /* General purpose data buffer 2 */
#define HP_SDC_D3 0x73 /* General purpose data buffer 3 */
#define HP_SDC_VT1 0x74 /* Timer for voice 1 */
#define HP_SDC_VT2 0x75 /* Timer for voice 2 */
#define HP_SDC_VT3 0x76 /* Timer for voice 3 */
#define HP_SDC_VT4 0x77 /* Timer for voice 4 */
#define HP_SDC_KBN 0x78 /* Which HIL devs are Nimitz */
#define HP_SDC_KBC 0x79 /* Which HIL devs are cooked kbds */
#define HP_SDC_LPS 0x7a /* i8042's view of HIL status */
#define HP_SDC_LPC 0x7b /* i8042's view of HIL "control" */
#define HP_SDC_RSV 0x7c /* Reserved "for testing" */
#define HP_SDC_LPR 0x7d /* i8042 count of HIL reconfigs */
#define HP_SDC_XTD 0x7e /* "Extended Configuration" register */
#define HP_SDC_STR 0x7f /* i8042 self-test result */
/* Bitfields for above registers */
#define HP_SDC_USE_LOOP 0x04 /* Command is currently on the loop. */
#define HP_SDC_IM_MASK 0x1f /* these bits not part of cmd/status */
#define HP_SDC_IM_FH 0x10 /* Mask the fast handshake irq */
#define HP_SDC_IM_PT 0x08 /* Mask the periodic timer irq */
#define HP_SDC_IM_TIMERS 0x04 /* Mask the MT/DT/CT irq */
#define HP_SDC_IM_RESET 0x02 /* Mask the reset key irq */
#define HP_SDC_IM_HIL 0x01 /* Mask the HIL MLC irq */
#define HP_SDC_CFG_ROLLOVER 0x08 /* WTF is "N-key rollover"? */
#define HP_SDC_CFG_KBD 0x10 /* There is a keyboard */
#define HP_SDC_CFG_NEW 0x20 /* Supports/uses HIL MLC */
#define HP_SDC_CFG_KBD_OLD 0x03 /* keyboard code for non-HIL */
#define HP_SDC_CFG_KBD_NEW 0x07 /* keyboard code from HIL autoconfig */
#define HP_SDC_CFG_REV 0x40 /* Code revision bit */
#define HP_SDC_CFG_IDPROM 0x80 /* IDPROM present in kbd (not HIL) */
#define HP_SDC_LPS_NDEV 0x07 /* # devices autoconfigured on HIL */
#define HP_SDC_LPS_ACSUCC 0x08 /* loop autoconfigured successfully */
#define HP_SDC_LPS_ACFAIL 0x80 /* last loop autoconfigure failed */
#define HP_SDC_LPC_APE_IPF 0x01 /* HIL MLC APE/IPF (autopoll) set */
#define HP_SDC_LPC_ARCONERR 0x02 /* i8042 autoreconfigs loop on err */
#define HP_SDC_LPC_ARCQUIET 0x03 /* i8042 doesn't report autoreconfigs*/
#define HP_SDC_LPC_COOK 0x10 /* i8042 cooks devices in _KBN */
#define HP_SDC_LPC_RC 0x80 /* causes autoreconfig */
#define HP_SDC_XTD_REV 0x07 /* contains revision code */
#define HP_SDC_XTD_REV_STRINGS(val, str) \
switch (val) { \
case 0x1: str = "1820-3712"; break; \
case 0x2: str = "1820-4379"; break; \
case 0x3: str = "1820-4784"; break; \
default: str = "unknown"; \
};
#define HP_SDC_XTD_BEEPER 0x08 /* TI SN76494 beeper available */
#define HP_SDC_XTD_BBRTC 0x20 /* OKI MSM-58321 BBRTC present */
#define HP_SDC_CMD_LOAD_RT 0x31 /* Load real time (from 8042) */
#define HP_SDC_CMD_LOAD_FHS 0x36 /* Load the fast handshake timer */
#define HP_SDC_CMD_LOAD_MT 0x38 /* Load the match timer */
#define HP_SDC_CMD_LOAD_DT 0x3B /* Load the delay timer */
#define HP_SDC_CMD_LOAD_CT 0x3E /* Load the cycle timer */
#define HP_SDC_CMD_SET_IM 0x40 /* 010xxxxx == set irq mask */
/* The documents provided do not explicitly state that all registers betweem
* 0x01 and 0x1f inclusive can be read by sending their register index as a
* command, but this is implied and appears to be the case.
*/
#define HP_SDC_CMD_READ_RAM 0x00 /* Load from i8042 RAM (autoinc) */
#define HP_SDC_CMD_READ_USE 0x02 /* Undocumented! Load from usage reg */
#define HP_SDC_CMD_READ_IM 0x04 /* Load current interrupt mask */
#define HP_SDC_CMD_READ_KCC 0x11 /* Load primary kbd config code */
#define HP_SDC_CMD_READ_KLC 0x12 /* Load primary kbd language code */
#define HP_SDC_CMD_READ_T1 0x13 /* Load timer output buffer byte 1 */
#define HP_SDC_CMD_READ_T2 0x14 /* Load timer output buffer byte 1 */
#define HP_SDC_CMD_READ_T3 0x15 /* Load timer output buffer byte 1 */
#define HP_SDC_CMD_READ_T4 0x16 /* Load timer output buffer byte 1 */
#define HP_SDC_CMD_READ_T5 0x17 /* Load timer output buffer byte 1 */
#define HP_SDC_CMD_READ_D0 0xf0 /* Load from i8042 RAM location 0x70 */
#define HP_SDC_CMD_READ_D1 0xf1 /* Load from i8042 RAM location 0x71 */
#define HP_SDC_CMD_READ_D2 0xf2 /* Load from i8042 RAM location 0x72 */
#define HP_SDC_CMD_READ_D3 0xf3 /* Load from i8042 RAM location 0x73 */
#define HP_SDC_CMD_READ_VT1 0xf4 /* Load from i8042 RAM location 0x74 */
#define HP_SDC_CMD_READ_VT2 0xf5 /* Load from i8042 RAM location 0x75 */
#define HP_SDC_CMD_READ_VT3 0xf6 /* Load from i8042 RAM location 0x76 */
#define HP_SDC_CMD_READ_VT4 0xf7 /* Load from i8042 RAM location 0x77 */
#define HP_SDC_CMD_READ_KBN 0xf8 /* Load from i8042 RAM location 0x78 */
#define HP_SDC_CMD_READ_KBC 0xf9 /* Load from i8042 RAM location 0x79 */
#define HP_SDC_CMD_READ_LPS 0xfa /* Load from i8042 RAM location 0x7a */
#define HP_SDC_CMD_READ_LPC 0xfb /* Load from i8042 RAM location 0x7b */
#define HP_SDC_CMD_READ_RSV 0xfc /* Load from i8042 RAM location 0x7c */
#define HP_SDC_CMD_READ_LPR 0xfd /* Load from i8042 RAM location 0x7d */
#define HP_SDC_CMD_READ_XTD 0xfe /* Load from i8042 RAM location 0x7e */
#define HP_SDC_CMD_READ_STR 0xff /* Load from i8042 RAM location 0x7f */
#define HP_SDC_CMD_SET_ARD 0xA0 /* Set emulated autorepeat delay */
#define HP_SDC_CMD_SET_ARR 0xA2 /* Set emulated autorepeat rate */
#define HP_SDC_CMD_SET_BELL 0xA3 /* Set voice 3 params for "beep" cmd */
#define HP_SDC_CMD_SET_RPGR 0xA6 /* Set "RPG" irq rate (doesn't work) */
#define HP_SDC_CMD_SET_RTMS 0xAD /* Set the RTC time (milliseconds) */
#define HP_SDC_CMD_SET_RTD 0xAF /* Set the RTC time (days) */
#define HP_SDC_CMD_SET_FHS 0xB2 /* Set fast handshake timer */
#define HP_SDC_CMD_SET_MT 0xB4 /* Set match timer */
#define HP_SDC_CMD_SET_DT 0xB7 /* Set delay timer */
#define HP_SDC_CMD_SET_CT 0xBA /* Set cycle timer */
#define HP_SDC_CMD_SET_RAMP 0xC1 /* Reset READ_RAM autoinc counter */
#define HP_SDC_CMD_SET_D0 0xe0 /* Load to i8042 RAM location 0x70 */
#define HP_SDC_CMD_SET_D1 0xe1 /* Load to i8042 RAM location 0x71 */
#define HP_SDC_CMD_SET_D2 0xe2 /* Load to i8042 RAM location 0x72 */
#define HP_SDC_CMD_SET_D3 0xe3 /* Load to i8042 RAM location 0x73 */
#define HP_SDC_CMD_SET_VT1 0xe4 /* Load to i8042 RAM location 0x74 */
#define HP_SDC_CMD_SET_VT2 0xe5 /* Load to i8042 RAM location 0x75 */
#define HP_SDC_CMD_SET_VT3 0xe6 /* Load to i8042 RAM location 0x76 */
#define HP_SDC_CMD_SET_VT4 0xe7 /* Load to i8042 RAM location 0x77 */
#define HP_SDC_CMD_SET_KBN 0xe8 /* Load to i8042 RAM location 0x78 */
#define HP_SDC_CMD_SET_KBC 0xe9 /* Load to i8042 RAM location 0x79 */
#define HP_SDC_CMD_SET_LPS 0xea /* Load to i8042 RAM location 0x7a */
#define HP_SDC_CMD_SET_LPC 0xeb /* Load to i8042 RAM location 0x7b */
#define HP_SDC_CMD_SET_RSV 0xec /* Load to i8042 RAM location 0x7c */
#define HP_SDC_CMD_SET_LPR 0xed /* Load to i8042 RAM location 0x7d */
#define HP_SDC_CMD_SET_XTD 0xee /* Load to i8042 RAM location 0x7e */
#define HP_SDC_CMD_SET_STR 0xef /* Load to i8042 RAM location 0x7f */
#define HP_SDC_CMD_DO_RTCW 0xc2 /* i8042 RAM 0x70 --> RTC */
#define HP_SDC_CMD_DO_RTCR 0xc3 /* RTC[0x70 0:3] --> irq/status/data */
#define HP_SDC_CMD_DO_BEEP 0xc4 /* i8042 RAM 0x70-74 --> beeper,VT3 */
#define HP_SDC_CMD_DO_HIL 0xc5 /* i8042 RAM 0x70-73 -->
HIL MLC R0,R1 i8042 HIL watchdog */
/* Values used to (de)mangle input/output to/from the HIL MLC */
#define HP_SDC_DATA 0x40 /* Data from an 8042 register */
#define HP_SDC_HIL_CMD 0x50 /* Data from HIL MLC R1/8042 */
#define HP_SDC_HIL_R1MASK 0x0f /* Contents of HIL MLC R1 0:3 */
#define HP_SDC_HIL_AUTO 0x10 /* Set if POL results from i8042 */
#define HP_SDC_HIL_ISERR 0x80 /* Has meaning as in next 4 values */
#define HP_SDC_HIL_RC_DONE 0x80 /* i8042 auto-configured loop */
#define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */
#define HP_SDC_HIL_TO 0x82 /* i8042 HIL watchdog expired */
#define HP_SDC_HIL_RC 0x84 /* i8042 is auto-configuring loop */
#define HP_SDC_HIL_DAT 0x60 /* Data from HIL MLC R0 */
typedef struct {
rwlock_t ibf_lock;
rwlock_t lock; /* user/tasklet lock */
rwlock_t rtq_lock; /* isr/tasklet lock */
rwlock_t hook_lock; /* isr/user lock for handler add/del */
unsigned int irq, nmi; /* Our IRQ lines */
unsigned long base_io, status_io, data_io; /* Our IO ports */
uint8_t im; /* Interrupt mask */
int set_im; /* Interrupt mask needs to be set. */
int ibf; /* Last known status of IBF flag */
uint8_t wi; /* current i8042 write index */
uint8_t r7[4]; /* current i8042[0x70 - 0x74] values */
uint8_t r11, r7e; /* Values from version/revision regs */
hp_sdc_irqhook *timer, *reg, *hil, *pup, *cooked;
#define HP_SDC_QUEUE_LEN 16
hp_sdc_transaction *tq[HP_SDC_QUEUE_LEN]; /* All pending read/writes */
int rcurr, rqty; /* Current read transact in process */
struct timeval rtv; /* Time when current read started */
int wcurr; /* Current write transact in process */
int dev_err; /* carries status from registration */
#if defined(__hppa__)
struct parisc_device *dev;
#elif defined(__mc68000__)
void *dev;
#else
#error No support for device registration on this arch yet.
#endif
struct timer_list kicker; /* Keeps below task alive */
struct tasklet_struct task;
} hp_i8042_sdc;
#endif /* _LINUX_HP_SDC_H */
include/linux/i2c-algo-bit.h
-4
View File
@@ -21,8 +21,6 @@
/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
Frodo Looijaard <frodol@dds.nl> */
/* $Id: i2c-algo-bit.h,v 1.10 2003/01/21 08:08:16 kmalkki Exp $ */
#ifndef _LINUX_I2C_ALGO_BIT_H
#define _LINUX_I2C_ALGO_BIT_H
@@ -46,8 +44,6 @@ struct i2c_algo_bit_data {
int timeout; /* in jiffies */
};
#define I2C_BIT_ADAP_MAX 16
int i2c_bit_add_bus(struct i2c_adapter *);
int i2c_bit_del_bus(struct i2c_adapter *);
include/linux/i2c-algo-pca.h
-2
View File
@@ -9,8 +9,6 @@ struct i2c_algo_pca_data {
int (*wait_for_interrupt) (struct i2c_algo_pca_data *adap);
};
#define I2C_PCA_ADAP_MAX 16
int i2c_pca_add_bus(struct i2c_adapter *);
int i2c_pca_del_bus(struct i2c_adapter *);
include/linux/i2c-algo-pcf.h
-4
View File
@@ -22,8 +22,6 @@
/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
Frodo Looijaard <frodol@dds.nl> */
/* $Id: i2c-algo-pcf.h,v 1.8 2003/01/21 08:08:16 kmalkki Exp $ */
#ifndef _LINUX_I2C_ALGO_PCF_H
#define _LINUX_I2C_ALGO_PCF_H
@@ -41,8 +39,6 @@ struct i2c_algo_pcf_data {
int timeout;
};
#define I2C_PCF_ADAP_MAX 16
int i2c_pcf_add_bus(struct i2c_adapter *);
int i2c_pcf_del_bus(struct i2c_adapter *);
include/linux/i2c-dev.h
-2
View File
@@ -19,8 +19,6 @@
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* $Id: i2c-dev.h,v 1.13 2003/01/21 08:08:16 kmalkki Exp $ */
#ifndef _LINUX_I2C_DEV_H
#define _LINUX_I2C_DEV_H

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