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clk: tegra210: update pll_c4 parameters

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Thomas Makin
2025-11-20 05:31:22 +00:00
parent 6298de0220
commit 9b8622f15f
1 changed files with 11 additions and 8 deletions
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19
drivers/clk/tegra/clk-tegra210.c
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@@ -1812,7 +1812,8 @@ static struct div_nmp pllss_nmp = {
static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = { static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
{ 12000000, 600000000, 50, 1, 1, 0 }, { 12000000, 600000000, 50, 1, 1, 0 },
{ 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */ { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
{ 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */ { 38400000, 998400000, 78, 3, 1, 0 },
{ 38400000, 793600000, 62, 3, 1, 0 },
{ 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 },
}; };
@@ -1824,14 +1825,16 @@ static const struct clk_div_table pll_vco_post_div_table[] = {
{ .val = 4, .div = 5 }, { .val = 4, .div = 5 },
{ .val = 5, .div = 6 }, { .val = 5, .div = 6 },
{ .val = 6, .div = 8 }, { .val = 6, .div = 8 },
{ .val = 7, .div = 10 }, { .val = 7, .div = 9 },
{ .val = 8, .div = 12 }, { .val = 8, .div = 10 },
{ .val = 9, .div = 16 }, { .val = 9, .div = 12 },
{ .val = 10, .div = 12 }, { .val = 10, .div = 15 },
{ .val = 11, .div = 16 }, { .val = 11, .div = 16 },
{ .val = 12, .div = 20 }, { .val = 12, .div = 18 },
{ .val = 13, .div = 24 }, { .val = 13, .div = 20 },
{ .val = 14, .div = 32 }, { .val = 14, .div = 24 },
{ .val = 15, .div = 30 },
{ .val = 16, .div = 32 },
{ .val = 0, .div = 0 }, { .val = 0, .div = 0 },
}; };