Merge tag 'spi-nor/for-5.20' into mtd/next

SPI NOR core changes:
- move SECT_4K_PMC flag out of the core as it's a vendor specific flag
- s/addr_width/addr_nbytes: address width means the number of IO lines
  used for the address, whereas in the code it is used as the number of
  address bytes.
- do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing
  time we should not change members of struct spi_nor, but instead fill
  members of struct spi_nor_flash_parameters which could later on be used
  by the callers.
- track flash's internal address mode so that we can use 4B opcodes
  together with opcodes that don't have a 4B opcode correspondent.

SPI NOR manufacturer drivers changes:
- esmt: Rename "f25l32qa" flash name to "f25l32qa-2s".
- micron-st: Skip FSR reading if SPI controller does not support it to
  allow flashes that support FSR to work even when attached to such SPI
  controllers.
- spansion: Add s25hl-t/s25hs-t IDs and fixups.

include/linux/mtd/spi-nor.h

@@ -351,7 +351,7 @@ struct spi_nor_flash_parameter;
  * @bouncebuf_size:	size of the bounce buffer
  * @info:		SPI NOR part JEDEC MFR ID and other info
  * @manufacturer:	SPI NOR manufacturer
- * @addr_width:		number of address bytes
+ * @addr_nbytes:	number of address bytes
  * @erase_opcode:	the opcode for erasing a sector
  * @read_opcode:	the read opcode
  * @read_dummy:		the dummy needed by the read operation
@@ -381,7 +381,7 @@ struct spi_nor {
 	size_t			bouncebuf_size;
 	const struct flash_info	*info;
 	const struct spi_nor_manufacturer *manufacturer;
-	u8			addr_width;
+	u8			addr_nbytes;
 	u8			erase_opcode;
 	u8			read_opcode;
 	u8			read_dummy;