From c878d518d7b628bc40cacfc9cee4a3db91a6a9ac Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Jun 2022 07:54:59 +0100 Subject: [PATCH 1/2] dt-bindings: can: mpfs: document the mpfs CAN controller Add a binding for the CAN controller on PolarFire SoC (MPFS). A data sheet and a register map can be downloaded at: | https://www.microsemi.com/document-portal/doc_download/1245725-polarfire-soc-fpga-mss-technical-reference-manual | https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map An alternative location for the register map is: | http://web.archive.org/web/20220403030214/https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map Link: https://lore.kernel.org/all/20220607065459.2035746-2-conor.dooley@microchip.com Signed-off-by: Conor Dooley Reviewed-by: Rob Herring [mkl: add link to data sheet and register map] Signed-off-by: Marc Kleine-Budde --- .../bindings/net/can/microchip,mpfs-can.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml diff --git a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml new file mode 100644 index 000000000000..45aa3de7cf01 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: + Microchip PolarFire SoC (MPFS) can controller + +maintainers: + - Conor Dooley + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + const: microchip,mpfs-can + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + can@2010c000 { + compatible = "microchip,mpfs-can"; + reg = <0x2010c000 0x1000>; + clocks = <&clkcfg 17>; + interrupt-parent = <&plic>; + interrupts = <56>; + }; From 38a71fc048955c5c9d8bd14351d0f8cbcfef4f5b Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Jun 2022 07:55:00 +0100 Subject: [PATCH 2/2] riscv: dts: microchip: add mpfs's CAN controllers PolarFire SoC has a pair of CAN controllers, but as they were undocumented there were omitted from the device tree. Add them. Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@microchip.com Signed-off-by: Conor Dooley Signed-off-by: Marc Kleine-Budde --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 8c3259134194..737e0e70c432 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -330,6 +330,24 @@ status = "disabled"; }; + can0: can@2010c000 { + compatible = "microchip,mpfs-can"; + reg = <0x0 0x2010c000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN0>; + interrupt-parent = <&plic>; + interrupts = <56>; + status = "disabled"; + }; + + can1: can@2010d000 { + compatible = "microchip,mpfs-can"; + reg = <0x0 0x2010d000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN1>; + interrupt-parent = <&plic>; + interrupts = <57>; + status = "disabled"; + }; + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>;