From 574b9e8d078f16cc55967b16f10e610b5d374cff Mon Sep 17 00:00:00 2001 From: James McGregor Date: Fri, 26 Apr 2024 09:29:41 +0000 Subject: [PATCH 01/16] dt-bindings: input: sun4i-lradc-keys: Add H616 compatible The Allwinner H616 SoC has an LRADC which is compatible with the versions in existing SoCs. Add a compatible string for H616, with the R329 fallback. This is the same as the D1, so put them into an enum. Signed-off-by: James McGregor Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240426092924.15489-2-jamcgregor@protonmail.com Signed-off-by: Chen-Yu Tsai --- .../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index c384bf0bb25d..6bdb8040be65 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -22,7 +22,9 @@ properties: - const: allwinner,sun8i-a83t-r-lradc - const: allwinner,sun50i-r329-lradc - items: - - const: allwinner,sun20i-d1-lradc + - enum: + - allwinner,sun50i-h616-lradc + - allwinner,sun20i-d1-lradc - const: allwinner,sun50i-r329-lradc reg: From 048ed5efbc4eec85c114d915ee0739341499d4b9 Mon Sep 17 00:00:00 2001 From: James McGregor Date: Fri, 26 Apr 2024 09:29:48 +0000 Subject: [PATCH 02/16] ARM: dts: sun50i: Add LRADC node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a DT node for the Allwinner H616 LRADC describing the base address, interrupt, reset and clock gates. Signed-off-by: James McGregor Reviewed-by: Andre Przywara Reviewed-by: Jernej Škrabec Link: https://lore.kernel.org/r/20240426092924.15489-3-jamcgregor@protonmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 921d5f61d8d6..cd866d8667ec 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -602,6 +602,16 @@ #thermal-sensor-cells = <1>; }; + lradc: lradc@5070800 { + compatible = "allwinner,sun50i-h616-lradc", + "allwinner,sun50i-r329-lradc"; + reg = <0x05070800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_KEYADC>; + resets = <&ccu RST_BUS_KEYADC>; + status = "disabled"; + }; + usbotg: usb@5100000 { compatible = "allwinner,sun50i-h616-musb", "allwinner,sun8i-h3-musb"; From 97babdce61f84f0344f91ca1b5bb702a375ccf03 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 28 Apr 2024 13:40:36 +0200 Subject: [PATCH 03/16] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Add missing cache information to the Allwinner H6 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper H6 cache information. Adding the cache information to the H6 SoC dtsi also makes the following warning message in the kernel log go away: cacheinfo: Unable to detect cache hierarchy for CPU 0 The cache parameters for the H6 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner H6 V200 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 37 ++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 8a8591c4e7dd..2301c59b41b1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -29,6 +29,13 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -39,6 +46,13 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -49,6 +63,13 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -59,6 +80,22 @@ clocks = <&ccu CLK_CPUX>; clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; From c452e215f8745912853a9d98ae23ddbdaa1f6104 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Mon, 27 May 2024 02:08:17 +0200 Subject: [PATCH 04/16] dt-bindings: arm: sunxi: Correct the descriptions for Pine64 boards Correct the descriptions of a few Pine64 boards and devices, according to their official names used in the Pine64 wiki and on the official Pine64 website. [1][2][3] This ensures consistency between the officially used names and the names in the source code. [1] https://wiki.pine64.org/wiki/PINE_A64 [2] https://wiki.pine64.org/wiki/PINE_H64 [3] https://pine64.org/devices/ Reviewed-by: Rob Herring (Arm) Cc: Marek Kraus Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/84cd1c70863704e950ca4cadffc7d5367434e06b.1716768092.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c6d0d8d81ed4..3196dbeb0cbb 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -708,12 +708,12 @@ properties: - const: olimex,a64-teres-i - const: allwinner,sun50i-a64 - - description: Pine64 + - description: Pine64 PINE A64 items: - const: pine64,pine64 - const: allwinner,sun50i-a64 - - description: Pine64+ + - description: Pine64 PINE A64+ items: - const: pine64,pine64-plus - const: allwinner,sun50i-a64 @@ -724,17 +724,17 @@ properties: - const: sochip,s3 - const: allwinner,sun8i-v3 - - description: Pine64 PineH64 model A + - description: Pine64 PINE H64 Model A items: - const: pine64,pine-h64 - const: allwinner,sun50i-h6 - - description: Pine64 PineH64 model B + - description: Pine64 PINE H64 Model B items: - const: pine64,pine-h64-model-b - const: allwinner,sun50i-h6 - - description: Pine64 LTS + - description: Pine64 PINE A64 LTS items: - const: pine64,pine64-lts - const: allwinner,sun50i-r18 @@ -763,17 +763,17 @@ properties: - const: pine64,pinephone - const: allwinner,sun50i-a64 - - description: Pine64 PineTab, Development Sample + - description: Pine64 PineTab Developer Sample items: - const: pine64,pinetab - const: allwinner,sun50i-a64 - - description: Pine64 PineTab, Early Adopter's batch (and maybe later ones) + - description: Pine64 PineTab Early Adopter items: - const: pine64,pinetab-early-adopter - const: allwinner,sun50i-a64 - - description: Pine64 SoPine Baseboard + - description: Pine64 SOPINE items: - const: pine64,sopine-baseboard - const: pine64,sopine From 523bfa3069eca7498e2ebb56206ac70c5ab6a74b Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Mon, 27 May 2024 02:08:18 +0200 Subject: [PATCH 05/16] arm64: dts: allwinner: Correct the model names for Pine64 boards Correct the model names of a few Pine64 boards and devices, according to their official names used in the Pine64 wiki and on the official Pine64 website. [1][2][3] This ensures consistency between the officially used names and the names in the source code. [1] https://wiki.pine64.org/wiki/PINE_A64 [2] https://wiki.pine64.org/wiki/PINE_H64 [3] https://pine64.org/devices/ Acked-by: Jernej Skrabec Cc: Marek Kraus Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/4a988518e0dba5de3ecfc172a0fa2b0653c00d8b.1716768092.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +- .../boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts index 596a25907432..709fe650a360 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts @@ -5,7 +5,7 @@ #include "sun50i-a64-sopine-baseboard.dts" / { - model = "Pine64 LTS"; + model = "Pine64 PINE A64 LTS"; compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", "allwinner,sun50i-a64"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts index b54099b654c8..026d843cd7e0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts @@ -4,7 +4,7 @@ #include "sun50i-a64-pine64.dts" / { - model = "Pine64+"; + model = "Pine64 PINE A64+"; compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; /* TODO: Camera, touchscreen, etc. */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index 2accb5ddf783..09e71fd60785 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -9,7 +9,7 @@ #include / { - model = "Pine64"; + model = "Pine64 PINE A64"; compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 6c65d5bc16ba..379c2c8466f5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -13,7 +13,7 @@ #include / { - model = "Pinebook"; + model = "Pine64 Pinebook"; compatible = "pine64,pinebook", "allwinner,sun50i-a64"; chassis-type = "laptop"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts index 6265360ce623..86cc85eb3d48 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab-early-adopter.dts @@ -9,7 +9,7 @@ #include "sun50i-a64-pinetab.dts" / { - model = "PineTab, Early Adopter's version"; + model = "Pine64 PineTab Early Adopter"; compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index c6007df99938..f5fb1ee32dad 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -14,7 +14,7 @@ #include / { - model = "PineTab, Development Sample"; + model = "Pine64 PineTab Developer Sample"; compatible = "pine64,pinetab", "allwinner,sun50i-a64"; chassis-type = "tablet"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 5e66ce1a334f..be2347c8f267 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -8,7 +8,7 @@ #include "sun50i-a64-sopine.dtsi" / { - model = "SoPine with baseboard"; + model = "Pine64 SOPINE on Baseboard carrier board"; compatible = "pine64,sopine-baseboard", "pine64,sopine", "allwinner,sun50i-a64"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index 66fe03910d5e..066fbeff8bfa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -8,7 +8,7 @@ /delete-node/ ®_gmac_3v3; / { - model = "Pine H64 model B"; + model = "Pine64 PINE H64 Model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; wifi_pwrseq: pwrseq { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 3910393be1f9..c8b275552872 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -9,7 +9,7 @@ #include / { - model = "Pine H64 model A"; + model = "Pine64 PINE H64 Model A"; compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; aliases { From 7360e752165496617e8fec4bbeb7aebf630ca775 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sun, 28 Apr 2024 13:40:35 +0200 Subject: [PATCH 06/16] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Add missing cache information to the Allwinner A64 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper A64 cache information. While there, use a more self-descriptive label for the L2 cache node, which also makes it more consistent with other SoC dtsi files. The cache parameters for the A64 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner A64 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 ++++++++++++++++--- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index ce4aa44c3353..e868ca5ae753 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -51,10 +51,16 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -62,10 +68,16 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -73,10 +85,16 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -84,16 +102,25 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; - L2: l2-cache { + l2_cache: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; From d4ec229eaeb8453ad7244fc1d919ac51ac5ba394 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Tue, 28 May 2024 18:45:16 +0200 Subject: [PATCH 07/16] arm64: dts: allwinner: Add cache information to the SoC dtsi for H616 Add missing cache information to the Allwinner H616 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper H616 cache information. Adding the cache information to the H616 SoC dtsi also makes the following warning message in the kernel log go away: cacheinfo: Unable to detect cache hierarchy for CPU 0 Rather conspicuously, almost no cache-related information is available in the publicly available Allwinner H616 datasheet (version 1.0) and H616 user manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were obtained and derived by hand from the cache size and layout specifications found in the following technical reference manual, and from the cache size and die revision hints available from the following community-provided data and memory subsystem benchmarks: - ARM Cortex-A53 revision r0p4 TRM, version J - Summary of the two available H616 die revisions and their differences in cache sizes observed from the CSSIDR_EL1 register readouts, provided by Andre Przywara [1][2] - Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC, provided by Thomas Kaiser [3] For future reference, here's a brief summary of the available documentation and the community-provided data and memory subsystem benchmarks: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The size of the L2 cache depends on the actual H616 die revision (there are two die revisions), so the entire SoC can have either 256 KB or 1 MB of unified L2 16-way, set-associative cache [1] Also for future reference, here's the relevant excerpt from the community- provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and 256 KB are the L1 data and L2 cache sizes, respectively: block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 4.3 ns / 7.3 ns 131072 : 6.6 ns / 10.5 ns 262144 : 9.8 ns / 15.2 ns 524288 : 91.8 ns / 142.9 ns 1048576 : 138.6 ns / 188.3 ns 2097152 : 163.0 ns / 204.8 ns 4194304 : 178.8 ns / 213.5 ns 8388608 : 187.1 ns / 217.9 ns 16777216 : 192.2 ns / 220.9 ns 33554432 : 196.5 ns / 224.0 ns 67108864 : 215.7 ns / 259.5 ns The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch will perform runtime adjustment of the device tree data, making the correct L2 cache size of 1 MB present in the device tree for the boards based on the revision of H616 that actually provides 1 MB of L2 cache. [1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/ [2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/ [3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt Suggested-by: Andre Przywara Helped-by: Andre Przywara Reviewed-by: Andre Przywara Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/e4b9cc3e3d366a571e552c31dafa5de847bc1c12.1716914537.git.dsimic@manjaro.org Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index cd866d8667ec..20564cc02267 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -27,6 +27,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -36,6 +43,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -45,6 +59,13 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -54,6 +75,22 @@ enable-method = "psci"; clocks = <&ccu CLK_CPUX>; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; }; }; From bba474656dd85b13e4c5d5bdb73ca08d9136df21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pavel=20L=C3=B6bl?= Date: Wed, 20 Mar 2024 07:10:19 +0100 Subject: [PATCH 08/16] ARM: dts: sunxi: remove duplicated entries in makefile MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit During introduction of DTS vendor subdirectories in 724ba6751532, sun8i section of the makefile got duplicated. Clean that up. Fixes: 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories") Signed-off-by: Pavel Löbl Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240320061027.4078852-1-pavel@loebl.cz Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 62 ---------------------------- 1 file changed, 62 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 4247f19b1adc..cd0d044882cf 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -261,68 +261,6 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-a23-evb.dtb \ - sun8i-a23-gt90h-v4.dtb \ - sun8i-a23-inet86dz.dtb \ - sun8i-a23-ippo-q8h-v5.dtb \ - sun8i-a23-ippo-q8h-v1.2.dtb \ - sun8i-a23-polaroid-mid2407pxe03.dtb \ - sun8i-a23-polaroid-mid2809pxe04.dtb \ - sun8i-a23-q8-tablet.dtb \ - sun8i-a33-et-q8-v1.6.dtb \ - sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-inet-d978-rev2.dtb \ - sun8i-a33-ippo-q8h-v1.2.dtb \ - sun8i-a33-olinuxino.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-tbs-a711.dtb \ - sun8i-h2-plus-bananapi-m2-zero.dtb \ - sun8i-h2-plus-libretech-all-h3-cc.dtb \ - sun8i-h2-plus-orangepi-r1.dtb \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ - sun8i-h3-bananapi-m2-plus-v1.2.dtb \ - sun8i-h3-beelink-x2.dtb \ - sun8i-h3-libretech-all-h3-cc.dtb \ - sun8i-h3-mapleboard-mp130.dtb \ - sun8i-h3-nanopi-duo2.dtb \ - sun8i-h3-nanopi-m1.dtb\ - \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ - sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ - sun8i-h3-orangepi-pc.dtb \ - sun8i-h3-orangepi-pc-plus.dtb \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ - sun8i-h3-zeropi.dtb \ - sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ - sun8i-r16-parrot.dtb \ - sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-r40-oka40i-c.dtb \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-lichee-zero-plus.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-t113s-mangopi-mq-r-t113.dtb \ - sun8i-t3-cqa3t-bv3.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb \ - sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb From 532857c2a76ba3553302cf2a2cbec7679fb5b4fe Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Jun 2024 12:20:46 -0500 Subject: [PATCH 09/16] dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks Add the required clock bindings for the GPADC. Signed-off-by: Chris Morgan Acked-by: Jernej Skrabec Reviewed-by: Andre Przywara Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + include/dt-bindings/reset/sun50i-h616-ccu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 6f8f01e67628..ebb146ab7f8c 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -112,5 +112,6 @@ #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 +#define CLK_BUS_GPADC 129 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index 1bd8bb0a11be..ed177c04afdd 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -66,5 +66,6 @@ #define RST_BUS_TVE0 57 #define RST_BUS_HDCP 58 #define RST_BUS_KEYADC 59 +#define RST_BUS_GPADC 60 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ From 59678cc9cc54e556f83a58c52aaac8c149edab67 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Jun 2024 12:20:48 -0500 Subject: [PATCH 10/16] arm64: dts: allwinner: h616: Add GPADC device node The H616 has a GPADC controller which is identical to the one found on the D1/T113s/R329/T507 SoCs. Reviewed-by: Andre Przywara Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240605172049.231108-4-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 20564cc02267..b07d7aee1896 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -626,6 +626,17 @@ status = "disabled"; }; + gpadc: adc@5070000 { + compatible = "allwinner,sun50i-h616-gpadc", + "allwinner,sun20i-d1-gpadc"; + reg = <0x05070000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + status = "disabled"; + #io-channel-cells = <1>; + }; + ths: thermal-sensor@5070400 { compatible = "allwinner,sun50i-h616-ths"; reg = <0x05070400 0x400>; From e41e5973bf4559b0918c59d243ba8612f070f854 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Jun 2024 12:20:49 -0500 Subject: [PATCH 11/16] arm64: dts: allwinner: anbernic-rg35xx-h: Add ADC joysticks Add support for the ADC joysticks found on the Anbernic RG35XX-H. The joysticks use one channel of the GPADC which is muxed 4 ways by an ADC mux. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240605172049.231108-5-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai --- .../sun50i-h700-anbernic-rg35xx-h.dts | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts index 63036256917f..ff453336eab1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -9,6 +9,78 @@ / { model = "Anbernic RG35XX H"; compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; + + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_pin>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <4096 0>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <0 4096>; + linux,code = ; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <0 4096>; + linux,code = ; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <4096 0>; + linux,code = ; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "left_y", "right_x", "right_y"; + #io-channel-cells = <1>; + io-channels = <&gpadc 0>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&pio 8 1 GPIO_ACTIVE_LOW>, + <&pio 8 2 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; +}; + +&gpadc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + }; }; &gpio_keys_gamepad { @@ -34,3 +106,10 @@ &ohci1 { status = "okay"; }; + +&pio { + joy_mux_pin: joy-mux-pin { + pins = "PI0"; + function = "gpio_out"; + }; +}; From b05f15d0fc15a21ffe480226b02d9352bddfa2e5 Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Fri, 7 Jun 2024 21:20:34 +1200 Subject: [PATCH 12/16] arm64: dts: allwinner: h616: add additional CPU OPPs for the H700 The H700 now shows stable operation with the 1.008, 1.032 and 1.512 GHz DVFS operating points. The 1.5GHz OPP requires a VDD-CPU of 1.16V, obtained from the vendor BSP. This voltage is slightly above the recommended operating voltage for the H616 (H700 datasheet not publicly available) but well within the absolute maximum of 1.3V. Add the additional 1.032 GHz operating point to the H616 CPU-OPP table, and enable the 1.008 and 1.512 points for the H700. Signed-off-by: Ryan Walklin Tested-by: Philippe Simons Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240607092140.33112-3-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun50i-h616-cpu-opp.dtsi | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi index aca22a7f0191..dd10aaf472b6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi @@ -11,7 +11,7 @@ opp-hz = /bits/ 64 <480000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; }; opp-600000000 { @@ -25,7 +25,7 @@ opp-hz = /bits/ 64 <720000000>; opp-microvolt = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-792000000 { @@ -50,8 +50,16 @@ opp-microvolt-speed2 = <950000>; opp-microvolt-speed3 = <950000>; opp-microvolt-speed4 = <1020000>; + opp-microvolt-speed5 = <900000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; + }; + + opp-1032000000 { + opp-hz = /bits/ 64 <1032000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x20>; }; opp-1104000000 { @@ -59,8 +67,9 @@ opp-microvolt-speed0 = <1000000>; opp-microvolt-speed2 = <1000000>; opp-microvolt-speed3 = <1000000>; + opp-microvolt-speed5 = <950000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-1200000000 { @@ -70,8 +79,9 @@ opp-microvolt-speed2 = <1050000>; opp-microvolt-speed3 = <1050000>; opp-microvolt-speed4 = <1100000>; + opp-microvolt-speed5 = <1020000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x1f>; + opp-supported-hw = <0x3f>; }; opp-1320000000 { @@ -85,15 +95,16 @@ opp-hz = /bits/ 64 <1416000000>; opp-microvolt = <1100000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0d>; + opp-supported-hw = <0x2d>; }; opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-microvolt-speed1 = <1100000>; opp-microvolt-speed3 = <1100000>; + opp-microvolt-speed5 = <1160000>; clock-latency-ns = <244144>; /* 8 32k periods */ - opp-supported-hw = <0x0a>; + opp-supported-hw = <0x2a>; }; }; }; From e1e61fe3452d511e53aa50720833148b11719269 Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Fri, 7 Jun 2024 21:20:35 +1200 Subject: [PATCH 13/16] arm64: dts: allwinner: rg35xx: Enable DVFS CPU frequency scaling The Anbernic RG35XX device variants (-2024, -H, -Plus and -SP) are the only currently known devices to have an Allwinner H700 SoC. The closely related RG28XX also has the H700 but a mainline DT for this device has not yet been submitted. Include the H616 CPU OPP table in the base device DTS, and increase the DCDC1 regulator (vdd-cpu) upper voltage range to 1.16V, allowing the CPU to reach 1.5GHz. Signed-off-by: Ryan Walklin Tested-by: Philippe Simons Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240607092140.33112-4-ryan@testtoast.com Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index ee30584b6ad7..afb49e65859f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" - +#include "sun50i-h616-cpu-opp.dtsi" #include #include #include @@ -221,7 +221,7 @@ reg_dcdc1: dcdc1 { regulator-always-on; regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; + regulator-max-microvolt = <1160000>; regulator-name = "vdd-cpu"; }; From 0c85e2e377c368e1e0f04ea28dcbc5aa06302551 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 16 Jun 2024 23:40:56 +0100 Subject: [PATCH 14/16] arm64: dts: allwinner: h616: add IOMMU node The Allwinner H616 contains a scatter-gather IOMMU connected to some video related devices. It's almost compatible to the one used in the H6, though with minor incompatibilities. Add the DT node describing its resources, so that devices like the video or display engine can connect to it. Signed-off-by: Andre Przywara Tested-by: Ryan Walklin Link: https://lore.kernel.org/r/20240616224056.29159-6-andre.przywara@arm.com [wens@csie.org: Move IOMMU node after GIC node for address order] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index b07d7aee1896..bf4d41ecbfdc 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -343,6 +343,15 @@ #interrupt-cells = <3>; }; + iommu: iommu@30f0000 { + compatible = "allwinner,sun50i-h616-iommu"; + reg = <0x030f0000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_IOMMU>; + resets = <&ccu RST_BUS_IOMMU>; + #iommu-cells = <1>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun50i-h616-mmc", "allwinner,sun50i-a100-mmc"; From 8f2cf4442b49365031f62f7d97484989251b0707 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 22 Jun 2024 23:07:30 +0800 Subject: [PATCH 15/16] riscv: dts: allwinner: d1s-t113: Add system LDOs Now that the bindings for the system LDOs have been merged, the nodes for the system LDOs can be added. These are used on the ClockworkPi. This was originally part of Samuel's D1 device tree series [1], but was dropped in v5 as the regulator bindings weren't merged at the time. [1] https://lore.kernel.org/linux-sunxi/20221231233851.24923-1-samuel@sholland.org/ Link: https://lore.kernel.org/r/20240622150731.1105901-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 5a9d7f5a75b4..e4175adb028d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -396,6 +396,17 @@ ranges; #address-cells = <1>; #size-cells = <1>; + + regulators@3000150 { + compatible = "allwinner,sun20i-d1-system-ldos"; + reg = <0x3000150 0x4>; + + reg_ldoa: ldoa { + }; + + reg_ldob: ldob { + }; + }; }; dma: dma-controller@3002000 { From 0ce1d34678e5d214746ee4887f9f7714c39e331f Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 22 Jun 2024 23:07:31 +0800 Subject: [PATCH 16/16] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible "ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC. The R-01 contains only the CPU, DRAM, and always-on voltage regulation; it does not merit a separate devicetree. The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an X-Powers AXP228 PMIC for managing a Li-ion battery. The DevTerm is a complete system which extends the ClockworkPi mainboard with a MIPI-DSI panel and a pair of expansion boards. These expansion boards provide a fan, a USB keyboard, speakers, and a thermal printer. Acked-by: Palmer Dabbelt Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20240622150731.1105901-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/Makefile | 2 + .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 252 ++++++++++++++++++ .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 36 +++ 3 files changed, 290 insertions(+) create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile index 87f70b1af6b4..1c91be38ea16 100644 --- a/arch/riscv/boot/dts/allwinner/Makefile +++ b/arch/riscv/boot/dts/allwinner/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts new file mode 100644 index 000000000000..750aec6cf2f2 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include + +/dts-v1/; + +#include "sun20i-d1.dtsi" +#include "sun20i-common-regulators.dtsi" + +/ { + model = "ClockworkPi v3.14 (R-01)"; + compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1"; + + aliases { + ethernet0 = &ap6256; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* + * This regulator is PWM-controlled, but the PWM controller is not + * yet supported, so fix the regulator to its default voltage. + */ + reg_vdd_cpu: vdd-cpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <®_vcc>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */ + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu>; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pb10_pins>; + pinctrl-names = "default"; + status = "okay"; + + axp221: pmic@34 { + compatible = "x-powers,axp228", "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */ + interrupt-controller; + #interrupt-cells = <1>; + + ac_power_supply: ac-power { + compatible = "x-powers,axp221-ac-power-supply"; + }; + + axp_adc: adc { + compatible = "x-powers,axp221-adc"; + #io-channel-cells = <1>; + }; + + battery_power_supply: battery-power { + compatible = "x-powers,axp221-battery-power-supply"; + }; + + axp_gpio: gpio { + compatible = "x-powers,axp221-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + regulators { + x-powers,dcdc-freq = <3000>; + + reg_dcdc1: dcdc1 { + regulator-name = "sys-3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_dcdc3: dcdc3 { + regulator-name = "sys-1v8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_aldo1: aldo1 { + regulator-name = "aud-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_aldo2: aldo2 { + regulator-name = "disp-3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_aldo3: aldo3 { + regulator-name = "vdd-wifi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* DLDO1 and ELDO1-3 are connected in parallel. */ + reg_dldo1: dldo1 { + regulator-name = "vbat-wifi-a"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* DLDO2-DLDO4 are connected in parallel. */ + reg_dldo2: dldo2 { + regulator-name = "vcc-3v3-ext-a"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_dldo3: dldo3 { + regulator-name = "vcc-3v3-ext-b"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_dldo4: dldo4 { + regulator-name = "vcc-3v3-ext-c"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_eldo1: eldo1 { + regulator-name = "vbat-wifi-b"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_eldo2: eldo2 { + regulator-name = "vbat-wifi-c"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_eldo3: eldo3 { + regulator-name = "vbat-wifi-d"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + usb_power_supply: usb-power { + compatible = "x-powers,axp221-usb-power-supply"; + status = "disabled"; + }; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_vcc_3v3>; + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo3>; + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + status = "okay"; + + ap6256: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pg-supply = <®_ldoa>; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb8_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + interrupt-parent = <&pio>; + interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */ + device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */ + shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */ + max-speed = <1500000>; + vbat-supply = <®_dldo1>; + vddio-supply = <®_aldo3>; + }; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb0_vbus_power-supply = <&ac_power_supply>; + usb1_vbus-supply = <®_vcc>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts new file mode 100644 index 000000000000..bc5c84f22762 --- /dev/null +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Samuel Holland + +#include "sun20i-d1-clockworkpi-v3.14.dts" + +/ { + model = "Clockwork DevTerm (R-01)"; + compatible = "clockwork,r-01-devterm-v3.14", + "clockwork,r-01-clockworkpi-v3.14", + "allwinner,sun20i-d1"; + + fan { + compatible = "gpio-fan"; + gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */ + gpio-fan,speed-map = <0 0>, + <6000 1>; + #cooling-cells = <2>; + }; + + i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */ + scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */ + #address-cells = <1>; + #size-cells = <0>; + + adc@54 { + compatible = "ti,adc101c"; + reg = <0x54>; + interrupt-parent = <&pio>; + interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */ + vref-supply = <®_dldo2>; + #io-channel-cells = <1>; + }; + }; +};