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xusb: bulk commit to split

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This commit is contained in:
Thomas Makin
2025-11-08 03:19:00 +00:00
parent a67ac5bf97
commit 8f6969be89
8 changed files with 113 additions and 9 deletions
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12
arch/arm64/boot/dts/nvidia/tegra210b01.dtsi
View File

@@ -4,6 +4,10 @@
/ {
compatible = "nvidia,tegra210b01", "nvidia,tegra210";
pcie@1003000 {
compatible = "nvidia,tegra210b01-pcie";
};
host1x@50000000 {
/delete-node/ sor@54540000;
/delete-node/ dpaux@545c0000;
@@ -119,6 +123,14 @@
padctl@7009f000 {
compatible = "nvidia,tegra210b01-xusb-padctl";
pads {
pcie {
clocks = <&tegra_car TEGRA210_CLK_PLL_E>,
<&tegra_car TEGRA210_CLK_PLL_P_UPHY_OUT>;
clock-names = "pll", "uphy_mgmt";
};
};
};
pinmux@700008d4 {

1
drivers/pci/controller/pci-tegra.c
View File

@@ -3003,7 +3003,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct pci_host_bridge *host;
struct tegra_pcie_port *port;
struct tegra_pcie *pcie;
int err;

36
drivers/phy/tegra/xusb-tegra210.c
View File

@@ -489,6 +489,32 @@ static int t210b01_compatible(struct tegra_xusb_padctl *padctl)
return 0;
}
static bool plle_hw_sequence_is_enabled(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
return tegra210b01_plle_hw_sequence_is_enabled();
return tegra210_plle_hw_sequence_is_enabled();
}
static int plle_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
return tegra210b01_plle_hw_sequence_start();
return tegra210_plle_hw_sequence_start();
}
static void xusb_pll_hw_control_enable(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
tegra210b01_xusb_pll_hw_control_enable();
else
return tegra210_xusb_pll_hw_control_enable();
}
static void xusb_pll_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
if (t210b01_compatible(padctl))
tegra210b01_xusb_pll_hw_sequence_start();
else
tegra210_xusb_pll_hw_sequence_start();
}
static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
{
const struct tegra_xusb_lane_map *map;
@@ -529,7 +555,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
return err;
}
if (tegra210_plle_hw_sequence_is_enabled())
if (plle_hw_sequence_is_enabled(padctl))
goto skip_pll_init;
err = reset_control_deassert(pcie->rst);
@@ -708,7 +734,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
tegra210_xusb_pll_hw_control_enable();
xusb_pll_hw_control_enable(padctl);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
@@ -724,7 +750,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
usleep_range(10, 20);
tegra210_xusb_pll_hw_sequence_start();
xusb_pll_hw_sequence_start(padctl);
skip_pll_init:
pcie->enable = true;
@@ -1077,8 +1103,8 @@ static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
if (padctl->sata)
tegra210_sata_uphy_enable(padctl);
if (!tegra210_plle_hw_sequence_is_enabled())
tegra210_plle_hw_sequence_start();
if (!plle_hw_sequence_is_enabled(padctl))
plle_hw_sequence_start(padctl);
else
dev_dbg(padctl->dev, "PLLE is already in HW control\n");

1
drivers/phy/tegra/xusb.h
View File

@@ -244,6 +244,7 @@ struct tegra_xusb_pcie_pad {
struct reset_control *rst;
struct clk *pll;
struct clk *uphy_mgmt_clk;
bool enable;
};

13
drivers/usb/host/xhci-tegra.c
View File

@@ -2546,27 +2546,34 @@ static const struct tegra_xusb_soc tegra210_soc = {
};
MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
static const struct tegra_xusb_phy_type tegra210b01_phy_types[] = {
{ .name = "usb3", .num = 4, },
{ .name = "usb2", .num = 4, },
};
static const struct tegra_xusb_soc tegra210b01_soc = {
.firmware = "nvidia/tegra210b01/xusb.bin",
.supply_names = tegra210_supply_names,
.num_supplies = ARRAY_SIZE(tegra210_supply_names),
.phy_types = tegra210_phy_types,
.num_types = ARRAY_SIZE(tegra210_phy_types),
.phy_types = tegra210b01_phy_types,
.num_types = ARRAY_SIZE(tegra210b01_phy_types),
.context = &tegra124_xusb_context,
.ports = {
.usb2 = { .offset = 4, .count = 4, },
.hsic = { .offset = 8, .count = 1, },
.usb3 = { .offset = 0, .count = 4, },
},
.scale_ss_clock = false,
.has_ipfs = true,
.otg_reset_sspi = true,
.ops = &tegra124_ops,
.mbox = {
.cmd = 0xe4,
.data_in = 0xe8,
.data_out = 0xec,
.owner = 0xf0,
.smi_intr = XUSB_CFG_ARU_SMI_INTR,
},
.lpm_support = false,
};
MODULE_FIRMWARE("nvidia/tegra210b01/xusb.bin");

50
gki/aarch64/abi.stg
View File

@@ -487077,6 +487077,15 @@ elf_symbol {
type_id: 0x578fa618
full_name: "pci_find_next_capability"
}
elf_symbol {
id: 0xbbf8a63b
name: "pci_flags"
is_defined: true
symbol_type: OBJECT
crc: 0xf296206e
type_id: 0x4585663f
full_name: "pci_flags"
}
elf_symbol {
id: 0x08190210
name: "pci_free_irq"
@@ -504837,6 +504846,42 @@ elf_symbol {
type_id: 0x10985193
full_name: "tegra210_xusb_pll_hw_sequence_start"
}
elf_symbol {
id: 0xd2118b04
name: "tegra210b01_plle_hw_sequence_is_enabled"
is_defined: true
symbol_type: FUNCTION
crc: 0x5e505530
type_id: 0xfea45b04
full_name: "tegra210b01_plle_hw_sequence_is_enabled"
}
elf_symbol {
id: 0x56591275
name: "tegra210b01_plle_hw_sequence_start"
is_defined: true
symbol_type: FUNCTION
crc: 0x7851be11
type_id: 0x9d80e32f
full_name: "tegra210b01_plle_hw_sequence_start"
}
elf_symbol {
id: 0xa6a8ece8
name: "tegra210b01_xusb_pll_hw_control_enable"
is_defined: true
symbol_type: FUNCTION
crc: 0xd272d446
type_id: 0x10985193
full_name: "tegra210b01_xusb_pll_hw_control_enable"
}
elf_symbol {
id: 0xc1ac282e
name: "tegra210b01_xusb_pll_hw_sequence_start"
is_defined: true
symbol_type: FUNCTION
crc: 0xd272d446
type_id: 0x10985193
full_name: "tegra210b01_xusb_pll_hw_sequence_start"
}
elf_symbol {
id: 0xe54ea1f3
name: "tegra_bpmp_free_mrq"
@@ -522102,6 +522147,7 @@ interface {
symbol_id: 0x780d1110
symbol_id: 0xbbb674cc
symbol_id: 0xdea420f5
symbol_id: 0xbbf8a63b
symbol_id: 0x08190210
symbol_id: 0x8ffabaa9
symbol_id: 0x50bce06e
@@ -524075,6 +524121,10 @@ interface {
symbol_id: 0xdfb56896
symbol_id: 0x72c26996
symbol_id: 0x7ac45534
symbol_id: 0xd2118b04
symbol_id: 0x56591275
symbol_id: 0xa6a8ece8
symbol_id: 0xc1ac282e
symbol_id: 0xe54ea1f3
symbol_id: 0x4a1dceb2
symbol_id: 0xa2565005

5
gki/aarch64/symbols/tegra
View File

@@ -2070,6 +2070,7 @@
irq_set_chained_handler_and_data
of_irq_parse_and_map_pci
of_pci_get_devfn
pci_flags
pci_generic_config_read32
pci_generic_config_write32
pci_host_probe
@@ -2125,6 +2126,10 @@
phy_destroy
regulator_get
regulator_put
tegra210b01_plle_hw_sequence_is_enabled
tegra210b01_plle_hw_sequence_start
tegra210b01_xusb_pll_hw_control_enable
tegra210b01_xusb_pll_hw_sequence_start
tegra210_plle_hw_sequence_is_enabled
tegra210_plle_hw_sequence_start
tegra210_sata_pll_hw_control_enable

4
include/linux/clk/tegra.h
View File

@@ -208,9 +208,13 @@ tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
#ifdef CONFIG_ARCH_TEGRA_210_SOC
int tegra210_plle_hw_sequence_start(void);
int tegra210b01_plle_hw_sequence_start(void);
bool tegra210_plle_hw_sequence_is_enabled(void);
bool tegra210b01_plle_hw_sequence_is_enabled(void);
void tegra210_xusb_pll_hw_control_enable(void);
void tegra210b01_xusb_pll_hw_control_enable(void);
void tegra210_xusb_pll_hw_sequence_start(void);
void tegra210b01_xusb_pll_hw_sequence_start(void);
void tegra210_sata_pll_hw_control_enable(void);
void tegra210_sata_pll_hw_sequence_start(void);
void tegra210_set_sata_pll_seq_sw(bool state);