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[POWERPC] spufs: use #defines for SPU class [012] exception status

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Add a few #defines for the class 0, 1 and 2 interrupt status bits, and
use them instead of magic numbers when we're setting or checking for
these interrupts.

Also, add a #define for the class 2 mailbox threshold interrupt mask.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Jeremy Kerr
2007-12-20 16:39:59 +09:00
committed by Paul Mackerras
parent c40aa47104
commit 8af30675c3
4 changed files with 54 additions and 33 deletions
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include/asm-powerpc/spu.h
+14
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@@ -527,8 +527,22 @@ struct spu_priv1 {
#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
u8 pad_0x118_0x140[0x28]; /* 0x118 */
u64 int_stat_RW[3]; /* 0x140 */
#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
#define CLASS0_SPU_ERROR_INTR 0x4L
#define CLASS0_INTR_MASK 0x7L
#define CLASS1_SEGMENT_FAULT_INTR 0x1L
#define CLASS1_STORAGE_FAULT_INTR 0x2L
#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
#define CLASS2_MAILBOX_INTR 0x1L
#define CLASS2_SPU_STOP_INTR 0x2L
#define CLASS2_SPU_HALT_INTR 0x4L
#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
u8 pad_0x158_0x180[0x28]; /* 0x158 */
u64 int_route_RW; /* 0x180 */