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Merge tag 'v6.4-rc1' into android-mainline

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Linux 6.4-rc1

Change-Id: I009b12376eefeec4f7570017f5e240226089eafe
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2023-06-19 17:22:18 +00:00
parent 050a58a4d0 ac9a78681b
commit 89c0d89828
3290 changed files with 288030 additions and 207940 deletions
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.clang-format
-1
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@@ -521,7 +521,6 @@ ForEachMacros:
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'pci_dev_for_each_resource'
- 'pci_doe_for_each_off'
- 'pcl_for_each_chunk'
- 'pcl_for_each_segment'
- 'pcm_for_each_format'
.mailmap
+5 -1
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@@ -213,7 +213,10 @@ Jeff Garzik <jgarzik@pretzel.yyz.us>
Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net>
Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com>
Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
Jens Axboe <axboe@suse.de>
Jens Axboe <axboe@kernel.dk> <axboe@suse.de>
Jens Axboe <axboe@kernel.dk> <jens.axboe@oracle.com>
Jens Axboe <axboe@kernel.dk> <axboe@fb.com>
Jens Axboe <axboe@kernel.dk> <axboe@meta.com>
Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Jessica Zhang <quic_jesszhan@quicinc.com> <jesszhan@codeaurora.org>
@@ -328,6 +331,7 @@ Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
Mayuresh Janorkar <mayur@ti.com>
Michael Buesch <m@bues.ch>
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
Michel Dänzer <michel@tungstengraphics.com>
Michel Lespinasse <michel@lespinasse.org>
Michel Lespinasse <michel@lespinasse.org> <walken@google.com>
CREDITS
+2 -2
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@@ -2510,8 +2510,8 @@ D: XF86_8514
D: cfdisk (curses based disk partitioning program)
N: Mat Martineau
E: mat@martineau.name
D: MPTCP subsystem co-maintainer 2020-2023
E: martineau@kernel.org
D: MPTCP subsystem co-maintainer
D: Keyctl restricted keyring and Diffie-Hellman UAPI
D: Bluetooth L2CAP ERTM mode and AMP
S: USA
Documentation/ABI/stable/sysfs-driver-dma-idxd
+51
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@@ -136,6 +136,22 @@ Description: The last executed device administrative command's status/error.
Also last configuration error overloaded.
Writing to it will clear the status.
What: /sys/bus/dsa/devices/dsa<m>/iaa_cap
Date: Sept 14, 2022
KernelVersion: 6.0.0
Contact: dmaengine@vger.kernel.org
Description: IAA (IAX) capability mask. Exported to user space for application
consumption. This attribute should only be visible on IAA devices
that are version 2 or later.
What: /sys/bus/dsa/devices/dsa<m>/event_log_size
Date: Sept 14, 2022
KernelVersion: 6.4.0
Contact: dmaengine@vger.kernel.org
Description: The event log size to be configured. Default is 64 entries and
occupies 4k size if the evl entry is 64 bytes. It's visible
only on platforms that support the capability.
What: /sys/bus/dsa/devices/wq<m>.<n>/block_on_fault
Date: Oct 27, 2020
KernelVersion: 5.11.0
@@ -219,6 +235,16 @@ Contact: dmaengine@vger.kernel.org
Description: Indicate whether ATS disable is turned on for the workqueue.
0 indicates ATS is on, and 1 indicates ATS is off for the workqueue.
What: /sys/bus/dsa/devices/wq<m>.<n>/prs_disable
Date: Sept 14, 2022
KernelVersion: 6.4.0
Contact: dmaengine@vger.kernel.org
Description: Controls whether PRS disable is turned on for the workqueue.
0 indicates PRS is on, and 1 indicates PRS is off for the
workqueue. This option overrides block_on_fault attribute
if set. It's visible only on platforms that support the
capability.
What: /sys/bus/dsa/devices/wq<m>.<n>/occupancy
Date May 25, 2021
KernelVersion: 5.14.0
@@ -302,3 +328,28 @@ Description: Allows control of the number of batch descriptors that can be
1 (1/2 of max value), 2 (1/4 of the max value), and 3 (1/8 of
the max value). It's visible only on platforms that support
the capability.
What: /sys/bus/dsa/devices/wq<m>.<n>/dsa<x>\!wq<m>.<n>/file<y>/cr_faults
Date: Sept 14, 2022
KernelVersion: 6.4.0
Contact: dmaengine@vger.kernel.org
Description: Show the number of Completion Record (CR) faults this application
has caused.
What: /sys/bus/dsa/devices/wq<m>.<n>/dsa<x>\!wq<m>.<n>/file<y>/cr_fault_failures
Date: Sept 14, 2022
KernelVersion: 6.4.0
Contact: dmaengine@vger.kernel.org
Description: Show the number of Completion Record (CR) faults failures that this
application has caused. The failure counter is incremented when the
driver cannot fault in the address for the CR. Typically this is caused
by a bad address programmed in the submitted descriptor or a malicious
submitter is using bad CR address on purpose.
What: /sys/bus/dsa/devices/wq<m>.<n>/dsa<x>\!wq<m>.<n>/file<y>/pid
Date: Sept 14, 2022
KernelVersion: 6.4.0
Contact: dmaengine@vger.kernel.org
Description: Show the process id of the application that opened the file. This is
helpful information for a monitor daemon that wants to kill the
application that opened the file.
Documentation/ABI/testing/debugfs-cxl
+35
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@@ -0,0 +1,35 @@
What: /sys/kernel/debug/cxl/memX/inject_poison
Date: April, 2023
KernelVersion: v6.4
Contact: linux-cxl@vger.kernel.org
Description:
(WO) When a Device Physical Address (DPA) is written to this
attribute, the memdev driver sends an inject poison command to
the device for the specified address. The DPA must be 64-byte
aligned and the length of the injected poison is 64-bytes. If
successful, the device returns poison when the address is
accessed through the CXL.mem bus. Injecting poison adds the
address to the device's Poison List and the error source is set
to Injected. In addition, the device adds a poison creation
event to its internal Informational Event log, updates the
Event Status register, and if configured, interrupts the host.
It is not an error to inject poison into an address that
already has poison present and no error is returned. The
inject_poison attribute is only visible for devices supporting
the capability.
What: /sys/kernel/debug/memX/clear_poison
Date: April, 2023
KernelVersion: v6.4
Contact: linux-cxl@vger.kernel.org
Description:
(WO) When a Device Physical Address (DPA) is written to this
attribute, the memdev driver sends a clear poison command to
the device for the specified address. Clearing poison removes
the address from the device's Poison List and writes 0 (zero)
for 64 bytes starting at address. It is not an error to clear
poison from an address that does not have poison set. If the
device cannot clear poison from the address, -ENXIO is returned.
The clear_poison attribute is only visible for devices
supporting the capability.
Documentation/ABI/testing/sysfs-bus-counter
+32
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@@ -1,3 +1,33 @@
What: /sys/bus/counter/devices/counterX/cascade_counts_enable
KernelVersion: 6.4
Contact: linux-iio@vger.kernel.org
Description:
Indicates the cascading of Counts on Counter X.
Valid attribute values are boolean.
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select
KernelVersion: 6.4
Contact: linux-iio@vger.kernel.org
Description:
Selects the external clock pin for phase counting mode of
Counter X.
MTCLKA-MTCLKB:
MTCLKA and MTCLKB pins are selected for the external
phase clock.
MTCLKC-MTCLKD:
MTCLKC and MTCLKD pins are selected for the external
phase clock.
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_available
KernelVersion: 6.4
Contact: linux-iio@vger.kernel.org
Description:
Discrete set of available values for the respective device
configuration are listed in this file.
What: /sys/bus/counter/devices/counterX/countY/count
KernelVersion: 5.2
Contact: linux-iio@vger.kernel.org
@@ -215,6 +245,8 @@ Contact: linux-iio@vger.kernel.org
Description:
This attribute indicates the number of overflows of count Y.
What: /sys/bus/counter/devices/counterX/cascade_counts_enable_component_id
What: /sys/bus/counter/devices/counterX/external_input_phase_clock_select_component_id
What: /sys/bus/counter/devices/counterX/countY/capture_component_id
What: /sys/bus/counter/devices/counterX/countY/ceiling_component_id
What: /sys/bus/counter/devices/counterX/countY/floor_component_id
Documentation/ABI/testing/sysfs-bus-cxl
+14
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@@ -415,3 +415,17 @@ Description:
1), and checks that the hardware accepts the commit request.
Reading this value indicates whether the region is committed or
not.
What: /sys/bus/cxl/devices/memX/trigger_poison_list
Date: April, 2023
KernelVersion: v6.4
Contact: linux-cxl@vger.kernel.org
Description:
(WO) When a boolean 'true' is written to this attribute the
memdev driver retrieves the poison list from the device. The
list consists of addresses that are poisoned, or would result
in poison if accessed, and the source of the poison. This
attribute is only visible for devices supporting the
capability. The retrieved errors are logged as kernel
events when cxl_poison event tracing is enabled.
Documentation/ABI/testing/sysfs-kernel-iommu_groups
-1
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@@ -53,7 +53,6 @@ Description: /sys/kernel/iommu_groups/<grp_id>/type shows the type of default
The default domain type of a group may be modified only when
- The group has only one device.
- The device in the group is not bound to any device driver.
So, the users must unbind the appropriate driver before
changing the default domain type.
Documentation/accounting/psi.rst
+4
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@@ -105,6 +105,10 @@ prevent overly frequent polling. Max limit is chosen as a high enough number
after which monitors are most likely not needed and psi averages can be used
instead.
Unprivileged users can also create monitors, with the only limitation that the
window size must be a multiple of 2s, in order to prevent excessive resource
usage.
When activated, psi monitor stays active for at least the duration of one
tracking window to avoid repeated activations/deactivations when system is
bouncing in and out of the stall state.
Documentation/admin-guide/blockdev/nbd.rst
+1 -1
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@@ -14,7 +14,7 @@ to borrow disk space from another computer.
Unlike NFS, it is possible to put any filesystem on it, etc.
For more information, or to download the nbd-client and nbd-server
tools, go to http://nbd.sf.net/.
tools, go to https://github.com/NetworkBlockDevice/nbd.
The nbd kernel module need only be installed on the client
system, as the nbd-server is completely in userspace. In fact,
Documentation/admin-guide/cgroup-v1/cpusets.rst
+1 -1
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@@ -719,7 +719,7 @@ There are ways to query or modify cpusets:
cat, rmdir commands from the shell, or their equivalent from C.
- via the C library libcpuset.
- via the C library libcgroup.
(http://sourceforge.net/projects/libcg/)
(https://github.com/libcgroup/libcgroup/)
- via the python application cset.
(http://code.google.com/p/cpuset/)
Documentation/admin-guide/kernel-parameters.txt
+12 -10
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@@ -912,15 +912,14 @@
cs89x0_media= [HW,NET]
Format: { rj45 | aui | bnc }
csdlock_debug= [KNL] Enable debug add-ons of cross-CPU function call
handling. When switched on, additional debug data is
printed to the console in case a hanging CPU is
detected, and that CPU is pinged again in order to try
to resolve the hang situation.
0: disable csdlock debugging (default)
1: enable basic csdlock debugging (minor impact)
ext: enable extended csdlock debugging (more impact,
but more data)
csdlock_debug= [KNL] Enable or disable debug add-ons of cross-CPU
function call handling. When switched on,
additional debug data is printed to the console
in case a hanging CPU is detected, and that
CPU is pinged again in order to try to resolve
the hang situation. The default value of this
option depends on the CSD_LOCK_WAIT_DEBUG_DEFAULT
Kconfig option.
dasd= [HW,NET]
See header of drivers/s390/block/dasd_devmap.c.
@@ -3617,7 +3616,10 @@
emulation library even if a 387 maths coprocessor
is present.
no5lvl [X86-64] Disable 5-level paging mode. Forces
no4lvl [RISCV] Disable 4-level and 5-level paging modes. Forces
kernel to use 3-level paging instead.
no5lvl [X86-64,RISCV] Disable 5-level paging mode. Forces
kernel to use 4-level paging instead.
noaliencache [MM, NUMA, SLAB] Disables the allocation of alien
Documentation/admin-guide/mm/ksm.rst
+1 -1
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@@ -20,7 +20,7 @@ content which can be replaced by a single write-protected page (which
is automatically copied if a process later wants to update its
content). The amount of pages that KSM daemon scans in a single pass
and the time between the passes are configured using :ref:`sysfs
intraface <ksm_sysfs>`
interface <ksm_sysfs>`
KSM only merges anonymous (private) pages, never pagecache (file) pages.
KSM's merged pages were originally locked into kernel memory, but can now
Documentation/admin-guide/xfs.rst
+4 -3
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@@ -236,13 +236,14 @@ the dates listed above.
Deprecated Mount Options
========================
=========================== ================
============================ ================
Name Removal Schedule
=========================== ================
============================ ================
Mounting with V4 filesystem September 2030
Mounting ascii-ci filesystem September 2030
ikeep/noikeep September 2025
attr2/noattr2 September 2025
=========================== ================
============================ ================
Removed Mount Options
Documentation/arch/x86/kernel-stacks.rst
+1 -1
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@@ -12,7 +12,7 @@ Most of the text from Keith Owens, hacked by AK
x86_64 page size (PAGE_SIZE) is 4K.
Like all other architectures, x86_64 has a kernel stack for every
active thread. These thread stacks are THREAD_SIZE (2*PAGE_SIZE) big.
active thread. These thread stacks are THREAD_SIZE (4*PAGE_SIZE) big.
These stacks contain useful data as long as a thread is alive or a
zombie. While the thread is in user space the kernel stack is empty
except for the thread_info structure at the bottom.
Documentation/arch/x86/sva.rst
+1 -1
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@@ -107,7 +107,7 @@ process share the same page tables, thus the same MSR value.
PASID Life Cycle Management
===========================
PASID is initialized as INVALID_IOASID (-1) when a process is created.
PASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.
Only processes that access SVA-capable devices need to have a PASID
allocated. This allocation happens when a process opens/binds an SVA-capable
Documentation/bpf/prog_lsm.rst
+1 -1
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@@ -18,7 +18,7 @@ LSM hook:
.. c:function:: int file_mprotect(struct vm_area_struct *vma, unsigned long reqprot, unsigned long prot);
Other LSM hooks which can be instrumented can be found in
``include/linux/lsm_hooks.h``.
``security/security.c``.
eBPF programs that use Documentation/bpf/btf.rst do not need to include kernel
headers for accessing information from the attached eBPF program's context.
Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
-49
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@@ -1,49 +0,0 @@
Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of:
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the first element specifies the base address and size of
the register region. An optional second element specifies
the base address and size of the alias register region.
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the pll parents.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "pll8_vote", "pxo".
- clock-output-names:
Usage: optional
Value type: <string>
Definition: Name of the output clock. Typically acpuX_aux where X is a
CPU number starting at 0.
Example:
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x02088000 0x1000>,
<0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
};
Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
-44
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@@ -1,44 +0,0 @@
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: should be one of the following. The generic compatible
"qcom,kpss-gcc" should also be included.
"qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
"qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
"qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
"qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: base address and size of the register region
- clocks:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to the pll parents.
- clock-names:
Usage: required
Value type: <stringlist>
Definition: must be "pll8_vote", "pxo".
- clock-output-names:
Usage: required
Value type: <string>
Definition: Name of the output clock. Typically acpu_l2_aux indicating
an L2 cache auxiliary clock.
Example:
l2cc: clock-controller@2011000 {
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu_l2_aux";
};
Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml
+40
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@@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
properties:
compatible:
const: brcm,bcm63268-timer-clocks
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
timer_clk: clock-controller@100000ac {
compatible = "brcm,bcm63268-timer-clocks";
reg = <0x100000ac 0x4>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml
+79
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@@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP AudioMIX Block Control Binding
maintainers:
- Marek Vasut <marex@denx.de>
description: |
NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
used to control Audio related clock on the SoC.
properties:
compatible:
const: fsl,imx8mp-audio-blk-ctrl
reg:
maxItems: 1
power-domains:
maxItems: 1
clocks:
minItems: 7
maxItems: 7
clock-names:
items:
- const: ahb
- const: sai1
- const: sai2
- const: sai3
- const: sai5
- const: sai6
- const: sai7
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
clock-controller@30e20000 {
compatible = "fsl,imx8mp-audio-blk-ctrl";
reg = <0x30e20000 0x10000>;
#clock-cells = <1>;
clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
<&clk IMX8MP_CLK_SAI1>,
<&clk IMX8MP_CLK_SAI2>,
<&clk IMX8MP_CLK_SAI3>,
<&clk IMX8MP_CLK_SAI5>,
<&clk IMX8MP_CLK_SAI6>,
<&clk IMX8MP_CLK_SAI7>;
clock-names = "ahb",
"sai1", "sai2", "sai3",
"sai5", "sai6", "sai7";
power-domains = <&pgc_audio>;
};
...
Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml
+45
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@@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-1 Clock Controller
maintainers:
- Keguang Zhang <keguang.zhang@gmail.com>
properties:
compatible:
enum:
- loongson,ls1b-clk
- loongson,ls1c-clk
reg:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
clkc: clock-controller@1fe78030 {
compatible = "loongson,ls1b-clk";
reg = <0x1fe78030 0x8>;
clocks = <&xtal>;
#clock-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
+6 -1
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@@ -16,7 +16,12 @@ description: |
properties:
compatible:
const: mediatek,mt8186-fhctl
enum:
- mediatek,mt6795-fhctl
- mediatek,mt8173-fhctl
- mediatek,mt8186-fhctl
- mediatek,mt8192-fhctl
- mediatek,mt8195-fhctl
reg:
maxItems: 1
Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
+71
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@@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8188
maintainers:
- Garmin Chang <garmin.chang@mediatek.com>
description: |
The clock architecture in MediaTek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The devices provide clock gate control in different IP blocks.
properties:
compatible:
enum:
- mediatek,mt8188-adsp-audio26m
- mediatek,mt8188-camsys
- mediatek,mt8188-camsys-rawa
- mediatek,mt8188-camsys-rawb
- mediatek,mt8188-camsys-yuva
- mediatek,mt8188-camsys-yuvb
- mediatek,mt8188-ccusys
- mediatek,mt8188-imgsys
- mediatek,mt8188-imgsys-wpe1
- mediatek,mt8188-imgsys-wpe2
- mediatek,mt8188-imgsys-wpe3
- mediatek,mt8188-imgsys1-dip-nr
- mediatek,mt8188-imgsys1-dip-top
- mediatek,mt8188-imp-iic-wrap-c
- mediatek,mt8188-imp-iic-wrap-en
- mediatek,mt8188-imp-iic-wrap-w
- mediatek,mt8188-ipesys
- mediatek,mt8188-mfgcfg
- mediatek,mt8188-vdecsys
- mediatek,mt8188-vdecsys-soc
- mediatek,mt8188-vencsys
- mediatek,mt8188-vppsys0
- mediatek,mt8188-vppsys1
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@11283000 {
compatible = "mediatek,mt8188-imp-iic-wrap-c";
reg = <0x11283000 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
+55
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@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8188
maintainers:
- Garmin Chang <garmin.chang@mediatek.com>
description: |
The clock architecture in MediaTek like below
PLLs -->
dividers -->
muxes
-->
clock gate
The apmixedsys provides most of PLLs which generated from SoC 26m.
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
The mcusys provides mux control to select the clock source in AP MCU.
The device nodes also provide the system control capacity for configuration.
properties:
compatible:
items:
- enum:
- mediatek,mt8188-apmixedsys
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@10000000 {
compatible = "mediatek,mt8188-topckgen", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+1
View File
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,msm8916-a53pll
Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml
+53
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@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ4019
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Robert Marko <robert.markoo@sartura.hr>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ4019.
See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq4019
clocks:
items:
- description: board XO clock
- description: sleep clock
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq4019";
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
};
...
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
+9 -4
View File
@@ -4,20 +4,25 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8909
title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8909.
domains on MSM8909, MSM8917 or QM215.
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8909.h
include/dt-bindings/clock/qcom,gcc-msm8917.h
properties:
compatible:
const: qcom,gcc-msm8909
enum:
- qcom,gcc-msm8909
- qcom,gcc-msm8917
- qcom,gcc-qm215
clocks:
items:
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
-2
View File
@@ -15,7 +15,6 @@ description: |
domains.
See also::
include/dt-bindings/clock/qcom,gcc-ipq4019.h
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
@@ -29,7 +28,6 @@ allOf:
properties:
compatible:
enum:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8953
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
+2
View File
@@ -15,6 +15,7 @@ description: |
See also::
include/dt-bindings/clock/qcom,gpucc-sdm845.h
include/dt-bindings/clock/qcom,gpucc-sa8775p.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h
include/dt-bindings/clock/qcom,gpucc-sc7280.h
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
@@ -27,6 +28,7 @@ properties:
compatible:
enum:
- qcom,sdm845-gpucc
- qcom,sa8775p-gpucc
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
Documentation/devicetree/bindings/clock/qcom,kpss-acc-v1.yaml
+72
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@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
description:
The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region. ACC v1 is currently used as a
clock-controller for enabling the cpu and hanling the aux clocks.
properties:
compatible:
const: qcom,kpss-acc-v1
reg:
items:
- description: Base address and size of the register region
- description: Optional base address and size of the alias register region
minItems: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pll8_vote
- const: pxo
clock-output-names:
description: Name of the aux clock. Krait can have at most 4 cpu.
enum:
- acpu0_aux
- acpu1_aux
- acpu2_aux
- acpu3_aux
'#clock-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- clock-output-names
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
clock-output-names = "acpu0_aux";
#clock-cells = <0>;
};
...
Documentation/devicetree/bindings/clock/qcom,kpss-gcc.yaml
+88
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@@ -0,0 +1,88 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
maintainers:
- Christian Marangi <ansuelsmth@gmail.com>
description:
Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
to control L2 mux (in the current implementation) and provide access
to the kpss-gcc registers.
properties:
compatible:
items:
- enum:
- qcom,kpss-gcc-ipq8064
- qcom,kpss-gcc-apq8064
- qcom,kpss-gcc-msm8974
- qcom,kpss-gcc-msm8960
- qcom,kpss-gcc-msm8660
- qcom,kpss-gcc-mdm9615
- const: qcom,kpss-gcc
- const: syscon
reg:
maxItems: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pll8_vote
- const: pxo
'#clock-cells':
const: 0
required:
- compatible
- reg
if:
properties:
compatible:
contains:
enum:
- qcom,kpss-gcc-ipq8064
- qcom,kpss-gcc-apq8064
- qcom,kpss-gcc-msm8974
- qcom,kpss-gcc-msm8960
then:
required:
- clocks
- clock-names
- '#clock-cells'
else:
properties:
clock: false
clock-names: false
'#clock-cells': false
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
clock-controller@2011000 {
compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
reg = <0x2011000 0x1000>;
clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
clock-names = "pll8_vote", "pxo";
#clock-cells = <0>;
};
- |
clock-controller@2011000 {
compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
reg = <0x02011000 0x1000>;
};
...
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
+2
View File
@@ -31,6 +31,7 @@ properties:
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
@@ -107,6 +108,7 @@ allOf:
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8916
- qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+7
View File
@@ -41,6 +41,12 @@ properties:
- const: qdsp6ss
- const: top_cc
qcom,adsp-pil-mode:
description:
Indicates if the LPASS would be brought out of reset using
remoteproc peripheral loader.
type: boolean
required:
- compatible
- reg
@@ -60,6 +66,7 @@ examples:
reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
qcom,adsp-pil-mode;
#clock-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
+52
View File
@@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM7150
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <davidwronek@gmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM7150
See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h
properties:
compatible:
const: qcom,sm7150-gcc
clocks:
items:
- description: Board XO source
- description: Board XO Active-Only source
- description: Sleep clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm7150-gcc";
reg = <0x00100000 0x001f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/renesas,9series.yaml
+6
View File
@@ -16,6 +16,11 @@ description: |
- 9FGV0241:
0 -- DIF0
1 -- DIF1
- 9FGV0441:
0 -- DIF0
1 -- DIF1
2 -- DIF2
3 -- DIF3
maintainers:
- Marek Vasut <marex@denx.de>
@@ -24,6 +29,7 @@ properties:
compatible:
enum:
- renesas,9fgv0241
- renesas,9fgv0441
reg:
description: I2C device address
Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/N1D (R9A06G032) System Controller
maintainers:
- Gareth Williams <gareth.williams.jx@renesas.com>
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
Documentation/devicetree/bindings/clock/skyworks,si521xx.yaml
+59
View File
@@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/skyworks,si521xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Skyworks Si521xx I2C PCIe clock generators
description: |
The Skyworks Si521xx are I2C PCIe clock generators providing
from 4 to 9 output clocks.
maintainers:
- Marek Vasut <marex@denx.de>
properties:
compatible:
enum:
- skyworks,si52144
- skyworks,si52146
- skyworks,si52147
reg:
const: 0x6b
'#clock-cells':
const: 1
clocks:
items:
- description: XTal input clock
skyworks,out-amplitude-microvolt:
enum: [ 300000, 400000, 500000, 600000, 700000, 800000, 900000, 1000000 ]
description: Output clock signal amplitude
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-generator@6b {
compatible = "skyworks,si52144";
reg = <0x6b>;
#clock-cells = <1>;
clocks = <&ref25m>;
};
};
...
Documentation/devicetree/bindings/dma/apple,admac.yaml
+1
View File
@@ -26,6 +26,7 @@ properties:
- enum:
- apple,t6000-admac
- apple,t8103-admac
- apple,t8112-admac
- const: apple,admac
reg:
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+1
View File
@@ -24,6 +24,7 @@ properties:
- qcom,sm6350-gpi-dma
- items:
- enum:
- qcom,qcm2290-gpi-dma
- qcom,qdu1000-gpi-dma
- qcom,sc7280-gpi-dma
- qcom,sm6115-gpi-dma
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+14
View File
@@ -54,6 +54,11 @@ properties:
- description: DMA main clock
- description: DMA register access clock
clock-names:
items:
- const: main
- const: register
'#dma-cells':
const: 1
description:
@@ -77,16 +82,23 @@ properties:
- description: Reset for DMA ARESETN reset terminal
- description: Reset for DMA RST_ASYNC reset terminal
reset-names:
items:
- const: arst
- const: rst_async
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- '#dma-cells'
- dma-channels
- power-domains
- resets
- reset-names
additionalProperties: false
@@ -124,9 +136,11 @@ examples:
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_DMAC_ARESETN>,
<&cpg R9A07G044_DMAC_RST_ASYNC>;
reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+22 -1
View File
@@ -20,6 +20,7 @@ properties:
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
- starfive,jh7110-axi-dma
reg:
minItems: 1
@@ -58,7 +59,8 @@ properties:
maximum: 8
resets:
maxItems: 1
minItems: 1
maxItems: 2
snps,dma-masters:
description: |
@@ -109,6 +111,25 @@ required:
- snps,priority
- snps,block-size
if:
properties:
compatible:
contains:
enum:
- starfive,jh7110-axi-dma
then:
properties:
resets:
minItems: 2
items:
- description: AXI reset line
- description: AHB reset line
- description: module reset
else:
properties:
resets:
maxItems: 1
additionalProperties: false
examples:
Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
+1 -1
View File
@@ -43,7 +43,7 @@ description: |
configuration of the legacy peripheral.
allOf:
- $ref: "../dma-controller.yaml#"
- $ref: ../dma-controller.yaml#
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
+1 -1
View File
@@ -15,7 +15,7 @@ maintainers:
- Michael Tretter <m.tretter@pengutronix.de>
allOf:
- $ref: "../dma-controller.yaml#"
- $ref: ../dma-controller.yaml#
properties:
"#dma-cells":
Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
+1 -1
View File
@@ -16,7 +16,7 @@ maintainers:
- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
allOf:
- $ref: "../dma-controller.yaml#"
- $ref: ../dma-controller.yaml#
properties:
"#dma-cells":
Documentation/devicetree/bindings/gpio/nxp,pcf8575.yaml
+4
View File
@@ -39,6 +39,10 @@ properties:
reg:
maxItems: 1
gpio-line-names:
minItems: 1
maxItems: 16
gpio-controller: true
'#gpio-cells':
Documentation/devicetree/bindings/i2c/brcm,kona-i2c.txt
-35
View File
@@ -1,35 +0,0 @@
Broadcom Kona Family I2C
=========================
This I2C controller is used in the following Broadcom SoCs:
BCM11130
BCM11140
BCM11351
BCM28145
BCM28155
Required Properties
-------------------
- compatible: "brcm,bcm11351-i2c", "brcm,kona-i2c"
- reg: Physical base address and length of controller registers
- interrupts: The interrupt number used by the controller
- clocks: clock specifier for the kona i2c external clock
- clock-frequency: The I2C bus frequency in Hz
- #address-cells: Should be <1>
- #size-cells: Should be <0>
Refer to clocks/clock-bindings.txt for generic clock consumer
properties.
Example:
i2c@3e016000 {
compatible = "brcm,bcm11351-i2c","brcm,kona-i2c";
reg = <0x3e016000 0x80>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bsc1_clk>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
Documentation/devicetree/bindings/i2c/brcm,kona-i2c.yaml
+59
View File
@@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/brcm,kona-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Kona family I2C controller
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
items:
- enum:
- brcm,bcm11351-i2c
- brcm,bcm21664-i2c
- brcm,bcm23550-i2c
- const: brcm,kona-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-frequency:
enum: [ 100000, 400000, 1000000, 3400000 ]
required:
- compatible
- reg
- interrupts
- clocks
- clock-frequency
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c@3e016000 {
compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
reg = <0x3e016000 0x80>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bsc1_clk>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
...
Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2M I2C Bus Interface
maintainers:
- Phil Edworthy <phil.edworthy@renesas.com>
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml
+72
View File
@@ -0,0 +1,72 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i3c/aspeed,ast2600-i3c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED AST2600 i3c controller
maintainers:
- Jeremy Kerr <jk@codeconstruct.com.au>
allOf:
- $ref: i3c.yaml#
properties:
compatible:
const: aspeed,ast2600-i3c
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
sda-pullup-ohms:
enum: [545, 750, 2000]
default: 2000
description: |
Value to configure SDA pullup resistor, in Ohms.
aspeed,global-regs:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to i3c global register syscon node
- description: index of this i3c controller in the global register set
description: |
A (phandle, controller index) reference to the i3c global register set
used for this device.
required:
- compatible
- reg
- clocks
- interrupts
- aspeed,global-regs
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
i3c-master@2000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x2000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon 0>;
resets = <&syscon 0>;
aspeed,global-regs = <&i3c_global 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c1_default>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
};
...
Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml
+1 -1
View File
@@ -45,7 +45,7 @@ properties:
when the keyboard has a custom design for the top row keys.
dependencies:
function-row-phsymap: [ 'linux,keymap' ]
function-row-physmap: [ 'linux,keymap' ]
google,needs-ghost-filter: [ 'linux,keymap' ]
required:
Documentation/devicetree/bindings/input/pwm-beeper.txt
-24
View File
@@ -1,24 +0,0 @@
* PWM beeper device tree bindings
Registers a PWM device as beeper.
Required properties:
- compatible: should be "pwm-beeper"
- pwms: phandle to the physical PWM device
Optional properties:
- amp-supply: phandle to a regulator that acts as an amplifier for the beeper
- beeper-hz: bell frequency in Hz
Example:
beeper_amp: amplifier {
compatible = "fixed-regulator";
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
};
beeper {
compatible = "pwm-beeper";
pwms = <&pwm0>;
amp-supply = <&beeper_amp>;
};
Documentation/devicetree/bindings/input/pwm-beeper.yaml
+41
View File
@@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/pwm-beeper.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PWM beeper
maintainers:
- Sascha Hauer <s.hauer@pengutronix.de>
properties:
compatible:
const: pwm-beeper
pwms:
maxItems: 1
amp-supply:
description: an amplifier for the beeper
beeper-hz:
description: bell frequency in Hz
minimum: 10
maximum: 10000
required:
- compatible
- pwms
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
beeper {
compatible = "pwm-beeper";
pwms = <&pwm0>;
amp-supply = <&beeper_amp>;
beeper-hz = <1000>;
};
Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+41 -4
View File
@@ -53,6 +53,7 @@ properties:
- qcom,sm8250-smmu-500
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- qcom,sm8550-smmu-500
- const: qcom,smmu-500
- const: arm,mmu-500
@@ -75,9 +76,22 @@ properties:
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- const: arm,mmu-500
- description: Qcom Adreno GPUs implementing "arm,smmu-500"
- description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
items:
- enum:
- qcom,sc7280-smmu-500
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
- qcom,sm8350-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
- description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
deprecated: true
items:
# Do not add additional SoC to this list. Instead use previous list.
- enum:
- qcom,sc7280-smmu-500
- qcom,sm8150-smmu-500
@@ -364,6 +378,30 @@ allOf:
- description: interface clock required to access smmu's registers
through the TCU's programming interface.
- if:
properties:
compatible:
items:
- enum:
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- const: qcom,adreno-smmu
- const: qcom,smmu-500
- const: arm,mmu-500
then:
properties:
clock-names:
items:
- const: mem
- const: hlos
- const: iface
clocks:
items:
- description: GPU memory bus clock
- description: Voter clock required for HLOS SMMU access
- description: Interface clock required for register access
# Disallow clocks for all other platforms with specific compatibles
- if:
properties:
@@ -383,12 +421,11 @@ allOf:
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- qcom,sm8550-smmu-500
then:
properties:
clock-names: false
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+24 -8
View File
@@ -74,16 +74,16 @@ properties:
renesas,ipmmu-main:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- minItems: 1
items:
- description: phandle to main IPMMU
- description: the interrupt bit number associated with the particular
cache IPMMU device. The interrupt bit number needs to match the main
IPMMU IMSSTR register. Only used by cache IPMMU instances.
- description:
The interrupt bit number associated with the particular cache
IPMMU device. If present, the interrupt bit number needs to match
the main IPMMU IMSSTR register. Only used by cache IPMMU
instances.
description:
Reference to the main IPMMU phandle plus 1 cell. The cell is
the interrupt bit number associated with the particular cache IPMMU
device. The interrupt bit number needs to match the main IPMMU IMSSTR
register. Only used by cache IPMMU instances.
Reference to the main IPMMU.
required:
- compatible
@@ -109,6 +109,22 @@ allOf:
required:
- power-domains
- if:
properties:
compatible:
contains:
const: renesas,rcar-gen4-ipmmu-vmsa
then:
properties:
renesas,ipmmu-main:
items:
- maxItems: 1
else:
properties:
renesas,ipmmu-main:
items:
- minItems: 2
examples:
- |
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
Documentation/devicetree/bindings/leds/common.yaml
+32 -3
View File
@@ -90,22 +90,51 @@ properties:
- heartbeat
# LED indicates disk activity
- disk-activity
# LED indicates disk read activity
- disk-read
# LED indicates disk write activity
- disk-write
# LED flashes at a fixed, configurable rate
- timer
# LED alters the brightness for the specified duration with one software
# timer (requires "led-pattern" property)
- pattern
# LED indicates mic mute state
- audio-micmute
# LED indicates audio mute state
- audio-mute
# LED indicates bluetooth power state
- bluetooth-power
# LED indicates activity of all CPUs
- cpu
# LED indicates camera flash state
- flash
# LED indicated keyboard capslock
- kbd-capslock
# LED indicates MTD memory activity
- mtd
# LED indicates NAND memory activity (deprecated),
# in new implementations use "mtd"
- nand-disk
# No trigger assigned to the LED. This is the default mode
# if trigger is absent
- none
# LED indicates camera torch state
- torch
# LED indicates USB gadget activity
- usb-gadget
# LED indicates USB host activity
- usb-host
# LED indicates USB port state
- usbport
# LED is triggered by CPU activity
- pattern: "^cpu[0-9]*$"
- pattern: "^hci[0-9]+-power$"
# LED is triggered by Bluetooth activity
- pattern: "^mmc[0-9]+$"
- pattern: "^hci[0-9]+-power$"
# LED is triggered by SD/MMC activity
- pattern: "^phy[0-9]+tx$"
- pattern: "^mmc[0-9]+$"
# LED is triggered by WLAN activity
- pattern: "^phy[0-9]+tx$"
led-pattern:
description: |
Documentation/devicetree/bindings/leds/leds-pca9532.txt
-49
View File
@@ -1,49 +0,0 @@
*NXP - pca9532 PWM LED Driver
The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
The PWM support 256 steps.
Required properties:
- compatible:
"nxp,pca9530"
"nxp,pca9531"
"nxp,pca9532"
"nxp,pca9533"
- reg - I2C slave address
Each led is represented as a sub-node of the nxp,pca9530.
Optional sub-node properties:
- label: see Documentation/devicetree/bindings/leds/common.txt
- type: Output configuration, see dt-bindings/leds/leds-pca9532.h (default NONE)
- linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt
- default-state: see Documentation/devicetree/bindings/leds/common.txt
This property is only valid for sub-nodes of type <PCA9532_TYPE_LED>.
Example:
#include <dt-bindings/leds/leds-pca9532.h>
leds: pca9530@60 {
compatible = "nxp,pca9530";
reg = <0x60>;
red-power {
label = "pca:red:power";
type = <PCA9532_TYPE_LED>;
};
green-power {
label = "pca:green:power";
type = <PCA9532_TYPE_LED>;
};
kernel-booting {
type = <PCA9532_TYPE_LED>;
default-state = "on";
};
sys-stat {
type = <PCA9532_TYPE_LED>;
default-state = "keep"; // don't touch, was set by U-Boot
};
};
For more product information please see the link below:
http://nxp.com/documents/data_sheet/PCA9532.pdf
Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml
+1
View File
@@ -27,6 +27,7 @@ properties:
- qcom,pmc8180c-lpg
- qcom,pmi8994-lpg
- qcom,pmi8998-lpg
- qcom,pmk8550-pwm
"#pwm-cells":
const: 2
Documentation/devicetree/bindings/leds/nxp,pca953x.yaml
+90
View File
@@ -0,0 +1,90 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/nxp,pca953x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP PCA9532 LED Dimmer
maintainers:
- Riku Voipio <riku.voipio@iki.fi>
description: |
The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
The PWM support 256 steps.
For more product information please see the link below:
https://www.nxp.com/docs/en/data-sheet/PCA9532.pdf
properties:
compatible:
enum:
- nxp,pca9530
- nxp,pca9531
- nxp,pca9532
- nxp,pca9533
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
patternProperties:
"^led-[0-9a-z]+$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
properties:
type:
description: |
Output configuration, see include/dt-bindings/leds/leds-pca9532.h
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
minimum: 0
maximum: 4
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/leds-pca9532.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
led-controller@62 {
compatible = "nxp,pca9533";
reg = <0x62>;
led-1 {
label = "pca:red:power";
type = <PCA9532_TYPE_LED>;
};
led-2 {
label = "pca:green:power";
type = <PCA9532_TYPE_LED>;
};
led-3 {
type = <PCA9532_TYPE_LED>;
default-state = "on";
};
led-4 {
type = <PCA9532_TYPE_LED>;
default-state = "keep";
};
};
};
...
Documentation/devicetree/bindings/leds/qcom,spmi-flash-led.yaml
+117
View File
@@ -0,0 +1,117 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/qcom,spmi-flash-led.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Flash LED device inside Qualcomm Technologies, Inc. PMICs
maintainers:
- Fenglin Wu <quic_fenglinw@quicinc.com>
description: |
Flash LED controller is present inside some Qualcomm Technologies, Inc. PMICs.
The flash LED module can have different number of LED channels supported
e.g. 3 or 4. There are some different registers between them but they can
both support maximum current up to 1.5 A per channel and they can also support
ganging 2 channels together to supply maximum current up to 2 A. The current
will be split symmetrically on each channel and they will be enabled and
disabled at the same time.
properties:
compatible:
items:
- enum:
- qcom,pm6150l-flash-led
- qcom,pm8150c-flash-led
- qcom,pm8150l-flash-led
- qcom,pm8350c-flash-led
- const: qcom,spmi-flash-led
reg:
maxItems: 1
patternProperties:
"^led-[0-3]$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
description:
Represents the physical LED components which are connected to the
flash LED channels' output.
properties:
led-sources:
description:
The HW indices of the flash LED channels that connect to the
physical LED
allOf:
- minItems: 1
maxItems: 2
items:
enum: [1, 2, 3, 4]
led-max-microamp:
anyOf:
- minimum: 5000
maximum: 500000
multipleOf: 5000
- minimum: 10000
maximum: 1000000
multipleOf: 10000
flash-max-microamp:
anyOf:
- minimum: 12500
maximum: 1500000
multipleOf: 12500
- minimum: 25000
maximum: 2000000
multipleOf: 25000
flash-max-timeout-us:
minimum: 10000
maximum: 1280000
multipleOf: 10000
required:
- led-sources
- led-max-microamp
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
spmi {
#address-cells = <1>;
#size-cells = <0>;
led-controller@ee00 {
compatible = "qcom,pm8350c-flash-led", "qcom,spmi-flash-led";
reg = <0xee00>;
led-0 {
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
led-sources = <1>, <4>;
led-max-microamp = <300000>;
flash-max-microamp = <2000000>;
flash-max-timeout-us = <1280000>;
function-enumerator = <0>;
};
led-1 {
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_YELLOW>;
led-sources = <2>, <3>;
led-max-microamp = <300000>;
flash-max-microamp = <2000000>;
flash-max-timeout-us = <1280000>;
function-enumerator = <1>;
};
};
};
Documentation/devicetree/bindings/leds/rohm,bd2606mvv.yaml
+81
View File
@@ -0,0 +1,81 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/rohm,bd2606mvv.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD2606MVV LED controller
maintainers:
- Andreas Kemnade <andreas@kemnade.info>
description:
The BD2606 MVV is a programmable LED controller connected via I2C that can
drive 6 separate lines. Each of them can be individually switched on and off,
but the brightness setting is shared between pairs of them.
Datasheet is available at
https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/led_driver/bd2606mvv_1-e.pdf
properties:
compatible:
const: rohm,bd2606mvv
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
enable-gpios:
maxItems: 1
description: GPIO pin to enable/disable the device.
patternProperties:
"^led@[0-6]$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
properties:
reg:
minimum: 0
maximum: 6
required:
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
led-controller@66 {
compatible = "rohm,bd2606mvv";
reg = <0x66>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0x0>;
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_POWER;
};
led@2 {
reg = <0x2>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_STATUS;
};
};
};
...
Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
+12 -8
View File
@@ -16,14 +16,18 @@ description:
properties:
compatible:
enum:
- mediatek,mt6779-gce
- mediatek,mt8173-gce
- mediatek,mt8183-gce
- mediatek,mt8186-gce
- mediatek,mt8188-gce
- mediatek,mt8192-gce
- mediatek,mt8195-gce
oneOf:
- enum:
- mediatek,mt6779-gce
- mediatek,mt8173-gce
- mediatek,mt8183-gce
- mediatek,mt8186-gce
- mediatek,mt8188-gce
- mediatek,mt8192-gce
- mediatek,mt8195-gce
- items:
- const: mediatek,mt6795-gce
- const: mediatek,mt8173-gce
"#mbox-cells":
const: 2
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+21 -19
View File
@@ -19,22 +19,15 @@ properties:
- items:
- enum:
- qcom,ipq5332-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,ipq9574-apcs-apps-global
- const: qcom,ipq6018-apcs-apps-global
- items:
- enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm8150-apss-shared
- const: qcom,sdm845-apss-shared
- items:
- enum:
- qcom,msm8916-apcs-kpss-global
@@ -45,6 +38,18 @@ properties:
- qcom,qcs404-apcs-apps-global
- qcom,sdx55-apcs-gcc
- const: syscon
- enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
reg:
maxItems: 1
@@ -88,30 +93,31 @@ allOf:
items:
- const: pll
- const: aux
- if:
properties:
compatible:
enum:
- qcom,sdx55-apcs-gcc
contains:
enum:
- qcom,sdx55-apcs-gcc
then:
properties:
clocks:
items:
- description: reference clock
- description: primary pll parent of the clock driver
- description: auxiliary parent
- description: reference clock
clock-names:
items:
- const: ref
- const: pll
- const: aux
- const: ref
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
then:
properties:
clocks:
@@ -133,14 +139,11 @@ allOf:
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
- qcom,sm8150-apss-shared
then:
properties:
clocks: false
@@ -152,7 +155,6 @@ allOf:
contains:
enum:
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
then:
properties:
'#clock-cells':
Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
-7
View File
@@ -26,11 +26,6 @@ properties:
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 2
@@ -89,7 +84,6 @@ required:
- compatible
- power-domains
- iommus
- dma-ranges
- ranges
additionalProperties: false
@@ -115,7 +109,6 @@ examples:
<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml
-7
View File
@@ -26,11 +26,6 @@ properties:
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
"#address-cells":
const: 2
@@ -89,7 +84,6 @@ required:
- compatible
- power-domains
- iommus
- dma-ranges
- ranges
additionalProperties: false
@@ -113,7 +107,6 @@ examples:
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml
-5
View File
@@ -56,11 +56,6 @@ properties:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
-5
View File
@@ -49,11 +49,6 @@ properties:
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
-5
View File
@@ -44,11 +44,6 @@ properties:
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
dma-ranges:
maxItems: 1
description: |
Describes the physical address space of IOMMU maps to memory.
required:
- compatible
- reg
Documentation/devicetree/bindings/memory-controllers/arm,pl35x-smc.yaml
-1
View File
@@ -8,7 +8,6 @@ title: Arm PL35x Series Static Memory Controller (SMC)
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
description: |
The PL35x Static Memory Controller is a bus where you can connect two kinds
Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
+3 -3
View File
@@ -36,7 +36,7 @@ properties:
clock-controller:
# Child node
type: object
$ref: "../clock/canaan,k210-clk.yaml"
$ref: ../clock/canaan,k210-clk.yaml
description:
Clock controller for the SoC clocks. This child node definition
should follow the bindings specified in
@@ -45,7 +45,7 @@ properties:
reset-controller:
# Child node
type: object
$ref: "../reset/canaan,k210-rst.yaml"
$ref: ../reset/canaan,k210-rst.yaml
description:
Reset controller for the SoC. This child node definition
should follow the bindings specified in
@@ -54,7 +54,7 @@ properties:
syscon-reboot:
# Child node
type: object
$ref: "../power/reset/syscon-reboot.yaml"
$ref: ../power/reset/syscon-reboot.yaml
description:
Reboot method for the SoC. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
+11 -11
View File
@@ -65,7 +65,7 @@ properties:
ARM Cortex M4 Co-processor. Contains the name of the rpmsg
device. Used to match the subnode to the rpmsg device announced by
the SCP.
$ref: "/schemas/types.yaml#/definitions/string"
$ref: /schemas/types.yaml#/definitions/string
spi-max-frequency: true
@@ -94,23 +94,23 @@ properties:
const: 0
typec:
$ref: "/schemas/chrome/google,cros-ec-typec.yaml#"
$ref: /schemas/chrome/google,cros-ec-typec.yaml#
ec-pwm:
$ref: "/schemas/pwm/google,cros-ec-pwm.yaml#"
$ref: /schemas/pwm/google,cros-ec-pwm.yaml#
deprecated: true
pwm:
$ref: "/schemas/pwm/google,cros-ec-pwm.yaml#"
$ref: /schemas/pwm/google,cros-ec-pwm.yaml#
kbd-led-backlight:
$ref: "/schemas/chrome/google,cros-kbd-led-backlight.yaml#"
$ref: /schemas/chrome/google,cros-kbd-led-backlight.yaml#
keyboard-controller:
$ref: "/schemas/input/google,cros-ec-keyb.yaml#"
$ref: /schemas/input/google,cros-ec-keyb.yaml#
proximity:
$ref: "/schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#"
$ref: /schemas/iio/proximity/google,cros-ec-mkbp-proximity.yaml#
codecs:
type: object
@@ -126,7 +126,7 @@ properties:
patternProperties:
"^ec-codec@[a-f0-9]+$":
type: object
$ref: "/schemas/sound/google,cros-ec-codec.yaml#"
$ref: /schemas/sound/google,cros-ec-codec.yaml#
required:
- "#address-cells"
@@ -151,15 +151,15 @@ properties:
patternProperties:
"^i2c-tunnel[0-9]*$":
type: object
$ref: "/schemas/i2c/google,cros-ec-i2c-tunnel.yaml#"
$ref: /schemas/i2c/google,cros-ec-i2c-tunnel.yaml#
"^regulator@[0-9]+$":
type: object
$ref: "/schemas/regulator/google,cros-ec-regulator.yaml#"
$ref: /schemas/regulator/google,cros-ec-regulator.yaml#
"^extcon[0-9]*$":
type: object
$ref: "/schemas/extcon/extcon-usbc-cros-ec.yaml#"
$ref: /schemas/extcon/extcon-usbc-cros-ec.yaml#
required:
- compatible
Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml
+1 -1
View File
@@ -53,7 +53,7 @@ properties:
'^ldo[0-9]+$':
type: object
$ref: "/schemas/regulator/regulator.yaml#"
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
Documentation/devicetree/bindings/mfd/maxim,max5970.yaml
+151
View File
@@ -0,0 +1,151 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/maxim,max5970.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Regulator for MAX5970 Smart Switch from Maxim Integrated
maintainers:
- Patrick Rudolph <patrick.rudolph@9elements.com>
description: |
The smart switch provides no output regulation, but independent fault protection
and voltage and current sensing.
Programming is done through I2C bus.
Datasheets:
https://datasheets.maximintegrated.com/en/ds/MAX5970.pdf
https://datasheets.maximintegrated.com/en/ds/MAX5978.pdf
properties:
compatible:
enum:
- maxim,max5970
- maxim,max5978
reg:
maxItems: 1
interrupts:
maxItems: 1
leds:
type: object
description:
Properties for four LEDS.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^led@[0-3]$":
$ref: /schemas/leds/common.yaml#
type: object
additionalProperties: false
vss1-supply:
description: Supply of the first channel.
vss2-supply:
description: Supply of the second channel.
regulators:
type: object
description:
Properties for both hot swap control/switch.
patternProperties:
"^sw[0-1]$":
$ref: /schemas/regulator/regulator.yaml#
type: object
properties:
shunt-resistor-micro-ohms:
description: |
The value of current sense resistor in microohms.
required:
- shunt-resistor-micro-ohms
unevaluatedProperties: false
additionalProperties: false
required:
- compatible
- reg
- regulators
- vss1-supply
allOf:
- if:
properties:
compatible:
enum:
- maxim,max5970
then:
required:
- vss2-supply
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
regulator@3a {
compatible = "maxim,max5978";
reg = <0x3a>;
vss1-supply = <&p3v3>;
regulators {
sw0_ref_0: sw0 {
shunt-resistor-micro-ohms = <12000>;
};
};
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
label = "led0";
default-state = "on";
};
led@1 {
reg = <1>;
label = "led1";
default-state = "on";
};
};
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
regulator@3a {
compatible = "maxim,max5970";
reg = <0x3a>;
vss1-supply = <&p3v3>;
vss2-supply = <&p5v>;
regulators {
sw0_ref_1: sw0 {
shunt-resistor-micro-ohms = <12000>;
};
sw1_ref_1: sw1 {
shunt-resistor-micro-ohms = <10000>;
};
};
};
};
...
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+13 -2
View File
@@ -33,6 +33,7 @@ properties:
compatible:
items:
- enum:
- qcom,pm2250
- qcom,pm6125
- qcom,pm6150
- qcom,pm6150l
@@ -78,6 +79,7 @@ properties:
- qcom,pmk8350
- qcom,pmk8550
- qcom,pmm8155au
- qcom,pmm8654au
- qcom,pmp8074
- qcom,pmr735a
- qcom,pmr735b
@@ -115,6 +117,7 @@ patternProperties:
type: object
oneOf:
- $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml#
- $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml#
- $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml#
"^adc-tm@[0-9a-f]+$":
@@ -135,6 +138,14 @@ patternProperties:
type: object
$ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
"^led-controller@[0-9a-f]+$":
type: object
$ref: /schemas/leds/qcom,spmi-flash-led.yaml#
"^nvram@[0-9a-f]+$":
type: object
$ref: /schemas/nvmem/qcom,spmi-sdam.yaml#
"pon@[0-9a-f]+$":
type: object
$ref: /schemas/power/reset/qcom,pon.yaml#
@@ -276,12 +287,12 @@ examples:
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};
adc-chan@4f {
channel@4f {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+4
View File
@@ -25,12 +25,16 @@ properties:
- qcom,sc8280xp-tcsr
- qcom,sdm630-tcsr
- qcom,sdm845-tcsr
- qcom,sdx55-tcsr
- qcom,sdx65-tcsr
- qcom,sm8150-tcsr
- qcom,sm8450-tcsr
- qcom,tcsr-apq8064
- qcom,tcsr-apq8084
- qcom,tcsr-ipq5332
- qcom,tcsr-ipq6018
- qcom,tcsr-ipq8064
- qcom,tcsr-ipq9574
- qcom,tcsr-mdm9615
- qcom,tcsr-msm8226
- qcom,tcsr-msm8660
Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
+1 -1
View File
@@ -49,7 +49,7 @@ patternProperties:
"rtc@[0-9a-f]+$":
type: object
$ref: "../rtc/qcom-pm8xxx-rtc.yaml"
$ref: ../rtc/qcom-pm8xxx-rtc.yaml
required:
- compatible
Documentation/devicetree/bindings/mfd/rohm,bd71815-pmic.yaml
+1 -1
View File
@@ -46,7 +46,7 @@ properties:
rohm,clkout-open-drain:
description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1
Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+1 -1
View File
@@ -46,7 +46,7 @@ properties:
rohm,clkout-open-drain:
description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
$ref: "/schemas/types.yaml#/definitions/uint32"
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1
Documentation/devicetree/bindings/mfd/syscon.yaml
+2
View File
@@ -56,6 +56,7 @@ properties:
- microchip,lan966x-cpu-syscon
- microchip,sparx5-cpu-syscon
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
- rockchip,px30-qos
- rockchip,rk3036-qos
@@ -67,6 +68,7 @@ properties:
- rockchip,rk3568-qos
- rockchip,rk3588-qos
- rockchip,rv1126-qos
- starfive,jh7100-sysmain
- const: syscon
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+11
View File
@@ -62,6 +62,12 @@ patternProperties:
description:
The phy node corresponding to the ethernet MAC.
"^chipid@[0-9a-f]+$":
type: object
$ref: /schemas/hwinfo/ti,k3-socinfo.yaml#
description:
The node corresponding to SoC chip identification.
required:
- compatible
- reg
@@ -99,5 +105,10 @@ examples:
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
...
Documentation/devicetree/bindings/mfd/ti,nspire-misc.yaml
+51
View File
@@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/ti,nspire-misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Nspire MISC hardware block
maintainers:
- Andrew Davis <afd@ti.com>
description:
System controller node represents a register region containing a set
of miscellaneous registers. The registers are not cohesive enough to
represent as any specific type of device. Currently there is a reset
controller.
properties:
compatible:
items:
- enum:
- ti,nspire-misc
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
reboot:
$ref: /schemas/power/reset/syscon-reboot.yaml#
required:
- compatible
- reg
- reboot
additionalProperties: false
examples:
- |
misc: misc@900a0000 {
compatible = "ti,nspire-misc", "syscon", "simple-mfd";
reg = <0x900a0000 0x1000>;
reboot {
compatible = "syscon-reboot";
offset = <0x08>;
value = <0x02>;
};
};
Documentation/devicetree/bindings/mfd/wlf,arizona.yaml
+1 -1
View File
@@ -156,7 +156,7 @@ properties:
entry has a value that is out of range for a 16 bit register then the
chip default will be used. If present exactly five values must be
specified.
$ref: "/schemas/types.yaml#/definitions/uint32-array"
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 5
Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+2 -2
View File
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mfd/x-powers,ac100.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: X-Powers AC100
Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml
+20 -12
View File
@@ -47,9 +47,8 @@ allOf:
- x-powers,axp209
then:
not:
required:
- x-powers,drive-vbus-en
properties:
x-powers,drive-vbus-en: false
- if:
not:
@@ -59,14 +58,9 @@ allOf:
const: x-powers,axp806
then:
allOf:
- not:
required:
- x-powers,self-working-mode
- not:
required:
- x-powers,master-mode
properties:
x-powers,self-working-mode: false
x-powers,master-mode: false
- if:
not:
@@ -79,6 +73,18 @@ allOf:
required:
- interrupts
- if:
properties:
compatible:
contains:
enum:
- x-powers,axp313a
- x-powers,axp15060
then:
properties:
x-powers,dcdc-freq: false
properties:
compatible:
oneOf:
@@ -88,10 +94,12 @@ properties:
- x-powers,axp209
- x-powers,axp221
- x-powers,axp223
- x-powers,axp313a
- x-powers,axp803
- x-powers,axp806
- x-powers,axp809
- x-powers,axp813
- x-powers,axp15060
- items:
- const: x-powers,axp228
- const: x-powers,axp221
@@ -260,7 +268,7 @@ properties:
Defines the work frequency of DC-DC in kHz.
patternProperties:
"^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|drivevbus|dc5ldo)$":
"^(([a-f])?ldo[0-9]|dcdc[0-7a-e]|ldo(_|-)io(0|1)|(dc1)?sw|rtc(_|-)ldo|cpusldo|drivevbus|dc5ldo)$":
$ref: /schemas/regulator/regulator.yaml#
type: object
unevaluatedProperties: false
Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml
+2 -2
View File
@@ -2,8 +2,8 @@
# Copyright 2019 Bootlin
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mfd/xylon,logicvc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/mfd/xylon,logicvc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xylon LogiCVC multi-function device
Documentation/devicetree/bindings/mtd/arasan,nand-controller.yaml
+1 -1
View File
@@ -10,7 +10,7 @@ allOf:
- $ref: nand-controller.yaml
maintainers:
- Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:
Documentation/devicetree/bindings/mtd/arm,pl353-nand-r2p1.yaml
-1
View File
@@ -11,7 +11,6 @@ allOf:
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
- Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
properties:
compatible:
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+5 -1
View File
@@ -21,8 +21,12 @@ allOf:
properties:
compatible:
items:
oneOf:
- const: rockchip,rk3568-pcie
- items:
- enum:
- rockchip,rk3588-pcie
- const: rockchip,rk3568-pcie
reg:
items:
Documentation/devicetree/bindings/perf/riscv,pmu.yaml
-1
View File
@@ -91,7 +91,6 @@ properties:
dependencies:
"riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
"riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ]
required:
- compatible
Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
+2 -2
View File
@@ -2,8 +2,8 @@
# Copyright 2019 Ondrej Jirman <megous@megous.com>
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner H6 USB3 PHY
Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+1 -1
View File
@@ -45,7 +45,7 @@ properties:
maxItems: 1
allwinner,direction:
$ref: '/schemas/types.yaml#/definitions/string'
$ref: /schemas/types.yaml#/definitions/string
description: |
Direction of the D-PHY:
- "rx" for receiving (e.g. when used with MIPI CSI-2);
Documentation/devicetree/bindings/phy/amlogic,axg-mipi-dphy.yaml
+2 -2
View File
@@ -2,8 +2,8 @@
# Copyright 2020 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,axg-mipi-dphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic AXG MIPI D-PHY
Documentation/devicetree/bindings/phy/amlogic,g12a-mipi-dphy-analog.yaml
+2 -2
View File
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic G12A MIPI analog PHY
Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml
+2 -2
View File
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic G12A USB2 PHY
Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml
+2 -2
View File
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic G12A USB3 + PCIE Combo PHY
Documentation/devicetree/bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
+2 -2
View File
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic AXG shared MIPI/PCIE analog PHY
Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
+2 -2
View File
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic AXG PCIE PHY
Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml
+2 -2
View File
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY
Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
+2 -2
View File
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml
+2 -2
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@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BCM63xx USBH PHY

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