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This commit is contained in:
Thomas Makin
2025-07-14 23:48:00 -05:00
parent 0394419db5
commit 86d4384d41
3 changed files with 434 additions and 111 deletions
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20
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@@ -2263,6 +2263,26 @@
};
};
core_dvfs_floor: core_dvfs_cdev_floor {
compatible = "nvidia,tegra-core-cdev-action";
cdev-type = "CORE-floor";
#cooling-cells = <2>; /* min followed by max */
};
core_dvfs_cap: core_dvfs_cdev_cap {
compatible = "nvidia,tegra-core-cdev-action";
cdev-type = "CORE-cap";
#cooling-cells = <2>; /* min followed by max */
clocks = <&tegra_car TEGRA210_CLK_CAP_VCORE_C2BUS>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_C3BUS>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_SCLK>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_HOST1X>,
<&tegra_car TEGRA210_CLK_CAP_VCORE_ABUS>;
clock-names = "c2bus_cap", "c3bus_cap", "sclk_cap",
"host1x_cap", "adsp_cap";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13

493
arch/arm64/boot/dts/nvidia/tegra210b01-nx.dtsi
View File

@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/mfd/max77620.h>
#include <dt-bindings/thermal/tegra210b01-trips.h>
#include <dt-bindings/thermal/thermal.h>
#include "tegra210b01.dtsi"
@@ -17,104 +19,104 @@
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
/* SDMMC4 for EMMC */
sdhci@700b0600 {
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) 0>;
cd-debounce = <128>;
bus-width = <8>;
uhs-mask = <0x0>; /* All modes */
tap-delay = <11>;
trim-delay = <13>;
only-1-8-v;
no-sdio;
no-sd;
max-clk-limit = <200000000>;
disable-dynamic-host-clk-gating;
adma-xfer-size = <8388608>; /* 8MiB */
pll_source = "pll_p", "pll_c4_out2";
clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
clock-names = "sdmmc", "pll_p", "pll_c4_out2", "sdmmc_legacy_tm";
status = "disabled";
};
// /* SDMMC4 for EMMC */
// sdhci@700b0600 {
// cd-gpios = <&gpio TEGRA_GPIO(Z, 1) 0>;
// cd-debounce = <128>;
// bus-width = <8>;
// uhs-mask = <0x0>; /* All modes */
// tap-delay = <11>;
// trim-delay = <13>;
// only-1-8-v;
// no-sdio;
// no-sd;
// max-clk-limit = <200000000>;
// disable-dynamic-host-clk-gating;
// adma-xfer-size = <8388608>; /* 8MiB */
// pll_source = "pll_p", "pll_c4_out2";
// clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
// <&tegra_car TEGRA210_CLK_PLL_P>,
// <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
// <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
// clock-names = "sdmmc", "pll_p", "pll_c4_out2", "sdmmc_legacy_tm";
// status = "disabled";
// };
/* SDMMC3 Unused */
sdhci@700b0400 {
status = "disabled";
};
// /* SDMMC3 Unused */
// sdhci@700b0400 {
// status = "disabled";
// };
/* SDMMC2 for Gamecard */
sdhci@700b0200 {
uhs-mask = <0x0>; /* All modes */
tap-delay = <11>;
trim-delay = <13>;
nvidia,is-ddr-tap-delay;
nvidia,ddr-tap-delay = <0>;
mmc-ocr-mask = <0>;
dqs-trim-delay = <17>;
dqs-trim-delay-hs533 = <24>;
max-clk-limit = <200000000>;
bus-width = <8>;
built-in;
calib-3v3-offsets = <0x0505>;
calib-1v8-offsets = <0x0505>;
compad-vref-3v3 = <0x7>;
compad-vref-1v8 = <0x7>;
nvidia,en-io-trim-volt;
nvidia,is-emmc;
nvidia,enable-cq;
ignore-pm-notify;
keep-power-in-suspend;
non-removable;
cap-mmc-highspeed;
cap-sd-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
nvidia,enable-strobe-mode;
pll_source = "pll_p", "pll_c4_out2";
clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
clock-names = "sdmmc", "pll_p", "pll_c4_out2";
status = "disabled";
};
// /* SDMMC2 for Gamecard */
// sdhci@700b0200 {
// uhs-mask = <0x0>; /* All modes */
// tap-delay = <11>;
// trim-delay = <13>;
// nvidia,is-ddr-tap-delay;
// nvidia,ddr-tap-delay = <0>;
// mmc-ocr-mask = <0>;
// dqs-trim-delay = <17>;
// dqs-trim-delay-hs533 = <24>;
// max-clk-limit = <200000000>;
// bus-width = <8>;
// built-in;
// calib-3v3-offsets = <0x0505>;
// calib-1v8-offsets = <0x0505>;
// compad-vref-3v3 = <0x7>;
// compad-vref-1v8 = <0x7>;
// nvidia,en-io-trim-volt;
// nvidia,is-emmc;
// nvidia,enable-cq;
// ignore-pm-notify;
// keep-power-in-suspend;
// non-removable;
// cap-mmc-highspeed;
// cap-sd-highspeed;
// mmc-ddr-1_8v;
// mmc-hs200-1_8v;
// mmc-hs400-1_8v;
// nvidia,enable-strobe-mode;
// pll_source = "pll_p", "pll_c4_out2";
// clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
// <&tegra_car TEGRA210_CLK_PLL_P>,
// <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
// clock-names = "sdmmc", "pll_p", "pll_c4_out2";
// status = "disabled";
// };
/* SDMMC1 for uSD card */
sdhci@700b0000 {
uhs-mask = <0x0c>; /* Disable SDR50/DDR50 */
tap-delay = <11>;
trim-delay = <14>;
power-off-rail;
nvidia,update-pinctrl-settings;
nvidia,sd-device;
no-sdio;
no-mmc;
max-current-800ma;
max-clk-limit = <208000000>;
sdr50-clk-limit = <100000000>;
sdr104-hs200-clk-limit = <200000000>;
ddr-clk-limit = <208000000>; /* 416 MHz for host */
ddr50-clk-limit = <48000000>; /* 86 MHz for host */
ddr200-clk-limit = <200000000>; /* 400 MHz for host */
disable-dynamic-host-clk-gating;
adma-xfer-size = <8388608>; /* 8MiB */
default-drv-type = <1>;
pll_source = "pll_p", "pll_c4_out2", "pll_c4_out0";
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
<&tegra_car TEGRA210_CLK_PLL_P>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
clock-names = "sdmmc", "pll_p", "pll_c4_out2", "pll_c4_out0", "sdmmc_legacy_tm";
nvidia,cd-wakeup-capable;
status = "okay";
// /* SDMMC1 for uSD card */
// sdhci@700b0000 {
// uhs-mask = <0x0c>; /* Disable SDR50/DDR50 */
// tap-delay = <11>;
// trim-delay = <14>;
// power-off-rail;
// nvidia,update-pinctrl-settings;
// nvidia,sd-device;
// no-sdio;
// no-mmc;
// max-current-800ma;
// max-clk-limit = <208000000>;
// sdr50-clk-limit = <100000000>;
// sdr104-hs200-clk-limit = <200000000>;
// ddr-clk-limit = <208000000>; /* 416 MHz for host */
// ddr50-clk-limit = <48000000>; /* 86 MHz for host */
// ddr200-clk-limit = <200000000>; /* 400 MHz for host */
// disable-dynamic-host-clk-gating;
// adma-xfer-size = <8388608>; /* 8MiB */
// default-drv-type = <1>;
// pll_source = "pll_p", "pll_c4_out2", "pll_c4_out0";
// clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
// <&tegra_car TEGRA210_CLK_PLL_P>,
// <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
// <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
// <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
// clock-names = "sdmmc", "pll_p", "pll_c4_out2", "pll_c4_out0", "sdmmc_legacy_tm";
// nvidia,cd-wakeup-capable;
// status = "okay";
nvidia,pmc-wakeup = <&tegra_pmc
PMC_WAKE_TYPE_EVENT 35 (PMC_TRIGGER_TYPE_RISING | PMC_TRIGGER_TYPE_FALLING)>; /* gpio_pz1_IB */
};
// // nvidia,pmc-wakeup = <&tegra_pmc
// // PMC_WAKE_TYPE_EVENT 35 (PMC_TRIGGER_TYPE_RISING | PMC_TRIGGER_TYPE_FALLING)>; /* gpio_pz1_IB */
// };
serial@70006000 {
/delete-property/ dmas;
@@ -122,6 +124,268 @@
status = "okay";
};
soctherm@700E2000 {
throttle-cfgs {
/* PG/ACOK/USB OC pin. CLK_32K_OUT. Used for LED PWM on Vali. */
/*
throttle_oc1: oc1 { // Sticky mode but not supported.
nvidia,priority = <16>;
nvidia,polarity-active-low = <1>;
nvidia,count-threshold = <0>;
nvidia,throttle-period = <2500000>;
nvidia,alarm-filter = <0xFFFFFFFF>;
nvidia,cpu-throt-percent = <75>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
};
*/
/* Battery OC pin. GPIO_PL1. Traced but missing resistor. */
/*
throttle_oc2: oc2 {
nvidia,priority = <24>;
nvidia,polarity-active-low = <1>;
nvidia,count-threshold = <0>;
nvidia,throttle-period = <100>;
nvidia,alarm-filter = <0xFFFFFFFF>;
nvidia,cpu-throt-percent = <75>;
nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
};
*/
/* throttle_oc3: oc3: GPIO_PZ5. Floating. */
};
};
thermal-zones {
PLL-therm {
status = "okay";
polling-delay-passive = <500>;
thermal-zone-params {
governor-name = "step_wise";
};
trips {
cpu_heavy {
temperature = <94500>;
hysteresis = <0>;
type = "hot";
writable;
};
cpu_throttle {
temperature = <90500>;
hysteresis = <0>;
type = "passive";
writable;
};
cpu_critical {
temperature = <96000>;
hysteresis = <0>;
type = "critical";
writable;
};
dfll_cap_trip0: dfll-cap-trip0 {
temperature = <TEGRA210B01_DFLL_THERMAL_CAP_0>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
dfll_cap_trip1: dfll-cap-trip1 {
temperature = <TEGRA210B01_DFLL_THERMAL_CAP_1>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
// cooling-maps {
// map0 {
// trip = <&{/thermal-zones/PLL-therm/trips/cpu_heavy}>;
// cdev-type = "tegra-heavy";
// cooling-device = <&throttle_heavy 1 1>;
// };
// map1 {
// trip = <&{/thermal-zones/PLL-therm/trips/cpu_throttle}>;
// cdev-type = "cpu-balanced";
// cooling-device = <&{/bthrot_cdev/cpu_balanced}
// THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
// };
// dfll-cap-map0 {
// trip = <&dfll_cap_trip0>;
// cooling-device = <&dfll_cap 1 1>;
// };
// dfll-cap-map1 {
// trip = <&dfll_cap_trip1>;
// cooling-device = <&dfll_cap 2 2>;
// };
// };
};
Tboard_tegra {
status = "okay";
polling-delay = <0>;
polling-delay-passive = <5500>;
trips {
board_emergency {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
writable;
};
};
// cooling-maps {
// map0 {
// trip = <&{/thermal-zones/Tboard_tegra/trips/board_emergency}>;
// cdev-type = "emergency-balanced";
// cooling-device = <&{/bthrot_cdev/emergency_balanced}
// THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
// };
// };
};
Tdiode_tegra {
status = "okay";
polling-delay = <0>;
polling-delay-passive = <1100>;
trips {
gpu_shutdown {
temperature = <92500>;
hysteresis = <0>;
type = "critical";
writable;
};
gpu_throttle {
temperature = <86000>;
hysteresis = <0>;
type = "passive";
writable;
};
gpu_scaling_trip0: gpu-scaling-trip0 {
temperature = <(TEGRA210B01_GPU_DVFS_THERMAL_MIN)>;
hysteresis = <0>; /* millicelsius */
type = "active";
};
gpu_scaling_trip1: gpu-scaling-trip1 {
temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_1>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
gpu_scaling_trip2: gpu-scaling-trip2 {
temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_2>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
gpu_scaling_trip3: gpu-scaling-trip3 {
temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_3>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
gpu_scaling_trip4: gpu-scaling-trip4 {
temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_4>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
gpu_scaling_trip5: gpu-scaling-trip5 {
temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_5>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
gpu_vmax_trip1: gpu-vmax-trip1 {
temperature = <TEGRA210B01_GPU_DVFS_THERMAL_CAP_1>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
core_dvfs_floor_trip0: core_dvfs_floor_trip0 {
temperature = <TEGRA210B01_SOC_THERMAL_FLOOR_0>;
hysteresis = <1000>;
type = "active";
};
core_dvfs_cap_trip0: core_dvfs_cap_trip0 {
temperature = <TEGRA210B01_SOC_THERMAL_CAP_0>;
hysteresis = <1000>;
type = "active";
};
soc_critical {
temperature = <96000>;
hysteresis = <0>;
type = "critical";
writable;
};
soc_emergency {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
writable;
};
dfll_floor_trip0: dfll-floor-trip0 {
temperature = <TEGRA210B01_DFLL_THERMAL_FLOOR_0>;
hysteresis = <1000>; /* millicelsius */
type = "active";
};
};
cooling-maps {
// map0 {
// trip = <&{/thermal-zones/Tdiode_tegra/trips/soc_critical}>;
// cdev-type = "tegra-shutdown";
// cooling-device = <&{/soctherm@0x700E2000/throttle@critical}
// THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
// };
// map1 {
// trip = <&{/thermal-zones/Tdiode_tegra/trips/soc_emergency}>;
// cdev-type = "emergency-balanced";
// cooling-device = <&{/bthrot_cdev/emergency_balanced}
// THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
// };
// gpu-scaling-map1 {
// trip = <&gpu_scaling_trip1>;
// cooling-device = <&gpu_scaling_cdev 1 1>;
// };
// gpu-scaling-map2 {
// trip = <&gpu_scaling_trip2>;
// cooling-device = <&gpu_scaling_cdev 2 2>;
// };
// gpu_scaling_map3 {
// trip = <&gpu_scaling_trip3>;
// cooling-device = <&gpu_scaling_cdev 3 3>;
// };
// gpu-scaling-map4 {
// trip = <&gpu_scaling_trip4>;
// cooling-device = <&gpu_scaling_cdev 4 4>;
// };
// gpu-scaling-map5 {
// trip = <&gpu_scaling_trip5>;
// cooling-device = <&gpu_scaling_cdev 5 5>;
// };
// gpu-vmax-map1 {
// trip = <&gpu_vmax_trip1>;
// cooling-device = <&gpu_vmax_cdev 1 1>;
// };
core_dvfs_floor_map0 {
trip = <&core_dvfs_floor_trip0>;
cooling-device = <&core_dvfs_floor 1 1>;
};
core_dvfs_cap_map0 {
trip = <&core_dvfs_cap_trip0>;
cooling-device = <&core_dvfs_cap 1 1>;
};
dfll-floor-map0 {
trip = <&dfll_floor_trip0>;
cooling-device = <&dfll_floor 1 1>;
};
// map2 {
// trip = <&{/thermal-zones/Tdiode_tegra/trips/gpu_throttle}>;
// cdev-type = "gpu-balanced";
// cooling-device = <&{/bthrot_cdev/gpu_balanced}
// THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
// };
};
};
AO-therm {
status = "okay";
};
};
pinmux@700008d4 {
dsi_ab_pad_default: dsi_ab_pad_default {
dsi_ab_pad_enable {
@@ -196,7 +460,7 @@
};
};
clock@70110000 {
tegra_clk_dfll: clock@70110000 {
status = "okay";
vdd-cpu-supply = <&cpu_max_reg>;
nvidia,align-step-uv = <5000>;
@@ -593,4 +857,43 @@
};
};
};
dfll_cap: dfll-cdev-cap {
compatible = "nvidia,tegra-dfll-cdev-action";
act-dev = <&tegra_clk_dfll>;
cdev-type = "DFLL-cap";
#cooling-cells = <2>; /* min followed by max */
};
dfll_floor: dfll-cdev-floor {
compatible = "nvidia,tegra-dfll-cdev-action";
act-dev = <&tegra_clk_dfll>;
cdev-type = "DFLL-floor";
#cooling-cells = <2>; /* min followed by max */
};
// gpu_scaling_cdev: gpu-scaling-cdev {
// cooling-min-state = <0>;
// cooling-max-state = <5>;
// #cooling-cells = <2>;
// compatible = "nvidia,tegra210-rail-scaling-cdev";
// cdev-type = "gpu_scaling";
// nvidia,constraint;
// nvidia,trips = <&gpu_scaling_trip0 800 &gpu_scaling_trip1 0
// &gpu_scaling_trip2 0 &gpu_scaling_trip3 0
// &gpu_scaling_trip4 0 &gpu_scaling_trip5 0>;
// };
// gpu_vmax_cdev: gpu-vmax-cdev {
// cooling-min-state = <0>;
// cooling-max-state = <1>;
// #cooling-cells = <2>;
// compatible = "nvidia,tegra210-rail-vmax-cdev";
// cdev-type = "GPU-cap";
// nvidia,constraint-ucm2;
// nvidia,trips = <&gpu_vmax_trip1 1010 1010>;
// clocks = <&tegra_car TEGRA210_CLK_CAP_VGPU_GBUS>;
// clock-names = "cap-clk";
// status = "disabled";
// };
};

32
arch/arm64/boot/dts/nvidia/tegra210b01-vali.dts
View File

@@ -92,23 +92,23 @@
};
};
sdhci@700b0600 {
vqmmc-supply = <&max77620_sd3>;
vmmc-supply = <&vdd_3v3>;
};
// sdhci@700b0600 {
// vqmmc-supply = <&max77620_sd3>;
// vmmc-supply = <&vdd_3v3>;
// };
sdhci@700b0400 {
vqmmc-supply = <&max77620_sd3>;
vmmc-supply = <&vdd_3v3>;
};
// sdhci@700b0400 {
// vqmmc-supply = <&max77620_sd3>;
// vmmc-supply = <&vdd_3v3>;
// };
sdhci@700b0200 {
vqmmc-supply = <&max77620_sd3>;
vmmc-supply = <&vdd_3v3>;
};
// sdhci@700b0200 {
// vqmmc-supply = <&max77620_sd3>;
// vmmc-supply = <&vdd_3v3>;
// };
sdhci@700b0000 {
vqmmc-supply = <&max77620_ldo2>;
vmmc-supply = <&en_vdd_sd>;
};
// sdhci@700b0000 {
// vqmmc-supply = <&max77620_ldo2>;
// vmmc-supply = <&en_vdd_sd>;
// };
};