Merge tag 'omap-for-v5.11/genpd-rest-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/omap-genpd
Remaining genpd changes for omaps for v5.11 This series contains the remaining genpd changes for omap4/5, and dra7 to add the power domain and reset control data to omap-prm driver. We also update several devices to probe without platform data to get us closer to booting omap4/5, and dra7 without platform data. There is also a build fix for the earlier am437x series that I should have applied into a separate branch on top of the am437x breaking commit. It ended here as I was originally planning to send out a single pull request for all the genpd changes, but then decided to break it down to smaller chunks. It's all really a larger single git branch though, so this should be OK and I really did not want to start reorganizing the branch after testing it and having it sit in Linux next. The changes done here are: - Clock driver needs idlest check dropped for IVA for omap4 and dra7 - Add remaining power domain and reset control data to omap-prm driver for omap4/5 and dra7 - Add device tree data for remaining power domains and reset control for omap4/5 and dra7 dts files - Update dss, dsp, iva and gpmc dts files to use genpd and to drop the remaining platform data - Update dss for omap5 to use genpd - Update dra7 iva to to use genpd and to drop the remaining platform data * tag 'omap-for-v5.11/genpd-rest-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2+: Fix am4 only build after genpd changes ARM: dts: Configure power domain for omap5 dss ARM: dts: omap5: add remaining PRM instances soc: ti: omap-prm: omap5: add genpd support for remaining PRM instances ARM: OMAP2+: Drop legacy platform data for dra7 gpmc ARM: dts: Configure interconnect target module for dra7 iva ARM: dts: dra7: add remaining PRM instances soc: ti: omap-prm: dra7: add genpd support for remaining PRM instances clk: ti: dra7: Drop idlest polling from IVA clkctrl clocks ARM: OMAP2+: Drop legacy platform data for omap4 gpmc ARM: OMAP2+: Drop legacy platform data for omap4 iva ARM: dts: Configure power domain for omap4 dsp ARM: dts: Configure power domain for omap4 dss ARM: dts: omap4: add remaining PRM instances soc: ti: omap-prm: omap4: add genpd support for remaining PRM instances clk: ti: omap4: Drop idlest polling from IVA clkctrl clocks Link: https://lore.kernel.org/r/pull-1606806458-694517@atomide.com-4 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
+136
-15
@@ -724,22 +724,40 @@
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/* OCP2SCP1 */
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/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x37c>; /* device IO registers */
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma_xbar 4 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000000 4>,
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<0x50000010 4>,
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<0x50000014 4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
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<0x00000000 0x00000000 0x40000000>; /* data */
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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reg = <0x50000000 0x37c>; /* device IO registers */
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma_xbar 4 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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target-module@56000000 {
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@@ -962,6 +980,32 @@
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};
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};
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iva_hd_target: target-module@5a000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5a05a400 0x4>,
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<0x5a05a410 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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power-domains = <&prm_iva>;
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resets = <&prm_iva 2>;
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reset-names = "rstctrl";
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clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5a000000 0x5a000000 0x1000000>,
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<0x5b000000 0x5b000000 0x1000000>;
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iva {
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compatible = "ti,ivahd";
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};
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};
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opp_supply_mpu: opp-supply@4a003b20 {
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compatible = "ti,omap5-opp-supply";
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reg = <0x4a003b20 0xc>;
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@@ -1031,53 +1075,130 @@
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#include "dra7xx-clocks.dtsi"
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&prm {
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prm_mpu: prm@300 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x300 0x100>;
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#power-domain-cells = <0>;
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};
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prm_dsp1: prm@400 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x400 0x100>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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prm_ipu: prm@500 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x500 0x100>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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prm_coreaon: prm@628 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x628 0xd8>;
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#power-domain-cells = <0>;
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};
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prm_core: prm@700 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x700 0x100>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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prm_iva: prm@f00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0xf00 0x100>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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prm_cam: prm@1000 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1000 0x100>;
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#power-domain-cells = <0>;
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};
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prm_dss: prm@1100 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1100 0x100>;
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#power-domain-cells = <0>;
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};
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prm_gpu: prm@1200 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1200 0x100>;
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#power-domain-cells = <0>;
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};
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prm_l3init: prm@1300 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1300 0x100>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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prm_l4per: prm@1400 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1400 0x100>;
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#power-domain-cells = <0>;
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};
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prm_custefuse: prm@1600 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1600 0x100>;
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#power-domain-cells = <0>;
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};
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prm_wkupaon: prm@1724 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1724 0x100>;
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#power-domain-cells = <0>;
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};
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prm_dsp2: prm@1b00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b00 0x40>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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prm_eve1: prm@1b40 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b40 0x40>;
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#power-domain-cells = <0>;
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};
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prm_eve2: prm@1b80 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1b80 0x40>;
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#power-domain-cells = <0>;
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};
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prm_eve3: prm@1bc0 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1bc0 0x40>;
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#power-domain-cells = <0>;
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};
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prm_eve4: prm@1c00 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1c00 0x60>;
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#power-domain-cells = <0>;
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};
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prm_rtc: prm@1c60 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1c60 0x20>;
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#power-domain-cells = <0>;
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};
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prm_vpe: prm@1c80 {
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compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
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reg = <0x1c80 0x80>;
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#power-domain-cells = <0>;
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};
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};
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@@ -1726,6 +1726,20 @@
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};
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};
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iva_cm: iva-cm@f00 {
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compatible = "ti,omap4-cm";
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reg = <0xf00 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xf00 0x100>;
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iva_clkctrl: iva-clkctrl@20 {
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compatible = "ti,clkctrl";
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reg = <0x20 0xc>;
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#clock-cells = <2>;
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};
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};
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cam_cm: cam-cm@1000 {
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compatible = "ti,omap4-cm";
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reg = <0x1000 0x100>;
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@@ -330,6 +330,7 @@
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/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
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clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
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clock-names = "fck";
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power-domains = <&prm_tesla>;
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resets = <&prm_tesla 1>;
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reset-names = "rstctrl";
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#address-cells = <1>;
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+129
-21
@@ -107,11 +107,6 @@
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ti,hwmods = "mpu";
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sram = <&ocmcram>;
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};
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iva {
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compatible = "ti,ivahd";
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ti,hwmods = "iva";
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};
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};
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/*
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@@ -150,24 +145,41 @@
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reg = <0x40304000 0xa000>; /* 40k */
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 4>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000000 4>,
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<0x50000010 4>,
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<0x50000014 4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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ti,no-idle-on-init;
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clocks = <&l3_div_ck>;
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clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
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clock-names = "fck";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
|
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ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
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<0x00000000 0x00000000 0x40000000>; /* data */
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
|
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
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dmas = <&sdma 4>;
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dma-names = "rxtx";
|
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gpmc,num-cs = <8>;
|
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gpmc,num-waitpins = <4>;
|
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clocks = <&l3_div_ck>;
|
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clock-names = "fck";
|
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interrupt-controller;
|
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#interrupt-cells = <2>;
|
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gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
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|
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target-module@52000000 {
|
||||
@@ -445,6 +457,7 @@
|
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<0x58000014 4>;
|
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reg-names = "rev", "syss";
|
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ti,syss-mask = <1>;
|
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power-domains = <&prm_dss>;
|
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clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
|
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<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
|
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<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
|
||||
@@ -650,6 +663,32 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
iva_hd_target: target-module@5a000000 {
|
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compatible = "ti,sysc-omap4", "ti,sysc";
|
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reg = <0x5a05a400 0x4>,
|
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<0x5a05a410 0x4>;
|
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reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
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<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
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<SYSC_IDLE_SMART>;
|
||||
power-domains = <&prm_ivahd>;
|
||||
resets = <&prm_ivahd 2>;
|
||||
reset-names = "rstctrl";
|
||||
clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x5a000000 0x5a000000 0x1000000>,
|
||||
<0x5b000000 0x5b000000 0x1000000>;
|
||||
|
||||
iva {
|
||||
compatible = "ti,ivahd";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -658,10 +697,17 @@
|
||||
#include "omap44xx-clocks.dtsi"
|
||||
|
||||
&prm {
|
||||
prm_mpu: prm@300 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x300 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_tesla: prm@400 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x400 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_abe: prm@500 {
|
||||
@@ -670,16 +716,78 @@
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_always_on_core: prm@600 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x600 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_core: prm@700 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x700 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_ivahd: prm@f00 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0xf00 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_cam: prm@1000 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1000 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_dss: prm@1100 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1100 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_gfx: prm@1200 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1200 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_l3init: prm@1300 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1300 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_l4per: prm@1400 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1400 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_cefuse: prm@1600 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1600 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_wkup: prm@1700 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1700 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_emu: prm@1900 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1900 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_dss: prm@1100 {
|
||||
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1100 0x40>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_device: prm@1b00 {
|
||||
|
||||
@@ -410,6 +410,7 @@
|
||||
<0x58000014 4>;
|
||||
reg-names = "rev", "syss";
|
||||
ti,syss-mask = <1>;
|
||||
power-domains = <&prm_dss>;
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
|
||||
@@ -670,10 +671,17 @@
|
||||
#include "omap54xx-clocks.dtsi"
|
||||
|
||||
&prm {
|
||||
prm_mpu: prm@300 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x300 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_dsp: prm@400 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x400 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_abe: prm@500 {
|
||||
@@ -682,16 +690,66 @@
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_coreaon: prm@600 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x600 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_core: prm@700 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x700 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_iva: prm@1200 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1200 0x100>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_cam: prm@1300 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1300 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_dss: prm@1400 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1400 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_gpu: prm@1500 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1500 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_l3init: prm@1600 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1600 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_custefuse: prm@1700 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1700 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_wkupaon: prm@1800 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1800 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_emu: prm@1a00 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1a00 0x100>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
|
||||
prm_device: prm@1c00 {
|
||||
|
||||
@@ -588,7 +588,6 @@ void __init am43xx_init_early(void)
|
||||
omap2_prcm_base_init();
|
||||
am43xx_powerdomains_init();
|
||||
am43xx_clockdomains_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap_l2_cache_init();
|
||||
omap_clk_soc_init = am43xx_dt_clk_init;
|
||||
omap_secure_init();
|
||||
|
||||
@@ -353,42 +353,6 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'gpmc' class
|
||||
* general purpose memory controller
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
|
||||
.name = "gpmc",
|
||||
.sysc = &omap44xx_gpmc_sysc,
|
||||
};
|
||||
|
||||
/* gpmc */
|
||||
static struct omap_hwmod omap44xx_gpmc_hwmod = {
|
||||
.name = "gpmc",
|
||||
.class = &omap44xx_gpmc_hwmod_class,
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
|
||||
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'iss' class
|
||||
* external images sensor pixel data processor
|
||||
@@ -440,39 +404,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
|
||||
};
|
||||
|
||||
/*
|
||||
* 'iva' class
|
||||
* multi-standard video encoder/decoder hardware accelerator
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
|
||||
.name = "iva",
|
||||
};
|
||||
|
||||
/* iva */
|
||||
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
|
||||
{ .name = "seq0", .rst_shift = 0 },
|
||||
{ .name = "seq1", .rst_shift = 1 },
|
||||
{ .name = "logic", .rst_shift = 2 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_iva_hwmod = {
|
||||
.name = "iva",
|
||||
.class = &omap44xx_iva_hwmod_class,
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.rst_lines = omap44xx_iva_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
|
||||
.main_clk = "dpll_iva_m5x2_ck",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
|
||||
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
|
||||
.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'mpu' class
|
||||
* mpu sub-system
|
||||
@@ -644,14 +575,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* iva -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
|
||||
.master = &omap44xx_iva_hwmod,
|
||||
.slave = &omap44xx_l3_instr_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_3 -> l3_instr */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
|
||||
.master = &omap44xx_l3_main_3_hwmod,
|
||||
@@ -708,14 +631,6 @@ static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* iva -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
|
||||
.master = &omap44xx_iva_hwmod,
|
||||
.slave = &omap44xx_l3_main_2_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> l3_main_2 */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
|
||||
.master = &omap44xx_l3_main_1_hwmod,
|
||||
@@ -836,14 +751,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> gpmc */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_gpmc_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> iss */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
@@ -852,22 +759,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* iva -> sl2if */
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
|
||||
.master = &omap44xx_iva_hwmod,
|
||||
.slave = &omap44xx_sl2if_hwmod,
|
||||
.clk = "dpll_iva_m5x2_ck",
|
||||
.user = OCP_USER_IVA,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> iva */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_iva_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* l3_main_2 -> ocmc_ram */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
@@ -943,7 +834,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
|
||||
static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l3_main_1__dmm,
|
||||
&omap44xx_mpu__dmm,
|
||||
&omap44xx_iva__l3_instr,
|
||||
&omap44xx_l3_main_3__l3_instr,
|
||||
&omap44xx_ocp_wp_noc__l3_instr,
|
||||
&omap44xx_l3_main_2__l3_main_1,
|
||||
@@ -951,7 +841,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_mpu__l3_main_1,
|
||||
&omap44xx_debugss__l3_main_2,
|
||||
&omap44xx_iss__l3_main_2,
|
||||
&omap44xx_iva__l3_main_2,
|
||||
&omap44xx_l3_main_1__l3_main_2,
|
||||
&omap44xx_l4_cfg__l3_main_2,
|
||||
&omap44xx_l3_main_1__l3_main_3,
|
||||
@@ -967,10 +856,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l4_wkup__ctrl_module_wkup,
|
||||
&omap44xx_l4_wkup__ctrl_module_pad_wkup,
|
||||
&omap44xx_l3_instr__debugss,
|
||||
&omap44xx_l3_main_2__gpmc,
|
||||
&omap44xx_l3_main_2__iss,
|
||||
/* &omap44xx_iva__sl2if, */
|
||||
&omap44xx_l3_main_2__iva,
|
||||
&omap44xx_l3_main_2__ocmc_ram,
|
||||
&omap44xx_mpu_private__prcm_mpu,
|
||||
&omap44xx_l4_wkup__cm_core_aon,
|
||||
|
||||
@@ -242,46 +242,6 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* 'gpmc' class
|
||||
*
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
|
||||
.name = "gpmc",
|
||||
.sysc = &dra7xx_gpmc_sysc,
|
||||
};
|
||||
|
||||
/* gpmc */
|
||||
|
||||
static struct omap_hwmod dra7xx_gpmc_hwmod = {
|
||||
.name = "gpmc",
|
||||
.class = &dra7xx_gpmc_hwmod_class,
|
||||
.clkdm_name = "l3main1_clkdm",
|
||||
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
|
||||
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
|
||||
.main_clk = "l3_iclk_div",
|
||||
.prcm = {
|
||||
.omap4 = {
|
||||
.clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
|
||||
.context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
|
||||
.modulemode = MODULEMODE_HWCTRL,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* 'mpu' class
|
||||
*
|
||||
@@ -611,14 +571,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l3_main_1 -> gpmc */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
|
||||
.master = &dra7xx_l3_main_1_hwmod,
|
||||
.slave = &dra7xx_gpmc_hwmod,
|
||||
.clk = "l3_iclk_div",
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_cfg -> mpu */
|
||||
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
|
||||
.master = &dra7xx_l4_cfg_hwmod,
|
||||
@@ -722,7 +674,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&dra7xx_l4_per2__atl,
|
||||
&dra7xx_l3_main_1__bb2d,
|
||||
&dra7xx_l4_wkup__ctrl_module_wkup,
|
||||
&dra7xx_l3_main_1__gpmc,
|
||||
&dra7xx_l4_cfg__mpu,
|
||||
&dra7xx_l3_main_1__pciess1,
|
||||
&dra7xx_l4_cfg__pciess1,
|
||||
|
||||
@@ -274,14 +274,6 @@ static void __init omap3_pandora_legacy_init(void)
|
||||
}
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
#if defined(CONFIG_SOC_AM43XX)
|
||||
static struct wkup_m3_platform_data wkup_m3_data = {
|
||||
.reset_name = "wkup_m3",
|
||||
.assert_reset = omap_device_assert_hardreset,
|
||||
.deassert_reset = omap_device_deassert_hardreset,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP5
|
||||
static void __init omap5_uevm_legacy_init(void)
|
||||
{
|
||||
@@ -507,10 +499,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
|
||||
OF_DEV_AUXDATA("ti,omap3-mcbsp", 0x49024000, "49024000.mcbsp", &mcbsp_pdata),
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_SOC_AM43XX
|
||||
OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
|
||||
&wkup_m3_data),
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
|
||||
OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000,
|
||||
"4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]),
|
||||
|
||||
@@ -255,7 +255,7 @@ static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initco
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
|
||||
{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m5x2_ck" },
|
||||
{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
@@ -252,6 +252,12 @@ static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initcons
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = {
|
||||
{ DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" },
|
||||
{ DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
static const char * const dra7_dss_dss_clk_parents[] __initconst = {
|
||||
"dpll_per_h12x2_ck",
|
||||
NULL,
|
||||
@@ -827,6 +833,7 @@ const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
|
||||
{ 0x4a008c00, dra7_atl_clkctrl_regs },
|
||||
{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
|
||||
{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
|
||||
{ 0x4a008f20, dra7_iva_clkctrl_regs },
|
||||
{ 0x4a009020, dra7_cam_clkctrl_regs },
|
||||
{ 0x4a009120, dra7_dss_clkctrl_regs },
|
||||
{ 0x4a009220, dra7_gpu_clkctrl_regs },
|
||||
|
||||
+221
-17
@@ -128,6 +128,12 @@ static const struct omap_prm_domain_map omap_prm_alwon = {
|
||||
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE),
|
||||
};
|
||||
|
||||
static const struct omap_prm_domain_map omap_prm_reton = {
|
||||
.usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_RETENTION),
|
||||
.statechange = 1,
|
||||
.logicretstate = 1,
|
||||
};
|
||||
|
||||
static const struct omap_rst_map rst_map_0[] = {
|
||||
{ .rst = 0, .st = 0 },
|
||||
{ .rst = -1 },
|
||||
@@ -147,39 +153,237 @@ static const struct omap_rst_map rst_map_012[] = {
|
||||
};
|
||||
|
||||
static const struct omap_prm_data omap4_prm_data[] = {
|
||||
{ .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{
|
||||
.name = "mpu", .base = 0x4a306300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
},
|
||||
{
|
||||
.name = "tesla", .base = 0x4a306400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "abe", .base = 0x4a306500,
|
||||
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
|
||||
},
|
||||
{ .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 },
|
||||
{ .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
|
||||
{ .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
|
||||
{
|
||||
.name = "always_on_core", .base = 0x4a306600,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
},
|
||||
{
|
||||
.name = "core", .base = 0x4a306700,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati",
|
||||
.rstmap = rst_map_012
|
||||
},
|
||||
{
|
||||
.name = "ivahd", .base = 0x4a306f00,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
|
||||
},
|
||||
{
|
||||
.name = "cam", .base = 0x4a307000,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{
|
||||
.name = "dss", .base = 0x4a307100,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
|
||||
},
|
||||
{
|
||||
.name = "gfx", .base = 0x4a307200,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "l3init", .base = 0x4a307300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
|
||||
},
|
||||
{
|
||||
.name = "l4per", .base = 0x4a307400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
|
||||
},
|
||||
{
|
||||
.name = "cefuse", .base = 0x4a307600,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "wkup", .base = 0x4a307700,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
|
||||
},
|
||||
{
|
||||
.name = "emu", .base = 0x4a307900,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "device", .base = 0x4a307b00,
|
||||
.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
|
||||
.flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct omap_prm_data omap5_prm_data[] = {
|
||||
{ .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{
|
||||
.name = "mpu", .base = 0x4ae06300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
},
|
||||
{
|
||||
.name = "dsp", .base = 0x4ae06400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "abe", .base = 0x4ae06500,
|
||||
.pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
|
||||
},
|
||||
{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 },
|
||||
{ .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
|
||||
{ .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
|
||||
{
|
||||
.name = "coreaon", .base = 0x4ae06600,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
|
||||
},
|
||||
{
|
||||
.name = "core", .base = 0x4ae06700,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
.rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu",
|
||||
.rstmap = rst_map_012
|
||||
},
|
||||
{
|
||||
.name = "iva", .base = 0x4ae07200,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012
|
||||
},
|
||||
{
|
||||
.name = "cam", .base = 0x4ae07300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "dss", .base = 0x4ae07400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact
|
||||
},
|
||||
{
|
||||
.name = "gpu", .base = 0x4ae07500,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "l3init", .base = 0x4ae07600,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton
|
||||
},
|
||||
{
|
||||
.name = "custefuse", .base = 0x4ae07700,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "wkupaon", .base = 0x4ae07800,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon
|
||||
},
|
||||
{
|
||||
.name = "emu", .base = 0x4ae07a00,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto
|
||||
},
|
||||
{
|
||||
.name = "device", .base = 0x4ae07c00,
|
||||
.rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01,
|
||||
.flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
static const struct omap_prm_data dra7_prm_data[] = {
|
||||
{ .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{ .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 },
|
||||
{ .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 },
|
||||
{ .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
|
||||
{ .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{ .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{ .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{ .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{ .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
|
||||
{
|
||||
.name = "mpu", .base = 0x4ae06300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_reton,
|
||||
},
|
||||
{
|
||||
.name = "dsp1", .base = 0x4ae06400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01,
|
||||
},
|
||||
{
|
||||
.name = "ipu", .base = 0x4ae06500,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
|
||||
.clkdm_name = "ipu1"
|
||||
},
|
||||
{
|
||||
.name = "coreaon", .base = 0x4ae06628,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
},
|
||||
{
|
||||
.name = "core", .base = 0x4ae06700,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
.rstctrl = 0x210, .rstst = 0x214, .rstmap = rst_map_012,
|
||||
.clkdm_name = "ipu2"
|
||||
},
|
||||
{
|
||||
.name = "iva", .base = 0x4ae06f00,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
|
||||
},
|
||||
{
|
||||
.name = "cam", .base = 0x4ae07000,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{
|
||||
.name = "dss", .base = 0x4ae07100,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{
|
||||
.name = "gpu", .base = 0x4ae07200,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{
|
||||
.name = "l3init", .base = 0x4ae07300,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012,
|
||||
.clkdm_name = "pcie"
|
||||
},
|
||||
{
|
||||
.name = "l4per", .base = 0x4ae07400,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
},
|
||||
{
|
||||
.name = "custefuse", .base = 0x4ae07600,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{
|
||||
.name = "wkupaon", .base = 0x4ae07724,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
},
|
||||
{
|
||||
.name = "emu", .base = 0x4ae07900,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{
|
||||
.name = "dsp2", .base = 0x4ae07b00,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "eve1", .base = 0x4ae07b40,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "eve2", .base = 0x4ae07b80,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "eve3", .base = 0x4ae07bc0,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "eve4", .base = 0x4ae07c00,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
.rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01
|
||||
},
|
||||
{
|
||||
.name = "rtc", .base = 0x4ae07c60,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon,
|
||||
},
|
||||
{
|
||||
.name = "vpe", .base = 0x4ae07c80,
|
||||
.pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
|
||||
@@ -84,6 +84,10 @@
|
||||
#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
|
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#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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/* iva clocks */
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#define DRA7_IVA_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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#define DRA7_SL2IF_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
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/* dss clocks */
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#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
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#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
|
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|
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Reference in New Issue
Block a user