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octeon_ep: control mailbox for multiple PFs

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Add control mailbox support for multiple PFs.
Update control mbox base address calculation based on PF function link.

Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
Signed-off-by: Abhijit Ayarekar <aayarekar@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Veerasenareddy Burru
2023-03-24 10:46:58 -07:00
committed by David S. Miller
parent 24d4333233
commit 7c05d3d06c
1 changed files with 15 additions and 1 deletions
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drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+15 -1
View File
@@ -13,6 +13,9 @@
#include "octep_main.h"
#include "octep_regs_cn9k_pf.h"
#define CTRL_MBOX_MAX_PF 128
#define CTRL_MBOX_SZ ((size_t)(0x400000 / CTRL_MBOX_MAX_PF))
/* Names of Hardware non-queue generic interrupts */
static char *cn93_non_ioq_msix_names[] = {
"epf_ire_rint",
@@ -198,7 +201,9 @@ static void octep_init_config_cn93_pf(struct octep_device *oct)
{
struct octep_config *conf = oct->conf;
struct pci_dev *pdev = oct->pdev;
u8 link = 0;
u64 val;
int pos;
/* Read ring configuration:
* PF ring count, number of VFs and rings per VF supported
@@ -234,7 +239,16 @@ static void octep_init_config_cn93_pf(struct octep_device *oct)
conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings;
conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names;
conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr + (0x400000ull * 7);
pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV);
if (pos) {
pci_read_config_byte(oct->pdev,
pos + PCI_SRIOV_FUNC_LINK,
&link);
link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link);
}
conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr +
(0x400000ull * 7) +
(link * CTRL_MBOX_SZ);
}
/* Setup registers for a hardware Tx Queue */