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Merge refs/heads/release from master.kernel.org:/pub/scm/linux/kernel/git/aegl/linux-2.6

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This commit is contained in:
Linus Torvalds
2005-09-01 10:58:18 -07:00
parent b25dd2842b 986632fd70
commit 712fbdd333
52 changed files with 3091 additions and 416 deletions
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include/asm-ia64/acpi.h
+5
View File
@@ -116,6 +116,11 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
extern u16 ia64_acpiid_to_sapicid[];
/*
* Refer Intel ACPI _PDC support document for bit definitions
*/
#define ACPI_PDC_EST_CAPABILITY_SMP 0x8
#endif /*__KERNEL__*/
#endif /*_ASM_ACPI_H*/
include/asm-ia64/fcntl.h
+2 -1
View File
@@ -81,6 +81,7 @@ struct flock {
#define F_LINUX_SPECIFIC_BASE 1024
#define force_o_largefile() ( ! (current->personality & PER_LINUX32) )
#define force_o_largefile() \
(personality(current->personality) != PER_LINUX32)
#endif /* _ASM_IA64_FCNTL_H */
include/asm-ia64/io.h
+2 -2
View File
@@ -23,7 +23,7 @@
#define __SLOW_DOWN_IO do { } while (0)
#define SLOW_DOWN_IO do { } while (0)
#define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */
#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
/*
* The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
@@ -41,7 +41,7 @@
#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | (p & 0xfff))
#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
struct io_space {
unsigned long mmio_base; /* base in MMIO space */
include/asm-ia64/mmu.h
+5 -3
View File
@@ -2,10 +2,12 @@
#define __MMU_H
/*
* Type for a context number. We declare it volatile to ensure proper ordering when it's
* accessed outside of spinlock'd critical sections (e.g., as done in activate_mm() and
* init_new_context()).
* Type for a context number. We declare it volatile to ensure proper
* ordering when it's accessed outside of spinlock'd critical sections
* (e.g., as done in activate_mm() and init_new_context()).
*/
typedef volatile unsigned long mm_context_t;
typedef unsigned long nv_mm_context_t;
#endif
include/asm-ia64/mmu_context.h
+37 -22
View File
@@ -19,6 +19,7 @@
#define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61))
# include <asm/page.h>
# ifndef __ASSEMBLY__
#include <linux/compiler.h>
@@ -55,34 +56,46 @@ static inline void
delayed_tlb_flush (void)
{
extern void local_flush_tlb_all (void);
unsigned long flags;
if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
local_flush_tlb_all();
__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
spin_lock_irqsave(&ia64_ctx.lock, flags);
{
if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
local_flush_tlb_all();
__ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
}
}
spin_unlock_irqrestore(&ia64_ctx.lock, flags);
}
}
static inline mm_context_t
static inline nv_mm_context_t
get_mmu_context (struct mm_struct *mm)
{
unsigned long flags;
mm_context_t context = mm->context;
nv_mm_context_t context = mm->context;
if (context)
return context;
spin_lock_irqsave(&ia64_ctx.lock, flags);
{
/* re-check, now that we've got the lock: */
context = mm->context;
if (context == 0) {
cpus_clear(mm->cpu_vm_mask);
if (ia64_ctx.next >= ia64_ctx.limit)
wrap_mmu_context(mm);
mm->context = context = ia64_ctx.next++;
if (unlikely(!context)) {
spin_lock_irqsave(&ia64_ctx.lock, flags);
{
/* re-check, now that we've got the lock: */
context = mm->context;
if (context == 0) {
cpus_clear(mm->cpu_vm_mask);
if (ia64_ctx.next >= ia64_ctx.limit)
wrap_mmu_context(mm);
mm->context = context = ia64_ctx.next++;
}
}
spin_unlock_irqrestore(&ia64_ctx.lock, flags);
}
spin_unlock_irqrestore(&ia64_ctx.lock, flags);
/*
* Ensure we're not starting to use "context" before any old
* uses of it are gone from our TLB.
*/
delayed_tlb_flush();
return context;
}
@@ -104,13 +117,13 @@ destroy_context (struct mm_struct *mm)
}
static inline void
reload_context (mm_context_t context)
reload_context (nv_mm_context_t context)
{
unsigned long rid;
unsigned long rid_incr = 0;
unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
old_rr4 = ia64_get_rr(0x8000000000000000UL);
old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
rid = context << 3; /* make space for encoding the region number */
rid_incr = 1 << 8;
@@ -122,6 +135,10 @@ reload_context (mm_context_t context)
rr4 = rr0 + 4*rid_incr;
#ifdef CONFIG_HUGETLB_PAGE
rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
# if RGN_HPAGE != 4
# error "reload_context assumes RGN_HPAGE is 4"
# endif
#endif
ia64_set_rr(0x0000000000000000UL, rr0);
@@ -138,7 +155,7 @@ reload_context (mm_context_t context)
static inline void
activate_context (struct mm_struct *mm)
{
mm_context_t context;
nv_mm_context_t context;
do {
context = get_mmu_context(mm);
@@ -157,8 +174,6 @@ activate_context (struct mm_struct *mm)
static inline void
activate_mm (struct mm_struct *prev, struct mm_struct *next)
{
delayed_tlb_flush();
/*
* We may get interrupts here, but that's OK because interrupt handlers cannot
* touch user-space.
include/asm-ia64/page.h
+18 -9
View File
@@ -12,6 +12,19 @@
#include <asm/intrinsics.h>
#include <asm/types.h>
/*
* The top three bits of an IA64 address are its Region Number.
* Different regions are assigned to different purposes.
*/
#define RGN_SHIFT (61)
#define RGN_BASE(r) (__IA64_UL_CONST(r)<<RGN_SHIFT)
#define RGN_BITS (RGN_BASE(-1))
#define RGN_KERNEL 7 /* Identity mapped region */
#define RGN_UNCACHED 6 /* Identity mapped I/O region */
#define RGN_GATE 5 /* Gate page, Kernel text, etc */
#define RGN_HPAGE 4 /* For Huge TLB pages */
/*
* PAGE_SHIFT determines the actual kernel page size.
*/
@@ -36,10 +49,9 @@
#define RGN_MAP_LIMIT ((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) /* per region addr limit */
#ifdef CONFIG_HUGETLB_PAGE
# define REGION_HPAGE (4UL) /* note: this is hardcoded in reload_context()!*/
# define REGION_SHIFT 61
# define HPAGE_REGION_BASE (REGION_HPAGE << REGION_SHIFT)
# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE)
# define HPAGE_SHIFT hpage_shift
# define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */
# define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT)
@@ -130,16 +142,13 @@ typedef union ia64_va {
#define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
#define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
#define REGION_SIZE REGION_NUMBER(1)
#define REGION_KERNEL 7
#ifdef CONFIG_HUGETLB_PAGE
# define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \
| (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT)))
# define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
# define is_hugepage_only_range(mm, addr, len) \
(REGION_NUMBER(addr) == REGION_HPAGE && \
REGION_NUMBER((addr)+(len)-1) == REGION_HPAGE)
(REGION_NUMBER(addr) == RGN_HPAGE && \
REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE)
extern unsigned int hpage_shift;
#endif
@@ -197,7 +206,7 @@ get_order (unsigned long size)
# define __pgprot(x) (x)
#endif /* !STRICT_MM_TYPECHECKS */
#define PAGE_OFFSET __IA64_UL_CONST(0xe000000000000000)
#define PAGE_OFFSET RGN_BASE(RGN_KERNEL)
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | \
include/asm-ia64/pal.h
+21
View File
@@ -75,6 +75,8 @@
#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
#define PAL_VM_TR_READ 261 /* read contents of translation register */
#define PAL_GET_PSTATE 262 /* get the current P-state */
#define PAL_SET_PSTATE 263 /* set the P-state */
#ifndef __ASSEMBLY__
@@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
return iprv.status;
}
/* Get the current P-state information */
static inline s64
ia64_pal_get_pstate (u64 *pstate_index)
{
struct ia64_pal_retval iprv;
PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
*pstate_index = iprv.v0;
return iprv.status;
}
/* Set the P-state */
static inline s64
ia64_pal_set_pstate (u64 pstate_index)
{
struct ia64_pal_retval iprv;
PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
return iprv.status;
}
/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
* suspended, but cache and TLB coherency is maintained.
*/
include/asm-ia64/pgtable.h
+5 -8
View File
@@ -204,21 +204,18 @@ ia64_phys_addr_valid (unsigned long addr)
#define set_pte(ptep, pteval) (*(ptep) = (pteval))
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
#define RGN_SIZE (1UL << 61)
#define RGN_KERNEL 7
#define VMALLOC_START 0xa000000200000000UL
#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
#ifdef CONFIG_VIRTUAL_MEM_MAP
# define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
# define VMALLOC_END vmalloc_end
extern unsigned long vmalloc_end;
#else
# define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
#endif
/* fs/proc/kcore.c */
#define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL)
#define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL)
#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
/*
* Conversion functions: convert page frame number (pfn) and a protection value to a page
include/asm-ia64/rwsem.h
+18 -17
View File
@@ -3,6 +3,7 @@
*
* Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com>
* Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com>
* Copyright (C) 2005 Christoph Lameter <clameter@sgi.com>
*
* Based on asm-i386/rwsem.h and other architecture implementation.
*
@@ -11,9 +12,9 @@
*
* The lock count is initialized to 0 (no active and no waiting lockers).
*
* When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case
* of an uncontended lock. Readers increment by 1 and see a positive value
* when uncontended, negative if there are writers (and maybe) readers
* When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for
* the case of an uncontended lock. Readers increment by 1 and see a positive
* value when uncontended, negative if there are writers (and maybe) readers
* waiting (in which case it goes to sleep).
*/
@@ -29,7 +30,7 @@
* the semaphore definition
*/
struct rw_semaphore {
signed int count;
signed long count;
spinlock_t wait_lock;
struct list_head wait_list;
#if RWSEM_DEBUG
@@ -37,10 +38,10 @@ struct rw_semaphore {
#endif
};
#define RWSEM_UNLOCKED_VALUE 0x00000000
#define RWSEM_ACTIVE_BIAS 0x00000001
#define RWSEM_ACTIVE_MASK 0x0000ffff
#define RWSEM_WAITING_BIAS (-0x00010000)
#define RWSEM_UNLOCKED_VALUE __IA64_UL_CONST(0x0000000000000000)
#define RWSEM_ACTIVE_BIAS __IA64_UL_CONST(0x0000000000000001)
#define RWSEM_ACTIVE_MASK __IA64_UL_CONST(0x00000000ffffffff)
#define RWSEM_WAITING_BIAS -__IA64_UL_CONST(0x0000000100000000)
#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
@@ -83,7 +84,7 @@ init_rwsem (struct rw_semaphore *sem)
static inline void
__down_read (struct rw_semaphore *sem)
{
int result = ia64_fetchadd4_acq((unsigned int *)&sem->count, 1);
long result = ia64_fetchadd8_acq((unsigned long *)&sem->count, 1);
if (result < 0)
rwsem_down_read_failed(sem);
@@ -95,7 +96,7 @@ __down_read (struct rw_semaphore *sem)
static inline void
__down_write (struct rw_semaphore *sem)
{
int old, new;
long old, new;
do {
old = sem->count;
@@ -112,7 +113,7 @@ __down_write (struct rw_semaphore *sem)
static inline void
__up_read (struct rw_semaphore *sem)
{
int result = ia64_fetchadd4_rel((unsigned int *)&sem->count, -1);
long result = ia64_fetchadd8_rel((unsigned long *)&sem->count, -1);
if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0)
rwsem_wake(sem);
@@ -124,7 +125,7 @@ __up_read (struct rw_semaphore *sem)
static inline void
__up_write (struct rw_semaphore *sem)
{
int old, new;
long old, new;
do {
old = sem->count;
@@ -141,7 +142,7 @@ __up_write (struct rw_semaphore *sem)
static inline int
__down_read_trylock (struct rw_semaphore *sem)
{
int tmp;
long tmp;
while ((tmp = sem->count) >= 0) {
if (tmp == cmpxchg_acq(&sem->count, tmp, tmp+1)) {
return 1;
@@ -156,7 +157,7 @@ __down_read_trylock (struct rw_semaphore *sem)
static inline int
__down_write_trylock (struct rw_semaphore *sem)
{
int tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
long tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
RWSEM_ACTIVE_WRITE_BIAS);
return tmp == RWSEM_UNLOCKED_VALUE;
}
@@ -167,7 +168,7 @@ __down_write_trylock (struct rw_semaphore *sem)
static inline void
__downgrade_write (struct rw_semaphore *sem)
{
int old, new;
long old, new;
do {
old = sem->count;
@@ -182,7 +183,7 @@ __downgrade_write (struct rw_semaphore *sem)
* Implement atomic add functionality. These used to be "inline" functions, but GCC v3.1
* doesn't quite optimize this stuff right and ends up with bad calls to fetchandadd.
*/
#define rwsem_atomic_add(delta, sem) atomic_add(delta, (atomic_t *)(&(sem)->count))
#define rwsem_atomic_update(delta, sem) atomic_add_return(delta, (atomic_t *)(&(sem)->count))
#define rwsem_atomic_add(delta, sem) atomic64_add(delta, (atomic64_t *)(&(sem)->count))
#define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
#endif /* _ASM_IA64_RWSEM_H */
include/asm-ia64/sn/addrs.h
+71 -41
View File
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_ADDRS_H
@@ -65,7 +65,6 @@
#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
#define REGION_BITS 0xe000000000000000UL
/*
@@ -79,38 +78,30 @@
#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
/*
* Base addresses for various address ranges.
*/
#define CACHED 0xe000000000000000UL
#define UNCACHED 0xc000000000000000UL
#define UNCACHED_PHYS 0x8000000000000000UL
/*
* Virtual Mode Local & Global MMR space.
*/
#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
#define LOCAL_MMR_SPACE (UNCACHED | LOCAL_MMR_OFFSET)
#define LOCAL_PHYS_MMR_SPACE (UNCACHED_PHYS | LOCAL_MMR_OFFSET)
#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
#define GLOBAL_MMR_SPACE (UNCACHED | GLOBAL_MMR_OFFSET)
#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
/*
* Physical mode addresses
*/
#define GLOBAL_PHYS_MMR_SPACE (UNCACHED_PHYS | GLOBAL_MMR_OFFSET)
#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
/*
* Clear region & AS bits.
*/
#define TO_PHYS_MASK (~(REGION_BITS | AS_MASK))
#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
/*
@@ -126,6 +117,7 @@
#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
#define IS_TIO_NASID(n) ((n) & 1)
/* non-II mmr's start at top of big window space (4G) */
@@ -134,10 +126,10 @@
/*
* general address defines
*/
#define CAC_BASE (CACHED | AS_CAC_SPACE)
#define AMO_BASE (UNCACHED | AS_AMO_SPACE)
#define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE)
#define GET_BASE (CACHED | AS_GET_SPACE)
#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
/*
* Convert Memory addresses between various addressing modes.
@@ -155,17 +147,35 @@
* the chiplet id is zero. If we implement TIO-TIO dma, we might need
* to insert a chiplet id into this macro. However, it is our belief
* right now that this chiplet id will be ICE, which is also zero.
* Nasid starts on bit 40.
*/
#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
#define SH1_TIO_PHYS_TO_DMA(x) \
((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
#define SH2_NETWORK_BANK_OFFSET(x) \
((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
#define SH2_NETWORK_BANK_SELECT(x) \
((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
>> (sn_hub_info->nasid_shift - 4)) << 36)
#define SH2_NETWORK_ADDRESS(x) \
(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
#define SH2_TIO_PHYS_TO_DMA(x) \
(((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
#define PHYS_TO_TIODMA(x) \
(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
#define PHYS_TO_DMA(x) \
((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
/*
* Macros to test for address type.
*/
#define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE)
#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE)
#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
/*
@@ -180,18 +190,20 @@
#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
((u64) (w) << TIO_SWIN_SIZE_BITS))
#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
#define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n))
#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
#define BWIN_WIDGET_MASK 0x7
#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
#define TIO_HWIN_SHIFT_BITS 33
#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
/*
* The following definitions pertain to the IO special address
@@ -216,10 +228,6 @@
#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
#define TIO_IOSPACE_ADDR(n,x) \
/* Move in the Chiplet ID for TIO Local Block MMR */ \
(REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
/*
* The following macros produce the correct base virtual address for
* the hub registers. The REMOTE_HUB_* macro produce
@@ -234,18 +242,40 @@
* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
* They're always safe.
*/
/* Shub1 TIO & MMR addressing macros */
#define SH1_TIO_IOSPACE_ADDR(n,x) \
GLOBAL_MMR_ADDR(n,x)
#define SH1_REMOTE_BWIN_MMR(n,x) \
GLOBAL_MMR_ADDR(n,x)
#define SH1_REMOTE_SWIN_MMR(n,x) \
(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
#define SH1_REMOTE_MMR(n,x) \
(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
SH1_REMOTE_SWIN_MMR(n,x))
/* Shub1 TIO & MMR addressing macros */
#define SH2_TIO_IOSPACE_ADDR(n,x) \
((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
#define SH2_REMOTE_MMR(n,x) \
GLOBAL_MMR_ADDR(n,x)
/* TIO & MMR addressing macros that work on both shub1 & shub2 */
#define TIO_IOSPACE_ADDR(n,x) \
((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
SH2_TIO_IOSPACE_ADDR(n,x)))
#define SH_REMOTE_MMR(n,x) \
(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
#define REMOTE_HUB_ADDR(n,x) \
((n & 1) ? \
/* TIO: */ \
(is_shub2() ? \
/* TIO on Shub2 */ \
(volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
: /* TIO on shub1 */ \
(volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
\
: /* SHUB1 and SHUB2 MMRs: */ \
(((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
: ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
(IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
((volatile u64*)SH_REMOTE_MMR(n,x)))
#define HUB_L(x) (*((volatile typeof(*x) *)x))
#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
include/asm-ia64/sn/geo.h
+1 -2
View File
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_GEO_H
@@ -108,7 +108,6 @@ typedef union geoid_u {
#define INVALID_SLAB (slabid_t)-1
#define INVALID_SLOT (slotid_t)-1
#define INVALID_MODULE ((moduleid_t)-1)
#define INVALID_PARTID ((partid_t)-1)
static inline slabid_t geo_slab(geoid_t g)
{
include/asm-ia64/sn/intr.h
+1 -2
View File
@@ -12,13 +12,12 @@
#include <linux/rcupdate.h>
#define SGI_UART_VECTOR (0xe9)
#define SGI_PCIBR_ERROR (0x33)
/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
#define SGI_XPC_ACTIVATE (0x30)
#define SGI_II_ERROR (0x31)
#define SGI_XBOW_ERROR (0x32)
#define SGI_PCIBR_ERROR (0x33)
#define SGI_PCIASIC_ERROR (0x33)
#define SGI_ACPI_SCI_INT (0x34)
#define SGI_TIOCA_ERROR (0x35)
#define SGI_TIO_ERROR (0x36)
include/asm-ia64/sn/nodepda.h
+2 -1
View File
@@ -37,7 +37,6 @@ struct phys_cpuid {
struct nodepda_s {
void *pdinfo; /* Platform-dependent per-node info */
spinlock_t bist_lock;
/*
* The BTEs on this node are shared by the local cpus
@@ -55,6 +54,8 @@ struct nodepda_s {
* Array of physical cpu identifiers. Indexed by cpuid.
*/
struct phys_cpuid phys_cpuid[NR_CPUS];
spinlock_t ptc_lock ____cacheline_aligned_in_smp;
spinlock_t bist_lock;
};
typedef struct nodepda_s nodepda_t;
include/asm-ia64/sn/pcibus_provider_defs.h
+6 -2
View File
@@ -18,8 +18,9 @@
#define PCIIO_ASIC_TYPE_PIC 2
#define PCIIO_ASIC_TYPE_TIOCP 3
#define PCIIO_ASIC_TYPE_TIOCA 4
#define PCIIO_ASIC_TYPE_TIOCE 5
#define PCIIO_ASIC_MAX_TYPES 5
#define PCIIO_ASIC_MAX_TYPES 6
/*
* Common pciio bus provider data. There should be one of these as the
@@ -30,7 +31,8 @@
struct pcibus_bussoft {
uint32_t bs_asic_type; /* chipset type */
uint32_t bs_xid; /* xwidget id */
uint64_t bs_persist_busnum; /* Persistent Bus Number */
uint32_t bs_persist_busnum; /* Persistent Bus Number */
uint32_t bs_persist_segment; /* Segment Number */
uint64_t bs_legacy_io; /* legacy io pio addr */
uint64_t bs_legacy_mem; /* legacy mem pio addr */
uint64_t bs_base; /* widget base */
@@ -47,6 +49,8 @@ struct sn_pcibus_provider {
dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
void (*force_interrupt)(struct sn_irq_info *);
void (*target_interrupt)(struct sn_irq_info *);
};
extern struct sn_pcibus_provider *sn_pci_provider[];
include/asm-ia64/sn/pda.h
-1
View File
@@ -39,7 +39,6 @@ typedef struct pda_s {
unsigned long pio_write_status_val;
volatile unsigned long *pio_shub_war_cam_addr;
unsigned long sn_soft_irr[4];
unsigned long sn_in_service_ivecs[4];
int sn_lb_int_war_ticks;
int sn_last_irq;
include/asm-ia64/sn/sn2/sn_hwperf.h
+10
View File
@@ -43,6 +43,7 @@ struct sn_hwperf_object_info {
/* macros for object classification */
#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
#define SN_HWPERF_IS_ROUTER(x) ((x) && strstr((x)->name, "Router"))
#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
@@ -214,6 +215,15 @@ struct sn_hwperf_ioctl_args {
*/
#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
/*
* Given a node id, determine the id of the nearest node with CPUs
* and the id of the nearest node that has memory. The argument
* node would normally be a "headless" node, e.g. an "IO node".
* Return 0 on success.
*/
extern int sn_hwperf_get_nearest_node(cnodeid_t node,
cnodeid_t *near_mem, cnodeid_t *near_cpu);
/* return codes */
#define SN_HWPERF_OP_OK 0
#define SN_HWPERF_OP_NOMEM 1
include/asm-ia64/sn/sn_sal.h
+6 -54
View File
@@ -55,7 +55,6 @@
#define SN_SAL_BUS_CONFIG 0x02000037
#define SN_SAL_SYS_SERIAL_GET 0x02000038
#define SN_SAL_PARTITION_SERIAL_GET 0x02000039
#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a
#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b
#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c
#define SN_SAL_COHERENCE 0x0200003d
@@ -78,7 +77,8 @@
#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
#define SN_SAL_BTE_RECOVER 0x02000061
#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000062
#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062
#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064
/*
* Service-specific constants
@@ -585,35 +585,6 @@ sn_partition_serial_number_val(void) {
return sn_partition_serial_number;
}
/*
* Returns the partition id of the nasid passed in as an argument,
* or INVALID_PARTID if the partition id cannot be retrieved.
*/
static inline partid_t
ia64_sn_sysctl_partition_get(nasid_t nasid)
{
struct ia64_sal_retval ret_stuff;
ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
0, 0, 0, 0, 0, 0);
if (ret_stuff.status != 0)
return INVALID_PARTID;
return ((partid_t)ret_stuff.v0);
}
/*
* Returns the partition id of the current processor.
*/
extern partid_t sn_partid;
static inline partid_t
sn_local_partid(void) {
if (unlikely(sn_partid < 0)) {
sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()));
}
return sn_partid;
}
/*
* Returns the physical address of the partition's reserved page through
* an iterative number of calls.
@@ -749,7 +720,8 @@ ia64_sn_power_down(void)
{
struct ia64_sal_retval ret_stuff;
SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
while(1);
while(1)
cpu_relax();
/* never returns */
}
@@ -1018,24 +990,6 @@ ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
ret_stuff.v2 = 0;
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
/***** BEGIN HACK - temp til old proms no longer supported ********/
if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
int nasid = get_sapicid() & 0xfff;;
#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
if (shubtype) *shubtype = 0;
if (nasid_bitmask) *nasid_bitmask = 0x7ff;
if (nasid_shift) *nasid_shift = 38;
if (systemsize) *systemsize = 11;
if (sharing_domain_size) *sharing_domain_size = 9;
if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
if (coher) *coher = nasid >> 9;
if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
SH_SHUB_ID_NODES_PER_BIT_SHFT;
return 0;
}
/***** END HACK *******/
if (ret_stuff.status < 0)
return ret_stuff.status;
@@ -1068,12 +1022,10 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
}
static inline int
ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab,
u64 buf, u64 len)
ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
{
struct ia64_sal_retval rv;
SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY,
rack, bay, slot, slab, buf, len, 0);
SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
return (int) rv.status;
}
include/asm-ia64/sn/tioce.h
+740
View File
@@ -0,0 +1,740 @@
/**************************************************************************
* *
* Unpublished copyright (c) 2005, Silicon Graphics, Inc. *
* THIS IS UNPUBLISHED CONFIDENTIAL AND PROPRIETARY SOURCE CODE OF SGI. *
* *
* The copyright notice above does not evidence any actual or intended *
* publication or disclosure of this source code, which includes *
* information that is confidential and/or proprietary, and is a trade *
* secret, of Silicon Graphics, Inc. ANY REPRODUCTION, MODIFICATION, *
* DISTRIBUTION, PUBLIC PERFORMANCE, OR PUBLIC DISPLAY OF OR THROUGH *
* USE OF THIS SOURCE CODE WITHOUT THE EXPRESS WRITTEN CONSENT OF *
* SILICON GRAPHICS, INC. IS STRICTLY PROHIBITED, AND IN VIOLATION OF *
* APPLICABLE LAWS AND INTERNATIONAL TREATIES. THE RECEIPT OR *
* POSSESSION OF THIS SOURCE CODE AND/OR RELATED INFORMATION DOES NOT *
* CONVEY OR IMPLY ANY RIGHTS TO REPRODUCE, DISCLOSE OR DISTRIBUTE ITS *
* CONTENTS, OR TO MANUFACTURE, USE, OR SELL ANYTHING THAT IT MAY *
* DESCRIBE, IN WHOLE OR IN PART. *
* *
**************************************************************************/
#ifndef __ASM_IA64_SN_TIOCE_H__
#define __ASM_IA64_SN_TIOCE_H__
/* CE ASIC part & mfgr information */
#define TIOCE_PART_NUM 0xCE00
#define TIOCE_MFGR_NUM 0x36
#define TIOCE_REV_A 0x1
/* CE Virtual PPB Vendor/Device IDs */
#define CE_VIRT_PPB_VENDOR_ID 0x10a9
#define CE_VIRT_PPB_DEVICE_ID 0x4002
/* CE Host Bridge Vendor/Device IDs */
#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
#define CE_HOST_BRIDGE_DEVICE_ID 0x4003
#define TIOCE_NUM_M40_ATES 4096
#define TIOCE_NUM_M3240_ATES 2048
#define TIOCE_NUM_PORTS 2
/*
* Register layout for TIOCE. MMR offsets are shown at the far right of the
* structure definition.
*/
typedef volatile struct tioce {
/*
* ADMIN : Administration Registers
*/
uint64_t ce_adm_id; /* 0x000000 */
uint64_t ce_pad_000008; /* 0x000008 */
uint64_t ce_adm_dyn_credit_status; /* 0x000010 */
uint64_t ce_adm_last_credit_status; /* 0x000018 */
uint64_t ce_adm_credit_limit; /* 0x000020 */
uint64_t ce_adm_force_credit; /* 0x000028 */
uint64_t ce_adm_control; /* 0x000030 */
uint64_t ce_adm_mmr_chn_timeout; /* 0x000038 */
uint64_t ce_adm_ssp_ure_timeout; /* 0x000040 */
uint64_t ce_adm_ssp_dre_timeout; /* 0x000048 */
uint64_t ce_adm_ssp_debug_sel; /* 0x000050 */
uint64_t ce_adm_int_status; /* 0x000058 */
uint64_t ce_adm_int_status_alias; /* 0x000060 */
uint64_t ce_adm_int_mask; /* 0x000068 */
uint64_t ce_adm_int_pending; /* 0x000070 */
uint64_t ce_adm_force_int; /* 0x000078 */
uint64_t ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
uint64_t ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
uint64_t ce_adm_error_summary; /* 0x000100 */
uint64_t ce_adm_error_summary_alias; /* 0x000108 */
uint64_t ce_adm_error_mask; /* 0x000110 */
uint64_t ce_adm_first_error; /* 0x000118 */
uint64_t ce_adm_error_overflow; /* 0x000120 */
uint64_t ce_adm_error_overflow_alias; /* 0x000128 */
uint64_t ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
uint64_t ce_adm_tnum_error; /* 0x000140 */
uint64_t ce_adm_mmr_err_detail; /* 0x000148 */
uint64_t ce_adm_msg_sram_perr_detail; /* 0x000150 */
uint64_t ce_adm_bap_sram_perr_detail; /* 0x000158 */
uint64_t ce_adm_ce_sram_perr_detail; /* 0x000160 */
uint64_t ce_adm_ce_credit_oflow_detail; /* 0x000168 */
uint64_t ce_adm_tx_link_idle_max_timer; /* 0x000170 */
uint64_t ce_adm_pcie_debug_sel; /* 0x000178 */
uint64_t ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
uint64_t ce_adm_pcie_debug_sel_top; /* 0x000200 */
uint64_t ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
uint64_t ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
uint64_t ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
uint64_t ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
uint64_t ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
uint64_t ce_adm_pcie_trig_compare_top; /* 0x000230 */
uint64_t ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
uint64_t ce_adm_ssp_debug_sel_top; /* 0x000240 */
uint64_t ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
uint64_t ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
uint64_t ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
uint64_t ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
uint64_t ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
uint64_t ce_adm_ssp_trig_compare_top; /* 0x000270 */
uint64_t ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
uint64_t ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
uint64_t ce_adm_bap_ctrl; /* 0x000400 */
uint64_t ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
uint64_t ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
uint64_t ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
uint64_t ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
uint64_t ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
uint64_t ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
uint64_t ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
uint64_t ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
/*
* LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
* Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
* NOTE: the comment offsets at far right: let 'z' = {2 or 3}
*/
#define ce_lsi(link_num) ce_lsi[link_num-1]
struct ce_lsi_reg {
uint64_t ce_lsi_lpu_id; /* 0x00z000 */
uint64_t ce_lsi_rst; /* 0x00z008 */
uint64_t ce_lsi_dbg_stat; /* 0x00z010 */
uint64_t ce_lsi_dbg_cfg; /* 0x00z018 */
uint64_t ce_lsi_ltssm_ctrl; /* 0x00z020 */
uint64_t ce_lsi_lk_stat; /* 0x00z028 */
uint64_t ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
uint64_t ce_lsi_int_and_stat; /* 0x00z040 */
uint64_t ce_lsi_int_mask; /* 0x00z048 */
uint64_t ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
uint64_t ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
uint64_t ce_pad_00z108; /* 0x00z108 */
uint64_t ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
uint64_t ce_pad_00z118; /* 0x00z118 */
uint64_t ce_lsi_lk_perf_cnt1; /* 0x00z120 */
uint64_t ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
uint64_t ce_lsi_lk_perf_cnt2; /* 0x00z130 */
uint64_t ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
uint64_t ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
uint64_t ce_lsi_lk_lyr_cfg; /* 0x00z200 */
uint64_t ce_lsi_lk_lyr_status; /* 0x00z208 */
uint64_t ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
uint64_t ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
uint64_t ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
uint64_t ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
uint64_t ce_lsi_fc_upd_ctl; /* 0x00z240 */
uint64_t ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
uint64_t ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
uint64_t ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
uint64_t ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
uint64_t ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
uint64_t ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
uint64_t ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
uint64_t ce_lsi_rply_tmr_thr; /* 0x00z410 */
uint64_t ce_lsi_rply_tmr; /* 0x00z418 */
uint64_t ce_lsi_rply_num_stat; /* 0x00z420 */
uint64_t ce_lsi_rty_buf_max_addr; /* 0x00z428 */
uint64_t ce_lsi_rty_fifo_ptr; /* 0x00z430 */
uint64_t ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
uint64_t ce_lsi_rty_fifo_cred; /* 0x00z440 */
uint64_t ce_lsi_seq_cnt; /* 0x00z448 */
uint64_t ce_lsi_ack_sent_seq_num; /* 0x00z450 */
uint64_t ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
uint64_t ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
uint64_t ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
uint64_t ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
uint64_t ce_pad_00z478; /* 0x00z478 */
uint64_t ce_lsi_mem_addr_ctl; /* 0x00z480 */
uint64_t ce_lsi_mem_d_ld0; /* 0x00z488 */
uint64_t ce_lsi_mem_d_ld1; /* 0x00z490 */
uint64_t ce_lsi_mem_d_ld2; /* 0x00z498 */
uint64_t ce_lsi_mem_d_ld3; /* 0x00z4A0 */
uint64_t ce_lsi_mem_d_ld4; /* 0x00z4A8 */
uint64_t ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
uint64_t ce_lsi_rty_d_cnt; /* 0x00z4C0 */
uint64_t ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
uint64_t ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
uint64_t ce_pad_00z4D8; /* 0x00z4D8 */
uint64_t ce_lsi_ack_lat_thr; /* 0x00z4E0 */
uint64_t ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
uint64_t ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
uint64_t ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
uint64_t ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
uint64_t ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
uint64_t ce_lsi_phy_lyr_cfg; /* 0x00z600 */
uint64_t ce_pad_00z608; /* 0x00z608 */
uint64_t ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
uint64_t ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
uint64_t ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
uint64_t ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
uint64_t ce_lsi_rcv_phy_cfg; /* 0x00z680 */
uint64_t ce_lsi_rcv_phy_stat1; /* 0x00z688 */
uint64_t ce_lsi_rcv_phy_stat2; /* 0x00z690 */
uint64_t ce_lsi_rcv_phy_stat3; /* 0x00z698 */
uint64_t ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
uint64_t ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
uint64_t ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
uint64_t ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
uint64_t ce_lsi_tx_phy_cfg; /* 0x00z700 */
uint64_t ce_lsi_tx_phy_stat; /* 0x00z708 */
uint64_t ce_lsi_tx_phy_int_stat; /* 0x00z710 */
uint64_t ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
uint64_t ce_lsi_tx_phy_int_mask; /* 0x00z720 */
uint64_t ce_lsi_tx_phy_stat2; /* 0x00z728 */
uint64_t ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
uint64_t ce_lsi_ltssm_cfg1; /* 0x00z780 */
uint64_t ce_lsi_ltssm_cfg2; /* 0x00z788 */
uint64_t ce_lsi_ltssm_cfg3; /* 0x00z790 */
uint64_t ce_lsi_ltssm_cfg4; /* 0x00z798 */
uint64_t ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
uint64_t ce_lsi_ltssm_stat1; /* 0x00z7A8 */
uint64_t ce_lsi_ltssm_stat2; /* 0x00z7B0 */
uint64_t ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
uint64_t ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
uint64_t ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
uint64_t ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
uint64_t ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
uint64_t ce_lsi_gb_cfg1; /* 0x00z800 */
uint64_t ce_lsi_gb_cfg2; /* 0x00z808 */
uint64_t ce_lsi_gb_cfg3; /* 0x00z810 */
uint64_t ce_lsi_gb_cfg4; /* 0x00z818 */
uint64_t ce_lsi_gb_stat; /* 0x00z820 */
uint64_t ce_lsi_gb_int_stat; /* 0x00z828 */
uint64_t ce_lsi_gb_int_stat_test; /* 0x00z830 */
uint64_t ce_lsi_gb_int_mask; /* 0x00z838 */
uint64_t ce_lsi_gb_pwr_dn1; /* 0x00z840 */
uint64_t ce_lsi_gb_pwr_dn2; /* 0x00z848 */
uint64_t ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
} ce_lsi[2];
uint64_t ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
/*
* CRM: Coretalk Receive Module Registers
*/
uint64_t ce_crm_debug_mux; /* 0x004050 */
uint64_t ce_pad_004058; /* 0x004058 */
uint64_t ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
uint64_t ce_crm_ssp_err_addr; /* 0x004068 */
uint64_t ce_crm_ssp_err_syn; /* 0x004070 */
uint64_t ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
/*
* CXM: Coretalk Xmit Module Registers
*/
uint64_t ce_cxm_dyn_credit_status; /* 0x005010 */
uint64_t ce_cxm_last_credit_status; /* 0x005018 */
uint64_t ce_cxm_credit_limit; /* 0x005020 */
uint64_t ce_cxm_force_credit; /* 0x005028 */
uint64_t ce_cxm_disable_bypass; /* 0x005030 */
uint64_t ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
uint64_t ce_cxm_debug_mux; /* 0x005050 */
uint64_t ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
/*
* DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
* DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
* DTL: the comment offsets at far right: let 'y' = {6 or 8}
*
* UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
* UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
* UTL: the comment offsets at far right: let 'z' = {7 or 9}
*/
#define ce_dtl(link_num) ce_dtl_utl[link_num-1]
#define ce_utl(link_num) ce_dtl_utl[link_num-1]
struct ce_dtl_utl_reg {
/* DTL */
uint64_t ce_dtl_dtdr_credit_limit; /* 0x00y000 */
uint64_t ce_dtl_dtdr_credit_force; /* 0x00y008 */
uint64_t ce_dtl_dyn_credit_status; /* 0x00y010 */
uint64_t ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
uint64_t ce_dtl_dtl_ctrl; /* 0x00y020 */
uint64_t ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
uint64_t ce_dtl_debug_sel; /* 0x00y050 */
uint64_t ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
/* UTL */
uint64_t ce_utl_utl_ctrl; /* 0x00z000 */
uint64_t ce_utl_debug_sel; /* 0x00z008 */
uint64_t ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
} ce_dtl_utl[2];
uint64_t ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
/*
* URE: Upstream Request Engine
*/
uint64_t ce_ure_dyn_credit_status; /* 0x00B010 */
uint64_t ce_ure_last_credit_status; /* 0x00B018 */
uint64_t ce_ure_credit_limit; /* 0x00B020 */
uint64_t ce_pad_00B028; /* 0x00B028 */
uint64_t ce_ure_control; /* 0x00B030 */
uint64_t ce_ure_status; /* 0x00B038 */
uint64_t ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
uint64_t ce_ure_debug_sel; /* 0x00B050 */
uint64_t ce_ure_pcie_debug_sel; /* 0x00B058 */
uint64_t ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
uint64_t ce_ure_ssp_err_addr; /* 0x00B068 */
uint64_t ce_ure_page_map; /* 0x00B070 */
uint64_t ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
uint64_t ce_ure_pipe_sel1; /* 0x00B088 */
uint64_t ce_ure_pipe_mask1; /* 0x00B090 */
uint64_t ce_ure_pipe_sel2; /* 0x00B098 */
uint64_t ce_ure_pipe_mask2; /* 0x00B0A0 */
uint64_t ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
uint64_t ce_ure_pcie1_credits_used; /* 0x00B0B0 */
uint64_t ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
uint64_t ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
uint64_t ce_ure_pcie2_credits_used; /* 0x00B0C8 */
uint64_t ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
uint64_t ce_ure_pcie_force_credit; /* 0x00B0D8 */
uint64_t ce_ure_rd_tnum_val; /* 0x00B0E0 */
uint64_t ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
uint64_t ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
uint64_t ce_ure_rd_tnum_error; /* 0x00B0F8 */
uint64_t ce_ure_rd_tnum_first_cl; /* 0x00B100 */
uint64_t ce_ure_rd_tnum_link_buf; /* 0x00B108 */
uint64_t ce_ure_wr_tnum_val; /* 0x00B110 */
uint64_t ce_ure_sram_err_addr0; /* 0x00B118 */
uint64_t ce_ure_sram_err_addr1; /* 0x00B120 */
uint64_t ce_ure_sram_err_addr2; /* 0x00B128 */
uint64_t ce_ure_sram_rd_addr0; /* 0x00B130 */
uint64_t ce_ure_sram_rd_addr1; /* 0x00B138 */
uint64_t ce_ure_sram_rd_addr2; /* 0x00B140 */
uint64_t ce_ure_sram_wr_addr0; /* 0x00B148 */
uint64_t ce_ure_sram_wr_addr1; /* 0x00B150 */
uint64_t ce_ure_sram_wr_addr2; /* 0x00B158 */
uint64_t ce_ure_buf_flush10; /* 0x00B160 */
uint64_t ce_ure_buf_flush11; /* 0x00B168 */
uint64_t ce_ure_buf_flush12; /* 0x00B170 */
uint64_t ce_ure_buf_flush13; /* 0x00B178 */
uint64_t ce_ure_buf_flush20; /* 0x00B180 */
uint64_t ce_ure_buf_flush21; /* 0x00B188 */
uint64_t ce_ure_buf_flush22; /* 0x00B190 */
uint64_t ce_ure_buf_flush23; /* 0x00B198 */
uint64_t ce_ure_pcie_control1; /* 0x00B1A0 */
uint64_t ce_ure_pcie_control2; /* 0x00B1A8 */
uint64_t ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
/* Upstream Data Buffer, Port1 */
struct ce_ure_maint_ups_dat1_data {
uint64_t data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
uint64_t data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
uint64_t parity[512]; /* 0x00E000 -- 0x00EFF8 */
} ce_ure_maint_ups_dat1;
/* Upstream Header Buffer, Port1 */
struct ce_ure_maint_ups_hdr1_data {
uint64_t data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
uint64_t data127_64[512]; /* 0x010000 -- 0x010FF8 */
uint64_t parity[512]; /* 0x011000 -- 0x011FF8 */
} ce_ure_maint_ups_hdr1;
/* Upstream Data Buffer, Port2 */
struct ce_ure_maint_ups_dat2_data {
uint64_t data63_0[512]; /* 0x012000 -- 0x012FF8 */
uint64_t data127_64[512]; /* 0x013000 -- 0x013FF8 */
uint64_t parity[512]; /* 0x014000 -- 0x014FF8 */
} ce_ure_maint_ups_dat2;
/* Upstream Header Buffer, Port2 */
struct ce_ure_maint_ups_hdr2_data {
uint64_t data63_0[512]; /* 0x015000 -- 0x015FF8 */
uint64_t data127_64[512]; /* 0x016000 -- 0x016FF8 */
uint64_t parity[512]; /* 0x017000 -- 0x017FF8 */
} ce_ure_maint_ups_hdr2;
/* Downstream Data Buffer */
struct ce_ure_maint_dns_dat_data {
uint64_t data63_0[512]; /* 0x018000 -- 0x018FF8 */
uint64_t data127_64[512]; /* 0x019000 -- 0x019FF8 */
uint64_t parity[512]; /* 0x01A000 -- 0x01AFF8 */
} ce_ure_maint_dns_dat;
/* Downstream Header Buffer */
struct ce_ure_maint_dns_hdr_data {
uint64_t data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
uint64_t data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
uint64_t parity[64]; /* 0x01B400 -- 0x01B5F8 */
} ce_ure_maint_dns_hdr;
/* RCI Buffer Data */
struct ce_ure_maint_rci_data {
uint64_t data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
uint64_t data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
} ce_ure_maint_rci;
/* Response Queue */
uint64_t ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
uint64_t ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
/* Admin Build-a-Packet Buffer */
struct ce_adm_maint_bap_buf_data {
uint64_t data63_0[258]; /* 0x024000 -- 0x024808 */
uint64_t data127_64[258]; /* 0x024810 -- 0x025018 */
uint64_t parity[258]; /* 0x025020 -- 0x025828 */
} ce_adm_maint_bap_buf;
uint64_t ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
/* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
uint64_t ce_ure_ate40[TIOCE_NUM_M40_ATES];
/* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
uint64_t ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
uint64_t ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
/*
* DRE: Down Stream Request Engine
*/
uint64_t ce_dre_dyn_credit_status1; /* 0x040010 */
uint64_t ce_dre_dyn_credit_status2; /* 0x040018 */
uint64_t ce_dre_last_credit_status1; /* 0x040020 */
uint64_t ce_dre_last_credit_status2; /* 0x040028 */
uint64_t ce_dre_credit_limit1; /* 0x040030 */
uint64_t ce_dre_credit_limit2; /* 0x040038 */
uint64_t ce_dre_force_credit1; /* 0x040040 */
uint64_t ce_dre_force_credit2; /* 0x040048 */
uint64_t ce_dre_debug_mux1; /* 0x040050 */
uint64_t ce_dre_debug_mux2; /* 0x040058 */
uint64_t ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
uint64_t ce_dre_ssp_err_addr; /* 0x040068 */
uint64_t ce_dre_comp_err_cmd_wrd; /* 0x040070 */
uint64_t ce_dre_comp_err_addr; /* 0x040078 */
uint64_t ce_dre_req_status; /* 0x040080 */
uint64_t ce_dre_config1; /* 0x040088 */
uint64_t ce_dre_config2; /* 0x040090 */
uint64_t ce_dre_config_req_status; /* 0x040098 */
uint64_t ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
uint64_t ce_dre_dyn_fifo; /* 0x040100 */
uint64_t ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
uint64_t ce_dre_last_fifo; /* 0x040120 */
uint64_t ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
/* DRE Downstream Head Queue */
struct ce_dre_maint_ds_head_queue {
uint64_t data63_0[32]; /* 0x040200 -- 0x0402F8 */
uint64_t data127_64[32]; /* 0x040300 -- 0x0403F8 */
uint64_t parity[32]; /* 0x040400 -- 0x0404F8 */
} ce_dre_maint_ds_head_q;
uint64_t ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
/* DRE Downstream Data Queue */
struct ce_dre_maint_ds_data_queue {
uint64_t data63_0[256]; /* 0x041000 -- 0x0417F8 */
uint64_t ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
uint64_t data127_64[256]; /* 0x042000 -- 0x0427F8 */
uint64_t ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
uint64_t parity[256]; /* 0x043000 -- 0x0437F8 */
uint64_t ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
} ce_dre_maint_ds_data_q;
/* DRE URE Upstream Response Queue */
struct ce_dre_maint_ure_us_rsp_queue {
uint64_t data63_0[8]; /* 0x044000 -- 0x044038 */
uint64_t ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
uint64_t data127_64[8]; /* 0x044100 -- 0x044138 */
uint64_t ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
uint64_t parity[8]; /* 0x044200 -- 0x044238 */
uint64_t ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
} ce_dre_maint_ure_us_rsp_q;
uint64_t ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
uint64_t ce_end_of_struct; /* 0x044400 */
} tioce_t;
/* ce_adm_int_mask/ce_adm_int_status register bit defines */
#define CE_ADM_INT_CE_ERROR_SHFT 0
#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
#define CE_ADM_INT_PCIE_ERROR_SHFT 3
#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
/* ce_adm_force_int register bit defines */
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
/* ce_adm_int_dest register bit masks & shifts */
#define INTR_VECTOR_SHFT 56
/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
/* ce_dre_config1 register bit masks and shifts */
#define CE_DRE_RO_ENABLE (0x1ULL << 0)
#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
#define CE_DRE_ADDR_MODE_SHFT 4
/* ce_dre_config_req_status register bit masks */
#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
/* ce_ure_control register bit masks & shifts */
#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
/* ce_ure_page_map register bit masks & shifts */
#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
#define CE_URE_PAGESIZE_SHFT 4
#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
/* ce_ure_pipe_sel register bit masks & shifts */
#define PKT_TRAFIC_SHRT 16
#define BUS_SRC_ID_SHFT 8
#define DEV_SRC_ID_SHFT 3
#define FNC_SRC_ID_SHFT 0
#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
#define CE_URE_PIPE_BUS(b) (((uint64_t)(b) << BUS_SRC_ID_SHFT) & \
CE_URE_BUS_MASK)
#define CE_URE_PIPE_DEV(d) (((uint64_t)(d) << DEV_SRC_ID_SHFT) & \
CE_URE_DEV_MASK)
#define CE_URE_PIPE_FNC(f) (((uint64_t)(f) << FNC_SRC_ID_SHFT) & \
CE_URE_FNC_MASK)
#define CE_URE_SEL1_SHFT 0
#define CE_URE_SEL2_SHFT 20
#define CE_URE_SEL3_SHFT 40
#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
/* ce_ure_pipe_mask register bit masks & shifts */
#define CE_URE_MASK1_SHFT 0
#define CE_URE_MASK2_SHFT 20
#define CE_URE_MASK3_SHFT 40
#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
/* ce_ure_pcie_control1 register bit masks & shifts */
#define CE_URE_SI (0x1ULL << 0)
#define CE_URE_ELAL_SHFT 4
#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
#define CE_URE_ELAL1_SHFT 8
#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
#define CE_URE_SCC (0x1ULL << 12)
#define CE_URE_PN1_SHFT 16
#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
#define CE_URE_PN2_SHFT 24
#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
#define CE_URE_PN1_SET(n) (((uint64_t)(n) << CE_URE_PN1_SHFT) & \
CE_URE_PN1_MASK)
#define CE_URE_PN2_SET(n) (((uint64_t)(n) << CE_URE_PN2_SHFT) & \
CE_URE_PN2_MASK)
/* ce_ure_pcie_control2 register bit masks & shifts */
#define CE_URE_ABP (0x1ULL << 0)
#define CE_URE_PCP (0x1ULL << 1)
#define CE_URE_MSP (0x1ULL << 2)
#define CE_URE_AIP (0x1ULL << 3)
#define CE_URE_PIP (0x1ULL << 4)
#define CE_URE_HPS (0x1ULL << 5)
#define CE_URE_HPC (0x1ULL << 6)
#define CE_URE_SPLV_SHFT 7
#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
#define CE_URE_SPLS_SHFT 15
#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
#define CE_URE_PSN1_SHFT 19
#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
#define CE_URE_PSN2_SHFT 32
#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
#define CE_URE_PSN1_SET(n) (((uint64_t)(n) << CE_URE_PSN1_SHFT) & \
CE_URE_PSN1_MASK)
#define CE_URE_PSN2_SET(n) (((uint64_t)(n) << CE_URE_PSN2_SHFT) & \
CE_URE_PSN2_MASK)
/*
* PIO address space ranges for CE
*/
/* Local CE Registers Space */
#define CE_PIO_MMR 0x00000000
#define CE_PIO_MMR_LEN 0x04000000
/* PCI Compatible Config Space */
#define CE_PIO_CONFIG_SPACE 0x04000000
#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
/* PCI I/O Space Alias */
#define CE_PIO_IO_SPACE_ALIAS 0x08000000
#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
/* PCI Enhanced Config Space */
#define CE_PIO_E_CONFIG_SPACE 0x10000000
#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
/* PCI I/O Space */
#define CE_PIO_IO_SPACE 0x100000000
#define CE_PIO_IO_SPACE_LEN 0x100000000
/* PCI MEM Space */
#define CE_PIO_MEM_SPACE 0x200000000
#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
/*
* CE PCI Enhanced Config Space shifts & masks
*/
#define CE_E_CONFIG_BUS_SHFT 20
#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
#define CE_E_CONFIG_DEVICE_SHFT 15
#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
#define CE_E_CONFIG_FUNC_SHFT 12
#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
#endif /* __ASM_IA64_SN_TIOCE_H__ */
include/asm-ia64/sn/tioce_provider.h
+66
View File
@@ -0,0 +1,66 @@
/**************************************************************************
* Copyright (C) 2005, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
**************************************************************************/
#ifndef _ASM_IA64_SN_CE_PROVIDER_H
#define _ASM_IA64_SN_CE_PROVIDER_H
#include <asm/sn/pcibus_provider_defs.h>
#include <asm/sn/tioce.h>
/*
* Common TIOCE structure shared between the prom and kernel
*
* DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
* PROM VERSION.
*/
struct tioce_common {
struct pcibus_bussoft ce_pcibus; /* common pciio header */
uint32_t ce_rev;
uint64_t ce_kernel_private;
uint64_t ce_prom_private;
};
struct tioce_kernel {
struct tioce_common *ce_common;
spinlock_t ce_lock;
struct list_head ce_dmamap_list;
uint64_t ce_ate40_shadow[TIOCE_NUM_M40_ATES];
uint64_t ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
uint32_t ce_ate3240_pagesize;
uint8_t ce_port1_secondary;
/* per-port resources */
struct {
int dirmap_refcnt;
uint64_t dirmap_shadow;
} ce_port[TIOCE_NUM_PORTS];
};
struct tioce_dmamap {
struct list_head ce_dmamap_list; /* headed by tioce_kernel */
uint32_t refcnt;
uint64_t nbytes; /* # bytes mapped */
uint64_t ct_start; /* coretalk start address */
uint64_t pci_start; /* bus start address */
uint64_t *ate_hw; /* hw ptr of first ate in map */
uint64_t *ate_shadow; /* shadow ptr of firat ate */
uint16_t ate_count; /* # ate's in the map */
};
extern int tioce_init_provider(void);
#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
include/asm-ia64/spinlock.h
+24 -9
View File
@@ -93,7 +93,15 @@ _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
# endif /* CONFIG_MCKINLEY */
#endif
}
#define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
/* Unlock by doing an ordered store and releasing the cacheline with nta */
static inline void _raw_spin_unlock(spinlock_t *x) {
barrier();
asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
}
#else /* !ASM_SUPPORTED */
#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
# define _raw_spin_lock(x) \
@@ -109,16 +117,16 @@ do { \
} while (ia64_spinlock_val); \
} \
} while (0)
#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
#endif /* !ASM_SUPPORTED */
#define spin_is_locked(x) ((x)->lock != 0)
#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
#define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
#define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
typedef struct {
volatile unsigned int read_counter : 31;
volatile unsigned int write_lock : 1;
volatile unsigned int read_counter : 24;
volatile unsigned int write_lock : 8;
#ifdef CONFIG_PREEMPT
unsigned int break_lock;
#endif
@@ -174,6 +182,13 @@ do { \
(result == 0); \
})
static inline void _raw_write_unlock(rwlock_t *x)
{
u8 *y = (u8 *)x;
barrier();
asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
}
#else /* !ASM_SUPPORTED */
#define _raw_write_lock(l) \
@@ -195,14 +210,14 @@ do { \
(ia64_val == 0); \
})
static inline void _raw_write_unlock(rwlock_t *x)
{
barrier();
x->write_lock = 0;
}
#endif /* !ASM_SUPPORTED */
#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
#define _raw_write_unlock(x) \
({ \
smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \
clear_bit(31, (x)); \
})
#endif /* _ASM_IA64_SPINLOCK_H */
include/asm-ia64/system.h
+3 -2
View File
@@ -19,12 +19,13 @@
#include <asm/pal.h>
#include <asm/percpu.h>
#define GATE_ADDR __IA64_UL_CONST(0xa000000000000000)
#define GATE_ADDR RGN_BASE(RGN_GATE)
/*
* 0xa000000000000000+2*PERCPU_PAGE_SIZE
* - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
*/
#define KERNEL_START __IA64_UL_CONST(0xa000000100000000)
#define KERNEL_START (GATE_ADDR+0x100000000)
#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
#ifndef __ASSEMBLY__