From 6237faf30d7deca70119cdfa1d2f8dc018dc2c59 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Sun, 12 Nov 2017 18:47:53 +0530 Subject: [PATCH] PCI: tegra: Fixups to avoid unnecessary wakeup from ASPM-L1.2 sets CLKREQ asserted delay to a higher value to avoid unnecessary wake up from L1.2.ENTRY state for Tegra210 bug 200420606 Change-Id: Iec2564bfd434897f0e50cd3f0ad6bc76aacc12e8 Signed-off-by: Vidya Sagar Reviewed-on: https://git-master.nvidia.com/r/1786545 (cherry picked from commit d7785c1e6c98e33a85ba9487d3be6ab7e518a285) Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407875 Reviewed-by: automaticguardword Reviewed-by: Manikanta Maddireddy Reviewed-by: Bitan Biswas Reviewed-by: mobile promotions Tested-by: Manikanta Maddireddy Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/pci/controller/pci-tegra.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index 4673603ffce1..7aaa8755b21c 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -185,6 +185,8 @@ #define RP_L1_PM_SUBSTATES_1_CTL 0xc04 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK 0x1fff #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY 0x26 +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK (0x1ff << 13) +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY (0x27 << 13) #define RP_L1_PM_SUBSTATES_2_CTL 0xc08 #define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK 0x1fff @@ -379,6 +381,7 @@ struct tegra_pcie_soc { bool enable_wrap; bool has_aspm_l1; bool has_aspm_l1ss; + bool l1ss_rp_wake_fixup; struct { struct { u32 rp_ectl_1_r1; @@ -871,6 +874,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP; writel(value, port->base + RP_L1_PM_SUBSTATES_2_CTL); } + + if (soc->l1ss_rp_wake_fixup) { + /* + * Set CLKREQ asserted delay greater than Power_Off + * time (2us) to avoid RP wakeup in L1.2.ENTRY + */ + value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); + value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK; + value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY; + writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL); + } } static void tegra_pcie_port_enable(struct tegra_pcie_port *port) @@ -2583,6 +2597,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .enable_wrap = false, .has_aspm_l1 = false, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, .ectl.enable = false, }; @@ -2615,6 +2630,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .enable_wrap = false, .has_aspm_l1 = true, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, .ectl.enable = false, }; @@ -2639,6 +2655,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .enable_wrap = false, .has_aspm_l1 = true, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, .ectl.enable = false, }; @@ -2665,6 +2682,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .enable_wrap = true, .has_aspm_l1 = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = true, .ectl = { .regs = { .rp_ectl_1_r1 = 0x0000001f, @@ -2747,6 +2765,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .enable_wrap = false, .has_aspm_l1 = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = false, .ectl.enable = false, };