Merge 6.12.33 into android16-6.12-lts
GKI (arm64) relevant 8 out of 25 changes, affecting 9 files +103/-61db758487f3tracing: Fix compilation warning on arm32 [1 file, +1/-1]bf49527089f2fs: fix to avoid accessing uninitialized curseg [2 files, +15/-1]a6a55fe660rtc: Make rtc_time64_to_tm() support dates before 1970 [1 file, +19/-5]6b482b16f3rtc: Fix offset calculation for .start_secs < 0 [1 file, +1/-1]3c4fed940dPCI/ASPM: Disable L1 before disabling L1 PM Substates [1 file, +50/-42]0c60158ff1block: fix adding folio to bio [1 file, +7/-4]23179d009cusb: quirks: Add NO_LPM quirk for SanDisk Extreme 55AE [1 file, +3/-0]e428b7e205Bluetooth: hci_qca: move the SoC type check to the right place [1 file, +7/-7] Changes in 6.12.33 tracing: Fix compilation warning on arm32 f2fs: fix to avoid accessing uninitialized curseg pinctrl: armada-37xx: use correct OUTPUT_VAL register for GPIOs > 31 pinctrl: armada-37xx: set GPIO output value before setting direction acpi-cpufreq: Fix nominal_freq units to KHz in get_max_boost_ratio() Documentation: ACPI: Use all-string data node references rtc: Make rtc_time64_to_tm() support dates before 1970 rtc: Fix offset calculation for .start_secs < 0 accel/ivpu: Add initial Panther Lake support accel/ivpu: Update power island delays PCI/ASPM: Disable L1 before disabling L1 PM Substates block: fix adding folio to bio Revert "cpufreq: tegra186: Share policy per cluster" usb: quirks: Add NO_LPM quirk for SanDisk Extreme 55AE usb: storage: Ignore UAS driver for SanDisk 3.2 Gen2 storage device USB: serial: pl2303: add new chip PL2303GC-Q20 and PL2303GT-2AB usb: typec: ucsi: fix Clang -Wsign-conversion warning Bluetooth: hci_qca: move the SoC type check to the right place serial: jsm: fix NPE during jsm_uart_port_init usb: usbtmc: Fix timeout value in get_stb thunderbolt: Do not double dequeue a configuration request dt-bindings: usb: cypress,hx3: Add support for all variants dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt property Revert "drm/amd/display: more liberal vmin/vmax update for freesync" Linux 6.12.33 Change-Id: I7c7a2ac6d4c5733af81a449f838133d9da60cafe Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
@@ -58,8 +58,7 @@ properties:
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fsl,phy-tx-vboost-level-microvolt:
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description:
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Adjust the boosted transmit launch pk-pk differential amplitude
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minimum: 880
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maximum: 1120
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enum: [844, 1008, 1156]
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fsl,phy-comp-dis-tune-percent:
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description:
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@@ -14,9 +14,22 @@ allOf:
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properties:
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compatible:
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enum:
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- usb4b4,6504
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- usb4b4,6506
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oneOf:
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- enum:
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- usb4b4,6504
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- usb4b4,6506
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- items:
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- enum:
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- usb4b4,6500
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- usb4b4,6508
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- const: usb4b4,6504
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- items:
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- enum:
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- usb4b4,6502
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- usb4b4,6503
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- usb4b4,6507
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- usb4b4,650a
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- const: usb4b4,6506
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reg: true
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@@ -12,11 +12,14 @@ ACPI in general allows referring to device objects in the tree only.
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Hierarchical data extension nodes may not be referred to directly, hence this
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document defines a scheme to implement such references.
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A reference consist of the device object name followed by one or more
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hierarchical data extension [dsd-guide] keys. Specifically, the hierarchical
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data extension node which is referred to by the key shall lie directly under
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the parent object i.e. either the device object or another hierarchical data
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extension node.
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A reference to a _DSD hierarchical data node is a string consisting of a
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device object reference followed by a dot (".") and a relative path to a data
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node object. Do not use non-string references as this will produce a copy of
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the hierarchical data node, not a reference!
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The hierarchical data extension node which is referred to shall be located
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directly under its parent object i.e. either the device object or another
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hierarchical data extension node [dsd-guide].
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The keys in the hierarchical data nodes shall consist of the name of the node,
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"@" character and the number of the node in hexadecimal notation (without pre-
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@@ -33,11 +36,9 @@ extension key.
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Example
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=======
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In the ASL snippet below, the "reference" _DSD property contains a
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device object reference to DEV0 and under that device object, a
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hierarchical data extension key "node@1" referring to the NOD1 object
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and lastly, a hierarchical data extension key "anothernode" referring to
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the ANOD object which is also the final target node of the reference.
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In the ASL snippet below, the "reference" _DSD property contains a string
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reference to a hierarchical data extension node ANOD under DEV0 under the parent
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of DEV1. ANOD is also the final target node of the reference.
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::
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Device (DEV0)
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@@ -76,10 +77,7 @@ the ANOD object which is also the final target node of the reference.
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () {
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"reference", Package () {
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^DEV0, "node@1", "anothernode"
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}
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Package () { "reference", "^DEV0.ANOD" }
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},
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}
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})
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@@ -66,12 +66,9 @@ of that port shall be zero. Similarly, if a port may only have a single
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endpoint, the number of that endpoint shall be zero.
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The endpoint reference uses property extension with "remote-endpoint" property
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name followed by a reference in the same package. Such references consist of
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the remote device reference, the first package entry of the port data extension
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reference under the device and finally the first package entry of the endpoint
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data extension reference under the port. Individual references thus appear as::
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name followed by a string reference in the same package. [data-node-ref]::
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Package() { device, "port@X", "endpoint@Y" }
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"device.datanode"
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In the above example, "X" is the number of the port and "Y" is the number of
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the endpoint.
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@@ -109,7 +106,7 @@ A simple example of this is show below::
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "reg", 0 },
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Package () { "remote-endpoint", Package() { \_SB.PCI0.ISP, "port@4", "endpoint@0" } },
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Package () { "remote-endpoint", "\\_SB.PCI0.ISP.EP40" },
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}
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})
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}
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@@ -141,7 +138,7 @@ A simple example of this is show below::
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () { "reg", 0 },
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Package () { "remote-endpoint", Package () { \_SB.PCI0.I2C2.CAM0, "port@0", "endpoint@0" } },
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Package () { "remote-endpoint", "\\_SB.PCI0.I2C2.CAM0.EP00" },
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}
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})
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}
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@@ -15,11 +15,6 @@ Referring to LEDs in Device tree is documented in [video-interfaces], in
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"flash-leds" property documentation. In short, LEDs are directly referred to by
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using phandles.
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While Device tree allows referring to any node in the tree [devicetree], in
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ACPI references are limited to device nodes only [acpi]. For this reason using
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the same mechanism on ACPI is not possible. A mechanism to refer to non-device
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ACPI nodes is documented in [data-node-ref].
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ACPI allows (as does DT) using integer arguments after the reference. A
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combination of the LED driver device reference and an integer argument,
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referring to the "reg" property of the relevant LED, is used to identify
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@@ -74,7 +69,7 @@ omitted. ::
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Package () {
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Package () {
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"flash-leds",
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Package () { ^LED, "led@0", ^LED, "led@1" },
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Package () { "^LED.LED0", "^LED.LED1" },
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}
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}
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})
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2
Makefile
2
Makefile
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 6
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PATCHLEVEL = 12
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SUBLEVEL = 32
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SUBLEVEL = 33
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EXTRAVERSION =
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NAME = Baby Opossum Posse
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11
block/bio.c
11
block/bio.c
@@ -1029,9 +1029,10 @@ EXPORT_SYMBOL(bio_add_page);
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void bio_add_folio_nofail(struct bio *bio, struct folio *folio, size_t len,
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size_t off)
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{
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unsigned long nr = off / PAGE_SIZE;
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WARN_ON_ONCE(len > UINT_MAX);
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WARN_ON_ONCE(off > UINT_MAX);
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__bio_add_page(bio, &folio->page, len, off);
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__bio_add_page(bio, folio_page(folio, nr), len, off % PAGE_SIZE);
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}
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EXPORT_SYMBOL_GPL(bio_add_folio_nofail);
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@@ -1052,9 +1053,11 @@ EXPORT_SYMBOL_GPL(bio_add_folio_nofail);
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bool bio_add_folio(struct bio *bio, struct folio *folio, size_t len,
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size_t off)
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{
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if (len > UINT_MAX || off > UINT_MAX)
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unsigned long nr = off / PAGE_SIZE;
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if (len > UINT_MAX)
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return false;
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return bio_add_page(bio, &folio->page, len, off) > 0;
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return bio_add_page(bio, folio_page(folio, nr), len, off % PAGE_SIZE) > 0;
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}
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EXPORT_SYMBOL(bio_add_folio);
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@@ -709,6 +709,7 @@ static struct pci_device_id ivpu_pci_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, ivpu_pci_ids);
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@@ -23,9 +23,10 @@
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#define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
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#define DRIVER_DATE "20230117"
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#define PCI_DEVICE_ID_MTL 0x7d1d
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#define PCI_DEVICE_ID_ARL 0xad1d
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#define PCI_DEVICE_ID_LNL 0x643e
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#define PCI_DEVICE_ID_MTL 0x7d1d
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#define PCI_DEVICE_ID_ARL 0xad1d
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#define PCI_DEVICE_ID_LNL 0x643e
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#define PCI_DEVICE_ID_PTL_P 0xb03e
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#define IVPU_HW_IP_37XX 37
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#define IVPU_HW_IP_40XX 40
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@@ -227,6 +228,8 @@ static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
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return IVPU_HW_IP_37XX;
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case PCI_DEVICE_ID_LNL:
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return IVPU_HW_IP_40XX;
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case PCI_DEVICE_ID_PTL_P:
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return IVPU_HW_IP_50XX;
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default:
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dump_stack();
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ivpu_err(vdev, "Unknown NPU IP generation\n");
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@@ -241,6 +244,7 @@ static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
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case PCI_DEVICE_ID_ARL:
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return IVPU_HW_BTRS_MTL;
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case PCI_DEVICE_ID_LNL:
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case PCI_DEVICE_ID_PTL_P:
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return IVPU_HW_BTRS_LNL;
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default:
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dump_stack();
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@@ -57,11 +57,14 @@ static struct {
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{ IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" },
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{ IVPU_HW_IP_40XX, "vpu_40xx.bin" },
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{ IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" },
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{ IVPU_HW_IP_50XX, "vpu_50xx.bin" },
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{ IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" },
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};
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/* Production fw_names from the table above */
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MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin");
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MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin");
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MODULE_FIRMWARE("intel/vpu/vpu_50xx_v0.0.bin");
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static int ivpu_fw_request(struct ivpu_device *vdev)
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{
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@@ -115,6 +115,8 @@
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#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u
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#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0)
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#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK GENMASK(15, 8)
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#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK GENMASK(23, 16)
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#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu
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#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0)
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@@ -8,15 +8,12 @@
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#include "ivpu_hw.h"
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#include "ivpu_hw_37xx_reg.h"
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#include "ivpu_hw_40xx_reg.h"
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#include "ivpu_hw_btrs.h"
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#include "ivpu_hw_ip.h"
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#include "ivpu_hw_reg_io.h"
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#include "ivpu_mmu.h"
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#include "ivpu_pm.h"
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#define PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT 0
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#define PWR_ISLAND_EN_POST_DLY_FREQ_HIGH 18
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#define PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT 3
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#define PWR_ISLAND_STATUS_DLY_FREQ_HIGH 46
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#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
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#define TIM_SAFE_ENABLE 0xf1d0dead
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@@ -268,20 +265,15 @@ void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev)
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idle_gen_drive_40xx(vdev, false);
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}
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static void pwr_island_delay_set_50xx(struct ivpu_device *vdev)
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static void
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pwr_island_delay_set_50xx(struct ivpu_device *vdev, u32 post, u32 post1, u32 post2, u32 status)
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{
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u32 val, post, status;
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if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_DEFAULT) {
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post = PWR_ISLAND_EN_POST_DLY_FREQ_DEFAULT;
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status = PWR_ISLAND_STATUS_DLY_FREQ_DEFAULT;
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} else {
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post = PWR_ISLAND_EN_POST_DLY_FREQ_HIGH;
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status = PWR_ISLAND_STATUS_DLY_FREQ_HIGH;
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}
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u32 val;
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val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY);
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val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val);
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val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val);
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val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val);
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REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val);
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|
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val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY);
|
||||
@@ -686,13 +678,36 @@ static void dpu_active_drive_37xx(struct ivpu_device *vdev, bool enable)
|
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REGV_WR32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE, val);
|
||||
}
|
||||
|
||||
static void pwr_island_delay_set(struct ivpu_device *vdev)
|
||||
{
|
||||
bool high = vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH;
|
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u32 post, post1, post2, status;
|
||||
|
||||
if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX)
|
||||
return;
|
||||
|
||||
switch (ivpu_device_id(vdev)) {
|
||||
case PCI_DEVICE_ID_PTL_P:
|
||||
post = high ? 18 : 0;
|
||||
post1 = 0;
|
||||
post2 = 0;
|
||||
status = high ? 46 : 3;
|
||||
break;
|
||||
|
||||
default:
|
||||
dump_stack();
|
||||
ivpu_err(vdev, "Unknown device ID\n");
|
||||
return;
|
||||
}
|
||||
|
||||
pwr_island_delay_set_50xx(vdev, post, post1, post2, status);
|
||||
}
|
||||
|
||||
int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_50XX)
|
||||
pwr_island_delay_set_50xx(vdev);
|
||||
|
||||
pwr_island_delay_set(vdev);
|
||||
pwr_island_enable(vdev);
|
||||
|
||||
ret = wait_for_pwr_island_status(vdev, 0x1);
|
||||
|
||||
@@ -2385,14 +2385,14 @@ static int qca_serdev_probe(struct serdev_device *serdev)
|
||||
|
||||
qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
|
||||
GPIOD_OUT_LOW);
|
||||
if (IS_ERR(qcadev->bt_en) &&
|
||||
(data->soc_type == QCA_WCN6750 ||
|
||||
data->soc_type == QCA_WCN6855)) {
|
||||
dev_err(&serdev->dev, "failed to acquire BT_EN gpio\n");
|
||||
return PTR_ERR(qcadev->bt_en);
|
||||
}
|
||||
if (IS_ERR(qcadev->bt_en))
|
||||
return dev_err_probe(&serdev->dev,
|
||||
PTR_ERR(qcadev->bt_en),
|
||||
"failed to acquire BT_EN gpio\n");
|
||||
|
||||
if (!qcadev->bt_en)
|
||||
if (!qcadev->bt_en &&
|
||||
(data->soc_type == QCA_WCN6750 ||
|
||||
data->soc_type == QCA_WCN6855))
|
||||
power_ctrl_enabled = false;
|
||||
|
||||
qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl",
|
||||
|
||||
@@ -663,7 +663,7 @@ static u64 get_max_boost_ratio(unsigned int cpu, u64 *nominal_freq)
|
||||
nominal_perf = perf_caps.nominal_perf;
|
||||
|
||||
if (nominal_freq)
|
||||
*nominal_freq = perf_caps.nominal_freq;
|
||||
*nominal_freq = perf_caps.nominal_freq * 1000;
|
||||
|
||||
if (!highest_perf || !nominal_perf) {
|
||||
pr_debug("CPU%d: highest or nominal performance missing\n", cpu);
|
||||
|
||||
@@ -73,18 +73,11 @@ static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
|
||||
unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id;
|
||||
u32 cpu;
|
||||
|
||||
policy->freq_table = data->clusters[cluster].table;
|
||||
policy->cpuinfo.transition_latency = 300 * 1000;
|
||||
policy->driver_data = NULL;
|
||||
|
||||
/* set same policy for all cpus in a cluster */
|
||||
for (cpu = 0; cpu < ARRAY_SIZE(tegra186_cpus); cpu++) {
|
||||
if (data->cpus[cpu].bpmp_cluster_id == cluster)
|
||||
cpumask_set_cpu(cpu, policy->cpus);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -668,21 +668,15 @@ static void dm_crtc_high_irq(void *interrupt_params)
|
||||
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
|
||||
|
||||
if (acrtc->dm_irq_params.stream &&
|
||||
acrtc->dm_irq_params.vrr_params.supported) {
|
||||
bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled;
|
||||
bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled;
|
||||
bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state == VRR_STATE_ACTIVE_VARIABLE;
|
||||
|
||||
acrtc->dm_irq_params.vrr_params.supported &&
|
||||
acrtc->dm_irq_params.freesync_config.state ==
|
||||
VRR_STATE_ACTIVE_VARIABLE) {
|
||||
mod_freesync_handle_v_update(adev->dm.freesync_module,
|
||||
acrtc->dm_irq_params.stream,
|
||||
&acrtc->dm_irq_params.vrr_params);
|
||||
|
||||
/* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */
|
||||
if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) {
|
||||
dc_stream_adjust_vmin_vmax(adev->dm.dc,
|
||||
acrtc->dm_irq_params.stream,
|
||||
&acrtc->dm_irq_params.vrr_params.adjust);
|
||||
}
|
||||
dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
|
||||
&acrtc->dm_irq_params.vrr_params.adjust);
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -805,6 +805,15 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
|
||||
pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
|
||||
pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
|
||||
|
||||
/* Disable L0s/L1 before updating L1SS config */
|
||||
if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
|
||||
FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
|
||||
pcie_capability_write_word(child, PCI_EXP_LNKCTL,
|
||||
child_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
|
||||
pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
|
||||
parent_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup L0s state
|
||||
*
|
||||
@@ -829,6 +838,13 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
|
||||
|
||||
aspm_l1ss_init(link);
|
||||
|
||||
/* Restore L0s/L1 if they were enabled */
|
||||
if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
|
||||
FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
|
||||
pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_lnkctl);
|
||||
pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_lnkctl);
|
||||
}
|
||||
|
||||
/* Save default state */
|
||||
link->aspm_default = link->aspm_enabled;
|
||||
|
||||
@@ -845,43 +861,12 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure the ASPM L1 substates */
|
||||
/* Configure the ASPM L1 substates. Caller must disable L1 first. */
|
||||
static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
|
||||
{
|
||||
u32 val, enable_req;
|
||||
u32 val;
|
||||
struct pci_dev *child = link->downstream, *parent = link->pdev;
|
||||
|
||||
enable_req = (link->aspm_enabled ^ state) & state;
|
||||
|
||||
/*
|
||||
* Here are the rules specified in the PCIe spec for enabling L1SS:
|
||||
* - When enabling L1.x, enable bit at parent first, then at child
|
||||
* - When disabling L1.x, disable bit at child first, then at parent
|
||||
* - When enabling ASPM L1.x, need to disable L1
|
||||
* (at child followed by parent).
|
||||
* - The ASPM/PCIPM L1.2 must be disabled while programming timing
|
||||
* parameters
|
||||
*
|
||||
* To keep it simple, disable all L1SS bits first, and later enable
|
||||
* what is needed.
|
||||
*/
|
||||
|
||||
/* Disable all L1 substates */
|
||||
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
|
||||
PCI_L1SS_CTL1_L1SS_MASK, 0);
|
||||
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
|
||||
PCI_L1SS_CTL1_L1SS_MASK, 0);
|
||||
/*
|
||||
* If needed, disable L1, and it gets enabled later
|
||||
* in pcie_config_aspm_link().
|
||||
*/
|
||||
if (enable_req & (PCIE_LINK_STATE_L1_1 | PCIE_LINK_STATE_L1_2)) {
|
||||
pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_ASPM_L1);
|
||||
pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_ASPM_L1);
|
||||
}
|
||||
|
||||
val = 0;
|
||||
if (state & PCIE_LINK_STATE_L1_1)
|
||||
val |= PCI_L1SS_CTL1_ASPM_L1_1;
|
||||
@@ -892,6 +877,20 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
|
||||
if (state & PCIE_LINK_STATE_L1_2_PCIPM)
|
||||
val |= PCI_L1SS_CTL1_PCIPM_L1_2;
|
||||
|
||||
/*
|
||||
* PCIe r6.2, sec 5.5.4, rules for enabling L1 PM Substates:
|
||||
* - Clear L1.x enable bits at child first, then at parent
|
||||
* - Set L1.x enable bits at parent first, then at child
|
||||
* - ASPM/PCIPM L1.2 must be disabled while programming timing
|
||||
* parameters
|
||||
*/
|
||||
|
||||
/* Disable all L1 substates */
|
||||
pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
|
||||
PCI_L1SS_CTL1_L1SS_MASK, 0);
|
||||
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
|
||||
PCI_L1SS_CTL1_L1SS_MASK, 0);
|
||||
|
||||
/* Enable what we need to enable */
|
||||
pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
|
||||
PCI_L1SS_CTL1_L1SS_MASK, val);
|
||||
@@ -937,21 +936,30 @@ static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
|
||||
dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Per PCIe r6.2, sec 5.5.4, setting either or both of the enable
|
||||
* bits for ASPM L1 PM Substates must be done while ASPM L1 is
|
||||
* disabled. Disable L1 here and apply new configuration after L1SS
|
||||
* configuration has been completed.
|
||||
*
|
||||
* Per sec 7.5.3.7, when disabling ASPM L1, software must disable
|
||||
* it in the Downstream component prior to disabling it in the
|
||||
* Upstream component, and ASPM L1 must be enabled in the Upstream
|
||||
* component prior to enabling it in the Downstream component.
|
||||
*
|
||||
* Sec 7.5.3.7 also recommends programming the same ASPM Control
|
||||
* value for all functions of a multi-function device.
|
||||
*/
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list)
|
||||
pcie_config_aspm_dev(child, 0);
|
||||
pcie_config_aspm_dev(parent, 0);
|
||||
|
||||
if (link->aspm_capable & PCIE_LINK_STATE_L1SS)
|
||||
pcie_config_aspm_l1ss(link, state);
|
||||
|
||||
/*
|
||||
* Spec 2.0 suggests all functions should be configured the
|
||||
* same setting for ASPM. Enabling ASPM L1 should be done in
|
||||
* upstream component first and then downstream, and vice
|
||||
* versa for disabling ASPM L1. Spec doesn't mention L0S.
|
||||
*/
|
||||
if (state & PCIE_LINK_STATE_L1)
|
||||
pcie_config_aspm_dev(parent, upstream);
|
||||
pcie_config_aspm_dev(parent, upstream);
|
||||
list_for_each_entry(child, &linkbus->devices, bus_list)
|
||||
pcie_config_aspm_dev(child, dwstream);
|
||||
if (!(state & PCIE_LINK_STATE_L1))
|
||||
pcie_config_aspm_dev(parent, upstream);
|
||||
|
||||
link->aspm_enabled = state;
|
||||
|
||||
|
||||
@@ -417,20 +417,22 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int reg = OUTPUT_EN;
|
||||
unsigned int en_offset = offset;
|
||||
unsigned int reg = OUTPUT_VAL;
|
||||
unsigned int mask, val, ret;
|
||||
|
||||
armada_37xx_update_reg(®, &offset);
|
||||
mask = BIT(offset);
|
||||
val = value ? mask : 0;
|
||||
|
||||
ret = regmap_update_bits(info->regmap, reg, mask, mask);
|
||||
|
||||
ret = regmap_update_bits(info->regmap, reg, mask, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg = OUTPUT_VAL;
|
||||
val = value ? mask : 0;
|
||||
regmap_update_bits(info->regmap, reg, mask, val);
|
||||
reg = OUTPUT_EN;
|
||||
armada_37xx_update_reg(®, &en_offset);
|
||||
|
||||
regmap_update_bits(info->regmap, reg, mask, mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -327,7 +327,7 @@ static void rtc_device_get_offset(struct rtc_device *rtc)
|
||||
*
|
||||
* Otherwise the offset seconds should be 0.
|
||||
*/
|
||||
if (rtc->start_secs > rtc->range_max ||
|
||||
if ((rtc->start_secs >= 0 && rtc->start_secs > rtc->range_max) ||
|
||||
rtc->start_secs + range_secs - 1 < rtc->range_min)
|
||||
rtc->offset_secs = rtc->start_secs - rtc->range_min;
|
||||
else if (rtc->start_secs > rtc->range_min)
|
||||
|
||||
@@ -46,24 +46,38 @@ EXPORT_SYMBOL(rtc_year_days);
|
||||
* rtc_time64_to_tm - converts time64_t to rtc_time.
|
||||
*
|
||||
* @time: The number of seconds since 01-01-1970 00:00:00.
|
||||
* (Must be positive.)
|
||||
* Works for values since at least 1900
|
||||
* @tm: Pointer to the struct rtc_time.
|
||||
*/
|
||||
void rtc_time64_to_tm(time64_t time, struct rtc_time *tm)
|
||||
{
|
||||
unsigned int secs;
|
||||
int days;
|
||||
int days, secs;
|
||||
|
||||
u64 u64tmp;
|
||||
u32 u32tmp, udays, century, day_of_century, year_of_century, year,
|
||||
day_of_year, month, day;
|
||||
bool is_Jan_or_Feb, is_leap_year;
|
||||
|
||||
/* time must be positive */
|
||||
/*
|
||||
* Get days and seconds while preserving the sign to
|
||||
* handle negative time values (dates before 1970-01-01)
|
||||
*/
|
||||
days = div_s64_rem(time, 86400, &secs);
|
||||
|
||||
/*
|
||||
* We need 0 <= secs < 86400 which isn't given for negative
|
||||
* values of time. Fixup accordingly.
|
||||
*/
|
||||
if (secs < 0) {
|
||||
days -= 1;
|
||||
secs += 86400;
|
||||
}
|
||||
|
||||
/* day of the week, 1970-01-01 was a Thursday */
|
||||
tm->tm_wday = (days + 4) % 7;
|
||||
/* Ensure tm_wday is always positive */
|
||||
if (tm->tm_wday < 0)
|
||||
tm->tm_wday += 7;
|
||||
|
||||
/*
|
||||
* The following algorithm is, basically, Proposition 6.3 of Neri
|
||||
@@ -93,7 +107,7 @@ void rtc_time64_to_tm(time64_t time, struct rtc_time *tm)
|
||||
* thus, is slightly different from [1].
|
||||
*/
|
||||
|
||||
udays = ((u32) days) + 719468;
|
||||
udays = days + 719468;
|
||||
|
||||
u32tmp = 4 * udays + 3;
|
||||
century = u32tmp / 146097;
|
||||
|
||||
@@ -148,6 +148,11 @@ static void tb_cfg_request_dequeue(struct tb_cfg_request *req)
|
||||
struct tb_ctl *ctl = req->ctl;
|
||||
|
||||
mutex_lock(&ctl->request_queue_lock);
|
||||
if (!test_bit(TB_CFG_REQUEST_ACTIVE, &req->flags)) {
|
||||
mutex_unlock(&ctl->request_queue_lock);
|
||||
return;
|
||||
}
|
||||
|
||||
list_del(&req->list);
|
||||
clear_bit(TB_CFG_REQUEST_ACTIVE, &req->flags);
|
||||
if (test_bit(TB_CFG_REQUEST_CANCELED, &req->flags))
|
||||
|
||||
@@ -451,6 +451,7 @@ int jsm_uart_port_init(struct jsm_board *brd)
|
||||
if (!brd->channels[i])
|
||||
continue;
|
||||
|
||||
brd->channels[i]->uart_port.dev = &brd->pci_dev->dev;
|
||||
brd->channels[i]->uart_port.irq = brd->irq;
|
||||
brd->channels[i]->uart_port.uartclk = 14745600;
|
||||
brd->channels[i]->uart_port.type = PORT_JSM;
|
||||
|
||||
@@ -483,6 +483,7 @@ static int usbtmc_get_stb(struct usbtmc_file_data *file_data, __u8 *stb)
|
||||
u8 tag;
|
||||
int rv;
|
||||
long wait_rv;
|
||||
unsigned long expire;
|
||||
|
||||
dev_dbg(dev, "Enter ioctl_read_stb iin_ep_present: %d\n",
|
||||
data->iin_ep_present);
|
||||
@@ -512,10 +513,11 @@ static int usbtmc_get_stb(struct usbtmc_file_data *file_data, __u8 *stb)
|
||||
}
|
||||
|
||||
if (data->iin_ep_present) {
|
||||
expire = msecs_to_jiffies(file_data->timeout);
|
||||
wait_rv = wait_event_interruptible_timeout(
|
||||
data->waitq,
|
||||
atomic_read(&data->iin_data_valid) != 0,
|
||||
file_data->timeout);
|
||||
expire);
|
||||
if (wait_rv < 0) {
|
||||
dev_dbg(dev, "wait interrupted %ld\n", wait_rv);
|
||||
rv = wait_rv;
|
||||
|
||||
@@ -372,6 +372,9 @@ static const struct usb_device_id usb_quirk_list[] = {
|
||||
/* SanDisk Corp. SanDisk 3.2Gen1 */
|
||||
{ USB_DEVICE(0x0781, 0x55a3), .driver_info = USB_QUIRK_DELAY_INIT },
|
||||
|
||||
/* SanDisk Extreme 55AE */
|
||||
{ USB_DEVICE(0x0781, 0x55ae), .driver_info = USB_QUIRK_NO_LPM },
|
||||
|
||||
/* Realforce 87U Keyboard */
|
||||
{ USB_DEVICE(0x0853, 0x011b), .driver_info = USB_QUIRK_NO_LPM },
|
||||
|
||||
|
||||
@@ -457,6 +457,8 @@ static int pl2303_detect_type(struct usb_serial *serial)
|
||||
case 0x605:
|
||||
case 0x700: /* GR */
|
||||
case 0x705:
|
||||
case 0x905: /* GT-2AB */
|
||||
case 0x1005: /* GC-Q20 */
|
||||
return TYPE_HXN;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -52,6 +52,13 @@ UNUSUAL_DEV(0x059f, 0x1061, 0x0000, 0x9999,
|
||||
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
|
||||
US_FL_NO_REPORT_OPCODES | US_FL_NO_SAME),
|
||||
|
||||
/* Reported-by: Zhihong Zhou <zhouzhihong@greatwall.com.cn> */
|
||||
UNUSUAL_DEV(0x0781, 0x55e8, 0x0000, 0x9999,
|
||||
"SanDisk",
|
||||
"",
|
||||
USB_SC_DEVICE, USB_PR_DEVICE, NULL,
|
||||
US_FL_IGNORE_UAS),
|
||||
|
||||
/* Reported-by: Hongling Zeng <zenghongling@kylinos.cn> */
|
||||
UNUSUAL_DEV(0x090c, 0x2000, 0x0000, 0x9999,
|
||||
"Hiksemi",
|
||||
|
||||
@@ -367,7 +367,7 @@ struct ucsi_debugfs_entry {
|
||||
u64 low;
|
||||
u64 high;
|
||||
} response;
|
||||
u32 status;
|
||||
int status;
|
||||
struct dentry *dentry;
|
||||
};
|
||||
|
||||
|
||||
@@ -6698,7 +6698,7 @@ static ssize_t tracing_splice_read_pipe(struct file *filp,
|
||||
ret = trace_seq_to_buffer(&iter->seq,
|
||||
page_address(spd.pages[i]),
|
||||
min((size_t)trace_seq_used(&iter->seq),
|
||||
PAGE_SIZE));
|
||||
(size_t)PAGE_SIZE));
|
||||
if (ret < 0) {
|
||||
__free_page(spd.pages[i]);
|
||||
break;
|
||||
|
||||
Reference in New Issue
Block a user