Merge tag 'mfd-for-linus-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD update from Lee Jones:
"Changes to existing drivers:
- checkpatch fixes throughout the subsystem
- use Regmap to handle IRQs in max77686, extcon-max77693 and
mc13xxx-core
- use DMA in rtsx_pcr
- restrict building on unsupported architectures on timberdale,
cs5535
- SPI hardening in cros_ec_spi
- more robust error handing in asic3, cros_ec, ab8500-debugfs,
max77686 and pcf50633-core
- reorder PM runtime and regulator handing during shutdown in arizona
- enable wakeup in cros_ec_spi
- unused variable/code clean-up in pm8921-core, cros_ec, htc-i2cpld,
tps65912-spi, wm5110-tables and ab8500-debugfs
- add regulator handing into suspend() in sec-core
- remove pointless wrapper functions in extcon-max77693 and
i2c-cros-ec-tunnel
- use cross-architecture friendly data sizes in stmpe-i2c, arizona,
max77686 and tps65910
- devicetree documentation updates throughout
- provide power management support in max77686
- few OF clean-ups in max77686
- use manged resources in tps6105x
New drivers/supported devices:
- add support for s2mpu02 to sec-core
- add support for Allwinner A32 to sun6i-prcm
- add support for Maxim 77802 in max77686
- add support for DA9063 AD in da9063
- new driver for Intel PMICs (generic) and specifically Crystal Cove
(Re-)moved drivers ==
- move out keyboard functionality cros_ec ==> input/keyboard/cros_ec_keyb"
* tag 'mfd-for-linus-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (101 commits)
MAINTAINERS: Update MFD repo location
mfd: omap-usb-host: Fix improper mask use.
mfd: arizona: Only free the CTRLIF_ERR IRQ if we requested it
mfd: arizona: Add missing handling for ISRC3 under/overclocked
mfd: wm5110: Add new interrupt register definitions
mfd: arizona: Rename thermal shutdown interrupt
mfd: wm5110: Add in the output done interrupts
mfd: wm5110: Remove non-existant interrupts
mfd: tps65912-spi: Remove unused variable
mfd: htc-i2cpld: Remove unused code
mfd: da9063: Add support for AD silicon variant
mfd: arizona: Map MICVDD from extcon device to the Arizona core
mfd: arizona: Add MICVDD to mapped regulators for wm8997
mfd: max77686: Ensure device type IDs are architecture agnostic
mfd: max77686: Add Maxim 77802 PMIC support
mfd: tps6105x: Use managed resources when allocating memory
mfd: wm8997-tables: Suppress 'line over 80 chars' warnings
mfd: kempld-core: Correct a variety of checkpatch warnings
mfd: ipaq-micro: Fix coding style errors/warnings reported by checkpatch
mfd: si476x-cmd: Remedy checkpatch style complains
...
This commit is contained in:
Linus Torvalds
@@ -505,6 +505,7 @@ static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
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void ab8500_override_turn_on_stat(u8 mask, u8 set);
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#ifdef CONFIG_AB8500_DEBUG
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extern int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
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void ab8500_dump_all_banks(struct device *dev);
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void ab8500_debug_register_interrupt(int line);
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#else
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@@ -18,7 +18,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/mfd/arizona/pdata.h>
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#define ARIZONA_MAX_CORE_SUPPLIES 3
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#define ARIZONA_MAX_CORE_SUPPLIES 2
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enum arizona_type {
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WM5102 = 1,
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@@ -46,8 +46,8 @@ enum arizona_type {
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#define ARIZONA_IRQ_DSP_IRQ6 17
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#define ARIZONA_IRQ_DSP_IRQ7 18
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#define ARIZONA_IRQ_DSP_IRQ8 19
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#define ARIZONA_IRQ_SPK_SHUTDOWN_WARN 20
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#define ARIZONA_IRQ_SPK_SHUTDOWN 21
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#define ARIZONA_IRQ_SPK_OVERHEAT_WARN 20
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#define ARIZONA_IRQ_SPK_OVERHEAT 21
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#define ARIZONA_IRQ_MICDET 22
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#define ARIZONA_IRQ_HPDET 23
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#define ARIZONA_IRQ_WSEQ_DONE 24
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@@ -78,8 +78,31 @@ enum arizona_type {
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#define ARIZONA_IRQ_FLL1_CLOCK_OK 49
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#define ARIZONA_IRQ_MICD_CLAMP_RISE 50
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#define ARIZONA_IRQ_MICD_CLAMP_FALL 51
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#define ARIZONA_IRQ_HP3R_DONE 52
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#define ARIZONA_IRQ_HP3L_DONE 53
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#define ARIZONA_IRQ_HP2R_DONE 54
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#define ARIZONA_IRQ_HP2L_DONE 55
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#define ARIZONA_IRQ_HP1R_DONE 56
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#define ARIZONA_IRQ_HP1L_DONE 57
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#define ARIZONA_IRQ_ISRC3_CFG_ERR 58
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#define ARIZONA_IRQ_DSP_SHARED_WR_COLL 59
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#define ARIZONA_IRQ_SPK_SHUTDOWN 60
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#define ARIZONA_IRQ_SPK1R_SHORT 61
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#define ARIZONA_IRQ_SPK1L_SHORT 62
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#define ARIZONA_IRQ_HP3R_SC_NEG 63
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#define ARIZONA_IRQ_HP3R_SC_POS 64
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#define ARIZONA_IRQ_HP3L_SC_NEG 65
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#define ARIZONA_IRQ_HP3L_SC_POS 66
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#define ARIZONA_IRQ_HP2R_SC_NEG 67
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#define ARIZONA_IRQ_HP2R_SC_POS 68
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#define ARIZONA_IRQ_HP2L_SC_NEG 69
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#define ARIZONA_IRQ_HP2L_SC_POS 70
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#define ARIZONA_IRQ_HP1R_SC_NEG 71
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#define ARIZONA_IRQ_HP1R_SC_POS 72
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#define ARIZONA_IRQ_HP1L_SC_NEG 73
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#define ARIZONA_IRQ_HP1L_SC_POS 74
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#define ARIZONA_NUM_IRQ 52
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#define ARIZONA_NUM_IRQ 75
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struct snd_soc_dapm_context;
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@@ -109,6 +132,8 @@ struct arizona {
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struct mutex clk_lock;
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int clk32k_ref;
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bool ctrlif_error;
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struct snd_soc_dapm_context *dapm;
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int tdm_width[ARIZONA_MAX_AIF];
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@@ -878,22 +878,26 @@
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#define ARIZONA_INTERRUPT_STATUS_3 0xD02
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#define ARIZONA_INTERRUPT_STATUS_4 0xD03
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#define ARIZONA_INTERRUPT_STATUS_5 0xD04
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#define ARIZONA_INTERRUPT_STATUS_6 0xD05
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#define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08
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#define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09
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#define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A
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#define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B
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#define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C
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#define ARIZONA_INTERRUPT_STATUS_6_MASK 0xD0D
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#define ARIZONA_INTERRUPT_CONTROL 0xD0F
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#define ARIZONA_IRQ2_STATUS_1 0xD10
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#define ARIZONA_IRQ2_STATUS_2 0xD11
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#define ARIZONA_IRQ2_STATUS_3 0xD12
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#define ARIZONA_IRQ2_STATUS_4 0xD13
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#define ARIZONA_IRQ2_STATUS_5 0xD14
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#define ARIZONA_IRQ2_STATUS_6 0xD15
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#define ARIZONA_IRQ2_STATUS_1_MASK 0xD18
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#define ARIZONA_IRQ2_STATUS_2_MASK 0xD19
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#define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A
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#define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B
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#define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C
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#define ARIZONA_IRQ2_STATUS_6_MASK 0xD1D
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#define ARIZONA_IRQ2_CONTROL 0xD1F
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#define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20
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#define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21
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@@ -902,6 +906,7 @@
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#define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24
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#define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25
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#define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26
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#define ARIZONA_INTERRUPT_RAW_STATUS_9 0xD28
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#define ARIZONA_IRQ_PIN_STATUS 0xD40
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#define ARIZONA_ADSP2_IRQ0 0xD41
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#define ARIZONA_AOD_WKUP_AND_TRIG 0xD50
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@@ -4691,14 +4696,14 @@
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/*
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* R3330 (0xD02) - Interrupt Status 3
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*/
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#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_WARN_EINT1 0x8000 /* SPK_OVERHEAT_WARN_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_WARN_EINT1_MASK 0x8000 /* SPK_OVERHEAD_WARN_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_WARN_EINT1_SHIFT 15 /* SPK_OVERHEAT_WARN_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_EINT1 0x4000 /* SPK_OVERHEAT_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_EINT1_MASK 0x4000 /* SPK_OVERHEAT_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_EINT1_SHIFT 14 /* SPK_OVERHEAT_EINT1 */
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#define ARIZONA_SPK_OVERHEAT_EINT1_WIDTH 1 /* SPK_OVERHEAT_EINT1 */
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#define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */
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#define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */
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#define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */
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@@ -4795,6 +4800,77 @@
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#define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_HP3R_DONE_EINT1 0x0020 /* HP3R_DONE_EINT1 */
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#define ARIZONA_HP3R_DONE_EINT1_MASK 0x0020 /* HP3R_DONE_EINT1 */
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#define ARIZONA_HP3R_DONE_EINT1_SHIFT 5 /* HP3R_DONE_EINT1 */
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#define ARIZONA_HP3R_DONE_EINT1_WIDTH 1 /* HP3R_DONE_EINT1 */
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#define ARIZONA_HP3L_DONE_EINT1 0x0010 /* HP3L_DONE_EINT1 */
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#define ARIZONA_HP3L_DONE_EINT1_MASK 0x0010 /* HP3L_DONE_EINT1 */
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#define ARIZONA_HP3L_DONE_EINT1_SHIFT 4 /* HP3L_DONE_EINT1 */
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#define ARIZONA_HP3L_DONE_EINT1_WIDTH 1 /* HP3L_DONE_EINT1 */
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#define ARIZONA_HP2R_DONE_EINT1 0x0008 /* HP2R_DONE_EINT1 */
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#define ARIZONA_HP2R_DONE_EINT1_MASK 0x0008 /* HP2R_DONE_EINT1 */
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#define ARIZONA_HP2R_DONE_EINT1_SHIFT 3 /* HP2R_DONE_EINT1 */
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#define ARIZONA_HP2R_DONE_EINT1_WIDTH 1 /* HP2R_DONE_EINT1 */
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#define ARIZONA_HP2L_DONE_EINT1 0x0004 /* HP2L_DONE_EINT1 */
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#define ARIZONA_HP2L_DONE_EINT1_MASK 0x0004 /* HP2L_DONE_EINT1 */
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#define ARIZONA_HP2L_DONE_EINT1_SHIFT 2 /* HP2L_DONE_EINT1 */
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#define ARIZONA_HP2L_DONE_EINT1_WIDTH 1 /* HP2L_DONE_EINT1 */
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#define ARIZONA_HP1R_DONE_EINT1 0x0002 /* HP1R_DONE_EINT1 */
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#define ARIZONA_HP1R_DONE_EINT1_MASK 0x0002 /* HP1R_DONE_EINT1 */
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#define ARIZONA_HP1R_DONE_EINT1_SHIFT 1 /* HP1R_DONE_EINT1 */
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#define ARIZONA_HP1R_DONE_EINT1_WIDTH 1 /* HP1R_DONE_EINT1 */
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#define ARIZONA_HP1L_DONE_EINT1 0x0001 /* HP1L_DONE_EINT1 */
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#define ARIZONA_HP1L_DONE_EINT1_MASK 0x0001 /* HP1L_DONE_EINT1 */
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#define ARIZONA_HP1L_DONE_EINT1_SHIFT 0 /* HP1L_DONE_EINT1 */
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#define ARIZONA_HP1L_DONE_EINT1_WIDTH 1 /* HP1L_DONE_EINT1 */
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/*
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* R3331 (0xD03) - Interrupt Status 4 (Alternate layout)
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*
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* Alternate layout used on later devices, note only fields that have moved
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* are specified
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*/
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#define ARIZONA_V2_AIF3_ERR_EINT1 0x8000 /* AIF3_ERR_EINT1 */
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#define ARIZONA_V2_AIF3_ERR_EINT1_MASK 0x8000 /* AIF3_ERR_EINT1 */
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#define ARIZONA_V2_AIF3_ERR_EINT1_SHIFT 15 /* AIF3_ERR_EINT1 */
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#define ARIZONA_V2_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */
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#define ARIZONA_V2_AIF2_ERR_EINT1 0x4000 /* AIF2_ERR_EINT1 */
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#define ARIZONA_V2_AIF2_ERR_EINT1_MASK 0x4000 /* AIF2_ERR_EINT1 */
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#define ARIZONA_V2_AIF2_ERR_EINT1_SHIFT 14 /* AIF2_ERR_EINT1 */
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#define ARIZONA_V2_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */
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#define ARIZONA_V2_AIF1_ERR_EINT1 0x2000 /* AIF1_ERR_EINT1 */
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#define ARIZONA_V2_AIF1_ERR_EINT1_MASK 0x2000 /* AIF1_ERR_EINT1 */
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#define ARIZONA_V2_AIF1_ERR_EINT1_SHIFT 13 /* AIF1_ERR_EINT1 */
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#define ARIZONA_V2_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */
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#define ARIZONA_V2_CTRLIF_ERR_EINT1 0x1000 /* CTRLIF_ERR_EINT1 */
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#define ARIZONA_V2_CTRLIF_ERR_EINT1_MASK 0x1000 /* CTRLIF_ERR_EINT1 */
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#define ARIZONA_V2_CTRLIF_ERR_EINT1_SHIFT 12 /* CTRLIF_ERR_EINT1 */
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#define ARIZONA_V2_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */
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#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1 0x0800 /* MIXER_DROPPED_SAMPLE_EINT1 */
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#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0800 /* MIXER_DROPPED_SAMPLE_EINT1 */
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#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 11 /* MIXER_DROPPED_SAMPLE_EINT1 */
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#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */
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#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1 0x0400 /* ASYNC_CLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0400 /* ASYNC_CLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 10 /* ASYNC_CLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1 0x0200 /* SYSCLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_MASK 0x0200 /* SYSCLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_SHIFT 9 /* SYSCLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */
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#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1 0x0100 /* ISRC1_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_MASK 0x0100 /* ISRC1_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_SHIFT 8 /* ISRC1_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1 0x0080 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_MASK 0x0080 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_SHIFT 7 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1 0x0040 /* ISRC3_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_MASK 0x0040 /* ISRC3_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_SHIFT 6 /* ISRC3_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ISRC3_CFG_ERR_EINT1_WIDTH 1 /* ISRC3_CFG_ERR_EINT1 */
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/*
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* R3332 (0xD04) - Interrupt Status 5
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@@ -4820,6 +4896,85 @@
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#define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */
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#define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */
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/*
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* R3332 (0xD05) - Interrupt Status 5 (Alternate layout)
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*
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* Alternate layout used on later devices, note only fields that have moved
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* are specified
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*/
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#define ARIZONA_V2_ASRC_CFG_ERR_EINT1 0x0008 /* ASRC_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ASRC_CFG_ERR_EINT1_MASK 0x0008 /* ASRC_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ASRC_CFG_ERR_EINT1_SHIFT 3 /* ASRC_CFG_ERR_EINT1 */
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#define ARIZONA_V2_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */
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/*
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* R3333 (0xD05) - Interrupt Status 6
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*/
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#define ARIZONA_DSP_SHARED_WR_COLL_EINT1 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */
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#define ARIZONA_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT1 */
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#define ARIZONA_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT1 */
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#define ARIZONA_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */
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#define ARIZONA_SPK1R_SHORT_EINT1 0x2000 /* SPK1R_SHORT_EINT1 */
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#define ARIZONA_SPK1R_SHORT_EINT1_MASK 0x2000 /* SPK1R_SHORT_EINT1 */
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#define ARIZONA_SPK1R_SHORT_EINT1_SHIFT 13 /* SPK1R_SHORT_EINT1 */
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#define ARIZONA_SPK1R_SHORT_EINT1_WIDTH 1 /* SPK1R_SHORT_EINT1 */
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||||
#define ARIZONA_SPK1L_SHORT_EINT1 0x1000 /* SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT1_MASK 0x1000 /* SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT1_SHIFT 12 /* SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT1_WIDTH 1 /* SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT1 0x0800 /* HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT1_MASK 0x0800 /* HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT1_SHIFT 11 /* HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT1_WIDTH 1 /* HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT1 0x0400 /* HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT1_MASK 0x0400 /* HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT1_SHIFT 10 /* HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT1_WIDTH 1 /* HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT1 0x0200 /* HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT1_MASK 0x0200 /* HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT1_SHIFT 9 /* HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT1_WIDTH 1 /* HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT1 0x0100 /* HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT1_MASK 0x0100 /* HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT1_SHIFT 8 /* HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT1_WIDTH 1 /* HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT1 0x0080 /* HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT1_MASK 0x0080 /* HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT1_SHIFT 7 /* HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT1_WIDTH 1 /* HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT1 0x0040 /* HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT1_MASK 0x0040 /* HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT1_SHIFT 6 /* HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT1_WIDTH 1 /* HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT1 0x0020 /* HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT1_MASK 0x0020 /* HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT1_SHIFT 5 /* HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT1_WIDTH 1 /* HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT1 0x0010 /* HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT1_MASK 0x0010 /* HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT1_SHIFT 4 /* HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT1_WIDTH 1 /* HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT1 0x0008 /* HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT1_MASK 0x0008 /* HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT1_SHIFT 3 /* HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT1_WIDTH 1 /* HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT1 0x0004 /* HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT1_MASK 0x0004 /* HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT1_SHIFT 2 /* HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT1_WIDTH 1 /* HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT1 0x0002 /* HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT1_MASK 0x0002 /* HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT1_SHIFT 1 /* HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT1_WIDTH 1 /* HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT1 0x0001 /* HP1L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT1_MASK 0x0001 /* HP1L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT1_SHIFT 0 /* HP1L_SC_POS_EINT1 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT1_WIDTH 1 /* HP1L_SC_POS_EINT1 */
|
||||
|
||||
/*
|
||||
* R3336 (0xD08) - Interrupt Status 1 Mask
|
||||
*/
|
||||
@@ -4859,14 +5014,14 @@
|
||||
/*
|
||||
* R3338 (0xD0A) - Interrupt Status 3 Mask
|
||||
*/
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_MASK 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_SHIFT 15 /* IM_SPK_OVERHEAT_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT1 0x4000 /* IM_SPK_OVERHEAT_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT1_MASK 0x4000 /* IM_SPK_OVERHEAT_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT1_SHIFT 14 /* IM_SPK_OVERHEAT_EINT1 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT1_WIDTH 1 /* IM_SPK_OVERHEAT_EINT1 */
|
||||
#define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */
|
||||
#define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */
|
||||
#define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */
|
||||
@@ -4963,6 +5118,77 @@
|
||||
#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT1 0x0020 /* IM_HP3R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT1_MASK 0x0020 /* IM_HP3R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT1_SHIFT 5 /* IM_HP3R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT1_WIDTH 1 /* IM_HP3R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT1 0x0010 /* IM_HP3L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT1_MASK 0x0010 /* IM_HP3L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT1_SHIFT 4 /* IM_HP3L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT1_WIDTH 1 /* IM_HP3L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT1 0x0008 /* IM_HP2R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT1_MASK 0x0008 /* IM_HP2R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT1_SHIFT 3 /* IM_HP2R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT1_WIDTH 1 /* IM_HP2R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT1 0x0004 /* IM_HP2L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT1_MASK 0x0004 /* IM_HP2L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT1_SHIFT 2 /* IM_HP2L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT1_WIDTH 1 /* IM_HP2L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT1 0x0002 /* IM_HP1R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT1_MASK 0x0002 /* IM_HP1R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT1_SHIFT 1 /* IM_HP1R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT1_WIDTH 1 /* IM_HP1R_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT1 0x0001 /* IM_HP1L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT1_MASK 0x0001 /* IM_HP1L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT1_SHIFT 0 /* IM_HP1L_DONE_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT1_WIDTH 1 /* IM_HP1L_DONE_EINT1 */
|
||||
|
||||
/*
|
||||
* R3339 (0xD0B) - Interrupt Status 4 Mask (Alternate layout)
|
||||
*
|
||||
* Alternate layout used on later devices, note only fields that have moved
|
||||
* are specified
|
||||
*/
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT1 0x8000 /* IM_AIF3_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT1_MASK 0x8000 /* IM_AIF3_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT1_SHIFT 15 /* IM_AIF3_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT1 0x4000 /* IM_AIF2_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT1_MASK 0x4000 /* IM_AIF2_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT1_SHIFT 14 /* IM_AIF2_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT1 0x2000 /* IM_AIF1_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT1_MASK 0x2000 /* IM_AIF1_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT1_SHIFT 13 /* IM_AIF1_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1 0x1000 /* IM_CTRLIF_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_MASK 0x1000 /* IM_CTRLIF_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_SHIFT 12 /* IM_CTRLIF_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 11 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 10 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1 0x0200 /* IM_SYSCLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_SYSCLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 9 /* IM_SYSCLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1 0x0100 /* IM_ISRC1_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0100 /* IM_ISRC1_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_SHIFT 8 /* IM_ISRC1_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1 0x0080 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1 0x0040 /* IM_ISRC3_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC3_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC3_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC3_CFG_ERR_EINT1 */
|
||||
|
||||
/*
|
||||
* R3340 (0xD0C) - Interrupt Status 5 Mask
|
||||
@@ -4988,6 +5214,85 @@
|
||||
#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */
|
||||
#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */
|
||||
|
||||
/*
|
||||
* R3340 (0xD0C) - Interrupt Status 5 Mask (Alternate layout)
|
||||
*
|
||||
* Alternate layout used on later devices, note only fields that have moved
|
||||
* are specified
|
||||
*/
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1 0x0008 /* IM_ASRC_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_MASK 0x0008 /* IM_ASRC_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_SHIFT 3 /* IM_ASRC_CFG_ERR_EINT1 */
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */
|
||||
|
||||
/*
|
||||
* R3341 (0xD0D) - Interrupt Status 6 Mask
|
||||
*/
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT1 */
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT1 */
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT1_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT1 0x2000 /* IM_SPK1R_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT1_MASK 0x2000 /* IM_SPK1R_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT1_SHIFT 13 /* IM_SPK1R_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT1_WIDTH 1 /* IM_SPK1R_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT1 0x1000 /* IM_SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT1_MASK 0x1000 /* IM_SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT1_SHIFT 12 /* IM_SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT1_WIDTH 1 /* IM_SPK1L_SHORT_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT1 0x0800 /* IM_HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT1_MASK 0x0800 /* IM_HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT1_SHIFT 11 /* IM_HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT1_WIDTH 1 /* IM_HP3R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT1 0x0400 /* IM_HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT1_MASK 0x0400 /* IM_HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT1_SHIFT 10 /* IM_HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT1_WIDTH 1 /* IM_HP3R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT1 0x0200 /* IM_HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT1_MASK 0x0200 /* IM_HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT1_SHIFT 9 /* IM_HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT1_WIDTH 1 /* IM_HP3L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT1 0x0100 /* IM_HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT1_MASK 0x0100 /* IM_HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT1_SHIFT 8 /* IM_HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT1_WIDTH 1 /* IM_HP3L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT1 0x0080 /* IM_HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT1_MASK 0x0080 /* IM_HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT1_SHIFT 7 /* IM_HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT1_WIDTH 1 /* IM_HP2R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT1 0x0040 /* IM_HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT1_MASK 0x0040 /* IM_HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT1_SHIFT 6 /* IM_HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT1_WIDTH 1 /* IM_HP2R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT1 0x0020 /* IM_HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT1_MASK 0x0020 /* IM_HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT1_SHIFT 5 /* IM_HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT1_WIDTH 1 /* IM_HP2L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT1 0x0010 /* IM_HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT1_MASK 0x0010 /* IM_HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT1_SHIFT 4 /* IM_HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT1_WIDTH 1 /* IM_HP2L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT1 0x0008 /* IM_HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT1_MASK 0x0008 /* IM_HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT1_SHIFT 3 /* IM_HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT1_WIDTH 1 /* IM_HP1R_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT1 0x0004 /* IM_HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT1_MASK 0x0004 /* IM_HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT1_SHIFT 2 /* IM_HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT1_WIDTH 1 /* IM_HP1R_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT1 0x0002 /* IM_HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT1_MASK 0x0002 /* IM_HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT1_SHIFT 1 /* IM_HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT1_WIDTH 1 /* IM_HP1L_SC_NEG_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT1 0x0001 /* IM_HP1L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT1_MASK 0x0001 /* IM_HP1L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT1_SHIFT 0 /* IM_HP1L_SC_POS_EINT1 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT1_WIDTH 1 /* IM_HP1L_SC_POS_EINT1 */
|
||||
|
||||
/*
|
||||
* R3343 (0xD0F) - Interrupt Control
|
||||
*/
|
||||
@@ -5035,14 +5340,14 @@
|
||||
/*
|
||||
* R3346 (0xD12) - IRQ2 Status 3
|
||||
*/
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_EINT2 0x8000 /* SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_EINT2_MASK 0x8000 /* SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_EINT2_SHIFT 15 /* SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_EINT2 0x4000 /* SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_EINT2_MASK 0x4000 /* SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_EINT2_SHIFT 14 /* SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_SPK_OVERHEAT_EINT2_WIDTH 1 /* SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */
|
||||
#define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */
|
||||
#define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */
|
||||
@@ -5139,6 +5444,77 @@
|
||||
#define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_HP3R_DONE_EINT2 0x0020 /* HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_HP3R_DONE_EINT2_MASK 0x0020 /* HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_HP3R_DONE_EINT2_SHIFT 5 /* HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_HP3R_DONE_EINT2_WIDTH 1 /* HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_HP3L_DONE_EINT2 0x0010 /* HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_HP3L_DONE_EINT2_MASK 0x0010 /* HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_HP3L_DONE_EINT2_SHIFT 4 /* HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_HP3L_DONE_EINT2_WIDTH 1 /* HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_HP2R_DONE_EINT2 0x0008 /* HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_HP2R_DONE_EINT2_MASK 0x0008 /* HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_HP2R_DONE_EINT2_SHIFT 3 /* HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_HP2R_DONE_EINT2_WIDTH 1 /* HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_HP2L_DONE_EINT2 0x0004 /* HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_HP2L_DONE_EINT2_MASK 0x0004 /* HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_HP2L_DONE_EINT2_SHIFT 2 /* HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_HP2L_DONE_EINT2_WIDTH 1 /* HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_HP1R_DONE_EINT2 0x0002 /* HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_HP1R_DONE_EINT2_MASK 0x0002 /* HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_HP1R_DONE_EINT2_SHIFT 1 /* HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_HP1R_DONE_EINT2_WIDTH 1 /* HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_HP1L_DONE_EINT2 0x0001 /* HP1L_DONE_EINT2 */
|
||||
#define ARIZONA_HP1L_DONE_EINT2_MASK 0x0001 /* HP1L_DONE_EINT2 */
|
||||
#define ARIZONA_HP1L_DONE_EINT2_SHIFT 0 /* HP1L_DONE_EINT2 */
|
||||
#define ARIZONA_HP1L_DONE_EINT2_WIDTH 1 /* HP1L_DONE_EINT2 */
|
||||
|
||||
/*
|
||||
* R3347 (0xD13) - IRQ2 Status 4 (Alternate layout)
|
||||
*
|
||||
* Alternate layout used on later devices, note only fields that have moved
|
||||
* are specified
|
||||
*/
|
||||
#define ARIZONA_V2_AIF3_ERR_EINT2 0x8000 /* AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF3_ERR_EINT2_MASK 0x8000 /* AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF3_ERR_EINT2_SHIFT 15 /* AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF2_ERR_EINT2 0x4000 /* AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF2_ERR_EINT2_MASK 0x4000 /* AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF2_ERR_EINT2_SHIFT 14 /* AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF1_ERR_EINT2 0x2000 /* AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF1_ERR_EINT2_MASK 0x2000 /* AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF1_ERR_EINT2_SHIFT 13 /* AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_CTRLIF_ERR_EINT2 0x1000 /* CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_CTRLIF_ERR_EINT2_MASK 0x1000 /* CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_CTRLIF_ERR_EINT2_SHIFT 12 /* CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2 0x0800 /* MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0800 /* MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 11 /* MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2 0x0400 /* ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0400 /* ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 10 /* ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2 0x0200 /* SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_MASK 0x0200 /* SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_SHIFT 9 /* SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2 0x0100 /* ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_MASK 0x0100 /* ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_SHIFT 8 /* ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2 0x0080 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_MASK 0x0080 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_SHIFT 7 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2 0x0040 /* ISRC3_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_MASK 0x0040 /* ISRC3_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_SHIFT 6 /* ISRC3_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ISRC3_CFG_ERR_EINT2_WIDTH 1 /* ISRC3_CFG_ERR_EINT2 */
|
||||
|
||||
/*
|
||||
* R3348 (0xD14) - IRQ2 Status 5
|
||||
@@ -5164,6 +5540,85 @@
|
||||
#define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */
|
||||
#define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */
|
||||
|
||||
/*
|
||||
* R3348 (0xD14) - IRQ2 Status 5 (Alternate layout)
|
||||
*
|
||||
* Alternate layout used on later devices, note only fields that have moved
|
||||
* are specified
|
||||
*/
|
||||
#define ARIZONA_V2_ASRC_CFG_ERR_EINT2 0x0008 /* ASRC_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ASRC_CFG_ERR_EINT2_MASK 0x0008 /* ASRC_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ASRC_CFG_ERR_EINT2_SHIFT 3 /* ASRC_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */
|
||||
|
||||
/*
|
||||
* R3349 (0xD15) - IRQ2 Status 6
|
||||
*/
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_EINT2 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_SPK1R_SHORT_EINT2 0x2000 /* SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1R_SHORT_EINT2_MASK 0x2000 /* SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1R_SHORT_EINT2_SHIFT 13 /* SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1R_SHORT_EINT2_WIDTH 1 /* SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT2 0x1000 /* SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT2_MASK 0x1000 /* SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT2_SHIFT 12 /* SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_SPK1L_SHORT_EINT2_WIDTH 1 /* SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT2 0x0800 /* HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT2_MASK 0x0800 /* HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT2_SHIFT 11 /* HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_NEG_EINT2_WIDTH 1 /* HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT2 0x0400 /* HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT2_MASK 0x0400 /* HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT2_SHIFT 10 /* HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3R_SC_POS_EINT2_WIDTH 1 /* HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT2 0x0200 /* HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT2_MASK 0x0200 /* HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT2_SHIFT 9 /* HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_NEG_EINT2_WIDTH 1 /* HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT2 0x0100 /* HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT2_MASK 0x0100 /* HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT2_SHIFT 8 /* HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP3L_SC_POS_EINT2_WIDTH 1 /* HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT2 0x0080 /* HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT2_MASK 0x0080 /* HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT2_SHIFT 7 /* HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_NEG_EINT2_WIDTH 1 /* HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT2 0x0040 /* HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT2_MASK 0x0040 /* HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT2_SHIFT 6 /* HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2R_SC_POS_EINT2_WIDTH 1 /* HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT2 0x0020 /* HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT2_MASK 0x0020 /* HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT2_SHIFT 5 /* HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_NEG_EINT2_WIDTH 1 /* HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT2 0x0010 /* HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT2_MASK 0x0010 /* HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT2_SHIFT 4 /* HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP2L_SC_POS_EINT2_WIDTH 1 /* HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT2 0x0008 /* HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT2_MASK 0x0008 /* HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT2_SHIFT 3 /* HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_NEG_EINT2_WIDTH 1 /* HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT2 0x0004 /* HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT2_MASK 0x0004 /* HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT2_SHIFT 2 /* HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1R_SC_POS_EINT2_WIDTH 1 /* HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT2 0x0002 /* HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT2_MASK 0x0002 /* HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT2_SHIFT 1 /* HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_NEG_EINT2_WIDTH 1 /* HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT2 0x0001 /* HP1L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT2_MASK 0x0001 /* HP1L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT2_SHIFT 0 /* HP1L_SC_POS_EINT2 */
|
||||
#define ARIZONA_HP1L_SC_POS_EINT2_WIDTH 1 /* HP1L_SC_POS_EINT2 */
|
||||
|
||||
/*
|
||||
* R3352 (0xD18) - IRQ2 Status 1 Mask
|
||||
*/
|
||||
@@ -5203,14 +5658,14 @@
|
||||
/*
|
||||
* R3354 (0xD1A) - IRQ2 Status 3 Mask
|
||||
*/
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_MASK 0x8000 /* IM_SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_SHIFT 15 /* IM_SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_WARN_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_WARN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT2 0x4000 /* IM_SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT2_MASK 0x4000 /* IM_SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT2_SHIFT 14 /* IM_SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_IM_SPK_OVERHEAT_EINT2_WIDTH 1 /* IM_SPK_OVERHEAT_EINT2 */
|
||||
#define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */
|
||||
#define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */
|
||||
#define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */
|
||||
@@ -5307,6 +5762,77 @@
|
||||
#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT2 0x0020 /* IM_HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT2_MASK 0x0020 /* IM_HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT2_SHIFT 5 /* IM_HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_DONE_EINT2_WIDTH 1 /* IM_HP3R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT2 0x0010 /* IM_HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT2_MASK 0x0010 /* IM_HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT2_SHIFT 4 /* IM_HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_DONE_EINT2_WIDTH 1 /* IM_HP3L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT2 0x0008 /* IM_HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT2_MASK 0x0008 /* IM_HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT2_SHIFT 3 /* IM_HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_DONE_EINT2_WIDTH 1 /* IM_HP2R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT2 0x0004 /* IM_HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT2_MASK 0x0004 /* IM_HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT2_SHIFT 2 /* IM_HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_DONE_EINT2_WIDTH 1 /* IM_HP2L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT2 0x0002 /* IM_HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT2_MASK 0x0002 /* IM_HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT2_SHIFT 1 /* IM_HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_DONE_EINT2_WIDTH 1 /* IM_HP1R_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT2 0x0001 /* IM_HP1L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT2_MASK 0x0001 /* IM_HP1L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT2_SHIFT 0 /* IM_HP1L_DONE_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_DONE_EINT2_WIDTH 1 /* IM_HP1L_DONE_EINT2 */
|
||||
|
||||
/*
|
||||
* R3355 (0xD1B) - IRQ2 Status 4 Mask (Alternate layout)
|
||||
*
|
||||
* Alternate layout used on later devices, note only fields that have moved
|
||||
* are specified
|
||||
*/
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT2 0x8000 /* IM_AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT2_MASK 0x8000 /* IM_AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT2_SHIFT 15 /* IM_AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT2 0x4000 /* IM_AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT2_MASK 0x4000 /* IM_AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT2_SHIFT 14 /* IM_AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT2 0x2000 /* IM_AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT2_MASK 0x2000 /* IM_AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT2_SHIFT 13 /* IM_AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2 0x1000 /* IM_CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_MASK 0x1000 /* IM_CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_SHIFT 12 /* IM_CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0800 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 11 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0400 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 10 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2 0x0200 /* IM_SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 9 /* IM_SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2 0x0100 /* IM_ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0100 /* IM_ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_SHIFT 8 /* IM_ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2 0x0080 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2 0x0040 /* IM_ISRC3_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC3_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC3_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ISRC3_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC3_CFG_ERR_EINT2 */
|
||||
|
||||
/*
|
||||
* R3356 (0xD1C) - IRQ2 Status 5 Mask
|
||||
@@ -5333,6 +5859,85 @@
|
||||
#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */
|
||||
#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */
|
||||
|
||||
/*
|
||||
* R3340 (0xD0C) - Interrupt Status 5 Mask (Alternate layout)
|
||||
*
|
||||
* Alternate layout used on later devices, note only fields that have moved
|
||||
* are specified
|
||||
*/
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2 0x0008 /* IM_ASRC_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_MASK 0x0008 /* IM_ASRC_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_SHIFT 3 /* IM_ASRC_CFG_ERR_EINT2 */
|
||||
#define ARIZONA_V2_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */
|
||||
|
||||
/*
|
||||
* R3357 (0xD1D) - IRQ2 Status 6 Mask
|
||||
*/
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_MASK 0x8000 /* IM_DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_SHIFT 15 /* IM_DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_IM_DSP_SHARED_WR_COLL_EINT2_WIDTH 1 /* IM_DSP_SHARED_WR_COLL_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT2 0x2000 /* IM_SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT2_MASK 0x2000 /* IM_SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT2_SHIFT 13 /* IM_SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1R_SHORT_EINT2_WIDTH 1 /* IM_SPK1R_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT2 0x1000 /* IM_SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT2_MASK 0x1000 /* IM_SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT2_SHIFT 12 /* IM_SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_SPK1L_SHORT_EINT2_WIDTH 1 /* IM_SPK1L_SHORT_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT2 0x0800 /* IM_HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT2_MASK 0x0800 /* IM_HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT2_SHIFT 11 /* IM_HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_NEG_EINT2_WIDTH 1 /* IM_HP3R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT2 0x0400 /* IM_HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT2_MASK 0x0400 /* IM_HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT2_SHIFT 10 /* IM_HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3R_SC_POS_EINT2_WIDTH 1 /* IM_HP3R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT2 0x0200 /* IM_HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT2_MASK 0x0200 /* IM_HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT2_SHIFT 9 /* IM_HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_NEG_EINT2_WIDTH 1 /* IM_HP3L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT2 0x0100 /* IM_HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT2_MASK 0x0100 /* IM_HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT2_SHIFT 8 /* IM_HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP3L_SC_POS_EINT2_WIDTH 1 /* IM_HP3L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT2 0x0080 /* IM_HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT2_MASK 0x0080 /* IM_HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT2_SHIFT 7 /* IM_HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_NEG_EINT2_WIDTH 1 /* IM_HP2R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT2 0x0040 /* IM_HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT2_MASK 0x0040 /* IM_HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT2_SHIFT 6 /* IM_HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2R_SC_POS_EINT2_WIDTH 1 /* IM_HP2R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT2 0x0020 /* IM_HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT2_MASK 0x0020 /* IM_HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT2_SHIFT 5 /* IM_HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_NEG_EINT2_WIDTH 1 /* IM_HP2L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT2 0x0010 /* IM_HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT2_MASK 0x0010 /* IM_HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT2_SHIFT 4 /* IM_HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP2L_SC_POS_EINT2_WIDTH 1 /* IM_HP2L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT2 0x0008 /* IM_HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT2_MASK 0x0008 /* IM_HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT2_SHIFT 3 /* IM_HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_NEG_EINT2_WIDTH 1 /* IM_HP1R_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT2 0x0004 /* IM_HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT2_MASK 0x0004 /* IM_HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT2_SHIFT 2 /* IM_HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1R_SC_POS_EINT2_WIDTH 1 /* IM_HP1R_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT2 0x0002 /* IM_HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT2_MASK 0x0002 /* IM_HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT2_SHIFT 1 /* IM_HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_NEG_EINT2_WIDTH 1 /* IM_HP1L_SC_NEG_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT2 0x0001 /* IM_HP1L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT2_MASK 0x0001 /* IM_HP1L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT2_SHIFT 0 /* IM_HP1L_SC_POS_EINT2 */
|
||||
#define ARIZONA_IM_HP1L_SC_POS_EINT2_WIDTH 1 /* IM_HP1L_SC_POS_EINT2 */
|
||||
|
||||
/*
|
||||
* R3359 (0xD1F) - IRQ2 Control
|
||||
*/
|
||||
@@ -5360,14 +5965,14 @@
|
||||
/*
|
||||
* R3361 (0xD21) - Interrupt Raw Status 3
|
||||
*/
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_STS 0x8000 /* SPK_OVERHEAT_WARN_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_STS_MASK 0x8000 /* SPK_OVERHEAT_WARN_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_STS_SHIFT 15 /* SPK_OVERHEAT_WARN_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_WARN_STS_WIDTH 1 /* SPK_OVERHEAT_WARN_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_STS 0x4000 /* SPK_OVERHEAT_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_STS_MASK 0x4000 /* SPK_OVERHEAT_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_STS_SHIFT 14 /* SPK_OVERHEAT_STS */
|
||||
#define ARIZONA_SPK_OVERHEAT_STS_WIDTH 1 /* SPK_OVERHEAT_STS */
|
||||
#define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */
|
||||
#define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */
|
||||
#define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */
|
||||
@@ -5464,6 +6069,30 @@
|
||||
#define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */
|
||||
#define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */
|
||||
#define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */
|
||||
#define ARIZONA_HP3R_DONE_STS 0x0020 /* HP3R_DONE_STS */
|
||||
#define ARIZONA_HP3R_DONE_STS_MASK 0x0020 /* HP3R_DONE_STS */
|
||||
#define ARIZONA_HP3R_DONE_STS_SHIFT 5 /* HP3R_DONE_STS */
|
||||
#define ARIZONA_HP3R_DONE_STS_WIDTH 1 /* HP3R_DONE_STS */
|
||||
#define ARIZONA_HP3L_DONE_STS 0x0010 /* HP3L_DONE_STS */
|
||||
#define ARIZONA_HP3L_DONE_STS_MASK 0x0010 /* HP3L_DONE_STS */
|
||||
#define ARIZONA_HP3L_DONE_STS_SHIFT 4 /* HP3L_DONE_STS */
|
||||
#define ARIZONA_HP3L_DONE_STS_WIDTH 1 /* HP3L_DONE_STS */
|
||||
#define ARIZONA_HP2R_DONE_STS 0x0008 /* HP2R_DONE_STS */
|
||||
#define ARIZONA_HP2R_DONE_STS_MASK 0x0008 /* HP2R_DONE_STS */
|
||||
#define ARIZONA_HP2R_DONE_STS_SHIFT 3 /* HP2R_DONE_STS */
|
||||
#define ARIZONA_HP2R_DONE_STS_WIDTH 1 /* HP2R_DONE_STS */
|
||||
#define ARIZONA_HP2L_DONE_STS 0x0004 /* HP2L_DONE_STS */
|
||||
#define ARIZONA_HP2L_DONE_STS_MASK 0x0004 /* HP2L_DONE_STS */
|
||||
#define ARIZONA_HP2L_DONE_STS_SHIFT 2 /* HP2L_DONE_STS */
|
||||
#define ARIZONA_HP2L_DONE_STS_WIDTH 1 /* HP2L_DONE_STS */
|
||||
#define ARIZONA_HP1R_DONE_STS 0x0002 /* HP1R_DONE_STS */
|
||||
#define ARIZONA_HP1R_DONE_STS_MASK 0x0002 /* HP1R_DONE_STS */
|
||||
#define ARIZONA_HP1R_DONE_STS_SHIFT 1 /* HP1R_DONE_STS */
|
||||
#define ARIZONA_HP1R_DONE_STS_WIDTH 1 /* HP1R_DONE_STS */
|
||||
#define ARIZONA_HP1L_DONE_STS 0x0001 /* HP1L_DONE_STS */
|
||||
#define ARIZONA_HP1L_DONE_STS_MASK 0x0001 /* HP1L_DONE_STS */
|
||||
#define ARIZONA_HP1L_DONE_STS_SHIFT 0 /* HP1L_DONE_STS */
|
||||
#define ARIZONA_HP1L_DONE_STS_WIDTH 1 /* HP1L_DONE_STS */
|
||||
|
||||
/*
|
||||
* R3363 (0xD23) - Interrupt Raw Status 5
|
||||
@@ -5580,6 +6209,10 @@
|
||||
#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_OVERCLOCKED_STS 0x0004 /* ISRC3_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_OVERCLOCKED_STS_MASK 0x0004 /* ISRC3_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_OVERCLOCKED_STS_SHIFT 2 /* ISRC3_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_OVERCLOCKED_STS_WIDTH 1 /* ISRC3_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */
|
||||
@@ -5604,6 +6237,10 @@
|
||||
#define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_UNDERCLOCKED_STS 0x0080 /* ISRC3_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_UNDERCLOCKED_STS_MASK 0x0080 /* ISRC3_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_UNDERCLOCKED_STS_SHIFT 7 /* ISRC3_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC3_UNDERCLOCKED_STS_WIDTH 1 /* ISRC3_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */
|
||||
@@ -5633,6 +6270,74 @@
|
||||
#define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
|
||||
#define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
|
||||
|
||||
/*
|
||||
* R3368 (0xD28) - Interrupt Raw Status 9
|
||||
*/
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_STS 0x8000 /* DSP_SHARED_WR_COLL_STS */
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_STS_MASK 0x8000 /* DSP_SHARED_WR_COLL_STS */
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_STS_SHIFT 15 /* DSP_SHARED_WR_COLL_STS */
|
||||
#define ARIZONA_DSP_SHARED_WR_COLL_STS_WIDTH 1 /* DSP_SHARED_WR_COLL_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
|
||||
#define ARIZONA_SPK1R_SHORT_STS 0x2000 /* SPK1R_SHORT_STS */
|
||||
#define ARIZONA_SPK1R_SHORT_STS_MASK 0x2000 /* SPK1R_SHORT_STS */
|
||||
#define ARIZONA_SPK1R_SHORT_STS_SHIFT 13 /* SPK1R_SHORT_STS */
|
||||
#define ARIZONA_SPK1R_SHORT_STS_WIDTH 1 /* SPK1R_SHORT_STS */
|
||||
#define ARIZONA_SPK1L_SHORT_STS 0x1000 /* SPK1L_SHORT_STS */
|
||||
#define ARIZONA_SPK1L_SHORT_STS_MASK 0x1000 /* SPK1L_SHORT_STS */
|
||||
#define ARIZONA_SPK1L_SHORT_STS_SHIFT 12 /* SPK1L_SHORT_STS */
|
||||
#define ARIZONA_SPK1L_SHORT_STS_WIDTH 1 /* SPK1L_SHORT_STS */
|
||||
#define ARIZONA_HP3R_SC_NEG_STS 0x0800 /* HP3R_SC_NEG_STS */
|
||||
#define ARIZONA_HP3R_SC_NEG_STS_MASK 0x0800 /* HP3R_SC_NEG_STS */
|
||||
#define ARIZONA_HP3R_SC_NEG_STS_SHIFT 11 /* HP3R_SC_NEG_STS */
|
||||
#define ARIZONA_HP3R_SC_NEG_STS_WIDTH 1 /* HP3R_SC_NEG_STS */
|
||||
#define ARIZONA_HP3R_SC_POS_STS 0x0400 /* HP3R_SC_POS_STS */
|
||||
#define ARIZONA_HP3R_SC_POS_STS_MASK 0x0400 /* HP3R_SC_POS_STS */
|
||||
#define ARIZONA_HP3R_SC_POS_STS_SHIFT 10 /* HP3R_SC_POS_STS */
|
||||
#define ARIZONA_HP3R_SC_POS_STS_WIDTH 1 /* HP3R_SC_POS_STS */
|
||||
#define ARIZONA_HP3L_SC_NEG_STS 0x0200 /* HP3L_SC_NEG_STS */
|
||||
#define ARIZONA_HP3L_SC_NEG_STS_MASK 0x0200 /* HP3L_SC_NEG_STS */
|
||||
#define ARIZONA_HP3L_SC_NEG_STS_SHIFT 9 /* HP3L_SC_NEG_STS */
|
||||
#define ARIZONA_HP3L_SC_NEG_STS_WIDTH 1 /* HP3L_SC_NEG_STS */
|
||||
#define ARIZONA_HP3L_SC_POS_STS 0x0100 /* HP3L_SC_POS_STS */
|
||||
#define ARIZONA_HP3L_SC_POS_STS_MASK 0x0100 /* HP3L_SC_POS_STS */
|
||||
#define ARIZONA_HP3L_SC_POS_STS_SHIFT 8 /* HP3L_SC_POS_STS */
|
||||
#define ARIZONA_HP3L_SC_POS_STS_WIDTH 1 /* HP3L_SC_POS_STS */
|
||||
#define ARIZONA_HP2R_SC_NEG_STS 0x0080 /* HP2R_SC_NEG_STS */
|
||||
#define ARIZONA_HP2R_SC_NEG_STS_MASK 0x0080 /* HP2R_SC_NEG_STS */
|
||||
#define ARIZONA_HP2R_SC_NEG_STS_SHIFT 7 /* HP2R_SC_NEG_STS */
|
||||
#define ARIZONA_HP2R_SC_NEG_STS_WIDTH 1 /* HP2R_SC_NEG_STS */
|
||||
#define ARIZONA_HP2R_SC_POS_STS 0x0040 /* HP2R_SC_POS_STS */
|
||||
#define ARIZONA_HP2R_SC_POS_STS_MASK 0x0040 /* HP2R_SC_POS_STS */
|
||||
#define ARIZONA_HP2R_SC_POS_STS_SHIFT 6 /* HP2R_SC_POS_STS */
|
||||
#define ARIZONA_HP2R_SC_POS_STS_WIDTH 1 /* HP2R_SC_POS_STS */
|
||||
#define ARIZONA_HP2L_SC_NEG_STS 0x0020 /* HP2L_SC_NEG_STS */
|
||||
#define ARIZONA_HP2L_SC_NEG_STS_MASK 0x0020 /* HP2L_SC_NEG_STS */
|
||||
#define ARIZONA_HP2L_SC_NEG_STS_SHIFT 5 /* HP2L_SC_NEG_STS */
|
||||
#define ARIZONA_HP2L_SC_NEG_STS_WIDTH 1 /* HP2L_SC_NEG_STS */
|
||||
#define ARIZONA_HP2L_SC_POS_STS 0x0010 /* HP2L_SC_POS_STS */
|
||||
#define ARIZONA_HP2L_SC_POS_STS_MASK 0x0010 /* HP2L_SC_POS_STS */
|
||||
#define ARIZONA_HP2L_SC_POS_STS_SHIFT 4 /* HP2L_SC_POS_STS */
|
||||
#define ARIZONA_HP2L_SC_POS_STS_WIDTH 1 /* HP2L_SC_POS_STS */
|
||||
#define ARIZONA_HP1R_SC_NEG_STS 0x0008 /* HP1R_SC_NEG_STS */
|
||||
#define ARIZONA_HP1R_SC_NEG_STS_MASK 0x0008 /* HP1R_SC_NEG_STS */
|
||||
#define ARIZONA_HP1R_SC_NEG_STS_SHIFT 3 /* HP1R_SC_NEG_STS */
|
||||
#define ARIZONA_HP1R_SC_NEG_STS_WIDTH 1 /* HP1R_SC_NEG_STS */
|
||||
#define ARIZONA_HP1R_SC_POS_STS 0x0004 /* HP1R_SC_POS_STS */
|
||||
#define ARIZONA_HP1R_SC_POS_STS_MASK 0x0004 /* HP1R_SC_POS_STS */
|
||||
#define ARIZONA_HP1R_SC_POS_STS_SHIFT 2 /* HP1R_SC_POS_STS */
|
||||
#define ARIZONA_HP1R_SC_POS_STS_WIDTH 1 /* HP1R_SC_POS_STS */
|
||||
#define ARIZONA_HP1L_SC_NEG_STS 0x0002 /* HP1L_SC_NEG_STS */
|
||||
#define ARIZONA_HP1L_SC_NEG_STS_MASK 0x0002 /* HP1L_SC_NEG_STS */
|
||||
#define ARIZONA_HP1L_SC_NEG_STS_SHIFT 1 /* HP1L_SC_NEG_STS */
|
||||
#define ARIZONA_HP1L_SC_NEG_STS_WIDTH 1 /* HP1L_SC_NEG_STS */
|
||||
#define ARIZONA_HP1L_SC_POS_STS 0x0001 /* HP1L_SC_POS_STS */
|
||||
#define ARIZONA_HP1L_SC_POS_STS_MASK 0x0001 /* HP1L_SC_POS_STS */
|
||||
#define ARIZONA_HP1L_SC_POS_STS_SHIFT 0 /* HP1L_SC_POS_STS */
|
||||
#define ARIZONA_HP1L_SC_POS_STS_WIDTH 1 /* HP1L_SC_POS_STS */
|
||||
|
||||
/*
|
||||
* R3392 (0xD40) - IRQ Pin Status
|
||||
*/
|
||||
|
||||
+58
-52
@@ -16,7 +16,9 @@
|
||||
#ifndef __LINUX_MFD_CROS_EC_H
|
||||
#define __LINUX_MFD_CROS_EC_H
|
||||
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/mfd/cros_ec_commands.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
/*
|
||||
* Command interface between EC and AP, for LPC, I2C and SPI interfaces.
|
||||
@@ -33,83 +35,76 @@ enum {
|
||||
EC_MSG_TX_PROTO_BYTES,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cros_ec_msg - A message sent to the EC, and its reply
|
||||
*
|
||||
/*
|
||||
* @version: Command version number (often 0)
|
||||
* @cmd: Command to send (EC_CMD_...)
|
||||
* @out_buf: Outgoing payload (to EC)
|
||||
* @outlen: Outgoing length
|
||||
* @in_buf: Incoming payload (from EC)
|
||||
* @in_len: Incoming length
|
||||
* @command: Command to send (EC_CMD_...)
|
||||
* @outdata: Outgoing data to EC
|
||||
* @outsize: Outgoing length in bytes
|
||||
* @indata: Where to put the incoming data from EC
|
||||
* @insize: Max number of bytes to accept from EC
|
||||
* @result: EC's response to the command (separate from communication failure)
|
||||
*/
|
||||
struct cros_ec_msg {
|
||||
u8 version;
|
||||
u8 cmd;
|
||||
uint8_t *out_buf;
|
||||
int out_len;
|
||||
uint8_t *in_buf;
|
||||
int in_len;
|
||||
struct cros_ec_command {
|
||||
uint32_t version;
|
||||
uint32_t command;
|
||||
uint8_t *outdata;
|
||||
uint32_t outsize;
|
||||
uint8_t *indata;
|
||||
uint32_t insize;
|
||||
uint32_t result;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cros_ec_device - Information about a ChromeOS EC device
|
||||
*
|
||||
* @name: Name of this EC interface
|
||||
* @ec_name: name of EC device (e.g. 'chromeos-ec')
|
||||
* @phys_name: name of physical comms layer (e.g. 'i2c-4')
|
||||
* @dev: Device pointer
|
||||
* @was_wake_device: true if this device was set to wake the system from
|
||||
* sleep at the last suspend
|
||||
* @cmd_xfer: send command to EC and get response
|
||||
* Returns the number of bytes received if the communication succeeded, but
|
||||
* that doesn't mean the EC was happy with the command. The caller
|
||||
* should check msg.result for the EC's result code.
|
||||
*
|
||||
* @priv: Private data
|
||||
* @irq: Interrupt to use
|
||||
* @din: input buffer (from EC)
|
||||
* @dout: output buffer (to EC)
|
||||
* @din: input buffer (for data from EC)
|
||||
* @dout: output buffer (for data to EC)
|
||||
* \note
|
||||
* These two buffers will always be dword-aligned and include enough
|
||||
* space for up to 7 word-alignment bytes also, so we can ensure that
|
||||
* the body of the message is always dword-aligned (64-bit).
|
||||
*
|
||||
* We use this alignment to keep ARM and x86 happy. Probably word
|
||||
* alignment would be OK, there might be a small performance advantage
|
||||
* to using dword.
|
||||
* @din_size: size of din buffer
|
||||
* @dout_size: size of dout buffer
|
||||
* @command_send: send a command
|
||||
* @command_recv: receive a command
|
||||
* @ec_name: name of EC device (e.g. 'chromeos-ec')
|
||||
* @phys_name: name of physical comms layer (e.g. 'i2c-4')
|
||||
* @din_size: size of din buffer to allocate (zero to use static din)
|
||||
* @dout_size: size of dout buffer to allocate (zero to use static dout)
|
||||
* @parent: pointer to parent device (e.g. i2c or spi device)
|
||||
* @dev: Device pointer
|
||||
* dev_lock: Lock to prevent concurrent access
|
||||
* @wake_enabled: true if this device can wake the system from sleep
|
||||
* @was_wake_device: true if this device was set to wake the system from
|
||||
* sleep at the last suspend
|
||||
* @event_notifier: interrupt event notifier for transport devices
|
||||
* @lock: one transaction at a time
|
||||
*/
|
||||
struct cros_ec_device {
|
||||
const char *name;
|
||||
|
||||
/* These are used by other drivers that want to talk to the EC */
|
||||
const char *ec_name;
|
||||
const char *phys_name;
|
||||
struct device *dev;
|
||||
bool was_wake_device;
|
||||
struct class *cros_class;
|
||||
int (*cmd_xfer)(struct cros_ec_device *ec,
|
||||
struct cros_ec_command *msg);
|
||||
|
||||
/* These are used to implement the platform-specific interface */
|
||||
void *priv;
|
||||
int irq;
|
||||
uint8_t *din;
|
||||
uint8_t *dout;
|
||||
int din_size;
|
||||
int dout_size;
|
||||
int (*command_send)(struct cros_ec_device *ec,
|
||||
uint16_t cmd, void *out_buf, int out_len);
|
||||
int (*command_recv)(struct cros_ec_device *ec,
|
||||
uint16_t cmd, void *in_buf, int in_len);
|
||||
int (*command_sendrecv)(struct cros_ec_device *ec,
|
||||
uint16_t cmd, void *out_buf, int out_len,
|
||||
void *in_buf, int in_len);
|
||||
int (*command_xfer)(struct cros_ec_device *ec,
|
||||
struct cros_ec_msg *msg);
|
||||
|
||||
const char *ec_name;
|
||||
const char *phys_name;
|
||||
struct device *parent;
|
||||
|
||||
/* These are --private-- fields - do not assign */
|
||||
struct device *dev;
|
||||
struct mutex dev_lock;
|
||||
bool wake_enabled;
|
||||
bool was_wake_device;
|
||||
struct blocking_notifier_head event_notifier;
|
||||
struct mutex lock;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -143,13 +138,24 @@ int cros_ec_resume(struct cros_ec_device *ec_dev);
|
||||
* @msg: Message to write
|
||||
*/
|
||||
int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
|
||||
struct cros_ec_msg *msg);
|
||||
struct cros_ec_command *msg);
|
||||
|
||||
/**
|
||||
* cros_ec_check_result - Check ec_msg->result
|
||||
*
|
||||
* This is used by ChromeOS EC drivers to check the ec_msg->result for
|
||||
* errors and to warn about them.
|
||||
*
|
||||
* @ec_dev: EC device
|
||||
* @msg: Message to check
|
||||
*/
|
||||
int cros_ec_check_result(struct cros_ec_device *ec_dev,
|
||||
struct cros_ec_command *msg);
|
||||
|
||||
/**
|
||||
* cros_ec_remove - Remove a ChromeOS EC
|
||||
*
|
||||
* Call this to deregister a ChromeOS EC. After this you should call
|
||||
* cros_ec_free().
|
||||
* Call this to deregister a ChromeOS EC, then clean up any private data.
|
||||
*
|
||||
* @ec_dev: Device to register
|
||||
* @return 0 if ok, -ve on error
|
||||
|
||||
@@ -34,7 +34,8 @@ enum da9063_models {
|
||||
};
|
||||
|
||||
enum da9063_variant_codes {
|
||||
PMIC_DA9063_BB = 0x5
|
||||
PMIC_DA9063_AD = 0x3,
|
||||
PMIC_DA9063_BB = 0x5,
|
||||
};
|
||||
|
||||
/* Interrupts */
|
||||
|
||||
@@ -104,16 +104,27 @@
|
||||
#define DA9063_REG_COUNT_D 0x43
|
||||
#define DA9063_REG_COUNT_MO 0x44
|
||||
#define DA9063_REG_COUNT_Y 0x45
|
||||
#define DA9063_REG_ALARM_S 0x46
|
||||
#define DA9063_REG_ALARM_MI 0x47
|
||||
#define DA9063_REG_ALARM_H 0x48
|
||||
#define DA9063_REG_ALARM_D 0x49
|
||||
#define DA9063_REG_ALARM_MO 0x4A
|
||||
#define DA9063_REG_ALARM_Y 0x4B
|
||||
#define DA9063_REG_SECOND_A 0x4C
|
||||
#define DA9063_REG_SECOND_B 0x4D
|
||||
#define DA9063_REG_SECOND_C 0x4E
|
||||
#define DA9063_REG_SECOND_D 0x4F
|
||||
|
||||
#define DA9063_AD_REG_ALARM_MI 0x46
|
||||
#define DA9063_AD_REG_ALARM_H 0x47
|
||||
#define DA9063_AD_REG_ALARM_D 0x48
|
||||
#define DA9063_AD_REG_ALARM_MO 0x49
|
||||
#define DA9063_AD_REG_ALARM_Y 0x4A
|
||||
#define DA9063_AD_REG_SECOND_A 0x4B
|
||||
#define DA9063_AD_REG_SECOND_B 0x4C
|
||||
#define DA9063_AD_REG_SECOND_C 0x4D
|
||||
#define DA9063_AD_REG_SECOND_D 0x4E
|
||||
|
||||
#define DA9063_BB_REG_ALARM_S 0x46
|
||||
#define DA9063_BB_REG_ALARM_MI 0x47
|
||||
#define DA9063_BB_REG_ALARM_H 0x48
|
||||
#define DA9063_BB_REG_ALARM_D 0x49
|
||||
#define DA9063_BB_REG_ALARM_MO 0x4A
|
||||
#define DA9063_BB_REG_ALARM_Y 0x4B
|
||||
#define DA9063_BB_REG_SECOND_A 0x4C
|
||||
#define DA9063_BB_REG_SECOND_B 0x4D
|
||||
#define DA9063_BB_REG_SECOND_C 0x4E
|
||||
#define DA9063_BB_REG_SECOND_D 0x4F
|
||||
|
||||
/* Sequencer Control Registers */
|
||||
#define DA9063_REG_SEQ 0x81
|
||||
@@ -223,37 +234,67 @@
|
||||
#define DA9063_REG_CONFIG_J 0x10F
|
||||
#define DA9063_REG_CONFIG_K 0x110
|
||||
#define DA9063_REG_CONFIG_L 0x111
|
||||
#define DA9063_REG_CONFIG_M 0x112
|
||||
#define DA9063_REG_CONFIG_N 0x113
|
||||
|
||||
#define DA9063_REG_MON_REG_1 0x114
|
||||
#define DA9063_REG_MON_REG_2 0x115
|
||||
#define DA9063_REG_MON_REG_3 0x116
|
||||
#define DA9063_REG_MON_REG_4 0x117
|
||||
#define DA9063_REG_MON_REG_5 0x11E
|
||||
#define DA9063_REG_MON_REG_6 0x11F
|
||||
#define DA9063_REG_TRIM_CLDR 0x120
|
||||
#define DA9063_AD_REG_MON_REG_1 0x112
|
||||
#define DA9063_AD_REG_MON_REG_2 0x113
|
||||
#define DA9063_AD_REG_MON_REG_3 0x114
|
||||
#define DA9063_AD_REG_MON_REG_4 0x115
|
||||
#define DA9063_AD_REG_MON_REG_5 0x116
|
||||
#define DA9063_AD_REG_MON_REG_6 0x117
|
||||
#define DA9063_AD_REG_TRIM_CLDR 0x118
|
||||
|
||||
#define DA9063_AD_REG_GP_ID_0 0x119
|
||||
#define DA9063_AD_REG_GP_ID_1 0x11A
|
||||
#define DA9063_AD_REG_GP_ID_2 0x11B
|
||||
#define DA9063_AD_REG_GP_ID_3 0x11C
|
||||
#define DA9063_AD_REG_GP_ID_4 0x11D
|
||||
#define DA9063_AD_REG_GP_ID_5 0x11E
|
||||
#define DA9063_AD_REG_GP_ID_6 0x11F
|
||||
#define DA9063_AD_REG_GP_ID_7 0x120
|
||||
#define DA9063_AD_REG_GP_ID_8 0x121
|
||||
#define DA9063_AD_REG_GP_ID_9 0x122
|
||||
#define DA9063_AD_REG_GP_ID_10 0x123
|
||||
#define DA9063_AD_REG_GP_ID_11 0x124
|
||||
#define DA9063_AD_REG_GP_ID_12 0x125
|
||||
#define DA9063_AD_REG_GP_ID_13 0x126
|
||||
#define DA9063_AD_REG_GP_ID_14 0x127
|
||||
#define DA9063_AD_REG_GP_ID_15 0x128
|
||||
#define DA9063_AD_REG_GP_ID_16 0x129
|
||||
#define DA9063_AD_REG_GP_ID_17 0x12A
|
||||
#define DA9063_AD_REG_GP_ID_18 0x12B
|
||||
#define DA9063_AD_REG_GP_ID_19 0x12C
|
||||
|
||||
#define DA9063_BB_REG_CONFIG_M 0x112
|
||||
#define DA9063_BB_REG_CONFIG_N 0x113
|
||||
|
||||
#define DA9063_BB_REG_MON_REG_1 0x114
|
||||
#define DA9063_BB_REG_MON_REG_2 0x115
|
||||
#define DA9063_BB_REG_MON_REG_3 0x116
|
||||
#define DA9063_BB_REG_MON_REG_4 0x117
|
||||
#define DA9063_BB_REG_MON_REG_5 0x11E
|
||||
#define DA9063_BB_REG_MON_REG_6 0x11F
|
||||
#define DA9063_BB_REG_TRIM_CLDR 0x120
|
||||
/* General Purpose Registers */
|
||||
#define DA9063_REG_GP_ID_0 0x121
|
||||
#define DA9063_REG_GP_ID_1 0x122
|
||||
#define DA9063_REG_GP_ID_2 0x123
|
||||
#define DA9063_REG_GP_ID_3 0x124
|
||||
#define DA9063_REG_GP_ID_4 0x125
|
||||
#define DA9063_REG_GP_ID_5 0x126
|
||||
#define DA9063_REG_GP_ID_6 0x127
|
||||
#define DA9063_REG_GP_ID_7 0x128
|
||||
#define DA9063_REG_GP_ID_8 0x129
|
||||
#define DA9063_REG_GP_ID_9 0x12A
|
||||
#define DA9063_REG_GP_ID_10 0x12B
|
||||
#define DA9063_REG_GP_ID_11 0x12C
|
||||
#define DA9063_REG_GP_ID_12 0x12D
|
||||
#define DA9063_REG_GP_ID_13 0x12E
|
||||
#define DA9063_REG_GP_ID_14 0x12F
|
||||
#define DA9063_REG_GP_ID_15 0x130
|
||||
#define DA9063_REG_GP_ID_16 0x131
|
||||
#define DA9063_REG_GP_ID_17 0x132
|
||||
#define DA9063_REG_GP_ID_18 0x133
|
||||
#define DA9063_REG_GP_ID_19 0x134
|
||||
#define DA9063_BB_REG_GP_ID_0 0x121
|
||||
#define DA9063_BB_REG_GP_ID_1 0x122
|
||||
#define DA9063_BB_REG_GP_ID_2 0x123
|
||||
#define DA9063_BB_REG_GP_ID_3 0x124
|
||||
#define DA9063_BB_REG_GP_ID_4 0x125
|
||||
#define DA9063_BB_REG_GP_ID_5 0x126
|
||||
#define DA9063_BB_REG_GP_ID_6 0x127
|
||||
#define DA9063_BB_REG_GP_ID_7 0x128
|
||||
#define DA9063_BB_REG_GP_ID_8 0x129
|
||||
#define DA9063_BB_REG_GP_ID_9 0x12A
|
||||
#define DA9063_BB_REG_GP_ID_10 0x12B
|
||||
#define DA9063_BB_REG_GP_ID_11 0x12C
|
||||
#define DA9063_BB_REG_GP_ID_12 0x12D
|
||||
#define DA9063_BB_REG_GP_ID_13 0x12E
|
||||
#define DA9063_BB_REG_GP_ID_14 0x12F
|
||||
#define DA9063_BB_REG_GP_ID_15 0x130
|
||||
#define DA9063_BB_REG_GP_ID_16 0x131
|
||||
#define DA9063_BB_REG_GP_ID_17 0x132
|
||||
#define DA9063_BB_REG_GP_ID_18 0x133
|
||||
#define DA9063_BB_REG_GP_ID_19 0x134
|
||||
|
||||
/* Chip ID and variant */
|
||||
#define DA9063_REG_CHIP_ID 0x181
|
||||
@@ -404,10 +445,10 @@
|
||||
/* DA9063_REG_CONTROL_B (addr=0x0F) */
|
||||
#define DA9063_CHG_SEL 0x01
|
||||
#define DA9063_WATCHDOG_PD 0x02
|
||||
#define DA9063_RESET_BLINKING 0x04
|
||||
#define DA9063_BB_RESET_BLINKING 0x04
|
||||
#define DA9063_NRES_MODE 0x08
|
||||
#define DA9063_NONKEY_LOCK 0x10
|
||||
#define DA9063_BUCK_SLOWSTART 0x80
|
||||
#define DA9063_BB_BUCK_SLOWSTART 0x80
|
||||
|
||||
/* DA9063_REG_CONTROL_C (addr=0x10) */
|
||||
#define DA9063_DEBOUNCING_MASK 0x07
|
||||
@@ -467,7 +508,7 @@
|
||||
#define DA9063_GPADC_PAUSE 0x02
|
||||
#define DA9063_PMIF_DIS 0x04
|
||||
#define DA9063_HS2WIRE_DIS 0x08
|
||||
#define DA9063_CLDR_PAUSE 0x10
|
||||
#define DA9063_BB_CLDR_PAUSE 0x10
|
||||
#define DA9063_BBAT_DIS 0x20
|
||||
#define DA9063_OUT_32K_PAUSE 0x40
|
||||
#define DA9063_PMCONT_DIS 0x80
|
||||
@@ -844,7 +885,7 @@
|
||||
#define DA9063_MONITOR 0x40
|
||||
|
||||
/* DA9063_REG_ALARM_S (addr=0x46) */
|
||||
#define DA9063_ALARM_S_MASK 0x3F
|
||||
#define DA9063_BB_ALARM_S_MASK 0x3F
|
||||
#define DA9063_ALARM_STATUS_ALARM 0x80
|
||||
#define DA9063_ALARM_STATUS_TICK 0x40
|
||||
/* DA9063_REG_ALARM_MI (addr=0x47) */
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* intel_soc_pmic.h - Intel SoC PMIC Driver
|
||||
*
|
||||
* Copyright (C) 2012-2014 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version
|
||||
* 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Author: Yang, Bin <bin.yang@intel.com>
|
||||
* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
|
||||
*/
|
||||
|
||||
#ifndef __INTEL_SOC_PMIC_H__
|
||||
#define __INTEL_SOC_PMIC_H__
|
||||
|
||||
#include <linux/regmap.h>
|
||||
|
||||
struct intel_soc_pmic {
|
||||
int irq;
|
||||
struct regmap *regmap;
|
||||
struct regmap_irq_chip_data *irq_chip_data;
|
||||
};
|
||||
|
||||
#endif /* __INTEL_SOC_PMIC_H__ */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* max77686-private.h - Voltage regulator driver for the Maxim 77686
|
||||
* max77686-private.h - Voltage regulator driver for the Maxim 77686/802
|
||||
*
|
||||
* Copyright (C) 2012 Samsung Electrnoics
|
||||
* Chiwoong Byun <woong.byun@samsung.com>
|
||||
@@ -28,6 +28,7 @@
|
||||
|
||||
#define MAX77686_REG_INVALID (0xff)
|
||||
|
||||
/* MAX77686 PMIC registers */
|
||||
enum max77686_pmic_reg {
|
||||
MAX77686_REG_DEVICE_ID = 0x00,
|
||||
MAX77686_REG_INTSRC = 0x01,
|
||||
@@ -181,8 +182,209 @@ enum max77686_rtc_reg {
|
||||
MAX77686_ALARM2_DATE = 0x1B,
|
||||
};
|
||||
|
||||
#define MAX77686_IRQSRC_PMIC (0)
|
||||
#define MAX77686_IRQSRC_RTC (1 << 0)
|
||||
/* MAX77802 PMIC registers */
|
||||
enum max77802_pmic_reg {
|
||||
MAX77802_REG_DEVICE_ID = 0x00,
|
||||
MAX77802_REG_INTSRC = 0x01,
|
||||
MAX77802_REG_INT1 = 0x02,
|
||||
MAX77802_REG_INT2 = 0x03,
|
||||
|
||||
MAX77802_REG_INT1MSK = 0x04,
|
||||
MAX77802_REG_INT2MSK = 0x05,
|
||||
|
||||
MAX77802_REG_STATUS1 = 0x06,
|
||||
MAX77802_REG_STATUS2 = 0x07,
|
||||
|
||||
MAX77802_REG_PWRON = 0x08,
|
||||
/* Reserved: 0x09 */
|
||||
MAX77802_REG_MRSTB = 0x0A,
|
||||
MAX77802_REG_EPWRHOLD = 0x0B,
|
||||
/* Reserved: 0x0C-0x0D */
|
||||
MAX77802_REG_BOOSTCTRL = 0x0E,
|
||||
MAX77802_REG_BOOSTOUT = 0x0F,
|
||||
|
||||
MAX77802_REG_BUCK1CTRL = 0x10,
|
||||
MAX77802_REG_BUCK1DVS1 = 0x11,
|
||||
MAX77802_REG_BUCK1DVS2 = 0x12,
|
||||
MAX77802_REG_BUCK1DVS3 = 0x13,
|
||||
MAX77802_REG_BUCK1DVS4 = 0x14,
|
||||
MAX77802_REG_BUCK1DVS5 = 0x15,
|
||||
MAX77802_REG_BUCK1DVS6 = 0x16,
|
||||
MAX77802_REG_BUCK1DVS7 = 0x17,
|
||||
MAX77802_REG_BUCK1DVS8 = 0x18,
|
||||
/* Reserved: 0x19 */
|
||||
MAX77802_REG_BUCK2CTRL1 = 0x1A,
|
||||
MAX77802_REG_BUCK2CTRL2 = 0x1B,
|
||||
MAX77802_REG_BUCK2PHTRAN = 0x1C,
|
||||
MAX77802_REG_BUCK2DVS1 = 0x1D,
|
||||
MAX77802_REG_BUCK2DVS2 = 0x1E,
|
||||
MAX77802_REG_BUCK2DVS3 = 0x1F,
|
||||
MAX77802_REG_BUCK2DVS4 = 0x20,
|
||||
MAX77802_REG_BUCK2DVS5 = 0x21,
|
||||
MAX77802_REG_BUCK2DVS6 = 0x22,
|
||||
MAX77802_REG_BUCK2DVS7 = 0x23,
|
||||
MAX77802_REG_BUCK2DVS8 = 0x24,
|
||||
/* Reserved: 0x25-0x26 */
|
||||
MAX77802_REG_BUCK3CTRL1 = 0x27,
|
||||
MAX77802_REG_BUCK3DVS1 = 0x28,
|
||||
MAX77802_REG_BUCK3DVS2 = 0x29,
|
||||
MAX77802_REG_BUCK3DVS3 = 0x2A,
|
||||
MAX77802_REG_BUCK3DVS4 = 0x2B,
|
||||
MAX77802_REG_BUCK3DVS5 = 0x2C,
|
||||
MAX77802_REG_BUCK3DVS6 = 0x2D,
|
||||
MAX77802_REG_BUCK3DVS7 = 0x2E,
|
||||
MAX77802_REG_BUCK3DVS8 = 0x2F,
|
||||
/* Reserved: 0x30-0x36 */
|
||||
MAX77802_REG_BUCK4CTRL1 = 0x37,
|
||||
MAX77802_REG_BUCK4DVS1 = 0x38,
|
||||
MAX77802_REG_BUCK4DVS2 = 0x39,
|
||||
MAX77802_REG_BUCK4DVS3 = 0x3A,
|
||||
MAX77802_REG_BUCK4DVS4 = 0x3B,
|
||||
MAX77802_REG_BUCK4DVS5 = 0x3C,
|
||||
MAX77802_REG_BUCK4DVS6 = 0x3D,
|
||||
MAX77802_REG_BUCK4DVS7 = 0x3E,
|
||||
MAX77802_REG_BUCK4DVS8 = 0x3F,
|
||||
/* Reserved: 0x40 */
|
||||
MAX77802_REG_BUCK5CTRL = 0x41,
|
||||
MAX77802_REG_BUCK5OUT = 0x42,
|
||||
/* Reserved: 0x43 */
|
||||
MAX77802_REG_BUCK6CTRL = 0x44,
|
||||
MAX77802_REG_BUCK6DVS1 = 0x45,
|
||||
MAX77802_REG_BUCK6DVS2 = 0x46,
|
||||
MAX77802_REG_BUCK6DVS3 = 0x47,
|
||||
MAX77802_REG_BUCK6DVS4 = 0x48,
|
||||
MAX77802_REG_BUCK6DVS5 = 0x49,
|
||||
MAX77802_REG_BUCK6DVS6 = 0x4A,
|
||||
MAX77802_REG_BUCK6DVS7 = 0x4B,
|
||||
MAX77802_REG_BUCK6DVS8 = 0x4C,
|
||||
/* Reserved: 0x4D */
|
||||
MAX77802_REG_BUCK7CTRL = 0x4E,
|
||||
MAX77802_REG_BUCK7OUT = 0x4F,
|
||||
/* Reserved: 0x50 */
|
||||
MAX77802_REG_BUCK8CTRL = 0x51,
|
||||
MAX77802_REG_BUCK8OUT = 0x52,
|
||||
/* Reserved: 0x53 */
|
||||
MAX77802_REG_BUCK9CTRL = 0x54,
|
||||
MAX77802_REG_BUCK9OUT = 0x55,
|
||||
/* Reserved: 0x56 */
|
||||
MAX77802_REG_BUCK10CTRL = 0x57,
|
||||
MAX77802_REG_BUCK10OUT = 0x58,
|
||||
|
||||
/* Reserved: 0x59-0x5F */
|
||||
|
||||
MAX77802_REG_LDO1CTRL1 = 0x60,
|
||||
MAX77802_REG_LDO2CTRL1 = 0x61,
|
||||
MAX77802_REG_LDO3CTRL1 = 0x62,
|
||||
MAX77802_REG_LDO4CTRL1 = 0x63,
|
||||
MAX77802_REG_LDO5CTRL1 = 0x64,
|
||||
MAX77802_REG_LDO6CTRL1 = 0x65,
|
||||
MAX77802_REG_LDO7CTRL1 = 0x66,
|
||||
MAX77802_REG_LDO8CTRL1 = 0x67,
|
||||
MAX77802_REG_LDO9CTRL1 = 0x68,
|
||||
MAX77802_REG_LDO10CTRL1 = 0x69,
|
||||
MAX77802_REG_LDO11CTRL1 = 0x6A,
|
||||
MAX77802_REG_LDO12CTRL1 = 0x6B,
|
||||
MAX77802_REG_LDO13CTRL1 = 0x6C,
|
||||
MAX77802_REG_LDO14CTRL1 = 0x6D,
|
||||
MAX77802_REG_LDO15CTRL1 = 0x6E,
|
||||
/* Reserved: 0x6F */
|
||||
MAX77802_REG_LDO17CTRL1 = 0x70,
|
||||
MAX77802_REG_LDO18CTRL1 = 0x71,
|
||||
MAX77802_REG_LDO19CTRL1 = 0x72,
|
||||
MAX77802_REG_LDO20CTRL1 = 0x73,
|
||||
MAX77802_REG_LDO21CTRL1 = 0x74,
|
||||
MAX77802_REG_LDO22CTRL1 = 0x75,
|
||||
MAX77802_REG_LDO23CTRL1 = 0x76,
|
||||
MAX77802_REG_LDO24CTRL1 = 0x77,
|
||||
MAX77802_REG_LDO25CTRL1 = 0x78,
|
||||
MAX77802_REG_LDO26CTRL1 = 0x79,
|
||||
MAX77802_REG_LDO27CTRL1 = 0x7A,
|
||||
MAX77802_REG_LDO28CTRL1 = 0x7B,
|
||||
MAX77802_REG_LDO29CTRL1 = 0x7C,
|
||||
MAX77802_REG_LDO30CTRL1 = 0x7D,
|
||||
/* Reserved: 0x7E */
|
||||
MAX77802_REG_LDO32CTRL1 = 0x7F,
|
||||
MAX77802_REG_LDO33CTRL1 = 0x80,
|
||||
MAX77802_REG_LDO34CTRL1 = 0x81,
|
||||
MAX77802_REG_LDO35CTRL1 = 0x82,
|
||||
/* Reserved: 0x83-0x8F */
|
||||
MAX77802_REG_LDO1CTRL2 = 0x90,
|
||||
MAX77802_REG_LDO2CTRL2 = 0x91,
|
||||
MAX77802_REG_LDO3CTRL2 = 0x92,
|
||||
MAX77802_REG_LDO4CTRL2 = 0x93,
|
||||
MAX77802_REG_LDO5CTRL2 = 0x94,
|
||||
MAX77802_REG_LDO6CTRL2 = 0x95,
|
||||
MAX77802_REG_LDO7CTRL2 = 0x96,
|
||||
MAX77802_REG_LDO8CTRL2 = 0x97,
|
||||
MAX77802_REG_LDO9CTRL2 = 0x98,
|
||||
MAX77802_REG_LDO10CTRL2 = 0x99,
|
||||
MAX77802_REG_LDO11CTRL2 = 0x9A,
|
||||
MAX77802_REG_LDO12CTRL2 = 0x9B,
|
||||
MAX77802_REG_LDO13CTRL2 = 0x9C,
|
||||
MAX77802_REG_LDO14CTRL2 = 0x9D,
|
||||
MAX77802_REG_LDO15CTRL2 = 0x9E,
|
||||
/* Reserved: 0x9F */
|
||||
MAX77802_REG_LDO17CTRL2 = 0xA0,
|
||||
MAX77802_REG_LDO18CTRL2 = 0xA1,
|
||||
MAX77802_REG_LDO19CTRL2 = 0xA2,
|
||||
MAX77802_REG_LDO20CTRL2 = 0xA3,
|
||||
MAX77802_REG_LDO21CTRL2 = 0xA4,
|
||||
MAX77802_REG_LDO22CTRL2 = 0xA5,
|
||||
MAX77802_REG_LDO23CTRL2 = 0xA6,
|
||||
MAX77802_REG_LDO24CTRL2 = 0xA7,
|
||||
MAX77802_REG_LDO25CTRL2 = 0xA8,
|
||||
MAX77802_REG_LDO26CTRL2 = 0xA9,
|
||||
MAX77802_REG_LDO27CTRL2 = 0xAA,
|
||||
MAX77802_REG_LDO28CTRL2 = 0xAB,
|
||||
MAX77802_REG_LDO29CTRL2 = 0xAC,
|
||||
MAX77802_REG_LDO30CTRL2 = 0xAD,
|
||||
/* Reserved: 0xAE */
|
||||
MAX77802_REG_LDO32CTRL2 = 0xAF,
|
||||
MAX77802_REG_LDO33CTRL2 = 0xB0,
|
||||
MAX77802_REG_LDO34CTRL2 = 0xB1,
|
||||
MAX77802_REG_LDO35CTRL2 = 0xB2,
|
||||
/* Reserved: 0xB3 */
|
||||
|
||||
MAX77802_REG_BBAT_CHG = 0xB4,
|
||||
MAX77802_REG_32KHZ = 0xB5,
|
||||
|
||||
MAX77802_REG_PMIC_END = 0xB6,
|
||||
};
|
||||
|
||||
enum max77802_rtc_reg {
|
||||
MAX77802_RTC_INT = 0xC0,
|
||||
MAX77802_RTC_INTM = 0xC1,
|
||||
MAX77802_RTC_CONTROLM = 0xC2,
|
||||
MAX77802_RTC_CONTROL = 0xC3,
|
||||
MAX77802_RTC_UPDATE0 = 0xC4,
|
||||
MAX77802_RTC_UPDATE1 = 0xC5,
|
||||
MAX77802_WTSR_SMPL_CNTL = 0xC6,
|
||||
MAX77802_RTC_SEC = 0xC7,
|
||||
MAX77802_RTC_MIN = 0xC8,
|
||||
MAX77802_RTC_HOUR = 0xC9,
|
||||
MAX77802_RTC_WEEKDAY = 0xCA,
|
||||
MAX77802_RTC_MONTH = 0xCB,
|
||||
MAX77802_RTC_YEAR = 0xCC,
|
||||
MAX77802_RTC_DATE = 0xCD,
|
||||
MAX77802_RTC_AE1 = 0xCE,
|
||||
MAX77802_ALARM1_SEC = 0xCF,
|
||||
MAX77802_ALARM1_MIN = 0xD0,
|
||||
MAX77802_ALARM1_HOUR = 0xD1,
|
||||
MAX77802_ALARM1_WEEKDAY = 0xD2,
|
||||
MAX77802_ALARM1_MONTH = 0xD3,
|
||||
MAX77802_ALARM1_YEAR = 0xD4,
|
||||
MAX77802_ALARM1_DATE = 0xD5,
|
||||
MAX77802_RTC_AE2 = 0xD6,
|
||||
MAX77802_ALARM2_SEC = 0xD7,
|
||||
MAX77802_ALARM2_MIN = 0xD8,
|
||||
MAX77802_ALARM2_HOUR = 0xD9,
|
||||
MAX77802_ALARM2_WEEKDAY = 0xDA,
|
||||
MAX77802_ALARM2_MONTH = 0xDB,
|
||||
MAX77802_ALARM2_YEAR = 0xDC,
|
||||
MAX77802_ALARM2_DATE = 0xDD,
|
||||
|
||||
MAX77802_RTC_END = 0xDF,
|
||||
};
|
||||
|
||||
enum max77686_irq_source {
|
||||
PMIC_INT1 = 0,
|
||||
@@ -205,30 +407,46 @@ enum max77686_irq {
|
||||
MAX77686_PMICIRQ_140C,
|
||||
MAX77686_PMICIRQ_120C,
|
||||
|
||||
MAX77686_RTCIRQ_RTC60S,
|
||||
MAX77686_RTCIRQ_RTC60S = 0,
|
||||
MAX77686_RTCIRQ_RTCA1,
|
||||
MAX77686_RTCIRQ_RTCA2,
|
||||
MAX77686_RTCIRQ_SMPL,
|
||||
MAX77686_RTCIRQ_RTC1S,
|
||||
MAX77686_RTCIRQ_WTSR,
|
||||
|
||||
MAX77686_IRQ_NR,
|
||||
};
|
||||
|
||||
#define MAX77686_INT1_PWRONF_MSK BIT(0)
|
||||
#define MAX77686_INT1_PWRONR_MSK BIT(1)
|
||||
#define MAX77686_INT1_JIGONBF_MSK BIT(2)
|
||||
#define MAX77686_INT1_JIGONBR_MSK BIT(3)
|
||||
#define MAX77686_INT1_ACOKBF_MSK BIT(4)
|
||||
#define MAX77686_INT1_ACOKBR_MSK BIT(5)
|
||||
#define MAX77686_INT1_ONKEY1S_MSK BIT(6)
|
||||
#define MAX77686_INT1_MRSTB_MSK BIT(7)
|
||||
|
||||
#define MAX77686_INT2_140C_MSK BIT(0)
|
||||
#define MAX77686_INT2_120C_MSK BIT(1)
|
||||
|
||||
#define MAX77686_RTCINT_RTC60S_MSK BIT(0)
|
||||
#define MAX77686_RTCINT_RTCA1_MSK BIT(1)
|
||||
#define MAX77686_RTCINT_RTCA2_MSK BIT(2)
|
||||
#define MAX77686_RTCINT_SMPL_MSK BIT(3)
|
||||
#define MAX77686_RTCINT_RTC1S_MSK BIT(4)
|
||||
#define MAX77686_RTCINT_WTSR_MSK BIT(5)
|
||||
|
||||
struct max77686_dev {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
|
||||
struct i2c_client *rtc; /* slave addr 0x0c */
|
||||
|
||||
int type;
|
||||
unsigned long type;
|
||||
|
||||
struct regmap *regmap; /* regmap for mfd */
|
||||
struct regmap *rtc_regmap; /* regmap for rtc */
|
||||
|
||||
struct irq_domain *irq_domain;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct regmap_irq_chip_data *rtc_irq_data;
|
||||
|
||||
int irq;
|
||||
int irq_gpio;
|
||||
bool wakeup;
|
||||
struct mutex irqlock;
|
||||
int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
|
||||
@@ -237,6 +455,7 @@ struct max77686_dev {
|
||||
|
||||
enum max77686_types {
|
||||
TYPE_MAX77686,
|
||||
TYPE_MAX77802,
|
||||
};
|
||||
|
||||
extern int max77686_irq_init(struct max77686_dev *max77686);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* max77686.h - Driver for the Maxim 77686
|
||||
* max77686.h - Driver for the Maxim 77686/802
|
||||
*
|
||||
* Copyright (C) 2012 Samsung Electrnoics
|
||||
* Chiwoong Byun <woong.byun@samsung.com>
|
||||
@@ -71,6 +71,54 @@ enum max77686_regulators {
|
||||
MAX77686_REG_MAX,
|
||||
};
|
||||
|
||||
/* MAX77802 regulator IDs */
|
||||
enum max77802_regulators {
|
||||
MAX77802_BUCK1 = 0,
|
||||
MAX77802_BUCK2,
|
||||
MAX77802_BUCK3,
|
||||
MAX77802_BUCK4,
|
||||
MAX77802_BUCK5,
|
||||
MAX77802_BUCK6,
|
||||
MAX77802_BUCK7,
|
||||
MAX77802_BUCK8,
|
||||
MAX77802_BUCK9,
|
||||
MAX77802_BUCK10,
|
||||
MAX77802_LDO1,
|
||||
MAX77802_LDO2,
|
||||
MAX77802_LDO3,
|
||||
MAX77802_LDO4,
|
||||
MAX77802_LDO5,
|
||||
MAX77802_LDO6,
|
||||
MAX77802_LDO7,
|
||||
MAX77802_LDO8,
|
||||
MAX77802_LDO9,
|
||||
MAX77802_LDO10,
|
||||
MAX77802_LDO11,
|
||||
MAX77802_LDO12,
|
||||
MAX77802_LDO13,
|
||||
MAX77802_LDO14,
|
||||
MAX77802_LDO15,
|
||||
MAX77802_LDO17,
|
||||
MAX77802_LDO18,
|
||||
MAX77802_LDO19,
|
||||
MAX77802_LDO20,
|
||||
MAX77802_LDO21,
|
||||
MAX77802_LDO23,
|
||||
MAX77802_LDO24,
|
||||
MAX77802_LDO25,
|
||||
MAX77802_LDO26,
|
||||
MAX77802_LDO27,
|
||||
MAX77802_LDO28,
|
||||
MAX77802_LDO29,
|
||||
MAX77802_LDO30,
|
||||
MAX77802_LDO32,
|
||||
MAX77802_LDO33,
|
||||
MAX77802_LDO34,
|
||||
MAX77802_LDO35,
|
||||
|
||||
MAX77802_REG_MAX,
|
||||
};
|
||||
|
||||
struct max77686_regulator_data {
|
||||
int id;
|
||||
struct regulator_init_data *initdata;
|
||||
@@ -83,14 +131,19 @@ enum max77686_opmode {
|
||||
MAX77686_OPMODE_STANDBY,
|
||||
};
|
||||
|
||||
enum max77802_opmode {
|
||||
MAX77802_OPMODE_OFF,
|
||||
MAX77802_OPMODE_STANDBY,
|
||||
MAX77802_OPMODE_LP,
|
||||
MAX77802_OPMODE_NORMAL,
|
||||
};
|
||||
|
||||
struct max77686_opmode_data {
|
||||
int id;
|
||||
int mode;
|
||||
};
|
||||
|
||||
struct max77686_platform_data {
|
||||
/* IRQ */
|
||||
int irq_gpio;
|
||||
int ono;
|
||||
int wakeup;
|
||||
|
||||
|
||||
@@ -86,6 +86,5 @@
|
||||
#define MC13783_IRQ_HSL 43
|
||||
#define MC13783_IRQ_ALSPTH 44
|
||||
#define MC13783_IRQ_AHSSHORT 45
|
||||
#define MC13783_NUM_IRQ MC13XXX_NUM_IRQ
|
||||
|
||||
#endif /* ifndef __LINUX_MFD_MC13783_H */
|
||||
|
||||
@@ -23,15 +23,10 @@ int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
|
||||
|
||||
int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
|
||||
irq_handler_t handler, const char *name, void *dev);
|
||||
int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
|
||||
irq_handler_t handler, const char *name, void *dev);
|
||||
int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev);
|
||||
|
||||
int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq);
|
||||
int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq);
|
||||
int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
|
||||
int *enabled, int *pending);
|
||||
int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
|
||||
|
||||
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
|
||||
|
||||
@@ -39,6 +34,22 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
|
||||
unsigned int mode, unsigned int channel,
|
||||
u8 ato, bool atox, unsigned int *sample);
|
||||
|
||||
/* Deprecated calls */
|
||||
static inline int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
|
||||
irq_handler_t handler,
|
||||
const char *name, void *dev)
|
||||
{
|
||||
return mc13xxx_irq_request(mc13xxx, irq, handler, name, dev);
|
||||
}
|
||||
|
||||
int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq);
|
||||
int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq);
|
||||
|
||||
#define MC13783_AUDIO_RX0 36
|
||||
#define MC13783_AUDIO_RX1 37
|
||||
#define MC13783_AUDIO_TX 38
|
||||
@@ -68,8 +79,6 @@ int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
|
||||
#define MC13XXX_IRQ_THWARNH 37
|
||||
#define MC13XXX_IRQ_CLK 38
|
||||
|
||||
#define MC13XXX_NUM_IRQ 46
|
||||
|
||||
struct regulator_init_data;
|
||||
|
||||
struct mc13xxx_regulator_init_data {
|
||||
|
||||
@@ -943,6 +943,12 @@ void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
|
||||
int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
|
||||
int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
|
||||
int num_sg, bool read, int timeout);
|
||||
int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
|
||||
int num_sg, bool read);
|
||||
void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
|
||||
int num_sg, bool read);
|
||||
int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
|
||||
int count, bool read, int timeout);
|
||||
int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
|
||||
int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
|
||||
int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
|
||||
|
||||
@@ -21,6 +21,7 @@ enum sec_device_type {
|
||||
S2MPA01,
|
||||
S2MPS11X,
|
||||
S2MPS14X,
|
||||
S2MPU02,
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@@ -129,6 +129,30 @@ enum s2mps14_irq {
|
||||
S2MPS14_IRQ_NR,
|
||||
};
|
||||
|
||||
enum s2mpu02_irq {
|
||||
S2MPU02_IRQ_PWRONF,
|
||||
S2MPU02_IRQ_PWRONR,
|
||||
S2MPU02_IRQ_JIGONBF,
|
||||
S2MPU02_IRQ_JIGONBR,
|
||||
S2MPU02_IRQ_ACOKBF,
|
||||
S2MPU02_IRQ_ACOKBR,
|
||||
S2MPU02_IRQ_PWRON1S,
|
||||
S2MPU02_IRQ_MRB,
|
||||
|
||||
S2MPU02_IRQ_RTC60S,
|
||||
S2MPU02_IRQ_RTCA1,
|
||||
S2MPU02_IRQ_RTCA0,
|
||||
S2MPU02_IRQ_SMPL,
|
||||
S2MPU02_IRQ_RTC1S,
|
||||
S2MPU02_IRQ_WTSR,
|
||||
|
||||
S2MPU02_IRQ_INT120C,
|
||||
S2MPU02_IRQ_INT140C,
|
||||
S2MPU02_IRQ_TSD,
|
||||
|
||||
S2MPU02_IRQ_NR,
|
||||
};
|
||||
|
||||
/* Masks for interrupts are the same as in s2mps11 */
|
||||
#define S2MPS14_IRQ_TSD_MASK (1 << 2)
|
||||
|
||||
|
||||
@@ -0,0 +1,201 @@
|
||||
/*
|
||||
* s2mpu02.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_S2MPU02_H
|
||||
#define __LINUX_MFD_S2MPU02_H
|
||||
|
||||
/* S2MPU02 registers */
|
||||
enum S2MPU02_reg {
|
||||
S2MPU02_REG_ID,
|
||||
S2MPU02_REG_INT1,
|
||||
S2MPU02_REG_INT2,
|
||||
S2MPU02_REG_INT3,
|
||||
S2MPU02_REG_INT1M,
|
||||
S2MPU02_REG_INT2M,
|
||||
S2MPU02_REG_INT3M,
|
||||
S2MPU02_REG_ST1,
|
||||
S2MPU02_REG_ST2,
|
||||
S2MPU02_REG_PWRONSRC,
|
||||
S2MPU02_REG_OFFSRC,
|
||||
S2MPU02_REG_BU_CHG,
|
||||
S2MPU02_REG_RTCCTRL,
|
||||
S2MPU02_REG_PMCTRL1,
|
||||
S2MPU02_REG_RSVD1,
|
||||
S2MPU02_REG_RSVD2,
|
||||
S2MPU02_REG_RSVD3,
|
||||
S2MPU02_REG_RSVD4,
|
||||
S2MPU02_REG_RSVD5,
|
||||
S2MPU02_REG_RSVD6,
|
||||
S2MPU02_REG_RSVD7,
|
||||
S2MPU02_REG_WRSTEN,
|
||||
S2MPU02_REG_RSVD8,
|
||||
S2MPU02_REG_RSVD9,
|
||||
S2MPU02_REG_RSVD10,
|
||||
S2MPU02_REG_B1CTRL1,
|
||||
S2MPU02_REG_B1CTRL2,
|
||||
S2MPU02_REG_B2CTRL1,
|
||||
S2MPU02_REG_B2CTRL2,
|
||||
S2MPU02_REG_B3CTRL1,
|
||||
S2MPU02_REG_B3CTRL2,
|
||||
S2MPU02_REG_B4CTRL1,
|
||||
S2MPU02_REG_B4CTRL2,
|
||||
S2MPU02_REG_B5CTRL1,
|
||||
S2MPU02_REG_B5CTRL2,
|
||||
S2MPU02_REG_B5CTRL3,
|
||||
S2MPU02_REG_B5CTRL4,
|
||||
S2MPU02_REG_B5CTRL5,
|
||||
S2MPU02_REG_B6CTRL1,
|
||||
S2MPU02_REG_B6CTRL2,
|
||||
S2MPU02_REG_B7CTRL1,
|
||||
S2MPU02_REG_B7CTRL2,
|
||||
S2MPU02_REG_RAMP1,
|
||||
S2MPU02_REG_RAMP2,
|
||||
S2MPU02_REG_L1CTRL,
|
||||
S2MPU02_REG_L2CTRL1,
|
||||
S2MPU02_REG_L2CTRL2,
|
||||
S2MPU02_REG_L2CTRL3,
|
||||
S2MPU02_REG_L2CTRL4,
|
||||
S2MPU02_REG_L3CTRL,
|
||||
S2MPU02_REG_L4CTRL,
|
||||
S2MPU02_REG_L5CTRL,
|
||||
S2MPU02_REG_L6CTRL,
|
||||
S2MPU02_REG_L7CTRL,
|
||||
S2MPU02_REG_L8CTRL,
|
||||
S2MPU02_REG_L9CTRL,
|
||||
S2MPU02_REG_L10CTRL,
|
||||
S2MPU02_REG_L11CTRL,
|
||||
S2MPU02_REG_L12CTRL,
|
||||
S2MPU02_REG_L13CTRL,
|
||||
S2MPU02_REG_L14CTRL,
|
||||
S2MPU02_REG_L15CTRL,
|
||||
S2MPU02_REG_L16CTRL,
|
||||
S2MPU02_REG_L17CTRL,
|
||||
S2MPU02_REG_L18CTRL,
|
||||
S2MPU02_REG_L19CTRL,
|
||||
S2MPU02_REG_L20CTRL,
|
||||
S2MPU02_REG_L21CTRL,
|
||||
S2MPU02_REG_L22CTRL,
|
||||
S2MPU02_REG_L23CTRL,
|
||||
S2MPU02_REG_L24CTRL,
|
||||
S2MPU02_REG_L25CTRL,
|
||||
S2MPU02_REG_L26CTRL,
|
||||
S2MPU02_REG_L27CTRL,
|
||||
S2MPU02_REG_L28CTRL,
|
||||
S2MPU02_REG_LDODSCH1,
|
||||
S2MPU02_REG_LDODSCH2,
|
||||
S2MPU02_REG_LDODSCH3,
|
||||
S2MPU02_REG_LDODSCH4,
|
||||
S2MPU02_REG_SELMIF,
|
||||
S2MPU02_REG_RSVD11,
|
||||
S2MPU02_REG_RSVD12,
|
||||
S2MPU02_REG_RSVD13,
|
||||
S2MPU02_REG_DVSSEL,
|
||||
S2MPU02_REG_DVSPTR,
|
||||
S2MPU02_REG_DVSDATA,
|
||||
};
|
||||
|
||||
/* S2MPU02 regulator ids */
|
||||
enum S2MPU02_regulators {
|
||||
S2MPU02_LDO1,
|
||||
S2MPU02_LDO2,
|
||||
S2MPU02_LDO3,
|
||||
S2MPU02_LDO4,
|
||||
S2MPU02_LDO5,
|
||||
S2MPU02_LDO6,
|
||||
S2MPU02_LDO7,
|
||||
S2MPU02_LDO8,
|
||||
S2MPU02_LDO9,
|
||||
S2MPU02_LDO10,
|
||||
S2MPU02_LDO11,
|
||||
S2MPU02_LDO12,
|
||||
S2MPU02_LDO13,
|
||||
S2MPU02_LDO14,
|
||||
S2MPU02_LDO15,
|
||||
S2MPU02_LDO16,
|
||||
S2MPU02_LDO17,
|
||||
S2MPU02_LDO18,
|
||||
S2MPU02_LDO19,
|
||||
S2MPU02_LDO20,
|
||||
S2MPU02_LDO21,
|
||||
S2MPU02_LDO22,
|
||||
S2MPU02_LDO23,
|
||||
S2MPU02_LDO24,
|
||||
S2MPU02_LDO25,
|
||||
S2MPU02_LDO26,
|
||||
S2MPU02_LDO27,
|
||||
S2MPU02_LDO28,
|
||||
S2MPU02_BUCK1,
|
||||
S2MPU02_BUCK2,
|
||||
S2MPU02_BUCK3,
|
||||
S2MPU02_BUCK4,
|
||||
S2MPU02_BUCK5,
|
||||
S2MPU02_BUCK6,
|
||||
S2MPU02_BUCK7,
|
||||
|
||||
S2MPU02_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
/* Regulator constraints for BUCKx */
|
||||
#define S2MPU02_BUCK1234_MIN_600MV 600000
|
||||
#define S2MPU02_BUCK5_MIN_1081_25MV 1081250
|
||||
#define S2MPU02_BUCK6_MIN_1700MV 1700000
|
||||
#define S2MPU02_BUCK7_MIN_900MV 900000
|
||||
|
||||
#define S2MPU02_BUCK1234_STEP_6_25MV 6250
|
||||
#define S2MPU02_BUCK5_STEP_6_25MV 6250
|
||||
#define S2MPU02_BUCK6_STEP_2_50MV 2500
|
||||
#define S2MPU02_BUCK7_STEP_6_25MV 6250
|
||||
|
||||
#define S2MPU02_BUCK1234_START_SEL 0x00
|
||||
#define S2MPU02_BUCK5_START_SEL 0x4D
|
||||
#define S2MPU02_BUCK6_START_SEL 0x28
|
||||
#define S2MPU02_BUCK7_START_SEL 0x30
|
||||
|
||||
#define S2MPU02_BUCK_RAMP_DELAY 12500
|
||||
|
||||
/* Regulator constraints for different types of LDOx */
|
||||
#define S2MPU02_LDO_MIN_900MV 900000
|
||||
#define S2MPU02_LDO_MIN_1050MV 1050000
|
||||
#define S2MPU02_LDO_MIN_1600MV 1600000
|
||||
#define S2MPU02_LDO_STEP_12_5MV 12500
|
||||
#define S2MPU02_LDO_STEP_25MV 25000
|
||||
#define S2MPU02_LDO_STEP_50MV 50000
|
||||
|
||||
#define S2MPU02_LDO_GROUP1_START_SEL 0x8
|
||||
#define S2MPU02_LDO_GROUP2_START_SEL 0xA
|
||||
#define S2MPU02_LDO_GROUP3_START_SEL 0x10
|
||||
|
||||
#define S2MPU02_LDO_VSEL_MASK 0x3F
|
||||
#define S2MPU02_BUCK_VSEL_MASK 0xFF
|
||||
#define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_ENABLE_SHIFT 6
|
||||
|
||||
/* On/Off controlled by PWREN */
|
||||
#define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT)
|
||||
#define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1)
|
||||
#define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1)
|
||||
|
||||
/* RAMP delay for BUCK1234*/
|
||||
#define S2MPU02_BUCK1_RAMP_SHIFT 6
|
||||
#define S2MPU02_BUCK2_RAMP_SHIFT 4
|
||||
#define S2MPU02_BUCK3_RAMP_SHIFT 2
|
||||
#define S2MPU02_BUCK4_RAMP_SHIFT 0
|
||||
#define S2MPU02_BUCK1234_RAMP_MASK 0x3
|
||||
|
||||
#endif /* __LINUX_MFD_S2MPU02_H */
|
||||
@@ -892,7 +892,7 @@ struct tps65910 {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c_client;
|
||||
struct regmap *regmap;
|
||||
unsigned int id;
|
||||
unsigned long id;
|
||||
|
||||
/* Client devices */
|
||||
struct tps65910_pmic *pmic;
|
||||
|
||||
Reference in New Issue
Block a user