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PCI: tegra: Bypass CLKREQ# control over PLLE

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When PCIe link is L2 CLKREQ# will be floating and this might interfere
with PLL power down. Bypass CLKREQ# control over PLLE when link is in L2.

bug 1356695
bug 200420606

Change-Id: I361db03df5f9a1a8d38bd9fb816d17fc4c64a9fc
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786565
(cherry picked from commit 69e79f42f65df70b0c76e62200aca40ed3972e3b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407877
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Manikanta Maddireddy
2018-07-24 10:30:34 +05:30
committed by Thomas Makin
parent 5f8f949eb9
commit 51ab98c25e
1 changed files with 5 additions and 0 deletions
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5
drivers/pci/controller/pci-tegra.c
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@@ -1765,6 +1765,11 @@ static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port)
val = afi_readl(pcie, AFI_PCIE_PME);
val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit);
afi_writel(pcie, val, AFI_PCIE_PME);
/* PCIe link is in L2, bypass CLKREQ# control over PLLE power down */
val = afi_readl(pcie, AFI_PLLE_CONTROL);
val |= AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
afi_writel(pcie, val, AFI_PLLE_CONTROL);
}
static void tegra_pcie_msi_irq(struct irq_desc *desc)