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Merge tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx into next/soc

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Merge "Xilinx Zynq changes for v3.16" from Michal Simek:

arm: Xilinx Zynq cleanup patches for v3.16

- Add support for BIG Endian
- Add SOC_BUS support
- Sort Kconfig options
- Fix early console

* tag 'zynq-cleanup-for-3.16' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: Enable big-endian
  ARM: zynq: Fix uart0 early console virtual address
  clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
  ARM: zynq: Sort Kconfig options
  ARM: zynq: Add support for SOC_BUS

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2014-05-26 14:52:23 -07:00
parent e469d6ba0a eb28d0bb85
commit 4fd0912044
8 changed files with 138 additions and 37 deletions
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arch/arm/include/debug/zynq.S
+6 -4
View File
@@ -20,18 +20,18 @@
#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
#define UART0_PHYS 0xE0000000
#define UART0_VIRT 0xF0000000
#define UART1_PHYS 0xE0001000
#define UART_SIZE SZ_4K
#define UART_VIRT 0xF0001000
#define UART1_VIRT 0xF0001000
#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
# define LL_UART_PADDR UART1_PHYS
# define LL_UART_VADDR UART1_VIRT
#else
# define LL_UART_PADDR UART0_PHYS
# define LL_UART_VADDR UART0_VIRT
#endif
#define LL_UART_VADDR UART_VIRT
.macro addruart, rp, rv, tmp
ldr \rp, =LL_UART_PADDR @ physical
ldr \rv, =LL_UART_VADDR @ virtual
@@ -43,12 +43,14 @@
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #UART_SR_OFFSET]
ARM_BE8( rev \rd, \rd )
tst \rd, #UART_SR_TXEMPTY
beq 1001b
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
ARM_BE8( rev \rd, \rd )
tst \rd, #UART_SR_TXFULL @
bne 1002b @ wait if FIFO is full
.endm