arm64: make ARM64_HAS_GIC_PRIO_MASKING depend on ARM64_HAS_GIC_CPUIF_SYSREGS
Currently the arm64_cpu_capabilities structure for ARM64_HAS_GIC_PRIO_MASKING open-codes the same CPU field definitions as the arm64_cpu_capabilities structure for ARM64_HAS_GIC_CPUIF_SYSREGS, so that can_use_gic_priorities() can use has_useable_gicv3_cpuif(). This duplication isn't ideal for the legibility of the code, and sets a bad example for any ARM64_HAS_GIC_* definitions added by subsequent patches. Instead, have ARM64_HAS_GIC_PRIO_MASKING check for the ARM64_HAS_GIC_CPUIF_SYSREGS cpucap, and add a comment explaining why this is safe. Subsequent patches will use the same pattern where one cpucap depends upon another. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20230130145429.903791-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Catalin Marinas
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c888b7bd91
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4b43f1cd70
@@ -2046,7 +2046,15 @@ early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
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static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
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/*
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* ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
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* feature, so will be detected earlier.
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*/
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BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
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if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
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return false;
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return enable_pseudo_nmi;
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}
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#endif
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@@ -2537,11 +2545,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.capability = ARM64_HAS_GIC_PRIO_MASKING,
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.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
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.matches = can_use_gic_priorities,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.field_pos = ID_AA64PFR0_EL1_GIC_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = 1,
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},
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#endif
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#ifdef CONFIG_ARM64_E0PD
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