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[MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors.

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Added support for RM200C machines with big endian firmware
Added support for RM200-C40 (R5000 support)
    
Signed-off-by: Florian Lohoff <flo@rfc822.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thomas Bogendoerfer
2006-06-13 13:59:01 +02:00
committed by Ralf Baechle
parent b00f473e1a
commit 4a0312fca6
7 changed files with 177 additions and 19 deletions
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include/asm-mips/mach-rm200/cpu-feature-overrides.h
-2
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@@ -35,10 +35,8 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 /* No S-cache on R5000 I think ... */
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
include/asm-mips/sni.h
+2 -5
View File
@@ -15,9 +15,6 @@
/*
* ASIC PCI registers for little endian configuration.
*/
#ifndef __MIPSEL__
#error "Fix me for big endian"
#endif
#define PCIMT_UCONF 0xbfff0000
#define PCIMT_IOADTIMEOUT2 0xbfff0008
#define PCIMT_IOMEMCONF 0xbfff0010
@@ -51,9 +48,9 @@
#define PCIMT_PCI_CONF 0xbfff0100
/*
* Data port for the PCI bus.
* Data port for the PCI bus in IO space
*/
#define PCIMT_CONFIG_DATA 0xb4000cfc
#define PCIMT_CONFIG_DATA 0x0cfc
/*
* Board specific registers