From 46093863d5f97e59b4d515ac245f87c7c7e36829 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Wed, 2 Aug 2017 12:50:34 -0700 Subject: [PATCH] clk: soc: tegra: Rename DFLL tune1 to tune1_low Renamed DFLL tune1 to tune1_low to be consistent with tune0_low/tune0_high naming convention. Bug 1967884 Change-Id: If23170305143b05c2918e04691c73fe13b777272 Signed-off-by: Alex Frid Reviewed-on: https://git-master.nvidia.com/r/1576306 Reviewed-by: mobile promotions Tested-by: mobile promotions Signed-off-by: Thomas Makin --- drivers/clk/tegra/clk-dfll.c | 2 +- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 44 +++++++++++----------- drivers/clk/tegra/cvb.h | 2 +- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 58fa5a59e0c7..97cf3c834cf0 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -452,7 +452,7 @@ static void dfll_tune_low(struct tegra_dfll *td) td->tune_range = DFLL_TUNE_LOW; dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0); - dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1); + dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1_low, DFLL_TUNE1); dfll_wmb(td); if (td->soc->set_clock_trimmers_low) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 64c665373395..9fa203e2e75d 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -74,7 +74,7 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0x005020ff, .tune0_high = 0x005040ff, - .tune1 = 0x00000060, + .tune1_low = 0x00000060, } }, }; @@ -242,7 +242,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -255,7 +255,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -268,7 +268,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, } }, { @@ -280,7 +280,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, } }, { @@ -292,7 +292,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, } }, { @@ -304,7 +304,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, } }, { @@ -316,7 +316,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -329,7 +329,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -341,7 +341,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { CPU_CVB_TABLE, .cpu_dfll_data = { .tune0_low = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, } }, { @@ -352,7 +352,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { CPU_CVB_TABLE, .cpu_dfll_data = { .tune0_low = 0xffead0ff, - .tune1 = 0x25501d0, + .tune1_low = 0x25501d0, } }, { @@ -364,7 +364,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -377,7 +377,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x25501d0, + .tune1_low = 0x25501d0, .tune_high_min_millivolts = 864, } }, @@ -389,7 +389,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { CPU_CVB_TABLE_XA, .cpu_dfll_data = { .tune0_low = 0xffead0ff, - .tune1 = 0x17711BD, + .tune1_low = 0x17711BD, } }, { @@ -401,7 +401,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -414,7 +414,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x25501d0, + .tune1_low = 0x25501d0, .tune_high_min_millivolts = 864, } }, @@ -426,7 +426,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { CPU_CVB_TABLE, .cpu_dfll_data = { .tune0_low = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, } }, { @@ -437,7 +437,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { CPU_CVB_TABLE, .cpu_dfll_data = { .tune0_low = 0xffead0ff, - .tune1 = 0x25501d0, + .tune1_low = 0x25501d0, } }, { @@ -449,7 +449,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -462,7 +462,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x25501d0, + .tune1_low = 0x25501d0, .tune_high_min_millivolts = 864, } }, @@ -475,7 +475,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x20091d9, + .tune1_low = 0x20091d9, .tune_high_min_millivolts = 864, } }, @@ -488,7 +488,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = { .cpu_dfll_data = { .tune0_low = 0xffead0ff, .tune0_high = 0xffead0ff, - .tune1 = 0x25501d0, + .tune1_low = 0x25501d0, .tune_high_min_millivolts = 864, } }, diff --git a/drivers/clk/tegra/cvb.h b/drivers/clk/tegra/cvb.h index 750095fe97d7..c2ff6379b35d 100644 --- a/drivers/clk/tegra/cvb.h +++ b/drivers/clk/tegra/cvb.h @@ -31,7 +31,7 @@ struct cvb_table_freq_entry { struct cvb_cpu_dfll_data { u32 tune0_low; u32 tune0_high; - u32 tune1; + u32 tune1_low; unsigned int tune_high_min_millivolts; };