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clk: tegra: dfll: add CVB tables for Tegra210B01

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To generate OPP tables for the soc

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
This commit is contained in:
Aaron Kling
2025-05-11 20:08:55 -05:00
committed by Thomas Makin
parent 31ecc0af39
commit 40380c8c38
1 changed files with 146 additions and 0 deletions
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146
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
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@@ -494,6 +494,141 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
}, },
}; };
static const unsigned long tegra210b01_cpu_max_freq_table[] = {
[0] = 1963500000UL,
[1] = 1963500000UL,
[2] = 2091000000UL,
[3] = 2014500000UL,
};
#define CPUB01_CVB_TABLE_SLT_B1 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0UL, { 0, 0, 0 } }, \
}
#define CPUB01_CVB_TABLE_SLT_B0 \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 732856, -17335, 113 } }, \
{ 306000000UL, { 760024, -18195, 113 } }, \
{ 408000000UL, { 789258, -19055, 113 } }, \
{ 510000000UL, { 820558, -19915, 113 } }, \
{ 612000000UL, { 853926, -20775, 113 } }, \
{ 714000000UL, { 889361, -21625, 113 } }, \
{ 816000000UL, { 926862, -22485, 113 } }, \
{ 918000000UL, { 966431, -23345, 113 } }, \
{ 1020000000UL, { 1008066, -24205, 113 } }, \
{ 1122000000UL, { 1051768, -25065, 113 } }, \
{ 1224000000UL, { 1097537, -25925, 113 } }, \
{ 1326000000UL, { 1145373, -26785, 113 } }, \
{ 1428000000UL, { 1195276, -27645, 113 } }, \
{ 1581000000UL, { 1274006, -28935, 113 } }, \
{ 1683000000UL, { 1329076, -29795, 113 } }, \
{ 1785000000UL, { 1386213, -30655, 113 } }, \
{ 1887000000UL, { 1445416, -31515, 113 } }, \
{ 1963500000UL, { 1490873, -32155, 113 } }, \
{ 2065500000UL, { 1553683, -33015, 113 } }, \
{ 2091000000UL, { 1580725, -33235, 113 } }, \
{ 0UL, { 0, 0, 0 } }, \
}
#define CPUB01_CVB_TABLE \
.speedo_scale = 100, \
.voltage_scale = 1000, \
.entries = { \
{ 204000000UL, { 721589, -12695, 27 } }, \
{ 306000000UL, { 747134, -14195, 27 } }, \
{ 408000000UL, { 776324, -15705, 27 } }, \
{ 510000000UL, { 809160, -17205, 27 } }, \
{ 612000000UL, { 845641, -18715, 27 } }, \
{ 714000000UL, { 885768, -20215, 27 } }, \
{ 816000000UL, { 929540, -21725, 27 } }, \
{ 918000000UL, { 976958, -23225, 27 } }, \
{ 1020000000UL, { 1028021, -24725, 27 } }, \
{ 1122000000UL, { 1082730, -26235, 27 } }, \
{ 1224000000UL, { 1141084, -27735, 27 } }, \
{ 1326000000UL, { 1203084, -29245, 27 } }, \
{ 1428000000UL, { 1268729, -30745, 27 } }, \
{ 1581000000UL, { 1374032, -33005, 27 } }, \
{ 1683000000UL, { 1448791, -34505, 27 } }, \
{ 1785000000UL, { 1527196, -36015, 27 } }, \
{ 1887000000UL, { 1609246, -37515, 27 } }, \
{ 1963500000UL, { 1675751, -38635, 27 } }, \
{ 2014500000UL, { 1716501, -39395, 27 } }, \
{ 0UL, { 0, 0, 0 } }, \
}
static struct cvb_table tegra210b01_cpu_cvb_tables[] = {
{
.speedo_id = 3,
.process_id = -1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0x0000ffcf,
.tune1 = 0x012207ff,
.tune_high_min_millivolts = 850,
}
},
{
.speedo_id = 2,
.process_id = 1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE_SLT_B1,
.cpu_dfll_data = {
.tune0_low = 0x0000ffa0,
.tune0_high = 0x0000ffff,
.tune1 = 0x021107ff,
.tune_high_min_millivolts = 850,
}
},
{
.speedo_id = 2,
.process_id = 0,
.max_millivolts = 1120,
CPUB01_CVB_TABLE_SLT_B0,
.cpu_dfll_data = {
.tune0_low = 0x0000ff90,
.tune0_high = 0x0000ffff,
.tune1 = 0x021107ff,
.tune_high_min_millivolts = 850,
}
},
{
.speedo_id = -1,
.process_id = -1,
.max_millivolts = 1120,
CPUB01_CVB_TABLE,
.cpu_dfll_data = {
.tune0_low = 0x0000ffcf,
.tune1 = 0x012207ff,
.tune_high_min_millivolts = 850,
}
},
};
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
.cpu_max_freq_table = tegra124_cpu_max_freq_table, .cpu_max_freq_table = tegra124_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
@@ -508,6 +643,13 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables), .cpu_cvb_tables_size = ARRAY_SIZE(tegra210_cpu_cvb_tables),
}; };
static const struct dfll_fcpu_data tegra210b01_dfll_fcpu_data = {
.cpu_max_freq_table = tegra210b01_cpu_max_freq_table,
.cpu_max_freq_table_size = ARRAY_SIZE(tegra210b01_cpu_max_freq_table),
.cpu_cvb_tables = tegra210b01_cpu_cvb_tables,
.cpu_cvb_tables_size = ARRAY_SIZE(tegra210b01_cpu_cvb_tables),
};
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
{ {
.compatible = "nvidia,tegra124-dfll", .compatible = "nvidia,tegra124-dfll",
@@ -517,6 +659,10 @@ static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
.compatible = "nvidia,tegra210-dfll", .compatible = "nvidia,tegra210-dfll",
.data = &tegra210_dfll_fcpu_data .data = &tegra210_dfll_fcpu_data
}, },
{
.compatible = "nvidia,tegra210b01-dfll",
.data = &tegra210b01_dfll_fcpu_data
},
{ }, { },
}; };