From 3e038a2f95ac6afbc181b0aa8ee186b5209f3d69 Mon Sep 17 00:00:00 2001 From: Thomas Makin Date: Tue, 2 Dec 2025 01:55:38 +0000 Subject: [PATCH] pci: tegra: b01 fix --- drivers/pci/controller/pci-tegra.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index d8d6c233741c..e6935c1a4861 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -2339,7 +2339,8 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) pcie->supplies[i++].supply = "hvdd-pex-pll"; pcie->supplies[i++].supply = "hvdd-pex"; pcie->supplies[i++].supply = "vddio-pexctl-aud"; - } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) { + } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie") || + of_device_is_compatible(np, "nvidia,tegra210b01-pcie")) { pcie->num_supplies = 3; pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies, @@ -2851,7 +2852,7 @@ static const struct tegra_pcie_soc tegra210b01_pcie = { .msi_base_shift = 8, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, - .pads_refclk_cfg0 = 0x90b890b8, + .pads_refclk_cfg0 = 0xb0b880b8, /* FC threshold is bit[25:18] */ .update_fc_threshold = 0x01800000, .has_pex_clkreq_en = true,