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PCI: tegra: Add PCIe support for tegra210b01 chip

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bug 200420606

Change-Id: I943e4ad90915332fbecc3ed9cb368d3f549925a6
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786562
(cherry picked from commit ef7328abda206df3b00364eeaeecc20103896326)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407885
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Manikanta Maddireddy
2018-07-19 22:51:04 +05:30
committed by Thomas Makin
parent a248214f65
commit 3db69fdfe2
1 changed files with 61 additions and 0 deletions
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61
drivers/pci/controller/pci-tegra.c
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@@ -167,6 +167,9 @@
#define AFI_PEXBIAS_CTRL_0 0x168
#define RP_ECTL_1_R1 0x00000e80
#define RP_ECTL_1_R1_TX_DRV_AMP_1C_MASK 0x3f
#define RP_ECTL_2_R1 0x00000e84
#define RP_ECTL_2_R1_RX_CTLE_1C_MASK 0xffff
@@ -180,6 +183,9 @@
#define RP_ECTL_6_R1 0x00000e94
#define RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK 0xffffffff
#define RP_ECTL_1_R2 0x00000ea0
#define RP_ECTL_1_R2_TX_DRV_AMP_1C_MASK 0x3f
#define RP_ECTL_2_R2 0x00000ea4
#define RP_ECTL_2_R2_RX_CTLE_1C_MASK 0xffff
@@ -306,10 +312,12 @@ struct tegra_pcie_soc {
bool has_cache_bars;
struct {
struct {
u32 rp_ectl_1_r1;
u32 rp_ectl_2_r1;
u32 rp_ectl_4_r1;
u32 rp_ectl_5_r1;
u32 rp_ectl_6_r1;
u32 rp_ectl_1_r2;
u32 rp_ectl_2_r2;
u32 rp_ectl_4_r2;
u32 rp_ectl_5_r2;
@@ -572,6 +580,11 @@ static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
const struct tegra_pcie_soc *soc = port->pcie->soc;
u32 value;
value = readl(port->base + RP_ECTL_1_R1);
value &= ~RP_ECTL_1_R1_TX_DRV_AMP_1C_MASK;
value |= soc->ectl.regs.rp_ectl_1_r1;
writel(value, port->base + RP_ECTL_1_R1);
value = readl(port->base + RP_ECTL_2_R1);
value &= ~RP_ECTL_2_R1_RX_CTLE_1C_MASK;
value |= soc->ectl.regs.rp_ectl_2_r1;
@@ -593,6 +606,11 @@ static void tegra_pcie_program_ectl_settings(struct tegra_pcie_port *port)
value |= soc->ectl.regs.rp_ectl_6_r1;
writel(value, port->base + RP_ECTL_6_R1);
value = readl(port->base + RP_ECTL_1_R2);
value &= ~RP_ECTL_1_R2_TX_DRV_AMP_1C_MASK;
value |= soc->ectl.regs.rp_ectl_1_r2;
writel(value, port->base + RP_ECTL_1_R2);
value = readl(port->base + RP_ECTL_2_R2);
value &= ~RP_ECTL_2_R2_RX_CTLE_1C_MASK;
value |= soc->ectl.regs.rp_ectl_2_r2;
@@ -1876,6 +1894,10 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;
return 0;
}
} else if (of_device_is_compatible(np, "nvidia,tegra210b01-pcie")) {
dev_info(dev, "4x1, 1x1 configuration\n");
*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
return 0;
} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
switch (lanes) {
@@ -2477,10 +2499,12 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.has_cache_bars = false,
.ectl = {
.regs = {
.rp_ectl_1_r1 = 0x0000001f,
.rp_ectl_2_r1 = 0x0000000f,
.rp_ectl_4_r1 = 0x00000067,
.rp_ectl_5_r1 = 0x55010000,
.rp_ectl_6_r1 = 0x00000001,
.rp_ectl_1_r2 = 0x0000001f,
.rp_ectl_2_r2 = 0x0000008f,
.rp_ectl_4_r2 = 0x000000c7,
.rp_ectl_5_r2 = 0x55010000,
@@ -2490,6 +2514,42 @@ static const struct tegra_pcie_soc tegra210_pcie = {
},
};
static const struct tegra_pcie_soc tegra210b01_pcie = {
.num_ports = 2,
.ports = tegra20_pcie_ports,
.msi_base_shift = 8,
.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
.pads_refclk_cfg0 = 0x90b890b8,
/* FC threshold is bit[25:18] */
.update_fc_threshold = 0x01800000,
.has_pex_clkreq_en = true,
.has_pex_bias_ctrl = true,
.has_intr_prsnt_sense = true,
.has_cml_clk = true,
.has_gen2 = true,
.force_pca_enable = true,
.program_uphy = true,
.program_deskew_time = true,
.update_fc_timer = true,
.has_cache_bars = false,
.ectl = {
.regs = {
.rp_ectl_1_r1 = 0x00000027,
.rp_ectl_2_r1 = 0x0000000f,
.rp_ectl_4_r1 = 0x00000067,
.rp_ectl_5_r1 = 0x00000000,
.rp_ectl_6_r1 = 0x00000000,
.rp_ectl_1_r2 = 0x00000027,
.rp_ectl_2_r2 = 0x0000008f,
.rp_ectl_4_r2 = 0x000000c7,
.rp_ectl_5_r2 = 0x00000000,
.rp_ectl_6_r2 = 0x00000000,
},
.enable = true,
},
};
static const struct tegra_pcie_port_soc tegra186_pcie_ports[] = {
{ .pme.turnoff_bit = 0, .pme.ack_bit = 5 },
{ .pme.turnoff_bit = 8, .pme.ack_bit = 10 },
@@ -2521,6 +2581,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
static const struct of_device_id tegra_pcie_of_match[] = {
{ .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
{ .compatible = "nvidia,tegra210b01-pcie", .data = &tegra210b01_pcie },
{ .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
{ .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
{ .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },