From 0c50b7fcf2773b4853e83fc15aba1a196ba95966 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Mon, 4 Mar 2024 14:14:53 +0100 Subject: [PATCH 001/969] firmware: qcom_scm: disable clocks if qcom_scm_bw_enable() fails There are several functions which are calling qcom_scm_bw_enable() then returns immediately if the call fails and leaves the clocks enabled. Change the code of these functions to disable clocks when the qcom_scm_bw_enable() call fails. This also fixes a possible dma buffer leak in the qcom_scm_pas_init_image() function. Compile tested only due to lack of hardware with interconnect support. Cc: stable@vger.kernel.org Fixes: 65b7ebda5028 ("firmware: qcom_scm: Add bw voting support to the SCM interface") Signed-off-by: Gabor Juhos Reviewed-by: Mukesh Ojha Link: https://lore.kernel.org/r/20240304-qcom-scm-disable-clk-v1-1-b36e51577ca1@gmail.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 520de9b5633a..e8460626fb0c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -569,13 +569,14 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, ret = qcom_scm_bw_enable(); if (ret) - return ret; + goto disable_clk; desc.args[1] = mdata_phys; ret = qcom_scm_call(__scm->dev, &desc, &res); - qcom_scm_bw_disable(); + +disable_clk: qcom_scm_clk_disable(); out: @@ -637,10 +638,12 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) ret = qcom_scm_bw_enable(); if (ret) - return ret; + goto disable_clk; ret = qcom_scm_call(__scm->dev, &desc, &res); qcom_scm_bw_disable(); + +disable_clk: qcom_scm_clk_disable(); return ret ? : res.result[0]; @@ -672,10 +675,12 @@ int qcom_scm_pas_auth_and_reset(u32 peripheral) ret = qcom_scm_bw_enable(); if (ret) - return ret; + goto disable_clk; ret = qcom_scm_call(__scm->dev, &desc, &res); qcom_scm_bw_disable(); + +disable_clk: qcom_scm_clk_disable(); return ret ? : res.result[0]; @@ -706,11 +711,12 @@ int qcom_scm_pas_shutdown(u32 peripheral) ret = qcom_scm_bw_enable(); if (ret) - return ret; + goto disable_clk; ret = qcom_scm_call(__scm->dev, &desc, &res); - qcom_scm_bw_disable(); + +disable_clk: qcom_scm_clk_disable(); return ret ? : res.result[0]; From e6f3dac9cf11eff1daddeaa69521370c8941a5f9 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Fri, 8 Mar 2024 10:25:07 +0100 Subject: [PATCH 002/969] firmware: qcom_scm: remove IS_ERR() checks from qcom_scm_bw_{en,dis}able() Since the qcom_scm_probe() function returns with an error if __scm->path contains an error pointer, it is not needed to verify that again in the qcom_scm_bw_{en,dis}able() functions so remove the superfluous IS_ERR() checks. Signed-off-by: Gabor Juhos Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240308-qcom_scm-is_err-check-v1-1-9c3e1ceefafe@gmail.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index e8460626fb0c..49ddbcab0680 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -163,9 +163,6 @@ static int qcom_scm_bw_enable(void) if (!__scm->path) return 0; - if (IS_ERR(__scm->path)) - return -EINVAL; - mutex_lock(&__scm->scm_bw_lock); if (!__scm->scm_vote_count) { ret = icc_set_bw(__scm->path, 0, UINT_MAX); @@ -183,7 +180,7 @@ err_bw: static void qcom_scm_bw_disable(void) { - if (IS_ERR_OR_NULL(__scm->path)) + if (!__scm->path) return; mutex_lock(&__scm->scm_bw_lock); From a8adf216136a16f8b31ece4455f60d59db3d6d62 Mon Sep 17 00:00:00 2001 From: wangkaiyuan Date: Sat, 9 Mar 2024 15:28:25 +0800 Subject: [PATCH 003/969] soc: qcom: icc-bwmon: Convert to use maple tree register cache The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: wangkaiyuan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240309072825.45385-1-wangkaiyuan@inspur.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/icc-bwmon.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index 656706259353..fb323b3364db 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -282,7 +282,7 @@ static const struct regmap_config msm8998_bwmon_regmap_cfg = { * Cache is necessary for using regmap fields with non-readable * registers. */ - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; static const struct regmap_config msm8998_bwmon_global_regmap_cfg = { @@ -301,7 +301,7 @@ static const struct regmap_config msm8998_bwmon_global_regmap_cfg = { * Cache is necessary for using regmap fields with non-readable * registers. */ - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; static const struct reg_field sdm845_cpu_bwmon_reg_fields[] = { @@ -369,7 +369,7 @@ static const struct regmap_config sdm845_cpu_bwmon_regmap_cfg = { * Cache is necessary for using regmap fields with non-readable * registers. */ - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; /* BWMON v5 */ @@ -446,7 +446,7 @@ static const struct regmap_config sdm845_llcc_bwmon_regmap_cfg = { * Cache is necessary for using regmap fields with non-readable * registers. */ - .cache_type = REGCACHE_RBTREE, + .cache_type = REGCACHE_MAPLE, }; static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all) From 15ec7c641dd3a33f4d7b7c0cc59369d87edcec5c Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Sat, 17 Feb 2024 19:27:07 +0530 Subject: [PATCH 004/969] soc: qcom: Update init level to core_initcall() for cmd-db and rpmh-rsc cmd-db and rpmh-rsc are used by clients like regulators, interconnects and clocks for resource voting. These clients are in core_initcall() while cmd-db and rpmh-rsc are in arch_initcall(). Update init level for these drivers also to core_initcall() to avoid unnecessary probe defer during boot up. Signed-off-by: Maulik Shah Reviewed-by: Ulf Hansson Link: https://lore.kernel.org/r/20240217-init_level-v1-1-bde9e11f8317@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/cmd-db.c | 2 +- drivers/soc/qcom/rpmh-rsc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index a5fd68411bed..c344107bc36c 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -362,7 +362,7 @@ static int __init cmd_db_device_init(void) { return platform_driver_register(&cmd_db_dev_driver); } -arch_initcall(cmd_db_device_init); +core_initcall(cmd_db_device_init); MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Command DB Driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index a021dc71807b..c4c7aad957e6 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -1154,7 +1154,7 @@ static int __init rpmh_driver_init(void) { return platform_driver_register(&rpmh_driver); } -arch_initcall(rpmh_driver_init); +core_initcall(rpmh_driver_init); MODULE_DESCRIPTION("Qualcomm Technologies, Inc. RPMh Driver"); MODULE_LICENSE("GPL v2"); From 734364d0ddee6c145705bac89400266c972efc0b Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 23 Feb 2024 16:37:55 +0200 Subject: [PATCH 005/969] dt-bindings: arm: qcom,ids: Add SoC ID for X1E80100 Add the ID for the Qualcomm X1E80100 SoC. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240223-x1e80100-socinfo-v1-1-be581ca60f27@linaro.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 19ac7b36f608..d040033dc8ee 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -258,6 +258,7 @@ #define QCOM_ID_QRU1000 539 #define QCOM_ID_SM8475_2 540 #define QCOM_ID_QDU1000 545 +#define QCOM_ID_X1E80100 555 #define QCOM_ID_SM8650 557 #define QCOM_ID_SM4450 568 #define QCOM_ID_QDU1010 587 From e876303c6f18da4c649d97f6d488ee0a850ad384 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 23 Feb 2024 16:37:56 +0200 Subject: [PATCH 006/969] soc: qcom: socinfo: Add X1E80100 SoC ID table entry Add SoC Info support for the X1E80100 platform. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240223-x1e80100-socinfo-v1-2-be581ca60f27@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index e8ff9819ac47..c8e968d7a620 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -430,6 +430,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QRU1000) }, { qcom_board_id(SM8475_2) }, { qcom_board_id(QDU1000) }, + { qcom_board_id(X1E80100) }, { qcom_board_id(SM8650) }, { qcom_board_id(SM4450) }, { qcom_board_id(QDU1010) }, From e025171d1ab1edf286c102f7adecafd51c3a84c3 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 23 Feb 2024 16:37:57 +0200 Subject: [PATCH 007/969] soc: qcom: socinfo: Add SMB2360 PMIC The SMB2360 PMIC is used on boards with X1E80100. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240223-x1e80100-socinfo-v1-3-be581ca60f27@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index c8e968d7a620..277c07a6603d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -133,6 +133,7 @@ static const char *const pmic_models[] = { [72] = "PMR735D", [73] = "PM8550", [74] = "PMK8550", + [82] = "SMB2360", }; struct socinfo_params { From 629c635eafbaf18260c8083360745c71674640d2 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 15 Feb 2024 16:09:29 +0530 Subject: [PATCH 008/969] arm64: dts: qcom: qcm6490-idp: add display and panel Enable Display Subsystem with Novatek NT36672E Panel on qcm6490 idp platform. Signed-off-by: Ritesh Kumar Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240215103929.19357-3-quic_riteshk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 92 ++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index e4bfad50a669..5bbe8aa63927 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -10,6 +10,7 @@ #define PM7250B_SID1 9 #include +#include #include #include "sc7280.dtsi" #include "pm7250b.dtsi" @@ -35,10 +36,29 @@ serial0 = &uart5; }; + pm8350c_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8350c_pwm 3 65535>; + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pmic_lcd_bl_en>; + pinctrl-names = "default"; + }; + chosen { stdout-path = "serial0:115200n8"; }; + lcd_disp_bias: regulator-lcd-disp-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_disp_bias"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_disp_bias_en>; + pinctrl-names = "default"; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -421,7 +441,79 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; + + panel@0 { + compatible = "novatek,nt36672e"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; + + vddi-supply = <&vreg_l8c_1p62>; + avdd-supply = <&lcd_disp_bias>; + avee-supply = <&lcd_disp_bias>; + + backlight = <&pm8350c_pwm_backlight>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + status = "okay"; +}; + +&pm7250b_gpios { + lcd_disp_bias_en: lcd-disp-bias-en-state { + pins = "gpio2"; + function = "func1"; + bias-disable; + qcom,drive-strength = ; + input-disable; + output-enable; + power-source = <0>; + }; +}; + +&pm8350c_gpios { + pmic_lcd_bl_en: pmic-lcd-bl-en-state { + pins = "gpio7"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + output-low; + power-source = <0>; + }; + + pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + bias-disable; + qcom,drive-strength = ; + output-low; + power-source = <0>; + }; +}; + &pm8350c_pwm { + pinctrl-0 = <&pmic_lcd_bl_pwm>; + pinctrl-names = "default"; status = "okay"; multi-led { From 55ca24e5f9f432e27499ce5baa85f233931901c1 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 15 Feb 2024 16:09:28 +0530 Subject: [PATCH 009/969] arm64: defconfig: enable Novatek NT36672E DSI Panel driver Build the Novatek NT36672E DSI Panel driver as module because it is used on Qualcomm qcm6490 idp board. Signed-off-by: Ritesh Kumar Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240215103929.19357-2-quic_riteshk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 500a5307a691..3a879c86c56b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -860,6 +860,7 @@ CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_NOVATEK_NT36672E=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m From 9fa6a0bad7077cac60ba98d801e13a74581ec46a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 17 Feb 2024 14:00:07 +0100 Subject: [PATCH 010/969] arm64: dts: qcom: sc8280xp: Add missing LMH interrupts Hook up the interrupts that signal the Limits Management Hardware has started some sort of throttling action. In testing, you may notice the A78C cluster throttle IRQ fire count stays at zero. After an hour of painful experiments on an X13s, I was able to get that cluster to heat up near 90 degC, after which the IRQ has indeed fired. So it stands to reason that the heat output difference between the A78C and X1C clusters is so massive that LMH rarely decides to throttle the "little" one based on its power metrics. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240217-topic-8280_lmh-v1-1-d72dd4fedfb8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a5b194813079..daaf054efca3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4966,6 +4966,11 @@ <0 0x18592000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; From 2b621971554a94094cf489314dc1c2b65401965c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 6 Mar 2024 10:56:50 +0100 Subject: [PATCH 011/969] arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP Add the missing PCIe CX performance level votes to avoid relying on other drivers (e.g. USB or UFS) to maintain the nominal performance level required for Gen3 speeds. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Cc: stable@vger.kernel.org # 6.2 Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20240306095651.4551-5-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index daaf054efca3..f42fc469af73 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1774,6 +1774,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_4_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; @@ -1872,6 +1873,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_3B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; phy-names = "pciephy"; @@ -1970,6 +1972,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_3A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; phy-names = "pciephy"; @@ -2071,6 +2074,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_2B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; phy-names = "pciephy"; @@ -2169,6 +2173,7 @@ reset-names = "pci"; power-domains = <&gcc PCIE_2A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; phy-names = "pciephy"; From 81051f14a66c3913f1d219bd97e47002f1dc91de Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 6 Mar 2024 10:56:51 +0100 Subject: [PATCH 012/969] arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. Note that using the GIC ITS on SC8280XP will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. This will specifically lead to notifications about Correctable Errors being logged for the Wi-Fi controller on the Lenovo ThinkPad X13s when ASPM L0s is enabled. Suggested-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20240306095651.4551-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index f42fc469af73..f3eb39f22702 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1731,6 +1731,8 @@ linux,pci-domain = <6>; num-lanes = <1>; + msi-map = <0x0 &its 0xe0000 0x10000>; + interrupts = , , , @@ -1832,6 +1834,8 @@ linux,pci-domain = <5>; num-lanes = <2>; + msi-map = <0x0 &its 0xd0000 0x10000>; + interrupts = , , , @@ -1931,6 +1935,8 @@ linux,pci-domain = <4>; num-lanes = <4>; + msi-map = <0x0 &its 0xc0000 0x10000>; + interrupts = , , , @@ -2033,6 +2039,8 @@ linux,pci-domain = <3>; num-lanes = <2>; + msi-map = <0x0 &its 0xb0000 0x10000>; + interrupts = , , , @@ -2132,6 +2140,8 @@ linux,pci-domain = <2>; num-lanes = <4>; + msi-map = <0x0 &its 0xa0000 0x10000>; + interrupts = , , , @@ -4804,7 +4814,7 @@ #size-cells = <2>; ranges; - msi-controller@17a40000 { + its: msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; From 91905d8368c69bea3fb85f5c76334274a232612d Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Sat, 2 Mar 2024 21:10:25 +0800 Subject: [PATCH 013/969] arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support Add usb pd negotiation, but charging is controlled by pm8150b pmic, so it can only charge battery with 5W, Signed-off-by: Jianhua Lu Link: https://lore.kernel.org/r/20240302131025.13741-1-lujianhua000@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 6f54f50a70b0..2042020eb0dd 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -636,7 +636,8 @@ connector { compatible = "usb-c-connector"; - power-role = "source"; + op-sink-microwatt = <10000000>; + power-role = "dual"; data-role = "dual"; self-powered; @@ -645,6 +646,12 @@ PDO_FIXED_USB_COMM | PDO_FIXED_DATA_SWAP)>; + sink-pdos = ; + ports { #address-cells = <1>; #size-cells = <0>; From dc6cb3854c44de4c7ac9fd173208f5d19ed5d882 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 7 Mar 2024 21:25:55 +0100 Subject: [PATCH 014/969] arm64: dts: qcom: sc8280xp: Add QFPROM node Describe the QFPROM NVMEM block. Also, add a subnode to represent the GPU speed bin region within it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-2-4eba20e08902@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index f3eb39f22702..eb19ae4e486f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -862,6 +862,18 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@18b { + reg = <0x18b 0x1>; + bits = <5 3>; + }; + }; + qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; From 865ff2e6f5daf4ea822120c873f4ba43eb2d8db7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 7 Mar 2024 21:25:56 +0100 Subject: [PATCH 015/969] arm64: dts: qcom: sc8280xp: Add PS_HOLD restart Killing the platform with a single write and no firmware involvement is pretty cool, add support for it. Note that due to restart notifier priority settings, PSCI reset will be used instead, unless: a) PSCI is not exposed by the firmware (e.g. because the fw was replaced) or b) PSCI restart fails for some reason Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-3-4eba20e08902@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index eb19ae4e486f..93f5c02b06da 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4475,6 +4475,11 @@ #thermal-sensor-cells = <1>; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0 0x0c264000 0 0x4>; + }; + tsens1: thermal-sensor@c265000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ From 27ef06ebd289992ad4469632b440cd0b072be562 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 7 Mar 2024 21:25:57 +0100 Subject: [PATCH 016/969] arm64: dts: qcom: sc8280xp: Describe TCSR download mode register To allow for swift EDL reboots, describe the respective register under the scm node. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-4-4eba20e08902@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 93f5c02b06da..9d54c63c20cd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -300,6 +300,7 @@ scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + qcom,dload-mode = <&tcsr 0x13000>; }; }; From 7d6d561fa934594faf359f6fffee0e2dd59f8110 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Sat, 9 Mar 2024 14:15:04 +0100 Subject: [PATCH 017/969] arm64: dts: qcom: qcm2290: Add LMH node Add a node for the Limits Management Hardware to ensure it can be configured by the operating system. Signed-off-by: Loic Poulain [Konrad: add commit msg, rebase] Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240308-topic-rb1_lmh-v2-3-bac3914b0fe3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 89beac833d43..1aacad50e7fc 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1858,7 +1858,7 @@ compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0x0 0x0f521000 0x0 0x1000>; reg-names = "freq-domain0"; - interrupts = ; + interrupts-extended = <&lmh_cluster 0>; interrupt-names = "dcvsh-irq-0"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; @@ -1866,6 +1866,18 @@ #freq-domain-cells = <1>; #clock-cells = <1>; }; + + lmh_cluster: lmh@f550800 { + compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; + reg = <0x0 0x0f550800 0x0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; }; thermal-zones { From d4fac32cbe95046bfe303a51dc2486db215cf86d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Feb 2024 15:27:23 +0100 Subject: [PATCH 018/969] arm64: dts: qcom: x1e80100: correct SWR1 pack mode Correct the SWR1 Soundwire controller port block pack mode to match reference code. Not sure if this has any impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227142725.625561-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 8e517f76189e..26d779ade489 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3088,7 +3088,7 @@ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; From 76cbe23e4399bc0130572981ab330e59d823696d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Feb 2024 15:27:24 +0100 Subject: [PATCH 019/969] arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio Each pair of WSA8845 speakers share the powerdown SD_N GPIO, thus this GPIO is specified twice in each WSA8845 device node. Such DTS was added hoping non-exclusive GPIO usage would be accepted, but it turned out otherwise: it is not supported by the Linux kernel. Linux kernel however supports sharing reset GPIOs, when used bia the reset controller framework as implemented in commit 26c8a435fce6 ("ASoC: dt-bindings: qcom,wsa8840: Add reset-gpios for shared line") and commit c721f189e89c ("reset: Instantiate reset GPIO controller for shared reset-gpios"). Convert the property with shutdown GPIO to "reset-gpios" to use mentioned Linux kernel feature. This allows to bring all four speakers out of reset. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227142725.625561-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 6a0a54532e5f..dfdb31227e8b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -683,13 +683,14 @@ &swr0 { status = "okay"; + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + /* WSA8845, Left Woofer */ left_woofer: speaker@0,0 { compatible = "sdw20217020400"; reg = <0 0>; - pinctrl-0 = <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -700,8 +701,7 @@ left_tweeter: speaker@0,1 { compatible = "sdw20217020400"; reg = <0 1>; - /* pinctrl in left_woofer node because of sharing the GPIO*/ - powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TwitterLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -734,13 +734,14 @@ &swr3 { status = "okay"; + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + /* WSA8845, Right Woofer */ right_woofer: speaker@0,0 { compatible = "sdw20217020400"; reg = <0 0>; - pinctrl-0 = <&spkr_23_sd_n_active>; - pinctrl-names = "default"; - powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -751,8 +752,7 @@ right_tweeter: speaker@0,1 { compatible = "sdw20217020400"; reg = <0 1>; - /* pinctrl in right_woofer node because of sharing the GPIO*/ - powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TwitterRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; From cf30987a9ae9a8a430f957f8516b2092f6bab29d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Feb 2024 15:27:25 +0100 Subject: [PATCH 020/969] arm64: defconfig: enable reset-gpio driver as module Qualcomm X1E80100-CRD board uses shared reset GPIOs for speakers: each pair out of four speakers share the GPIO. Enable the reset-gpio driver which handles such case seamlessly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227142725.625561-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3a879c86c56b..01ab8f65cb5c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1463,6 +1463,7 @@ CONFIG_PWM_VISCONTI=m CONFIG_SL28CPLD_INTC=y CONFIG_QCOM_PDC=y CONFIG_QCOM_MPM=y +CONFIG_RESET_GPIO=m CONFIG_RESET_IMX7=y CONFIG_RESET_QCOM_AOSS=y CONFIG_RESET_QCOM_PDC=m From 6e995a1b53444d09f7707f4f79b752213343b05c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 27 Feb 2024 09:39:54 -0800 Subject: [PATCH 021/969] arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making debug prints and regulator_summary impossible to reason about. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227-rb3gen2-regulator-names-v1-1-63ceb845dcc8@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 97824c769ba3..63ebe0774f1d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -153,129 +153,151 @@ vdd-l14-l16-supply = <&vreg_s8b_1p272>; vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; regulator-min-microvolt = <570070>; regulator-max-microvolt = <1050000>; }; vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = ; }; vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = ; }; vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = ; }; vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; regulator-min-microvolt = <752000>; regulator-max-microvolt = <820000>; regulator-initial-mode = ; }; reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; regulator-min-microvolt = <552000>; regulator-max-microvolt = <832000>; regulator-initial-mode = ; }; vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = ; }; vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = ; }; vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = ; }; vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -304,109 +326,128 @@ vdd-bob-supply = <&vph_pwr>; vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; }; vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <800000>; }; vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <1050000>; }; vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <800000>; }; vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; }; vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3540000>; regulator-initial-mode = ; }; vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <35440000>; regulator-initial-mode = ; }; vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = ; }; vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; }; From 033fbfa0eb60e519f50e97ef93baec270cd28a88 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 27 Feb 2024 13:53:04 +0100 Subject: [PATCH 022/969] arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 91d70eb70867 ("arm64: dts: qcom: sm8450: add fastrpc nodes") Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-1-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..92b052f7b20e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2363,6 +2363,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2665,6 +2666,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2731,6 +2733,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 49c50ad9e6cbaa6a3da59cdd85d4ffb354ef65f4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 27 Feb 2024 13:53:05 +0100 Subject: [PATCH 023/969] arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: d0c061e366ed ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes") Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-2-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3904348075f6..5cae8d773cec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4316,6 +4316,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -4454,6 +4455,7 @@ compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 039d379490eabf798baded4de2d698a7324ab7e6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 27 Feb 2024 13:53:06 +0100 Subject: [PATCH 024/969] arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-3-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ba72d8f38420..1bfcf069c9ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4845,6 +4845,8 @@ label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; @@ -5002,6 +5004,8 @@ label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; From 232490b925272d54dd91847a183bdbc2deec904b Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 8 Feb 2024 19:16:44 -0500 Subject: [PATCH 025/969] arm64: dts: qcom: sdm670-google-sargo: add panel Add the panel used in the Google Pixel 3a. Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20240209001639.387374-9-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm670-google-sargo.dts | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 32a7bd59e1ec..176b0119fe6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -441,6 +441,47 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1a_1p225>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e3fa7-ams559nk06"; + reg = <0>; + + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default>; + + power-supply = <&vreg_l6b_3p3>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm660l_gpios { vol_up_pin: vol-up-state { pins = "gpio7"; @@ -481,6 +522,29 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + panel_default: panel-default-state { + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mode-pins { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + touchscreen_default: ts-default-state { ts-reset-pins { pins = "gpio99"; From a5b150af2c6ad2749aee51edc36f9f9883869f5b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 8 Feb 2024 10:52:32 +0100 Subject: [PATCH 026/969] dt-bindings: soc: qcom: qcom,pmic-glink: document QCM6490 compatible Document the QCM6490 compatible used to describe the pmic glink on this platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240208-fp5-pmic-glink-v2-1-4837d4abd5a4@fairphone.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index d3f3259ef77d..4310bae6c58e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - qcom,qcm6490-pmic-glink - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink From 4aa609a922e3ce387d18d8e7327d3912f0a85653 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:55 +0200 Subject: [PATCH 027/969] arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path Fix GPU firmware path so it uses model-specific directory. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-2-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 0c22f3efec20..49b740c54674 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -350,7 +350,7 @@ zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; }; }; From 8c28575a4aba092feb5a5ca0b446eb8a0fa39396 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:56 +0200 Subject: [PATCH 028/969] arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes Set names, so they correspond to devices connected to these interfaces. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-3-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 49b740c54674..af61acf58d68 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -362,7 +362,7 @@ status = "okay"; - hid@10 { + touchscreen@10 { compatible = "hid-over-i2c"; reg = <0x10>; hid-descr-addr = <0x1>; @@ -379,7 +379,7 @@ status = "okay"; - hid@5 { + keyboard@5 { compatible = "hid-over-i2c"; reg = <0x5>; hid-descr-addr = <0x20>; @@ -387,7 +387,7 @@ interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; }; - hid@2c { + touchpad@2c { compatible = "hid-over-i2c"; reg = <0x2c>; hid-descr-addr = <0x20>; From 0d76ffe33e5eb5b0a7bd09e4fa8a72f7f4cfbc0d Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:57 +0200 Subject: [PATCH 029/969] arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes Split keyboard and touchpad pinctrl nodes since they are for different devices and move keyboard, touchpad and touchscreen pinctrl references to appropriate nodes. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-4-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 41 +++++++++++++------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index af61acf58d68..6ae6cb030b70 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -357,7 +357,7 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>; + pinctrl-0 = <&i2c1_active>; pinctrl-names = "default"; status = "okay"; @@ -368,13 +368,16 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; }; }; &i2c7 { clock-frequency = <100000>; - pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>; + pinctrl-0 = <&i2c7_active>; pinctrl-names = "default"; status = "okay"; @@ -385,6 +388,9 @@ hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kb_int_default>; + pinctrl-names = "default"; }; touchpad@2c { @@ -393,6 +399,9 @@ hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tp_int_default>; + pinctrl-names = "default"; }; }; @@ -669,14 +678,6 @@ drive-strength = <2>; }; - i2c1_hid_active: i2c1-hid-active-state { - pins = "gpio122"; - function = "gpio"; - - bias-pull-up; - drive-strength = <2>; - }; - i2c7_active: i2c7-active-state { pins = "gpio98", "gpio99"; function = "qup7"; @@ -685,8 +686,8 @@ drive-strength = <2>; }; - i2c7_hid_active: i2c7-hid-active-state { - pins = "gpio37", "gpio24"; + kb_int_default: kb-int-default-state { + pins = "gpio37"; function = "gpio"; bias-pull-up; @@ -718,6 +719,22 @@ }; }; + tp_int_default: tp-int-default-state { + pins = "gpio24"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio122"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + usbprim_sbu_default: usbprim-sbu-state { oe-n-pins { pins = "gpio152"; From 46c2f36e76a018c269d236ec1a1cca03fe5bb47b Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:59 +0200 Subject: [PATCH 030/969] arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz This solves the issue when touchpad gets stuck on right or middle click. This also makes touchpad working smoother. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-6-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6ae6cb030b70..5f07933183e1 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -375,7 +375,7 @@ }; &i2c7 { - clock-frequency = <100000>; + clock-frequency = <1000000>; pinctrl-0 = <&i2c7_active>; pinctrl-names = "default"; From 42ee55cb2e27d8bf3d26b8c4199727df029a5878 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:12:00 +0200 Subject: [PATCH 031/969] arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting The UFS driver expects to be able to set load (and by extension, mode) on the supplied regulators. Add the necessary properties to make that possible. Based on https://lore.kernel.org/r/20231214-topic-sc8180_fixes-v1-6-421904863006@linaro.org Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-7-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 5f07933183e1..6f2e1c732ed3 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -329,12 +329,18 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-allowed-modes = ; + regulator-allow-set-load; }; vreg_l10e_2p9: ldo10 { regulator-min-microvolt = <2904000>; regulator-max-microvolt = <2904000>; regulator-initial-mode = ; + regulator-allowed-modes = ; + regulator-allow-set-load; }; vreg_l16e_3p0: ldo16 { From f8627c303fd34ab70ff6fd8a1048ac11035b7fd6 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 15 Feb 2024 14:53:50 +0530 Subject: [PATCH 032/969] soc: qcom: qcom_stats: Add DSPs and apss subsystem stats Add SMEM items for compute, general purpose DSPs and application processor subsystem stats. Signed-off-by: Maulik Shah Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240215-qcom_stats-v1-1-4a2cf83d0bdd@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_stats.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 0216fc24f2ca..c429d5154aae 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -35,11 +35,15 @@ static const struct subsystem_data subsystems[] = { { "wpss", 605, 13 }, { "adsp", 606, 2 }, { "cdsp", 607, 5 }, + { "cdsp1", 607, 12 }, + { "gpdsp0", 607, 17 }, + { "gpdsp1", 607, 18 }, { "slpi", 608, 3 }, { "gpu", 609, 0 }, { "display", 610, 0 }, { "adsp_island", 613, 2 }, { "slpi_island", 613, 3 }, + { "apss", 631, QCOM_SMEM_HOST_ANY }, }; struct stats_config { From 343dfe6206b2793f7f5196b849dfbb4efcc5c048 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Mon, 19 Feb 2024 13:27:20 +0530 Subject: [PATCH 033/969] arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes Recent binding update [1] indicates that there are hs_phy_irq present in primary and secondary usb controllers of sc8280xp. Add the missing hs_phy_irq for these controllers. Since the driver doesn't use this interrupt, this change has been only compile tested. [1]: https://lore.kernel.org/all/20231227091951.685-2-quic_kriskura@quicinc.com/ Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240219075720.640529-1-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 9d54c63c20cd..75fa7ac5b60a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3389,10 +3389,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -3449,10 +3451,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; From fd5afa5d7e5259cb2320fbe2cf60250f7336f439 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 19 Feb 2024 11:16:02 +0100 Subject: [PATCH 034/969] arm64: dts: qcom: sm6350: Add Crypto Engine Add crypto engine (CE) and CE BAM related nodes and definitions for this SoC. For reference: [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1 Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240219-sm6350-qce-v2-1-7acb8838f248@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 24bcec3366ef..4864bd33e448 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1205,6 +1205,37 @@ status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; + iommus = <&apps_smmu 0x426 0x11>, + <&apps_smmu 0x432 0x0>, + <&apps_smmu 0x436 0x11>, + <&apps_smmu 0x438 0x1>, + <&apps_smmu 0x43f 0x0>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x426 0x11>, + <&apps_smmu 0x432 0x0>, + <&apps_smmu 0x436 0x11>, + <&apps_smmu 0x438 0x1>, + <&apps_smmu 0x43f 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm6350-ipa"; From 90053b1574f8cff3a3b53accc496246ad2e0aec3 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 20 Feb 2024 13:01:22 +0100 Subject: [PATCH 035/969] arm64: dts: qcom: sdm632-fairphone-fp3: enable USB-C port handling Add the definition for the USB-C connector found on this phone and hook up the relevant bits. This enables USB role switching. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240220-fp3-typec-v1-1-1930cad81139@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 14 +++++++++ .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 31 +++++++++++++++++-- 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index f1011bb641c6..5d818fe057dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1323,6 +1323,20 @@ snps,hird-threshold = /bits/ 8 <0x00>; maximum-speed = "high-speed"; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 057579ae3013..e2708c74e95a 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -116,6 +116,33 @@ }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + port { + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1000000>; + status = "okay"; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; @@ -240,8 +267,8 @@ status = "okay"; }; -&usb3_dwc3 { - dr_mode = "peripheral"; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; }; &wcnss { From 601feafa7dad3a1de094ea524b6c2e1315a738d2 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Tue, 20 Feb 2024 23:21:47 +0300 Subject: [PATCH 036/969] arm64: dts: qcom: pm6150: define USB-C related blocks Define VBUS regulator and the Type-C handling block as present on the Qualcomm PM6150 PMIC. Signed-off-by: Danila Tikhonov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240220202147.228911-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index ddbaf7280b03..11158c2bd524 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -63,6 +63,52 @@ }; }; + pm6150_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm6150-vbus-reg, + qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm6150_typec: typec@1500 { + compatible = "qcom,pm6150-typec, + qcom,pm8150b-typec"; + reg = <0x1500>, <0x1700>; + interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x01 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x03 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x06 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect", + "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + status = "disabled"; + }; + pm6150_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; From 53fdae5e086b699a66c6927395fa66c0116ec7ac Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:19 +0200 Subject: [PATCH 037/969] arm64: dts: qcom: x1e80100: Add SPMI support The X1E80100 platform implements the v7 SPMI arbiter, which means it implements two separate buses. The difference, when compared to existing platforms that also implement v7 SPMI arbiter, is that this is the first platform that actually has boards with secondary bus populated with some PMICs. This is why it needs to have 2 separate buses as child nodes of the arbiter. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-1-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 26d779ade489..fa04a24173a7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4221,6 +4221,48 @@ #clock-cells = <0>; }; + spmi: arbiter@c400000 { + compatible = "qcom,x1e80100-spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x400000>, + <0 0x0c440000 0 0x80000>; + reg-names = "core", "chnls", "obsrvr"; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg = <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c432000 { + reg = <0 0x0c432000 0 0x4000>, + <0 0x0c4d0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + }; tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; From 3298d47894b0f30a42a4f93c36dae4838f638dba Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:20 +0200 Subject: [PATCH 038/969] arm64: dts: qcom: x1e80100: Add dedicated pmic dtsi Add dedicated file for x1e80100 PMICs, add the all 3 smb2360 PMIC nodes with the eUSB2 repeater nodes. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-2-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 51 ++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi new file mode 100644 index 000000000000..04301f772fbd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include + +/ { +}; + +&spmi_bus1 { + smb2360_0: pmic@7 { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_0_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2360_1: pmic@a { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_1_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2360_2: pmic@b { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From 3930056f30d374967746876e01e8dca10fbc7ff9 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:21 +0200 Subject: [PATCH 039/969] arm64: dts: qcom: x1e80100-crd: Add repeater nodes Include the PMIC dedicated file and add regulators to each one of those 3 eUSB2 repeaters. Tie up the repeaters to their corresponding USB HS PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-3-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index dfdb31227e8b..d4198fa204fd 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -9,6 +9,7 @@ #include #include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; @@ -680,6 +681,21 @@ status = "okay"; }; +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + &swr0 { status = "okay"; @@ -817,6 +833,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_0_eusb2_repeater>; + status = "okay"; }; @@ -837,6 +855,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_1_eusb2_repeater>; + status = "okay"; }; @@ -857,6 +877,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_2_eusb2_repeater>; + status = "okay"; }; From 04124220d8ce77409a5fa8cdea75dc2be999c932 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:22 +0200 Subject: [PATCH 040/969] arm64: dts: qcom: x1e80100-qcp: Add repeater nodes Include the PMIC dedicated file and add regulators to each one of those 3 eUSB2 repeaters. Tie up the repeaters to their corresponding USB HS PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-4-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index e76d29053d79..35580ac3430d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -9,6 +9,7 @@ #include #include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 QCP"; @@ -491,6 +492,21 @@ status = "okay"; }; +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -513,6 +529,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_0_eusb2_repeater>; + status = "okay"; }; @@ -533,6 +551,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_1_eusb2_repeater>; + status = "okay"; }; @@ -553,6 +573,8 @@ vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_2_eusb2_repeater>; + status = "okay"; }; From 08429b4ef46080c79534c4eee427ee2e6012877c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Owoc?= Date: Thu, 29 Feb 2024 21:54:16 +0100 Subject: [PATCH 041/969] arm64: dts: qcom: ipq8074: Add QUP UART6 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node to support the QUP UART6 controller inside of IPQ8074. Used by some routers to communicate with a Bluetooth controller. Signed-off-by: Paweł Owoc Link: https://lore.kernel.org/r/20240229205426.232205-1-frut3k7@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 87a192de7a68..50f725053b96 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -323,6 +323,13 @@ bias-disable; }; + serial_5_pins: serial5-state { + pins = "gpio9", "gpio16"; + function = "blsp5_uart"; + drive-strength = <8>; + bias-disable; + }; + i2c_0_pins: i2c-0-state { pins = "gpio42", "gpio43"; function = "blsp1_i2c"; @@ -471,6 +478,18 @@ status = "disabled"; }; + blsp1_uart6: serial@78b4000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b4000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-0 = <&serial_5_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; From c39c5aed65d428f2a1c2364851c8b44702e9d7db Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 4 Mar 2024 11:26:11 +0200 Subject: [PATCH 042/969] arm64: dts: qcom: qrb2210-rb1: enable USB-C port handling Plug in USB-C related bits and pieces to enable USB role switching and USB-C orientation handling for the Qualcomm RB1 board. Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240304-pm4125-typec-v4-2-f3601a16f9ea@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 42 +++++++++++++++++ arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 60 ++++++++++++++++++++---- 2 files changed, 94 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 1aacad50e7fc..8221336a8212 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -694,10 +694,31 @@ clock-output-names = "usb3_phy_pipe_clk_src"; #phy-cells = <0>; + orientation-switch; qcom,tcsr-reg = <&tcsr_regs 0xb244>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; system_noc: interconnect@1880000 { @@ -1380,6 +1401,27 @@ snps,usb3_lpm_capable; maximum-speed = "super-speed"; dr_mode = "otg"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 6e9dd0312adc..fca341300521 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -262,6 +262,46 @@ status = "okay"; }; +&pm4125_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm4125_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pm4125_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -535,14 +575,8 @@ status = "okay"; }; -&usb_qmpphy { - vdda-phy-supply = <&pm4125_l12>; - vdda-pll-supply = <&pm4125_l13>; - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "host"; +&usb_dwc3_hs { + remote-endpoint = <&pm4125_hs_in>; }; &usb_hsphy { @@ -552,6 +586,16 @@ status = "okay"; }; +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + status = "okay"; +}; + +&usb_qmpphy_out { + remote-endpoint = <&pm4125_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; From 9b1e891179cacd12aa77d27a2c00b75fdbef4823 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Mon, 4 Mar 2024 14:41:15 -0800 Subject: [PATCH 043/969] arm64: dts: qcom: sm8650: Add missing reserved memory for chipinfo Add missing reserved memory for chipinfo region. Cc: Patrick Daly Cc: Neil Armstrong Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Elliot Berman Reviewed-by: Mukesh Ojha Link: https://lore.kernel.org/r/20240304-sm8650-missing-chipinfo-region-v1-1-8a0b41dd8308@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1bfcf069c9ae..32c0a7b9aded 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -485,9 +485,9 @@ no-map; }; - /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { - reg = <0 0x81c80000 0 0x74000>; + reg = <0 0x81c80000 0 0x75000>; no-map; }; From c0b9c616e881a1ea6b158dcad73e2198c483a56a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 6 Mar 2024 00:18:04 +0100 Subject: [PATCH 044/969] ARM: dts: qcom: msm8974pro-castor: Clean up formatting Clean up some easy things do prepare the dts for further changes. * Move pinctrl-names below pinctrl-* * Move status as last property * Remove default linux,input-type value Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240306-castor-changes-v1-1-2286eaf85fff@z3ntu.xyz Signed-off-by: Bjorn Andersson --- ...-msm8974pro-sony-xperia-shinano-castor.dts | 65 ++++++++----------- 1 file changed, 27 insertions(+), 38 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index ee94741a26ed..2db2ddf00580 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -23,34 +23,30 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; + pinctrl-names = "default"; key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = ; }; key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = ; }; key-camera-focus { label = "camera_focus"; gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = ; }; key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = ; }; }; @@ -67,8 +63,8 @@ vin-supply = <&pm8941_s3>; startup-delay-us = <70000>; - pinctrl-names = "default"; pinctrl-0 = <&lcd_backlight_en_pin_a>; + pinctrl-names = "default"; }; vreg_vsp: lcd-dcdc-regulator { @@ -80,8 +76,8 @@ gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-names = "default"; pinctrl-0 = <&lcd_dcdc_en_pin_a>; + pinctrl-names = "default"; }; vreg_boost: vreg-boost { @@ -121,8 +117,8 @@ gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; enable-active-high; - pinctrl-names = "default"; pinctrl-0 = <&wlan_regulator_pin>; + pinctrl-names = "default"; }; }; @@ -131,9 +127,10 @@ }; &blsp2_i2c2 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; + synaptics@2c { compatible = "syna,rmi4-i2c"; reg = <0x2c>; @@ -147,8 +144,8 @@ vdd-supply = <&pm8941_l22>; vio-supply = <&pm8941_lvs3>; - pinctrl-names = "default"; pinctrl-0 = <&ts_int_pin>; + pinctrl-names = "default"; syna,startup-delay-ms = <100>; @@ -166,9 +163,10 @@ }; &blsp2_i2c5 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; + lp8566_wled: backlight@2c { compatible = "ti,lp8556"; reg = <0x2c>; @@ -232,8 +230,8 @@ compatible = "brcm,bcm43438-bt"; max-speed = <3000000>; - pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_pin>, <&bt_dev_wake_pin>, <&bt_reg_on_pin>; + pinctrl-names = "default"; host-wakeup-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; device-wakeup-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; @@ -242,17 +240,16 @@ }; &pm8941_coincell { - status = "okay"; - qcom,rset-ohms = <2100>; qcom,vset-millivolts = <3000>; + + status = "okay"; }; &pm8941_gpios { gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio5"; function = "normal"; - bias-pull-up; power-source = ; }; @@ -260,7 +257,6 @@ bt_reg_on_pin: bt-reg-on-state { pins = "gpio16"; function = "normal"; - output-low; power-source = ; }; @@ -268,7 +264,6 @@ wlan_sleep_clk_pin: wl-sleep-clk-state { pins = "gpio17"; function = "func2"; - output-high; power-source = ; }; @@ -276,7 +271,6 @@ wlan_regulator_pin: wl-reg-active-state { pins = "gpio18"; function = "normal"; - bias-disable; power-source = ; }; @@ -284,20 +278,18 @@ lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { pins = "gpio20"; function = "normal"; - bias-disable; power-source = ; input-disable; output-low; }; - }; &pm8941_lpg { - status = "okay"; - qcom,power-source = <1>; + status = "okay"; + multi-led { color = ; function = LED_FUNCTION_STATUS; @@ -530,41 +522,38 @@ }; &sdhc_1 { - status = "okay"; - vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_on>; pinctrl-1 = <&sdc1_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; }; &sdhc_2 { - status = "okay"; - vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_on>; pinctrl-1 = <&sdc2_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; }; &sdhc_3 { - status = "okay"; - max-frequency = <100000000>; vmmc-supply = <&vreg_wlan>; non-removable; - pinctrl-names = "default"; pinctrl-0 = <&sdc3_on>; + pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; + status = "okay"; bcrmf@1 { compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; @@ -572,8 +561,8 @@ brcm,drive-strength = <10>; - pinctrl-names = "default"; pinctrl-0 = <&wlan_sleep_clk_pin>; + pinctrl-names = "default"; }; }; @@ -682,8 +671,6 @@ }; &usb { - status = "okay"; - phys = <&usb_hs1_phy>; phy-select = <&tcsr 0xb000 0>; extcon = <&smbb>, <&usb_id>; @@ -692,14 +679,16 @@ hnp-disable; srp-disable; adp-disable; + + status = "okay"; }; &usb_hs1_phy { - status = "okay"; - v1p8-supply = <&pm8941_l6>; v3p3-supply = <&pm8941_l24>; extcon = <&smbb>; qcom,init-seq = /bits/ 8 <0x1 0x64>; + + status = "okay"; }; From 0268bfec8ae06bc1091c2b9058287391872f8853 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 6 Mar 2024 00:18:05 +0100 Subject: [PATCH 045/969] ARM: dts: qcom: msm8974pro-castor: Add mmc aliases Add the mmc0 & mmc1 aliases to make sure internal storage always becomes /dev/mmcblk0 and SD card becomes /dev/mmcblk1 Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-castor-changes-v1-2-2286eaf85fff@z3ntu.xyz Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 2db2ddf00580..da554f72528a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -12,6 +12,8 @@ chassis-type = "tablet"; aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; serial0 = &blsp1_uart2; serial1 = &blsp2_uart1; }; From 26b950f2af40bd6cc36c3ac8ee6643ff3e905753 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 6 Mar 2024 00:18:06 +0100 Subject: [PATCH 046/969] ARM: dts: qcom: msm8974pro-castor: Remove camera button definitions >From what I can tell, the camera buttons are not part of Z2 Tablet hardware even though other devices based on 'shinano' do have them. Fixes: ab80661883de ("ARM: dts: qcom: msm8974: Add Sony Xperia Z2 Tablet") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240306-castor-changes-v1-3-2286eaf85fff@z3ntu.xyz Signed-off-by: Bjorn Andersson --- .../qcom-msm8974pro-sony-xperia-shinano-castor.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index da554f72528a..97b55bda9189 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -34,18 +34,6 @@ linux,code = ; }; - key-camera-snapshot { - label = "camera_snapshot"; - gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-camera-focus { - label = "camera_focus"; - gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; From ead56f2e68b874c3549a67c6ae0c6186f780bf2f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 6 Mar 2024 00:18:07 +0100 Subject: [PATCH 047/969] ARM: dts: qcom: msm8974pro-castor: Add debounce-interval for keys Set the debounce-interval for the GPIO keys. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-castor-changes-v1-4-2286eaf85fff@z3ntu.xyz Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 97b55bda9189..c9f74bf2f8bd 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -32,12 +32,14 @@ label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,code = ; + debounce-interval = <15>; }; key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,code = ; + debounce-interval = <15>; }; }; From b756001175b1145a4855c8cfa77ceec78350c36a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 6 Mar 2024 00:18:08 +0100 Subject: [PATCH 048/969] ARM: dts: qcom: msm8974pro-castor: Rename wifi node name Give the wifi node a generic node name 'wifi'. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-castor-changes-v1-5-2286eaf85fff@z3ntu.xyz Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index c9f74bf2f8bd..20f98a9e49ea 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -547,7 +547,7 @@ status = "okay"; - bcrmf@1 { + wifi@1 { compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; reg = <1>; From 511b4858dc8a1b4d857dc847976a5481c9b367fa Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Mon, 11 Mar 2024 18:09:31 +0800 Subject: [PATCH 049/969] arm64: dts: qcom: qcm6490-idp: enable PMIC Volume and Power buttons The Volume Down & Power buttons are controlled by the PMIC via the PON hardware, and the Volume Up is connected to a PMIC gpio. Enable the necessary hardware and setup the GPIO state for the Volume Up gpio key. Signed-off-by: Hui Liu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240311-gpio-keys-v5-1-08823582f6c9@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 5bbe8aa63927..f8f8a43f638d 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include #include #include #include @@ -59,6 +60,22 @@ pinctrl-names = "default"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -511,6 +528,16 @@ }; }; +&pm7325_gpios { + key_vol_up_default: key-vol-up-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; +}; + &pm8350c_pwm { pinctrl-0 = <&pmic_lcd_bl_pwm>; pinctrl-names = "default"; @@ -540,6 +567,15 @@ }; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From 67a6a98575974416834c2294853b3814376a7ce7 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sat, 9 Mar 2024 05:24:42 +0100 Subject: [PATCH 050/969] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK3328 Add missing cache information to the Rockchip RK3328 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper RK3328 cache information. While there, use a more self-descriptive label for the L2 cache node, which also makes it more consistent with other SoC dtsi files. The cache parameters for the RK3328 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets, official vendor websites, and technical reference manuals: - Rockchip RK3328 datasheet, version 1.4 - https://opensource.rock-chips.com/wiki_RK3328, accessed on 2024-02-28 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 256 KB of unified L2 16-way, set-associative cache The RK3328 SoC dtsi is also used for the single RK3318-based supported board. Unfortunately, no datasheet is available for the RK3318, but some unofficial sources state that its L2 cache size is the same as RK3328's, so it's perhaps safe to assume the same for the L1 instruction and data cache sizes. Reviewed-by: Anand Moon Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/a681b3c6dbf7b25b1527b11cea5ae0d6d1733714.1709958234.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 37 ++++++++++++++++++++---- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b6f045069ee2..07dcc949b899 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -46,8 +46,14 @@ cpu-idle-states = <&CPU_SLEEP>; dynamic-power-coefficient = <120>; enable-method = "psci"; - next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -59,8 +65,14 @@ cpu-idle-states = <&CPU_SLEEP>; dynamic-power-coefficient = <120>; enable-method = "psci"; - next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -72,8 +84,14 @@ cpu-idle-states = <&CPU_SLEEP>; dynamic-power-coefficient = <120>; enable-method = "psci"; - next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -85,8 +103,14 @@ cpu-idle-states = <&CPU_SLEEP>; dynamic-power-coefficient = <120>; enable-method = "psci"; - next-level-cache = <&l2>; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; idle-states { @@ -102,10 +126,13 @@ }; }; - l2: l2-cache0 { + l2_cache: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; }; }; From 8612169a05c5e979af033868b7a9b177e0f9fcdf Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Sat, 9 Mar 2024 05:25:06 +0100 Subject: [PATCH 051/969] arm64: dts: rockchip: Add cache information to the SoC dtsi for RK356x Add missing cache information to the Rockchip RK356x SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper RK3566 and RK3568 cache information. Adding the cache information to the RK356x SoC dtsi also makes the following warning message in the kernel log go away: cacheinfo: Unable to detect cache hierarchy for CPU 0 The cache parameters for the RK356x dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Rockchip RK3566 datasheet, version 1.1 - Rockchip RK3568 datasheet, version 1.3 - ARM Cortex-A55 revision r1p0 TRM, version 0100-00 - ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02 For future reference, here's a rather detailed summary of the documentation, which applies to both Rockchip RK3566 and RK3568 SoCs: - All caches employ the 64-byte cache line length - Each Cortex-A55 core has 32 KB of L1 4-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - There are no L2 caches, which are per-core and private in Cortex-A55, because it belongs to the ARM DynamIQ IP core lineup - The entire SoC has 512 KB of unified L3 16-way, set-associative cache, which is shared among all four Cortex-A55 CPU cores - Cortex-A55 cores can be configured without private per-core L2 caches, in which case the shared L3 cache appears to them as an L2 cache; this is the case for the RK356x SoCs, so let's use "cache-level = <2>" to prevent the "huh, no L2 caches, but an L3 cache?" confusion among the users viewing the data presented to the userspace; another option could be to have additional 0 KB L2 caches defined, which may be technically correct, but would probably be even more confusing Helped-by: Anand Moon Tested-By: Diederik de Haas Reviewed-by: Anand Moon Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/2dee6dad8460b0c5f3b5da53cf55f735840efef1.1709957777.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 92f96ec01385..d8543b5557ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -57,6 +57,13 @@ #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; }; cpu1: cpu@100 { @@ -66,6 +73,13 @@ #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; }; cpu2: cpu@200 { @@ -75,6 +89,13 @@ #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; }; cpu3: cpu@300 { @@ -84,9 +105,29 @@ #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l3_cache>; }; }; + /* + * There are no private per-core L2 caches, but only the + * L3 cache that appears to the CPU cores as L2 caches + */ + l3_cache: l3-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; From ad7c5ebead13323ac4a45e01bda0609629523076 Mon Sep 17 00:00:00 2001 From: Xiu Jianfeng Date: Thu, 21 Mar 2024 13:17:33 +0000 Subject: [PATCH 052/969] mm/slub: remove dummy slabinfo functions The SLAB implementation has been removed since 6.8, so there is no other version of slabinfo_show_stats() and slabinfo_write(), then we can remove these two dummy functions. Signed-off-by: Xiu Jianfeng Acked-by: David Rientjes Signed-off-by: Vlastimil Babka --- mm/slab.h | 3 --- mm/slab_common.c | 2 -- mm/slub.c | 10 ---------- 3 files changed, 15 deletions(-) diff --git a/mm/slab.h b/mm/slab.h index d2bc9b191222..78e205b46e19 100644 --- a/mm/slab.h +++ b/mm/slab.h @@ -496,9 +496,6 @@ struct slabinfo { }; void get_slabinfo(struct kmem_cache *s, struct slabinfo *sinfo); -void slabinfo_show_stats(struct seq_file *m, struct kmem_cache *s); -ssize_t slabinfo_write(struct file *file, const char __user *buffer, - size_t count, loff_t *ppos); #ifdef CONFIG_SLUB_DEBUG #ifdef CONFIG_SLUB_DEBUG_ON diff --git a/mm/slab_common.c b/mm/slab_common.c index f5234672f03c..67c03d6bd26c 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -1078,7 +1078,6 @@ static void cache_show(struct kmem_cache *s, struct seq_file *m) sinfo.limit, sinfo.batchcount, sinfo.shared); seq_printf(m, " : slabdata %6lu %6lu %6lu", sinfo.active_slabs, sinfo.num_slabs, sinfo.shared_avail); - slabinfo_show_stats(m, s); seq_putc(m, '\n'); } @@ -1155,7 +1154,6 @@ static const struct proc_ops slabinfo_proc_ops = { .proc_flags = PROC_ENTRY_PERMANENT, .proc_open = slabinfo_open, .proc_read = seq_read, - .proc_write = slabinfo_write, .proc_lseek = seq_lseek, .proc_release = seq_release, }; diff --git a/mm/slub.c b/mm/slub.c index 1bb2a93cf7b6..cc7e68fbdbba 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -7099,14 +7099,4 @@ void get_slabinfo(struct kmem_cache *s, struct slabinfo *sinfo) sinfo->objects_per_slab = oo_objects(s->oo); sinfo->cache_order = oo_order(s->oo); } - -void slabinfo_show_stats(struct seq_file *m, struct kmem_cache *s) -{ -} - -ssize_t slabinfo_write(struct file *file, const char __user *buffer, - size_t count, loff_t *ppos) -{ - return -EIO; -} #endif /* CONFIG_SLUB_DEBUG */ From 87654cf7a9865c0be256d67229b7354125d7498e Mon Sep 17 00:00:00 2001 From: linke li Date: Thu, 21 Mar 2024 11:48:15 +0800 Subject: [PATCH 053/969] mm/slub: mark racy accesses on slab->slabs The reads of slab->slabs are racy because it may be changed by put_cpu_partial concurrently. In slabs_cpu_partial_show() and show_slab_objects(), slab->slabs is only used for showing information. Data-racy reads from shared variables that are used only for diagnostic purposes should typically use data_race(), since it is normally not a problem if the values are off by a little. This patch is aimed at reducing the number of benign races reported by KCSAN in order to focus future debugging effort on harmful races. Signed-off-by: linke li Reviewed-by: Chengming Zhou Signed-off-by: Vlastimil Babka --- mm/slub.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/mm/slub.c b/mm/slub.c index cc7e68fbdbba..d35d91877625 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -6036,7 +6036,7 @@ static ssize_t show_slab_objects(struct kmem_cache *s, else if (flags & SO_OBJECTS) WARN_ON_ONCE(1); else - x = slab->slabs; + x = data_race(slab->slabs); total += x; nodes[node] += x; } @@ -6241,7 +6241,7 @@ static ssize_t slabs_cpu_partial_show(struct kmem_cache *s, char *buf) slab = slub_percpu_partial(per_cpu_ptr(s->cpu_slab, cpu)); if (slab) - slabs += slab->slabs; + slabs += data_race(slab->slabs); } #endif @@ -6255,7 +6255,7 @@ static ssize_t slabs_cpu_partial_show(struct kmem_cache *s, char *buf) slab = slub_percpu_partial(per_cpu_ptr(s->cpu_slab, cpu)); if (slab) { - slabs = READ_ONCE(slab->slabs); + slabs = data_race(slab->slabs); objects = (slabs * oo_objects(s->oo)) / 2; len += sysfs_emit_at(buf, len, " C%d=%d(%d)", cpu, objects, slabs); From 5c794301eb4e5373822e8898661bacdc7f46ba14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 8 Mar 2024 09:51:17 +0100 Subject: [PATCH 054/969] tee: optee: smc: Convert to platform remove callback returning void MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- drivers/tee/optee/smc_abi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index a37f87087e5c..c82b7b88991d 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -1433,7 +1433,7 @@ static optee_invoke_fn *get_invoke_func(struct device *dev) * optee_remove is called by platform subsystem to alert the driver * that it should release the device */ -static int optee_smc_remove(struct platform_device *pdev) +static void optee_smc_remove(struct platform_device *pdev) { struct optee *optee = platform_get_drvdata(pdev); @@ -1453,8 +1453,6 @@ static int optee_smc_remove(struct platform_device *pdev) memunmap(optee->smc.memremaped_shm); kfree(optee); - - return 0; } /* optee_shutdown - Device Removal Routine @@ -1806,7 +1804,7 @@ MODULE_DEVICE_TABLE(of, optee_dt_match); static struct platform_driver optee_driver = { .probe = optee_probe, - .remove = optee_smc_remove, + .remove_new = optee_smc_remove, .shutdown = optee_shutdown, .driver = { .name = "optee", From 87d8e522d6f5a004f0aa06c0def302df65aff296 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Mar 2024 19:31:02 +0100 Subject: [PATCH 055/969] ARM: dts: samsung: smdkv310: fix keypad no-autorepeat Although the Samsung SoC keypad binding defined linux,keypad-no-autorepeat property, Linux driver never implemented it and always used linux,input-no-autorepeat. Correct the DTS to use property actually implemented. This also fixes dtbs_check errors like: exynos4210-smdkv310.dtb: keypad@100a0000: 'linux,keypad-no-autorepeat' does not match any of the regexes: '^key-[0-9a-z]+$', 'pinctrl-[0-9]+' Cc: Fixes: 0561ceabd0f1 ("ARM: dts: Add intial dts file for EXYNOS4210 SoC, SMDKV310 and ORIGEN") Link: https://lore.kernel.org/r/20240312183105.715735-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts index b566f878ed84..18f4f494093b 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts @@ -88,7 +88,7 @@ &keypad { samsung,keypad-num-rows = <2>; samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; + linux,input-no-autorepeat; wakeup-source; pinctrl-names = "default"; pinctrl-0 = <&keypad_rows &keypad_cols>; From 88208d3cd79821117fd3fb80d9bcab618467d37b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Mar 2024 19:31:03 +0100 Subject: [PATCH 056/969] ARM: dts: samsung: exynos4412-origen: fix keypad no-autorepeat Although the Samsung SoC keypad binding defined linux,keypad-no-autorepeat property, Linux driver never implemented it and always used linux,input-no-autorepeat. Correct the DTS to use property actually implemented. This also fixes dtbs_check errors like: exynos4412-origen.dtb: keypad@100a0000: 'linux,keypad-no-autorepeat' does not match any of the regexes: '^key-[0-9a-z]+$', 'pinctrl-[0-9]+' Cc: Fixes: bd08f6277e44 ("ARM: dts: Add keypad entries to Exynos4412 based Origen") Link: https://lore.kernel.org/r/20240312183105.715735-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos4412-origen.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos4412-origen.dts b/arch/arm/boot/dts/samsung/exynos4412-origen.dts index 23b151645d66..10ab7bc90f50 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-origen.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-origen.dts @@ -453,7 +453,7 @@ &keypad { samsung,keypad-num-rows = <3>; samsung,keypad-num-columns = <2>; - linux,keypad-no-autorepeat; + linux,input-no-autorepeat; wakeup-source; pinctrl-0 = <&keypad_rows &keypad_cols>; pinctrl-names = "default"; From 4ac4c1d794e7ff454d191bbdab7585ed8dbf3758 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Mar 2024 19:31:04 +0100 Subject: [PATCH 057/969] ARM: dts: samsung: smdk4412: fix keypad no-autorepeat Although the Samsung SoC keypad binding defined linux,keypad-no-autorepeat property, Linux driver never implemented it and always used linux,input-no-autorepeat. Correct the DTS to use property actually implemented. This also fixes dtbs_check errors like: exynos4412-smdk4412.dtb: keypad@100a0000: 'key-A', 'key-B', 'key-C', 'key-D', 'key-E', 'linux,keypad-no-autorepeat' do not match any of the regexes: '^key-[0-9a-z]+$', 'pinctrl-[0-9]+' Cc: Fixes: c9b92dd70107 ("ARM: dts: Add keypad entries to SMDK4412") Link: https://lore.kernel.org/r/20240312183105.715735-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts index 715dfcba1417..e16df9e75fcb 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts @@ -69,7 +69,7 @@ &keypad { samsung,keypad-num-rows = <3>; samsung,keypad-num-columns = <8>; - linux,keypad-no-autorepeat; + linux,input-no-autorepeat; wakeup-source; pinctrl-0 = <&keypad_rows &keypad_cols>; pinctrl-names = "default"; From ad722fc2ed6f056ba6c49bf161cf45a3e1b88853 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Mar 2024 19:31:05 +0100 Subject: [PATCH 058/969] ARM: dts: samsung: smdk4412: align keypad node names with dtschema DT schema expects certain node names, as pointed out but dtbs_check: exynos4412-smdk4412.dtb: keypad@100a0000: 'key-A', 'key-B', 'key-C', 'key-D', 'key-E' do not match any of the regexes: '^key-[0-9a-z]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20240312183105.715735-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts index e16df9e75fcb..c83fb250e664 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-smdk4412.dts @@ -105,31 +105,31 @@ linux,code = <6>; }; - key-A { + key-a { keypad,row = <2>; keypad,column = <6>; linux,code = <30>; }; - key-B { + key-b { keypad,row = <2>; keypad,column = <7>; linux,code = <48>; }; - key-C { + key-c { keypad,row = <0>; keypad,column = <5>; linux,code = <46>; }; - key-D { + key-d { keypad,row = <2>; keypad,column = <5>; linux,code = <32>; }; - key-E { + key-e { keypad,row = <0>; keypad,column = <7>; linux,code = <18>; From 75d7fa24772d0d7f78aff9eff013b3e2bcce3335 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 13 Mar 2024 19:30:11 +0100 Subject: [PATCH 059/969] ARM: dts: samsung: exynos5800-peach-pi: switch to undeprecated DP HPD GPIOs 'samsung,hpd-gpio' property is deprecated and uses also deprecated 'gpio' suffix which is not matched by dtbs_check: exynos5800-peach-pi.dtb: dp-controller@145b0000: 'samsung,hpd-gpio' does not match any of the regexes: 'pinctrl-[0-9]+' Switch to hpd-gpios property. Link: https://lore.kernel.org/r/20240313183011.14253-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts index 9bbbdce9103a..bb019868b996 100644 --- a/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/samsung/exynos5800-peach-pi.dts @@ -185,7 +185,7 @@ samsung,color-depth = <1>; samsung,link-rate = <0x0a>; samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; ports { port { From e8b41d201f82127b05bee204db92e7f97c65cf8e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 13 Mar 2024 20:11:47 +0100 Subject: [PATCH 060/969] ARM: dts: samsung: s5pv210: align onenand node name with bindings Bindings expect NAND controllers to match certain pattern: s5pv210-fascinate4g.dtb: onenand@b0600000: $nodename:0: 'onenand@b0600000' does not match '^nand-controller(@.*)?' Link: https://lore.kernel.org/r/20240313191148.21792-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi index ed560c9a3aa1..23459430410f 100644 --- a/arch/arm/boot/dts/samsung/s5pv210.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -72,7 +72,7 @@ #size-cells = <1>; ranges; - onenand: onenand@b0600000 { + onenand: nand-controller@b0600000 { compatible = "samsung,s5pv210-onenand"; reg = <0xb0600000 0x2000>, <0xb0000000 0x20000>, From 3a64e95e1a64a2d4c63c4df28b61cd3cbb63cd92 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 13 Mar 2024 20:11:48 +0100 Subject: [PATCH 061/969] ARM: dts: samsung: s5pv210: correct onenand size-cells Children of NAND controllers have only chip select, so address without the size. Correct size-cells as reported by dtbs_check: s5pv210-galaxys.dtb: onenand@b0600000: #size-cells:0:0: 0 was expected Link: https://lore.kernel.org/r/20240313191148.21792-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi index 23459430410f..9720573d84dc 100644 --- a/arch/arm/boot/dts/samsung/s5pv210.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -82,7 +82,7 @@ clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; clock-names = "bus", "onenand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; status = "disabled"; }; From 43dc9f88ff4db5c932cfb35cfe4bfeff25ed60e2 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:43 +0000 Subject: [PATCH 062/969] ARM: dts: samsung: exynos3250: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos3250.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 a 64 byte FIFO depth. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos3250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos3250.dtsi b/arch/arm/boot/dts/samsung/exynos3250.dtsi index 3f1015edab43..b6c3826a9424 100644 --- a/arch/arm/boot/dts/samsung/exynos3250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos3250.dtsi @@ -826,6 +826,7 @@ samsung,spi-src-clk = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; status = "disabled"; }; @@ -842,6 +843,7 @@ samsung,spi-src-clk = <0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; status = "disabled"; }; From f743fedc881b38a62ee47d752e59ab1ddb247052 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:44 +0000 Subject: [PATCH 063/969] ARM: dts: samsung: exynos4: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos4.dtsi defines the following SPI aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos4.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4.dtsi b/arch/arm/boot/dts/samsung/exynos4.dtsi index 7f981b5c0d64..ed47d0ce04e1 100644 --- a/arch/arm/boot/dts/samsung/exynos4.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4.dtsi @@ -621,6 +621,7 @@ clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; status = "disabled"; }; @@ -636,6 +637,7 @@ clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; status = "disabled"; }; @@ -651,6 +653,7 @@ clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; + fifo-depth = <64>; status = "disabled"; }; From a0f87a269f660cb41c2b38041183e3e31c69818d Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:45 +0000 Subject: [PATCH 064/969] ARM: dts: samsung: exynos5250: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos5250.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-4-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos5250.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi index 99c84bebf25a..b9e7c4938818 100644 --- a/arch/arm/boot/dts/samsung/exynos5250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -511,6 +511,7 @@ clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; + fifo-depth = <256>; }; spi_1: spi@12d30000 { @@ -526,6 +527,7 @@ clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; + fifo-depth = <64>; }; spi_2: spi@12d40000 { @@ -541,6 +543,7 @@ clock-names = "spi", "spi_busclk0"; pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; + fifo-depth = <64>; }; mmc_0: mmc@12200000 { From cc8e49917ca8a3a939d303a7103b9d30ed7d0873 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:46 +0000 Subject: [PATCH 065/969] ARM: dts: samsung: exynos5420: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. exynos5420.dtsi defines the following aliases: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos4210-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, Thus spi0 was considered having a 256 byte FIFO depth, and spi1 and spi2 having 64 byte FIFO depth each. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5420.dtsi b/arch/arm/boot/dts/samsung/exynos5420.dtsi index 25ed90374679..196c6d04675a 100644 --- a/arch/arm/boot/dts/samsung/exynos5420.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5420.dtsi @@ -658,6 +658,7 @@ pinctrl-0 = <&spi0_bus>; clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; + fifo-depth = <256>; status = "disabled"; }; @@ -674,6 +675,7 @@ pinctrl-0 = <&spi1_bus>; clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; + fifo-depth = <64>; status = "disabled"; }; @@ -690,6 +692,7 @@ pinctrl-0 = <&spi2_bus>; clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; + fifo-depth = <64>; status = "disabled"; }; From 65993c76e64a2fa71ffd05ce260f553d1b3e904f Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:47 +0000 Subject: [PATCH 066/969] arm64: dts: exynos5433: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depthj Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. The FIFO depth were determined based on the SPI aliases that are defined in exynos5433-tm2-common.dtsi: spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; spi-s3c64xx.c driver defines the following fifo_lvl_mask for the "samsung,exynos5433-spi" compatible: .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, Thus spi{0, 4} were considered having 256 byte FIFO depths, and spi{1, 2, 3} having 64 byte FIFO depths. Update device tree with these FIFO depths. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7fbbec04bff0..0b9053b9b2b5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1468,6 +1468,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; num-cs = <1>; + fifo-depth = <256>; status = "disabled"; }; @@ -1487,6 +1488,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1506,6 +1508,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1525,6 +1528,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi3_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; @@ -1544,6 +1548,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi4_bus>; num-cs = <1>; + fifo-depth = <64>; status = "disabled"; }; From b115751fddaf31a0367c19bf080dddcb928a109a Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:48 +0000 Subject: [PATCH 067/969] arm64: dts: exynosautov9: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. There are no SPI aliases defined, thus the FIFO depth was determined by matching the FIFO depth of the I2C node of the same USI parent. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-7-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index c871a2f49fda..0248329da49a 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -435,6 +435,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -526,6 +527,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -617,6 +619,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -708,6 +711,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -799,6 +803,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -890,6 +895,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -981,6 +987,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -1072,6 +1079,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1163,6 +1171,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1254,6 +1263,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1345,6 +1355,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; @@ -1434,6 +1445,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; From d2c81a9b6acc9ad6fa1a97bf21939adad1882dfa Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 16 Feb 2024 14:04:49 +0000 Subject: [PATCH 068/969] ARM: dts: samsung: s5pv210: specify the SPI FIFO depth Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO depth. Drop the dependency on the SPI alias and specify the SPI FIFO depth directly into the SPI node. The SPI nodes defined in s5pv210.dtsi are not enabled in any board file. No SPI aliases are defined, thus choose the FIFO depth using common sense: index 0 of the array for spi0, and index 1 for spi1. No functional change expected. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240216140449.2564625-8-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/s5pv210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/samsung/s5pv210.dtsi b/arch/arm/boot/dts/samsung/s5pv210.dtsi index 9720573d84dc..34e8a3d5efa5 100644 --- a/arch/arm/boot/dts/samsung/s5pv210.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210.dtsi @@ -161,6 +161,7 @@ pinctrl-0 = <&spi0_bus>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <256>; status = "disabled"; }; @@ -177,6 +178,7 @@ pinctrl-0 = <&spi1_bus>; #address-cells = <1>; #size-cells = <0>; + fifo-depth = <64>; status = "disabled"; }; From 0b45bd8491ee2efeae80848111b0c088602fc720 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 3 Jan 2024 15:20:51 +0100 Subject: [PATCH 069/969] arm64: dts: juno: fix thermal zone node names Linux kernel uses thermal zone node name during registering thermal zones and has a hard-coded limit of 20 characters, including terminating NUL byte. Exceeding the limit will cause failure to configure thermal zone. Reported-by: Rob Herring Closes: https://lore.kernel.org/all/CAL_JsqKogbT_4DPd1n94xqeHaU_J8ve5K09WOyVsRX3jxxUW3w@mail.gmail.com/ Fixes: fb4d25d7a33f ("arm64: dts: juno: Align thermal zone names with bindings") Reviewed-by: Rob Herring Acked-by: Sudeep Holla Link: https://lore.kernel.org/r/20240103142051.111717-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/arm/juno-base.dtsi | 4 ++-- arch/arm64/boot/dts/arm/juno-scmi.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index b897f5542c0a..98ed2b329ed6 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -773,14 +773,14 @@ }; }; - big_cluster_thermal_zone: big-cluster-thermal { + big_cluster_thermal_zone: big-cl-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 21>; status = "disabled"; }; - little_cluster_thermal_zone: little-cluster-thermal { + little_cluster_thermal_zone: little-cl-thermal { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 22>; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index 31929e2377d8..f38c5b6ef657 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -84,11 +84,11 @@ thermal-sensors = <&scmi_sensors0 3>; }; - big-cluster-thermal { + big-cl-thermal { thermal-sensors = <&scmi_sensors0 21>; }; - little-cluster-thermal { + little-cl-thermal { thermal-sensors = <&scmi_sensors0 22>; }; From e23359d88a81679e7c55d221e7cb4c39abf5d760 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Mar 2024 20:03:48 +0100 Subject: [PATCH 070/969] dt-bindings: memory-controllers: add Samsung S5Pv210 SoC DMC Document bindings for the S5Pv210 SoC DMC memory controller, already used in DTS and Linux CPU frequency scaling driver. The binding looks quite empty and is most likely incomplete, but the platform is so old that no one expects any effort on this, except documenting what is in DTS. Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20240312190348.724361-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../samsung,s5pv210-dmc.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/samsung,s5pv210-dmc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,s5pv210-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,s5pv210-dmc.yaml new file mode 100644 index 000000000000..c0e47055f28c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,s5pv210-dmc.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/samsung,s5pv210-dmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5Pv210 SoC Dynamic Memory Controller + +maintainers: + - Krzysztof Kozlowski + +description: + Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM. + +properties: + compatible: + const: samsung,s5pv210-dmc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@f0000000 { + compatible = "samsung,s5pv210-dmc"; + reg = <0xf0000000 0x1000>; + }; From 4b660dbd9ee2059850fd30e0df420ca7a38a1856 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Feb 2024 11:53:14 +0100 Subject: [PATCH 071/969] arm64: dts: amd: use capital "OR" for multiple licenses in SPDX Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Link: https://lore.kernel.org/r/20240208105314.129095-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amd/elba-16core.dtsi | 2 +- arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 2 +- arch/arm64/boot/dts/amd/elba-asic.dts | 2 +- arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 2 +- arch/arm64/boot/dts/amd/elba.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi index 568bcc39ce9f..6c1b7b8fe354 100644 --- a/arch/arm64/boot/dts/amd/elba-16core.dtsi +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2023 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi index 46b6c6783f58..d12e9a7b5587 100644 --- a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2022 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts index c3f4da2f7449..20b0fa0807a1 100644 --- a/arch/arm64/boot/dts/amd/elba-asic.dts +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Device Tree file for AMD Pensando Elba Board. * diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi index cf761a05a81f..6ea2d777c8c9 100644 --- a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2023 Advanced Micro Devices, Inc. */ diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi index 674890cf2a34..758bce0a0b2a 100644 --- a/arch/arm64/boot/dts/amd/elba.dtsi +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* * Copyright 2020-2022 Advanced Micro Devices, Inc. */ From 93e09fdceed1aefd3546fda927805b8306d49e0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Sat, 24 Feb 2024 20:19:02 +0100 Subject: [PATCH 072/969] arm64: dts: renesas: eagle: Add capture overlay for Function expansion board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Eagle board supports an optional "Function expansion board". The expansion board adds support for HDMI OUT, HDMI capture from two different sources, and eMMC. This change only adds support for the two HDMI capture sources. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240224191902.2065733-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 + .../r8a77970-eagle-function-expansion.dtso | 214 ++++++++++++++++++ 2 files changed, 217 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5f3e0e61d78d..fbd214a1a638 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -62,6 +62,9 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb +dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtbo +r8a77970-eagle-function-expansion-dtbs := r8a77970-eagle.dtb r8a77970-eagle-function-expansion.dtbo +dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle-function-expansion.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso new file mode 100644 index 000000000000..3aa243c5f04c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle-function-expansion.dtso @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Eagle V3M Function expansion board. + * + * Copyright (C) 2024 Niklas Söderlund + */ + +/dts-v1/; +/plugin/; + +#include +#include + +/ { + /* CN4 */ + /* Eagle: SW18 set to OFF */ + cvbs-in-cn4 { + compatible = "composite-video-connector"; + label = "CVBS IN CN4"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + /* CN2 */ + /* Eagle: SW35 set 5, 6 and 8 to OFF */ + hdmi-in-cn2 { + compatible = "hdmi-connector"; + label = "HDMI IN CN2"; + type = "a"; + + port { + hdmi_in_con2: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + + /* CN3 */ + /* Eagle: SW18 set to OFF */ + hdmi-in-cn3 { + compatible = "hdmi-connector"; + label = "HDMI IN CN3"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; +}; + +/* Disconnect MAX9286 GMSL I2C. */ +&i2c3 { + status = "disabled"; +}; + +/* Connect expansion board I2C. */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + gpio@27 { + compatible = "onnn,pca9654"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + + vin0_adv7612_en { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-high; + line-name = "VIN0_ADV7612_ENn"; + }; + }; + + hdmi-decoder@4c { + compatible = "adi,adv7612"; + reg = <0x4c>, <0x50>, <0x52>, <0x54>, <0x56>, <0x58>; + reg-names = "main", "afe", "rep", "edid", "hdmi", "cp"; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7612_in: endpoint { + remote-endpoint = <&hdmi_in_con2>; + }; + }; + + port@2 { + reg = <2>; + + adv7612_out: endpoint { + remote-endpoint = <&vin0_in>; + }; + }; + }; + }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70 0x71 0x72 0x73 0x74 0x75 + 0x60 0x61 0x62 0x63 0x64 0x65>; + reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater", + "infoframe", "cbus", "cec", "sdp", "txa", "txb" ; + interrupt-parent = <&gpio3>; + interrupts = <03 IRQ_TYPE_LEVEL_LOW>, <04 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "intrq1", "intrq2"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + +}; + +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + +&pfc { + vin0_pins_parallel: vin0 { + groups = "vin0_data12", "vin0_sync", "vin0_clk", "vin0_clkenb"; + function = "vin0"; + }; +}; + +&vin0 { + status = "okay"; + + pinctrl-0 = <&vin0_pins_parallel>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin0_in: endpoint { + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + remote-endpoint = <&adv7612_out>; + }; + }; + }; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; From 1aa24b0b4e6f65935418a50c3167adf954a04770 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 26 Feb 2024 19:47:14 +0000 Subject: [PATCH 073/969] arm64: dts: renesas: rzg2ul-smarc: Enable PMIC and built-in RTC, GPIO and ONKEY Enable PMIC DA9062 and the built-in RTC, GPIO and ONKEY modules on the RZ/{G2UL,Five} SMARC EVK development boards. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240226194715.427597-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index de590996e10a..433860987f73 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ +#include #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" @@ -23,6 +24,63 @@ &i2c0 { clock-frequency = <400000>; + da9062: pmic@58 { + compatible = "dlg,da9062"; + reg = <0x58>; + gpio-controller; + #gpio-cells = <2>; + + gpio { + compatible = "dlg,da9062-gpio"; + }; + + onkey { + compatible = "dlg,da9062-onkey"; + }; + + pmic-good-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PMIC_PGOOD"; + }; + + rtc { + compatible = "dlg,da9062-rtc"; + }; + + sd0-pwr-sel-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + line-name = "SD0_PWR_SEL"; + }; + + sd1-pwr-sel-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "SD1_PWR_SEL"; + }; + + sw-et0-en-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + input; + line-name = "SW_ET0_EN#"; + }; + + thermal { + compatible = "dlg,da9062-thermal"; + status = "disabled"; + }; + + watchdog { + compatible = "dlg,da9062-watchdog"; + status = "disabled"; + }; + }; + versa3: clock-generator@68 { compatible = "renesas,5p35023"; reg = <0x68>; From e4caa0ba29e235c00090083c8570022c40bef508 Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Wed, 6 Mar 2024 11:58:35 +0100 Subject: [PATCH 074/969] arm64: dts: renesas: r8a779h0: Add thermal nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) and the various thermal zones on the Renesas R-Car V4M (R8A779H0) SoC. Add support for 2 TSC nodes of thermal. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/d1f07c77943912145583d8916ba3ca65d143b1b1.1709722573.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 11885729181b..a01929231e08 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -318,6 +318,16 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a779h0-thermal"; + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; @@ -653,6 +663,36 @@ }; }; + thermal-zones { + sensor_thermal_cr52: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_ca76: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, From 7db74b65a93bac5a3ad14b62615379ee2839e8ff Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 18 Mar 2024 17:43:45 +0000 Subject: [PATCH 075/969] ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes Add "interrupt-names" properties to SCIF nodes for clarity. This allows us to update the DT bindings to mark the "interrupt-names" property required for all SoCs which have multiple interrupts, and to validate the DTBs using dtbs_check. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240318174345.46824-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r7s72100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index e6d8da6faffb..08ea4c551ed0 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -125,6 +125,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -138,6 +139,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -151,6 +153,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -164,6 +167,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -177,6 +181,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -190,6 +195,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -203,6 +209,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -216,6 +223,7 @@ , , ; + interrupt-names = "eri", "rxi", "txi", "bri"; clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; clock-names = "fck"; power-domains = <&cpg_clocks>; From ecc79ab919ec54c658fb14f955c76872119829b8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Mar 2024 17:29:05 +0100 Subject: [PATCH 076/969] ARM: dts: renesas: r8a73a4: Add TMU nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the Timer Units (TMU) on the R-Mobile APE6 SoC, and the clocks serving them. Note that TMU channels 1 and 2 are not added, as their interrupts are not wired to the interrupt controller for the AP-System Core (INTC-SYS), only to the interrupt controller for the AP-Realtime Core (INTC-RT). Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/1a60832f3ba37afb4a5791f4e5db4610ab31beb3.1710864964.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 37 +++++++++++++++++++++++ include/dt-bindings/clock/r8a73a4-clock.h | 4 +++ 2 files changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index ac654ff45d0e..9a2ae282a46b 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -60,6 +60,32 @@ ; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&mstp1_clks R8A73A4_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&pd_c5>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&mstp1_clks R8A73A4_CLK_TMU3>; + clock-names = "fck"; + power-domains = <&pd_a3r>; + status = "disabled"; + }; + dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; @@ -654,6 +680,17 @@ }; /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&cp_clk>, <&mp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3 + >; + clock-output-names = + "tmu0", "tmu3"; + }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h index 1ec4827b8091..655440a3e7c6 100644 --- a/include/dt-bindings/clock/r8a73a4-clock.h +++ b/include/dt-bindings/clock/r8a73a4-clock.h @@ -24,6 +24,10 @@ #define R8A73A4_CLK_ZS 14 #define R8A73A4_CLK_HP 15 +/* MSTP1 */ +#define R8A73A4_CLK_TMU0 25 +#define R8A73A4_CLK_TMU3 21 + /* MSTP2 */ #define R8A73A4_CLK_DMAC 18 #define R8A73A4_CLK_SCIFB3 17 From e98c6844ae028075cf9a7de64f115e244478090d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Mar 2024 17:29:06 +0100 Subject: [PATCH 077/969] ARM: dts: renesas: rzg1: Add TMU nodes Add device nodes for the Timer Units (TMU) on the RZ/G1H (R8A7742), RZ/G1M (R8A7743), RZ/G1N (R8A7744), RZ/G1E (R8A7745), and RZ/G1C (R8A77470) SoCs. Note that TMU channel 0 on RZ/G1C is not added, as its module clock is not documented. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b09f55e0089a9824d43e89fd6bac3cbd48f40d8b.1710864964.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a7742.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7743.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7744.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7745.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a77470.dtsi | 44 +++++++++++++++++++ 5 files changed, 276 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi index 16d146db824a..d55c344c1cd2 100644 --- a/arch/arm/boot/dts/renesas/r8a7742.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7742.dtsi @@ -404,6 +404,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7742", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7742", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7742", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7742", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7742", "renesas,rcar-gen2-thermal"; diff --git a/arch/arm/boot/dts/renesas/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi index 2245d19a23bb..d917c0a971f5 100644 --- a/arch/arm/boot/dts/renesas/r8a7743.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7743.dtsi @@ -329,6 +329,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7743", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7743", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7743", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7743", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7743", "renesas,rcar-gen2-thermal"; diff --git a/arch/arm/boot/dts/renesas/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi index aa13841f9781..754859c38a93 100644 --- a/arch/arm/boot/dts/renesas/r8a7744.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7744.dtsi @@ -329,6 +329,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7744", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7744", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7744", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7744", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7744", "renesas,rcar-gen2-thermal"; diff --git a/arch/arm/boot/dts/renesas/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi index 44688b8431c3..168298300490 100644 --- a/arch/arm/boot/dts/renesas/r8a7745.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7745.dtsi @@ -304,6 +304,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7745", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7745", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7745", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7745", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; diff --git a/arch/arm/boot/dts/renesas/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi index a5cf663a0118..2375438d83c9 100644 --- a/arch/arm/boot/dts/renesas/r8a77470.dtsi +++ b/arch/arm/boot/dts/renesas/r8a77470.dtsi @@ -241,6 +241,50 @@ resets = <&cpg 407>; }; + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a77470", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a77470", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a77470", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; From b320e8c5634ee62d4849400a9ea48542aa980758 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Mar 2024 17:29:07 +0100 Subject: [PATCH 078/969] ARM: dts: renesas: rcar-gen2: Add TMU nodes Add device nodes for the Timer Units (TMU) on the R-Car H2 (R8A7790), M2-W (R8A7791), V2H (R8A7792), M2-N (R8A7793), and E2 (R8A7794) SoCs. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/7efbc8dbac6876f454011563edc1ae8eb50c95db.1710864964.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a7790.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7791.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7792.dtsi | 59 ++++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7793.dtsi | 58 +++++++++++++++++++++++++ arch/arm/boot/dts/renesas/r8a7794.dtsi | 58 +++++++++++++++++++++++++ 5 files changed, 291 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index 46fb81f5062f..583b74a9f071 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -434,6 +434,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7790", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7790", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7790", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7790", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7790", "renesas,rcar-gen2-thermal", diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index b9d34147628e..de08ceb62230 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -351,6 +351,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7791", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7791", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7791", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7791", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7791", "renesas,rcar-gen2-thermal", diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index ecfab3ff59e8..7defeb8e4cd1 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -351,6 +351,65 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7792", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7792", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7792", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7792", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index f51bf687f4bd..d32a9d5d3faa 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -326,6 +326,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7793", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7793", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7793", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7793", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + thermal: thermal@e61f0000 { compatible = "renesas,thermal-r8a7793", "renesas,rcar-gen2-thermal", diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index 371dd4715dde..f37f094cecc8 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -292,6 +292,64 @@ resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7794", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@fff60000 { + compatible = "renesas,tmu-r8a7794", "renesas,tmu"; + reg = <0 0xfff60000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 111>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 111>; + status = "disabled"; + }; + + tmu2: timer@fff70000 { + compatible = "renesas,tmu-r8a7794", "renesas,tmu"; + reg = <0 0xfff70000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu3: timer@fff80000 { + compatible = "renesas,tmu-r8a7794", "renesas,tmu"; + reg = <0 0xfff80000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; From 0be9a322307994443e854efd6a05b129c26ce287 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 27 Feb 2024 23:25:30 +0000 Subject: [PATCH 079/969] soc: renesas: Add identification support for RZ/V2H SoC Add support to identify the RZ/V2H (R9A09G057) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240227232531.218159-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 5 +++++ drivers/soc/renesas/renesas-soc.c | 20 +++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 5deca747fb77..91464ea48baf 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -344,6 +344,11 @@ config ARCH_R9A09G011 help This enables support for the Renesas RZ/V2M SoC. +config ARCH_R9A09G057 + bool "ARM64 Platform support for RZ/V2H(P)" + help + This enables support for the Renesas RZ/V2H(P) SoC variants. + endif # ARM64 if RISCV diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 8f9b8d3736dc..172d59e6fbcf 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -75,6 +75,10 @@ static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { .name = "RZ/G3S", }; +static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { + .name = "RZ/V2H", +}; + static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { .name = "RZ/V2L", }; @@ -177,6 +181,11 @@ static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { .id = 0x85e0447, }; +static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { + .family = &fam_rzv2h, + .id = 0x847a447, +}; + static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { .family = &fam_rzv2l, .id = 0x8447447, @@ -407,6 +416,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif +#ifdef CONFIG_ARCH_R9A09G057 + { .compatible = "renesas,r9a09g057", .data = &soc_rz_v2h }, +#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -432,6 +444,11 @@ static const struct renesas_id id_rzg2l __initconst = { .mask = 0xfffffff, }; +static const struct renesas_id id_rzv2h __initconst = { + .offset = 0x304, + .mask = 0xfffffff, +}; + static const struct renesas_id id_rzv2m __initconst = { .offset = 0x104, .mask = 0xff, @@ -449,6 +466,7 @@ static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l }, { .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m }, + { .compatible = "renesas,r9a09g057-sys", .data = &id_rzv2h }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } }; @@ -513,7 +531,7 @@ static int __init renesas_soc_init(void) eslo = product & 0xf; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, eslo); - } else if (id == &id_rzg2l) { + } else if (id == &id_rzg2l || id == &id_rzv2h) { eshi = ((product >> 28) & 0x0f); soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", eshi); From 3d2db954d2d922a8193654f2aa09c1bdee47818a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 19 Mar 2024 17:29:55 +0100 Subject: [PATCH 080/969] soc: renesas: Enable TMU support on R-Car Gen2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All Renesas R-Car Gen2 SoCs have Timer Units (TMU). Enable support for them by selecting the SYS_SUPPORTS_SH_TMU gatekeeper config symbol. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/b7b9fdd6f517a8b29bf5754e7f083d3b71805130.1710865761.git.geert+renesas@glider.be --- drivers/soc/renesas/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 91464ea48baf..5d94c3f31494 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -24,6 +24,7 @@ config ARCH_RCAR_GEN2 select RENESAS_IRQC select RST_RCAR select SYS_SUPPORTS_SH_CMT + select SYS_SUPPORTS_SH_TMU config ARCH_RCAR_GEN3 bool From 8ea517c014ad4956ab7536277dd3f89bfad39069 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 23 Feb 2024 12:36:46 +0000 Subject: [PATCH 081/969] arm64: defconfig: Enable Renesas RZ/G2L display unit DRM driver Enable the RZ/G2L display unit DRM drivers used on the RZ/{G2L,G2LC,V2L} SMARC EVK development boards. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240223123646.245655-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..08820606bfef 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -854,6 +854,7 @@ CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_DW_HDMI=m CONFIG_DRM_RCAR_MIPI_DSI=m CONFIG_DRM_RZG2L_MIPI_DSI=m +CONFIG_DRM_RZG2L_DU=m CONFIG_DRM_SUN4I=m CONFIG_DRM_SUN6I_DSI=m CONFIG_DRM_SUN8I_DW_HDMI=m From 3fe8d529076f6ef94c30c9afa0b0aeb49fc9509d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 27 Feb 2024 13:00:10 +0000 Subject: [PATCH 082/969] arm64: defconfig: Enable Renesas DA9062 PMIC Enable the config for the Renesas DA9062 PMIC and the built-in RTC, GPIO and ONKEY drivers as it is populated on the RZ/G2UL SMARC EVK development board. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240227130010.45361-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 08820606bfef..7fb4285e4f29 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -445,6 +445,7 @@ CONFIG_INPUT_TPS65219_PWRBUTTON=m CONFIG_INPUT_PWM_BEEPER=m CONFIG_INPUT_PWM_VIBRA=m CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_DA9063_ONKEY=m CONFIG_INPUT_HISI_POWERKEY=y # CONFIG_SERIO_SERPORT is not set CONFIG_SERIO_AMBAKMI=y @@ -562,6 +563,7 @@ CONFIG_SPI_TEGRA114=m CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y CONFIG_SPMI_MTK_PMIF=m +CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_MAX77620=y CONFIG_PINCTRL_RK805=m CONFIG_PINCTRL_SINGLE=y @@ -727,6 +729,7 @@ CONFIG_MFD_ALTERA_SYSMGR=y CONFIG_MFD_BD9571MWV=y CONFIG_MFD_AXP20X_I2C=y CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_DA9062=m CONFIG_MFD_EXYNOS_LPASS=m CONFIG_MFD_HI6421_PMIC=y CONFIG_MFD_HI655X_PMIC=y @@ -1170,6 +1173,7 @@ CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_CROS_EC=y CONFIG_RTC_DRV_FSL_FTM_ALARM=m From 27e51e83891bb4b9c806bae1ffb17c44fd8ea459 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 27 Feb 2024 23:25:31 +0000 Subject: [PATCH 083/969] arm64: defconfig: Enable R9A09G057 SoC Enable support for the Renesas RZ/V2H (R9A09G057) SoC in the ARM64 defconfig. Signed-off-by: Lad Prabhakar Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240227232531.218159-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7fb4285e4f29..6254ad2c16ad 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1413,6 +1413,7 @@ CONFIG_ARCH_R9A07G044=y CONFIG_ARCH_R9A07G054=y CONFIG_ARCH_R9A08G045=y CONFIG_ARCH_R9A09G011=y +CONFIG_ARCH_R9A09G057=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y From 66010ba94c9b9c273eb9682132d6b809440b9013 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 27 Feb 2024 23:25:28 +0000 Subject: [PATCH 084/969] dt-bindings: soc: renesas: Document Renesas RZ/V2H(P) SoC variants Document Renesas RZ/V2H(P) (R9A09G057) SoC variants. Signed-off-by: Lad Prabhakar Reviewed-by: Fabrizio Castro Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240227232531.218159-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/soc/renesas/renesas.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index c1ce4da2dc32..09d3ce97efa2 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -513,6 +513,14 @@ properties: - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - const: renesas,r9a09g011 + - description: RZ/V2H(P) (R9A09G057) + items: + - enum: + - renesas,r9a09g057h41 # RZ/V2H + - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support + - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support + - const: renesas,r9a09g057 + additionalProperties: true ... From d4319f220f577156200ad43c823e22be05f34523 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 27 Feb 2024 23:25:29 +0000 Subject: [PATCH 085/969] dt-bindings: arm: renesas: Document Renesas RZ/V2H(P) System Controller Add DT binding documentation for System Controller (SYS) found on RZ/V2H(P) ("R9A09G057") SoC's. SYS block contains the SYS_LSI_DEVID register which can be used to retrieve SoC version information. Signed-off-by: Lad Prabhakar Reviewed-by: Fabrizio Castro Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240227232531.218159-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../soc/renesas/renesas,r9a09g057-sys.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml new file mode 100644 index 000000000000..ebbf0c9109ce --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) System Controller (SYS) + +maintainers: + - Geert Uytterhoeven + +description: | + The RZ/V2H(P) SYS (System Controller) controls the overall + configuration of the LSI and supports the following functions, + - Trust zone control + - Extend access by specific masters to address beyond 4GB space + - GBETH configuration + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU + - LSI version + - WDT stop control + - General registers + +properties: + compatible: + const: renesas,r9a09g057-sys + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + sys: system-controller@10430000 { + compatible = "renesas,r9a09g057-sys"; + reg = <0x10430000 0x10000>; + clocks = <&cpg 1>; + resets = <&cpg 1>; + }; From 704094c5981287c85dfdb0bf53abdfcdcc1f8597 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 29 Feb 2024 19:51:18 -0600 Subject: [PATCH 086/969] arm64: dts: exynos850: Add CPU clocks Define CPU cluster 0 and CPU cluster 1 CMUs, which generate CPU clocks, and add corresponding CPU clocks to CPU nodes. Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20240301015118.30072-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 2ba67c3d0681..0706c8534ceb 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -93,6 +93,8 @@ compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; + clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; + clock-names = "cluster0_clk"; }; cpu1: cpu@1 { device_type = "cpu"; @@ -117,6 +119,8 @@ compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; + clock-names = "cluster1_clk"; }; cpu5: cpu@101 { device_type = "cpu"; @@ -254,6 +258,28 @@ "dout_peri_uart", "dout_peri_ip"; }; + cmu_cpucl1: clock-controller@10800000 { + compatible = "samsung,exynos850-cmu-cpucl1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL1_DBG>; + clock-names = "oscclk", "dout_cpucl1_switch", + "dout_cpucl1_dbg"; + }; + + cmu_cpucl0: clock-controller@10900000 { + compatible = "samsung,exynos850-cmu-cpucl0"; + reg = <0x10900000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, + <&cmu_top CLK_DOUT_CPUCL0_DBG>; + clock-names = "oscclk", "dout_cpucl0_switch", + "dout_cpucl0_dbg"; + }; + cmu_g3d: clock-controller@11400000 { compatible = "samsung,exynos850-cmu-g3d"; reg = <0x11400000 0x8000>; From 7bff1d35c1294c011b0269b8eaeb8f930df386fe Mon Sep 17 00:00:00 2001 From: Artur Weber Date: Sat, 17 Feb 2024 20:02:47 +0100 Subject: [PATCH 087/969] ARM: dts: exynos4212-tab3: limit usable memory range The stock bootloader on the Samsung Galaxy Tab 3 8.0 provides an incorrect available memory range over ATAG_MEM. Limit the usable memory in the DTS to prevent it from doing so, without having to disable ATAG support. Signed-off-by: Artur Weber Reviewed-by: Henrik Grimler Link: https://lore.kernel.org/r/20240217-tab3-limit-usable-memory-range-v1-1-49cc9c86a5cc@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi index e5254e32aa8f..9bc05961577d 100644 --- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -45,6 +45,12 @@ /* Default S-BOOT bootloader loads initramfs here */ linux,initrd-start = <0x42000000>; linux,initrd-end = <0x42800000>; + + /* + * Stock bootloader provides incorrect memory size in ATAG_MEM; + * override it here + */ + linux,usable-memory-range = <0x40000000 0x3fc00000>; }; firmware@204f000 { From 42a31d4410a8be76c39fe47c6b280bfc0eca3e42 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 22 Mar 2024 16:05:31 +0800 Subject: [PATCH 088/969] firmware: arm_scmi: Log the perf domain names in the error paths Currently, the performance domain names are not logged whenever any error occurs when processing the OPPs by adding to local data structures or to the OPP library. It would be easier to locate the problem if domain name is printed out. So let us add the performance domain names to the other information logged already in the error paths. Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20240322080531.3365016-1-peng.fan@oss.nxp.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/perf.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index 345fff167b52..4b7f1cbb9b04 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -387,8 +387,8 @@ process_response_opp(struct device *dev, struct perf_dom_info *dom, ret = xa_insert(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL); if (ret) - dev_warn(dev, "Failed to add opps_by_lvl at %d - ret:%d\n", - opp->perf, ret); + dev_warn(dev, "Failed to add opps_by_lvl at %d for %s - ret:%d\n", + opp->perf, dom->info.name, ret); } static inline void @@ -405,8 +405,8 @@ process_response_opp_v4(struct device *dev, struct perf_dom_info *dom, ret = xa_insert(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL); if (ret) - dev_warn(dev, "Failed to add opps_by_lvl at %d - ret:%d\n", - opp->perf, ret); + dev_warn(dev, "Failed to add opps_by_lvl at %d for %s - ret:%d\n", + opp->perf, dom->info.name, ret); /* Note that PERF v4 reports always five 32-bit words */ opp->indicative_freq = le32_to_cpu(r->opp[loop_idx].indicative_freq); @@ -417,8 +417,8 @@ process_response_opp_v4(struct device *dev, struct perf_dom_info *dom, GFP_KERNEL); if (ret) dev_warn(dev, - "Failed to add opps_by_idx at %d - ret:%d\n", - opp->level_index, ret); + "Failed to add opps_by_idx at %d for %s - ret:%d\n", + opp->level_index, dom->info.name, ret); hash_add(dom->opps_by_freq, &opp->hash, opp->indicative_freq); } @@ -879,7 +879,8 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph, ret = dev_pm_opp_add_dynamic(dev, &data); if (ret) { - dev_warn(dev, "failed to add opp %luHz\n", freq); + dev_warn(dev, "[%d][%s]: Failed to add OPP[%d] %lu\n", + domain, dom->info.name, idx, freq); dev_pm_opp_remove_all_dynamic(dev); return ret; } From da251ce210617fa31aa2a65ba7f28e1c584a1938 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 25 Mar 2024 20:46:16 +0000 Subject: [PATCH 089/969] include: trace: Widen the tag buffer in trace_scmi_dump_msg A bigger buffer allow for more diverse tag names. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20240325204620.1437237-2-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- include/trace/events/scmi.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/trace/events/scmi.h b/include/trace/events/scmi.h index 422c1ad9484d..127300481123 100644 --- a/include/trace/events/scmi.h +++ b/include/trace/events/scmi.h @@ -7,6 +7,8 @@ #include +#define TRACE_SCMI_MAX_TAG_LEN 6 + TRACE_EVENT(scmi_fc_call, TP_PROTO(u8 protocol_id, u8 msg_id, u32 res_id, u32 val1, u32 val2), TP_ARGS(protocol_id, msg_id, res_id, val1, val2), @@ -150,7 +152,7 @@ TRACE_EVENT(scmi_msg_dump, __field(u8, channel_id) __field(u8, protocol_id) __field(u8, msg_id) - __array(char, tag, 5) + __array(char, tag, TRACE_SCMI_MAX_TAG_LEN) __field(u16, seq) __field(int, status) __field(size_t, len) @@ -162,7 +164,7 @@ TRACE_EVENT(scmi_msg_dump, __entry->channel_id = channel_id; __entry->protocol_id = protocol_id; __entry->msg_id = msg_id; - strscpy(__entry->tag, tag, 5); + strscpy(__entry->tag, tag, TRACE_SCMI_MAX_TAG_LEN); __entry->seq = seq; __entry->status = status; __entry->len = len; From 5dc0e0b1f0ea2b55031f84a365962b9b45869b98 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 25 Mar 2024 20:46:17 +0000 Subject: [PATCH 090/969] firmware: arm_scmi: Add helper to trace bad messages Upon reception of malformed and unexpected timed-out SCMI messages, it is not possible to trace those bad messages in their entirety, because usually we cannot even retrieve the payload, or it is just not reliable. Add a helper to trace at least the content of the header of the received message while associating a meaningful tag and error code. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20240325204620.1437237-3-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/common.h | 11 +++++++++ drivers/firmware/arm_scmi/driver.c | 39 ++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index 6affbfdd1dec..b5ac25dbc1ca 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -301,6 +301,17 @@ extern const struct scmi_desc scmi_optee_desc; void scmi_rx_callback(struct scmi_chan_info *cinfo, u32 msg_hdr, void *priv); +enum scmi_bad_msg { + MSG_UNEXPECTED = -1, + MSG_INVALID = -2, + MSG_UNKNOWN = -3, + MSG_NOMEM = -4, + MSG_MBOX_SPURIOUS = -5, +}; + +void scmi_bad_message_trace(struct scmi_chan_info *cinfo, u32 msg_hdr, + enum scmi_bad_msg err); + /* shmem related declarations */ struct scmi_shared_mem; diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 2709598f3008..7fc1c5b1a2a4 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -696,6 +696,45 @@ scmi_xfer_lookup_unlocked(struct scmi_xfers_info *minfo, u16 xfer_id) return xfer ?: ERR_PTR(-EINVAL); } +/** + * scmi_bad_message_trace - A helper to trace weird messages + * + * @cinfo: A reference to the channel descriptor on which the message was + * received + * @msg_hdr: Message header to track + * @err: A specific error code used as a status value in traces. + * + * This helper can be used to trace any kind of weird, incomplete, unexpected, + * timed-out message that arrives and as such, can be traced only referring to + * the header content, since the payload is missing/unreliable. + */ +void scmi_bad_message_trace(struct scmi_chan_info *cinfo, u32 msg_hdr, + enum scmi_bad_msg err) +{ + char *tag; + struct scmi_info *info = handle_to_scmi_info(cinfo->handle); + + switch (MSG_XTRACT_TYPE(msg_hdr)) { + case MSG_TYPE_COMMAND: + tag = "!RESP"; + break; + case MSG_TYPE_DELAYED_RESP: + tag = "!DLYD"; + break; + case MSG_TYPE_NOTIFICATION: + tag = "!NOTI"; + break; + default: + tag = "!UNKN"; + break; + } + + trace_scmi_msg_dump(info->id, cinfo->id, + MSG_XTRACT_PROT_ID(msg_hdr), + MSG_XTRACT_ID(msg_hdr), tag, + MSG_XTRACT_TOKEN(msg_hdr), err, NULL, 0); +} + /** * scmi_msg_response_validate - Validate message type against state of related * xfer From 5076ab66db1671a5cd9ecfb857d1949e36a33142 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 25 Mar 2024 20:46:18 +0000 Subject: [PATCH 091/969] firmware: arm_scmi: Add message dump traces for bad and unexpected replies It is useful to have message dump traces for any invalid/bad/unexpected replies. Let us add traces for the same as well as late-timed-out, out-of-order and unexpected/spurious messages. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20240325204620.1437237-4-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 10 ++++++++++ drivers/firmware/arm_scmi/mailbox.c | 3 +++ 2 files changed, 13 insertions(+) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 7fc1c5b1a2a4..207ed1a52d69 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -861,6 +861,9 @@ scmi_xfer_command_acquire(struct scmi_chan_info *cinfo, u32 msg_hdr) "Message for %d type %d is not expected!\n", xfer_id, msg_type); spin_unlock_irqrestore(&minfo->xfer_lock, flags); + + scmi_bad_message_trace(cinfo, msg_hdr, MSG_UNEXPECTED); + return xfer; } refcount_inc(&xfer->users); @@ -885,6 +888,9 @@ scmi_xfer_command_acquire(struct scmi_chan_info *cinfo, u32 msg_hdr) dev_err(cinfo->dev, "Invalid message type:%d for %d - HDR:0x%X state:%d\n", msg_type, xfer_id, msg_hdr, xfer->state); + + scmi_bad_message_trace(cinfo, msg_hdr, MSG_INVALID); + /* On error the refcount incremented above has to be dropped */ __scmi_xfer_put(minfo, xfer); xfer = ERR_PTR(-EINVAL); @@ -921,6 +927,9 @@ static void scmi_handle_notification(struct scmi_chan_info *cinfo, if (IS_ERR(xfer)) { dev_err(dev, "failed to get free message slot (%ld)\n", PTR_ERR(xfer)); + + scmi_bad_message_trace(cinfo, msg_hdr, MSG_NOMEM); + scmi_clear_channel(info, cinfo); return; } @@ -1040,6 +1049,7 @@ void scmi_rx_callback(struct scmi_chan_info *cinfo, u32 msg_hdr, void *priv) break; default: WARN_ONCE(1, "received unknown msg_type:%d\n", msg_type); + scmi_bad_message_trace(cinfo, msg_hdr, MSG_UNKNOWN); break; } } diff --git a/drivers/firmware/arm_scmi/mailbox.c b/drivers/firmware/arm_scmi/mailbox.c index b8d470417e8f..615a3b2ad83d 100644 --- a/drivers/firmware/arm_scmi/mailbox.c +++ b/drivers/firmware/arm_scmi/mailbox.c @@ -56,6 +56,9 @@ static void rx_callback(struct mbox_client *cl, void *m) */ if (cl->knows_txdone && !shmem_channel_free(smbox->shmem)) { dev_warn(smbox->cinfo->dev, "Ignoring spurious A2P IRQ !\n"); + scmi_bad_message_trace(smbox->cinfo, + shmem_read_header(smbox->shmem), + MSG_MBOX_SPURIOUS); return; } From 264a2c52062802ea6052011015cb3d919dc14d9f Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 25 Mar 2024 20:46:19 +0000 Subject: [PATCH 092/969] firmware: arm_scmi: Simplify scmi_devm_notifier_unregister Unregistering SCMI notifications using the managed devres interface can be done providing as a reference simply the previously successfully registered notification block since it could have been registered only on one kernel notification_chain: drop any reference to SCMI protocol, events and sources. Devres internal helpers can search for the provided notification block reference and, once found, the associated devres object will already provide the above SCMI references for the event. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20240325204620.1437237-5-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/notify.c | 30 ++++-------------------------- include/linux/scmi_protocol.h | 2 -- 2 files changed, 4 insertions(+), 28 deletions(-) diff --git a/drivers/firmware/arm_scmi/notify.c b/drivers/firmware/arm_scmi/notify.c index 27c52531194d..e160ecb22948 100644 --- a/drivers/firmware/arm_scmi/notify.c +++ b/drivers/firmware/arm_scmi/notify.c @@ -1513,17 +1513,12 @@ static int scmi_devm_notifier_register(struct scmi_device *sdev, static int scmi_devm_notifier_match(struct device *dev, void *res, void *data) { struct scmi_notifier_devres *dres = res; - struct scmi_notifier_devres *xres = data; + struct notifier_block *nb = data; - if (WARN_ON(!dres || !xres)) + if (WARN_ON(!dres || !nb)) return 0; - return dres->proto_id == xres->proto_id && - dres->evt_id == xres->evt_id && - dres->nb == xres->nb && - ((!dres->src_id && !xres->src_id) || - (dres->src_id && xres->src_id && - dres->__src_id == xres->__src_id)); + return dres->nb == nb; } /** @@ -1531,10 +1526,6 @@ static int scmi_devm_notifier_match(struct device *dev, void *res, void *data) * notifier_block for an event * @sdev: A reference to an scmi_device whose embedded struct device is to * be used for devres accounting. - * @proto_id: Protocol ID - * @evt_id: Event ID - * @src_id: Source ID, when NULL register for events coming form ALL possible - * sources * @nb: A standard notifier block to register for the specified event * * Generic devres managed helper to explicitly un-register a notifier_block @@ -1544,25 +1535,12 @@ static int scmi_devm_notifier_match(struct device *dev, void *res, void *data) * Return: 0 on Success */ static int scmi_devm_notifier_unregister(struct scmi_device *sdev, - u8 proto_id, u8 evt_id, - const u32 *src_id, struct notifier_block *nb) { int ret; - struct scmi_notifier_devres dres; - - dres.handle = sdev->handle; - dres.proto_id = proto_id; - dres.evt_id = evt_id; - if (src_id) { - dres.__src_id = *src_id; - dres.src_id = &dres.__src_id; - } else { - dres.src_id = NULL; - } ret = devres_release(&sdev->dev, scmi_devm_release_notifier, - scmi_devm_notifier_match, &dres); + scmi_devm_notifier_match, nb); WARN_ON(ret); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index b807141acc14..a3addb07e00a 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -783,8 +783,6 @@ struct scmi_notify_ops { const u32 *src_id, struct notifier_block *nb); int (*devm_event_notifier_unregister)(struct scmi_device *sdev, - u8 proto_id, u8 evt_id, - const u32 *src_id, struct notifier_block *nb); int (*event_notifier_register)(const struct scmi_handle *handle, u8 proto_id, u8 evt_id, From 3a7d93d1f71b3843a64a1672536d42ff7c77a34d Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 25 Mar 2024 20:46:20 +0000 Subject: [PATCH 093/969] firmware: arm_scmi: Use dev_err_probe to bail out Improve the error logging in the driver probe failure paths. Also use dev_err_probe which is probe error check and log helper to prevent logging in case of probe deferral. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20240325204620.1437237-6-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 34 +++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 207ed1a52d69..d0091459a276 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -2540,6 +2540,10 @@ scmi_txrx_setup(struct scmi_info *info, struct device_node *of_node, ret = 0; } + if (ret) + dev_err(info->dev, + "failed to setup channel for protocol:0x%X\n", prot_id); + return ret; } @@ -2809,6 +2813,7 @@ static int scmi_debugfs_raw_mode_setup(struct scmi_info *info) static int scmi_probe(struct platform_device *pdev) { int ret; + char *err_str = "probe failure\n"; struct scmi_handle *handle; const struct scmi_desc *desc; struct scmi_info *info; @@ -2859,27 +2864,37 @@ static int scmi_probe(struct platform_device *pdev) if (desc->ops->link_supplier) { ret = desc->ops->link_supplier(dev); - if (ret) + if (ret) { + err_str = "transport not ready\n"; goto clear_ida; + } } /* Setup all channels described in the DT at first */ ret = scmi_channels_setup(info); - if (ret) + if (ret) { + err_str = "failed to setup channels\n"; goto clear_ida; + } ret = bus_register_notifier(&scmi_bus_type, &info->bus_nb); - if (ret) + if (ret) { + err_str = "failed to register bus notifier\n"; goto clear_txrx_setup; + } ret = blocking_notifier_chain_register(&scmi_requested_devices_nh, &info->dev_req_nb); - if (ret) + if (ret) { + err_str = "failed to register device notifier\n"; goto clear_bus_notifier; + } ret = scmi_xfer_info_init(info); - if (ret) + if (ret) { + err_str = "failed to init xfers pool\n"; goto clear_dev_req_notifier; + } if (scmi_top_dentry) { info->dbg = scmi_debugfs_common_setup(info); @@ -2916,9 +2931,11 @@ static int scmi_probe(struct platform_device *pdev) */ ret = scmi_protocol_acquire(handle, SCMI_PROTOCOL_BASE); if (ret) { - dev_err(dev, "unable to communicate with SCMI\n"); - if (coex) + err_str = "unable to communicate with SCMI\n"; + if (coex) { + dev_err(dev, err_str); return 0; + } goto notification_exit; } @@ -2972,7 +2989,8 @@ clear_txrx_setup: scmi_cleanup_txrx_channels(info); clear_ida: ida_free(&scmi_id, info->id); - return ret; + + return dev_err_probe(dev, ret, err_str); } static void scmi_remove(struct platform_device *pdev) From b5ffc424360eaced41f405f0e38bcabe61fecf39 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Tue, 5 Mar 2024 15:36:33 +0100 Subject: [PATCH 094/969] arm64: dts: rockchip: add i2s_8ch_2 and i2s_8ch_3 to rk3308 These are I2S engines internally connected to the built-in audio codec. Signed-off-by: Luca Ceresoli Link: https://lore.kernel.org/r/20240305-rk3308-audio-codec-v4-6-312acdbe628f@bootlin.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index cfc0a87b5195..662c55fe9b77 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -578,6 +578,48 @@ #dma-cells = <1>; }; + /* + * - can be clock producer or consumer + * - up to 8 capture channels and 2 playback channels + * - connected internally to audio codec + */ + i2s_8ch_2: i2s@ff320000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff320000 0x0 0x1000>; + interrupts = ; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + clocks = <&cru SCLK_I2S2_8CH_TX>, + <&cru SCLK_I2S2_8CH_RX>, + <&cru HCLK_I2S2_8CH>; + dmas = <&dmac1 5>, <&dmac1 4>; + dma-names = "rx", "tx"; + resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + /* + * - can be clock consumer only + * - up to 4 capture channels, no playback + * - connected internally to audio codec + */ + i2s_8ch_3: i2s@ff330000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff330000 0x0 0x1000>; + interrupts = ; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + clocks = <&cru SCLK_I2S3_8CH_TX>, + <&cru SCLK_I2S3_8CH_RX>, + <&cru HCLK_I2S3_8CH>; + dmas = <&dmac1 7>; + dma-names = "rx"; + resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + i2s_2ch_0: i2s@ff350000 { compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff350000 0x0 0x1000>; From 30d72458624bb1ba7bab1c7a1d5f4c42f512010c Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Tue, 5 Mar 2024 15:36:34 +0100 Subject: [PATCH 095/969] arm64: dts: rockchip: add the internal audio codec on rk3308 The RK3308 has a built-in audio codec that connects internally to i2s_8ch_2 or i2s_8ch_3. Signed-off-by: Luca Ceresoli Link: https://lore.kernel.org/r/20240305-rk3308-audio-codec-v4-7-312acdbe628f@bootlin.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 662c55fe9b77..962ea893999b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -803,6 +803,20 @@ assigned-clock-rates = <32768>; }; + codec: codec@ff560000 { + compatible = "rockchip,rk3308-codec"; + reg = <0x0 0xff560000 0x0 0x10000>; + rockchip,grf = <&grf>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + clocks = <&cru SCLK_I2S2_8CH_TX_OUT>, + <&cru SCLK_I2S2_8CH_RX_OUT>, + <&cru PCLK_ACODEC>; + reset-names = "codec-reset"; + resets = <&cru SRST_ACODEC_P>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@ff580000 { compatible = "arm,gic-400"; reg = <0x0 0xff581000 0x0 0x1000>, From 9fdd7b45da18b84d5e7d5a6b8b4b0167910f2d13 Mon Sep 17 00:00:00 2001 From: Luca Ceresoli Date: Tue, 5 Mar 2024 15:36:32 +0100 Subject: [PATCH 096/969] arm64: defconfig: enable Rockchip RK3308 internal audio codec driver This codec now has a driver. Signed-off-by: Luca Ceresoli Link: https://lore.kernel.org/r/20240305-rk3308-audio-codec-v4-5-312acdbe628f@bootlin.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..f48a19b28a4f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -991,6 +991,7 @@ CONFIG_SND_SOC_GTM601=m CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_RK3308=m CONFIG_SND_SOC_RK817=m CONFIG_SND_SOC_RT5640=m CONFIG_SND_SOC_RT5659=m From 37a6d5864fb8226c97eefa59a79de57571e1fee8 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Mar 2024 15:22:31 +0100 Subject: [PATCH 097/969] dt-bindings: add wolfvision vendor prefix Add vendor prefix for WolfVision GmbH (https://wolfvision.com). Signed-off-by: Michael Riesch Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240325-feature-wolfvision-pf5-v1-1-5725445f792a@wolfvision.net Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b97d298b3eb6..59c6c6760bc0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1627,6 +1627,8 @@ patternProperties: description: Wondermedia Technologies, Inc. "^wobo,.*": description: Wobo + "^wolfvision,.*": + description: WolfVision GmbH "^x-powers,.*": description: X-Powers "^xen,.*": From 6be2ad17acb76c47e544864467680a7b738d7eb8 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Mar 2024 15:22:32 +0100 Subject: [PATCH 098/969] dt-bindings: arm: rockchip: add wolfvision pf5 mainboard Add the WolfVision PF5 mainboard, which serves as base for recent WolfVision products. It features the Rockchip RK3568 SoC and can be extended with several different extension boards. Signed-off-by: Michael Riesch Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240325-feature-wolfvision-pf5-v1-2-5725445f792a@wolfvision.net Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index fcf7316ecd74..99bd5e2c76a0 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -927,6 +927,11 @@ properties: - const: turing,rk1 - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard + items: + - const: wolfvision,rk3568-pf5 + - const: rockchip,rk3568 + - description: Xunlong Orange Pi 5 Plus items: - const: xunlong,orangepi-5-plus From 0be29f76633a447e15fc58066ea47688974e68d9 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Mar 2024 15:22:33 +0100 Subject: [PATCH 099/969] arm64: dts: rockchip: add wolfvision pf5 mainboard Add device tree for the WolfVision PF5 mainboard. It features - Rockchip RK3568 SoC - eMMC - RTC with backup battery - on-board PDM microphone - 12V DC jack - HDMI output - USB-C device port as well as various expansion headers for different extension boards. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20240325-feature-wolfvision-pf5-v1-3-5725445f792a@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-wolfvision-pf5.dts | 528 ++++++++++++++++++ 2 files changed, 529 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f906a868b71a..8fb35a363e4f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -107,6 +107,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts new file mode 100644 index 000000000000..170b14f92f51 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5.dts @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree for the WolfVision PF5 mainboard. + * + * Copyright (C) 2024 WolfVision GmbH. + */ + +/dts-v1/; +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "WolfVision PF5"; + compatible = "wolfvision,rk3568-pf5", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdhci; + rtc0 = &pcf85623; + rtc1 = &rk809; + }; + + chosen: chosen { + stdout-path = "serial2:115200n8"; + }; + + hdmi_tx: hdmi-tx-connector { + compatible = "hdmi-connector"; + hdmi-pwr-supply = <&hdmi_tx_5v>; + type = "a"; + + port { + hdmi_tx_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + hdmi_tx_5v: hdmi-tx-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_tx_5v_en>; + regulator-name = "hdmi_tx_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_in>; + }; + + pdm_codec: pdm-codec { + compatible = "dmic-codec"; + num-channels = <1>; + #sound-dai-cells = <0>; + }; + + pdm_sound: pdm-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "microphone"; + + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + + simple-audio-card,codec { + sound-dai = <&pdm_codec>; + }; + }; + + vcc12v_cam: vcc12v-cam-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc12v_cam_en>; + regulator-name = "12v_cam"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_in>; + }; + + vcc12v_in: vcc12v-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "12v_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v8_cam: vcc3v8-cam-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v8_cam_en>; + regulator-name = "3v8_cam"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + vin-supply = <&vcc5v_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v_in>; + }; + + vcc5v_in: vcc5v-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "5v_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_in>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vcc0v9_cpu>; +}; + +&cpu1 { + cpu-supply = <&vcc0v9_cpu>; +}; + +&cpu2 { + cpu-supply = <&vcc0v9_cpu>; +}; + +&cpu3 { + cpu-supply = <&vcc0v9_cpu>; +}; + +&gpu { + mali-supply = <&vcc0v9_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vcc0v9a_image>; + avdd-1v8-supply = <&vcc1v8a_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_tx_in>; + }; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + vcc1-supply = <&vcc5v_in>; + vcc2-supply = <&vcc5v_in>; + vcc3-supply = <&vcc5v_in>; + vcc4-supply = <&vcc5v_in>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc5v_in>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vcc0v9_logic: DCDC_REG1 { + regulator-name = "0v9_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc0v9_gpu: DCDC_REG2 { + regulator-name = "0v9_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v1_ddr4: DCDC_REG3 { + regulator-name = "1v1_ddr4"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc0v9_npu: DCDC_REG4 { + regulator-name = "0v9_npu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8: DCDC_REG5 { + regulator-name = "1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc0v9a_image: LDO_REG1 { + regulator-name = "0v9a_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc0v9a: LDO_REG2 { + regulator-name = "0v9a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc0v9a_pmu: LDO_REG3 { + regulator-name = "0v9a_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc3v3_acodec: LDO_REG4 { + regulator-name = "3v3_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG5 { + regulator-name = "3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc1v8a: LDO_REG7 { + regulator-name = "1v8a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8a_pmu: LDO_REG8 { + regulator-name = "1v8a_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8a_image: LDO_REG9 { + regulator-name = "1v8a_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sw: SWITCH_REG1 { + regulator-name = "3v3_sw"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + regulator@42 { + compatible = "ti,tps62869"; + reg = <0x42>; + + regulators { + vcc0v9_cpu: SW { + regulator-name = "0v9_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = ; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1150000>; + vin-supply = <&vcc5v_in>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pcf85623: rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_in>; + quartz-load-femtofarads = <12500>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; +}; + +&pdm { + pinctrl-0 = <&pdmm0_clk + &pdmm0_sdi0>; + status = "okay"; +}; + +&pinctrl { + cam { + vcc12v_cam_en: vcc12v-cam-en-pinctrl { + rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v8_cam_en: vcc3v8-cam-en-pinctrl { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmitx { + hdmi_tx_5v_en: hdmi-tx-5v-en-pinctrl { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l-pinctrl { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc3v3_acodec>; + vccio2-supply = <&vcc1v8>; + vccio3-supply = <&vcc3v3_sd>; + vccio4-supply = <&vcc1v8>; + vccio5-supply = <&vcc1v8>; + vccio6-supply = <&vcc3v3_sw>; + vccio7-supply = <&vcc3v3_sw>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc1v8a>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc3v3_sw>; + vqmmc-supply = <&vcc1v8>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + /* The following quirks are required since the bInterval is 1 and we + * handle steady ISOC streaming. See Usecase 3 in commit 729dcffd1ed3 + * ("usb: dwc3: gadget: Add support for disabling U1 and U2 entries"). + */ + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + /* + * Without this quirk the available fifosize seems to be miscalculated + * in cases where many endpoints are used. In one particular situation + * 8 IN EPs and 3 OUT EPs where selected and lead to stalled transfers + * without the resize quirk. + */ + tx-fifo-resize; + + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP2>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 28799a7734a0e1a38d01b511ca08d33d8cf91b6c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Mar 2024 15:22:34 +0100 Subject: [PATCH 100/969] arm64: dts: rockchip: add wolfvision pf5 io expander board Add device tree overlay for the WolfVision PF5 IO Expander board. This extension board can be attached to the WolfVision PF5 mainboard and features - TI DP83826 Ethernet PHY - RJ45 jack - USB-A host port Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20240325-feature-wolfvision-pf5-v1-4-5725445f792a@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rk3568-wolfvision-pf5-io-expander.dtso | 137 ++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 8fb35a363e4f..0192980ef37f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso new file mode 100644 index 000000000000..ebcaeafc3800 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for the WolfVision PF5 IO Expander board. + * + * Copyright (C) 2024 WolfVision GmbH. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&{/} { + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "gmac0_clkin"; + #clock-cells = <0>; + }; + + usb_host_vbus: usb-host-vbus-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_vbus_en>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_in>; + }; + + vcc1v8_eth: vcc1v8-eth-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc1v8_eth_en>; + regulator-always-on; + regulator-boot-on; + regulator-name = "1v8_eth"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_eth: vcc3v3-eth-regulator { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_eth_enn>; + regulator-always-on; + regulator-boot-on; + regulator-name = "3v3_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RMII_SPEED>, + <&gmac0_clkin>; + clock_in_out = "input"; + phy-handle = <&dp83826>; + phy-mode = "rmii"; + phy-supply = <&vcc3v3_eth>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_clkinout + &gmac0_rx_er + &gmac0_rx_bus2 + &gmac0_tx_bus2>; + status = "okay"; +}; + +&mdio0 { + #address-cells = <1>; + #size-cells = <0>; + + dp83826: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <ð_wake_intn ð_phy_rstn>; + reset-assert-us = <1000>; + reset-deassert-us = <2000>; + reset-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; +}; + +&pinctrl { + ethernet { + eth_wake_intn: eth-wake-intn-pinctrl { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + eth_phy_rstn: eth-phy-rstn-pinctrl { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc1v8_eth_en: vcc1v8-eth-en-pinctrl { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_eth_enn: vcc3v3-eth-enn-pinctrl { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_vbus_en: usb-host-vbus-en-pinctrl { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_host1_xhci { + maximum-speed = "high-speed"; + phys = <&usb2phy0_host>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&usb_host_vbus>; + status = "okay"; +}; From 89a7056ed4f771e689729f7992ef5351e64e26c6 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Sat, 17 Feb 2024 22:48:26 +0800 Subject: [PATCH 101/969] riscv: dts: sophgo: add sdcard support for milkv duo Add sdhci dt node in SoC dtsi and enable it in milkv duo dts. Signed-off-by: Jisheng Zhang Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20240217144826.3944-1-jszhang@kernel.org Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- .../riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts | 8 ++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts index 3af9e34b3bc7..94e64ddce8fa 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts @@ -33,6 +33,14 @@ clock-frequency = <25000000>; }; +&sdhci0 { + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 2d6f4a4b1e58..405f4ba18392 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2023 Inochi Amaoto */ +#include #include / { @@ -45,6 +46,13 @@ #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <375000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -175,6 +183,15 @@ status = "disabled"; }; + sdhci0: mmc@4310000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4310000 0x1000>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + status = "disabled"; + }; + plic: interrupt-controller@70000000 { reg = <0x70000000 0x4000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; From e6968faa33ce754bbe36dd6d9fe6951ec10616b1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 26 Mar 2024 17:52:05 +0100 Subject: [PATCH 102/969] arm64: defconfig: support Mali CSF-based GPUs Enable support for Mali CSF-based GPUs, which is found on recent ARM SoCs, such as Rockchip or Mediatek. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240326165232.73585-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f48a19b28a4f..d30e234803c2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -907,6 +907,7 @@ CONFIG_DRM_MESON=m CONFIG_DRM_PL111=m CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m +CONFIG_DRM_PANTHOR=m CONFIG_DRM_TIDSS=m CONFIG_DRM_POWERVR=m CONFIG_FB=y From 6fca4edb93d335f29f81e484936f38a5eed6a9b1 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 26 Mar 2024 17:52:06 +0100 Subject: [PATCH 103/969] arm64: dts: rockchip: Add rk3588 GPU node Add Mali GPU Node to the RK3588 SoC DT including GPU clock operating points Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 87b83c87bd55..89d40cff635f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -501,6 +501,62 @@ status = "disabled"; }; + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; From 038347286941148b6fd0cc2c40afcd540315aa6f Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 26 Mar 2024 17:52:07 +0100 Subject: [PATCH 104/969] arm64: dts: rockchip: Enable GPU on rk3588-rock5b Enable the Mali GPU in the Rock 5B. Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240326165232.73585-4-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 1fe8b2a0ed75..d6bf2ee07e87 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -180,6 +180,11 @@ cpu-supply = <&vdd_cpu_lit_s0>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; From 75a287219a782951e671026ed4fbe611e4629c83 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Tue, 26 Mar 2024 17:52:08 +0100 Subject: [PATCH 105/969] arm64: dts: rockchip: Enable GPU on rk3588-evb1 Enable the Mali GPU in the RK3588 EVB1. This marks the GPU regulators as always-on, because the generic coupler regulator logic from the kernel can only handle them when they are marked as always-on. Technically it's okay to disable the regulators, when the GPU is not used. Considering the RK3588 EVB1 is not battery powered, the slightly increased power consumption for keeping the regulator always enabled is not a big deal. Thus it's better to enable GPU support than wait for a better solution. Signed-off-by: Boris Brezillon Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240326165232.73585-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index de30c2632b8e..56c019b25fa8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -281,6 +281,12 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + &i2c2 { status = "okay"; @@ -484,12 +490,16 @@ regulators { vdd_gpu_s0: dcdc-reg1 { + /* regulator coupling requires always-on */ + regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; regulator-name = "vdd_gpu_s0"; regulator-enable-ramp-delay = <400>; + regulator-coupled-with = <&vdd_gpu_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -534,12 +544,16 @@ }; vdd_gpu_mem_s0: dcdc-reg5 { + /* regulator coupling requires always-on */ + regulator-always-on; regulator-boot-on; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; regulator-enable-ramp-delay = <400>; regulator-name = "vdd_gpu_mem_s0"; + regulator-coupled-with = <&vdd_gpu_s0>; + regulator-coupled-max-spread = <10000>; regulator-state-mem { regulator-off-in-suspend; }; From 3a9172fe55e8806d6937f45f6b3c52ee9243b67c Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Mon, 25 Mar 2024 17:19:04 +0100 Subject: [PATCH 106/969] arm64: dts: rockchip: Enable the GPU on quartzpro64 Following the approach used to enable the Mali GPU on the rk3588-evb1, [1] do the same for the Pine64 QuartzPro64, which uses nearly identical hardware design as the RK3588 EVB1. The slight disadvantage is that the regulator coupling logic requires the regulators to be always on, which is also noted in the comments. This is obviously something to be improved at some point in the future, but should be fine for now, especially because the QuartzPro64 isn't a battery-powered board, so low power consumption isn't paramount. [1] https://lore.kernel.org/linux-rockchip/20240325153850.189128-5-sebastian.reichel@collabora.com/ Signed-off-by: Dragan Simic Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/0f3759ee390f245dac447bbee038445ddfecbec0.1711383286.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index 67414d72e2b6..68d432c61ea5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -285,6 +285,12 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + &i2c2 { status = "okay"; @@ -491,11 +497,15 @@ regulators { vdd_gpu_s0: dcdc-reg1 { regulator-name = "vdd_gpu_s0"; + /* regulator coupling requires always-on */ + regulator-always-on; regulator-boot-on; regulator-enable-ramp-delay = <400>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; + regulator-coupled-with = <&vdd_gpu_mem_s0>; + regulator-coupled-max-spread = <10000>; regulator-state-mem { regulator-off-in-suspend; @@ -545,11 +555,15 @@ vdd_gpu_mem_s0: dcdc-reg5 { regulator-name = "vdd_gpu_mem_s0"; + /* regulator coupling requires always-on */ + regulator-always-on; regulator-boot-on; regulator-enable-ramp-delay = <400>; regulator-min-microvolt = <675000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; + regulator-coupled-with = <&vdd_gpu_s0>; + regulator-coupled-max-spread = <10000>; regulator-state-mem { regulator-off-in-suspend; From 51ca6a22c52b10a787fa3fad2343279f11da27bb Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 27 Mar 2024 12:21:19 +0100 Subject: [PATCH 107/969] arm64: dts: rockchip: enable gpu on rk3588-jaguar Enable the mali gpu node and add the board-specific supply-regulator. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240327112120.1181570-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 39d65002add1..4076c92668ba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -245,6 +245,11 @@ }; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; status = "okay"; From f5256f8ed4b729c3ab9d9cd7d406313773484b59 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 27 Mar 2024 12:21:20 +0100 Subject: [PATCH 108/969] arm64: dts: rockchip: enable gpu on rk3588-tiger Enable the mali gpu node and add the som-specific supply-regulator. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240327112120.1181570-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 1eb2543a5fde..72fe696b0034 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -139,6 +139,11 @@ snps,reset-delays-us = <0 10000 100000>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c1 { pinctrl-0 = <&i2c1m0_xfer>; }; From abd9ba92bac5f49d5b24669b66a5806b6ceef248 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Mon, 22 Jan 2024 16:06:00 +0200 Subject: [PATCH 109/969] arm64: dts: s32g: add SCMI firmware node Linux controls the clocks over SCMI on S32G SoCs. Therefore, add the SCMI device tree node and the reserved region for SCMI messages. Signed-off-by: Catalin Udma Signed-off-by: Ghennadi Procopciuc Reviewed-by: Matthias Brugger Reviewed-by: Chester Lin Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 5ac1cc9ff50e..ef1a1d61f2ba 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2017-2021 NXP + * Copyright 2017-2021, 2024 NXP */ #include @@ -14,6 +14,18 @@ #address-cells = <2>; #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_buf: shm@d0000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd0000000 0x0 0x80>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -77,6 +89,19 @@ }; firmware { + scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_buf>; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; From 6e5f3ac6f779047524b9a398820289a90b905309 Mon Sep 17 00:00:00 2001 From: Ghennadi Procopciuc Date: Mon, 22 Jan 2024 16:06:01 +0200 Subject: [PATCH 110/969] arm64: dts: s32g: add uSDHC node Add the uSDHC node for the boards that are based on S32G SoCs. Signed-off-by: Ciprian Costea Signed-off-by: Ghennadi Procopciuc Reviewed-by: Matthias Brugger Reviewed-by: Chester Lin Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 10 ++++++++++ arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 6 +++++- arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 6 +++++- 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index ef1a1d61f2ba..fc19ae2e8d3b 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -138,6 +138,16 @@ status = "disabled"; }; + usdhc0: mmc@402f0000 { + compatible = "nxp,s32g2-usdhc"; + reg = <0x402f0000 0x1000>; + interrupts = ; + clocks = <&clks 32>, <&clks 31>, <&clks 33>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; reg = <0x50800000 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index 9118d8d2ee01..00070c949e2a 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2019-2021 NXP + * Copyright 2019-2021, 2024 NXP */ /dts-v1/; @@ -32,3 +32,7 @@ &uart0 { status = "okay"; }; + +&usdhc0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index e05ee854cdf5..b3fc12899cae 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC - * Copyright (c) 2019-2021 NXP + * Copyright 2019-2021, 2024 NXP */ /dts-v1/; @@ -38,3 +38,7 @@ &uart1 { status = "okay"; }; + +&usdhc0 { + status = "okay"; +}; From 5bd46f739a4de1fe16e4b3c2d03045996b512bd0 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sun, 25 Feb 2024 23:56:22 +0100 Subject: [PATCH 111/969] ARM: dts: imx6sl: tolino-shine2hd: fix IRQ config of touchscreen Correctly describe the interrupt as level low. Driver enforces that anyways, but do not rely on that in the devicetree. Suggested-by: Dmitry Torokhov Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts index 5636fb3661e8..1fbe2e6d3e4d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -138,7 +138,7 @@ pinctrl-0 = <&pinctrl_zforce>; reg = <0x50>; interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&ldo1_reg>; reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; touchscreen-size-x = <1072>; From 2ab9fd540e360e1c2e61299917f3d99e6d2e2e0e Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sun, 25 Feb 2024 23:57:20 +0100 Subject: [PATCH 112/969] ARM: dts: imx6: fix IRQ config of RC5T619 Set interrupt type to level low to correctly describe the hardware and do not rely on the driver to do the right thing. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/e60k02.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/e70k02.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi index dd03e3860f97..13756d39fb7b 100644 --- a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi @@ -127,7 +127,7 @@ compatible = "ricoh,rc5t619"; reg = <0x32>; interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; system-power-controller; regulators { diff --git a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi index 4e1bf080eaca..dcc3c9d488a8 100644 --- a/arch/arm/boot/dts/nxp/imx/e70k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e70k02.dtsi @@ -145,7 +145,7 @@ compatible = "ricoh,rc5t619"; reg = <0x32>; interrupt-parent = <&gpio4>; - interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; system-power-controller; regulators { diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts index 1fbe2e6d3e4d..03d6965f0149 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -163,7 +163,7 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; reg = <0x32>; interrupt-parent = <&gpio5>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; system-power-controller; regulators { From 7d7df014617ba8df7fbdacac54cafe0d13573dcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 26 Mar 2024 15:12:57 +0000 Subject: [PATCH 113/969] arm64: dts: exynos: gs101: reorder pinctrl-* properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Preferred order for these is pinctrl-0 pinctrl-names. Update the DTSI & DTS accordingly. Signed-off-by: André Draszik Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-2-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 4 ++-- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 6ccade2c8cb4..40de2b0aa086 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -29,8 +29,8 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; + pinctrl-names = "default"; button-vol-down { label = "KEY_VOLUMEDOWN"; @@ -103,8 +103,8 @@ }; &serial_0 { - pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 55e6bcb3689e..5868c96c771f 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -393,8 +393,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; From 73618dfa705dc8f993a6829c895eaf5af8402ceb Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:12:58 +0000 Subject: [PATCH 114/969] arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinctrl nodes are coming from the shared gs101-pinctrl.dtsi, thus the pinctrl-0/names shall stay in dtsi. Move them. Reviewed-by: André Draszik Reviewed-by: Alim Akhtar Reviewed-by: Peter Griffin Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-3-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 2 -- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 40de2b0aa086..6be15e990b65 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -103,8 +103,6 @@ }; &serial_0 { - pinctrl-0 = <&uart0_bus>; - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 5868c96c771f..a1aff219208a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -424,6 +424,8 @@ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; + pinctrl-0 = <&uart0_bus>; + pinctrl-names = "default"; samsung,uart-fifosize = <256>; status = "disabled"; }; From d978c70e8d4775c62db21f85947d12b4f874104a Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:12:59 +0000 Subject: [PATCH 115/969] arm64: dts: exynos: gs101: move pinctrl-* properties after clocks Move the pinctrl-* properties after clocks so that we keep alphabetic order and align with the other similar definitions. Reviewed-by: Alim Akhtar Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-4-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a1aff219208a..cfb3ddc7f885 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -393,11 +393,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&hsi2c8_bus>; - pinctrl-names = "default"; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>; clock-names = "hsi2c", "hsi2c_pclk"; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; status = "disabled"; }; }; @@ -473,11 +473,11 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&hsi2c12_bus>; - pinctrl-names = "default"; clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>, <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>; clock-names = "hsi2c", "hsi2c_pclk"; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; status = "disabled"; }; }; From 028a87e91fcd8c485afcf8bd0d26ae34a0872438 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:13:00 +0000 Subject: [PATCH 116/969] arm64: dts: exynos: gs101: join lines close to 80 chars These lines fit 81 characters, which is pretty close to 80. Join the lines for better readability. Reviewed-by: Alim Akhtar Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-5-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index cfb3ddc7f885..690deca37e4f 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -374,8 +374,7 @@ }; usi8: usi@109700c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x109700c0 0x20>; ranges; #address-cells = <1>; @@ -403,8 +402,7 @@ }; usi_uart: usi@10a000c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10a000c0 0x20>; ranges; #address-cells = <1>; @@ -419,8 +417,7 @@ serial_0: serial@10a00000 { compatible = "google,gs101-uart"; reg = <0x10a00000 0xc0>; - interrupts = ; + interrupts = ; clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; @@ -454,8 +451,7 @@ }; usi12: usi@10d500c0 { - compatible = "google,gs101-usi", - "samsung,exynos850-usi"; + compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10d500c0 0x20>; ranges; #address-cells = <1>; From a45c3a9b1ef9571741d40bf10f22ce3c60bc5111 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 26 Mar 2024 15:13:01 +0000 Subject: [PATCH 117/969] arm64: dts: exynos: gs101: define all PERIC USI nodes Universal Serial Interface (USI) supports three types of serial interface such as UART, SPI and I2C. Each protocol works independently. USI can be configured to work as one of these protocols. Define all the USI nodes from the PERIC blocks (USI0-14), in all their possible configurations. These blocks have the TX/RX FIFO depth of 64 bytes. Reviewed-by: Peter Griffin Reviewed-by: Alim Akhtar Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240326151301.348932-6-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 769 +++++++++++++++++++ 1 file changed, 769 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 690deca37e4f..eddb6b326fde 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -373,6 +373,391 @@ interrupts = ; }; + usi1: usi@109000c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1000>; + status = "disabled"; + + hsi2c_1: i2c@10900000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_1: serial@10900000 { + compatible = "google,gs101-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart1_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_1: spi@10900000 { + compatible = "google,gs101-spi"; + reg = <0x10900000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@109100c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1004>; + status = "disabled"; + + hsi2c_2: i2c@10910000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@10910000 { + compatible = "google,gs101-uart"; + reg = <0x10910000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_2: spi@10910000 { + compatible = "google,gs101-spi"; + reg = <0x10910000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@109200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1008>; + status = "disabled"; + + hsi2c_3: i2c@10920000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@10920000 { + compatible = "google,gs101-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_3: spi@10920000 { + compatible = "google,gs101-spi"; + reg = <0x10920000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi4: usi@109300c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x100c>; + status = "disabled"; + + hsi2c_4: i2c@10930000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@10930000 { + compatible = "google,gs101-uart"; + reg = <0x10930000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_4: spi@10930000 { + compatible = "google,gs101-spi"; + reg = <0x10930000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@109400c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1010>; + status = "disabled"; + + hsi2c_5: i2c@10940000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@10940000 { + compatible = "google,gs101-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_5: spi@10940000 { + compatible = "google,gs101-spi"; + reg = <0x10940000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6: usi@109500c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1014>; + status = "disabled"; + + hsi2c_6: i2c@10950000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@10950000 { + compatible = "google,gs101-uart"; + reg = <0x10950000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_6: spi@10950000 { + compatible = "google,gs101-spi"; + reg = <0x10950000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi7: usi@109600c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1018>; + status = "disabled"; + + hsi2c_7: i2c@10960000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@10960000 { + compatible = "google,gs101-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_7: spi@10960000 { + compatible = "google,gs101-spi"; + reg = <0x10960000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + usi8: usi@109700c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x109700c0 0x20>; @@ -399,6 +784,33 @@ pinctrl-names = "default"; status = "disabled"; }; + + serial_8: serial@10970000 { + compatible = "google,gs101-uart"; + reg = <0x10970000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_8: spi@10970000 { + compatible = "google,gs101-spi"; + reg = <0x10970000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; }; usi_uart: usi@10a000c0 { @@ -428,6 +840,61 @@ }; }; + usi14: usi@10a200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10a200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric0 0x1028>; + status = "disabled"; + + hsi2c_14: i2c@10a20000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10a20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@10a20000 { + compatible = "google,gs101-uart"; + reg = <0x10a20000 0xc0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_14: spi@10a20000 { + compatible = "google,gs101-spi"; + reg = <0x10a20000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2>, + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_peric1: clock-controller@10c00000 { compatible = "google,gs101-cmu-peric1"; reg = <0x10c00000 0x4000>; @@ -450,6 +917,226 @@ interrupts = ; }; + usi0: usi@10d100c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1000>; + status = "disabled"; + + hsi2c_0: i2c@10d10000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_usi0: serial@10d10000 { + compatible = "google,gs101-uart"; + reg = <0x10d10000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart0_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_0: spi@10d10000 { + compatible = "google,gs101-spi"; + reg = <0x10d10000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@10d200c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1004>; + status = "disabled"; + + hsi2c_9: i2c@10d20000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@10d20000 { + compatible = "google,gs101-uart"; + reg = <0x10d20000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_9: spi@10d20000 { + compatible = "google,gs101-spi"; + reg = <0x10d20000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@10d300c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1008>; + status = "disabled"; + + hsi2c_10: i2c@10d30000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@10d30000 { + compatible = "google,gs101-uart"; + reg = <0x10d30000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_10: spi@10d30000 { + compatible = "google,gs101-spi"; + reg = <0x10d30000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@10d400c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x100c>; + status = "disabled"; + + hsi2c_11: i2c@10d40000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@10d40000 { + compatible = "google,gs101-uart"; + reg = <0x10d40000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_11: spi@10d40000 { + compatible = "google,gs101-spi"; + reg = <0x10d40000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + usi12: usi@10d500c0 { compatible = "google,gs101-usi", "samsung,exynos850-usi"; reg = <0x10d500c0 0x20>; @@ -476,6 +1163,88 @@ pinctrl-names = "default"; status = "disabled"; }; + + serial_12: serial@10d50000 { + compatible = "google,gs101-uart"; + reg = <0x10d50000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_12: spi@10d50000 { + compatible = "google,gs101-spi"; + reg = <0x10d50000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi13: usi@10d600c0 { + compatible = "google,gs101-usi", "samsung,exynos850-usi"; + reg = <0x10d600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&sysreg_peric1 0x1014>; + status = "disabled"; + + hsi2c_13: i2c@10d60000 { + compatible = "google,gs101-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10d60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@10d60000 { + compatible = "google,gs101-uart"; + reg = <0x10d60000 0xc0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_13: spi@10d60000 { + compatible = "google,gs101-spi"; + reg = <0x10d60000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6>, + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; }; pinctrl_hsi1: pinctrl@11840000 { From 4202fa93328d2d73218130cc4a4ccf9faa0efad3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 26 Feb 2024 21:08:26 +0800 Subject: [PATCH 118/969] arm64: dts: imx93: drop the 4th interrupt for ADC Per i.MX93 Reference Mannual Rev.4, 12/2023, there is no interrupt 268, drop it. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 601c94e1fac8..b8ef9b938856 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -509,8 +509,7 @@ reg = <0x44530000 0x10000>; interrupts = , , - , - ; + ; clocks = <&clk IMX93_CLK_ADC1_GATE>; clock-names = "ipg"; #io-channel-cells = <1>; From a1aa1852124130bd1f2c5c6100894b711a5d9b69 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 26 Feb 2024 22:26:28 +0100 Subject: [PATCH 119/969] ARM: dts: imx: Add UNI-T UTi260B thermal camera board Add DT for the UNI-T UTi260B handheld thermal camera. Reviewed-by: Stefan Wahren Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts | 566 ++++++++++++++++++ 2 files changed, 567 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 4052cad859fa..598361d0632e 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -355,6 +355,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-tarragon-slavext.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ + imx6ull-uti260b.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts new file mode 100644 index 000000000000..e4576d509a5b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-uti260b.dts @@ -0,0 +1,566 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Copyright (C) 2022-2024 Sebastian Reichel + +/dts-v1/; +#include "imx6ull.dtsi" +#include +#include +#include +#include + +/ { + model = "UNI-T UTi260B Thermal Camera"; + compatible = "uni-t,uti260b", "fsl,imx6ull"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + panel_backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_backlight_enable>; + power-supply = <®_vsd>; + pwms = <&pwm1 0 50000 0>; + }; + + battery: battery { + compatible = "simple-battery"; + /* generic 26650 battery */ + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <5000000>; + voltage-max-design-microvolt = <4200000>; + voltage-min-design-microvolt = <3300000>; + }; + + tp5000: charger { + compatible = "gpio-charger"; + charger-type = "usb-sdp"; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_charger_stat1>; + }; + + fuel-gauge { + compatible = "adc-battery"; + charged-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + io-channel-names = "voltage"; + io-channels = <&adc1 7>; + monitored-battery = <&battery>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_charger_stat2>; + power-supplies = <&tp5000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&mux_gpio_keys>; + autorepeat; + + up-key { + label = "Up"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + down-key { + label = "Down"; + gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + left-key { + label = "Left"; + gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + right-key { + label = "Right"; + gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ok-key { + label = "Ok"; + gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + return-key { + label = "Return"; + gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + play-key { + label = "Media"; + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + trigger-key { + label = "Trigger"; + gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + power-key { + label = "Power"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + light-key { + label = "Light"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&mux_led_ctrl>; + + led { + color = ; + function = LED_FUNCTION_FLASH; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_poweroff>; + }; + + reg_vref: regulator-vref-4v2 { + compatible = "regulator-fixed"; + regulator-name = "VREF_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + }; + + reg_vsd: regulator-vsd { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc1 { + #io-channel-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_adc>; + vref-supply = <®_vref>; + status = "okay"; +}; + +&csi { + pinctrl-names = "default"; + pinctrl-0 = <&mux_csi>; + status = "okay"; + + port { + parallel_from_gc0308: endpoint { + remote-endpoint = <&gc0308_to_parallel>; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_spi3>; + status = "okay"; + + panel@0 { + compatible = "inanbo,t28cp45tn89-v17"; + reg = <0>; + backlight = <&panel_backlight>; + power-supply = <®_vsd>; + spi-cpha; + spi-cpol; + spi-max-frequency = <1000000>; + spi-rx-bus-width = <0>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&gpio1 { + ir-reset-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + line-name = "ir-reset-gpio"; + output-low; + pinctrl-names = "default"; + pinctrl-0 = <&mux_ir_reset>; + }; +}; + +&gpio2 { + /* configuring this to output-high results in poweroff */ + power-en-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "power-en-gpio"; + output-low; + pinctrl-names = "default"; + pinctrl-0 = <&mux_poweroff2>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_i2c1>; + status = "okay"; + + camera@21 { + compatible = "galaxycore,gc0308"; + reg = <0x21>; + clocks = <&clks IMX6UL_CLK_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_gc0308>; + powerdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + vdd28-supply = <®_vsd>; + + port { + gc0308_to_parallel: endpoint { + remote-endpoint = <¶llel_from_gc0308>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <1>; /* active high */ + vsync-active = <1>; /* active high */ + data-active = <1>; /* active high */ + pclk-sample = <1>; /* sample on rising edge */ + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_i2c2>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lcdif { + assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; + pinctrl-names = "default"; + pinctrl-0 = <&mux_lcd_data>, <&mux_lcd_ctrl>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&mux_pwm>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&mux_uart>; + status = "okay"; +}; + +&usbotg1 { + /* USB-C connector */ + disable-over-current; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + /* thermal sensor */ + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +&usdhc1 { + /* MicroSD */ + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&mux_sdhc1>, <&mux_sdhc1_cd>; + pinctrl-1 = <&mux_sdhc1_100mhz>, <&mux_sdhc1_cd>; + pinctrl-2 = <&mux_sdhc1_200mhz>, <&mux_sdhc1_cd>; + wakeup-source; + vmmc-supply = <®_vsd>; + status = "okay"; +}; + +&usdhc2 { + /* eMMC */ + keep-power-in-suspend; + no-1-8-v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&mux_sdhc2>; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&mux_wdog>; +}; + +&iomuxc { + mux_adc: adcgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0xb0 + >; + }; + + mux_backlight_enable: blenablegrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3008 + >; + }; + + mux_charger_stat1: charger1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3008 + >; + }; + + mux_charger_stat2: charger2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x3008 + >; + }; + + mux_csi: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + mux_gc0308: gc0308grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1e038 + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b088 + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x1b088 + >; + }; + + mux_gpio_keys: gpiokeygrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x3008 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x3008 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x3008 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x3008 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x3008 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x3008 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x3008 + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x3008 + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x3008 + MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x3008 + >; + }; + + mux_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + mux_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8a8 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8a8 + >; + }; + + mux_ir_reset: irresetgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3008 + >; + }; + + mux_lcd_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + mux_lcd_data: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + mux_led_ctrl: ledctrlgrp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x3008 + >; + }; + + mux_poweroff: poweroffgrp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x3008 + >; + }; + + mux_poweroff2: poweroff2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x3008 + >; + }; + + mux_pwm: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + mux_sdhc1: sdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + mux_sdhc1_100mhz: sdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + mux_sdhc1_200mhz: sdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + mux_sdhc1_cd: sdhc1-cd-grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + mux_sdhc2: sdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + mux_spi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x3008 + >; + }; + + mux_uart: uartgrp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + mux_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; +}; From ac931ade1c7d9bc55c418aaa293448da9a5f725e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 27 Feb 2024 14:30:46 -0500 Subject: [PATCH 120/969] arm64: dts: imx8qm-mek: add adc0 support Add adc0 for imx8qm-mek board. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 77ac0efdfaad..0c4972724b04 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -39,6 +39,20 @@ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; }; &i2c1 { @@ -130,6 +144,12 @@ >; }; + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 From 43c7953ee3526f8f580f151d0f51089931eda8c7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 27 Feb 2024 14:30:47 -0500 Subject: [PATCH 121/969] arm64: dts: imx8qm-mek: add lpspi2 support Add lpspi2 support for imx8qm-mek board. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 0c4972724b04..66e0400d7bf8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -85,6 +85,21 @@ status = "okay"; }; +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -169,6 +184,20 @@ >; }; + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040 + IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040 + IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040 + >; + }; + + pinctrl_lpspi2_cs: lpspi2csgrp { + fsl,pins = < + IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 From d558a88bf95c6c05ef8594abc2bf48477cf0bb61 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 27 Feb 2024 14:30:48 -0500 Subject: [PATCH 122/969] arm64: dts: imx8qm-mek: add flexspi0 support Add flexspi0 support for imx8qm-mek board. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 37 ++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 66e0400d7bf8..5c6b39c6933f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -100,6 +100,22 @@ }; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -198,6 +214,27 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 From f6772c5882d2229b4e0d9aadbcac3eb922e822c0 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 27 Feb 2024 16:04:37 -0600 Subject: [PATCH 123/969] arm64: dts: imx8mp: add HDMI power-domains This adds the PGC and HDMI blk-ctrl nodes providing power control for HDMI subsystem peripherals. Signed-off-by: Adam Ford Signed-off-by: Lucas Stach Tested-by: Marek Vasut Tested-by: Luca Ceresoli Tested-by: Tommaso Merciai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bfc5c81a5bd4..c9bcb6641de7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -836,6 +836,23 @@ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; }; + pgc_hdmimix: power-domain@14 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <500000000>, <133000000>; + }; + + pgc_hdmi_phy: power-domain@15 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_mipi_phy2: power-domain@16 { #power-domain-cells = <0>; reg = ; @@ -1889,6 +1906,27 @@ #power-domain-cells = <1>; #clock-cells = <0>; }; + + hdmi_blk_ctrl: blk-ctrl@32fc0000 { + compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; + reg = <0x32fc0000 0x1000>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_HDMI_24M>, + <&clk IMX8MP_CLK_HDMI_FDCC_TST>; + clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; + power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmimix>, + <&pgc_hdmimix>, <&pgc_hdmi_phy>, + <&pgc_hdmimix>, <&pgc_hdmimix>; + power-domain-names = "bus", "irqsteer", "lcdif", + "pai", "pvi", "trng", + "hdmi-tx", "hdmi-tx-phy", + "hdcp", "hrv"; + #power-domain-cells = <1>; + }; }; pcie: pcie@33800000 { From cc1de24853245e79ed06a9975cebea197c622166 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 27 Feb 2024 16:04:38 -0600 Subject: [PATCH 124/969] arm64: dts: imx8mp: add HDMI irqsteer The HDMI irqsteer is a secondary interrupt controller within the HDMI subsystem that maps all HDMI peripheral IRQs into a single upstream IRQ line. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli Tested-by: Tommaso Merciai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c9bcb6641de7..18bfa7d9aa7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1927,6 +1927,19 @@ "hdcp", "hrv"; #power-domain-cells = <1>; }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; }; pcie: pcie@33800000 { From 14c46854e7575d1c270c04c4962ff14ad3f475a3 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 27 Feb 2024 16:04:39 -0600 Subject: [PATCH 125/969] arm64: dts: imx8mp: add HDMI display pipeline This adds the DT nodes for all the peripherals that make up the HDMI display pipeline. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Marek Vasut Tested-by: Luca Ceresoli Reviewed-by: Luca Ceresoli Tested-by: Tommaso Merciai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 96 +++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 18bfa7d9aa7f..e3510fef6030 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1940,6 +1940,102 @@ clock-names = "ipg"; power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; }; + + hdmi_pvi: display-bridge@32fc4000 { + compatible = "fsl,imx8mp-hdmi-pvi"; + reg = <0x32fc4000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <12>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pvi_from_lcdif3: endpoint { + remote-endpoint = <&lcdif3_to_pvi>; + }; + }; + + port@1 { + reg = <1>; + pvi_to_hdmi_tx: endpoint { + remote-endpoint = <&hdmi_tx_from_pvi>; + }; + }; + }; + }; + + lcdif3: display-controller@32fc6000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32fc6000 0x1000>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <8>; + clocks = <&hdmi_tx_phy>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif3_to_pvi: endpoint { + remote-endpoint = <&pvi_from_lcdif3>; + }; + }; + }; + + hdmi_tx: hdmi@32fd8000 { + compatible = "fsl,imx8mp-hdmi-tx"; + reg = <0x32fd8000 0x7eff>; + interrupt-parent = <&irqsteer_hdmi>; + interrupts = <0>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>, + <&clk IMX8MP_CLK_32K>, + <&hdmi_tx_phy>; + clock-names = "iahb", "isfr", "cec", "pix"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; + reg-io-width = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_tx_from_pvi: endpoint { + remote-endpoint = <&pvi_to_hdmi_tx>; + }; + }; + + port@1 { + reg = <1>; + /* Point endpoint to the HDMI connector */ + }; + }; + }; + + hdmi_tx_phy: phy@32fdff00 { + compatible = "fsl,imx8mp-hdmi-phy"; + reg = <0x32fdff00 0x100>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_24M>; + clock-names = "apb", "ref"; + assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie: pcie@33800000 { From bcf1b3eec61f2e35f4a0516a882b452ab9fc49b3 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 27 Feb 2024 16:04:40 -0600 Subject: [PATCH 126/969] arm64: defconfig: Enable DRM_IMX8MP_DW_HDMI_BRIDGE as module The i.MX8M Plus has support for an HDMI transmitter. The video is genereated by lcdif3, routed to the hdmi parallel video interface, then fed to a DW HDMI bridge to support up to 4K video output. Signed-off-by: Adam Ford Reviewed-by: Luca Ceresoli Tested-by: Luca Ceresoli Tested-by: Tommaso Merciai Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..c9964e5e1e7d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -890,6 +890,7 @@ CONFIG_DRM_ANALOGIX_ANX7625=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_IMX_DCSS=m From 12b1afc6f6a9a7bc4c76bbe2d98b708c362c06fb Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 28 Feb 2024 11:30:11 +0800 Subject: [PATCH 127/969] arm64: dts: imx8mp: Add AUD2HTX device node The AUD2HTX is a digital module that provides a bridge between the Audio Subsystem and the HDMI RTX Subsystem. This module includes intermediate storage to queue SDMA transactions prior to being synchronized and passed to the HDMI RTX Subsystem over the Audio Link. Signed-off-by: Shengjiu Wang Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e3510fef6030..3556773a6422 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1530,6 +1530,16 @@ status = "disabled"; }; + aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = ; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + status = "disabled"; + }; }; sdma3: dma-controller@30e00000 { From a9226157af7c15be4f608ac6799249442173075f Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 28 Feb 2024 11:30:12 +0800 Subject: [PATCH 128/969] arm64: dts: imx8mp-evk: Add HDMI audio sound card support AUD2HTX works as the cpu dai in HDMI audio sound card. This sound card only support playback/output. Signed-off-by: Shengjiu Wang Acked-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9beba8d6a0df..c83c480ddd5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -145,6 +145,13 @@ }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -198,6 +205,10 @@ cpu-supply = <®_arm>; }; +&aud2htx { + status = "okay"; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; From 224598e2d536259be4a3f7e198f7003d9fbfcc82 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 28 Feb 2024 11:30:13 +0800 Subject: [PATCH 129/969] arm64: dts: imx8mp-evk: Add PDM micphone sound card support Add PDM micphone sound card support, configure the pinmux. This sound card supports recording sound from PDM micphone and convert the PDM format data to PCM data. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 34 ++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c83c480ddd5c..8be5b2a57f27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -152,6 +152,20 @@ hdmi-out; }; + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -535,6 +549,16 @@ status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; @@ -801,6 +825,16 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 From e3b5697195c875dd297c83592763b1c1449983b7 Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Thu, 29 Feb 2024 13:53:37 +0530 Subject: [PATCH 130/969] ARM: dts: imx6ull: add seeed studio NPi dev board Add support for Seed Stuidos NPi i.MX6ULL SoM equipped with 512MB RAM and 8GB eMMC or 512MB NAND flash. Development board comes with either eMMC or NAND based SoM with peripheral interfaces like 2 x ethernet, 2 x USB, LCD, CSI and more. Signed-off-by: Parthiban Nallathambi Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../imx/imx6ull-seeed-npi-dev-board-emmc.dts | 19 + .../imx/imx6ull-seeed-npi-dev-board-nand.dts | 19 + .../nxp/imx/imx6ull-seeed-npi-dev-board.dtsi | 424 ++++++++++++++++++ .../boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi | 155 +++++++ 5 files changed, 619 insertions(+) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 598361d0632e..231c0d73a53e 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -349,6 +349,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-phytec-tauri-emmc.dtb \ imx6ull-phytec-tauri-nand.dtb \ + imx6ull-seeed-npi-dev-board-emmc.dtb \ + imx6ull-seeed-npi-dev-board-nand.dtb \ imx6ull-tarragon-master.dtb \ imx6ull-tarragon-micro.dtb \ imx6ull-tarragon-slave.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts new file mode 100644 index 000000000000..cfcd8783c31d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-emmc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Linumiz + * Author: Parthiban + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-seeed-npi.dtsi" +#include "imx6ull-seeed-npi-dev-board.dtsi" + +/ { + model = "Seeed NPi iMX6ULL Dev Board with NAND"; + compatible = "seeed,imx6ull-seeed-npi-emmc", "seeed,imx6ull-seeed-npi", "fsl,imx6ull"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts new file mode 100644 index 000000000000..87c9434b09c5 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board-nand.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Linumiz + * Author: Parthiban + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-seeed-npi.dtsi" +#include "imx6ull-seeed-npi-dev-board.dtsi" + +/ { + model = "Seeed NPi iMX6ULL Dev Board with NAND"; + compatible = "seeed,imx6ull-seeed-npi-nand", "seeed,imx6ull-seeed-npi", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi new file mode 100644 index 000000000000..6bb12e0bbc7e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Linumiz + * Author: Parthiban + */ + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_button>; + + button-0 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + label = "SW2"; + linux,code = ; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-blue { + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + label = "LED_B"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led-green { + gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + label = "LED_G"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led-red { + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + label = "LED_R"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led-user { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + label = "User"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + reg_5v_sys: regulator-5v-sys { + compatible = "regulator-fixed"; + regulator-name = "5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5v_sys>; + }; + + reg_3v3_in: regulator-3v3-in { + compatible = "regulator-fixed"; + regulator-name = "3V3_IN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5v_sys>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_3v3_in>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vmmc>; + enable-active-high; + regulator-always-on; + vin-supply = <®_3v3>; + }; +}; + +&csi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + status = "disabled"; /* LED Blue & Green shared */ +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&lcdif { + pinctrl-0 = <&pinctrl_lcdif>; + pinctrl-names = "default"; + status = "disabled"; +}; + +®_dcdc_3v3 { + vin-supply = <®_3v3_in>; +}; + +&sai2 { + assigned-clock-rates = <320000000>; + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_cd>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_button: buttongrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x0b0b0 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x0b0b0 + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + >; + }; + + pinctrl_lcdif: lcdif-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x79 + >; + }; + + pinctrl_reg_vmmc: usdhc1regvmmc { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pin = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pin = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pin = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pin = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pin = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_cd: usdhc1cd { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi new file mode 100644 index 000000000000..f5ad6b5c1ad0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Linumiz + * Author: Parthiban + */ + +#include + +/ { + model = "Seeed NPi-iMX6ULL Dev Board"; + compatible = "seeed,imx6ull-seeed-npi", "fsl,imx6ull"; + + reg_dcdc_3v3: regulator-dcdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "DCDC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_dram_1v35: regulator-dram-1v35 { + compatible = "regulator-fixed"; + regulator-name = "DRAM_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <®_dcdc_3v3>; + }; + + reg_vdd_arm_soc_in: regulator-vdd-arm-soc-in { + compatible = "regulator-fixed"; + regulator-name = "VDD_ARM_SOC_IN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_dcdc_3v3>; + }; + + reg_dcdc_1v8: regulator-dcdc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "DCDC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_dcdc_3v3>; + }; + + reg_sd1_vqmmc: regulator-sd1-vqmmc { + compatible = "regulator-fixed"; + regulator-name = "NVCC_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vqmmc>; + regulator-always-on; + vin-supply = <®_dcdc_1v8>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; +}; + +&usdhc1 { + vqmmc-supply = <®_sd1_vqmmc>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "disabled"; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_reg_vqmmc: usdhc1regvqmmc { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; From 17800d911f45bf8fa706da10fcb4c65d6a1b32bb Mon Sep 17 00:00:00 2001 From: Parthiban Nallathambi Date: Thu, 29 Feb 2024 13:53:36 +0530 Subject: [PATCH 131/969] dt-bindings: arm: fsl: Add Seeed studio NPi based boards NPi i.MX6ULL eMMC/NAND is Seed Studios SoM using i.MX6ULL. Development baords can be either based on NAND or eMMC SoM. Signed-off-by: Parthiban Nallathambi Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0027201e19f8..aa4b3a511768 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -813,6 +813,14 @@ properties: - const: tq,imx6ull-tqma6ull2l # MCIMX6Y2, LGA SoM variant - const: fsl,imx6ull + - description: Seeed Stuido i.MX6ULL SoM on dev boards + items: + - enum: + - seeed,imx6ull-seeed-npi-emmc + - seeed,imx6ull-seeed-npi-nand + - const: seeed,imx6ull-seeed-npi + - const: fsl,imx6ull + - description: i.MX6ULZ based Boards items: - enum: From c726439fd92b48f6a22732c1ff174857db132b16 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 1 Mar 2024 10:14:09 +0100 Subject: [PATCH 132/969] arm64: dts: imx8mm: Add empty DSI output endpoint Also add a corresponding label so overlays can reference that node. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 8a1b42b94dce..46473950e926 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1168,6 +1168,13 @@ remote-endpoint = <&lcdif_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; From 5cca780fd8c190f70e557be46a12584f4839a7f8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 1 Mar 2024 10:14:10 +0100 Subject: [PATCH 133/969] arm64: dts: imx8mn: Add empty DSI output endpoint Also add a corresponding label so overlays can reference that node. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 932c8b05c75f..b901ee0d2d03 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1104,6 +1104,13 @@ remote-endpoint = <&lcdif_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; From 4ba8634b0c63c2b7d03848141afbb2a17256f65d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 1 Mar 2024 10:14:11 +0100 Subject: [PATCH 134/969] arm64: dts: imx8mq: Add empty DSI output endpoint Also add a corresponding label so overlays can reference that node. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c6dc3ba0d43b..e03186bbc415 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1290,6 +1290,13 @@ remote-endpoint = <&lcdif_mipi_dsi>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; From 3bd897dc1e3933411ae6ffe7a4bc72312b5fbfa8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 1 Mar 2024 10:14:12 +0100 Subject: [PATCH 135/969] arm64: dts: imx8mp: Add empty DSI output endpoint Also add a corresponding label so overlays can reference that node. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3556773a6422..9f3e7c23b2ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1752,6 +1752,13 @@ remote-endpoint = <&lcdif1_to_dsim>; }; }; + + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + }; + }; }; }; From 0dccd835f0d86a51c1a4caca2160c5ed4d224881 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 1 Mar 2024 10:14:13 +0100 Subject: [PATCH 136/969] arm64: dts: mba8mx: Simplify DSI connection With the DSI output label in place, use the phandle directly. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/mba8mx.dtsi | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 427467df42bf..815241526a0d 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -316,17 +316,11 @@ &mipi_dsi { samsung,burst-clock-frequency = <891000000>; samsung,esc-clock-frequency = <20000000>; +}; - ports { - port@1 { - reg = <1>; - - mipi_dsi_out: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&lvds_bridge_in>; - }; - }; - }; +&mipi_dsi_out { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_bridge_in>; }; &pwm3 { From 5582e357d0c6bfdc889773ca3c9b7b0dd31dc334 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 28 Mar 2024 08:45:44 +0100 Subject: [PATCH 137/969] arm64: dts: qcom: pm6150: correct Type-C compatible The first part of the compatible of Type-C node misses ending quote, thus we have one long compatible consisting of two compatible strings leading to dtbs_check warnings: sc7180-idp.dtb: usb-vbus-regulator@1100: compatible:0: 'qcom,pm6150-vbus-reg,\n qcom,pm8150b-vbus-reg' does not match '^[a-zA-Z0-9][a-zA-Z0-9,+\\-._/]+$' sc7180-idp.dtb: /soc@0/spmi@c440000/pmic@0/usb-vbus-regulator@1100: failed to match any schema with compatible: ['qcom,pm6150-vbus-reg,\n qcom,pm8150b-vbus-reg'] Reported-by: Rob Herring Fixes: f81c2f01cad6 ("arm64: dts: qcom: pm6150: define USB-C related blocks") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240328074544.5076-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 11158c2bd524..b20a639cddf3 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -71,8 +71,8 @@ }; pm6150_typec: typec@1500 { - compatible = "qcom,pm6150-typec, - qcom,pm8150b-typec"; + compatible = "qcom,pm6150-typec", + "qcom,pm8150b-typec"; reg = <0x1500>, <0x1700>; interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, From 18af50f17c5c255a42b6a88413d49ab37f64a88f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 5 Mar 2024 12:20:45 -0800 Subject: [PATCH 138/969] arm64: dts: imx8mp-venice-gw74xx-imx219.dtso: fix dt warning Fix the following warning from a 'make dtbs W=1': arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso:65.10-70.5: Warning (unit_address_vs_reg): /fragment@3/__overlay__/ports/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-venice-gw74xx-imx219.dtso | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso index 270a9114da97..edf22ff549a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso @@ -62,12 +62,25 @@ status = "okay"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + mipi_csi_0_in: endpoint { remote-endpoint = <&imx219_to_mipi_csi2>; data-lanes = <1 2>; }; }; + + port@1 { + reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; + }; }; }; From cdba4a5c81d73a4846119313a3cf0a333c382066 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 12 Mar 2024 20:56:54 +0100 Subject: [PATCH 139/969] arm64: dts: fsl-lx2162a-som: add description for rtc SolidRun LX2162A SoM has an RTC on bus IIC6 (dts i2c5). Enable this bus and add description for the rtc. Signed-off-by: Josua Mayer Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi index 0580ea30cfbc..e914291e63a1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -71,3 +71,12 @@ reg = <0x54>; }; }; + +&i2c5 { + status = "okay"; + + rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; From 8afaff6951edaf1101e2514d54f0105d38615005 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 12 Mar 2024 20:56:55 +0100 Subject: [PATCH 140/969] arm64: dts: fsl-lx2162a-clearfog: add alias for i2c bus iic6 SoM dts has enabled i2c bus IIC6 (dts i2c5), but defines no aliases. LX2162A Clearfog dts has aliases for all i2c buses to ensure predictable numbering for userspace. Add an additional alias for this extra bus. Signed-off-by: Josua Mayer Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 9f88583aa25e..eafef8718a0f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -25,6 +25,7 @@ i2c7 = &mpcie1_i2c; i2c8 = &mpcie0_i2c; i2c9 = &pcieclk_i2c; + i2c10 = &i2c5; mmc0 = &esdhc0; mmc1 = &esdhc1; serial0 = &uart0; From 9a810c1b0340984676f025d6917651d544ca7203 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 5 Mar 2024 12:20:15 -0800 Subject: [PATCH 141/969] arm64: dts: imx8mp-venice-gw74xx: add ADC rail for VDD_1P0 The imx8mp-venice-gw74xx revB PCB added an ADC rail for VDD_1P0. Add it to the GSC ADC rails. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index cae586cd45bd..a77e9a44d9fa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -404,6 +404,12 @@ label = "vdd_dram"; }; + channel@9e { + gw,mode = <2>; + reg = <0x9e>; + label = "vdd_1p0"; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; From 3436ded09656f1f49e064c5e791656acf0dd25c5 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 30 Mar 2024 18:01:33 +0800 Subject: [PATCH 142/969] arm64: dts: rockchip: Enable gpu on Cool Pi CM5 Enable mali gpu node and add the board specific supply-regulator. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20240330100134.3588223-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index cce1c8e83587..def4fb0c04ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -136,6 +136,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; status = "okay"; From 604552d0102c4260ef2561b8c84f849e43731678 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sat, 30 Mar 2024 18:01:34 +0800 Subject: [PATCH 143/969] arm64: dts: rockchip: Enable gpu on Cool Pi 4B Enable mali gpu node and add the board specific supply-regulator. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20240330100134.3588223-2-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index e037bf9db75a..25a2ae7d4827 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -203,6 +203,11 @@ cpu-supply = <&vdd_cpu_big1_s0>; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; status = "okay"; From f720dd9b8b6d8b2160beda789429d5489ce8a099 Mon Sep 17 00:00:00 2001 From: Folker Schwesinger Date: Wed, 27 Mar 2024 20:26:37 +0100 Subject: [PATCH 144/969] arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK Pi 4 Commit 8b5c2b45b8f0 disabled the internal pull-down for the strobe line causing I/O errors in HS400 mode for various eMMC modules. Enable the internal strobe pull-down for ROCK Pi 4 boards. Also re-enable HS400 mode, that was replaced with HS200 mode as a workaround for the stability issues in: cee572756aa2 ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4"). This was tested on ROCK 4SE and ROCK Pi 4B+. Fixes: 8b5c2b45b8f0 ("phy: rockchip: set pulldown for strobe line in dts") Signed-off-by: Folker Schwesinger Reviewed-by: Dragan Simic Link: https://lore.kernel.org/r/20240327192641.14220-2-dev@folker-schwesinger.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 281a12180703..b9d6284bb804 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -194,6 +194,7 @@ }; &emmc_phy { + rockchip,enable-strobe-pulldown; status = "okay"; }; @@ -648,7 +649,8 @@ &sdhci { max-frequency = <150000000>; bus-width = <8>; - mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; non-removable; status = "okay"; }; From c1b1f340dd7db11f273e426e110697551c9f501f Mon Sep 17 00:00:00 2001 From: Folker Schwesinger Date: Wed, 27 Mar 2024 20:26:38 +0100 Subject: [PATCH 145/969] arm64: dts: rockchip: Add enable-strobe-pulldown to emmc phy on ROCK 4C+ Commit 8b5c2b45b8f0 disabled the internal pull-down for the strobe line causing I/O errors in HS400 mode for various eMMC modules. Enable the internal strobe pull-down for the ROCK 4C+ board. Also re-enable HS400 mode, that was replaced with HS200 mode as a workaround for the stability issues in: 2bd1d2dd808c ("arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+"). Fixes: 8b5c2b45b8f0 ("phy: rockchip: set pulldown for strobe line in dts") Signed-off-by: Folker Schwesinger Reviewed-by: Dragan Simic Link: https://lore.kernel.org/r/20240327192641.14220-3-dev@folker-schwesinger.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index 7baf9d1b22fd..972aea843afd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -151,6 +151,7 @@ }; &emmc_phy { + rockchip,enable-strobe-pulldown; status = "okay"; }; @@ -549,7 +550,8 @@ &sdhci { max-frequency = <150000000>; bus-width = <8>; - mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; non-removable; status = "okay"; }; From 6dd62ce41c66522ac9f1f0d52907b0ba2bc41535 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 14 Mar 2024 15:17:35 +0100 Subject: [PATCH 146/969] ARM: dts: imx6qdl: mba6: Add missing vdd-supply for on-board USB hub This adds vdd-supply powering the USB hub. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index 4d2abcd44eff..9bf1cc6f508d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -298,6 +298,7 @@ reg = <1>; #address-cells = <1>; #size-cells = <0>; + vdd-supply = <®_mba6_3p3v>; ethernet@1 { compatible = "usb424,9e00"; From 3eaf1870d7455b88436cc08dbaa459528b96da53 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 14 Mar 2024 15:17:36 +0100 Subject: [PATCH 147/969] ARM: dts: imx6qdl: Remove LCD.CONTRAST pinctrl from muxing GPIO4_IO20 is unused on MBA6x, unless LVDS display is attached. Remove the pinctrl for GPIO4_IO20, so it can be used otherwise. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index 9bf1cc6f508d..60aa1e947f62 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -442,8 +442,6 @@ pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b099 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x0001b099 From a196684376d51bf6b1d2ad6542f5ea17f243fe82 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 19 Mar 2024 05:37:09 +0100 Subject: [PATCH 148/969] arm64: dts: imx8mp: Describe CSI2 GPIO expander on i.MX8MP DHCOM PDK3 board The production PDK3 carrier board rev.200 contains additional GPIO expander to control power and reset signals for each CSI2 plug separately. Describe this expander in the carrier board DT. The label is used by sensor DTOs to reference the expander and its signals. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index b749e28e5ede..ac7ec7533a3c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -167,6 +167,16 @@ VDDIO-supply = <®_vdd_3p3v_awo>; }; + csi2exp: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "CSI2_#RESET", "CSI2_#PWDN", + "CSI_#PWDN", "CSI_#RESET"; + }; + typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; From 54c7a04ea3afa6c566e57b342b8e0ff6e488cdd7 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Wed, 20 Mar 2024 14:28:49 +0800 Subject: [PATCH 149/969] arm64: dts: imx93-11x11-evk: add pca9451a support Support pca9451a on imx93-11x11-evk. Signed-off-by: Joy Zou Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 9921ea13ab48..07e85a30a25f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -183,6 +183,104 @@ status = "okay"; }; +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -238,6 +336,19 @@ >; }; + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < From eefb9049875a693cbf87d97d5db2a8ae305cb83b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Mar 2024 11:31:15 -0300 Subject: [PATCH 150/969] ARM: dts: imx7s: Add snvs-poweroff support Just like other i.MX devices, i.MX7 also supports using the SNVS block to poweroff the chip. Add an entry for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx7s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 9c81c6baa2d3..22dd72499ef2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -636,6 +636,15 @@ clock-names = "snvs-rtc"; }; + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + value = <0x60>; + mask = <0x60>; + status = "disabled"; + }; + snvs_pwrkey: snvs-powerkey { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; From 3cdce0b531fbf6ad1d06b52c49b191a5b18d59ea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 12 Mar 2024 10:02:34 +0100 Subject: [PATCH 151/969] arm64: dts: renesas: r8a779h0: Add remaining HSCIF nodes Add device nodes for the remaining High Speed Serial Communication Interfaces with FIFO (HSCIF) on the Renesas R-Car V4M (R8A779H0) SoC, including DMA support and the optional external clock source used by HSCIF2. Based on a patch in the BSP by Nghia Nguyen. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b39f081db01fde2d1bf83a193f25b295cfeb002d.1709741303.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 59 ++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index a01929231e08..4bad906bf2cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -144,13 +144,19 @@ method = "smc"; }; - /* External SCIF clock - to be overridden by boards that provide it */ + /* External SCIF clocks - to be overridden by boards that provide them */ scif_clk: scif-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; + scif_clk2: scif-clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -413,6 +419,57 @@ status = "disabled"; }; + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk2>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + dmas = <&dmac1 0x37>, <&dmac1 0x36>, + <&dmac2 0x37>, <&dmac2 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779h0", "renesas,etheravb-rcar-gen4"; From 0833ec2fc4b1f01a82a83967a6386a0579a85898 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 12 Mar 2024 10:02:35 +0100 Subject: [PATCH 152/969] arm64: dts: renesas: r8a779h0: Add SCIF nodes Add device nodes for the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car V4M (R8A779H0) SoC, including DMA support. Based on a patch in the BSP by Nghia Nguyen. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/1285062a78f8ec810d2c93366c2c9dc1f883683f.1709741303.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 4bad906bf2cb..3a40b56c4dcf 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -614,6 +614,74 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + dmas = <&dmac1 0x57>, <&dmac1 0x56>, + <&dmac2 0x57>, <&dmac2 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779h0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk2>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + dmas = <&dmac1 0x59>, <&dmac1 0x58>, + <&dmac2 0x59>, <&dmac2 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + status = "disabled"; + }; + dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; From 20f4b85a26a58258611dcffe81bef99ce306bbbc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 12 Mar 2024 10:02:36 +0100 Subject: [PATCH 153/969] arm64: dts: renesas: gray-hawk-single: Add second debug serial port Describe the second debug serial port (CN9800) on the Gray Hawk Single board, as provided by HSCIF2, including the SCIF_CLK2 external clock source, and all related pin control. Based on a patch for Gray Hawk in the BSP by Nghia Nguyen. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/6e1faff6a717cb8344661bafcae5db5dcfb53a90.1709741303.git.geert+renesas@glider.be --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index bc8616a56c03..acf1d625ec41 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -18,6 +18,7 @@ aliases { serial0 = &hscif0; + serial1 = &hscif2; ethernet0 = &avb0; }; @@ -90,6 +91,14 @@ status = "okay"; }; +&hscif2 { + pinctrl-0 = <&hscif2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -144,7 +153,7 @@ }; &pfc { - pinctrl-0 = <&scif_clk_pins>; + pinctrl-0 = <&scif_clk_pins>, <&scif_clk2_pins>; pinctrl-names = "default"; avb0_pins: avb0 { @@ -170,6 +179,11 @@ function = "hscif0"; }; + hscif2_pins: hscif2 { + groups = "hscif2_data", "hscif2_ctrl"; + function = "hscif2"; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; @@ -190,6 +204,11 @@ groups = "scif_clk"; function = "scif_clk"; }; + + scif_clk2_pins: scif-clk2 { + groups = "scif_clk2"; + function = "scif_clk2"; + }; }; &rpc { @@ -228,3 +247,7 @@ &scif_clk { clock-frequency = <24000000>; }; + +&scif_clk2 { + clock-frequency = <24000000>; +}; From b98807c7befe675d27a81406f9966f8c92bb88bb Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Fri, 22 Mar 2024 12:46:20 +0000 Subject: [PATCH 154/969] arm64: dts: freescale: verdin-imx8mp: enable Verdin I2C_3_HDMI interface Enable Verdin I2C_3_HDMI interface on iMX8MP Toradex Verdin boards. Signed-off-by: Vitor Soares Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-verdin-dahlia.dtsi | 5 ++++ .../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 5 ++++ .../dts/freescale/imx8mp-verdin-mallow.dtsi | 5 ++++ .../dts/freescale/imx8mp-verdin-yavia.dtsi | 5 ++++ .../boot/dts/freescale/imx8mp-verdin.dtsi | 27 ++++++++++++++++--- 5 files changed, 43 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 7e9e4b13b5c5..8d954259085f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -110,6 +110,11 @@ }; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index a509b2b7fa85..e5400140e5c6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -131,6 +131,11 @@ }; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi index 8482393f3cac..1d15f7449c58 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -112,6 +112,11 @@ status = "okay"; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index db1722f0d80e..3a8542266d85 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -117,6 +117,11 @@ status = "okay"; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + status = "okay"; +}; + /* Verdin PCIE_1 */ &pcie { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index faa17cbbe2fd..f033d4310305 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -664,8 +664,6 @@ }; }; -/* TODO: Verdin I2C_3_HDMI */ - /* Verdin I2C_4_CSI */ &i2c3 { clock-frequency = <400000>; @@ -764,6 +762,16 @@ }; }; +/* Verdin I2C_3_HDMI */ +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + /* Verdin PCIE_1 */ &pcie { pinctrl-names = "default"; @@ -1106,8 +1114,6 @@ pinctrl_hdmi_hog: hdmihoggrp { fsl,pins = , /* SODIMM 63 */ - , /* SODIMM 59 */ - , /* SODIMM 57 */ ; /* SODIMM 61 */ }; @@ -1163,6 +1169,19 @@ ; /* SODIMM 12 */ }; + /* Verdin I2C_3_HDMI */ + pinctrl_i2c5: i2c5grp { + fsl,pins = + , /* SODIMM 59 */ + ; /* SODIMM 57 */ + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = + , /* SODIMM 59 */ + ; /* SODIMM 57 */ + }; + /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = From f86f5471f1381a35325149bdbf19c4917c68d005 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:46 +0200 Subject: [PATCH 155/969] arm64: dts: marvell: ap80x: fix IOMMU unit address Correct the IOMMU device node unit address to match "reg" and fix dtc W=1 warnings: armada-ap80x.dtsi:64.24-80.6: Warning (simple_bus_reg): /ap807/config-space@f0000000/iommu@5000000: simple-bus unit address format error, expected "100000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 7ec7c789d87e..fdf88cd0eb02 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -61,7 +61,7 @@ compatible = "simple-bus"; ranges = <0x0 0x0 0xf0000000 0x1000000>; - smmu: iommu@5000000 { + smmu: iommu@100000 { compatible = "marvell,ap806-smmu-500", "arm,mmu-500"; reg = <0x100000 0x100000>; dma-coherent; From 270bd4c3ce3608cfda90aa957f8ea03895edf7b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:47 +0200 Subject: [PATCH 156/969] arm64: dts: marvell: cn9130-db: drop unneeded flash address/size-cells Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: cn9130-db.dtsi:313.10-336.4: Warning (avoid_unnecessary_addr_size): /cp0/config-space@f2000000/spi@700680/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 6eb6a175de38..01d6645ddba7 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -311,8 +311,6 @@ reg = <0x700680 0x50>; flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; compatible = "jedec,spi-nor"; reg = <0x0>; /* On-board MUX does not allow higher frequencies */ From 5d83c23bc77b8ed49bea7850a1b7fe36e5686328 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:48 +0200 Subject: [PATCH 157/969] arm64: dts: marvell: cn9131-db: drop unneeded flash address/size-cells Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: cn9131-db.dtsi:140.10-163.4: Warning (avoid_unnecessary_addr_size): /cp1/config-space@f4000000/spi@700680/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index ff8422fae31b..8f2523786cfb 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -138,8 +138,6 @@ reg = <0x700680 0x50>; flash@0 { - #address-cells = <0x1>; - #size-cells = <0x1>; compatible = "jedec,spi-nor"; reg = <0x0>; /* On-board MUX does not allow higher frequencies */ From 0f78d6da0eea475d5eb50c32b6eced4bd4d95b31 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:49 +0200 Subject: [PATCH 158/969] arm64: dts: marvell: cn9130-db: drop wrong unit-addresses Top-level nodes, not being on MMIO bus, do not have "reg" properties and should not have unit addresses. Correct their name as well to match "Generic node names" recommendation from Devicetree specification. This also fixes dtc W=1 warnings: cn9130-db.dtsi:28.11-31.4: Warning (unique_unit_address_if_enabled): /memory@0: duplicate unit-address (also used in node /ap0_sd_vccq@0) cn9130-db.dtsi:28.11-31.4: Warning (unique_unit_address_if_enabled): /memory@0: duplicate unit-address (also used in node /cp0_usb3_vbus@0) cn9130-db.dtsi:33.33-40.4: Warning (unique_unit_address_if_enabled): /ap0_sd_vccq@0: duplicate unit-address (also used in node /cp0_usb3_vbus@0) cn9130-db.dtsi:28.11-31.4: Warning (unique_unit_address_if_enabled): /memory@0: duplicate unit-address (also used in node /cp0_usb3_phy@0) cn9130-db.dtsi:33.33-40.4: Warning (unit_address_vs_reg): /ap0_sd_vccq@0: node has a unit name, but no reg or ranges property cn9130-db.dtsi:42.38-49.4: Warning (unit_address_vs_reg): /cp0_usb3_vbus@0: node has a unit name, but no reg or ranges property cn9130-db.dtsi:51.34-54.4: Warning (unit_address_vs_reg): /cp0_usb3_phy@0: node has a unit name, but no reg or ranges property cn9130-db.dtsi:56.38-63.4: Warning (unit_address_vs_reg): /cp0_usb3_vbus@1: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 6 +++--- arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 12 ++++++------ 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 01d6645ddba7..be56a2336265 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -30,7 +30,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ap0_reg_sd_vccq: ap0_sd_vccq@0 { + ap0_reg_sd_vccq: regulator-1 { compatible = "regulator-gpio"; regulator-name = "ap0_sd_vccq"; regulator-min-microvolt = <1800000>; @@ -39,7 +39,7 @@ states = <1800000 0x1 3300000 0x0>; }; - cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 { + cp0_reg_usb3_vbus0: regulator-2 { compatible = "regulator-fixed"; regulator-name = "cp0-xhci0-vbus"; regulator-min-microvolt = <5000000>; @@ -48,12 +48,12 @@ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; }; - cp0_usb3_0_phy0: cp0_usb3_phy@0 { + cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp0_reg_usb3_vbus0>; }; - cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + cp0_reg_usb3_vbus1: regulator-3 { compatible = "regulator-fixed"; regulator-name = "cp0-xhci1-vbus"; regulator-min-microvolt = <5000000>; @@ -62,12 +62,12 @@ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; }; - cp0_usb3_0_phy1: cp0_usb3_phy@1 { + cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp0_reg_usb3_vbus1>; }; - cp0_reg_sd_vccq: cp0_sd_vccq@0 { + cp0_reg_sd_vccq: regulator-4 { compatible = "regulator-gpio"; regulator-name = "cp0_sd_vccq"; regulator-min-microvolt = <1800000>; @@ -77,7 +77,7 @@ 3300000 0x0>; }; - cp0_reg_sd_vcc: cp0_sd_vcc@0 { + cp0_reg_sd_vcc: regulator-5 { compatible = "regulator-fixed"; regulator-name = "cp0_sd_vcc"; regulator-min-microvolt = <3300000>; @@ -87,7 +87,7 @@ regulator-always-on; }; - cp0_sfp_eth0: sfp-eth@0 { + cp0_sfp_eth0: sfp-eth-1 { compatible = "sff,sfp"; i2c-bus = <&cp0_sfpp0_i2c>; los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index 8f2523786cfb..ad7360c83048 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -18,7 +18,7 @@ ethernet4 = &cp1_eth1; }; - cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 { + cp1_reg_usb3_vbus0: regulator-6 { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&cp1_xhci0_vbus_pins>; @@ -29,12 +29,12 @@ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>; }; - cp1_usb3_0_phy0: cp1_usb3_phy0 { + cp1_usb3_0_phy0: usb-phy-3 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp1_reg_usb3_vbus0>; }; - cp1_sfp_eth1: sfp-eth1 { + cp1_sfp_eth1: sfp-eth-2 { compatible = "sff,sfp"; i2c-bus = <&cp1_i2c0>; los-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index 512a4fa2861e..e753cfdac697 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -17,7 +17,7 @@ ethernet5 = &cp2_eth0; }; - cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 { + cp2_reg_usb3_vbus0: regulator-7 { compatible = "regulator-fixed"; regulator-name = "cp2-xhci0-vbus"; regulator-min-microvolt = <5000000>; @@ -26,12 +26,12 @@ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>; }; - cp2_usb3_0_phy0: cp2_usb3_phy0 { + cp2_usb3_0_phy0: usb-phy-4 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp2_reg_usb3_vbus0>; }; - cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 { + cp2_reg_usb3_vbus1: regulator-8 { compatible = "regulator-fixed"; regulator-name = "cp2-xhci1-vbus"; regulator-min-microvolt = <5000000>; @@ -40,12 +40,12 @@ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>; }; - cp2_usb3_0_phy1: cp2_usb3_phy1 { + cp2_usb3_0_phy1: usb-phy-5 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp2_reg_usb3_vbus1>; }; - cp2_reg_sd_vccq: cp2_sd_vccq@0 { + cp2_reg_sd_vccq: regulator-9 { compatible = "regulator-gpio"; regulator-name = "cp2_sd_vcc"; regulator-min-microvolt = <1800000>; @@ -54,7 +54,7 @@ states = <1800000 0x1 3300000 0x0>; }; - cp2_sfp_eth0: sfp-eth0 { + cp2_sfp_eth0: sfp-eth-3 { compatible = "sff,sfp"; i2c-bus = <&cp2_sfpp0_i2c>; los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>; From f69025d38d8e31ccf37aa3842cf3b7fbd13f7e5c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:50 +0200 Subject: [PATCH 159/969] arm64: dts: marvell: cn9130-crb: drop wrong unit-addresses Top-level nodes, not being on MMIO bus, do not have "reg" properties and should not have unit addresses. Correct their name as well to match "Generic node names" recommendation from Devicetree specification. This also fixes dtc W=1 warnings: cn9130-crb.dtsi:29.35-37.4: Warning (unit_address_vs_reg): /ap0_mmc_vccq@0: node has a unit name, but no reg or ranges property cn9130-crb.dtsi:39.38-46.4: Warning (unit_address_vs_reg): /cp0_usb3_vbus@1: node has a unit name, but no reg or ranges property cn9130-crb.dtsi:57.33-65.4: Warning (unit_address_vs_reg): /cp0_sd_vccq@0: node has a unit name, but no reg or ranges property cn9130-crb.dtsi:67.31-75.4: Warning (unit_address_vs_reg): /cp0_sd_vcc@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 6fcc34f7b464..d48dd6bca6e5 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -26,7 +26,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - ap0_reg_mmc_vccq: ap0_mmc_vccq@0 { + ap0_reg_mmc_vccq: regulator-1 { compatible = "regulator-gpio"; regulator-name = "ap0_mmc_vccq"; regulator-min-microvolt = <1800000>; @@ -36,7 +36,7 @@ 3300000 0x0>; }; - cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 { + cp0_reg_usb3_vbus1: regulator-2 { compatible = "regulator-fixed"; regulator-name = "cp0-xhci1-vbus"; regulator-min-microvolt = <5000000>; @@ -45,16 +45,16 @@ gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; }; - cp0_usb3_0_phy0: cp0_usb3_phy0 { + cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; }; - cp0_usb3_0_phy1: cp0_usb3_phy1 { + cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; vcc-supply = <&cp0_reg_usb3_vbus1>; }; - cp0_reg_sd_vccq: cp0_sd_vccq@0 { + cp0_reg_sd_vccq: regulator-3 { compatible = "regulator-gpio"; regulator-name = "cp0_sd_vccq"; regulator-min-microvolt = <1800000>; @@ -64,7 +64,7 @@ 3300000 0x0>; }; - cp0_reg_sd_vcc: cp0_sd_vcc@0 { + cp0_reg_sd_vcc: regulator-4 { compatible = "regulator-fixed"; regulator-name = "cp0_sd_vcc"; regulator-min-microvolt = <3300000>; From 058bfa0ead87e05ffdc837d534e68a8ca6b73dc4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:10:51 +0200 Subject: [PATCH 160/969] arm64: dts: marvell: cn9130-crb: drop unneeded "status" Devices are enabled by default. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index d48dd6bca6e5..5e7d6de3cdde 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -82,7 +82,6 @@ tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <3000>; - status = "okay"; }; }; From f0c31febdaa7046b9652fe66da901b8bc0e9e828 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Feb 2024 11:51:37 +0100 Subject: [PATCH 161/969] arm64: dts: sprd: minor whitespace cleanup The DTS code coding style expects exactly one space before '{' character. Link: https://lore.kernel.org/r/20240208105137.128601-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index e27eb3ed1d47..2b8867fad285 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -113,7 +113,7 @@ }; }; - idle-states{ + idle-states { entry-method = "psci"; CORE_PD: core_pd { diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts index 6b95fd94cee3..de468189a4fb 100644 --- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts @@ -24,7 +24,7 @@ spi0 = &adi_bus; }; - memory{ + memory { device_type = "memory"; reg = <0x0 0x80000000 0 0x60000000>, <0x1 0x80000000 0 0x60000000>; From 61f1a8f4abba8795d8e81df1bdee03da9000f0e1 Mon Sep 17 00:00:00 2001 From: Wadim Mueller Date: Sun, 24 Mar 2024 22:43:23 +0100 Subject: [PATCH 162/969] dt-bindings: arm: fsl: add NXP S32G3 board Add bindings for NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) [1] [1] https://www.nxp.com/design/design-center/designs/s32g3-vehicle-networking-reference-design:S32G-VNP-RDB3 Signed-off-by: Wadim Mueller Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index aa4b3a511768..35494a294c6b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1544,6 +1544,12 @@ properties: - nxp,s32g274a-rdb2 - const: nxp,s32g2 + - description: S32G3 based Boards + items: + - enum: + - nxp,s32g399a-rdb3 + - const: nxp,s32g3 + - description: S32V234 based Boards items: - enum: From 44b305a2de85b810135ec99f5bd3d67e1ba14232 Mon Sep 17 00:00:00 2001 From: Wadim Mueller Date: Sun, 24 Mar 2024 22:43:26 +0100 Subject: [PATCH 163/969] arm64: dts: S32G3: Introduce device tree for S32G-VNP-RDB3 This commit adds device tree support for the NXP S32G3-based S32G-VNP-RDB3 Board [1]. The S32G3 features an 8-core ARM Cortex-A53 based SoC developed by NXP. The device tree files are derived from the official NXP downstream Linux tree [2]. This addition encompasses a limited selection of peripherals that are upstream-supported. Apart from the ARM System Modules (GIC, Generic Timer, etc.), the following IPs have been validated: * UART: fsl-linflexuart * SDHC: fsl-imx-esdhc Clock settings for the chip rely on ATF Firmware [3]. Pin control integration into the device tree is pending and currently relies on Firmware/U-Boot settings [4]. These changes were validated using BSP39 Firmware/U-Boot from NXP [5]. The modifications enable booting the official Ubuntu 22.04 from NXP on the RDB3 with default settings from the SD card and eMMC. [1] https://www.nxp.com/design/design-center/designs/s32g3-vehicle-networking-reference-design:S32G-VNP-RDB3 [2] https://github.com/nxp-auto-linux/linux [3] https://github.com/nxp-auto-linux/arm-trusted-firmware [4] https://github.com/nxp-auto-linux/u-boot [5] https://github.com/nxp-auto-linux/auto_yocto_bsp Signed-off-by: Wadim Mueller Tested-by: Ghennadi Procopciuc Reviewed-by: Ghennadi Procopciuc Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/s32g3.dtsi | 233 ++++++++++++++++++ .../boot/dts/freescale/s32g399a-rdb3.dts | 45 ++++ 3 files changed, 279 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32g3.dtsi create mode 100644 arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 045250d0a040..768feb886ea2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -259,4 +259,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb +dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi new file mode 100644 index 000000000000..c1b08992754b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2021-2023 NXP + * + * Authors: Ghennadi Procopciuc + * Ciprian Costea + * Andra-Teodora Ilie + */ + +#include + +/ { + compatible = "nxp,s32g3"; + interrupt-parent = <&gic>; + #address-cells = <0x02>; + #size-cells = <0x02>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + clocks = <&dfs 0>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0xc20000fe>; + #address-cells = <1>; + #size-cells = <0>; + + dfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shm@d0000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0xd0000000 0x0 0x80>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x80000000>; + + uart0: serial@401c8000 { + compatible = "nxp,s32g3-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401c8000 0x3000>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@401cc000 { + compatible = "nxp,s32g3-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401cc000 0x3000>; + interrupts = ; + status = "disabled"; + }; + + uart2: serial@402bc000 { + compatible = "nxp,s32g3-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x402bc000 0x3000>; + interrupts = ; + status = "disabled"; + }; + + usdhc0: mmc@402f0000 { + compatible = "nxp,s32g3-usdhc", + "nxp,s32g2-usdhc"; + reg = <0x402f0000 0x1000>; + interrupts = ; + clocks = <&clks 32>, + <&clks 31>, + <&clks 33>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + gic: interrupt-controller@50800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50800000 0x10000>, + <0x50900000 0x200000>, + <0x50400000 0x2000>, + <0x50410000 0x2000>, + <0x50420000 0x2000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , /* sec-phys */ + , /* phys */ + , /* virt */ + , /* hyp-phys */ + ; /* hyp-virt */ + arm,no-tick-in-suspend; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts new file mode 100644 index 000000000000..9d674819876e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2021-2023 NXP + * + * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) + */ + +/dts-v1/; + +#include "s32g3.dtsi" + +/ { + model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)"; + compatible = "nxp,s32g399a-rdb3", "nxp,s32g3"; + + aliases { + mmc0 = &usdhc0; + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 4GiB RAM */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>, + <0x8 0x80000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc0 { + bus-width = <8>; + status = "okay"; +}; From 9198ffbd2b494daae3a67cac1d59c3a2754e64cd Mon Sep 17 00:00:00 2001 From: Chen Jun Date: Sat, 30 Mar 2024 16:23:35 +0800 Subject: [PATCH 164/969] mm/slub: Reduce memory consumption in extreme scenarios When kmalloc_node() is called without __GFP_THISNODE and the target node lacks sufficient memory, SLUB allocates a folio from a different node other than the requested node, instead of taking a partial slab from it. However, since the allocated folio does not belong to the requested node, on the following allocation it is deactivated and added to the partial slab list of the node it belongs to. This behavior can result in excessive memory usage when the requested node has insufficient memory, as SLUB will repeatedly allocate folios from other nodes without reusing the previously allocated ones. To prevent memory wastage, when a preferred node is indicated (not NUMA_NO_NODE) but without a prior __GFP_THISNODE constraint: 1) try to get a partial slab from target node only by having __GFP_THISNODE in pc.flags for get_partial() 2) if 1) failed, try to allocate a new slab from target node with GFP_NOWAIT | __GFP_THISNODE opportunistically. 3) if 2) failed, retry with original gfpflags which will allow get_partial() try partial lists of other nodes before potentially allocating new page from other nodes Without a preferred node, or with __GFP_THISNODE constraint, the behavior remains unchanged. On qemu with 4 numa nodes and each numa has 1G memory. Write a test ko to call kmalloc_node(196, GFP_KERNEL, 3) for (4 * 1024 + 4) * 1024 times. cat /proc/slabinfo shows: kmalloc-256 4200530 13519712 256 32 2 : tunables.. after this patch, cat /proc/slabinfo shows: kmalloc-256 4200558 4200768 256 32 2 : tunables.. Signed-off-by: Chen Jun Signed-off-by: Kefeng Wang Signed-off-by: Vlastimil Babka --- mm/slub.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/mm/slub.c b/mm/slub.c index d35d91877625..f152b5df8ab2 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -2699,7 +2699,7 @@ static struct slab *get_partial(struct kmem_cache *s, int node, searchnode = numa_mem_id(); slab = get_partial_node(s, get_node(s, searchnode), pc); - if (slab || node != NUMA_NO_NODE) + if (slab || (node != NUMA_NO_NODE && (pc->flags & __GFP_THISNODE))) return slab; return get_any_partial(s, pc); @@ -3375,6 +3375,7 @@ static void *___slab_alloc(struct kmem_cache *s, gfp_t gfpflags, int node, struct slab *slab; unsigned long flags; struct partial_context pc; + bool try_thisnode = true; stat(s, ALLOC_SLOWPATH); @@ -3501,6 +3502,21 @@ new_slab: new_objects: pc.flags = gfpflags; + /* + * When a preferred node is indicated but no __GFP_THISNODE + * + * 1) try to get a partial slab from target node only by having + * __GFP_THISNODE in pc.flags for get_partial() + * 2) if 1) failed, try to allocate a new slab from target node with + * GPF_NOWAIT | __GFP_THISNODE opportunistically + * 3) if 2) failed, retry with original gfpflags which will allow + * get_partial() try partial lists of other nodes before potentially + * allocating new page from other nodes + */ + if (unlikely(node != NUMA_NO_NODE && !(gfpflags & __GFP_THISNODE) + && try_thisnode)) + pc.flags = GFP_NOWAIT | __GFP_THISNODE; + pc.orig_size = orig_size; slab = get_partial(s, node, &pc); if (slab) { @@ -3522,10 +3538,15 @@ new_objects: } slub_put_cpu_ptr(s->cpu_slab); - slab = new_slab(s, gfpflags, node); + slab = new_slab(s, pc.flags, node); c = slub_get_cpu_ptr(s->cpu_slab); if (unlikely(!slab)) { + if (node != NUMA_NO_NODE && !(gfpflags & __GFP_THISNODE) + && try_thisnode) { + try_thisnode = false; + goto new_objects; + } slab_out_of_memory(s, gfpflags, node); return NULL; } From f7ae20f2fc4e6a5e32f43c4fa2acab3281a61c81 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 1 Apr 2024 13:41:59 -0400 Subject: [PATCH 165/969] docs: dma: correct dma_set_mask() sample code There are bunch of codes in driver like if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) Actually it is wrong because if dma_set_mask_and_coherent(64) fails, dma_set_mask_and_coherent(32) will fail for the same reason. And dma_set_mask_and_coherent(64) never returns failure. According to the definition of dma_set_mask(), it indicates the width of address that device DMA can access. If it can access 64-bit address, it must access 32-bit address inherently. So only need set biggest address width. See below code fragment: dma_set_mask(mask) { mask = (dma_addr_t)mask; if (!dev->dma_mask || !dma_supported(dev, mask)) return -EIO; arch_dma_set_mask(dev, mask); *dev->dma_mask = mask; return 0; } dma_supported() will call dma_direct_supported or iommux's dma_supported call back function. int dma_direct_supported(struct device *dev, u64 mask) { u64 min_mask = (max_pfn - 1) << PAGE_SHIFT; /* * Because 32-bit DMA masks are so common we expect every architecture * to be able to satisfy them - either by not supporting more physical * memory, or by providing a ZONE_DMA32. If neither is the case, the * architecture needs to use an IOMMU instead of the direct mapping. */ if (mask >= DMA_BIT_MASK(32)) return 1; ... } The iommux's dma_supported() actually means iommu requires devices's minimized dma capability. An example: static int sba_dma_supported( struct device *dev, u64 mask)() { ... * check if mask is >= than the current max IO Virt Address * The max IO Virt address will *always* < 30 bits. */ return((int)(mask >= (ioc->ibase - 1 + (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); ... } 1 means supported. 0 means unsupported. Correct document to make it more clear and provide correct sample code. Signed-off-by: Frank Li Reviewed-by: Christoph Hellwig Signed-off-by: Jonathan Corbet [jc: fixed then/than typo] Link: https://lore.kernel.org/r/20240401174159.642998-1-Frank.Li@nxp.com --- Documentation/core-api/dma-api-howto.rst | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/core-api/dma-api-howto.rst b/Documentation/core-api/dma-api-howto.rst index e8a55f9d61db..0bf31b6c4383 100644 --- a/Documentation/core-api/dma-api-howto.rst +++ b/Documentation/core-api/dma-api-howto.rst @@ -203,13 +203,33 @@ setting the DMA mask fails. In this manner, if a user of your driver reports that performance is bad or that the device is not even detected, you can ask them for the kernel messages to find out exactly why. -The standard 64-bit addressing device would do something like this:: +The 24-bit addressing device would do something like this:: - if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) { + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(24))) { dev_warn(dev, "mydev: No suitable DMA available\n"); goto ignore_this_device; } +The standard 64-bit addressing device would do something like this:: + + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) + +dma_set_mask_and_coherent() never return fail when DMA_BIT_MASK(64). Typical +error code like:: + + /* Wrong code */ + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) + +dma_set_mask_and_coherent() will never return failure when bigger than 32. +So typical code like:: + + /* Recommended code */ + if (support_64bit) + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); + else + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); + If the device only supports 32-bit addressing for descriptors in the coherent allocations, but supports full 64-bits for streaming mappings it would look like this:: From 058f1923ae32710ddefb4b37c0b053f83b52d175 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 29 Mar 2024 13:35:29 +0100 Subject: [PATCH 166/969] docs/zh: Fix Cc, Co-developed-by, and Signed-off-by tags The updates from commit ae67ee6c5e1d5b6a ("docs: fix Co-Developed-by docs") in v5.0 were never applied to the Chinese translations. In addition: - "Cc" used wrong case, - "Co-developed-by" lacked a dash, - "Signed-off-by" was misspelled. Signed-off-by: Geert Uytterhoeven Reviewed-by: Hu Haowen <2023002089@link.tyut.edu.cn> Reviewed-by: Alex Shi Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/22892a8ab5c17d7121ef5b85f7d18d8b1f41e434.1711715655.git.geert+renesas@glider.be --- .../translations/zh_CN/process/submitting-patches.rst | 8 ++++---- .../translations/zh_TW/process/submitting-patches.rst | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/translations/zh_CN/process/submitting-patches.rst b/Documentation/translations/zh_CN/process/submitting-patches.rst index f8978f02057c..7864107e60a8 100644 --- a/Documentation/translations/zh_CN/process/submitting-patches.rst +++ b/Documentation/translations/zh_CN/process/submitting-patches.rst @@ -333,10 +333,10 @@ Linus 和其他的内核开发者需要阅读和评论你提交的改动。对 未参与其开发。签署链应当反映补丁传播到维护者并最终传播到Linus所经过的 **真实** 路径，首个签署指明单个作者的主要作者身份。 -何时使用Acked-by:，CC:，和Co-Developed by: +何时使用Acked-by:，Cc:，和Co-developed-by: ------------------------------------------ -Singed-off-by: 标签表示签名者参与了补丁的开发，或者他/她在补丁的传递路径中。 +Signed-off-by: 标签表示签名者参与了补丁的开发，或者他/她在补丁的传递路径中。 如果一个人没有直接参与补丁的准备或处理，但希望表示并记录他们对补丁的批准/赞成， 那么他们可以要求在补丁的变更日志中添加一个Acked-by:。 @@ -358,8 +358,8 @@ Acked-by：不一定表示对整个补丁的确认。例如，如果一个补丁 Co-developed-by: 声明补丁是由多个开发人员共同创建的；当几个人在一个补丁上工 作时，它用于给出共同作者（除了From:所给出的作者之外）。因为Co-developed-by: 表示作者身份，所以每个Co-developed-by:必须紧跟在相关合作作者的签署之后。标准 -签署程序要求Singed-off-by:标签的顺序应尽可能反映补丁的时间历史，无论作者是通 -过From:还是Co-developed-by:表明。值得注意的是，最后一个Singed-off-by:必须是 +签署程序要求Signed-off-by:标签的顺序应尽可能反映补丁的时间历史，无论作者是通 +过From:还是Co-developed-by:表明。值得注意的是，最后一个Signed-off-by:必须是 提交补丁的开发人员。 注意，如果From:作者也是电子邮件标题的From:行中列出的人，则From:标签是可选的。 diff --git a/Documentation/translations/zh_TW/process/submitting-patches.rst b/Documentation/translations/zh_TW/process/submitting-patches.rst index 99fa0f2fe6f4..f12f2f193f85 100644 --- a/Documentation/translations/zh_TW/process/submitting-patches.rst +++ b/Documentation/translations/zh_TW/process/submitting-patches.rst @@ -334,10 +334,10 @@ Linus 和其他的內核開發者需要閱讀和評論你提交的改動。對 未參與其開發。簽署鏈應當反映補丁傳播到維護者並最終傳播到Linus所經過的 **真實** 路徑，首個簽署指明單個作者的主要作者身份。 -何時使用Acked-by:，CC:，和Co-Developed by: +何時使用Acked-by:，Cc:，和Co-developed-by: ------------------------------------------ -Singed-off-by: 標籤表示簽名者參與了補丁的開發，或者他/她在補丁的傳遞路徑中。 +Signed-off-by: 標籤表示簽名者參與了補丁的開發，或者他/她在補丁的傳遞路徑中。 如果一個人沒有直接參與補丁的準備或處理，但希望表示並記錄他們對補丁的批准/贊成， 那麼他們可以要求在補丁的變更日誌中添加一個Acked-by:。 @@ -359,8 +359,8 @@ Acked-by：不一定表示對整個補丁的確認。例如，如果一個補丁 Co-developed-by: 聲明補丁是由多個開發人員共同創建的；當幾個人在一個補丁上工 作時，它用於給出共同作者（除了From:所給出的作者之外）。因爲Co-developed-by: 表示作者身份，所以每個Co-developed-by:必須緊跟在相關合作作者的簽署之後。標準 -簽署程序要求Singed-off-by:標籤的順序應儘可能反映補丁的時間歷史，無論作者是通 -過From:還是Co-developed-by:表明。值得注意的是，最後一個Singed-off-by:必須是 +簽署程序要求Signed-off-by:標籤的順序應儘可能反映補丁的時間歷史，無論作者是通 +過From:還是Co-developed-by:表明。值得注意的是，最後一個Signed-off-by:必須是 提交補丁的開發人員。 注意，如果From:作者也是電子郵件標題的From:行中列出的人，則From:標籤是可選的。 From 886f6cac31cb2072ee79fe3009b7a89cea960ac7 Mon Sep 17 00:00:00 2001 From: Li Hua Date: Tue, 26 Mar 2024 18:45:15 +0800 Subject: [PATCH 167/969] scripts/sphinx-pre-install: fix Arch xelatex dependency On Arch Linux, xelatex is installed in the texlive-xetex package. Signed-off-by: Li Hua Link: https://lore.kernel.org/r/20240326104515.40346-1-lihua@email.com Signed-off-by: Jonathan Corbet --- scripts/sphinx-pre-install | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/sphinx-pre-install b/scripts/sphinx-pre-install index 4c781617ffe6..c559e43b2230 100755 --- a/scripts/sphinx-pre-install +++ b/scripts/sphinx-pre-install @@ -560,7 +560,7 @@ sub give_arch_linux_hints() "virtualenv" => "python-virtualenv", "dot" => "graphviz", "convert" => "imagemagick", - "xelatex" => "texlive-bin", + "xelatex" => "texlive-xetex", "latexmk" => "texlive-core", "rsvg-convert" => "extra/librsvg", ); From 1cbd16e3c125f34bef481ea048ec59bf24f1cbf4 Mon Sep 17 00:00:00 2001 From: Thorsten Blum Date: Sat, 23 Mar 2024 13:58:38 +0100 Subject: [PATCH 168/969] scripts: sphinx-pre-install: Add pyyaml hint to other distros Extend commit 84b4cc8189f2 ("docs: scripts: sphinx-pre-install: Fix building docs with pyyaml package") and add pyyaml as an optional package to Mageia, ArchLinux, and Gentoo. The Python module pyyaml is required to build the docs, but it is only listed in Documentation/sphinx/requirements.txt and is therefore missing when Sphinx is installed as a package and not via pip/pypi. Signed-off-by: Thorsten Blum Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240323125837.2022-2-thorsten.blum@toblux.com --- scripts/sphinx-pre-install | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/sphinx-pre-install b/scripts/sphinx-pre-install index c559e43b2230..c1121f098542 100755 --- a/scripts/sphinx-pre-install +++ b/scripts/sphinx-pre-install @@ -514,6 +514,7 @@ sub give_mageia_hints() { my %map = ( "python-sphinx" => "python3-sphinx", + "yaml" => "python3-yaml", "virtualenv" => "python3-virtualenv", "dot" => "graphviz", "convert" => "ImageMagick", @@ -557,6 +558,7 @@ sub give_mageia_hints() sub give_arch_linux_hints() { my %map = ( + "yaml" => "python-yaml", "virtualenv" => "python-virtualenv", "dot" => "graphviz", "convert" => "imagemagick", @@ -587,6 +589,7 @@ sub give_arch_linux_hints() sub give_gentoo_hints() { my %map = ( + "yaml" => "dev-python/pyyaml", "virtualenv" => "dev-python/virtualenv", "dot" => "media-gfx/graphviz", "convert" => "media-gfx/imagemagick", From 23bfb947eb0ae29aaf2882b19208f5af6033a429 Mon Sep 17 00:00:00 2001 From: Maki Hatano Date: Sat, 23 Mar 2024 14:21:12 +0800 Subject: [PATCH 169/969] doc: fix spelling about ReStructured Text - ReStructured Text should be exactly reStructuredText - "reStructuredText" is ONE word, not two! according to https://docutils.sourceforge.io/rst.html Signed-off-by: Maki Hatano Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240323062141.14863-1-Maki.Y.Hatano@gmail.com --- Documentation/doc-guide/parse-headers.rst | 2 +- Documentation/index.rst | 2 +- Documentation/translations/it_IT/index.rst | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/doc-guide/parse-headers.rst b/Documentation/doc-guide/parse-headers.rst index 5da0046f7059..204b025f1349 100644 --- a/Documentation/doc-guide/parse-headers.rst +++ b/Documentation/doc-guide/parse-headers.rst @@ -61,7 +61,7 @@ DESCRIPTION *********** -Convert a C header or source file (C_FILE), into a ReStructured Text +Convert a C header or source file (C_FILE), into a reStructuredText included via ..parsed-literal block with cross-references for the documentation files that describe the API. It accepts an optional EXCEPTIONS_FILE with describes what elements will be either ignored or diff --git a/Documentation/index.rst b/Documentation/index.rst index 5298611e00ee..f9f525f4c0dd 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -107,7 +107,7 @@ Other documentation There are several unsorted documents that don't seem to fit on other parts of the documentation body, or may require some adjustments and/or conversion -to ReStructured Text format, or are simply too old. +to reStructuredText format, or are simply too old. .. toctree:: :maxdepth: 1 diff --git a/Documentation/translations/it_IT/index.rst b/Documentation/translations/it_IT/index.rst index 70ccd23b2cde..9220f65e30d1 100644 --- a/Documentation/translations/it_IT/index.rst +++ b/Documentation/translations/it_IT/index.rst @@ -132,4 +132,4 @@ Documentazione varia Ci sono documenti che sono difficili da inserire nell'attuale organizzazione della documentazione; altri hanno bisogno di essere migliorati e/o convertiti -nel formato *ReStructured Text*; altri sono semplicamente troppo vecchi. +nel formato *reStructuredText*; altri sono semplicamente troppo vecchi. From 7a225ece7165496a91261001a0a2f3626f2766b9 Mon Sep 17 00:00:00 2001 From: Sarat Mandava Date: Thu, 21 Mar 2024 16:57:57 +0530 Subject: [PATCH 170/969] trace doc: Minor grammatical correction Use the correct relative pronoun. Signed-off-by: Sarat Mandava Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240321112757.17502-1-mandavasarat@gmail.com --- Documentation/trace/tracepoints.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/trace/tracepoints.rst b/Documentation/trace/tracepoints.rst index 0cb8d9ca3d60..decabcc77b56 100644 --- a/Documentation/trace/tracepoints.rst +++ b/Documentation/trace/tracepoints.rst @@ -27,7 +27,7 @@ the tracepoint site). You can put tracepoints at important locations in the code. They are lightweight hooks that can pass an arbitrary number of parameters, -which prototypes are described in a tracepoint declaration placed in a +whose prototypes are described in a tracepoint declaration placed in a header file. They can be used for tracing and performance accounting. From df60ab3d34384caa3ee88295d212bcd71a241684 Mon Sep 17 00:00:00 2001 From: Avadhut Naik Date: Tue, 5 Mar 2024 16:18:36 -0600 Subject: [PATCH 171/969] docs/sp_SP: Update process/submitting-patches Commit 329ac9af902e (docs: submitting-patches: Discuss interleaved replies) updates the original Documentation/process/submitting-patches.rst file. Translate and add the updates to its corresponding version in Spanish. Signed-off-by: Avadhut Naik Reviewed-by: Carlos Bilbao Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240305221839.2764380-2-avadhut.naik@amd.com --- .../sp_SP/process/submitting-patches.rst | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/translations/sp_SP/process/submitting-patches.rst b/Documentation/translations/sp_SP/process/submitting-patches.rst index c2757d9ab216..3b35566db736 100644 --- a/Documentation/translations/sp_SP/process/submitting-patches.rst +++ b/Documentation/translations/sp_SP/process/submitting-patches.rst @@ -356,6 +356,34 @@ Consulte Documentation/process/email-clients.rst para obtener recomendaciones sobre clientes de correo electrónico y normas de etiqueta en la lista de correo. +.. _sp_interleaved_replies: + +Uso de respuestas intercaladas recortadas en las discusiones por correo electrónico +----------------------------------------------------------------------------------- + +Se desaconseja encarecidamente la publicación en la parte superior de las +discusiones sobre el desarrollo del kernel de Linux. Las respuestas +intercaladas (o "en línea") hacen que las conversaciones sean mucho más +fáciles de seguir. Para obtener más detalles, consulte: +https://en.wikipedia.org/wiki/Posting_style#Interleaved_style + +Como se cita frecuentemente en la lista de correo:: + + A: http://en.wikipedia.org/wiki/Top_post + Q: ¿Dónde puedo encontrar información sobre esto que se llama top-posting? + A: Porque desordena el orden en el que la gente normalmente lee el texto. + Q: ¿Por qué es tan malo el top-posting? + A: Top-posting. + Q: ¿Qué es lo más molesto del correo electrónico? + +Del mismo modo, por favor, recorte todas las citas innecesarias que no +sean relevantes para su respuesta. Esto hace que las respuestas sean más +fáciles de encontrar y ahorra tiempo y espacio. Para obtener más +información, consulte: http://daringfireball.net/2007/07/on_top :: + + A: No. + Q: ¿Debo incluir citas después de mi respuesta? + .. _sp_resend_reminders: No se desanime o impaciente From 4ab16eb6f25988788c6d573298caede56889336b Mon Sep 17 00:00:00 2001 From: Avadhut Naik Date: Tue, 5 Mar 2024 16:18:37 -0600 Subject: [PATCH 172/969] docs/sp_SP: Add translation of process/development-process.rst Translate Documentation/process/development-process.rst into Spanish Signed-off-by: Avadhut Naik Reviewed-by: Carlos Bilbao Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240305221839.2764380-3-avadhut.naik@amd.com --- .../sp_SP/process/development-process.rst | 24 +++++++++++++++++++ .../translations/sp_SP/process/index.rst | 1 + 2 files changed, 25 insertions(+) create mode 100644 Documentation/translations/sp_SP/process/development-process.rst diff --git a/Documentation/translations/sp_SP/process/development-process.rst b/Documentation/translations/sp_SP/process/development-process.rst new file mode 100644 index 000000000000..41616249aa9e --- /dev/null +++ b/Documentation/translations/sp_SP/process/development-process.rst @@ -0,0 +1,24 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/development-process.rst +:Translator: Avadhut Naik + +.. _sp_development_process_main: + +Guía del proceso de desarrollo del kernel +========================================= + +El propósito de este documento es ayudar a los desarrolladores (y sus +gerentes) a trabajar con la comunidad de desarrollo con un mínimo de +frustración. Es un intento de documentar cómo funciona esta comunidad +de una manera accesible para aquellos que no están familiarizados +íntimamente con el desarrollo del kernel de Linux (o, de hecho, el +desarrollo de software libre en general). Si bien hay algo de material +técnico aquí, este es en gran medida una discusión orientada al proceso +que no requiere un conocimiento profundo de la programación del kernel +para entenderla. + +.. toctree:: + :caption: Contenido + :numbered: + :maxdepth: 2 diff --git a/Documentation/translations/sp_SP/process/index.rst b/Documentation/translations/sp_SP/process/index.rst index 2239373b3999..4892159310ff 100644 --- a/Documentation/translations/sp_SP/process/index.rst +++ b/Documentation/translations/sp_SP/process/index.rst @@ -28,3 +28,4 @@ management-style submit-checklist howto + development-process From 169e54c2d705f5865a94d151e32de0326fdd5894 Mon Sep 17 00:00:00 2001 From: Avadhut Naik Date: Tue, 5 Mar 2024 16:18:38 -0600 Subject: [PATCH 173/969] docs/sp_SP: Add translation of process/1.Intro.rst Translate Documentation/process/1.Intro.rst into Spanish In order to avoid broken links in the translated document, empty files have been created for documents which have not yet been translated. Signed-off-by: Avadhut Naik Reviewed-by: Carlos Bilbao Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240305221839.2764380-4-avadhut.naik@amd.com --- .../translations/sp_SP/process/1.Intro.rst | 302 ++++++++++++++++++ .../translations/sp_SP/process/2.Process.rst | 11 + .../sp_SP/process/3.Early-stage.rst | 11 + .../translations/sp_SP/process/4.Coding.rst | 11 + .../translations/sp_SP/process/5.Posting.rst | 11 + .../sp_SP/process/6.Followthrough.rst | 11 + .../sp_SP/process/7.AdvancedTopics.rst | 11 + .../sp_SP/process/8.Conclusion.rst | 11 + .../sp_SP/process/development-process.rst | 2 + 9 files changed, 381 insertions(+) create mode 100644 Documentation/translations/sp_SP/process/1.Intro.rst create mode 100644 Documentation/translations/sp_SP/process/2.Process.rst create mode 100644 Documentation/translations/sp_SP/process/3.Early-stage.rst create mode 100644 Documentation/translations/sp_SP/process/4.Coding.rst create mode 100644 Documentation/translations/sp_SP/process/5.Posting.rst create mode 100644 Documentation/translations/sp_SP/process/6.Followthrough.rst create mode 100644 Documentation/translations/sp_SP/process/7.AdvancedTopics.rst create mode 100644 Documentation/translations/sp_SP/process/8.Conclusion.rst diff --git a/Documentation/translations/sp_SP/process/1.Intro.rst b/Documentation/translations/sp_SP/process/1.Intro.rst new file mode 100644 index 000000000000..9b92b6c85221 --- /dev/null +++ b/Documentation/translations/sp_SP/process/1.Intro.rst @@ -0,0 +1,302 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/1.Intro.rst +:Translator: Avadhut Naik + +.. _sp_development_process_intro: + +Introducción +============ + +Resumen ejecutivo +----------------- + +El resto de esta sección cubre el alcance del proceso de desarrollo del +kernel y los tipos de frustraciones que los desarrolladores y sus +empleadores pueden encontrar allí. Hay muchas razones por las que el +código del kernel debe fusionarse con el kernel oficial (“mainline”), +incluyendo la disponibilidad automática para los usuarios, el apoyo de la +comunidad en muchas formas, y la capacidad de influir en la dirección del +desarrollo del kernel. El código contribuido al kernel de Linux debe +estar disponible bajo una licencia compatible con GPL. + +:ref:`sp_development_process` introduce el proceso de desarrollo, el ciclo +de lanzamiento del kernel y la mecánica de la "ventana de combinación" +(merge window). Se cubren las distintas fases en el desarrollo del parche, +la revisión y, el ciclo de fusión. Hay algunas discusiones sobre +herramientas y listas de correo. Se anima a los desarrolladores que deseen +comenzar con el desarrollo del kernel a encontrar y corregir errores como +ejercicio inicial. + +:ref:`sp_development_early_stage` cubre la planificación de proyectos en +etapas tempranas, con énfasis en involucrar a la comunidad de desarrollo +lo antes posible. + +:ref:`sp_development_coding` trata sobre el proceso de codificación. Se +discuten varios escollos encontrados por otros desarrolladores. Se cubren +algunos requisitos para los parches, y hay una introducción a algunas de +las herramientas que pueden ayudar a garantizar que los parches del kernel +sean correctos. + +:ref:`sp_development_posting` trata sobre el proceso de enviar parches para +su revisión. Para ser tomados en serio por la comunidad de desarrollo, +los parches deben estar correctamente formateados y descritos, y deben +enviarse al lugar correcto. Seguir los consejos de esta sección debería +ayudar a garantizar la mejor recepción posible para su trabajo. + +:ref:`sp_development_followthrough` cubre lo que sucede después de publicar +parches; el trabajo está lejos de terminar en ese momento. Trabajar con +revisores es una parte crucial del proceso de desarrollo; esta sección +ofrece varios consejos sobre cómo evitar problemas en esta importante +etapa. Se advierte a los desarrolladores que no asuman que el trabajo está +terminado cuando un parche se fusiona en mainline. + +:ref:`sp_development_advancedtopics` introduce un par de temas “avanzados”: +la administración de parches con git y la revisión de parches publicados +por otros. + +:ref:`sp_development_conclusion` concluye el documento con punteros a las +fuentes para obtener más información sobre el desarrollo del kernel. + +De qué trata este documento +--------------------------- + +El kernel de Linux, con más de 8 millones de líneas de código y más de +1000 colaboradores en cada versión, en uno de los proyectos de software +libre más grandes y activos que existen. Desde sus humildes comienzos en +1991, este kernel ha evolucionado hasta convertirse en el mejor componente +del sistema operativo que se ejecuta en reproductores de música digital +de bolsillo, PC de escritorio, las supercomputadoras más grandes que +existen y todo tipo de sistemas intermedios. Es una solución robusta, +eficiente, y escalable para casi cualquier situación. + +Con el crecimiento de Linux, ha llegado un aumento en el número de +desarrolladores (y empresas) que desean participar en su desarrollo. Los +vendedores de hardware quieren asegurarse de que Linux sea compatible con +sus productos, lo que hace que esos productos sean atractivos para los +usuarios de Linux. Los vendedores de sistemas embebidos, que utilizan +Linux como componente de un producto integrado, quieren que Linux sea lo +más capaz y adecuado posible para tarea en cuestión. Los distribuidores +y otros vendedores de software que basan sus productos en Linux tienen un +claro interés en las capacidades, el rendimiento, y la fiabilidad del +kernel de Linux. Y los usuarios finales, también, a menudo desearán +cambiar Linux para que se adapte mejor a sus necesidades. + +Una de las características más convincentes de Linux es que es accesible +a estos desarrolladores; cualquier persona con las habilidades necesarias +puede mejorar Linux e influir en la dirección de su desarrollo. Los +productos propietarios no pueden ofrecer este tipo de apertura, que es una +característica del proceso de software libre. Pero, en todo caso, el +kernel es aún más libre que la mayoría de los otros proyectos de software +libre. Un ciclo típico de desarrollo de kernel de tres meses puede +involucrar a más de 1000 desarrolladores que trabajan para más de 100 +empresas diferentes (o sin pertenecer a ninguna empresa). + +Trabajar con la comunidad de desarrollo del kernel no es especialmente +difícil. Pero, a pesar de eso, muchos colaboradores potenciales han +experimentado dificultades al tratar de hacer el trabajo del kernel. La +comunidad del kernel ha desarrollado sus propias formas distintivas de +operar, lo que le permite funcionar de manera fluida (y producir un +producto de alta calidad) en un entorno donde miles de líneas de código +se cambian todos los días. Por lo tanto, no es sorprendente que el +proceso de desarrollo del kernel de Linux difiera mucho de los métodos de +desarrollo propietarios. + +El proceso de desarrollo del kernel puede parecer extraño e intimidante +para los nuevos desarrolladores, pero hay buenas razones y una sólida +experiencia detrás de él. Un desarrollador que no entienda las formas de +la comunidad del kernel (o, peor aún, que intente burlarse o eludirlas) +tendrá una experiencia frustrante por delante. La comunidad de +desarrollo, si bien es servicial para aquellos que están tratando de +aprender, tiene poco tiempo para aquellos que no escuchan o que no se +preocupan por el proceso de desarrollo. + +Se espera que quienes lean este documento puedan evitar esa experiencia +frustrante. Hay mucho material aquí, pero el esfuerzo que implica leerlo +será recompensado en poco tiempo. La comunidad de desarrollo siempre +necesita desarrolladores que ayudan a mejorar el kernel; el siguiente +texto debería ayudarle – o a quienes trabajan para usted, a unirse a +nuestra comunidad. + +Créditos +-------- + +Este documento fue escrito por Jonathan Corbet, corbet@lwn.net. Ha sido +mejorado por los comentarios de Johannes Berg, James Berry, Alex Chiang, +Roland Dreier, Randy Dunlap, Jake Edge, Jiri Kosina, Matt Mackall, Arthur +Marsh, Amanda McPherson, Andrew Morton, Andrew Price, Tsugikazu Shibata y +Jochen Voß. +Este trabajo fue respaldado por la Fundación Linux; gracias especialmente +a Amanda McPherson, quien reconoció el valor de este esfuerzo e hizo que +todo sucediera. + +Importancia de integrar el código en el mainline +------------------------------------------------ + +Algunas empresas y desarrolladores ocasionalmente se preguntan por qué +deberían molestarse en aprender cómo trabajar con la comunidad del +kernel y obtener su código en el kernel mainline (el “mainline” es el +kernel mantenido por Linus Torvalds y utilizado como base por los +distribuidores de Linux. A corto plazo, contribuir con código puede +parecer un gasto evitable; parece más fácil mantener el código separado +y dar soporte a los usuarios directamente. La verdad del asunto es que +mantener el código separado (“fuera del árbol”) es pan para hoy y hambre +para mañana. + +Para ilustrar los costos del código fuera-del-árbol, aquí hay algunos +aspectos relevantes del proceso de desarrollo del kernel. La mayoría de +estos se discutirán con mayor detalle más adelante en este documento. +Considerar: + +- El código que se ha fusionado con el kernel mainline está disponible + para todos los usuarios de Linux. Estará presente automáticamente en + todas las distribuciones que lo habiliten. No hay necesidad de discos + de controladores, descargas, o las molestias de admitir múltiples + versiones de múltiples distribuciones; todo simplemente funciona, para + el desarrollador y para el usuario. La incorporación al mainline + resuelve un gran número de problemas de distribución y soporte. + +- Mientras los desarrolladores del kernel se esfuerzan por mantener una + interfaz estable para el espacio de usuario, la API interna de kernel + está en constante cambio. La falta de una interfaz interna estable es + una decisión deliberada de diseño; permite realizar mejoras + fundamentales en cualquier momento y da como resultado un código de + mayor calidad. Pero uno resultado de esa política es que cualquier + código fuera-del-árbol requiere un mantenimiento constante si va a + funcionar con los nuevos kernels. Mantener el código fuera-del-árbol + requiere una cantidad significativa de trabajo sólo para que ese código + siga funcionando. + + En su lugar, el código en el mainline no requiere este trabajo como + resultado de una regla simple que requiere que cualquier desarrollador + que realice un cambio en la API también corrija cualquier código que + se rompa como resultado de ese cambio. Así que, el código fusionado en + el mainline tiene costos de mantenimiento significativamente más bajos. + +- Más allá de eso, el código que está en el kernel a menudo será + mejorado por otros desarrolladores. Resultados sorprendentes pueden + provenir de capacitar a su comunidad de usuarios y clientes para mejorar + su producto. + +- El código del kernel se somete a revisión, tanto antes como después + de fusionarse con el mainline. No importa cuán fuertes sean las + habilidades del desarrollador original, este proceso de revisión + invariablemente encuentra formas en las que se puede mejorar el código. + A menudo la revisión encuentra errores graves y problemas de seguridad. + Esto es especialmente cierto para el código que se ha desarrollado en + un entorno cerrado; dicho código se beneficia fuertemente de la + revisión por desarrolladores externos. El código fuera-del-árbol es + de menor calidad. + +- La participación en el proceso de desarrollo es su manera de influir en + la dirección del desarrollo del kernel. Los usuarios que se quejan + desde el sofa son escuchados, pero los desarrolladores activos tienen + una voz más fuerte – y la capacidad de implementar cambios que hacen + que el kernel funcione mejor para sus necesidades. + +- Cuando el código se mantiene por separado, siempre existe la posibilidad + de que un tercero contribuya a una implementación diferente de una + característica similar. Si eso sucede, conseguir que su código + fusionado será mucho más difícil – hasta el punto de la imposibilidad. + Entonces se enfrentará a las desagradables alternativas de (1) mantener + una característica no estándar fuera del árbol indefinidamente, o + (2) abandonar su código y migrar sus usuarios a la versión en el árbol. + +- La contribución del código es la acción fundamental que hace que todo + el proceso funcione. Al contribuir con su código, puede agregar nuevas + funcionalidades al kernel y proporcionar capacidades y ejemplos que son + útiles para otros desarrolladores del kernel. Si ha desarrollado código + para Linux (o está pensando en hacerlo), claramente tiene un interés + en el éxito continuo de esta plataforma; contribuir con código es una + de las mejores maneras de ayudar a garantizar ese éxito. + +Todo el razonamiento anterior se aplica a cualquier código de kernel +fuera-del-árbol, incluido el código que se distribuye en forma propietaria +y únicamente en binario. Sin embargo, hay factores adicionales que deben +tenerse en cuenta antes de considerar cualquier tipo de distribución de +código de kernel únicamente en binario. Estos incluyen: + +- Las cuestiones legales en torno a la distribución de módulos + propietarios del kernel son, en el mejor de los casos, confusas; + bastantes titulares de derechos de autor del kernel creen que la + mayoría de los módulos binarios son productos derivados del kernel y + que, como resultado, su distribución es una violación de la licencia + Pública General de GNU (sobre la que se dirá más adelante). El autor + de este texto no es abogado, y nada en este documento puede considerarse + asesoramiento legal. Solo los tribunales pueden determinar el verdadero + estatus legal de los módulos de código cerrado. Pero la incertidumbre + que acecha a esos módulos está ahí a pesar de todo. + +- Los módulos binarios aumentan enormemente la dificultad de depurar + problemas del kernel, hasta el punto de que la mayoría de los + desarrolladores del kernel ni siquiera lo intentarán. Por lo tanto, + la distribución de módulos únicamente en binario hará que sea más + difícil para sus usuarios obtener soporte de la comunidad. + +- El soporte también es más difícil para los distribuidores de módulos + únicamente en binario, que deben proporcionar una versión del módulo + para cada distribución y cada versión del kernel que deseen apoyar. + Podría requerir docenas de compilaciones de un solo módulo para + proporcionar una cobertura razonablemente completa, y sus usuarios + tendrán que actualizar su módulo por separado cada vez que + actualicen su kernel. + +- Todo lo que se dijo anteriormente sobre la revisión de código se aplica + doblemente al código cerrado. Dado que este código no está disponible + en absoluto, no puede haber sido revisado por la comunidad y, sin duda, + tendrá serios problemas. + +Los fabricantes de sistemas embebidos, en particular, pueden verse +tentados a ignorar gran parte de lo que se ha dicho en esta sección +creyendo que están enviando un producto autónomo que utiliza una +versión de kernel congelada y no requiere más desarrollo después de su +lanzamiento. Este argumento desaprovecha el valor de la revisión +generalizad del código y el valor de permitir que sus usuarios agreguen +capacidades a su producto. Pero estos productos también tienen una vida +comercial limitada, después de la cual se debe lanzar una nueva versión. +En ese punto, los vendedores cuyo código esté en el mainline y bien +mantenido estarán en una posición mucho mejor para preparar el nuevo +producto rápidamente para el mercado. + +Licencias +--------- + +El código se contribuye al kernel de Linux bajo varias licencias, pero +todo el código debe ser compatible con la versión 2 de la Licencia +Pública General de GNU (GPLv2), que cubre la distribución del kernel. En +la práctica, esto significa que todas las contribuciones de código están +cubiertas ya sea por la GPLv2 (con, opcionalmente, un lenguaje que permite +la distribución en versiones posteriores de la GPL) o por la licencia BSD +de tres cláusulas. Cualquier contribución que no esté cubierta por una +licencia compatible no será aceptada en el kernel. + +No se requieren (ni se solicitan) cesiones de derechos de autor para el +código aportado al kernel. Todo el código fusionado en el kernel +mainline conserva su propiedad original; como resultado, el kernel ahora +tiene miles de propietarios. + +Una implicación de esta estructura de propiedad es que cualquier intento +de cambiar la licencia del kernel está condenado a un fracaso casi seguro. +Hay pocos escenarios prácticos en los que se pueda obtener el acuerdo de +todos los titulares de derechos de autor (o eliminar su código del +kernel). Así que, en particular, no hay perspectivas de una migración a +la versión 3 de la GPL en un futuro previsible. + +Es imperativo que todo el código aportado al kernel sea legítimamente +software libre. Por esa razón, no se aceptará código de colaboradores +anónimos (o seudónimos). Todos los colaboradores están obligados a +“firmar” su código, indicando que el código puede ser distribuido con +el kernel bajo la GPL. El código que no ha sido licenciado como software +libre por su propietario, o que corre el riesgo de crear problemas +relacionadas con los derechos de autor para el kernel (como el código que +se deriva de esfuerzos de ingeniería inversa que carecen de las garantías +adecuadas) no puede ser contribuido. + +Las preguntas sobre cuestiones relacionadas con los derechos de autor son +comunes en las listas de correo de desarrollo de Linux. Normalmente, estas +preguntas no recibirán escasez de respuestas, pero se debe tener en cuenta +que las personas que responden a esas preguntas no son abogados y no +pueden proporcionar consejo legal. Si tiene preguntas legales relacionadas +con el código fuente de Linux, no hay sustituto para hablar con un abogado +que entienda este campo. Confiar en las respuestas obtenidas en listas +técnicas de correo es un asunto arriesgado. diff --git a/Documentation/translations/sp_SP/process/2.Process.rst b/Documentation/translations/sp_SP/process/2.Process.rst new file mode 100644 index 000000000000..768c43dfd805 --- /dev/null +++ b/Documentation/translations/sp_SP/process/2.Process.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/2.Process.rst + +.. _sp_development_process: + +Cómo funciona el proceso de desarrollo +====================================== + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/3.Early-stage.rst b/Documentation/translations/sp_SP/process/3.Early-stage.rst new file mode 100644 index 000000000000..71cfb3fb0fda --- /dev/null +++ b/Documentation/translations/sp_SP/process/3.Early-stage.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/3.Early-stage.rst + +.. _sp_development_early_stage: + +Planificación en etapa inicial +============================== + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/4.Coding.rst b/Documentation/translations/sp_SP/process/4.Coding.rst new file mode 100644 index 000000000000..d9436e039b4b --- /dev/null +++ b/Documentation/translations/sp_SP/process/4.Coding.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/4.Coding.rst + +.. _sp_development_coding: + +Conseguir el código correcto +============================ + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/5.Posting.rst b/Documentation/translations/sp_SP/process/5.Posting.rst new file mode 100644 index 000000000000..50a3bc5998a8 --- /dev/null +++ b/Documentation/translations/sp_SP/process/5.Posting.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/5.Posting.rst + +.. _sp_development_posting: + +Publicar parches +================ + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/6.Followthrough.rst b/Documentation/translations/sp_SP/process/6.Followthrough.rst new file mode 100644 index 000000000000..f0acf9082bb3 --- /dev/null +++ b/Documentation/translations/sp_SP/process/6.Followthrough.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/6.Followthrough.rst + +.. _sp_development_followthrough: + +Seguimiento +=========== + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/7.AdvancedTopics.rst b/Documentation/translations/sp_SP/process/7.AdvancedTopics.rst new file mode 100644 index 000000000000..553759857339 --- /dev/null +++ b/Documentation/translations/sp_SP/process/7.AdvancedTopics.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/7.AdvancedTopics.rst + +.. _sp_development_advancedtopics: + +Temas avanzados +=============== + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/8.Conclusion.rst b/Documentation/translations/sp_SP/process/8.Conclusion.rst new file mode 100644 index 000000000000..dd181cb8ec9a --- /dev/null +++ b/Documentation/translations/sp_SP/process/8.Conclusion.rst @@ -0,0 +1,11 @@ +.. include:: ../disclaimer-sp.rst + +:Original: Documentation/process/8.Conclusion.rst + +.. _sp_development_conclusion: + +Para más información +==================== + +.. warning:: + TODO aún no traducido diff --git a/Documentation/translations/sp_SP/process/development-process.rst b/Documentation/translations/sp_SP/process/development-process.rst index 41616249aa9e..17fb168418ac 100644 --- a/Documentation/translations/sp_SP/process/development-process.rst +++ b/Documentation/translations/sp_SP/process/development-process.rst @@ -22,3 +22,5 @@ para entenderla. :caption: Contenido :numbered: :maxdepth: 2 + + 1.Intro From 3dfa8cd96e99f12b31124985f4f97b5ea817f808 Mon Sep 17 00:00:00 2001 From: Avadhut Naik Date: Tue, 5 Mar 2024 16:18:39 -0600 Subject: [PATCH 174/969] docs/sp_SP: Add translation of process/2.Process.rst Translate Documentation/process/2.Process.rst into Spanish Signed-off-by: Avadhut Naik Reviewed-by: Carlos Bilbao Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240305221839.2764380-5-avadhut.naik@amd.com --- .../translations/sp_SP/process/2.Process.rst | 535 +++++++++++++++++- .../sp_SP/process/development-process.rst | 1 + 2 files changed, 534 insertions(+), 2 deletions(-) diff --git a/Documentation/translations/sp_SP/process/2.Process.rst b/Documentation/translations/sp_SP/process/2.Process.rst index 768c43dfd805..5993eed71563 100644 --- a/Documentation/translations/sp_SP/process/2.Process.rst +++ b/Documentation/translations/sp_SP/process/2.Process.rst @@ -1,11 +1,542 @@ .. include:: ../disclaimer-sp.rst :Original: Documentation/process/2.Process.rst +:Translator: Avadhut Naik .. _sp_development_process: Cómo funciona el proceso de desarrollo ====================================== -.. warning:: - TODO aún no traducido +El desarrollo del kernel de Linux a principios de la década de 1990 fue +un asunto relajado, con un número relativamente pequeño de usuarios y +desarrolladores involucrados. Con una base de usuarios en los millones y +alrededor de 2,000 desarrolladores involucrados durante un año, el kernel +ha tenido que adaptar varios procesos para mantener el desarrollo sin +problemas. Se requiere una comprensión solida de cómo funciona el proceso +para ser una parte efectiva del mismo. + +El panorama general +------------------- + +Los desarrolladores del kernel utilizan un proceso de lanzamiento basado +en el tiempo de manera flexible, con uno nuevo lanzamiento principal del +kernel ocurriendo cada dos o tres meses. El historial reciente de +lanzamientos se ve así: + + ====== ================== + 5.0 Marzo 3, 2019 + 5.1 Mayo 5, 2019 + 5.2 Julio 7, 2019 + 5.3 Septiembre 15, 2019 + 5.4 Noviembre 24, 2019 + 5.5 Enero 6, 2020 + ====== ================== + +Cada lanzamiento 5.x es un lanzamiento principal del kernel con nuevas +características, cambios internos en la API y más. Un lanzamiento típico +puede contener alrededor de 13,000 conjuntos de cambios incluyendo en +varias centenas de miles de líneas de código. 5.x es la vanguardia del +desarrollo del kernel de Linux; el kernel utiliza un modelo de desarrollo +continuo que está integrando continuamente cambios importantes. + +Se sigue una disciplina relativamente sencilla con respecto a la fusión +de parches para cada lanzamiento. Al comienzo de cada ciclo de desarrollo, +se dice que la "merge window" (ventana de fusión) está abierta. En ese +momento, el código que se considera lo suficientemente estable (y que es +aceptado por la comunidad de desarrollo) se fusiona en el kernel mainline. +La mayor parte de los cambios para un nuevo ciclo de desarrollo (y todos +los cambios principales) se fusionarán durante este tiempo, a un ritmo +cercano a los 1,000 cambios (“parches” o “conjuntos de cambios”) por +día. + +(Aparte, vale la pena señalar que los cambios integrados durante la +ventana de fusión no surgen de la nada; han sido recolectados, probados +y montados con anticipación. Como funciona ese proceso se describirá en +detalle más adelante). + +La ventana de fusión dura aproximadamente dos semanas. Al final de este +tiempo, Linux Torvalds declarará que la ventana está cerrada y publicará +el primero de los kernels “rc”. Para el kernel destinado a ser 5.6, por +ejemplo, el lanzamiento al final de la ventana de fusión se llamará +5.6-rc1. El lanzamiento -rc1 señala que el tiempo para fusionar nuevas +características ha pasado y que el tiempo para estabilizar el siguiente +kernel ha comenzado. + +Durante las próximas seis a diez semanas, solo los parches que solucionen +problemas deben enviarse al mainline. En ocasiones, se permitirá un cambio +más significativo, pero tales ocasiones son raras; los desarrolladores que +intentan fusionar nuevas características fuera de la ventana de fusión +suelen recibir una recepción poco amistosa. Como regla general, si se +pierde la ventana de fusión de una característica determinada, lo mejor +que puede hacer es esperar al siguiente ciclo de desarrollo. (Se hace una +excepción ocasional para los drivers de hardware que no se admitía +anteriormente; si no afectan a ningún código en árbol, no pueden causar +regresiones y debería ser seguro agregarlos en cualquier momento). + +A medida que las correcciones se abren paso en el mainline, la tasa de +parches se ralentizará con el tiempo. Linus lanza nuevos kernels -rc +aproximadamente una vez a la semana; una serie normal llegará a algún +punto entre -rc6 y -rc9 antes de que se considere que el kernel es +suficientemente estable y realice el lanzamiento final. En ese momento, +todo el proceso vuelve a empezar. + +Como ejemplo, así fue el ciclo de desarrollo de 5.4 (todas las fechas son +de 2019): + + ============== ======================================= + Septiembre 15 5.3 lanzamiento estable + Septiembre 30 5.4-rc1, la ventana de fusion se cierra + Octubre 6 5.4-rc2 + Octubre 13 5.4-rc3 + Octubre 20 5.4-rc4 + Octubre 27 5.4-rc5 + Noviembre 3 5.4-rc6 + Noviembre 10 5.4-rc7 + Noviembre 17 5.4-rc8 + Noviembre 24 5.4 lanzamiento estable + ============== ======================================= + +¿Cómo deciden los desarrolladores cuándo cerrar el ciclo de desarrollo +y crear el lanzamiento estable? La métrica más significativa utilizada +es la lista de regresiones de lanzamientos anteriores. Ningunos errores +son bienvenidos, pero aquellos que rompen sistemas que funcionaron en el +pasado se consideran especialmente graves. Por esta razón, los parches +que causan regresiones se ven con malos ojos y es bastante probable que +se reviertan durante el periodo de estabilización. + +El objetivo de los desarrolladores es corregir todas las regresiones +conocidas antes de que se realice el lanzamiento estable. En el mundo +real, este tipo de perfección es difícil de lograr; hay demasiados +variables en un proyecto de este tamaño. Llega un punto en el que +retrasar el lanzamiento final solo empeora el problema; la pila de cambios +que esperan la siguiente ventana de fusión crecerá, creando aún más +regresiones la próxima vez. Por lo tanto, la mayoría de los kernels 5.x +se lanzan con un punado de regresiones conocidas, aunque, con suerte, +ninguna de ellas es seria. + +Una vez que se realiza un lanzamiento estable, su mantenimiento continuo +se transfiere al “equipo estable”, actualmente encabezado por Greg +Kroah-Hartman. El equipo estable lanzará actualizaciones ocasionales al +lanzamiento estable utilizando el esquema de numeración 5.x.y. Para ser +considerado para un lanzamiento de actualización, un parche debe +(1) corregir un error significativo y (2) ya estar fusionado en el +mainline para el siguiente kernel de desarrollo. Por lo general, los +kernels recibirán actualizaciones estables durante un poco más de un +ciclo de desarrollo después de su lanzamiento inicial. Así, por ejemplo, +la historia del kernel 5.2 se veía así (todas las fechas en 2019): + + ============== =============================== + Julio 7 5.2 lanzamiento estable + Julio 14 5.2.1 + Julio 21 5.2.2 + Julio 26 5.2.3 + Julio 28 5.2.4 + Julio 31 5.2.5 + ... ... + Octubre 11 5.2.21 + ============== =============================== + +5.2.21 fue la última actualización estable del lanzamiento 5.2. + +Algunos kernels se designan como kernels “a largo plazo”; recibirán +soporte durante un periodo más largo. Consulte el siguiente enlace para +obtener la lista de versiones activas del kernel a largo plazos y sus +maintainers: + + https://www.kernel.org/category/releases.html + +La selección de un kernel para soporte a largo plazo es puramente una +cuestión de que un maintainer tenga la necesidad y el tiempo para +mantener ese lanzamiento. No hay planes conocidos para ofrecer soporte a +largo plazo para ningún lanzamiento especifico próximo. + +Ciclo de vida de un parche +-------------------------- + +Los parches no van directamente desde el teclado del desarrollador al +kernel mainline. Hay, en cambio, un proceso algo complicado (aunque algo +informal) diseñado para garantizar que cada parche sea revisado en cuanto +a calidad y que cada parche implemente un cambio que es deseable tener en +el mainline. Este proceso puede ocurrir rápidamente para correcciones +menores, o, en el caso de cambios grandes y controvertidos, continuar +durante años. Gran parte de la frustración de los desarrolladores proviene +de la falta de compresión de este proceso o de sus intentos de eludirlo. + +Con la esperanza de reducir esa frustración, este documento describirá +cómo un parche entra en el kernel. Lo que sigue a continuación es una +introducción que describe el proceso de una manera tanto idealizada. Un +tratamiento mucho más detallado vendrá en secciones posteriores. + +Las etapas por las que pasa un parche son, generalmente: + + - Diseño. Aquí es donde se establecen los requisitos reales para el + parche – y la forma en que se cumplirán esos requisitos. El trabajo + de diseño a menudo se realiza sin involucrar a la comunidad, pero es + mejor hacer este trabajo de manera abierta si es posible; puede ahorrar + mucho tiempo rediseñando las cosas más tarde. + + - Revisión inicial. Los parches se publican en la lista de correo + relevante y los desarrolladores en esa lista responden con cualquier + comentario que puedan tener. Este proceso debería revelar cualquier + problema importante con un parche si todo va bien. + + - Revisión más amplia. Cuando el parche se acerca a estar listo para su + inclusión en el mainline, debe ser aceptado por un maintainer del + subsistema relevante – aunque esta aceptación no es una garantía de + que el parche llegara hasta el mainline. El parche aparecerá en el + árbol de subsistemas del maintainer y en los árboles -next (descritos + a continuación). Cuando el proceso funciona, este paso conduce a una + revisión exhaustiva del parche y al descubrimiento de cualquier + problema resultante de la integración de este parche con el trabajo + realizado por otros. + + - Tenga en cuenta que la mayoría de los maintainers también tienen + trabajos diurnos, por lo que fusionar su parche no puede ser su máxima + prioridad. Si su parche está recibiendo comentarios sobre los cambios + que se necesitan, debería realizar esos cambios o justificar por qué + no deberían realizarse. Si su parche no tiene quejas de revisión, pero + no está siendo fusionado por el maintainer apropiado del subsistema o + del driver, debe ser persistente en la actualización del parche + al kernel actual para que se aplique limpiamente y seguir enviándolo + para su revisión y fusión. + + - Fusión en el mainline. Eventualmente, un parche exitoso se fusionará + en el repositorio mainline administrado por Linux Torvalds. Mas + comentarios y/o problemas pueden surgir en este momento; es importante + que el desarrollador responda a estos y solucione cualquier problema + que surja. + + - Lanzamiento estable. El número de usuarios potencialmente afectados por + el parche es ahora grande, por lo que, una vez más, pueden surgir + nuevos problemas. + + - Mantenimiento a largo plazo. Si bien un desarrollador puede olvidarse + del código después de fusionarlo, ese comportamiento tiende a dejar + una impresión negativa en la comunidad de desarrollo. Fusionar el + código elimina parte de la carga de mantenimiento; otros solucionarán + los problemas causados por los cambios en la API. Sin embargo, el + desarrollador original debe seguir asumiendo la responsabilidad del + código si quiere seguir siendo útil a largo plazo. + +Uno de los peores errores cometidos por los desarrolladores del kernel +(o sus empleadores) es tratar de reducir el proceso a un solo paso de +“fusión en el mainline”. Este enfoque conduce invariablemente a la +frustración de todos los involucrados. + +Cómo se integran los parches en el kernel +----------------------------------------- + +Hay exactamente una persona que puede fusionar parches en el repositorio +mainline del kernel: Linus Torvalds. Pero, por ejemplo, de los más de +9,500 parches que se incluyeron en el kernel 2.6.38, solo 112 (alrededor +del 1.3%) fueron elegidos directamente por Linus mismo. El proyecto del +kernel ha crecido mucho desde hace tiempo a un tamaño en el que ningún +desarrollador individual podría inspeccionar y seleccionar todos los +parches sin ayuda. La forma que los desarrolladores del kernel han +abordado este crecimiento es a través del uso de un sistema jerárquico +alrededor de una cadena de confianza. + +La base de código del kernel se descompone lógicamente en un conjunto de +subsistemas: redes, soporte de arquitectura especifica, gestión de +memoria, dispositivos de video, etc. La mayoría de los subsistemas tienen +un maintainer designado, un desarrollador que tiene la responsabilidad +general del código dentro de ese subsistema. Estos maintainers de +subsistemas son los guardianes (en cierto modo) de la parte del kernel que +gestionan; son los que (usualmente) aceptarán un parche para incluirlo en +el kernel mainline. + +Cada uno de los maintainers del subsistema administra su propia versión +del árbol de fuentes del kernel, generalmente (pero, ciertamente no +siempre) usando la herramienta de administración de código fuente de git. +Herramientas como git (y herramientas relacionadas como quilt o mercurial) +permiten a los maintainers realizar un seguimiento de una lista de +parches, incluida la información de autoría y otros metadatos. En +cualquier momento, el maintainer puede identificar qué parches de su +repositorio no se encuentran en el mainline. + +Cuando se abre la ventana de fusión, los maintainers de nivel superior +le pedirán a Linus que “extraiga” los parches que han seleccionado para +fusionar de sus repositorios. Si Linus está de acuerdo, el flujo de +parches fluirá hacia su repositorio, convirtiéndose en parte del kernel +mainline. La cantidad de atención que Linus presta a los parches +específicos recibidos en una operación de extracción varia. Está claro +que, a veces, examina bastante de cerca. Pero, como regla general, Linus +confía en que los maintainers del subsistema no envíen parches +defectuosos al upstream. + +Los maintainers de subsistemas, a su vez, pueden extraer parches de otros +maintainers. Por ejemplo, el árbol de red se construye a partir de +parches que se acumulan primero en arboles dedicados a drivers de +dispositivos de red, redes inalámbricas, etc. Esta cadena de repositorios +puede ser arbitrariamente larga, aunque rara vez supera los dos o tres +enlaces. Dado que cada maintainer de la cadena confía en los que +administran árboles de nivel inferior, este proceso se conoce como la +“cadena de confianza”. + +Claramente, en un sistema como este, lograr que los parches se integren +en el kernel depende de encontrar el maintainer adecuado. Enviar parches +directamente a Linus no es normalmente la forma correcta de hacerlo. + +Árboles siguientes (next) +------------------------- + +La cadena de árboles de subsistemas guía el flujo de parches en el +kernel, pero también plantea una pregunta interesante: ¿Qué pasa si +alguien quiere ver todos los parches que se están preparando para la +próxima ventana de fusión? Los desarrolladores estarán interesados en +saber que otros cambios están pendientes para ver si hay algún conflicto +del que preocuparse; un parche que cambia un prototipo de función del +núcleo del kernel, por ejemplo, entrará en conflicto con cualquier otro +parche que utilice la forma anterior de esa función. Los revisores y +probadores quieren tener acceso a los cambios en su forma integrada antes +de que todos esos cambios se integren en el kernel mainline. Uno podría +extraer cambios de todos los árboles de subsistemas interesantes, pero +eso sería un trabajo tedioso y propenso a errores. + +La respuesta viene en forma de árboles -next, donde los árboles de +subsistemas se recopilan para pruebas y revisiones. El más antiguo de +estos árboles, mantenido por Andrew Morton, se llama “-mm” (por gestión +de la memoria, que es como comenzó). El árbol “-mm” integra parches +de una larga lista de árboles de subsistemas; también tiene algunos +parches destinados a ayudar con la depuración. + +Más allá de eso, -mm contiene una colección significativa de parches +que han sido seleccionados directamente por Andrew. Estos parches pueden +haber sido publicados en una lista de correo o aplicarse a una parte del +kernel para la que no hay un árbol de subsistemas designado. Como +resultado, -mm funciona como una especie de árbol de subsistemas de +último recurso; si no hay otro camino obvio para un parche en el mainline, +es probable que termine en -mm. Los parches misceláneos que se acumulan +en -mm eventualmente se enviarán a un árbol de subsistema apropiado o se +enviarán directamente a Linus. En un ciclo de desarrollo típico, +aproximadamente el 5-10% de los parches que van al mainline llegan allí +a través de -mm. + +El parche -mm actual está disponible en el directorio “mmotm” (-mm +del momento) en: + + https://www.ozlabs.org/~akpm/mmotm/ + +Sin embargo, es probable que el uso del árbol MMOTM sea una experiencia +frustrante; existe una posibilidad definitiva de que ni siquiera se +compile. + +El árbol principal para la fusión de parches del siguiente ciclo es +linux-next, mantenido por Stephen Rothwell. El árbol linux-next es, por +diseño, una instantánea de cómo se espera que se vea el mainline después +de que se cierre la siguiente ventana de fusión. Los árboles linux-next +se anuncian en las listas de correo linux-kernel y linux-next cuando se +ensamblan; Se pueden descargar desde: + + https://www.kernel.org/pub/linux/kernel/next/ + +Linux-next se ha convertido en una parte integral del proceso de +desarrollo del kernel; todos los parches fusionados durante una ventana +de fusión determinada deberían haber encontrado su camino en linux-next +en algún momento antes de que se abra la ventana de fusión. + +Árboles de staging +------------------ + +El árbol de fuentes del kernel contiene el directorio drivers/staging/, +donde residen muchos subdirectorios para drivers o sistemas de archivos +que están en proceso de ser agregados al árbol del kernel. Permanecen +en drivers/staging mientras aún necesitan más trabajo; una vez +completados, se pueden mover al kernel propiamente dicho. Esta es una +forma de realizar un seguimiento de los drivers drivers que no están a la +altura de la codificación o los estándares de calidad del kernel de +Linux, pero que las personas pueden querer usarlos y realizar un +seguimiento del desarrollo. + +Greg Kroah-Hartman mantiene actualmente el árbol de staging. Los drivers +que aun necesitan trabajo se le envían, y cada driver tiene su propio +subdirectorio en drivers/staging/. Junto con los archivos de origen del +driver, también debe haber un archivo TODO en el directorio. El archivo +TODO enumera el trabajo pendiente que el driver necesita para ser aceptado +en el kernel propiamente dicho, así como una lista de personas a las que +Cc’d para cualquier parche para el driver. Las reglas actuales exigen +que los drivers que contribuyen a staging deben, como mínimo, compilarse +correctamente. + +El staging puede ser una forma relativamente fácil de conseguir nuevos +drivers en el mainline donde, con suerte, llamarán la atención de otros +desarrolladores y mejorarán rápidamente. Sin embargo, la entrada en el +staging no es el final de la historia; el código que no está viendo +progreso regular eventualmente será eliminado. Los distribuidores también +tienden a ser relativamente reacios a habilitar los drivers de staging. +Por lo tanto, el staging es, en el mejor de los casos, una parada en el +camino para hacia convertirse en un apropiado driver del mainline. + +Herramientas +------------ + +Como se puede ver en el texto anterior, el proceso de desarrollo del +kernel depende en gran medida de la capacidad de dirigir colecciones de +parches en varias direcciones. Todo ello no funcionaría tan bien como lo +hace sin herramientas apropiadamente potentes. Los tutoriales sobre cómo +usar estas herramientas están mucho más allá del alcance de este +documento, pero hay espacio para algunos consejos. + +Con mucho, el sistema de gestión de código fuente dominante utilizado +por la comunidad del kernel es git. Git es uno de los varios sistemas de +control de versiones distribuidos que se están desarrollando en la +comunidad de software libre. Está bien ajustado para el desarrollo de +kernel, ya que funciona bastante bien cuando se trata de grandes +repositorios y grandes cantidades de parches. También tiene la reputación +de ser difícil de aprender y usar, aunque ha mejorado con el tiempo. +Algún tipo de familiaridad con git es casi un requisito para los +desarrolladores del kernel; incluso si no lo usan para su propio +trabajo, necesitarán git para mantenerse al día con lo que otros +desarrolladores (y el mainline) están haciendo. + +Git ahora está empaquetado por casi todas las distribuciones de Linux. +Hay una página de inicio en: + + https://git-scm.com/ + +Esa página tiene punteros a documentación y tutoriales. + +Entre los desarrolladores de kernel que no usan git, la opción más +popular es casi con certeza Mercurial: + + https://www.selenic.com/mercurial/ + +Mercurial comparte muchas características con git, pero proporciona una +interfaz que muchos encuentran más fácil de usar. + +Otra herramienta que vale la pena conocer es Quilt: + + https://savannah.nongnu.org/projects/quilt/ + +Quilt es un sistema de gestión de parches, en lugar de un sistema de +gestión de código fuente. No rastrea el historial a lo largo del tiempo; +en cambio, está orientado al seguimiento de un conjunto especifico de +cambios en relación con una base de código en evolución. Algunos de los +principales maintainers de subsistemas utilizan Quilt para gestionar los +parches destinados a ir upstream. Para la gestión de ciertos tipos de +árboles (por ejemplo, -mm) Quilt es la mejor herramienta para el trabajo. + +Listas de correo +---------------- + +Una gran parte del trabajo de desarrollo del kernel de Linux se realiza a +través de listas de correo. Es difícil ser un miembro plenamente funcional +de la comunidad sin unirse al menos a una lista en algún parte. Pero las +listas de correo de Linux también representan un peligro potencial para +los desarrolladores, que corren el riesgo de quedar enterrados bajo una +carga de correo electrónico, incumplir las convenciones utilizadas en las +listas de Linux, o ambas cosas. + +La mayoría de las listas de correo del kernel se ejecutan en +vger.kernel.org; la lista principal se puede encontrar en: + + http://vger.kernel.org/vger-lists.html + +Sim embargo, hay listas alojadas en otros lugares; varios de ellos se +encuentran en redhat.com/mailman/listinfo. + +La lista de correo principal para el desarrollo del kernel es, por +supuesto, linux-kernel. Esta lista es un lugar intimidante; el volumen +puede alcanzar 500 mensajes por día, la cantidad de ruido es alta, la +conversación puede ser muy técnica y los participantes no siempre se +preocupan por mostrar un alto grado de cortesía. Pero no hay otro lugar +donde la comunidad de desarrollo del kernel se reúna como un todo; los +desarrolladores que eviten esta lista se perderán información importante. + +Hay algunos consejos que pueden ayudar a sobrevivir en el kernel de Linux: + +- Haga que la lista se entregue en una carpeta separada, en lugar de su + buzón principal. Uno debe ser capaz de ignorar el flujo durante + periodos prolongados. + +- No trate de seguir cada conversación, nadie lo hace. Es importante + filtrar tanto por el tema de interés (aunque tenga en cuenta que las + conversaciones prolongadas pueden alejarse del asunto original sin + cambiar la línea de asunto del correo electrónico) por las personas + que participan. + +- No alimente a los trolls. Si alguien está tratando de provocar una + respuesta de enojo, ignórelos. + +- Al responder al correo electrónico del kernel de Linux (o al de otras + listas) conserve el encabezado Cc: para todos los involucrados. En + ausencia de una razón solida (como una solicitud explícita), nunca debe + eliminar destinarios. Asegúrese siempre de que la persona a la que está + respondiendo esté en la lista Cc:. Esta convención también hace que no + sea necesario solicitar explícitamente que se le copie en las respuestas + a sus publicaciones. + +- Busque en los archivos de la lista (y en la red en su conjunto) antes + de hacer preguntas. Algunos desarrolladores pueden impacientarse con + las personas que claramente no han hecho sus deberes. + +- Utilice respuestas intercaladas (“en línea”), lo que hace que su + respuesta sea más fácil de leer. (Es decir, evite top-posting – la + práctica de poner su respuesta encima del texto citado al que está + respondiendo.) Para obtener más información, consulte + :ref:`Documentation/translations/sp_SP/process/submitting-patches.rst `. + +- Pregunte en la lista de correo correcta. linux-kernel puede ser el + punto de encuentro general, pero no es el mejor lugar para encontrar + desarrolladores de todos los subsistemas. + +El último punto, encontrar la lista de correo correcta, es una fuente +común de errores para desarrolladores principiantes. Alguien que haga +una pregunta relacionada con las redes en linux-kernel seguramente +recibirá una surgencia educada para preguntar en la lista de netdev en su +lugar, ya que esa es la lista frecuentada por la mayoría de los +desarrolladores de redes. Existen otras listas para los subsistemas SCSI, +video4linux, IDE, sistema de archivos, etc. El mejor lugar para buscar +listas de correo es en el archivo MAINTAINERS incluido con el código +fuente del kernel. + +Comenzar con el desarrollo del kernel +------------------------------------- + +Las preguntas sobre como comenzar con el proceso de desarrollo del kernel +son comunes, tanto de individuos como de empresas. Igualmente comunes son +los pasos en falso que hacen que el comienzo de la relación sea más +difícil de lo que tiene que ser. + +Las empresas a menudo buscan contratar desarrolladores conocidos para +iniciar un grupo de desarrollo. De hecho, esta puede ser una técnica +efectiva. Pero también tiende a ser caro y no hace mucho para crecer el +grupo de desarrolladores de kernel experimentados. Es posible poner al +día a los desarrolladores internos en el desarrollo de kernel de Linux, +dada la inversión de algún tiempo. Tomarse este tiempo puede dotar a un +empleador de un grupo de desarrolladores que comprendan tanto el kernel +como la empresa, y que también puedan ayudar a educar a otros. A medio +plazo, este es a menudo el enfoque más rentable. + +Los desarrolladores individuales, a menudo, comprensiblemente, no tienen +un lugar para empezar. Comenzar con un proyecto grande puede ser +intimidante; a menudo uno quiere probar las aguas con algo más pequeño +primero. Este es el punto en el que algunos desarrolladores se lanzan a +la creación de parches para corregir errores ortográficos o problemas +menores de estilo de codificación. Desafortunadamente, dicho parches +crean un nivel de ruido que distrae a la comunidad de desarrollo en su +conjunto, por lo que, cada vez más, se los mira con desprecio. Los nuevos +desarrolladores que deseen presentarse a la comunidad no recibirán la +recepción que desean por estos medios. + +Andrew Morton da este consejo (traducido) para los aspirantes a +desarrolladores de kernel. + +:: + + El proyecto #1 para los principiantes en el kernel seguramente debería + ser “asegúrese de que el kernel funcione perfectamente en todo momento + en todas las máquinas que pueda conseguir”. Por lo general, la forma + de hacer esto es trabajar con otros para arreglar las cosas (¡esto + puede requerir persistencia!), pero eso está bien, es parte del + desarrollo del kernel. + +(https://lwn.net/Articles/283982/) + +En ausencia de problemas obvios que solucionar, se aconseja a los +desarrolladores que consulten las listas actuales de regresiones y errores +abiertos en general. Nunca faltan problemas que necesitan solución; al +abordar estos problemas, los desarrolladores ganarán experiencia con el +proceso mientras, al mismo tiempo, se ganarán el respeto del resto de la +comunidad de desarrollo. diff --git a/Documentation/translations/sp_SP/process/development-process.rst b/Documentation/translations/sp_SP/process/development-process.rst index 17fb168418ac..40d74086f22e 100644 --- a/Documentation/translations/sp_SP/process/development-process.rst +++ b/Documentation/translations/sp_SP/process/development-process.rst @@ -24,3 +24,4 @@ para entenderla. :maxdepth: 2 1.Intro + 2.Process From 9e192b39a5992d8b730383d57416964b44ea1041 Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Sat, 2 Mar 2024 22:00:50 +0800 Subject: [PATCH 175/969] docs/zh_CN: Add dev-tools/ubsan Chinese translation Translate dev-tools/ubsan.rst into Chinese, add it into zh_CN/dev-tools/index.rst. Signed-off-by: Dongliang Mu Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240302140058.1527765-1-dzm91@hust.edu.cn --- .../translations/zh_CN/dev-tools/index.rst | 2 +- .../translations/zh_CN/dev-tools/ubsan.rst | 91 +++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 Documentation/translations/zh_CN/dev-tools/ubsan.rst diff --git a/Documentation/translations/zh_CN/dev-tools/index.rst b/Documentation/translations/zh_CN/dev-tools/index.rst index c2db3e566b1b..c4463f0750f0 100644 --- a/Documentation/translations/zh_CN/dev-tools/index.rst +++ b/Documentation/translations/zh_CN/dev-tools/index.rst @@ -22,13 +22,13 @@ Documentation/translations/zh_CN/dev-tools/testing-overview.rst sparse gcov kasan + ubsan gdb-kernel-debugging Todolist: - coccinelle - kcov - - ubsan - kmemleak - kcsan - kfence diff --git a/Documentation/translations/zh_CN/dev-tools/ubsan.rst b/Documentation/translations/zh_CN/dev-tools/ubsan.rst new file mode 100644 index 000000000000..2487696b3772 --- /dev/null +++ b/Documentation/translations/zh_CN/dev-tools/ubsan.rst @@ -0,0 +1,91 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../disclaimer-zh_CN.rst + +:Original: Documentation/dev-tools/ubsan.rst +:Translator: Dongliang Mu + +未定义行为消毒剂 - UBSAN +==================================== + +UBSAN是一种动态未定义行为检查工具。 + +UBSAN使用编译时插桩捕捉未定义行为。编译器在可能导致未定义行为的操作前插入特定 +检测代码。如果检查失败，即检测到未定义行为，__ubsan_handle_* 函数将被调用打印 +错误信息。 + +GCC自4.9.x [1_] （详见 ``-fsanitize=undefined`` 选项及其子选项）版本后引入这 +一特性。GCC 5.x 版本实现了更多检查器 [2_]。 + +报告样例 +-------------- + +:: + + ================================================================================ + UBSAN: Undefined behaviour in ../include/linux/bitops.h:110:33 + shift exponent 32 is to large for 32-bit type 'unsigned int' + CPU: 0 PID: 0 Comm: swapper Not tainted 4.4.0-rc1+ #26 + 0000000000000000 ffffffff82403cc8 ffffffff815e6cd6 0000000000000001 + ffffffff82403cf8 ffffffff82403ce0 ffffffff8163a5ed 0000000000000020 + ffffffff82403d78 ffffffff8163ac2b ffffffff815f0001 0000000000000002 + Call Trace: + [] dump_stack+0x45/0x5f + [] ubsan_epilogue+0xd/0x40 + [] __ubsan_handle_shift_out_of_bounds+0xeb/0x130 + [] ? radix_tree_gang_lookup_slot+0x51/0x150 + [] _mix_pool_bytes+0x1e6/0x480 + [] ? dmi_walk_early+0x48/0x5c + [] add_device_randomness+0x61/0x130 + [] ? dmi_save_one_device+0xaa/0xaa + [] dmi_walk_early+0x48/0x5c + [] dmi_scan_machine+0x278/0x4b4 + [] ? vprintk_default+0x1a/0x20 + [] ? early_idt_handler_array+0x120/0x120 + [] setup_arch+0x405/0xc2c + [] ? early_idt_handler_array+0x120/0x120 + [] start_kernel+0x83/0x49a + [] ? early_idt_handler_array+0x120/0x120 + [] x86_64_start_reservations+0x2a/0x2c + [] x86_64_start_kernel+0x16b/0x17a + ================================================================================ + +用法 +----- + +使用如下内核配置启用UBSAN:: + + CONFIG_UBSAN=y + +使用如下内核配置检查整个内核:: + + CONFIG_UBSAN_SANITIZE_ALL=y + +为了在特定文件或目录启动代码插桩，需要在相应的内核Makefile中添加一行类似内容: + +- 单文件（如main.o）:: + + UBSAN_SANITIZE_main.o := y + +- 一个目录中的所有文件:: + + UBSAN_SANITIZE := y + +即使设置了``CONFIG_UBSAN_SANITIZE_ALL=y``，为了避免文件被插桩，可使用:: + + UBSAN_SANITIZE_main.o := n + +与:: + + UBSAN_SANITIZE := n + +未对齐的内存访问检测可通过开启独立选项 - CONFIG_UBSAN_ALIGNMENT 检测。 +该选项在支持未对齐访问的架构上(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y) +默认为关闭。该选项仍可通过内核配置启用，但它将产生大量的UBSAN报告。 + +参考文献 +---------- + +.. _1: https://gcc.gnu.org/onlinedocs/gcc-4.9.0/gcc/Debugging-Options.html +.. _2: https://gcc.gnu.org/onlinedocs/gcc/Debugging-Options.html +.. _3: https://clang.llvm.org/docs/UndefinedBehaviorSanitizer.html From 7fb5680b589d5eae64ada1d917b6ff2dab82f5ae Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 05:57:16 +0300 Subject: [PATCH 176/969] arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells The property #stream-id-cells is legacy, it is not documented as valid for the GPU. Drop it now. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240402-fd-fix-schema-v3-2-817ea6ddf775@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 32afc78d5b76..99462b42cfc5 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2225,7 +2225,6 @@ gpu: gpu@2c00000 { compatible = "qcom,adreno-680.1", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; From 580701ec27f61e0996dd5fcd23b091b6bf6933e3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 05:57:17 +0300 Subject: [PATCH 177/969] arm64: dts: qcom: sc8180x: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240402-fd-fix-schema-v3-3-817ea6ddf775@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 99462b42cfc5..6d74867d3b61 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2804,7 +2804,7 @@ power-domains = <&rpmhpd SC8180X_MMCX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -2877,7 +2877,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -2963,7 +2963,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From 1106ea2266d11ebd97c3493a0c36a45272bfb67a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 05:57:18 +0300 Subject: [PATCH 178/969] arm64: dts: qcom: sc8180x: add dp_p1 register blocks to DP nodes DisplayPort nodes must declare the dp_p1 register space in addition to dp_p0. Add corresponding resource to DisplayPort DT nodes. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240402-fd-fix-schema-v3-4-817ea6ddf775@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 6d74867d3b61..019104bd70fb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3029,7 +3029,8 @@ reg = <0 0xae90000 0 0x200>, <0 0xae90200 0 0x200>, <0 0xae90400 0 0x600>, - <0 0xae90a00 0 0x400>; + <0 0xae90a00 0 0x400>, + <0 0xae91000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -3105,7 +3106,8 @@ reg = <0 0xae98000 0 0x200>, <0 0xae98200 0 0x200>, <0 0xae98400 0 0x600>, - <0 0xae98a00 0 0x400>; + <0 0xae98a00 0 0x400>, + <0 0xae99000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <13>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From e48919dc1ed568f895eca090dc6c5dc56b12480c Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 3 Dec 2023 00:47:18 +0100 Subject: [PATCH 179/969] ARM: dts: qcom: include cpu in idle-state node names Required for dt-schema validation. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20231202234832.155306-2-david@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 9a5ba978775a..c428a5c16c65 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -87,7 +87,7 @@ }; idle-states { - CPU_SPC: spc { + CPU_SPC: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <400>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 8204e64d9a97..ca53dff820ef 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -79,7 +79,7 @@ }; idle-states { - CPU_SPC: spc { + CPU_SPC: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <150>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 5efc38d712cc..233d9bf42298 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -85,7 +85,7 @@ }; idle-states { - CPU_SPC: spc { + CPU_SPC: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <150>; From 8f2cc88cd4a35e33931ca1375ea508c8c9267b57 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 3 Dec 2023 00:47:19 +0100 Subject: [PATCH 180/969] ARM: dts: qcom: msm8916: idle-state compatible require the generic idle-state compatible must be qcom,idle-state-spc AND arm,idle-state. Fixes: d468f825b3fd ("ARM: dts: qcom: msm8916: Add include for SMP without PSCI on ARM32") Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20231202234832.155306-3-david@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi index 36328dbe4212..1ba403b83cb1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8916-smp.dtsi @@ -26,7 +26,7 @@ }; &CPU_SLEEP_0 { - compatible = "qcom,idle-state-spc"; + compatible = "qcom,idle-state-spc", "arm,idle-state"; }; &cpu0_acc { From 328ad44c5290cc4575be5f0dc457c75bb71015d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 28 Mar 2024 10:37:10 +0100 Subject: [PATCH 181/969] arm64: dts: broadcom: bcmbca: bcm4908: set brcm,wp-not-connected MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Every described BCM4908 board has WP pin not connected. This caused problems for drivers since day 0 but there was no property to describe that properly. Projects like OpenWrt were modifying Linux driver to deal with it. It's not clear if that is hardware limitation or just reference design being copied over and over but this applies to all known / supported BCM4908 boards. Handle it by marking WP as not connected by default. Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files") Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240328093710.28206-1-zajec5@gmail.com Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 + arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index e01cf4f54077..8b924812322c 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -594,6 +594,7 @@ reg-names = "nand", "nand-int-base"; interrupts = ; interrupt-names = "nand_ctlrdy"; + brcm,wp-not-connected; status = "disabled"; nandcs: nand@0 { diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts index 030ffa5364fb..e5b37643296b 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts @@ -34,7 +34,6 @@ }; &nand_controller { - brcm,wp-not-connected; status = "okay"; }; From 8a1365c7bbc122bd843096f0008d259e7a8afc61 Mon Sep 17 00:00:00 2001 From: Carlos Song Date: Thu, 28 Mar 2024 14:14:19 +0800 Subject: [PATCH 182/969] arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery I2C bus recovery need a pinmux and gpio. So i2c driver can switch gpio mode to toggle scl to recovery bus. Add pinctrl-single node to every i2c bus on fsl-ls2160 layerscape platform. Signed-off-by: Carlos Song Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++++- 1 file changed, 106 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index e665c629e1a1..96055593204a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -748,7 +748,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; - scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_scl>; + pinctrl-1 = <&i2c0_scl_gpio>; + scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -761,6 +764,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_scl>; + pinctrl-1 = <&i2c1_scl_gpio>; + scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -773,6 +780,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_scl>; + pinctrl-1 = <&i2c2_scl_gpio>; + scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -785,6 +796,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c3_scl>; + pinctrl-1 = <&i2c3_scl_gpio>; + scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -797,7 +812,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; - scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_scl>; + pinctrl-1 = <&i2c4_scl_gpio>; + scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -810,6 +828,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c5_scl>; + pinctrl-1 = <&i2c5_scl_gpio>; + scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -822,6 +844,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c6_scl>; + pinctrl-1 = <&i2c6_scl_gpio>; + scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -834,6 +860,10 @@ clock-names = "i2c"; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c7_scl>; + pinctrl-1 = <&i2c7_scl_gpio>; + scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -1669,6 +1699,80 @@ }; }; + pinmux_i2crv: pinmux@70010012c { + compatible = "pinctrl-single"; + reg = <0x00000007 0x0010012c 0x0 0xc>; + #address-cells = <2>; + #size-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; + + i2c1_scl: i2c1-scl-pins { + pinctrl-single,bits = <0x0 0 0x7>; + }; + + i2c1_scl_gpio: i2c1-scl-gpio-pins { + pinctrl-single,bits = <0x0 0x1 0x7>; + }; + + i2c2_scl: i2c2-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 3)>; + }; + + i2c2_scl_gpio: i2c2-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; + }; + + i2c3_scl: i2c3-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 6)>; + }; + + i2c3_scl_gpio: i2c3-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; + }; + + i2c4_scl: i2c4-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 9)>; + }; + + i2c4_scl_gpio: i2c4-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; + }; + + i2c5_scl: i2c5-scl-pins { + pinctrl-single,bits = <0x0 0 (0x7 << 12)>; + }; + + i2c5_scl_gpio: i2c5-scl-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; + }; + + i2c6_scl: i2c6-scl-pins { + pinctrl-single,bits = <0x4 0x2 0x7>; + }; + + i2c6_scl_gpio: i2c6-scl-gpio-pins { + pinctrl-single,bits = <0x4 0x1 0x7>; + }; + + i2c7_scl: i2c7-scl-pins { + pinctrl-single,bits = <0x4 0x2 0x7>; + }; + + i2c7_scl_gpio: i2c7-scl-gpio-pins { + pinctrl-single,bits = <0x4 0x1 0x7>; + }; + + i2c0_scl: i2c0-scl-pins { + pinctrl-single,bits = <0x8 0 (0x7 << 10)>; + }; + + i2c0_scl_gpio: i2c0-scl-gpio-pins { + pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, From cb8d3006d5ceea3f78c7ab06bfeb63820b31e7ad Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 28 Mar 2024 10:51:36 -0400 Subject: [PATCH 183/969] arm64: dts: imx8: fix audio lpcg index lpcg cell0 should be clock's 'indices' instead of 'index'. imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec, void *data) { struct clk_hw_onecell_data *hw_data = data; unsigned int idx = clkspec->args[0] / 4; .... } <@sai0_lpcg 1> will be the same as <@sai_lpcg 0>. Replace 0 with IMX_LPCG_CLK_0 and replace 1 with IMX_LPCG_CLK_4. It can work at iMX8QXP because IMX_LPCG_CLK_4 is ipg clock, which already enabled. But for iMX8QM IMX_LPCG_CLK_4 is mclk, which trigger issue. Fixes: 0a9279e9ae88 ("arm64: dts: imx8qxp: Add audio SAI nodes") Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 07afeb78ed56..d8bbe53320bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -123,9 +123,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59040000 0x10000>; interrupts = ; - clocks = <&sai0_lpcg 1>, + clocks = <&sai0_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai0_lpcg 0>, + <&sai0_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -139,9 +139,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59050000 0x10000>; interrupts = ; - clocks = <&sai1_lpcg 1>, + clocks = <&sai1_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai1_lpcg 0>, + <&sai1_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -155,9 +155,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59060000 0x10000>; interrupts = ; - clocks = <&sai2_lpcg 1>, + clocks = <&sai2_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai2_lpcg 0>, + <&sai2_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; @@ -171,9 +171,9 @@ audio_subsys: bus@59000000 { compatible = "fsl,imx8qm-sai"; reg = <0x59070000 0x10000>; interrupts = ; - clocks = <&sai3_lpcg 1>, + clocks = <&sai3_lpcg IMX_LPCG_CLK_4>, <&clk_dummy>, - <&sai3_lpcg 0>, + <&sai3_lpcg IMX_LPCG_CLK_0>, <&clk_dummy>, <&clk_dummy>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; From 5125617c7a4d32920c769a7ee0493d95e0521978 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 28 Mar 2024 10:51:37 -0400 Subject: [PATCH 184/969] arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5] Add asrc[0,1], esai0, spdif0, sai[4,5] and related lpcg node for imx8 audio subsystem. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-audio.dtsi | 269 ++++++++++++++++++ 1 file changed, 269 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index d8bbe53320bc..897cbb7b6742 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -6,6 +6,7 @@ #include #include +#include #include audio_ipg_clk: clock-audio-ipg { @@ -119,6 +120,89 @@ audio_subsys: bus@59000000 { #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x1000000>; + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59000000 0x10000>; + interrupts = ; + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, + <&edma0 1 0 0>, + <&edma0 2 0 0>, + <&edma0 3 0 FSL_EDMA_RX>, + <&edma0 4 0 FSL_EDMA_RX>, + <&edma0 5 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <0>; + power-domains = <&pd IMX_SC_R_ASRC_0>; + status = "disabled"; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x59010000 0x10000>; + interrupts = ; + clocks = <&esai0_lpcg IMX_LPCG_CLK_4>, + <&esai0_lpcg IMX_LPCG_CLK_0>, + <&esai0_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59020000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", + "rxtx5", "rxtx6", "rxtx7", "spba"; + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + status = "disabled"; + }; + sai0: sai@59040000 { compatible = "fsl,imx8qm-sai"; reg = <0x59040000 0x10000>; @@ -239,6 +323,40 @@ audio_subsys: bus@59000000 { <&pd IMX_SC_R_DMA_0_CH23>; }; + asrc0_lpcg: clock-controller@59400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59400000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = ; + clock-output-names = "asrc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_0>; + }; + + esai0_lpcg: clock-controller@59410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59410000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "esai0_lpcg_extal_clk", + "esai0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_0>; + }; + + spdif0_lpcg: clock-controller@59420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59420000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "spdif0_lpcg_tx_clk", + "spdif0_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_0>; + }; + sai0_lpcg: clock-controller@59440000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59440000 0x10000>; @@ -333,6 +451,101 @@ audio_subsys: bus@59000000 { status = "disabled"; }; + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc"; + reg = <0x59800000 0x10000>; + interrupts = ; + clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>, + <&asrc1_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, + <&edma1 1 0 0>, + <&edma1 2 0 0>, + <&edma1 3 0 FSL_EDMA_RX>, + <&edma1 4 0 FSL_EDMA_RX>, + <&edma1 5 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + fsl,asrc-clk-map = <1>; + power-domains = <&pd IMX_SC_R_ASRC_1>; + status = "disabled"; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&sai4_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&sai5_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 10 0 0>; + dma-names = "tx"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-audmix"; + reg = <0x59840000 0x10000>; + clocks = <&amix_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_AMIX>; + dais = <&sai4>, <&sai5>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x59850000 0x10000>; + clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk", "core"; + power-domains = <&pd IMX_SC_R_MQS_0>; + status = "disabled"; + }; + edma1: dma-controller@599f0000 { compatible = "fsl,imx8qm-edma"; reg = <0x599f0000 0xc0000>; @@ -481,4 +694,60 @@ audio_subsys: bus@59000000 { "sai3_rx_bclk", "sai4_rx_bclk"; }; + + asrc1_lpcg: clock-controller@59c00000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c00000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = ; + clock-output-names = "asrc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ASRC_1>; + }; + + sai4_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai4_lpcg_mclk", + "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + }; + + sai5_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai5_lpcg_mclk", + "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + }; + + amix_lpcg: clock-controller@59c40000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c40000 0x10000>; + #clock-cells = <1>; + clocks = <&audio_ipg_clk>; + clock-indices = ; + clock-output-names = "amix_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_AMIX>; + }; + + mqs0_lpcg: clock-controller@59c50000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c50000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "mqs0_lpcg_mclk", + "mqs0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MQS_0>; + }; }; From e487d804104286494e4c47e17f0f42f5d9df993d Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Mar 2024 08:09:39 -0700 Subject: [PATCH 185/969] arm64: dts: imx8mp-venice-gw72xx: add mac addr for eth1 The SoM used on this board does not bring down the pins for the QOS ethernet and instead offers the 2nd ethernet as a PCI GbE device. Set the alias as such and add the PCI bus topology for eth1 so that boot firmware can set the local-mac-address property. The eth1 device is behind a PCI switch: # lspci -n 00:00.0 0604: 16c3:abcd (rev 01) 01:00.0 0604: 12d8:b404 (rev 01) 02:01.0 0604: 12d8:b404 (rev 01) 02:02.0 0604: 12d8:b404 (rev 01) 02:03.0 0604: 12d8:b404 (rev 01) 05:00.0 0200: 11ab:4380 # lspci -t -[0000:00]---00.0-[01-ff]----00.0-[02-05]--+-01.0-[03]-- +-02.0-[04]-- \-03.0-[05]----00.0 Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-venice-gw72xx.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi index 41c79d2ebdd6..cda1671d2259 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi @@ -8,6 +8,10 @@ #include / { + aliases { + ethernet1 = ð1; + }; + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; pinctrl-names = "default"; @@ -151,6 +155,38 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@3,0 { + reg = <0x1800 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + eth1: ethernet@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; }; /* GPS */ From 3237a31ae2775b0546a37a369df667075d7f6d87 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Mar 2024 08:09:40 -0700 Subject: [PATCH 186/969] arm64: dts: imx8mp-venice-gw73xx: add mac addr for eth1 The SoM used on this board does not bring down the pins for the QOS ethernet and instead offers the 2nd ethernet as a PCI GbE device. Set the alias as such and add the PCI bus topology for eth1 so that boot firmware can set the local-mac-address property. The eth1 device is behind a PCI switch: # lspci -n 00:00.0 0604: 16c3:abcd (rev 01) 01:00.0 0604: 12d8:2608 02:01.0 0604: 12d8:2608 02:02.0 0604: 12d8:2608 02:03.0 0604: 12d8:2608 02:04.0 0604: 12d8:2608 c0:00.0 0200: 1055:7430 (rev 11) # lspci -t -[0000:00]---00.0-[01-ff]----00.0-[02-fe]--+-01.0-[03-41]-- +-02.0-[42-80]-- +-03.0-[81-bf]-- \-04.0-[c0-fe]----00.0 Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-venice-gw73xx.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi index d5c400b355af..e63811b38c64 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi @@ -8,6 +8,10 @@ #include / { + aliases { + ethernet1 = ð1; + }; + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; pinctrl-names = "default"; @@ -163,6 +167,38 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + pcie@4,0 { + reg = <0x2000 0 0 0 0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + eth1: ethernet@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; }; /* GPS */ From 101e72eeb5ec119fededcc12446fe31e8237aee4 Mon Sep 17 00:00:00 2001 From: Gilles Talis Date: Sat, 30 Mar 2024 09:34:08 -0400 Subject: [PATCH 187/969] dt-bindings: vendor-prefixes: Add Emcraft Systems Add an entry for Emcraft Systems (https://www.emcraft.com/) Signed-off-by: Gilles Talis Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b97d298b3eb6..8b978c6f1dfd 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -438,6 +438,8 @@ patternProperties: description: Dongguan EmbedFire Electronic Technology Co., Ltd. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. + "^emcraft,.*": + description: Emcraft Systems "^emlid,.*": description: Emlid, Ltd. "^emmicro,.*": From 9cdddb03339874f3039955bfb5432bec29407b19 Mon Sep 17 00:00:00 2001 From: Gilles Talis Date: Sat, 30 Mar 2024 09:34:09 -0400 Subject: [PATCH 188/969] dt-bindings: arm: Add Emcraft Systems i.MX8M Plus NavQ+ Kit Add DT compatible string for Emcraft NavQ+ kit based on the i.MX8M Plus SoC from NXP Signed-off-by: Gilles Talis Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 35494a294c6b..304db8f302aa 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1058,6 +1058,7 @@ properties: - enum: - beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC + - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board From 682729a9d506d066afc8b0563cbeed69c54cce68 Mon Sep 17 00:00:00 2001 From: Gilles Talis Date: Sat, 30 Mar 2024 09:34:10 -0400 Subject: [PATCH 189/969] arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit The Emcraft Systems NavQ+ kit is a mobile robotics platform based on NXP i.MX8 MPlus SoC. The following interfaces and devices are enabled: - eMMC - Gigabit Ethernet - RTC - SD-Card - UART console Signed-off-by: Gilles Talis Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../arm64/boot/dts/freescale/imx8mp-navqp.dts | 424 ++++++++++++++++++ 2 files changed, 425 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-navqp.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 768feb886ea2..ee2b28d76c44 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts new file mode 100644 index 000000000000..5fd1614982cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Emcraft Systems + * Copyright 2024 Gilles Talis + */ + +/dts-v1/; + +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "Emcraft Systems i.MX8MPlus NavQ+ Kit"; + compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <10000>; + qca,disable-smarteee; + qca,disable-hibernation-mode; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + }; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; From 0bb36055c049b9600ea0fbf4b1ad66a1dc3d5aa3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 31 Mar 2024 23:33:46 -0300 Subject: [PATCH 190/969] ARM: imx_v6_v7_defconfig: Select CONFIG_USB_ONBOARD_HUB The imx6qdl-udoo board has a USB2514 Hub connected to the USB Host1 port. Select CONFIG_USB_ONBOARD_HUB so that USB hub can be functional. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 7327fce87808..b06128da94e5 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -336,6 +336,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_TEST=m CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ONBOARD_HUB=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y From f246a0a3c40802aba2f5bda1c2e65923a444f735 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 31 Mar 2024 23:33:47 -0300 Subject: [PATCH 191/969] ARM: dts: imx6qdl-udoo: Enable USB host Commit 8f2ca252ee1f ("ARM: dts: imx6qdl-udoo: Disable USB host to work around boot issues") disabled USB host to avoid boot hang. Properly describe the USB2514 USB hub to fix this issue. Tested on a imx6q-udoo board and verified that it boots fine and USB host functionality works. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi | 25 ++++++++++----------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi index 647ba5e623dd..14272b42f9a1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi @@ -59,16 +59,6 @@ }; }; - reg_usb_h1_vbus: regulator-usb-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ - gpio = <&gpio7 12 0>; - }; - reg_panel: regulator-panel { compatible = "regulator-fixed"; regulator-name = "lcd_panel"; @@ -285,9 +275,18 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh>; - vbus-supply = <®_usb_h1_vbus>; - clocks = <&clks IMX6QDL_CLK_CKO>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb-port@1 { + compatible = "usb424,2514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO>; + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; }; &usbotg { From 7a761ddbb9da9de257f6c120c61401f837ac7cd7 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 1 Apr 2024 20:54:15 +0800 Subject: [PATCH 192/969] ARM: dts: imx6sx-nitrogen6sx: drop incorrect cpu-dai property drop incorrect cpu-dai property, change it to ssi-controller Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts index cd9cbc9ccc9e..b82d91a7d76d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts @@ -83,7 +83,7 @@ sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx6sx-nitrogen6sx-sgtl5000"; - cpu-dai = <&ssi1>; + ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "MIC_IN", "Mic Jack", From 66c6700467663c9acc4d843161e210260fc37b36 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 2 Apr 2024 12:33:55 -0700 Subject: [PATCH 193/969] arm64: dts: imx8m*-venice-gw7: Fix TPM schema violations Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS bindings"), several issues are reported by "make dtbs_check" for arm64 devicetrees: The compatible property needs to contain the chip's name in addition to the generic "tcg,tpm_tis-spi". tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml# Fix these schema violations. Gateworks Venice uses an Atmel ATTPM20P: https://trac.gateworks.com/wiki/tpm Cc: Lukas Wunner Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 41c966147b94..429be2bab8a2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -57,7 +57,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 5e2cbaf27e0f..35ae0faa815b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -297,7 +297,7 @@ }; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi index e7bf032265e0..2f740d74707b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -68,7 +68,7 @@ status = "okay"; tpm@1 { - compatible = "tcg,tpm_tis-spi"; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x1>; spi-max-frequency = <36000000>; }; From 64f86ba290d0c861ce430e9bb4db9eef0bc2315f Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Tue, 2 Apr 2024 10:41:28 -0400 Subject: [PATCH 194/969] arm64: dts: imx8: add cm40 subsystem dtsi Add cm40 subsystem dtsi. Reviewed-by: Peng Fan Signed-off-by: Dong Aisheng Reviewed-by: Alexander Stein Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 + arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + 3 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi new file mode 100644 index 000000000000..84d7ae01e5f4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng + */ + +#include + +cm40_ipg_clk: clock-cm40-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm40_ipg_clk"; +}; + +cm40_subsys: bus@34000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x34000000 0x0 0x34000000 0x4000000>; + interrupt-parent = <&cm40_intmux>; + + cm40_i2c: i2c@37230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x37230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>, + <&cm40_i2c_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + status = "disabled"; + }; + + cm40_intmux: intmux@37400000 { + compatible = "fsl,imx-intmux"; + reg = <0x37400000 0x1000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&cm40_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; + status = "disabled"; + }; + + cm40_i2c_lpcg: clock-controller@37630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + clock-indices = , ; + clock-output-names = "cm40_lpcg_i2c_clk", + "cm40_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_I2C>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a0674c5c5576..9d49c75a2622 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -231,6 +232,7 @@ }; /* sorted in register address */ + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 10e16d84c0c3..0313f295de2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -317,6 +317,7 @@ /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-cm40.dtsi" #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" From 651a45f684224b9188de58932bef318bd90a7a21 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 2 Apr 2024 10:41:29 -0400 Subject: [PATCH 195/969] arm64: dts: imx8dxl: add lpuart device in cm40 subsystem Add lpuart device in cm40 subsystem. Signed-off-by: Alice Guo Reviewed-by: Peng Fan Reviewed-by: Alexander Stein Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-cm40.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi index 84d7ae01e5f4..92752c0c5eb5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi @@ -20,6 +20,18 @@ cm40_subsys: bus@34000000 { ranges = <0x34000000 0x0 0x34000000 0x4000000>; interrupt-parent = <&cm40_intmux>; + cm40_lpuart: serial@37220000 { + compatible = "fsl,imx8qxp-lpuart"; + reg = <0x37220000 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + status = "disabled"; + }; + cm40_i2c: i2c@37230000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x37230000 0x1000>; @@ -53,6 +65,18 @@ cm40_subsys: bus@34000000 { status = "disabled"; }; + cm40_uart_lpcg: clock-controller@37620000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x37620000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>, + <&cm40_ipg_clk>; + clock-indices = , ; + clock-output-names = "cm40_lpcg_uart_clk", + "cm40_lpcg_uart_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_0_UART>; + }; + cm40_i2c_lpcg: clock-controller@37630000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x37630000 0x1000>; From e6d3431b6b5f1c12a2e08535e6db8020fa7dbd8c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 2 Apr 2024 10:41:30 -0400 Subject: [PATCH 196/969] arm64: dts: imx8dxl: update cm40 irq number information Update cm40 irq number for imx8dxl chip. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 9d49c75a2622..b9d137d69f5a 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -243,3 +243,14 @@ #include "imx8dxl-ss-conn.dtsi" #include "imx8dxl-ss-lsio.dtsi" #include "imx8dxl-ss-ddr.dtsi" + +&cm40_intmux { + interrupts = , + , + , + , + , + , + , + ; +}; From 56853cda3ca4a1c9d462a9dcd68e7c55e04592dc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 2 Apr 2024 10:41:31 -0400 Subject: [PATCH 197/969] arm64: dts: imx8dxl-evk: add lpuart1 and cm40 uart Add lpuart1 and cm40 uart. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 2123d431e061..2412ab145c06 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -16,6 +16,8 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart0; + serial1 = &lpuart1; + serial6 = &cm40_lpuart; }; chosen { @@ -51,6 +53,16 @@ }; }; + m2_uart1_sel: regulator-m2uart1sel { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "m2_uart1_sel"; + gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + mux3_en: regulator-0 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -340,6 +352,12 @@ status = "okay"; }; +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -354,6 +372,16 @@ status = "okay"; }; +&cm40_intmux { + status = "disabled"; +}; + +&cm40_lpuart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm40_lpuart>; + status = "disabled"; +}; + &lsio_gpio4 { status = "okay"; }; @@ -595,6 +623,15 @@ >; }; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020 + IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 + IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 + IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 From cb69e758d5918cc03e449e159162e263e8bc7ec1 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 28 Feb 2024 17:28:26 -0800 Subject: [PATCH 198/969] arm64: dts: qcom: sc7180: Disable pmic pinctrl node on Trogdor We don't use this pmic pinctrl node on any Trogdor devices. The AP_SUSPEND pin is here, but this pinctrl device isn't a supplier to anything in the devicetrees that include this file. Disable this device node in the DTS so that we don't waste time or memory on this device. Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240229012828.438020-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f3a6da8b2890..f0a7de8f4b7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1165,6 +1165,7 @@ ap_spi_fp: &spi10 { }; &pm6150l_gpios { + status = "disabled"; /* No GPIOs are consumed or configured */ gpio-line-names = "AP_SUSPEND", "", "", From 9f618cdce29d7bef10c2f4c8cbf58bc5cb778d6a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 28 Feb 2024 17:35:01 -0800 Subject: [PATCH 199/969] arm64: dts: qcom: sc7180: Disable DCC node by default We don't use this device on Trogdor boards. If we did, it would be enabled in the sc7180-trogdor.dtsi file. Let's disable this here so that boards with t he sc7180 SoC can decide to enable or disable this device. Cc: Souradeep Chowdhury Fixes: add74cad7c9d ("arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support node") Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240229013503.483651-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2b481e20ae38..3215709a7001 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2309,6 +2309,7 @@ compatible = "qcom,sc7180-dcc", "qcom,dcc"; reg = <0x0 0x010a2000 0x0 0x1000>, <0x0 0x010ae000 0x0 0x2000>; + status = "disabled"; }; stm@6002000 { From 53426f53eda5e4a17197a8bc7dd1045601db407e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 14 Mar 2024 19:56:22 +0100 Subject: [PATCH 200/969] ARM: dts: qcom: msm8974-sony-castor: Split into shinano-common In preparation for adding the Sony Xperia Z3 smartphone, split the common parts into shinano-common.dtsi. No functional change intended. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240314-shinano-common-v2-1-a0fce1c72c74@z3ntu.xyz Signed-off-by: Bjorn Andersson --- ...-msm8974pro-sony-xperia-shinano-castor.dts | 551 +----------------- ...msm8974pro-sony-xperia-shinano-common.dtsi | 535 +++++++++++++++++ 2 files changed, 556 insertions(+), 530 deletions(-) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 20f98a9e49ea..409d1798de34 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -1,48 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "pm8841.dtsi" -#include "pm8941.dtsi" -#include -#include -#include +#include "qcom-msm8974pro-sony-xperia-shinano-common.dtsi" / { model = "Sony Xperia Z2 Tablet"; compatible = "sony,xperia-castor", "qcom,msm8974pro", "qcom,msm8974"; chassis-type = "tablet"; - aliases { - mmc0 = &sdhc_1; - mmc1 = &sdhc_2; - serial0 = &blsp1_uart2; - serial1 = &blsp2_uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&gpio_keys_pin_a>; - pinctrl-names = "default"; - - key-volume-down { - label = "volume_down"; - gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - }; - }; - vreg_bl_vddio: lcd-backlight-vddio { compatible = "regulator-fixed"; regulator-name = "vreg_bl_vddio"; @@ -58,100 +21,6 @@ pinctrl-0 = <&lcd_backlight_en_pin_a>; pinctrl-names = "default"; }; - - vreg_vsp: lcd-dcdc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_vsp"; - regulator-min-microvolt = <5600000>; - regulator-max-microvolt = <5600000>; - - gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&lcd_dcdc_en_pin_a>; - pinctrl-names = "default"; - }; - - vreg_boost: vreg-boost { - compatible = "regulator-fixed"; - - regulator-name = "vreg-boost"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - regulator-always-on; - regulator-boot-on; - - gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&boost_bypass_n_pin>; - }; - - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wlan_regulator_pin>; - pinctrl-names = "default"; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_i2c2 { - clock-frequency = <355000>; - - status = "okay"; - - synaptics@2c { - compatible = "syna,rmi4-i2c"; - reg = <0x2c>; - - interrupt-parent = <&tlmm>; - interrupts = <86 IRQ_TYPE_EDGE_FALLING>; - - #address-cells = <1>; - #size-cells = <0>; - - vdd-supply = <&pm8941_l22>; - vio-supply = <&pm8941_lvs3>; - - pinctrl-0 = <&ts_int_pin>; - pinctrl-names = "default"; - - syna,startup-delay-ms = <100>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f11@11 { - reg = <0x11>; - syna,sensor-type = <1>; - touchscreen-inverted-x; - }; - }; }; &blsp2_i2c5 { @@ -172,42 +41,52 @@ rom-addr = /bits/ 8 <0xa0>; rom-val = /bits/ 8 <0xff>; }; + rom-a1h { rom-addr = /bits/ 8 <0xa1>; rom-val = /bits/ 8 <0x3f>; }; + rom-a2h { rom-addr = /bits/ 8 <0xa2>; rom-val = /bits/ 8 <0x20>; }; + rom-a3h { rom-addr = /bits/ 8 <0xa3>; rom-val = /bits/ 8 <0x5e>; }; + rom-a4h { rom-addr = /bits/ 8 <0xa4>; rom-val = /bits/ 8 <0x02>; }; + rom-a5h { rom-addr = /bits/ 8 <0xa5>; rom-val = /bits/ 8 <0x04>; }; + rom-a6h { rom-addr = /bits/ 8 <0xa6>; rom-val = /bits/ 8 <0x80>; }; + rom-a7h { rom-addr = /bits/ 8 <0xa7>; rom-val = /bits/ 8 <0xf7>; }; + rom-a9h { rom-addr = /bits/ 8 <0xa9>; rom-val = /bits/ 8 <0x80>; }; + rom-aah { rom-addr = /bits/ 8 <0xaa>; rom-val = /bits/ 8 <0x0f>; }; + rom-aeh { rom-addr = /bits/ 8 <0xae>; rom-val = /bits/ 8 <0x0f>; @@ -231,330 +110,26 @@ }; }; -&pm8941_coincell { - qcom,rset-ohms = <2100>; - qcom,vset-millivolts = <3000>; - - status = "okay"; -}; - &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio2", "gpio5"; - function = "normal"; - bias-pull-up; - power-source = ; - }; - bt_reg_on_pin: bt-reg-on-state { pins = "gpio16"; function = "normal"; output-low; power-source = ; }; - - wlan_sleep_clk_pin: wl-sleep-clk-state { - pins = "gpio17"; - function = "func2"; - output-high; - power-source = ; - }; - - wlan_regulator_pin: wl-reg-active-state { - pins = "gpio18"; - function = "normal"; - bias-disable; - power-source = ; - }; - - lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { - pins = "gpio20"; - function = "normal"; - bias-disable; - power-source = ; - input-disable; - output-low; - }; -}; - -&pm8941_lpg { - qcom,power-source = <1>; - - status = "okay"; - - multi-led { - color = ; - function = LED_FUNCTION_STATUS; - - #address-cells = <1>; - #size-cells = <0>; - - led@5 { - reg = <5>; - color = ; - }; - - led@6 { - reg = <6>; - color = ; - }; - - led@7 { - reg = <7>; - color = ; - }; - }; -}; - -&remoteproc_adsp { - cx-supply = <&pm8841_s2>; - status = "okay"; -}; - -&remoteproc_mss { - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - status = "okay"; }; &rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8841-regulators"; - - pm8841_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s3: s3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - }; - regulators-1 { - compatible = "qcom,rpm-pm8941-regulators"; - - vdd_l1_l3-supply = <&pm8941_s1>; - vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; - vdd_l4_l11-supply = <&pm8941_s1>; - vdd_l5_l7-supply = <&pm8941_s2>; - vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; - vdd_l9_l10_l17_l22-supply = <&vreg_boost>; - vdd_l13_l20_l23_l24-supply = <&vreg_boost>; - vdd_l21-supply = <&vreg_boost>; - - pm8941_s1: s1 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s2: s2 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - regulator-boot-on; - }; - - pm8941_s3: s3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-system-load = <154000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_s4: s4 { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - pm8941_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l3: l3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8941_l4: l4 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pm8941_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; - - pm8941_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - pm8941_l11: l11 { regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1350000>; }; - pm8941_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - pm8941_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8941_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8941_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l17: l17 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pm8941_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - pm8941_l19: l19 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; }; - - pm8941_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <500000>; - regulator-allow-set-load; - regulator-boot-on; - }; - - pm8941_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-boot-on; - }; - - pm8941_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pm8941_l23: l23 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8941_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - regulator-boot-on; - }; - - pm8941_lvs3: lvs3 {}; - }; -}; - -&sdhc_1 { - vmmc-supply = <&pm8941_l20>; - vqmmc-supply = <&pm8941_s3>; - - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - pinctrl-names = "default", "sleep"; - - status = "okay"; -}; - -&sdhc_2 { - vmmc-supply = <&pm8941_l21>; - vqmmc-supply = <&pm8941_l13>; - - cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - pinctrl-names = "default", "sleep"; - - status = "okay"; -}; - -&sdhc_3 { - max-frequency = <100000000>; - vmmc-supply = <&vreg_wlan>; - non-removable; - - pinctrl-0 = <&sdc3_on>; - pinctrl-names = "default"; - - status = "okay"; - - wifi@1 { - compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; - reg = <1>; - - brcm,drive-strength = <10>; - - pinctrl-0 = <&wlan_sleep_clk_pin>; - pinctrl-names = "default"; }; }; @@ -572,75 +147,13 @@ status = "okay"; }; +&synaptics_touchscreen { + vio-supply = <&pm8941_lvs3>; +}; + &tlmm { - lcd_backlight_en_pin_a: lcd-backlight-vddio-state { - pins = "gpio69"; - function = "gpio"; - drive-strength = <10>; - output-low; - bias-disable; - }; - - sdc1_on: sdc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - sdc2_on: sdc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - - cd-pins { - pins = "gpio62"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - }; - - sdc3_on: sdc3-on-state { - clk-pins { - pins = "gpio40"; - function = "sdc3"; - drive-strength = <10>; - bias-disable; - }; - - cmd-pins { - pins = "gpio39"; - function = "sdc3"; - drive-strength = <10>; - bias-pull-up; - }; - - data-pins { - pins = "gpio35", "gpio36", "gpio37", "gpio38"; - function = "sdc3"; - drive-strength = <10>; - bias-pull-up; - }; - }; - - ts_int_pin: ts-int-pin-state { - pins = "gpio86"; + bt_dev_wake_pin: bt-dev-wake-state { + pins = "gpio96"; function = "gpio"; drive-strength = <2>; bias-disable; @@ -654,33 +167,11 @@ output-low; }; - bt_dev_wake_pin: bt-dev-wake-state { - pins = "gpio96"; + lcd_backlight_en_pin_a: lcd-backlight-vddio-state { + pins = "gpio69"; function = "gpio"; - drive-strength = <2>; + drive-strength = <10>; + output-low; bias-disable; }; }; - -&usb { - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - extcon = <&smbb>, <&usb_id>; - vbus-supply = <&chg_otg>; - - hnp-disable; - srp-disable; - adp-disable; - - status = "okay"; -}; - -&usb_hs1_phy { - v1p8-supply = <&pm8941_l6>; - v3p3-supply = <&pm8941_l24>; - - extcon = <&smbb>; - qcom,init-seq = /bits/ 8 <0x1 0x64>; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi new file mode 100644 index 000000000000..3a0c0035de09 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" +#include +#include +#include + +/ { + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_pin_a>; + pinctrl-names = "default"; + + key-volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + vreg_vsp: lcd-dcdc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_vsp"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + + gpio = <&pm8941_gpios 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&lcd_dcdc_en_pin_a>; + pinctrl-names = "default"; + }; + + vreg_boost: vreg-boost { + compatible = "regulator-fixed"; + + regulator-name = "vreg-boost"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + regulator-always-on; + regulator-boot-on; + + gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&boost_bypass_n_pin>; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8941_gpios 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wlan_regulator_pin>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c2 { + clock-frequency = <355000>; + + status = "okay"; + + synaptics_touchscreen: synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupt-parent = <&tlmm>; + interrupts = <86 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + /* vio-supply is set in dts */ + + pinctrl-0 = <&ts_int_pin>; + pinctrl-names = "default"; + + syna,startup-delay-ms = <100>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + touchscreen-inverted-x; + }; + }; +}; + +&pm8941_coincell { + qcom,rset-ohms = <2100>; + qcom,vset-millivolts = <3000>; + + status = "okay"; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio5"; + function = "normal"; + bias-pull-up; + power-source = ; + }; + + wlan_sleep_clk_pin: wl-sleep-clk-state { + pins = "gpio17"; + function = "func2"; + output-high; + power-source = ; + }; + + wlan_regulator_pin: wl-reg-active-state { + pins = "gpio18"; + function = "normal"; + bias-disable; + power-source = ; + }; + + lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { + pins = "gpio20"; + function = "normal"; + bias-disable; + power-source = ; + input-disable; + output-low; + }; +}; + +&pm8941_lpg { + qcom,power-source = <1>; + + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@5 { + reg = <5>; + color = ; + }; + + led@6 { + reg = <6>; + color = ; + }; + + led@7 { + reg = <7>; + color = ; + }; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <154000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s4: s4 { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <500000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + + pm8941_lvs3: lvs3 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l13>; + + cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sdhc_3 { + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + non-removable; + + pinctrl-0 = <&sdc3_on>; + pinctrl-names = "default"; + + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4339-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + brcm,drive-strength = <10>; + + pinctrl-0 = <&wlan_sleep_clk_pin>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + + cd-pins { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + sdc3_on: sdc3-on-state { + clk-pins { + pins = "gpio40"; + function = "sdc3"; + drive-strength = <10>; + bias-disable; + }; + + cmd-pins { + pins = "gpio39"; + function = "sdc3"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "gpio35", "gpio36", "gpio37", "gpio38"; + function = "sdc3"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + ts_int_pin: ts-int-pin-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&usb { + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + status = "okay"; +}; + +&usb_hs1_phy { + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x64>; + + status = "okay"; +}; From 8d91a5a4a6f5aff714a14ac4a86931aa789655d8 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 14 Mar 2024 19:56:24 +0100 Subject: [PATCH 201/969] ARM: dts: qcom: Add Sony Xperia Z3 smartphone Add the dts for the Xperia Z3 smartphone which is based on Sony's shinano platform, so at the moment there's little device-specific dts to add on top of the common parts. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240314-shinano-common-v2-3-a0fce1c72c74@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + ...com-msm8974pro-sony-xperia-shinano-leo.dts | 44 +++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-leo.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 6478a39b3be5..de5b0d282e74 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974pro-oneplus-bacon.dtb \ qcom-msm8974pro-samsung-klte.dtb \ qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ + qcom-msm8974pro-sony-xperia-shinano-leo.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ qcom-sdx55-mtp.dtb \ qcom-sdx55-t55.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-leo.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-leo.dts new file mode 100644 index 000000000000..1ed6e1cc21d5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-leo.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro-sony-xperia-shinano-common.dtsi" + +/ { + model = "Sony Xperia Z3"; + compatible = "sony,xperia-leo", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + gpio-keys { + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; +}; + +&gpio_keys_pin_a { + pins = "gpio2", "gpio3", "gpio4", "gpio5"; +}; + +&smbb { + usb-charge-current-limit = <1500000>; + qcom,fast-charge-safe-current = <3000000>; + qcom,fast-charge-current-limit = <2150000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4280000>; + qcom,minimum-input-voltage = <4200000>; + + status = "okay"; +}; + +&synaptics_touchscreen { + vio-supply = <&pm8941_s3>; +}; From a97b6c42a7b823c429fac562a02d291b47b98d7e Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:23 -0700 Subject: [PATCH 202/969] arm64: defconfig: Enable sc7280 display and gpu clock controllers Enable the SC7280 display and gpu clock controllers to enable display support on the QCS6490 RB3gen2. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-6-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6c45a465a071..a25a28e6117b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1287,6 +1287,7 @@ CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m +CONFIG_SC_DISPCC_7280=m CONFIG_SC_DISPCC_8280XP=m CONFIG_SA_GCC_8775P=y CONFIG_SA_GPUCC_8775P=m @@ -1294,6 +1295,7 @@ CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y CONFIG_SC_GCC_8280XP=y +CONFIG_SC_GPUCC_7280=m CONFIG_SC_GPUCC_8280XP=m CONFIG_SC_LPASSCC_8280XP=m CONFIG_SDM_CAMCC_845=m From 8b90269ee6d7f8e714a1ba57a85444a67b9f0104 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 19 Mar 2024 17:01:45 -0700 Subject: [PATCH 203/969] MAINTAINERS: Split Qualcomm SoC and linux-arm-msm entries The Qualcomm Support entry in MAINTAINERS has served the purpose of both defining the scope of the Qualcomm support, and to make Qualcomm-related patches show up on the linux-arm-msm mailing list. While this continues to serve our needs, it occasionally do create confusion about the ownership. Split the entry to clarify which components are maintained under the qcom-soc tree. Signed-off-by: Bjorn Andersson Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240319-maintainer-qcom-split-v1-1-735d975af2c2@quicinc.com Signed-off-by: Bjorn Andersson --- MAINTAINERS | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..1f642120fbec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2586,12 +2586,8 @@ F: arch/arm64/boot/dts/qcom/sc7180* F: arch/arm64/boot/dts/qcom/sc7280* F: arch/arm64/boot/dts/qcom/sdm845-cheza* -ARM/QUALCOMM SUPPORT -M: Bjorn Andersson -M: Konrad Dybcio +ARM/QUALCOMM MAILING LIST L: linux-arm-msm@vger.kernel.org -S: Maintained -T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git F: Documentation/devicetree/bindings/*/qcom* F: Documentation/devicetree/bindings/soc/qcom/ F: arch/arm/boot/dts/qcom/ @@ -2628,6 +2624,33 @@ F: include/dt-bindings/*/qcom* F: include/linux/*/qcom* F: include/linux/soc/qcom/ +ARM/QUALCOMM SUPPORT +M: Bjorn Andersson +M: Konrad Dybcio +L: linux-arm-msm@vger.kernel.org +S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git +F: Documentation/devicetree/bindings/arm/qcom-soc.yaml +F: Documentation/devicetree/bindings/arm/qcom.yaml +F: Documentation/devicetree/bindings/bus/qcom* +F: Documentation/devicetree/bindings/cache/qcom,llcc.yaml +F: Documentation/devicetree/bindings/firmware/qcom,scm.yaml +F: Documentation/devicetree/bindings/reserved-memory/qcom +F: Documentation/devicetree/bindings/soc/qcom/ +F: arch/arm/boot/dts/qcom/ +F: arch/arm/configs/qcom_defconfig +F: arch/arm/mach-qcom/ +F: arch/arm64/boot/dts/qcom/ +F: drivers/bus/qcom* +F: drivers/firmware/qcom/ +F: drivers/soc/qcom/ +F: include/dt-bindings/arm/qcom,ids.h +F: include/dt-bindings/firmware/qcom,scm.h +F: include/dt-bindings/soc/qcom* +F: include/linux/firmware/qcom +F: include/linux/soc/qcom/ +F: include/soc/qcom/ + ARM/RDA MICRO ARCHITECTURE M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) From 0439fcff304acdedfc493dbf900dce86922fd31f Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Mon, 25 Mar 2024 16:11:01 +0100 Subject: [PATCH 204/969] tee: Refactor TEE subsystem header files Since commit 25559c22cef8 ("tee: add kernel internal client interface"), it has been a common include/linux/tee_drv.h header file which is shared to hold TEE subsystem internal bits along with the APIs exposed to the TEE client drivers. However, this practice is prone to TEE subsystem internal APIs abuse and especially so with the new TEE implementation drivers being added to reuse existing functionality. In order to address this split TEE subsystem internal bits as a separate header file: include/linux/tee_core.h which should be the one used by TEE implementation drivers. With that include/linux/tee_drv.h lists only APIs exposed by TEE subsystem to the TEE client drivers. Signed-off-by: Sumit Garg Signed-off-by: Balint Dobszay Signed-off-by: Jens Wiklander --- MAINTAINERS | 1 + drivers/tee/amdtee/amdtee_private.h | 2 +- drivers/tee/amdtee/call.c | 2 +- drivers/tee/amdtee/core.c | 3 +- drivers/tee/amdtee/shm_pool.c | 2 +- drivers/tee/optee/call.c | 2 +- drivers/tee/optee/core.c | 2 +- drivers/tee/optee/device.c | 2 +- drivers/tee/optee/ffa_abi.c | 2 +- drivers/tee/optee/notif.c | 2 +- drivers/tee/optee/optee_private.h | 2 +- drivers/tee/optee/rpc.c | 2 +- drivers/tee/optee/smc_abi.c | 2 +- drivers/tee/tee_core.c | 2 +- drivers/tee/tee_private.h | 35 --- drivers/tee/tee_shm.c | 2 +- drivers/tee/tee_shm_pool.c | 2 +- include/linux/tee_core.h | 296 ++++++++++++++++++++++++++ include/linux/tee_drv.h | 317 +++++----------------------- 19 files changed, 359 insertions(+), 321 deletions(-) create mode 100644 include/linux/tee_core.h diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..fd221a7d4d1c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21684,6 +21684,7 @@ F: Documentation/driver-api/tee.rst F: Documentation/tee/ F: Documentation/userspace-api/tee.rst F: drivers/tee/ +F: include/linux/tee_core.h F: include/linux/tee_drv.h F: include/uapi/linux/tee.h diff --git a/drivers/tee/amdtee/amdtee_private.h b/drivers/tee/amdtee/amdtee_private.h index 6d0f7062bb87..d87050033894 100644 --- a/drivers/tee/amdtee/amdtee_private.h +++ b/drivers/tee/amdtee/amdtee_private.h @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include #include "amdtee_if.h" diff --git a/drivers/tee/amdtee/call.c b/drivers/tee/amdtee/call.c index e9b63dcb3194..4c21b02be4af 100644 --- a/drivers/tee/amdtee/call.c +++ b/drivers/tee/amdtee/call.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/tee/amdtee/core.c b/drivers/tee/amdtee/core.c index 3c15f6a9e91c..e487231d25dc 100644 --- a/drivers/tee/amdtee/core.c +++ b/drivers/tee/amdtee/core.c @@ -9,13 +9,12 @@ #include #include #include -#include +#include #include #include #include #include #include "amdtee_private.h" -#include "../tee_private.h" #include static struct amdtee_driver_data *drv_data; diff --git a/drivers/tee/amdtee/shm_pool.c b/drivers/tee/amdtee/shm_pool.c index f0303126f199..6346e0bc8a64 100644 --- a/drivers/tee/amdtee/shm_pool.c +++ b/drivers/tee/amdtee/shm_pool.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include "amdtee_private.h" diff --git a/drivers/tee/optee/call.c b/drivers/tee/optee/call.c index a91e50be11be..16eb953e14bb 100644 --- a/drivers/tee/optee/call.c +++ b/drivers/tee/optee/call.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include #include "optee_private.h" diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 3aed554bc8d8..f762e3a25119 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include "optee_private.h" diff --git a/drivers/tee/optee/device.c b/drivers/tee/optee/device.c index 1892e49a8e6a..d296c70ddfdc 100644 --- a/drivers/tee/optee/device.c +++ b/drivers/tee/optee/device.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include #include "optee_private.h" diff --git a/drivers/tee/optee/ffa_abi.c b/drivers/tee/optee/ffa_abi.c index ecb5eb079408..cee8ccb84cb8 100644 --- a/drivers/tee/optee/ffa_abi.c +++ b/drivers/tee/optee/ffa_abi.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include "optee_private.h" #include "optee_ffa.h" diff --git a/drivers/tee/optee/notif.c b/drivers/tee/optee/notif.c index 05212842b0a5..0d7878e770cd 100644 --- a/drivers/tee/optee/notif.c +++ b/drivers/tee/optee/notif.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include "optee_private.h" struct notif_entry { diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 7a5243c78b55..a0698ac18993 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include "optee_msg.h" diff --git a/drivers/tee/optee/rpc.c b/drivers/tee/optee/rpc.c index e69bc6380683..f086812f1179 100644 --- a/drivers/tee/optee/rpc.c +++ b/drivers/tee/optee/rpc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "optee_private.h" #include "optee_rpc_cmd.h" diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index a37f87087e5c..9c296b887dc1 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include "optee_private.h" diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index e59c20d74b36..82ad095d2b1c 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/tee/tee_private.h b/drivers/tee/tee_private.h index 754e11dcb240..9bc50605227c 100644 --- a/drivers/tee/tee_private.h +++ b/drivers/tee/tee_private.h @@ -12,41 +12,6 @@ #include #include -#define TEE_DEVICE_FLAG_REGISTERED 0x1 -#define TEE_MAX_DEV_NAME_LEN 32 - -/** - * struct tee_device - TEE Device representation - * @name: name of device - * @desc: description of device - * @id: unique id of device - * @flags: represented by TEE_DEVICE_FLAG_REGISTERED above - * @dev: embedded basic device structure - * @cdev: embedded cdev - * @num_users: number of active users of this device - * @c_no_user: completion used when unregistering the device - * @mutex: mutex protecting @num_users and @idr - * @idr: register of user space shared memory objects allocated or - * registered on this device - * @pool: shared memory pool - */ -struct tee_device { - char name[TEE_MAX_DEV_NAME_LEN]; - const struct tee_desc *desc; - int id; - unsigned int flags; - - struct device dev; - struct cdev cdev; - - size_t num_users; - struct completion c_no_users; - struct mutex mutex; /* protects num_users and idr */ - - struct idr idr; - struct tee_shm_pool *pool; -}; - int tee_shm_get_fd(struct tee_shm *shm); bool tee_device_get(struct tee_device *teedev); diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c index 731d9028b67f..96a45c817427 100644 --- a/drivers/tee/tee_shm.c +++ b/drivers/tee/tee_shm.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/tee/tee_shm_pool.c b/drivers/tee/tee_shm_pool.c index 058bfbac657a..80004b55628d 100644 --- a/drivers/tee/tee_shm_pool.c +++ b/drivers/tee/tee_shm_pool.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include "tee_private.h" static int pool_op_gen_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, diff --git a/include/linux/tee_core.h b/include/linux/tee_core.h new file mode 100644 index 000000000000..d9b3ba8e8fa9 --- /dev/null +++ b/include/linux/tee_core.h @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Linaro Limited + */ + +#ifndef __TEE_CORE_H +#define __TEE_CORE_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The file describes the API provided by the generic TEE driver to the + * specific TEE driver. + */ + +#define TEE_SHM_DYNAMIC BIT(0) /* Dynamic shared memory registered */ + /* in secure world */ +#define TEE_SHM_USER_MAPPED BIT(1) /* Memory mapped in user space */ +#define TEE_SHM_POOL BIT(2) /* Memory allocated from pool */ +#define TEE_SHM_PRIV BIT(3) /* Memory private to TEE driver */ + +#define TEE_DEVICE_FLAG_REGISTERED 0x1 +#define TEE_MAX_DEV_NAME_LEN 32 + +/** + * struct tee_device - TEE Device representation + * @name: name of device + * @desc: description of device + * @id: unique id of device + * @flags: represented by TEE_DEVICE_FLAG_REGISTERED above + * @dev: embedded basic device structure + * @cdev: embedded cdev + * @num_users: number of active users of this device + * @c_no_user: completion used when unregistering the device + * @mutex: mutex protecting @num_users and @idr + * @idr: register of user space shared memory objects allocated or + * registered on this device + * @pool: shared memory pool + */ +struct tee_device { + char name[TEE_MAX_DEV_NAME_LEN]; + const struct tee_desc *desc; + int id; + unsigned int flags; + + struct device dev; + struct cdev cdev; + + size_t num_users; + struct completion c_no_users; + struct mutex mutex; /* protects num_users and idr */ + + struct idr idr; + struct tee_shm_pool *pool; +}; + +/** + * struct tee_driver_ops - driver operations vtable + * @get_version: returns version of driver + * @open: called when the device file is opened + * @release: release this open file + * @open_session: open a new session + * @close_session: close a session + * @system_session: declare session as a system session + * @invoke_func: invoke a trusted function + * @cancel_req: request cancel of an ongoing invoke or open + * @supp_recv: called for supplicant to get a command + * @supp_send: called for supplicant to send a response + * @shm_register: register shared memory buffer in TEE + * @shm_unregister: unregister shared memory buffer in TEE + */ +struct tee_driver_ops { + void (*get_version)(struct tee_device *teedev, + struct tee_ioctl_version_data *vers); + int (*open)(struct tee_context *ctx); + void (*release)(struct tee_context *ctx); + int (*open_session)(struct tee_context *ctx, + struct tee_ioctl_open_session_arg *arg, + struct tee_param *param); + int (*close_session)(struct tee_context *ctx, u32 session); + int (*system_session)(struct tee_context *ctx, u32 session); + int (*invoke_func)(struct tee_context *ctx, + struct tee_ioctl_invoke_arg *arg, + struct tee_param *param); + int (*cancel_req)(struct tee_context *ctx, u32 cancel_id, u32 session); + int (*supp_recv)(struct tee_context *ctx, u32 *func, u32 *num_params, + struct tee_param *param); + int (*supp_send)(struct tee_context *ctx, u32 ret, u32 num_params, + struct tee_param *param); + int (*shm_register)(struct tee_context *ctx, struct tee_shm *shm, + struct page **pages, size_t num_pages, + unsigned long start); + int (*shm_unregister)(struct tee_context *ctx, struct tee_shm *shm); +}; + +/** + * struct tee_desc - Describes the TEE driver to the subsystem + * @name: name of driver + * @ops: driver operations vtable + * @owner: module providing the driver + * @flags: Extra properties of driver, defined by TEE_DESC_* below + */ +#define TEE_DESC_PRIVILEGED 0x1 +struct tee_desc { + const char *name; + const struct tee_driver_ops *ops; + struct module *owner; + u32 flags; +}; + +/** + * tee_device_alloc() - Allocate a new struct tee_device instance + * @teedesc: Descriptor for this driver + * @dev: Parent device for this device + * @pool: Shared memory pool, NULL if not used + * @driver_data: Private driver data for this device + * + * Allocates a new struct tee_device instance. The device is + * removed by tee_device_unregister(). + * + * @returns a pointer to a 'struct tee_device' or an ERR_PTR on failure + */ +struct tee_device *tee_device_alloc(const struct tee_desc *teedesc, + struct device *dev, + struct tee_shm_pool *pool, + void *driver_data); + +/** + * tee_device_register() - Registers a TEE device + * @teedev: Device to register + * + * tee_device_unregister() need to be called to remove the @teedev if + * this function fails. + * + * @returns < 0 on failure + */ +int tee_device_register(struct tee_device *teedev); + +/** + * tee_device_unregister() - Removes a TEE device + * @teedev: Device to unregister + * + * This function should be called to remove the @teedev even if + * tee_device_register() hasn't been called yet. Does nothing if + * @teedev is NULL. + */ +void tee_device_unregister(struct tee_device *teedev); + +/** + * tee_session_calc_client_uuid() - Calculates client UUID for session + * @uuid: Resulting UUID + * @connection_method: Connection method for session (TEE_IOCTL_LOGIN_*) + * @connectuon_data: Connection data for opening session + * + * Based on connection method calculates UUIDv5 based client UUID. + * + * For group based logins verifies that calling process has specified + * credentials. + * + * @return < 0 on failure + */ +int tee_session_calc_client_uuid(uuid_t *uuid, u32 connection_method, + const u8 connection_data[TEE_IOCTL_UUID_LEN]); + +/** + * struct tee_shm_pool - shared memory pool + * @ops: operations + * @private_data: private data for the shared memory manager + */ +struct tee_shm_pool { + const struct tee_shm_pool_ops *ops; + void *private_data; +}; + +/** + * struct tee_shm_pool_ops - shared memory pool operations + * @alloc: called when allocating shared memory + * @free: called when freeing shared memory + * @destroy_pool: called when destroying the pool + */ +struct tee_shm_pool_ops { + int (*alloc)(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align); + void (*free)(struct tee_shm_pool *pool, struct tee_shm *shm); + void (*destroy_pool)(struct tee_shm_pool *pool); +}; + +/* + * tee_shm_pool_alloc_res_mem() - Create a shm manager for reserved memory + * @vaddr: Virtual address of start of pool + * @paddr: Physical address of start of pool + * @size: Size in bytes of the pool + * + * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure. + */ +struct tee_shm_pool *tee_shm_pool_alloc_res_mem(unsigned long vaddr, + phys_addr_t paddr, size_t size, + int min_alloc_order); + +/** + * tee_shm_pool_free() - Free a shared memory pool + * @pool: The shared memory pool to free + * + * The must be no remaining shared memory allocated from this pool when + * this function is called. + */ +static inline void tee_shm_pool_free(struct tee_shm_pool *pool) +{ + pool->ops->destroy_pool(pool); +} + +/** + * tee_get_drvdata() - Return driver_data pointer + * @returns the driver_data pointer supplied to tee_register(). + */ +void *tee_get_drvdata(struct tee_device *teedev); + +/** + * tee_shm_alloc_priv_buf() - Allocate shared memory for private use by specific + * TEE driver + * @ctx: The TEE context for shared memory allocation + * @size: Shared memory allocation size + * @returns a pointer to 'struct tee_shm' on success or an ERR_PTR on failure + */ +struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size); + +/** + * tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind + * @shm: Shared memory handle + * @returns true if object is dynamic shared memory + */ +static inline bool tee_shm_is_dynamic(struct tee_shm *shm) +{ + return shm && (shm->flags & TEE_SHM_DYNAMIC); +} + +/** + * tee_shm_put() - Decrease reference count on a shared memory handle + * @shm: Shared memory handle + */ +void tee_shm_put(struct tee_shm *shm); + +/** + * tee_shm_get_id() - Get id of a shared memory object + * @shm: Shared memory handle + * @returns id + */ +static inline int tee_shm_get_id(struct tee_shm *shm) +{ + return shm->id; +} + +/** + * tee_shm_get_from_id() - Find shared memory object and increase reference + * count + * @ctx: Context owning the shared memory + * @id: Id of shared memory object + * @returns a pointer to 'struct tee_shm' on success or an ERR_PTR on failure + */ +struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id); + +static inline bool tee_param_is_memref(struct tee_param *param) +{ + switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: + case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: + return true; + default: + return false; + } +} + +/** + * teedev_open() - Open a struct tee_device + * @teedev: Device to open + * + * @return a pointer to struct tee_context on success or an ERR_PTR on failure. + */ +struct tee_context *teedev_open(struct tee_device *teedev); + +/** + * teedev_close_context() - closes a struct tee_context + * @ctx: The struct tee_context to close + */ +void teedev_close_context(struct tee_context *ctx); + +#endif /*__TEE_CORE_H*/ diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h index 71632e3c5f18..786b9ae6cf4d 100644 --- a/include/linux/tee_drv.h +++ b/include/linux/tee_drv.h @@ -1,40 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2022 Linaro Limited + * Copyright (c) 2015-2024 Linaro Limited */ #ifndef __TEE_DRV_H #define __TEE_DRV_H #include -#include #include #include #include #include #include -#include /* - * The file describes the API provided by the generic TEE driver to the - * specific TEE driver. + * The file describes the API provided by the TEE subsystem to the + * TEE client drivers. */ -#define TEE_SHM_DYNAMIC BIT(0) /* Dynamic shared memory registered */ - /* in secure world */ -#define TEE_SHM_USER_MAPPED BIT(1) /* Memory mapped in user space */ -#define TEE_SHM_POOL BIT(2) /* Memory allocated from pool */ -#define TEE_SHM_PRIV BIT(3) /* Memory private to TEE driver */ - -struct device; struct tee_device; -struct tee_shm; -struct tee_shm_pool; /** * struct tee_context - driver specific context on file pointer data * @teedev: pointer to this drivers struct tee_device - * @list_shm: List of shared memory object owned by this context * @data: driver specific context data, managed by the driver * @refcount: reference counter for this structure * @releasing: flag that indicates if context is being released right now. @@ -57,6 +45,37 @@ struct tee_context { bool cap_memref_null; }; +/** + * struct tee_shm - shared memory object + * @ctx: context using the object + * @paddr: physical address of the shared memory + * @kaddr: virtual address of the shared memory + * @size: size of shared memory + * @offset: offset of buffer in user space + * @pages: locked pages from userspace + * @num_pages: number of locked pages + * @refcount: reference counter + * @flags: defined by TEE_SHM_* in tee_core.h + * @id: unique id of a shared memory object on this device, shared + * with user space + * @sec_world_id: + * secure world assigned id of this shared memory object, not + * used by all drivers + */ +struct tee_shm { + struct tee_context *ctx; + phys_addr_t paddr; + void *kaddr; + size_t size; + unsigned int offset; + struct page **pages; + size_t num_pages; + refcount_t refcount; + u32 flags; + int id; + u64 sec_world_id; +}; + struct tee_param_memref { size_t shm_offs; size_t size; @@ -78,228 +97,31 @@ struct tee_param { }; /** - * struct tee_driver_ops - driver operations vtable - * @get_version: returns version of driver - * @open: called when the device file is opened - * @release: release this open file - * @open_session: open a new session - * @close_session: close a session - * @system_session: declare session as a system session - * @invoke_func: invoke a trusted function - * @cancel_req: request cancel of an ongoing invoke or open - * @supp_recv: called for supplicant to get a command - * @supp_send: called for supplicant to send a response - * @shm_register: register shared memory buffer in TEE - * @shm_unregister: unregister shared memory buffer in TEE + * tee_shm_alloc_kernel_buf() - Allocate kernel shared memory for a + * particular TEE client driver + * @ctx: The TEE context for shared memory allocation + * @size: Shared memory allocation size + * @returns a pointer to 'struct tee_shm' on success or an ERR_PTR on failure */ -struct tee_driver_ops { - void (*get_version)(struct tee_device *teedev, - struct tee_ioctl_version_data *vers); - int (*open)(struct tee_context *ctx); - void (*release)(struct tee_context *ctx); - int (*open_session)(struct tee_context *ctx, - struct tee_ioctl_open_session_arg *arg, - struct tee_param *param); - int (*close_session)(struct tee_context *ctx, u32 session); - int (*system_session)(struct tee_context *ctx, u32 session); - int (*invoke_func)(struct tee_context *ctx, - struct tee_ioctl_invoke_arg *arg, - struct tee_param *param); - int (*cancel_req)(struct tee_context *ctx, u32 cancel_id, u32 session); - int (*supp_recv)(struct tee_context *ctx, u32 *func, u32 *num_params, - struct tee_param *param); - int (*supp_send)(struct tee_context *ctx, u32 ret, u32 num_params, - struct tee_param *param); - int (*shm_register)(struct tee_context *ctx, struct tee_shm *shm, - struct page **pages, size_t num_pages, - unsigned long start); - int (*shm_unregister)(struct tee_context *ctx, struct tee_shm *shm); -}; - -/** - * struct tee_desc - Describes the TEE driver to the subsystem - * @name: name of driver - * @ops: driver operations vtable - * @owner: module providing the driver - * @flags: Extra properties of driver, defined by TEE_DESC_* below - */ -#define TEE_DESC_PRIVILEGED 0x1 -struct tee_desc { - const char *name; - const struct tee_driver_ops *ops; - struct module *owner; - u32 flags; -}; - -/** - * tee_device_alloc() - Allocate a new struct tee_device instance - * @teedesc: Descriptor for this driver - * @dev: Parent device for this device - * @pool: Shared memory pool, NULL if not used - * @driver_data: Private driver data for this device - * - * Allocates a new struct tee_device instance. The device is - * removed by tee_device_unregister(). - * - * @returns a pointer to a 'struct tee_device' or an ERR_PTR on failure - */ -struct tee_device *tee_device_alloc(const struct tee_desc *teedesc, - struct device *dev, - struct tee_shm_pool *pool, - void *driver_data); - -/** - * tee_device_register() - Registers a TEE device - * @teedev: Device to register - * - * tee_device_unregister() need to be called to remove the @teedev if - * this function fails. - * - * @returns < 0 on failure - */ -int tee_device_register(struct tee_device *teedev); - -/** - * tee_device_unregister() - Removes a TEE device - * @teedev: Device to unregister - * - * This function should be called to remove the @teedev even if - * tee_device_register() hasn't been called yet. Does nothing if - * @teedev is NULL. - */ -void tee_device_unregister(struct tee_device *teedev); - -/** - * tee_session_calc_client_uuid() - Calculates client UUID for session - * @uuid: Resulting UUID - * @connection_method: Connection method for session (TEE_IOCTL_LOGIN_*) - * @connectuon_data: Connection data for opening session - * - * Based on connection method calculates UUIDv5 based client UUID. - * - * For group based logins verifies that calling process has specified - * credentials. - * - * @return < 0 on failure - */ -int tee_session_calc_client_uuid(uuid_t *uuid, u32 connection_method, - const u8 connection_data[TEE_IOCTL_UUID_LEN]); - -/** - * struct tee_shm - shared memory object - * @ctx: context using the object - * @paddr: physical address of the shared memory - * @kaddr: virtual address of the shared memory - * @size: size of shared memory - * @offset: offset of buffer in user space - * @pages: locked pages from userspace - * @num_pages: number of locked pages - * @refcount: reference counter - * @flags: defined by TEE_SHM_* in tee_drv.h - * @id: unique id of a shared memory object on this device, shared - * with user space - * @sec_world_id: - * secure world assigned id of this shared memory object, not - * used by all drivers - * - * This pool is only supposed to be accessed directly from the TEE - * subsystem and from drivers that implements their own shm pool manager. - */ -struct tee_shm { - struct tee_context *ctx; - phys_addr_t paddr; - void *kaddr; - size_t size; - unsigned int offset; - struct page **pages; - size_t num_pages; - refcount_t refcount; - u32 flags; - int id; - u64 sec_world_id; -}; - -/** - * struct tee_shm_pool - shared memory pool - * @ops: operations - * @private_data: private data for the shared memory manager - */ -struct tee_shm_pool { - const struct tee_shm_pool_ops *ops; - void *private_data; -}; - -/** - * struct tee_shm_pool_ops - shared memory pool operations - * @alloc: called when allocating shared memory - * @free: called when freeing shared memory - * @destroy_pool: called when destroying the pool - */ -struct tee_shm_pool_ops { - int (*alloc)(struct tee_shm_pool *pool, struct tee_shm *shm, - size_t size, size_t align); - void (*free)(struct tee_shm_pool *pool, struct tee_shm *shm); - void (*destroy_pool)(struct tee_shm_pool *pool); -}; - -/* - * tee_shm_pool_alloc_res_mem() - Create a shm manager for reserved memory - * @vaddr: Virtual address of start of pool - * @paddr: Physical address of start of pool - * @size: Size in bytes of the pool - * - * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure. - */ -struct tee_shm_pool *tee_shm_pool_alloc_res_mem(unsigned long vaddr, - phys_addr_t paddr, size_t size, - int min_alloc_order); - -/** - * tee_shm_pool_free() - Free a shared memory pool - * @pool: The shared memory pool to free - * - * The must be no remaining shared memory allocated from this pool when - * this function is called. - */ -static inline void tee_shm_pool_free(struct tee_shm_pool *pool) -{ - pool->ops->destroy_pool(pool); -} - -/** - * tee_get_drvdata() - Return driver_data pointer - * @returns the driver_data pointer supplied to tee_register(). - */ -void *tee_get_drvdata(struct tee_device *teedev); - -struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size); struct tee_shm *tee_shm_alloc_kernel_buf(struct tee_context *ctx, size_t size); +/** + * tee_shm_register_kernel_buf() - Register kernel shared memory for a + * particular TEE client driver + * @ctx: The TEE context for shared memory registration + * @addr: Kernel buffer address + * @length: Kernel buffer length + * @returns a pointer to 'struct tee_shm' on success or an ERR_PTR on failure + */ struct tee_shm *tee_shm_register_kernel_buf(struct tee_context *ctx, void *addr, size_t length); -/** - * tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind - * @shm: Shared memory handle - * @returns true if object is dynamic shared memory - */ -static inline bool tee_shm_is_dynamic(struct tee_shm *shm) -{ - return shm && (shm->flags & TEE_SHM_DYNAMIC); -} - /** * tee_shm_free() - Free shared memory * @shm: Handle to shared memory to free */ void tee_shm_free(struct tee_shm *shm); -/** - * tee_shm_put() - Decrease reference count on a shared memory handle - * @shm: Shared memory handle - */ -void tee_shm_put(struct tee_shm *shm); - /** * tee_shm_get_va() - Get virtual address of a shared memory plus an offset * @shm: Shared memory handle @@ -352,25 +174,6 @@ static inline size_t tee_shm_get_page_offset(struct tee_shm *shm) return shm->offset; } -/** - * tee_shm_get_id() - Get id of a shared memory object - * @shm: Shared memory handle - * @returns id - */ -static inline int tee_shm_get_id(struct tee_shm *shm) -{ - return shm->id; -} - -/** - * tee_shm_get_from_id() - Find shared memory object and increase reference - * count - * @ctx: Context owning the shared memory - * @id: Id of shared memory object - * @returns a pointer to 'struct tee_shm' on success or an ERR_PTR on failure - */ -struct tee_shm *tee_shm_get_from_id(struct tee_context *ctx, int id); - /** * tee_client_open_context() - Open a TEE context * @start: if not NULL, continue search after this context @@ -470,18 +273,6 @@ int tee_client_invoke_func(struct tee_context *ctx, int tee_client_cancel_req(struct tee_context *ctx, struct tee_ioctl_cancel_arg *arg); -static inline bool tee_param_is_memref(struct tee_param *param) -{ - switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { - case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: - case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: - case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: - return true; - default: - return false; - } -} - extern const struct bus_type tee_bus_type; /** @@ -509,18 +300,4 @@ struct tee_client_driver { #define to_tee_client_driver(d) \ container_of(d, struct tee_client_driver, driver) -/** - * teedev_open() - Open a struct tee_device - * @teedev: Device to open - * - * @return a pointer to struct tee_context on success or an ERR_PTR on failure. - */ -struct tee_context *teedev_open(struct tee_device *teedev); - -/** - * teedev_close_context() - closes a struct tee_context - * @ctx: The struct tee_context to close - */ -void teedev_close_context(struct tee_context *ctx); - #endif /*__TEE_DRV_H*/ From b0c981667564d8e0d1464399fd8a7efbb156dedd Mon Sep 17 00:00:00 2001 From: Arthur Demchenkov Date: Wed, 28 Feb 2024 10:38:47 +0200 Subject: [PATCH 205/969] ARM: dts: n900: set charge current limit to 950mA The vendor kernel used 950mA as the default. The same value works fine on the mainline Linux kernel, and has been tested extensively under Maemo Leste [1] and postmarketOS, who have been using it for a number of years. [1] https://github.com/maemo-leste/n9xx-linux/commit/fbc4ce7a84e59215914a8981afe918002b191493 Signed-off-by: Arthur Demchenkov Signed-off-by: Sicelo A. Mhlongo Message-ID: <20240228083846.2401108-2-absicsz@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/omap3-n900.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/omap3-n900.dts b/arch/arm/boot/dts/ti/omap/omap3-n900.dts index d33485341251..07c5b963af78 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-n900.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-n900.dts @@ -754,7 +754,7 @@ ti,current-limit = <100>; ti,weak-battery-voltage = <3400>; ti,battery-regulation-voltage = <4200>; - ti,charge-current = <650>; + ti,charge-current = <950>; ti,termination-current = <100>; ti,resistor-sense = <68>; From cf4441503e20a0c0a36e0a98dcf57de3d3844c91 Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Mon, 25 Mar 2024 16:11:02 +0100 Subject: [PATCH 206/969] tee: optee: Move pool_op helper functions Move the pool alloc and free helper functions from the OP-TEE driver to the TEE subsystem, since these could be reused in other TEE drivers. This patch is not supposed to change behavior, it's only reorganizing the code. Reviewed-by: Sumit Garg Suggested-by: Jens Wiklander Signed-off-by: Balint Dobszay Signed-off-by: Jens Wiklander --- drivers/tee/optee/core.c | 64 ------------------------------ drivers/tee/optee/ffa_abi.c | 6 +-- drivers/tee/optee/optee_private.h | 12 ------ drivers/tee/optee/smc_abi.c | 9 ++--- drivers/tee/tee_shm.c | 65 +++++++++++++++++++++++++++++++ include/linux/tee_core.h | 10 +++++ 6 files changed, 82 insertions(+), 84 deletions(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index f762e3a25119..39e688d4e974 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -17,69 +16,6 @@ #include #include "optee_private.h" -int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm, - size_t size, size_t align, - int (*shm_register)(struct tee_context *ctx, - struct tee_shm *shm, - struct page **pages, - size_t num_pages, - unsigned long start)) -{ - size_t nr_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE; - struct page **pages; - unsigned int i; - int rc = 0; - - /* - * Ignore alignment since this is already going to be page aligned - * and there's no need for any larger alignment. - */ - shm->kaddr = alloc_pages_exact(nr_pages * PAGE_SIZE, - GFP_KERNEL | __GFP_ZERO); - if (!shm->kaddr) - return -ENOMEM; - - shm->paddr = virt_to_phys(shm->kaddr); - shm->size = nr_pages * PAGE_SIZE; - - pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL); - if (!pages) { - rc = -ENOMEM; - goto err; - } - - for (i = 0; i < nr_pages; i++) - pages[i] = virt_to_page((u8 *)shm->kaddr + i * PAGE_SIZE); - - shm->pages = pages; - shm->num_pages = nr_pages; - - if (shm_register) { - rc = shm_register(shm->ctx, shm, pages, nr_pages, - (unsigned long)shm->kaddr); - if (rc) - goto err; - } - - return 0; -err: - free_pages_exact(shm->kaddr, shm->size); - shm->kaddr = NULL; - return rc; -} - -void optee_pool_op_free_helper(struct tee_shm_pool *pool, struct tee_shm *shm, - int (*shm_unregister)(struct tee_context *ctx, - struct tee_shm *shm)) -{ - if (shm_unregister) - shm_unregister(shm->ctx, shm); - free_pages_exact(shm->kaddr, shm->size); - shm->kaddr = NULL; - kfree(shm->pages); - shm->pages = NULL; -} - static void optee_bus_scan(struct work_struct *work) { WARN_ON(optee_enumerate_devices(PTA_CMD_GET_DEVICES_SUPP)); diff --git a/drivers/tee/optee/ffa_abi.c b/drivers/tee/optee/ffa_abi.c index cee8ccb84cb8..3235e1c719e8 100644 --- a/drivers/tee/optee/ffa_abi.c +++ b/drivers/tee/optee/ffa_abi.c @@ -374,14 +374,14 @@ static int optee_ffa_shm_unregister_supp(struct tee_context *ctx, static int pool_ffa_op_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, size_t size, size_t align) { - return optee_pool_op_alloc_helper(pool, shm, size, align, - optee_ffa_shm_register); + return tee_dyn_shm_alloc_helper(shm, size, align, + optee_ffa_shm_register); } static void pool_ffa_op_free(struct tee_shm_pool *pool, struct tee_shm *shm) { - optee_pool_op_free_helper(pool, shm, optee_ffa_shm_unregister); + tee_dyn_shm_free_helper(shm, optee_ffa_shm_unregister); } static void pool_ffa_op_destroy_pool(struct tee_shm_pool *pool) diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index a0698ac18993..429cc20be5cc 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -283,18 +283,6 @@ int optee_cancel_req(struct tee_context *ctx, u32 cancel_id, u32 session); int optee_enumerate_devices(u32 func); void optee_unregister_devices(void); -int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm, - size_t size, size_t align, - int (*shm_register)(struct tee_context *ctx, - struct tee_shm *shm, - struct page **pages, - size_t num_pages, - unsigned long start)); -void optee_pool_op_free_helper(struct tee_shm_pool *pool, struct tee_shm *shm, - int (*shm_unregister)(struct tee_context *ctx, - struct tee_shm *shm)); - - void optee_remove_common(struct optee *optee); int optee_open(struct tee_context *ctx, bool cap_memref_null); void optee_release(struct tee_context *ctx); diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index 9c296b887dc1..734c484ed0f6 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -592,19 +592,18 @@ static int pool_op_alloc(struct tee_shm_pool *pool, * to be registered with OP-TEE. */ if (shm->flags & TEE_SHM_PRIV) - return optee_pool_op_alloc_helper(pool, shm, size, align, NULL); + return tee_dyn_shm_alloc_helper(shm, size, align, NULL); - return optee_pool_op_alloc_helper(pool, shm, size, align, - optee_shm_register); + return tee_dyn_shm_alloc_helper(shm, size, align, optee_shm_register); } static void pool_op_free(struct tee_shm_pool *pool, struct tee_shm *shm) { if (!(shm->flags & TEE_SHM_PRIV)) - optee_pool_op_free_helper(pool, shm, optee_shm_unregister); + tee_dyn_shm_free_helper(shm, optee_shm_unregister); else - optee_pool_op_free_helper(pool, shm, NULL); + tee_dyn_shm_free_helper(shm, NULL); } static void pool_op_destroy_pool(struct tee_shm_pool *pool) diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c index 96a45c817427..daf6e5cfd59a 100644 --- a/drivers/tee/tee_shm.c +++ b/drivers/tee/tee_shm.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -202,6 +203,70 @@ struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size) } EXPORT_SYMBOL_GPL(tee_shm_alloc_priv_buf); +int tee_dyn_shm_alloc_helper(struct tee_shm *shm, size_t size, size_t align, + int (*shm_register)(struct tee_context *ctx, + struct tee_shm *shm, + struct page **pages, + size_t num_pages, + unsigned long start)) +{ + size_t nr_pages = roundup(size, PAGE_SIZE) / PAGE_SIZE; + struct page **pages; + unsigned int i; + int rc = 0; + + /* + * Ignore alignment since this is already going to be page aligned + * and there's no need for any larger alignment. + */ + shm->kaddr = alloc_pages_exact(nr_pages * PAGE_SIZE, + GFP_KERNEL | __GFP_ZERO); + if (!shm->kaddr) + return -ENOMEM; + + shm->paddr = virt_to_phys(shm->kaddr); + shm->size = nr_pages * PAGE_SIZE; + + pages = kcalloc(nr_pages, sizeof(*pages), GFP_KERNEL); + if (!pages) { + rc = -ENOMEM; + goto err; + } + + for (i = 0; i < nr_pages; i++) + pages[i] = virt_to_page((u8 *)shm->kaddr + i * PAGE_SIZE); + + shm->pages = pages; + shm->num_pages = nr_pages; + + if (shm_register) { + rc = shm_register(shm->ctx, shm, pages, nr_pages, + (unsigned long)shm->kaddr); + if (rc) + goto err; + } + + return 0; +err: + free_pages_exact(shm->kaddr, shm->size); + shm->kaddr = NULL; + return rc; +} +EXPORT_SYMBOL_GPL(tee_dyn_shm_alloc_helper); + +void tee_dyn_shm_free_helper(struct tee_shm *shm, + int (*shm_unregister)(struct tee_context *ctx, + struct tee_shm *shm)) +{ + if (shm_unregister) + shm_unregister(shm->ctx, shm); + free_pages_exact(shm->kaddr, shm->size); + shm->kaddr = NULL; + kfree(shm->pages); + shm->pages = NULL; +} +EXPORT_SYMBOL_GPL(tee_dyn_shm_free_helper); + static struct tee_shm * register_shm_helper(struct tee_context *ctx, struct iov_iter *iter, u32 flags, int id) diff --git a/include/linux/tee_core.h b/include/linux/tee_core.h index d9b3ba8e8fa9..efd16ed52315 100644 --- a/include/linux/tee_core.h +++ b/include/linux/tee_core.h @@ -232,6 +232,16 @@ void *tee_get_drvdata(struct tee_device *teedev); */ struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size); +int tee_dyn_shm_alloc_helper(struct tee_shm *shm, size_t size, size_t align, + int (*shm_register)(struct tee_context *ctx, + struct tee_shm *shm, + struct page **pages, + size_t num_pages, + unsigned long start)); +void tee_dyn_shm_free_helper(struct tee_shm *shm, + int (*shm_unregister)(struct tee_context *ctx, + struct tee_shm *shm)); + /** * tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind * @shm: Shared memory handle From c835e5a3153cae2956efdbb9948b90f2b9e5e64d Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Mon, 25 Mar 2024 16:11:03 +0100 Subject: [PATCH 207/969] tee: tstee: Add Trusted Services TEE driver The Trusted Services project provides a framework for developing and deploying device Root of Trust services in FF-A Secure Partitions. The FF-A SPs are accessible through the FF-A driver, but this doesn't provide a user space interface. The goal of this TEE driver is to make Trusted Services SPs accessible for user space clients. All TS SPs have the same FF-A UUID, it identifies the RPC protocol used by TS. A TS SP can host one or more services, a service is identified by its service UUID. The same type of service cannot be present twice in the same SP. During SP boot each service in an SP is assigned an interface ID, this is just a short ID to simplify message addressing. There is 1:1 mapping between TS SPs and TEE devices, i.e. a separate TEE device is registered for each TS SP. This is required since contrary to the generic TEE design where memory is shared with the whole TEE implementation, in case of FF-A, memory is shared with a specific SP. A user space client has to be able to separately share memory with each SP based on its endpoint ID. Acked-by: Sumit Garg Signed-off-by: Balint Dobszay Signed-off-by: Jens Wiklander --- drivers/tee/Kconfig | 1 + drivers/tee/Makefile | 1 + drivers/tee/tstee/Kconfig | 11 + drivers/tee/tstee/Makefile | 3 + drivers/tee/tstee/core.c | 480 ++++++++++++++++++++++++++++++ drivers/tee/tstee/tstee_private.h | 92 ++++++ include/uapi/linux/tee.h | 1 + 7 files changed, 589 insertions(+) create mode 100644 drivers/tee/tstee/Kconfig create mode 100644 drivers/tee/tstee/Makefile create mode 100644 drivers/tee/tstee/core.c create mode 100644 drivers/tee/tstee/tstee_private.h diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig index 73a147202e88..61b507c18780 100644 --- a/drivers/tee/Kconfig +++ b/drivers/tee/Kconfig @@ -15,5 +15,6 @@ if TEE source "drivers/tee/optee/Kconfig" source "drivers/tee/amdtee/Kconfig" +source "drivers/tee/tstee/Kconfig" endif diff --git a/drivers/tee/Makefile b/drivers/tee/Makefile index 68da044afbfa..5488cba30bd2 100644 --- a/drivers/tee/Makefile +++ b/drivers/tee/Makefile @@ -5,3 +5,4 @@ tee-objs += tee_shm.o tee-objs += tee_shm_pool.o obj-$(CONFIG_OPTEE) += optee/ obj-$(CONFIG_AMDTEE) += amdtee/ +obj-$(CONFIG_ARM_TSTEE) += tstee/ diff --git a/drivers/tee/tstee/Kconfig b/drivers/tee/tstee/Kconfig new file mode 100644 index 000000000000..d32f91d47398 --- /dev/null +++ b/drivers/tee/tstee/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config ARM_TSTEE + tristate "Arm Trusted Services TEE driver" + depends on ARM_FFA_TRANSPORT + default n + help + The Trusted Services project provides a framework for developing and + deploying device Root of Trust services in FF-A Secure Partitions. + This driver provides an interface to make Trusted Services Secure + Partitions accessible for user space clients, since the FF-A driver + doesn't implement a user space interface directly. diff --git a/drivers/tee/tstee/Makefile b/drivers/tee/tstee/Makefile new file mode 100644 index 000000000000..5227020ebd30 --- /dev/null +++ b/drivers/tee/tstee/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +arm-tstee-objs := core.o +obj-$(CONFIG_ARM_TSTEE) = arm-tstee.o diff --git a/drivers/tee/tstee/core.c b/drivers/tee/tstee/core.c new file mode 100644 index 000000000000..533425e9e9e7 --- /dev/null +++ b/drivers/tee/tstee/core.c @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Arm Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tstee_private.h" + +#define FFA_DIRECT_REQ_ARG_NUM 5 +#define FFA_INVALID_MEM_HANDLE U64_MAX + +static void arg_list_to_ffa_data(const u32 *args, + struct ffa_send_direct_data *data) +{ + data->data0 = args[0]; + data->data1 = args[1]; + data->data2 = args[2]; + data->data3 = args[3]; + data->data4 = args[4]; +} + +static void arg_list_from_ffa_data(const struct ffa_send_direct_data *data, + u32 *args) +{ + args[0] = lower_32_bits(data->data0); + args[1] = lower_32_bits(data->data1); + args[2] = lower_32_bits(data->data2); + args[3] = lower_32_bits(data->data3); + args[4] = lower_32_bits(data->data4); +} + +static void tstee_get_version(struct tee_device *teedev, + struct tee_ioctl_version_data *vers) +{ + struct tstee *tstee = tee_get_drvdata(teedev); + struct tee_ioctl_version_data v = { + .impl_id = TEE_IMPL_ID_TSTEE, + /* FF-A endpoint ID only uses the lower 16 bits */ + .impl_caps = lower_16_bits(tstee->ffa_dev->vm_id), + .gen_caps = 0, + }; + + *vers = v; +} + +static int tstee_open(struct tee_context *ctx) +{ + struct ts_context_data *ctxdata; + + ctxdata = kzalloc(sizeof(*ctxdata), GFP_KERNEL); + if (!ctxdata) + return -ENOMEM; + + xa_init_flags(&ctxdata->sess_list, XA_FLAGS_ALLOC); + + ctx->data = ctxdata; + + return 0; +} + +static void tstee_release(struct tee_context *ctx) +{ + struct ts_context_data *ctxdata = ctx->data; + struct ts_session *sess; + unsigned long idx; + + if (!ctxdata) + return; + + xa_for_each(&ctxdata->sess_list, idx, sess) { + xa_erase(&ctxdata->sess_list, idx); + kfree(sess); + } + + xa_destroy(&ctxdata->sess_list); + + kfree(ctxdata); + ctx->data = NULL; +} + +static int tstee_open_session(struct tee_context *ctx, + struct tee_ioctl_open_session_arg *arg, + struct tee_param *param __always_unused) +{ + struct tstee *tstee = tee_get_drvdata(ctx->teedev); + struct ffa_device *ffa_dev = tstee->ffa_dev; + struct ts_context_data *ctxdata = ctx->data; + struct ffa_send_direct_data ffa_data; + struct ts_session *sess = NULL; + u32 ffa_args[FFA_DIRECT_REQ_ARG_NUM] = {}; + u32 sess_id; + int rc; + + ffa_args[TS_RPC_CTRL_REG] = + TS_RPC_CTRL_PACK_IFACE_OPCODE(TS_RPC_MGMT_IFACE_ID, + TS_RPC_OP_SERVICE_INFO); + + memcpy(ffa_args + TS_RPC_SERVICE_INFO_UUID0, arg->uuid, UUID_SIZE); + + arg_list_to_ffa_data(ffa_args, &ffa_data); + rc = ffa_dev->ops->msg_ops->sync_send_receive(ffa_dev, &ffa_data); + if (rc) + return rc; + + arg_list_from_ffa_data(&ffa_data, ffa_args); + + if (ffa_args[TS_RPC_SERVICE_INFO_RPC_STATUS] != TS_RPC_OK) + return -ENODEV; + + if (ffa_args[TS_RPC_SERVICE_INFO_IFACE] > U8_MAX) + return -EINVAL; + + sess = kzalloc(sizeof(*sess), GFP_KERNEL); + if (!sess) + return -ENOMEM; + + sess->iface_id = ffa_args[TS_RPC_SERVICE_INFO_IFACE]; + + rc = xa_alloc(&ctxdata->sess_list, &sess_id, sess, xa_limit_32b, + GFP_KERNEL); + if (rc) { + kfree(sess); + return rc; + } + + arg->session = sess_id; + arg->ret = 0; + + return 0; +} + +static int tstee_close_session(struct tee_context *ctx, u32 session) +{ + struct ts_context_data *ctxdata = ctx->data; + struct ts_session *sess; + + /* Calls xa_lock() internally */ + sess = xa_erase(&ctxdata->sess_list, session); + if (!sess) + return -EINVAL; + + kfree(sess); + + return 0; +} + +static int tstee_invoke_func(struct tee_context *ctx, + struct tee_ioctl_invoke_arg *arg, + struct tee_param *param) +{ + struct tstee *tstee = tee_get_drvdata(ctx->teedev); + struct ffa_device *ffa_dev = tstee->ffa_dev; + struct ts_context_data *ctxdata = ctx->data; + struct ffa_send_direct_data ffa_data; + struct tee_shm *shm = NULL; + struct ts_session *sess; + u32 req_len, ffa_args[FFA_DIRECT_REQ_ARG_NUM] = {}; + int shm_id, rc; + u8 iface_id; + u64 handle; + u16 opcode; + + xa_lock(&ctxdata->sess_list); + sess = xa_load(&ctxdata->sess_list, arg->session); + + /* + * Do this while holding the lock to make sure that the session wasn't + * closed meanwhile + */ + if (sess) + iface_id = sess->iface_id; + + xa_unlock(&ctxdata->sess_list); + if (!sess) + return -EINVAL; + + opcode = lower_16_bits(arg->func); + shm_id = lower_32_bits(param[0].u.value.a); + req_len = lower_32_bits(param[0].u.value.b); + + if (shm_id != 0) { + shm = tee_shm_get_from_id(ctx, shm_id); + if (IS_ERR(shm)) + return PTR_ERR(shm); + + if (shm->size < req_len) { + dev_err(&ffa_dev->dev, + "request doesn't fit into shared memory buffer\n"); + rc = -EINVAL; + goto out; + } + + handle = shm->sec_world_id; + } else { + handle = FFA_INVALID_MEM_HANDLE; + } + + ffa_args[TS_RPC_CTRL_REG] = TS_RPC_CTRL_PACK_IFACE_OPCODE(iface_id, + opcode); + ffa_args[TS_RPC_SERVICE_MEM_HANDLE_LSW] = lower_32_bits(handle); + ffa_args[TS_RPC_SERVICE_MEM_HANDLE_MSW] = upper_32_bits(handle); + ffa_args[TS_RPC_SERVICE_REQ_LEN] = req_len; + ffa_args[TS_RPC_SERVICE_CLIENT_ID] = 0; + + arg_list_to_ffa_data(ffa_args, &ffa_data); + rc = ffa_dev->ops->msg_ops->sync_send_receive(ffa_dev, &ffa_data); + if (rc) + goto out; + + arg_list_from_ffa_data(&ffa_data, ffa_args); + + if (ffa_args[TS_RPC_SERVICE_RPC_STATUS] != TS_RPC_OK) { + dev_err(&ffa_dev->dev, "invoke_func rpc status: %d\n", + ffa_args[TS_RPC_SERVICE_RPC_STATUS]); + rc = -EINVAL; + goto out; + } + + arg->ret = ffa_args[TS_RPC_SERVICE_STATUS]; + if (shm && shm->size >= ffa_args[TS_RPC_SERVICE_RESP_LEN]) + param[0].u.value.a = ffa_args[TS_RPC_SERVICE_RESP_LEN]; + +out: + if (shm) + tee_shm_put(shm); + + return rc; +} + +static int tstee_shm_register(struct tee_context *ctx, struct tee_shm *shm, + struct page **pages, size_t num_pages, + unsigned long start __always_unused) +{ + struct tstee *tstee = tee_get_drvdata(ctx->teedev); + struct ffa_device *ffa_dev = tstee->ffa_dev; + struct ffa_mem_region_attributes mem_attr = { + .receiver = tstee->ffa_dev->vm_id, + .attrs = FFA_MEM_RW, + .flag = 0, + }; + struct ffa_mem_ops_args mem_args = { + .attrs = &mem_attr, + .use_txbuf = true, + .nattrs = 1, + .flags = 0, + }; + struct ffa_send_direct_data ffa_data; + struct sg_table sgt; + u32 ffa_args[FFA_DIRECT_REQ_ARG_NUM] = {}; + int rc; + + rc = sg_alloc_table_from_pages(&sgt, pages, num_pages, 0, + num_pages * PAGE_SIZE, GFP_KERNEL); + if (rc) + return rc; + + mem_args.sg = sgt.sgl; + rc = ffa_dev->ops->mem_ops->memory_share(&mem_args); + sg_free_table(&sgt); + if (rc) + return rc; + + shm->sec_world_id = mem_args.g_handle; + + ffa_args[TS_RPC_CTRL_REG] = + TS_RPC_CTRL_PACK_IFACE_OPCODE(TS_RPC_MGMT_IFACE_ID, + TS_RPC_OP_RETRIEVE_MEM); + ffa_args[TS_RPC_RETRIEVE_MEM_HANDLE_LSW] = + lower_32_bits(shm->sec_world_id); + ffa_args[TS_RPC_RETRIEVE_MEM_HANDLE_MSW] = + upper_32_bits(shm->sec_world_id); + ffa_args[TS_RPC_RETRIEVE_MEM_TAG_LSW] = 0; + ffa_args[TS_RPC_RETRIEVE_MEM_TAG_MSW] = 0; + + arg_list_to_ffa_data(ffa_args, &ffa_data); + rc = ffa_dev->ops->msg_ops->sync_send_receive(ffa_dev, &ffa_data); + if (rc) { + (void)ffa_dev->ops->mem_ops->memory_reclaim(shm->sec_world_id, + 0); + return rc; + } + + arg_list_from_ffa_data(&ffa_data, ffa_args); + + if (ffa_args[TS_RPC_RETRIEVE_MEM_RPC_STATUS] != TS_RPC_OK) { + dev_err(&ffa_dev->dev, "shm_register rpc status: %d\n", + ffa_args[TS_RPC_RETRIEVE_MEM_RPC_STATUS]); + ffa_dev->ops->mem_ops->memory_reclaim(shm->sec_world_id, 0); + return -EINVAL; + } + + return 0; +} + +static int tstee_shm_unregister(struct tee_context *ctx, struct tee_shm *shm) +{ + struct tstee *tstee = tee_get_drvdata(ctx->teedev); + struct ffa_device *ffa_dev = tstee->ffa_dev; + struct ffa_send_direct_data ffa_data; + u32 ffa_args[FFA_DIRECT_REQ_ARG_NUM] = {}; + int rc; + + ffa_args[TS_RPC_CTRL_REG] = + TS_RPC_CTRL_PACK_IFACE_OPCODE(TS_RPC_MGMT_IFACE_ID, + TS_RPC_OP_RELINQ_MEM); + ffa_args[TS_RPC_RELINQ_MEM_HANDLE_LSW] = + lower_32_bits(shm->sec_world_id); + ffa_args[TS_RPC_RELINQ_MEM_HANDLE_MSW] = + upper_32_bits(shm->sec_world_id); + + arg_list_to_ffa_data(ffa_args, &ffa_data); + rc = ffa_dev->ops->msg_ops->sync_send_receive(ffa_dev, &ffa_data); + if (rc) + return rc; + arg_list_from_ffa_data(&ffa_data, ffa_args); + + if (ffa_args[TS_RPC_RELINQ_MEM_RPC_STATUS] != TS_RPC_OK) { + dev_err(&ffa_dev->dev, "shm_unregister rpc status: %d\n", + ffa_args[TS_RPC_RELINQ_MEM_RPC_STATUS]); + return -EINVAL; + } + + rc = ffa_dev->ops->mem_ops->memory_reclaim(shm->sec_world_id, 0); + + return rc; +} + +static const struct tee_driver_ops tstee_ops = { + .get_version = tstee_get_version, + .open = tstee_open, + .release = tstee_release, + .open_session = tstee_open_session, + .close_session = tstee_close_session, + .invoke_func = tstee_invoke_func, +}; + +static const struct tee_desc tstee_desc = { + .name = "tstee-clnt", + .ops = &tstee_ops, + .owner = THIS_MODULE, +}; + +static int pool_op_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align) +{ + return tee_dyn_shm_alloc_helper(shm, size, align, tstee_shm_register); +} + +static void pool_op_free(struct tee_shm_pool *pool, struct tee_shm *shm) +{ + tee_dyn_shm_free_helper(shm, tstee_shm_unregister); +} + +static void pool_op_destroy_pool(struct tee_shm_pool *pool) +{ + kfree(pool); +} + +static const struct tee_shm_pool_ops pool_ops = { + .alloc = pool_op_alloc, + .free = pool_op_free, + .destroy_pool = pool_op_destroy_pool, +}; + +static struct tee_shm_pool *tstee_create_shm_pool(void) +{ + struct tee_shm_pool *pool = kzalloc(sizeof(*pool), GFP_KERNEL); + + if (!pool) + return ERR_PTR(-ENOMEM); + + pool->ops = &pool_ops; + + return pool; +} + +static bool tstee_check_rpc_compatible(struct ffa_device *ffa_dev) +{ + struct ffa_send_direct_data ffa_data; + u32 ffa_args[FFA_DIRECT_REQ_ARG_NUM] = {}; + + ffa_args[TS_RPC_CTRL_REG] = + TS_RPC_CTRL_PACK_IFACE_OPCODE(TS_RPC_MGMT_IFACE_ID, + TS_RPC_OP_GET_VERSION); + + arg_list_to_ffa_data(ffa_args, &ffa_data); + if (ffa_dev->ops->msg_ops->sync_send_receive(ffa_dev, &ffa_data)) + return false; + + arg_list_from_ffa_data(&ffa_data, ffa_args); + + return ffa_args[TS_RPC_GET_VERSION_RESP] == TS_RPC_PROTOCOL_VERSION; +} + +static int tstee_probe(struct ffa_device *ffa_dev) +{ + struct tstee *tstee; + int rc; + + ffa_dev->ops->msg_ops->mode_32bit_set(ffa_dev); + + if (!tstee_check_rpc_compatible(ffa_dev)) + return -EINVAL; + + tstee = kzalloc(sizeof(*tstee), GFP_KERNEL); + if (!tstee) + return -ENOMEM; + + tstee->ffa_dev = ffa_dev; + + tstee->pool = tstee_create_shm_pool(); + if (IS_ERR(tstee->pool)) { + rc = PTR_ERR(tstee->pool); + tstee->pool = NULL; + goto err_free_tstee; + } + + tstee->teedev = tee_device_alloc(&tstee_desc, NULL, tstee->pool, tstee); + if (IS_ERR(tstee->teedev)) { + rc = PTR_ERR(tstee->teedev); + tstee->teedev = NULL; + goto err_free_pool; + } + + rc = tee_device_register(tstee->teedev); + if (rc) + goto err_unreg_teedev; + + ffa_dev_set_drvdata(ffa_dev, tstee); + + return 0; + +err_unreg_teedev: + tee_device_unregister(tstee->teedev); +err_free_pool: + tee_shm_pool_free(tstee->pool); +err_free_tstee: + kfree(tstee); + return rc; +} + +static void tstee_remove(struct ffa_device *ffa_dev) +{ + struct tstee *tstee = ffa_dev->dev.driver_data; + + tee_device_unregister(tstee->teedev); + tee_shm_pool_free(tstee->pool); + kfree(tstee); +} + +static const struct ffa_device_id tstee_device_ids[] = { + /* TS RPC protocol UUID: bdcd76d7-825e-4751-963b-86d4f84943ac */ + { TS_RPC_UUID }, + {} +}; + +static struct ffa_driver tstee_driver = { + .name = "arm_tstee", + .probe = tstee_probe, + .remove = tstee_remove, + .id_table = tstee_device_ids, +}; + +module_ffa_driver(tstee_driver); + +MODULE_AUTHOR("Balint Dobszay "); +MODULE_DESCRIPTION("Arm Trusted Services TEE driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/tee/tstee/tstee_private.h b/drivers/tee/tstee/tstee_private.h new file mode 100644 index 000000000000..8e58725b57eb --- /dev/null +++ b/drivers/tee/tstee/tstee_private.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Arm Limited + */ + +#ifndef TSTEE_PRIVATE_H +#define TSTEE_PRIVATE_H + +#include +#include +#include +#include +#include +#include + +/* + * The description of the ABI implemented in this file is available at + * https://trusted-services.readthedocs.io/en/v1.0.0/developer/service-access-protocols.html#abi + */ + +/* UUID of this protocol */ +#define TS_RPC_UUID UUID_INIT(0xbdcd76d7, 0x825e, 0x4751, \ + 0x96, 0x3b, 0x86, 0xd4, 0xf8, 0x49, 0x43, 0xac) + +/* Protocol version*/ +#define TS_RPC_PROTOCOL_VERSION (1) + +/* Status codes */ +#define TS_RPC_OK (0) + +/* RPC control register */ +#define TS_RPC_CTRL_REG (0) +#define OPCODE_MASK GENMASK(15, 0) +#define IFACE_ID_MASK GENMASK(23, 16) +#define TS_RPC_CTRL_OPCODE(x) ((u16)(FIELD_GET(OPCODE_MASK, (x)))) +#define TS_RPC_CTRL_IFACE_ID(x) ((u8)(FIELD_GET(IFACE_ID_MASK, (x)))) +#define TS_RPC_CTRL_PACK_IFACE_OPCODE(i, o) \ + (FIELD_PREP(IFACE_ID_MASK, (i)) | FIELD_PREP(OPCODE_MASK, (o))) +#define TS_RPC_CTRL_SAP_RC BIT(30) +#define TS_RPC_CTRL_SAP_ERR BIT(31) + +/* Interface ID for RPC management operations */ +#define TS_RPC_MGMT_IFACE_ID (0xff) + +/* Management calls */ +#define TS_RPC_OP_GET_VERSION (0x0000) +#define TS_RPC_GET_VERSION_RESP (1) + +#define TS_RPC_OP_RETRIEVE_MEM (0x0001) +#define TS_RPC_RETRIEVE_MEM_HANDLE_LSW (1) +#define TS_RPC_RETRIEVE_MEM_HANDLE_MSW (2) +#define TS_RPC_RETRIEVE_MEM_TAG_LSW (3) +#define TS_RPC_RETRIEVE_MEM_TAG_MSW (4) +#define TS_RPC_RETRIEVE_MEM_RPC_STATUS (1) + +#define TS_RPC_OP_RELINQ_MEM (0x0002) +#define TS_RPC_RELINQ_MEM_HANDLE_LSW (1) +#define TS_RPC_RELINQ_MEM_HANDLE_MSW (2) +#define TS_RPC_RELINQ_MEM_RPC_STATUS (1) + +#define TS_RPC_OP_SERVICE_INFO (0x0003) +#define TS_RPC_SERVICE_INFO_UUID0 (1) +#define TS_RPC_SERVICE_INFO_UUID1 (2) +#define TS_RPC_SERVICE_INFO_UUID2 (3) +#define TS_RPC_SERVICE_INFO_UUID3 (4) +#define TS_RPC_SERVICE_INFO_RPC_STATUS (1) +#define TS_RPC_SERVICE_INFO_IFACE (2) + +/* Service call */ +#define TS_RPC_SERVICE_MEM_HANDLE_LSW (1) +#define TS_RPC_SERVICE_MEM_HANDLE_MSW (2) +#define TS_RPC_SERVICE_REQ_LEN (3) +#define TS_RPC_SERVICE_CLIENT_ID (4) +#define TS_RPC_SERVICE_RPC_STATUS (1) +#define TS_RPC_SERVICE_STATUS (2) +#define TS_RPC_SERVICE_RESP_LEN (3) + +struct tstee { + struct ffa_device *ffa_dev; + struct tee_device *teedev; + struct tee_shm_pool *pool; +}; + +struct ts_session { + u8 iface_id; +}; + +struct ts_context_data { + struct xarray sess_list; +}; + +#endif /* TSTEE_PRIVATE_H */ diff --git a/include/uapi/linux/tee.h b/include/uapi/linux/tee.h index 23e57164693c..d0430bee8292 100644 --- a/include/uapi/linux/tee.h +++ b/include/uapi/linux/tee.h @@ -56,6 +56,7 @@ */ #define TEE_IMPL_ID_OPTEE 1 #define TEE_IMPL_ID_AMDTEE 2 +#define TEE_IMPL_ID_TSTEE 3 /* * OP-TEE specific capabilities From 3912b1f576b10093d6cd50bf8b4c3404c6c132ec Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Mon, 25 Mar 2024 16:11:04 +0100 Subject: [PATCH 208/969] Documentation: tee: Add TS-TEE driver Add documentation for the Trusted Services TEE driver. Acked-by: Sumit Garg Signed-off-by: Balint Dobszay Signed-off-by: Jens Wiklander --- Documentation/tee/index.rst | 1 + Documentation/tee/ts-tee.rst | 71 ++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 Documentation/tee/ts-tee.rst diff --git a/Documentation/tee/index.rst b/Documentation/tee/index.rst index a23bd08847e5..4be6e69d7837 100644 --- a/Documentation/tee/index.rst +++ b/Documentation/tee/index.rst @@ -10,6 +10,7 @@ TEE Subsystem tee op-tee amd-tee + ts-tee .. only:: subproject and html diff --git a/Documentation/tee/ts-tee.rst b/Documentation/tee/ts-tee.rst new file mode 100644 index 000000000000..843e34422648 --- /dev/null +++ b/Documentation/tee/ts-tee.rst @@ -0,0 +1,71 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================================= +TS-TEE (Trusted Services project) +================================= + +This driver provides access to secure services implemented by Trusted Services. + +Trusted Services [1] is a TrustedFirmware.org project that provides a framework +for developing and deploying device Root of Trust services in FF-A [2] S-EL0 +Secure Partitions. The project hosts the reference implementation of the Arm +Platform Security Architecture [3] for Arm A-profile devices. + +The FF-A Secure Partitions (SP) are accessible through the FF-A driver [4] which +provides the low level communication for this driver. On top of that the Trusted +Services RPC protocol is used [5]. To use the driver from user space a reference +implementation is provided at [6], which is part of the Trusted Services client +library called libts [7]. + +All Trusted Services (TS) SPs have the same FF-A UUID; it identifies the TS RPC +protocol. A TS SP can host one or more services (e.g. PSA Crypto, PSA ITS, etc). +A service is identified by its service UUID; the same type of service cannot be +present twice in the same SP. During SP boot each service in the SP is assigned +an "interface ID". This is just a short ID to simplify message addressing. + +The generic TEE design is to share memory at once with the Trusted OS, which can +then be reused to communicate with multiple applications running on the Trusted +OS. However, in case of FF-A, memory sharing works on an endpoint level, i.e. +memory is shared with a specific SP. User space has to be able to separately +share memory with each SP based on its endpoint ID; therefore a separate TEE +device is registered for each discovered TS SP. Opening the SP corresponds to +opening the TEE device and creating a TEE context. A TS SP hosts one or more +services. Opening a service corresponds to opening a session in the given +tee_context. + +Overview of a system with Trusted Services components:: + + User space Kernel space Secure world + ~~~~~~~~~~ ~~~~~~~~~~~~ ~~~~~~~~~~~~ + +--------+ +-------------+ + | Client | | Trusted | + +--------+ | Services SP | + /\ +-------------+ + || /\ + || || + || || + \/ \/ + +-------+ +----------+--------+ +-------------+ + | libts | | TEE | TS-TEE | | FF-A SPMC | + | | | subsys | driver | | + SPMD | + +-------+----------------+----+-----+--------+-----------+-------------+ + | Generic TEE API | | FF-A | TS RPC protocol | + | IOCTL (TEE_IOC_*) | | driver | over FF-A | + +-----------------------------+ +--------+-------------------------+ + +References +========== + +[1] https://www.trustedfirmware.org/projects/trusted-services/ + +[2] https://developer.arm.com/documentation/den0077/ + +[3] https://www.arm.com/architecture/security-features/platform-security + +[4] drivers/firmware/arm_ffa/ + +[5] https://trusted-services.readthedocs.io/en/v1.0.0/developer/service-access-protocols.html#abi + +[6] https://git.trustedfirmware.org/TS/trusted-services.git/tree/components/rpc/ts_rpc/caller/linux/ts_rpc_caller_linux.c?h=v1.0.0 + +[7] https://git.trustedfirmware.org/TS/trusted-services.git/tree/deployments/libts/arm-linux/CMakeLists.txt?h=v1.0.0 From 31611cc8faa082a96009c29822d9906d893cce57 Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Mon, 25 Mar 2024 16:11:05 +0100 Subject: [PATCH 209/969] MAINTAINERS: tee: tstee: Add entry Create an entry for the newly added Trusted Services TEE driver, with Sudeep and myself as maintainers. Signed-off-by: Balint Dobszay Reviewed-by: Sumit Garg Acked-by: Sudeep Holla Signed-off-by: Jens Wiklander --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fd221a7d4d1c..eaa89feabd25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22470,6 +22470,15 @@ F: Documentation/ABI/testing/configfs-tsm F: drivers/virt/coco/tsm.c F: include/linux/tsm.h +TRUSTED SERVICES TEE DRIVER +M: Balint Dobszay +M: Sudeep Holla +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: trusted-services@lists.trustedfirmware.org +S: Maintained +F: Documentation/tee/ts-tee.rst +F: drivers/tee/tstee/ + TTY LAYER AND SERIAL DRIVERS M: Greg Kroah-Hartman M: Jiri Slaby From e478c5fb6aa10af7b7edbff69bc8aef6fbb5f0ed Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 20 Nov 2023 19:56:23 +0100 Subject: [PATCH 210/969] firmware: qcom: qcm: fix unused qcom_scm_qseecom_allowlist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For !OF builds, the qcom_scm_qseecom_allowlist is unused: drivers/firmware/qcom/qcom_scm.c:1652:34: error: ‘qcom_scm_qseecom_allowlist’ defined but not used [-Werror=unused-const-variable=] Fixes: 00b1248606ba ("firmware: qcom_scm: Add support for Qualcomm Secure Execution Environment SCM interface") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202311191654.S4wlVUrz-lkp@intel.com/ Signed-off-by: Krzysztof Kozlowski Acked-by: Maximilian Luz Link: https://lore.kernel.org/r/20231120185623.338608-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 49ddbcab0680..81c15aeff934 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1652,7 +1652,7 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_send); * We do not yet support re-entrant calls via the qseecom interface. To prevent + any potential issues with this, only allow validated machines for now. */ -static const struct of_device_id qcom_scm_qseecom_allowlist[] = { +static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "lenovo,thinkpad-x13s", }, { } }; From 7b3ecb64f9ae7ceb0fe0a0cafc3eb2a91326c054 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 25 Mar 2024 09:57:56 +0100 Subject: [PATCH 211/969] arm64: defconfig: build ath12k as a module Qualcomm sm8550-qrd and sm8650-qrd boards have ath12k modules as part of their on-board WCN7850 WLAN/BT packages. Enable the relevant driver in defconfig. Signed-off-by: Bartosz Golaszewski Acked-by: Arnd Bergmann Reviewed-by: Neil Armstrong Reviewed-by: Jeff Johnson Link: https://lore.kernel.org/r/20240325085756.13843-1-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index a25a28e6117b..546af6b8ce2c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -411,6 +411,7 @@ CONFIG_WCN36XX=m CONFIG_ATH11K=m CONFIG_ATH11K_AHB=m CONFIG_ATH11K_PCI=m +CONFIG_ATH12K=m CONFIG_BRCMFMAC=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m From cb06e2b406279f65890233af103c638d3752d328 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 13 Mar 2024 03:32:09 +0200 Subject: [PATCH 212/969] arm64: dts: qcom: sm8350: Add interconnects to UFS To ensure that UFS doesn't get disconnected from NoC, add interconnect properties to the UFS controller. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240313-sm8350-ufs-icc-v1-1-73fa2da99779@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a5e7dbbd8c6c..a878f5ac5bb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1730,6 +1731,11 @@ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; freq-table-hz = <75000000 300000000>, <0 0>, From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Owoc?= Date: Wed, 13 Mar 2024 11:27:06 +0100 Subject: [PATCH 213/969] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gpio16 will only be used for LCD support, as its NAND/LCDC data[8] so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8 or 16-bit with only 8-bit one being supported in our case so that pin is unused. It should be dropped from the default NAND pinctrl configuration as its unused and only needed for LCD. Signed-off-by: Paweł Owoc Reviewed-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 7e4e6a5a02d5..bed405559866 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -356,7 +356,7 @@ "gpio5", "gpio6", "gpio7", "gpio8", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17"; + "gpio15", "gpio17"; function = "qpic"; drive-strength = <8>; bias-disable; From dfd5ee7b34bb7611d4d2f4f3cb37152baeaae96d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 13 Mar 2024 13:53:15 +0100 Subject: [PATCH 214/969] arm64: dts: qcom: sc7280: Add inline crypto engine Add the ICE found on sc7280 and link it to the UFS node. For reference: [ 0.261424] qcom-ice 1d88000.crypto: Found QC Inline Crypto Engine (ICE) v3.2.0 Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240313-sc7280-ice-v1-2-3fa089fb7a27@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7e7f0f0fb41b..6518c9c3a07f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2352,6 +2352,8 @@ <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -2374,6 +2376,13 @@ status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sc7280-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From 88d0e4e10d77bb4e575b74ac0f6dd3140ecc3bcd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 14 Mar 2024 03:42:48 +0200 Subject: [PATCH 215/969] dt-bindings: arm: qcom: drop dtbTool-specific compatibles Drop two board compatibles that were used by the skales dtbTool to index device tree blobs. It was required to boot those devices with the original bootloader, however all users should have switched to the lk2nd bootloader by now. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240314-msm8916-drop-compats-v2-1-5a4b40f832d3@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 66beaac60e1d..66c98a1c8ac6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -187,11 +187,6 @@ properties: - const: qcom,msm8974pro - const: qcom,msm8974 - - items: - - const: qcom,msm8916-mtp - - const: qcom,msm8916-mtp/1 - - const: qcom,msm8916 - - items: - enum: - acer,a1-724 @@ -200,6 +195,8 @@ properties: - gplus,fl8005a - huawei,g7 - longcheer,l8910 + - longcheer,l8150 + - qcom,msm8916-mtp - samsung,a3u-eur - samsung,a5u-eur - samsung,e5 @@ -220,11 +217,6 @@ properties: - yiming,uz801-v3 - const: qcom,msm8916 - - items: - - const: longcheer,l8150 - - const: qcom,msm8916-v1-qrd/9-v1 - - const: qcom,msm8916 - - items: - enum: - motorola,potter From 3867ad6d39cd97875aca7e5f1b17ea6dd5b1107a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 14 Mar 2024 03:42:49 +0200 Subject: [PATCH 216/969] arm64: dts: qcom: msm8916: drop dtbTool-specific compatibles Drop two board compatibles that were used by the skales dtbTool to index device tree blobs. It was required to boot those devices with the original bootloader, however all users should have switched to the lk2nd bootloader by now. Suggested-by: Stephan Gerhold Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240314-msm8916-drop-compats-v2-2-5a4b40f832d3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 3a3e794c022f..7f0c2c1b8a94 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -12,7 +12,7 @@ / { model = "Longcheer L8150"; - compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916"; + compatible = "longcheer,l8150", "qcom,msm8916"; chassis-type = "handset"; aliases { diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index ac527a3a0826..c11a845e91bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916"; chassis-type = "handset"; aliases { From 9f42f7380f6757ce7f0cab5bad56fb350941d32b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 14 Mar 2024 09:53:06 +0100 Subject: [PATCH 217/969] arm64: dts: qcom: sm8650: fix usb interrupts properties Update the usb interrupts properties to fix the following bindings check errors: usb@a6f8800: interrupt-names:0: 'pwr_event' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:1: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:2: 'dp_hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:3: 'dm_hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names: ['hs_phy_irq', 'ss_phy_irq', 'dm_hs_phy_irq', 'dp_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# Cc: Krishna Kurapati Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240314-topic-sm8650-upstream-usb-dt-irq-fix-v1-1-ea8ab2051869@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 32c0a7b9aded..fc057ea41d56 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3584,14 +3584,16 @@ compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, From 216e62744b91c9716228fe13f564e83381a1342e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 14 Mar 2024 12:26:57 +0100 Subject: [PATCH 218/969] arm64: dts: qcom: apq8016-sbc: correct GPIO LEDs node names Individual LEDs in a GPIO LEDs device node are not addressable, thus unit address is not correct. dtc is also not happy: Warning (unit_address_vs_reg): /leds/led@5: node has a unit name, but no reg or ranges property Reported-by: Sumit Garg Closes: https://lore.kernel.org/all/CAFA6WYNRwF7GqhBk2B7i-deT3aLxNQckhnOasjip2TYm4HZgAw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240314112657.167006-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 9ffad7d1f2b6..aba08424aa38 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -91,7 +91,7 @@ compatible = "gpio-leds"; - led@1 { + led-1 { label = "apq8016-sbc:green:user1"; function = LED_FUNCTION_HEARTBEAT; color = ; @@ -100,7 +100,7 @@ default-state = "off"; }; - led@2 { + led-2 { label = "apq8016-sbc:green:user2"; function = LED_FUNCTION_DISK_ACTIVITY; color = ; @@ -109,7 +109,7 @@ default-state = "off"; }; - led@3 { + led-3 { label = "apq8016-sbc:green:user3"; function = LED_FUNCTION_DISK_ACTIVITY; color = ; @@ -118,7 +118,7 @@ default-state = "off"; }; - led@4 { + led-4 { label = "apq8016-sbc:green:user4"; color = ; gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; @@ -127,7 +127,7 @@ default-state = "off"; }; - led@5 { + led-5 { label = "apq8016-sbc:yellow:wlan"; function = LED_FUNCTION_WLAN; color = ; @@ -136,7 +136,7 @@ default-state = "off"; }; - led@6 { + led-6 { label = "apq8016-sbc:blue:bt"; function = LED_FUNCTION_BLUETOOTH; color = ; From d2209f6730051cf9caec1877699329a9c0cd6ac6 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 14 Mar 2024 19:56:23 +0100 Subject: [PATCH 219/969] dt-bindings: arm: qcom: Add Sony Xperia Z3 Add the compatible for this Sony smartphone. Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240314-shinano-common-v2-2-a0fce1c72c74@z3ntu.xyz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 66c98a1c8ac6..1646e5bd23d8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -184,6 +184,7 @@ properties: - oneplus,bacon - samsung,klte - sony,xperia-castor + - sony,xperia-leo - const: qcom,msm8974pro - const: qcom,msm8974 From 0fba148c3ac0fb8bc3d2a788c19b2ede4e5d3695 Mon Sep 17 00:00:00 2001 From: Sebastian Raase Date: Fri, 15 Mar 2024 09:59:25 +0100 Subject: [PATCH 220/969] arm64: dts: qcom: sdm630-nile: add pinctrl for camera key Add pinctrl configuration for gpio-keys. Without this, camera button half-presses are not detected. Tested on discovery and pioneer. Fixes: e781633b6067 ("arm64: dts: qcom: Add support for Sony Xperia XA2/Plus/Ultra (Nile platform)") Signed-off-by: Sebastian Raase Link: https://lore.kernel.org/r/20240315085934.1511722-1-linux@sraa.de Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 819a5f8825e7..a4b722e0fc1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -90,6 +90,8 @@ gpio-keys { compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; key-camera-focus { label = "Camera Focus"; @@ -645,6 +647,13 @@ bias-disable; }; + gpio_keys_default: gpio-keys-default-state { + pins = "gpio64", "gpio113"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + imx300_vana_default: imx300-vana-default-state { pins = "gpio50"; function = "gpio"; From 83ef6a5afc1d5e2270797a164972a3de3bd2ea52 Mon Sep 17 00:00:00 2001 From: Sebastian Raase Date: Fri, 15 Mar 2024 23:52:29 +0100 Subject: [PATCH 221/969] arm64: dts: qcom: msm8998-yoshino: fix volume-up key The volume-up key is connected to gpio6 on yoshino. Fix button node ordering while at it. Disable pm8998_resin, since it is now unused. Tested on maple and lilac. Fixes: 390883af89d2e ("arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform") Signed-off-by: Sebastian Raase Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240315225237.1616550-1-linux@sraa.de Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 44 +++++++++++-------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 876c6921ddf0..fdd3953938d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -98,30 +98,35 @@ gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &vol_up_n>; pinctrl-names = "default"; - pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>; - button-vol-down { - label = "Volume Down"; - gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; + button-camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <15>; }; button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; - linux,input-type = ; linux,code = ; debounce-interval = <15>; }; - button-camera-focus { - label = "Camera Focus"; - gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; + button-vol-down { + label = "Volume Down"; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + button-vol-up { + label = "Volume Up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; debounce-interval = <15>; }; }; @@ -345,6 +350,14 @@ qcom,drive-strength = ; }; + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; + focus_n: focus-n-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; @@ -405,11 +418,6 @@ }; }; -&pm8998_resin { - linux,code = ; - status = "okay"; -}; - &qusb2phy { status = "okay"; From 7c2a774f028f6e2acc40bf969fcac288d3143c7f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 16 Mar 2024 13:10:46 +0100 Subject: [PATCH 222/969] arm64: dts: qcom: msm8998-yoshino: Enable RGB led Add the multicolor description and enable the PMI8998 LPG to expose the RGB notification LED. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240316-topic-maple_led-v1-1-ca3430fd9dc5@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index fdd3953938d9..d8cc0d729e99 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -418,6 +418,35 @@ }; }; +&pmi8998_lpg { + qcom,power-source = <1>; + + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = ; + }; + + led@4 { + reg = <4>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; +}; + &qusb2phy { status = "okay"; From d0d6230aa9652afc2c96a83eb2d217761683cad8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:18 -0700 Subject: [PATCH 223/969] arm64: dts: qcom: sc7280: Enable MDP turbo mode The max frequency listed in the DPU opp-table is 506MHz, this is not sufficient to drive a 4k@60 display, resulting in constant underrun. Add the missing MDP_CLK turbo frequency of 608MHz to the opp-table to fix this. Acked-by: Douglas Anderson Reviewed-by: Abhinav Kumar Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-1-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 6518c9c3a07f..bd9b1898d7a7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4467,6 +4467,11 @@ opp-hz = /bits/ 64 <506666667>; required-opps = <&rpmhpd_opp_nom>; }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; }; }; From 756efb7cb7293b0d971f661405e044cceab13d99 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:19 -0700 Subject: [PATCH 224/969] arm64: dts: qcom: qcs6490-rb3gen2: Add DP output The RB3Gen2 board comes with a mini DP connector, describe this, enable MDSS, DP controller and the PHY that drives this. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-2-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 63ebe0774f1d..f90bf3518e98 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -39,6 +39,20 @@ stdout-path = "serial0:115200n8"; }; + dp-connector { + compatible = "dp-connector"; + label = "DP"; + type = "mini"; + + hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -471,6 +485,25 @@ ; }; +&mdss { + status = "okay"; +}; + +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&dp_connector_in>; +}; + +&mdss_edp_phy { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -511,3 +544,10 @@ &wifi { memory-region = <&wlan_fw_mem>; }; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&edp_hot_plug_det { + function = "gpio"; + bias-disable; +}; From 3eb0b024decf99f917509db124f399dc47894075 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:20 -0700 Subject: [PATCH 225/969] arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp Define firmware paths and enable the ADSP and CDSP remoteprocs. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-3-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index f90bf3518e98..5b267a94a282 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -508,6 +508,16 @@ status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From a1615efb7c775adbee5400739a5e0a0d7a548dd8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:21 -0700 Subject: [PATCH 226/969] arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver The RB3gen2 has a USB redriver on APPS_I2C, enable the bus and introduce the redriver. The plumbing with other components is kept separate for clarity. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-4-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 5b267a94a282..2f94b1b865e7 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -485,6 +485,20 @@ ; }; +&i2c1 { + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l18b_1p8>; + + retimer-switch; + orientation-switch; + }; +}; + &mdss { status = "okay"; }; From c3d9acc529d581e3391dac3578812a7402e21c8a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:22 -0700 Subject: [PATCH 227/969] arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display With the ADSP remoteproc loaded pmic_glink can be introduced and together with the redriver wired up to provide role and orientation switching signals as well as USB Type-C display on the RB3gen2. Reviewed-by: Neil Armstrong Tested-By: Krishna Kurapati PSSNV Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-5-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 107 ++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 2f94b1b865e7..3cc19ccff90c 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -135,6 +135,49 @@ }; }; + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -496,6 +539,36 @@ retimer-switch; orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@2 { + reg = <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; }; }; @@ -503,6 +576,15 @@ status = "okay"; }; +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &mdss_edp { status = "okay"; }; @@ -547,7 +629,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -562,9 +653,23 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p912>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_phy_con_ss>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp_out>; +}; + &wifi { memory-region = <&wlan_fw_mem>; }; From acc8f4dbf1b3293dc0b5a51eadde086123806c0f Mon Sep 17 00:00:00 2001 From: Xiongwei Song Date: Thu, 4 Apr 2024 13:58:24 +0800 Subject: [PATCH 228/969] mm/slub: remove the check of !kmem_cache_has_cpu_partial() The check of !kmem_cache_has_cpu_partial(s) with CONFIG_SLUB_CPU_PARTIAL enabled here is always false. We have already checked kmem_cache_debug() earlier and if it was true, then we either continued or broke from the loop so we can't reach this code in that case and don't need to check kmem_cache_debug() as part of kmem_cache_has_cpu_partial() again. Here we can remove it. Signed-off-by: Xiongwei Song Signed-off-by: Vlastimil Babka --- mm/slub.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/mm/slub.c b/mm/slub.c index f152b5df8ab2..2e0351066c5d 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -2610,8 +2610,7 @@ static struct slab *get_partial_node(struct kmem_cache *s, partial_slabs++; } #ifdef CONFIG_SLUB_CPU_PARTIAL - if (!kmem_cache_has_cpu_partial(s) - || partial_slabs > s->cpu_partial_slabs / 2) + if (partial_slabs > s->cpu_partial_slabs / 2) break; #else break; From 721a2f8be134f9bb61f4358cbb7ae394eaf74573 Mon Sep 17 00:00:00 2001 From: Xiongwei Song Date: Thu, 4 Apr 2024 13:58:25 +0800 Subject: [PATCH 229/969] mm/slub: add slub_get_cpu_partial() helper Add slub_get_cpu_partial() and dummy function to help improve get_partial_node(). It can help remove #ifdef of CONFIG_SLUB_CPU_PARTIAL and improve filling cpu partial logic. Signed-off-by: Xiongwei Song Signed-off-by: Vlastimil Babka --- mm/slub.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/mm/slub.c b/mm/slub.c index 2e0351066c5d..936f2b13a78e 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -604,11 +604,21 @@ static void slub_set_cpu_partial(struct kmem_cache *s, unsigned int nr_objects) nr_slabs = DIV_ROUND_UP(nr_objects * 2, oo_objects(s->oo)); s->cpu_partial_slabs = nr_slabs; } + +static inline unsigned int slub_get_cpu_partial(struct kmem_cache *s) +{ + return s->cpu_partial_slabs; +} #else static inline void slub_set_cpu_partial(struct kmem_cache *s, unsigned int nr_objects) { } + +static inline unsigned int slub_get_cpu_partial(struct kmem_cache *s) +{ + return 0; +} #endif /* CONFIG_SLUB_CPU_PARTIAL */ /* From ff99b18fee793826dd5604da72d6259a531b45e9 Mon Sep 17 00:00:00 2001 From: Xiongwei Song Date: Thu, 4 Apr 2024 13:58:26 +0800 Subject: [PATCH 230/969] mm/slub: simplify get_partial_node() The break conditions for filling cpu partial can be more readable and simple. If slub_get_cpu_partial() returns 0, we can confirm that we don't need to fill cpu partial, then we should break from the loop. On the other hand, we also should break from the loop if we have added enough cpu partial slabs. Meanwhile, the logic above gets rid of the #ifdef and also fixes a weird corner case that if we set cpu_partial_slabs to 0 from sysfs, we still allocate at least one here. Signed-off-by: Xiongwei Song Signed-off-by: Vlastimil Babka --- mm/slub.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/mm/slub.c b/mm/slub.c index 936f2b13a78e..a9b1337e81c2 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -2614,18 +2614,18 @@ static struct slab *get_partial_node(struct kmem_cache *s, if (!partial) { partial = slab; stat(s, ALLOC_FROM_PARTIAL); + + if ((slub_get_cpu_partial(s) == 0)) { + break; + } } else { put_cpu_partial(s, slab, 0); stat(s, CPU_PARTIAL_NODE); - partial_slabs++; - } -#ifdef CONFIG_SLUB_CPU_PARTIAL - if (partial_slabs > s->cpu_partial_slabs / 2) - break; -#else - break; -#endif + if (++partial_slabs > slub_get_cpu_partial(s) / 2) { + break; + } + } } spin_unlock_irqrestore(&n->list_lock, flags); return partial; From 495667d49c5067ef4f732dcc44c9a7b0d7e98d39 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 3 Apr 2024 13:10:24 +0200 Subject: [PATCH 231/969] firmware: arm_scmi: Avoid non-constant printk format strings A recent rework changed the constant format strings to a local variable, which causes warnings from clang when -Wformat-security is enabled: drivers/firmware/arm_scmi/driver.c: In function 'scmi_probe': drivers/firmware/arm_scmi/driver.c:2936:25: error: format not a string literal and no format arguments [-Werror=format-security] 2936 | dev_err(dev, err_str); | ^~~~~~~ drivers/firmware/arm_scmi/driver.c:2993:9: error: format not a string literal and no format arguments [-Werror=format-security] 2993 | return dev_err_probe(dev, ret, err_str); Print these using an explicit "%s" string instead. Fixes: 3a7d93d1f71b ("firmware: arm_scmi: Use dev_err_probe to bail out") Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20240403111040.3924658-1-arnd@kernel.org Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index d0091459a276..36e3eb50a8d4 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -2933,7 +2933,7 @@ static int scmi_probe(struct platform_device *pdev) if (ret) { err_str = "unable to communicate with SCMI\n"; if (coex) { - dev_err(dev, err_str); + dev_err(dev, "%s", err_str); return 0; } goto notification_exit; @@ -2990,7 +2990,7 @@ clear_txrx_setup: clear_ida: ida_free(&scmi_id, info->id); - return dev_err_probe(dev, ret, err_str); + return dev_err_probe(dev, ret, "%s", err_str); } static void scmi_remove(struct platform_device *pdev) From b1080c667b3b2c8c38a7fa83ca5567124887abae Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Tue, 2 Apr 2024 06:38:39 -0700 Subject: [PATCH 232/969] mm/slub, kunit: Use inverted data to corrupt kmem cache Two failure patterns are seen randomly when running slub_kunit tests with CONFIG_SLAB_FREELIST_RANDOM and CONFIG_SLAB_FREELIST_HARDENED enabled. Pattern 1: # test_clobber_zone: pass:1 fail:0 skip:0 total:1 ok 1 test_clobber_zone # test_next_pointer: EXPECTATION FAILED at lib/slub_kunit.c:72 Expected 3 == slab_errors, but slab_errors == 0 (0x0) # test_next_pointer: EXPECTATION FAILED at lib/slub_kunit.c:84 Expected 2 == slab_errors, but slab_errors == 0 (0x0) # test_next_pointer: pass:0 fail:1 skip:0 total:1 not ok 2 test_next_pointer In this case, test_next_pointer() overwrites p[s->offset], but the data at p[s->offset] is already 0x12. Pattern 2: ok 1 test_clobber_zone # test_next_pointer: EXPECTATION FAILED at lib/slub_kunit.c:72 Expected 3 == slab_errors, but slab_errors == 2 (0x2) # test_next_pointer: pass:0 fail:1 skip:0 total:1 not ok 2 test_next_pointer In this case, p[s->offset] has a value other than 0x12, but one of the expected failures is nevertheless missing. Invert data instead of writing a fixed value to corrupt the cache data structures to fix the problem. Fixes: 1f9f78b1b376 ("mm/slub, kunit: add a KUnit test for SLUB debugging functionality") Cc: Oliver Glitta Cc: Vlastimil Babka CC: Daniel Latypov Cc: Marco Elver Signed-off-by: Guenter Roeck Signed-off-by: Vlastimil Babka --- lib/slub_kunit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/slub_kunit.c b/lib/slub_kunit.c index d4a3730b08fa..4ce960438806 100644 --- a/lib/slub_kunit.c +++ b/lib/slub_kunit.c @@ -55,7 +55,7 @@ static void test_next_pointer(struct kunit *test) ptr_addr = (unsigned long *)(p + s->offset); tmp = *ptr_addr; - p[s->offset] = 0x12; + p[s->offset] = ~p[s->offset]; /* * Expecting three errors. From fe09d2e314e5501e4673018270e6e1ed92e6e446 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 31 Jan 2024 04:15:42 -0800 Subject: [PATCH 233/969] scftorture: Increase memory provided to guest OS The tradition, extending back almost a full year, has been 2GB plus an additional number of GBs equal to the number of CPUs divided by sixteen. This tradition has served scftorture well, even the CONFIG_PREEMPT=y version running KASAN within guest OSes having 40 CPUs. However, this test recently started OOMing on larger systems, and this commit therefore gives this test an additional GB of memory. It is quite possible that further testing on larger systems will show a need to decrease the divisor from 16 to (say) 8, but that is a change to make once it has been demonstrated to be required. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- tools/testing/selftests/rcutorture/bin/torture.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/rcutorture/bin/torture.sh b/tools/testing/selftests/rcutorture/bin/torture.sh index bbac5f4b03d0..42f0aee09e51 100755 --- a/tools/testing/selftests/rcutorture/bin/torture.sh +++ b/tools/testing/selftests/rcutorture/bin/torture.sh @@ -425,7 +425,7 @@ fi if test "$do_scftorture" = "yes" then # Scale memory based on the number of CPUs. - scfmem=$((2+HALF_ALLOTED_CPUS/16)) + scfmem=$((3+HALF_ALLOTED_CPUS/16)) torture_bootargs="scftorture.nthreads=$HALF_ALLOTED_CPUS torture.disable_onoff_at_boot csdlock_debug=1" torture_set "scftorture" tools/testing/selftests/rcutorture/bin/kvm.sh --torture scf --allcpus --duration "$duration_scftorture" --configs "$configs_scftorture" --kconfig "CONFIG_NR_CPUS=$HALF_ALLOTED_CPUS" --memory ${scfmem}G --trust-make fi From 9e97ea7796412e23b8ecc946fd0488a2de39ea76 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 9 Feb 2024 03:11:25 -0800 Subject: [PATCH 234/969] rcutorture: Disable tracing to permit Tasks Rude RCU testing Now that the KPROBES, TRACING, BLK_DEV_IO_TRACE, and UPROBE_EVENTS Kconfig options select the TASKS_TRACE_RCU option, the torture.sh tests of enabling exactly one of the RCU Tasks flavors fail. This commit therefore disables these options to allow this testing to succeed. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- tools/testing/selftests/rcutorture/bin/torture.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/rcutorture/bin/torture.sh b/tools/testing/selftests/rcutorture/bin/torture.sh index 42f0aee09e51..13875ee7b050 100755 --- a/tools/testing/selftests/rcutorture/bin/torture.sh +++ b/tools/testing/selftests/rcutorture/bin/torture.sh @@ -391,7 +391,7 @@ __EOF__ forceflavor="`echo $flavor | sed -e 's/^CONFIG/CONFIG_FORCE/'`" deselectedflavors="`grep -v $flavor $T/rcutasksflavors | tr '\012' ' ' | tr -s ' ' | sed -e 's/ *$//'`" echo " --- Running RCU Tasks Trace flavor $flavor `date`" >> $rtfdir/log - tools/testing/selftests/rcutorture/bin/kvm.sh --datestamp "$ds/results-rcutasksflavors/$flavor" --buildonly --configs "TINY01 TREE04" --kconfig "CONFIG_RCU_EXPERT=y CONFIG_RCU_SCALE_TEST=y $forceflavor=y $deselectedflavors" --trust-make > $T/$flavor.out 2>&1 + tools/testing/selftests/rcutorture/bin/kvm.sh --datestamp "$ds/results-rcutasksflavors/$flavor" --buildonly --configs "TINY01 TREE04" --kconfig "CONFIG_RCU_EXPERT=y CONFIG_RCU_SCALE_TEST=y CONFIG_KPROBES=n CONFIG_RCU_TRACE=n CONFIG_TRACING=n CONFIG_BLK_DEV_IO_TRACE=n CONFIG_UPROBE_EVENTS=n $forceflavor=y $deselectedflavors" --trust-make > $T/$flavor.out 2>&1 retcode=$? if test "$retcode" -ne 0 then From b062539c4e2f31ff346795ce32012e9e6300d212 Mon Sep 17 00:00:00 2001 From: Xiu Jianfeng Date: Mon, 25 Mar 2024 12:22:17 +0000 Subject: [PATCH 235/969] mm/slub: correct comment in do_slab_free() slab_alloc_node() should be __slab_alloc_node(). Signed-off-by: Xiu Jianfeng Signed-off-by: Vlastimil Babka --- mm/slub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/slub.c b/mm/slub.c index a9b1337e81c2..f4fd460854fd 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -4256,7 +4256,7 @@ redo: c = raw_cpu_ptr(s->cpu_slab); tid = READ_ONCE(c->tid); - /* Same with comment on barrier() in slab_alloc_node() */ + /* Same with comment on barrier() in __slab_alloc_node() */ barrier(); if (unlikely(slab != c->slab)) { From 2604f31693c886aacf41758b7bac2dd481673ad8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Mar 2024 21:58:05 +0200 Subject: [PATCH 236/969] dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Add gpio child node Unlike the other child nodes of the raspberrypi,bcm2835-firmware device, the gpio child is documented in a legacy text-based binding in gpio/raspberrypi,firmware-gpio.txt. This causes DT validation failures: arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dtb: 'gpio' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/arm/bcm/raspberrypi,bcm2835-firmware.yaml# Convert the binding to YAML and move it to raspberrypi,bcm2835-firmware.yaml. Signed-off-by: Laurent Pinchart Reviewed-by: Krzysztof Kozlowski Reviewed-by: Stefan Wahren Tested-by: Ivan T. Ivanov Link: https://lore.kernel.org/r/20240326195807.15163-2-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- .../arm/bcm/raspberrypi,bcm2835-firmware.yaml | 30 +++++++++++++++++++ .../gpio/raspberrypi,firmware-gpio.txt | 30 ------------------- 2 files changed, 30 insertions(+), 30 deletions(-) delete mode 100644 Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml index 39e3c248f5b7..1f84407a73e4 100644 --- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml @@ -46,6 +46,30 @@ properties: - compatible - "#clock-cells" + gpio: + type: object + additionalProperties: false + + properties: + compatible: + const: raspberrypi,firmware-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + The first cell is the pin number, and the second cell is used to + specify the gpio polarity (GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW). + + gpio-line-names: + minItems: 8 + + required: + - compatible + - gpio-controller + - "#gpio-cells" + reset: type: object additionalProperties: false @@ -96,6 +120,12 @@ examples: #clock-cells = <1>; }; + expgpio: gpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + reset: reset { compatible = "raspberrypi,firmware-reset"; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt b/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt deleted file mode 100644 index ce97265e23ba..000000000000 --- a/Documentation/devicetree/bindings/gpio/raspberrypi,firmware-gpio.txt +++ /dev/null @@ -1,30 +0,0 @@ -Raspberry Pi GPIO expander - -The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The -firmware exposes a mailbox interface that allows the ARM core to control the -GPIO lines on the expander. - -The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi -firmware node. - -Required properties: - -- compatible : Should be "raspberrypi,firmware-gpio" -- gpio-controller : Marks the device node as a gpio controller -- #gpio-cells : Should be two. The first cell is the pin number, and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low - -Example: - -firmware: firmware-rpi { - compatible = "raspberrypi,bcm2835-firmware"; - mboxes = <&mailbox>; - - expgpio: gpio { - compatible = "raspberrypi,firmware-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; -}; From df518a0ae1b982a4dcf2235464016c0c4576a34d Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Mar 2024 21:58:06 +0200 Subject: [PATCH 237/969] firmware: raspberrypi: Use correct device for DMA mappings The buffer used to transfer data over the mailbox interface is mapped using the client's device. This is incorrect, as the device performing the DMA transfer is the mailbox itself. Fix it by using the mailbox controller device instead. This requires including the mailbox_controller.h header to dereference the mbox_chan and mbox_controller structures. The header is not meant to be included by clients. This could be fixed by extending the client API with a function to access the controller's device. Fixes: 4e3d60656a72 ("ARM: bcm2835: Add the Raspberry Pi firmware driver") Signed-off-by: Laurent Pinchart Reviewed-by: Stefan Wahren Tested-by: Ivan T. Ivanov Link: https://lore.kernel.org/r/20240326195807.15163-3-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- drivers/firmware/raspberrypi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c index 322aada20f74..ac34876a97f8 100644 --- a/drivers/firmware/raspberrypi.c +++ b/drivers/firmware/raspberrypi.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -97,8 +98,8 @@ int rpi_firmware_property_list(struct rpi_firmware *fw, if (size & 3) return -EINVAL; - buf = dma_alloc_coherent(fw->cl.dev, PAGE_ALIGN(size), &bus_addr, - GFP_ATOMIC); + buf = dma_alloc_coherent(fw->chan->mbox->dev, PAGE_ALIGN(size), + &bus_addr, GFP_ATOMIC); if (!buf) return -ENOMEM; @@ -126,7 +127,7 @@ int rpi_firmware_property_list(struct rpi_firmware *fw, ret = -EINVAL; } - dma_free_coherent(fw->cl.dev, PAGE_ALIGN(size), buf, bus_addr); + dma_free_coherent(fw->chan->mbox->dev, PAGE_ALIGN(size), buf, bus_addr); return ret; } From e54c32f8bc7e1c44f7674b29d3db8e5d193b9dad Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 26 Mar 2024 21:58:07 +0200 Subject: [PATCH 238/969] ARM: dts: bcm283x: Drop unneeded properties in the bcm2835-firmware node The firmware node contains a "dma-ranges" property to enable usage of the DMA mapping API with its child devices, along with "#address-cells" and "#size-cells" properties to support the dma-ranges. This was needed due to usage of the incorrect device to perform the DMA mapping in drivers. Now that this has been fixed, drop the properties. This effectively reverts commits be08d278eb09 ("ARM: dts: bcm283x: Add cells encoding format to firmware bus") and 55c7c0621078 ("ARM: dts: bcm283x: Fix vc4's firmware bus DMA limitations"). Signed-off-by: Laurent Pinchart Reviewed-by: Stefan Wahren Tested-by: Ivan T. Ivanov Link: https://lore.kernel.org/r/20240326195807.15163-4-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi index f0acc9390f31..761a9da97bd0 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi @@ -4,11 +4,7 @@ soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - mboxes = <&mailbox>; - dma-ranges; }; power: power { From f702475b839cad900cc08ddf29dd7a9e43c5976a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 2 Apr 2024 03:04:12 +0300 Subject: [PATCH 239/969] ARM: dts: bcm2835-rpi: Move duplicate firmware-clocks to bcm2835-rpi.dtsi The Raspberry Pi firmware handles clocks on all BCM2835-derived SoCs. It is currently defined identically in both bcm2711-rpi.dtsi and bcm2835-rpi-common.dtsi. Move the definitions to the common bcm2835-rpi.dtsi file. Signed-off-by: Laurent Pinchart Reviewed-by: Dave Stevenson Link: https://lore.kernel.org/r/20240402000424.4650-6-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 5 ----- arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi | 7 ------- arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 5 +++++ 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi index d233a191c139..86188eabeb24 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi @@ -20,11 +20,6 @@ }; &firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; - expgpio: gpio { compatible = "raspberrypi,firmware-gpio"; gpio-controller; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi index 4e7b4a592da7..8b3c21d9f333 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-common.dtsi @@ -7,13 +7,6 @@ #include -&firmware { - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; -}; - &hdmi { clocks = <&firmware_clocks 9>, <&firmware_clocks 13>; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi index 761a9da97bd0..6e6dc109f0c2 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi @@ -5,6 +5,11 @@ firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; mboxes = <&mailbox>; + + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; }; power: power { From 84b1d6cc3e4cc49f04aaacc5e0094c221a772cf0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Apr 2024 03:04:14 +0300 Subject: [PATCH 240/969] ARM: dts: bcm2711-rpi: Add pinctrl-based multiplexing for I2C0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM2711-based Raspberry Pi boards (4B, CM4 and 400) multiplex the I2C0 controller over two sets of pins, GPIO0+1 and GPIO44+45. The former is exposed on the 40-pin header, while the latter is used for the CSI and DSI connectors. Add a pinctrl-based I2C bus multiplexer to bcm2711-rpi.dtsi to model this multiplexing. The two child buses are named i2c0_0 and i2c0_1. Note that if you modified the dts before to add devices to the i2c bus appearing on pins gpio0 + gpio1 (either directly in the dts or using an overlay), you have to put these into the i2c0_0 node introduced here now. Signed-off-by: Uwe Kleine-König Signed-off-by: Laurent Pinchart Acked-by: Dave Stevenson Link: https://lore.kernel.org/r/20240402000424.4650-8-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 29 +++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi index 86188eabeb24..6bf4241fe3b7 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi @@ -17,6 +17,30 @@ pcie0 = &pcie0; blconfig = &blconfig; }; + + i2c0mux: i2c-mux0 { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c0>; + + pinctrl-names = "i2c0", "i2c0-vc"; + pinctrl-0 = <&i2c0_gpio0>; + pinctrl-1 = <&i2c0_gpio44>; + + i2c0_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; &firmware { @@ -49,6 +73,11 @@ clocks = <&firmware_clocks 4>; }; +&i2c0 { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + &rmem { /* * RPi4's co-processor will copy the board's bootloader configuration From d72e40d41736d083e47dc50c6c2e1d59e5af6944 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Tue, 2 Apr 2024 03:04:15 +0300 Subject: [PATCH 241/969] ARM: dts: bcm2711-rpi-cm4-io: Add RTC on I2C0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The cm4-io board comes with a PCF85063 on I2C0, connected to the GPIO44 and GPIO45 pins. Add it to the device tree. Signed-off-by: Uwe Kleine-König Signed-off-by: Laurent Pinchart Acked-by: Dave Stevenson Link: https://lore.kernel.org/r/20240402000424.4650-9-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts index d7ba02f586d3..7c6a5bdf48aa 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -101,6 +101,15 @@ status = "okay"; }; +&i2c0_1 { + rtc@51 { + /* Attention: An alarm resets the machine */ + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; +}; + &led_act { gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; }; From d990221ba5490046d291667c75c0db61afb370d9 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Tue, 2 Apr 2024 03:04:16 +0300 Subject: [PATCH 242/969] ARM: dts: bcm2711-rpi-4-b: Add CAM1 regulator Add a fixed regulator to model the power supply to the camera connector. Signed-off-by: Laurent Pinchart Reviewed-by: Dave Stevenson Link: https://lore.kernel.org/r/20240402000424.4650-10-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts index d5f8823230db..cfc8cb5e10ba 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -15,6 +15,13 @@ stdout-path = "serial1:115200n8"; }; + cam1_reg: regulator-cam1 { + compatible = "regulator-fixed"; + regulator-name = "cam1-reg"; + enable-active-high; + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>; + }; + sd_io_1v8_reg: regulator-sd-io-1v8 { compatible = "regulator-gpio"; regulator-name = "vdd-sd-io"; From f8dddefcb90eaa339c77b2cb3f5a87dec8b1e3b5 Mon Sep 17 00:00:00 2001 From: Joe Mason Date: Thu, 4 Apr 2024 12:17:44 +0000 Subject: [PATCH 243/969] arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreen Like msm8916-samsung-a3u-eur, the Grand Prime uses a Zinitix BT541 touchscreen. Add it together with the necessary fixed-regulator to the device tree. Signed-off-by: Joe Mason [Raymond: Move to fortuna-common. Use interrupts-extended] Signed-off-by: Raymond Hackley Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240404121703.17086-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-fortuna-common.dtsi | 47 +++++++++++++++++++ .../qcom/msm8916-samsung-rossa-common.dtsi | 3 ++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index c2800ad2dd5b..6c66a24ef1af 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -66,6 +66,19 @@ pinctrl-0 = <&motor_en_default>; pinctrl-names = "default"; }; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp_a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; }; &blsp_i2c1 { @@ -94,6 +107,26 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen: touchscreen@20 { + compatible = "zinitix,bt541"; + reg = <0x20>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vcca-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -200,4 +233,18 @@ drive-strength = <2>; bias-disable; }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 42843771ae2a..4048b72efcdc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -5,6 +5,9 @@ /* SM5504 MUIC instead of SM5502 */ /delete-node/ &muic; +/* Touchscreen varies depending on model variant */ +/delete-node/ &touchscreen; + &blsp_i2c1 { muic: extcon@14 { compatible = "siliconmitus,sm5504-muic"; From 05c65922bd58cc3fc057b37628b143f76e524496 Mon Sep 17 00:00:00 2001 From: Siddharth Manthan Date: Thu, 4 Apr 2024 12:17:57 +0000 Subject: [PATCH 244/969] arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlight Most of the Galaxy Grand Prime use backlight drivers controlled with PWM signal. To simplify the description, add the backlight with the necessary clk-pwm to the common dtsi. Signed-off-by: Siddharth Manthan [Stephan: Move to fortuna-common and disable on rossa-common] Signed-off-by: Stephan Gerhold [Raymond: Add the commit message] Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240404121703.17086-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-fortuna-common.dtsi | 36 +++++++++++++++++++ .../qcom/msm8916-samsung-rossa-common.dtsi | 9 +++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 6c66a24ef1af..5e933fb8b363 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -26,6 +26,30 @@ }; }; + clk_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&clk_pwm 0 100000>; + + enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <128>; + + pinctrl-0 = <&backlight_en_default>; + pinctrl-names = "default"; + }; + + clk_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&backlight_pwm_default>; + pinctrl-names = "default"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -199,6 +223,18 @@ }; &tlmm { + backlight_en_default: backlight-en-default-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default: backlight-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 4048b72efcdc..b438fa81886c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -17,3 +17,12 @@ pinctrl-names = "default"; }; }; + +/* On rossa backlight is controlled with MIPI DCS commands */ +&clk_pwm { + status = "disabled"; +}; + +&clk_pwm_backlight { + status = "disabled"; +}; From e5fd6512f6e842d8c5883b9fa4d72c8a5295efdc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Apr 2024 20:10:12 +0300 Subject: [PATCH 245/969] arm64: dts: qcom: sm8150-hdk: enable WiFI support Enable modem DSP and WiFI devices on the SM8150 HDK device. The HDK is manufactured by Lantronix, but it attributed to Qualcomm, so the calibration string uses Qualcomm as manufacturer. For reference: ath10k_snoc 18800000.wifi: qmi chip_id 0x30224 chip_family 0x4001 board_id 0x55 soc_id 0x40060000 ath10k_snoc 18800000.wifi: qmi fw_version 0x32040163 fw_build_timestamp 2019-10-08 05:42 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.2.0-00355-QCAHLSWMTPLZ-1 ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc 18800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc 18800000.wifi: htt-ver 3.73 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 ath10k_snoc 18800000.wifi: invalid MAC address; choosing random Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240403-sm8150-hdk-wifi-v1-1-8da3063829c2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index de670b407ef1..6cb6f503fdac 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -609,6 +609,11 @@ firmware-name = "qcom/sm8150/cdsp.mbn"; }; +&remoteproc_mpss { + firmware-name = "qcom/sm8150/modem.mbn"; + status = "okay"; +}; + &remoteproc_slpi { status = "okay"; @@ -713,3 +718,14 @@ &usb_2_dwc3 { dr_mode = "host"; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l1a_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + + qcom,ath10k-calibration-variant = "Qualcomm_sm8150hdk"; +}; From 58dc9622d5de6ce0b80969b136e8e09a7645eca5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 27 Mar 2024 19:01:13 -0700 Subject: [PATCH 246/969] arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS The rb3gen2 has UFS memory, adjust the necessary supply voltage and add the controller and phy nodes to enable this. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240327-rb3gen2-ufs-v2-1-3de6b5dd78dd@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 28 +++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 3cc19ccff90c..c98c41f8f3b1 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -278,8 +278,8 @@ vreg_l7b_2p952: ldo7 { regulator-name = "vreg_l7b_2p952"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <3544000>; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; regulator-initial-mode = ; }; @@ -293,8 +293,11 @@ vreg_l9b_1p2: ldo9 { regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1304000>; + regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; }; vreg_l11b_1p504: ldo11 { @@ -670,6 +673,25 @@ remote-endpoint = <&mdss_dp_out>; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + &wifi { memory-region = <&wlan_fw_mem>; }; From d7218d3c9e078072a02eeb1d1aced8d1ad1537c8 Mon Sep 17 00:00:00 2001 From: Oleksii Moisieiev Date: Fri, 5 Jan 2024 14:03:52 +0100 Subject: [PATCH 247/969] dt-bindings: document generic access controllers Introducing of the generic access controllers bindings for the access controller provider and consumer devices. Those bindings are intended to allow a better handling of accesses to resources in a hardware architecture supporting several compartments. This patch is based on [1]. It is integrated in this patchset as it provides a use-case for it. Diffs with [1]: - Rename feature-domain* properties to access-control* to narrow down the scope of the binding - YAML errors and typos corrected. - Example updated - Some rephrasing in the binding description [1]: https://lore.kernel.org/lkml/0c0a82bb-18ae-d057-562b Signed-off-by: Oleksii Moisieiev Signed-off-by: Gatien Chevallier Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../access-controllers.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/access-controllers/access-controllers.yaml diff --git a/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml b/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml new file mode 100644 index 000000000000..99e2865f0e46 --- /dev/null +++ b/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Domain Access Controllers + +maintainers: + - Oleksii Moisieiev + +description: |+ + Common access controllers properties + + Access controllers are in charge of stating which of the hardware blocks under + their responsibility (their domain) can be accesssed by which compartment. A + compartment can be a cluster of CPUs (or coprocessors), a range of addresses + or a group of hardware blocks. An access controller's domain is the set of + resources covered by the access controller. + + This device tree binding can be used to bind devices to their access + controller provided by access-controllers property. In this case, the device + is a consumer and the access controller is the provider. + + An access controller can be represented by any node in the device tree and + can provide one or more configuration parameters, needed to control parameters + of the consumer device. A consumer node can refer to the provider by phandle + and a set of phandle arguments, specified by '#access-controller-cells' + property in the access controller node. + + Access controllers are typically used to set/read the permissions of a + hardware block and grant access to it. Any of which depends on the access + controller. The capabilities of each access controller are defined by the + binding of the access controller device. + + Each node can be a consumer for the several access controllers. + +# always select the core schema +select: true + +properties: + "#access-controller-cells": + description: + Number of cells in an access-controllers specifier; + Can be any value as specified by device tree binding documentation + of a particular provider. The node is an access controller. + + access-controller-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + A list of access-controllers names, sorted in the same order as + access-controllers entries. Consumer drivers will use + access-controller-names to match with existing access-controllers entries. + + access-controllers: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A list of access controller specifiers, as defined by the + bindings of the access-controllers provider. + +additionalProperties: true + +examples: + - | + clock_controller: access-controllers@50000 { + reg = <0x50000 0x400>; + #access-controller-cells = <2>; + }; + + bus_controller: bus@60000 { + reg = <0x60000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #access-controller-cells = <3>; + + uart4: serial@60100 { + reg = <0x60100 0x400>; + clocks = <&clk_serial>; + access-controllers = <&clock_controller 1 2>, + <&bus_controller 1 3 5>; + access-controller-names = "clock", "bus"; + }; + }; From 02ec75edaa94a28b4e89ca6594ae988918be3dc5 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:53 +0100 Subject: [PATCH 248/969] dt-bindings: treewide: add access-controllers description access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controller. It allows an accurate representation of the hardware, where various peripherals are connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Gatien Chevallier Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml | 4 ++++ Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 4 ++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 26 files changed, 104 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml index 0ddeb8a9a7a0..27354658d054 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml @@ -46,6 +46,10 @@ properties: power-domains: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index ac480765cde0..822318414095 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -51,6 +51,10 @@ properties: power-domains: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 329847ef096a..ff935a0068ec 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -82,6 +82,10 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index e722fbcd8a5f..ddf82bf1e71a 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -28,6 +28,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 1b31b87c1800..8fd8be76875e 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -127,6 +127,10 @@ properties: wakeup-source: true + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 995cbf8cefc6..ec34c48d4878 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -93,6 +93,10 @@ properties: '#size-cells': const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + allOf: - if: properties: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 1970503389aa..c1b1324fa132 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -59,6 +59,10 @@ properties: If not, SPI CLKOUT frequency will not be accurate. maximum: 20000000 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 04045b932bd2..b15de4eb209c 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -45,6 +45,10 @@ properties: '#size-cells': const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + additionalProperties: false required: diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml index 2314a9a14650..1d930d9e10fd 100644 --- a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml @@ -29,6 +29,10 @@ properties: - const: cec - const: hdmi-cec + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 6b3e413cedb2..34147127192f 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -36,6 +36,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 84ac6f50a6fc..706e45eb4d27 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -50,6 +50,10 @@ properties: Reflects the memory layout with four integer values per bank. Format: 0
+ access-controllers: + minItems: 1 + maxItems: 2 + patternProperties: "^.*@[0-4],[a-f0-9]+$": additionalProperties: true diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 27329c5dc38e..d41308856408 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -44,6 +44,10 @@ properties: wakeup-source: true + access-controllers: + minItems: 1 + maxItems: 2 + pwm: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f84e09a5743b..b0e438ff4950 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -67,6 +67,10 @@ properties: "#size-cells": const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + pwm: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml index 940b12688167..8f62e2c7fa64 100644 --- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml +++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml @@ -79,6 +79,10 @@ properties: - const: rx - const: tx + access-controllers: + minItems: 1 + maxItems: 2 + power-domains: true resets: diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index f9ffb963d6b1..c4887522e8fe 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -118,6 +118,10 @@ properties: phys: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7d..f2714b5b6cf4 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -93,6 +93,10 @@ properties: select RCC clock instead of ETH_REF_CLK. type: boolean + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 24a3dbde223b..ceea122ae1a6 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -55,6 +55,10 @@ properties: description: number of clock cells for ck_usbo_48m consumer const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + # Required child nodes: patternProperties: diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 05f4ad2c7d3a..6ceaffb45dc9 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -30,6 +30,10 @@ properties: vdda-supply: description: phandle to the vdda input analog voltage. + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 717f6b321f88..340d01d481d1 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -37,6 +37,10 @@ properties: description: If set, the RNG configuration in RNG_CR, RNG_HTCR and RNG_NSCR will be locked. + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 62f97da1b2fd..2ed526139269 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -73,6 +73,10 @@ properties: enum: [1, 2, 4, 8, 12, 14, 16] default: 8 + access-controllers: + minItems: 1 + maxItems: 2 + allOf: - $ref: rs485.yaml# - $ref: serial.yaml# diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index b9111d375b93..8978f6bd63e5 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -65,6 +65,10 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index 59df8a832310..b46a4778807d 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -48,6 +48,10 @@ properties: clock-names: maxItems: 3 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index bc48151b9adb..3dedc81ec12f 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -50,6 +50,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 8bba965a9ae6..3f1a27efff80 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -46,6 +46,10 @@ properties: - const: tx - const: rx + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 4bd9aeb81208..a55c8633c32c 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -52,6 +52,10 @@ properties: - const: rx - const: tx + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 0a5c98ea711d..88c077673c8b 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -172,6 +172,10 @@ properties: tpl-support: true + access-controllers: + minItems: 1 + maxItems: 2 + dependencies: port: [ usb-role-switch ] role-switch-default-mode: [ usb-role-switch ] From eac9fba67f47b75e78d57d00fffb9d59a3331379 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:54 +0100 Subject: [PATCH 249/969] dt-bindings: bus: document RIFSC Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources. Signed-off-by: Gatien Chevallier Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml new file mode 100644 index 000000000000..20acd1a6b173 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller + +maintainers: + - Gatien Chevallier + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +select: + properties: + compatible: + contains: + const: st,stm32mp25-rifsc + required: + - compatible + +properties: + compatible: + items: + - const: st,stm32mp25-rifsc + - const: simple-bus + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + description: + Contains the firewall ID associated to the peripheral. + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + + additionalProperties: true + + required: + - access-controllers + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; + }; + }; From c1c67654df0713539f9b5e8f84ce8fc573465efb Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:55 +0100 Subject: [PATCH 250/969] dt-bindings: bus: document ETZPC Document ETZPC (Extended TrustZone protection controller). ETZPC is a firewall controller. Signed-off-by: Gatien Chevallier Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../bindings/bus/st,stm32-etzpc.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml new file mode 100644 index 000000000000..d12b62a3a5a8 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Extended TrustZone protection controller + +description: | + The ETZPC configures TrustZone security in a SoC having bus masters and + devices with programmable-security attributes (securable resources). + +maintainers: + - Gatien Chevallier + +select: + properties: + compatible: + contains: + const: st,stm32-etzpc + required: + - compatible + +properties: + compatible: + items: + - const: st,stm32-etzpc + - const: simple-bus + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + description: + Contains the firewall ID associated to the peripheral. + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + + additionalProperties: true + + required: + - access-controllers + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its access + // controller. + // Access rights are verified before creating devices. + + #include + #include + #include + + etzpc: bus@5c007000 { + compatible = "st,stm32-etzpc", "simple-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc 17>; + }; + }; From 5c9668cfc6d7c7de30fa57fa0a6c0ddc93462969 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:56 +0100 Subject: [PATCH 251/969] firewall: introduce stm32_firewall framework Introduce a STM32 firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s). The STM32 firewall framework offers a generic API for STM32 firewall controllers that is defined in their drivers to best fit the specificity of each firewall. There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -No type for undefined type of firewall Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- MAINTAINERS | 5 + arch/arm/mach-stm32/Kconfig | 1 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 294 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 ++++++ include/linux/bus/stm32_firewall_device.h | 142 +++++++++++ 8 files changed, 537 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..b896bd80d361 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20811,6 +20811,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c +ST STM32 FIREWALL +M: Gatien Chevallier +S: Maintained +F: drivers/bus/stm32_firewall.c + ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET M: Alain Volmat diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 98145031586f..ae21a9f78f9c 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -12,6 +12,7 @@ menuconfig ARCH_STM32 select PINCTRL select RESET_CONTROLLER select STM32_EXTI + select STM32_FIREWALL help Support for STMicroelectronics STM32 processors. diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..13ed0a483617 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -305,6 +305,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI + select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including: diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index d5e7fa9173a1..64cd2ee03aa3 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above. +config STM32_FIREWALL + bool "STM32 Firewall framework" + depends on (ARCH_STM32 || COMPILE_TEST) && OF + select OF_DYNAMIC + help + Say y to enable STM32 firewall framework and its services. Firewall + controllers will be able to register to the framework. Access for + hardware resources linked to a firewall controller can be requested + through this STM32 framework. + config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..decb79449047 --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 1) + +static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock); + +/* Firewall device API */ + +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall, + unsigned int nb_firewall) +{ + struct stm32_firewall_controller *ctrl; + struct of_phandle_iterator it; + unsigned int i, j = 0; + int err; + + if (!firewall || !nb_firewall) + return -EINVAL; + + /* Parse property with phandle parsed out */ + of_for_each_phandle(&it, err, np, "access-controllers", "#access-controller-cells", 0) { + struct of_phandle_args provider_args; + struct device_node *provider = it.node; + const char *fw_entry; + bool match = false; + + if (err) { + pr_err("Unable to get access-controllers property for node %s\n, err: %d", + np->full_name, err); + of_node_put(provider); + return err; + } + + if (j > nb_firewall) { + pr_err("Too many firewall controllers"); + of_node_put(provider); + return -EINVAL; + } + + provider_args.args_count = of_phandle_iterator_args(&it, provider_args.args, + STM32_FIREWALL_MAX_ARGS); + + /* Check if the parsed phandle corresponds to a registered firewall controller */ + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl->dev->of_node->phandle == it.phandle) { + match = true; + firewall[j].firewall_ctrl = ctrl; + break; + } + } + mutex_unlock(&firewall_controller_list_lock); + + if (!match) { + firewall[j].firewall_ctrl = NULL; + pr_err("No firewall controller registered for %s\n", np->full_name); + of_node_put(provider); + return -ENODEV; + } + + err = of_property_read_string_index(np, "access-controller-names", j, &fw_entry); + if (err == 0) + firewall[j].entry = fw_entry; + + /* Handle the case when there are no arguments given along with the phandle */ + if (provider_args.args_count < 0 || + provider_args.args_count > STM32_FIREWALL_MAX_ARGS) { + of_node_put(provider); + return -EINVAL; + } else if (provider_args.args_count == 0) { + firewall[j].extra_args_size = 0; + firewall[j].firewall_id = U32_MAX; + j++; + continue; + } + + /* The firewall ID is always the first argument */ + firewall[j].firewall_id = provider_args.args[0]; + + /* Extra args start at the second argument */ + for (i = 0; i < provider_args.args_count - 1; i++) + firewall[j].extra_args[i] = provider_args.args[i + 1]; + + /* Remove the firewall ID arg that is not an extra argument */ + firewall[j].extra_args_size = provider_args.args_count - 1; + + j++; + } + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall); + +int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || firewall->firewall_id == U32_MAX) + return -EINVAL; + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) + return -ENODEV; + + return firewall_controller->grant_access(firewall_controller, firewall->firewall_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access); + +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) + return -EINVAL; + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) + return -ENODEV; + + return firewall_controller->grant_access(firewall_controller, subsystem_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id); + +void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || firewall->firewall_id == U32_MAX) { + pr_debug("Incorrect arguments when releasing a firewall access\n"); + return; + } + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) { + pr_debug("No firewall controller to release\n"); + return; + } + + firewall_controller->release_access(firewall_controller, firewall->firewall_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access); + +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) { + pr_debug("Incorrect arguments when releasing a firewall access"); + return; + } + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) { + pr_debug("No firewall controller to release"); + return; + } + + firewall_controller->release_access(firewall_controller, subsystem_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id); + +/* Firewall controller API */ + +int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall_controller *ctrl; + + if (!firewall_controller) + return -ENODEV; + + pr_info("Registering %s firewall controller\n", firewall_controller->name); + + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl == firewall_controller) { + pr_debug("%s firewall controller already registered\n", + firewall_controller->name); + mutex_unlock(&firewall_controller_list_lock); + return 0; + } + } + list_add_tail(&firewall_controller->entry, &firewall_controller_list); + mutex_unlock(&firewall_controller_list_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_controller_register); + +void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall_controller *ctrl; + bool controller_removed = false; + + if (!firewall_controller) { + pr_debug("Null reference while unregistering firewall controller\n"); + return; + } + + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl == firewall_controller) { + controller_removed = true; + list_del_init(&ctrl->entry); + break; + } + } + mutex_unlock(&firewall_controller_list_lock); + + if (!controller_removed) + pr_debug("There was no firewall controller named %s to unregister\n", + firewall_controller->name); +} +EXPORT_SYMBOL_GPL(stm32_firewall_controller_unregister); + +int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall *firewalls; + struct device_node *child; + struct device *parent; + unsigned int i; + int len; + int err; + + parent = firewall_controller->dev; + + dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev)); + + for_each_available_child_of_node(dev_of_node(parent), child) { + /* The access-controllers property is mandatory for firewall bus devices */ + len = of_count_phandle_with_args(child, "access-controllers", + "#access-controller-cells"); + if (len <= 0) { + of_node_put(child); + return -EINVAL; + } + + firewalls = kcalloc(len, sizeof(*firewalls), GFP_KERNEL); + if (!firewalls) { + of_node_put(child); + return -ENOMEM; + } + + err = stm32_firewall_get_firewall(child, firewalls, (unsigned int)len); + if (err) { + kfree(firewalls); + of_node_put(child); + return err; + } + + for (i = 0; i < len; i++) { + if (firewall_controller->grant_access(firewall_controller, + firewalls[i].firewall_id)) { + /* + * Peripheral access not allowed or not defined. + * Mark the node as populated so platform bus won't probe it + */ + of_detach_node(child); + dev_err(parent, "%s: Device driver will not be probed\n", + child->full_name); + } + } + + kfree(firewalls); + } + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_populate_bus); diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..e5fac85fe346 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H + +#include +#include +#include +#include +#include + +/** + * STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals + * STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory + * zones + * STM32_NOTYPE_FIREWALL: Undefined firewall type + */ + +#define STM32_PERIPHERAL_FIREWALL BIT(1) +#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_NOTYPE_FIREWALL BIT(3) + +/** + * struct stm32_firewall_controller - Information on firewall controller supplying services + * + * @name: Name of the firewall controller + * @dev: Device reference of the firewall controller + * @mmio: Base address of the firewall controller + * @entry: List entry of the firewall controller list + * @type: Type of firewall + * @max_entries: Number of entries covered by the firewall + * @grant_access: Callback used to grant access for a device access against a + * firewall controller + * @release_access: Callback used to release resources taken by a device when access was + * granted + * @grant_memory_range_access: Callback used to grant access for a device to a given memory region + */ +struct stm32_firewall_controller { + const char *name; + struct device *dev; + void __iomem *mmio; + struct list_head entry; + unsigned int type; + unsigned int max_entries; + + int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id); + void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id); + int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr, + size_t size); +}; + +/** + * stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall + * framework + * @firewall_controller: Firewall controller to register + * + * Returns 0 in case of success or -ENODEV if no controller was given. + */ +int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller); + +/** + * stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32 + * firewall framework + * @firewall_controller: Firewall controller to unregister + */ +void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller); + +/** + * stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall + * configuration. This is used at boot-time only, as a sanity check + * between device tree and firewalls hardware configurations to + * prevent a kernel crash when a device driver is not granted access + * + * @firewall_controller: Firewall controller which nodes will be populated or not + * + * Returns 0 in case of success or appropriate errno code if error occurred. + */ +int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller); + +#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..18e0a2fc3816 --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H + +#include +#include +#include + +#define STM32_FIREWALL_MAX_EXTRA_ARGS 5 + +/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller; + +/** + * struct stm32_firewall - Information on a device's firewall. Each device can have more than one + * firewall. + * + * @firewall_ctrl: Pointer referencing a firewall controller of the device. It is + * opaque so a device cannot manipulate the controller's ops or access + * the controller's data + * @extra_args: Extra arguments that are implementation dependent + * @entry: Name of the firewall entry + * @extra_args_size: Number of extra arguments + * @firewall_id: Firewall ID associated the device for this firewall controller + */ +struct stm32_firewall { + struct stm32_firewall_controller *firewall_ctrl; + u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS]; + const char *entry; + size_t extra_args_size; + u32 firewall_id; +}; + +#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/** + * stm32_firewall_get_firewall - Get the firewall(s) associated to given device. + * The firewall controller reference is always the first argument + * of each of the access-controller property entries. + * The firewall ID is always the second argument of each of the + * access-controller property entries. + * If there's no argument linked to the phandle, then the firewall ID + * field is set to U32_MAX, which is an invalid ID. + * + * @np: Device node to parse + * @firewall: Array of firewall references + * @nb_firewall: Number of firewall references to get. Must be at least 1. + * + * Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno + * code if error occurred. + */ +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall, + unsigned int nb_firewall); + +/** + * stm32_firewall_grant_access - Request firewall access rights and grant access. + * + * @firewall: Firewall reference containing the ID to check against its firewall + * controller + * + * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or + * appropriate errno code if error occurred + */ +int stm32_firewall_grant_access(struct stm32_firewall *firewall); + +/** + * stm32_firewall_release_access - Release access granted from a call to + * stm32_firewall_grant_access(). + * + * @firewall: Firewall reference containing the ID to check against its firewall + * controller + */ +void stm32_firewall_release_access(struct stm32_firewall *firewall); + +/** + * stm32_firewall_grant_access_by_id - Request firewall access rights of a given device + * based on a specific firewall ID + * + * Warnings: + * There is no way to ensure that the given ID will correspond to the firewall referenced in the + * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this + * function must be used with caution. + * This function should be used for subsystem resources that do not have the same firewall ID + * as their parent. + * U32_MAX is an invalid ID. + * + * @firewall: Firewall reference containing the firewall controller + * @subsystem_id: Firewall ID of the subsystem resource + * + * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or + * appropriate errno code if error occurred + */ +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id); + +/** + * stm32_firewall_release_access_by_id - Release access granted from a call to + * stm32_firewall_grant_access_by_id(). + * + * Warnings: + * There is no way to ensure that the given ID will correspond to the firewall referenced in the + * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this + * function must be used with caution. + * This function should be used for subsystem resources that do not have the same firewall ID + * as their parent. + * U32_MAX is an invalid ID. + * + * @firewall: Firewall reference containing the firewall controller + * @subsystem_id: Firewall ID of the subsystem resource + */ +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id); + +#else /* CONFIG_STM32_FIREWALL */ + +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall, + unsigned int nb_firewall); +{ + return -ENODEV; +} + +int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{ + return -ENODEV; +} + +void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +} + +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + return -ENODEV; +} + +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +} + +#endif /* CONFIG_STM32_FIREWALL */ +#endif /* STM32_FIREWALL_DEVICE_H */ From ef10bdf9c3e63fca765e57df1f5160faa6a7b947 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Fri, 29 Mar 2024 01:06:09 +0800 Subject: [PATCH 252/969] riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4], we remove the use of SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from now on. And allows ARCH_CANAAN to be selected for other Canaan SoCs. However, we should keep the config SOC_CANAAN and use def_bool to redirect the symbol temporarily to avoid potential conflict. Since we now have Canaan Kendryte K230 with MMU, ARCH_CANAAN is no longer referred to as K210. There are some special features for K210, like M-Mode No MMU and loader.bin in arch/riscv/Makefile. If we keep ARCH_CANAAN for other Canaan SoCs and remove the K210, the depends on !MMU in Kconfig may confuse some users who try to boot Kernel with MMU on K210, as Damien mentioned in the list [5]. Thus, we introduce a new symbol SOC_CANAAN_K210 for any conditional code or driver selection specific to the K210, so users will not try to build some K210-specific things when MMU is enabled and see it fails to boot on K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ [5] https://lore.kernel.org/linux-riscv/2b0511af-1b5b-4c90-a673-c9113bb58142@kernel.org/ Signed-off-by: Yangyu Chen Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 10 ++++++++-- arch/riscv/Makefile | 2 +- arch/riscv/configs/nommu_k210_defconfig | 3 ++- arch/riscv/configs/nommu_k210_sdcard_defconfig | 3 ++- 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 623de5f8a208..17340aa4dcfc 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -72,11 +72,17 @@ config SOC_VIRT This enables support for QEMU Virt Machine. config ARCH_CANAAN - def_bool SOC_CANAAN + bool "Canaan Kendryte SoC" + help + This enables support for Canaan Kendryte series SoC platform hardware. config SOC_CANAAN + def_bool SOC_CANAAN_K210 + depends on ARCH_CANAAN + +config SOC_CANAAN_K210 bool "Canaan Kendryte K210 SoC" - depends on !MMU + depends on !MMU && ARCH_CANAAN select CLINT_TIMER if RISCV_M_MODE select ARCH_HAS_RESET_CONTROLLER select PINCTRL diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 252d63942f34..fa6c389c3986 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -154,7 +154,7 @@ vdso-install-y += arch/riscv/kernel/vdso/vdso.so.dbg vdso-install-$(CONFIG_COMPAT) += arch/riscv/kernel/compat_vdso/compat_vdso.so.dbg:../compat_vdso/compat_vdso.so ifneq ($(CONFIG_XIP_KERNEL),y) -ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy) +ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN_K210),yy) KBUILD_IMAGE := $(boot)/loader.bin else ifeq ($(CONFIG_EFI_ZBOOT),) diff --git a/arch/riscv/configs/nommu_k210_defconfig b/arch/riscv/configs/nommu_k210_defconfig index 7e75200543f4..2552e78074a3 100644 --- a/arch/riscv/configs/nommu_k210_defconfig +++ b/arch/riscv/configs/nommu_k210_defconfig @@ -27,7 +27,8 @@ CONFIG_EXPERT=y CONFIG_SLUB=y CONFIG_SLUB_TINY=y # CONFIG_MMU is not set -CONFIG_SOC_CANAAN=y +CONFIG_ARCH_CANAAN=y +CONFIG_SOC_CANAAN_K210=y CONFIG_NONPORTABLE=y CONFIG_SMP=y CONFIG_NR_CPUS=2 diff --git a/arch/riscv/configs/nommu_k210_sdcard_defconfig b/arch/riscv/configs/nommu_k210_sdcard_defconfig index 0ba353e9ca71..8f67fb830585 100644 --- a/arch/riscv/configs/nommu_k210_sdcard_defconfig +++ b/arch/riscv/configs/nommu_k210_sdcard_defconfig @@ -19,7 +19,8 @@ CONFIG_EXPERT=y CONFIG_SLUB=y CONFIG_SLUB_TINY=y # CONFIG_MMU is not set -CONFIG_SOC_CANAAN=y +CONFIG_ARCH_CANAAN=y +CONFIG_SOC_CANAAN_K210=y CONFIG_NONPORTABLE=y CONFIG_SMP=y CONFIG_NR_CPUS=2 From 915fb0e31c5b894c0b06a030a087d1ed49a601ac Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Fri, 29 Mar 2024 01:06:10 +0800 Subject: [PATCH 253/969] soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4], we remove the use of SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from now on. Thus, we should also change the Makefile here to use ARCH_CANAAN. Then, since we have introduced SOC_CANAAN_K210 for K210-specific drivers, we should replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ Signed-off-by: Yangyu Chen Acked-by: Guo Ren Signed-off-by: Conor Dooley --- drivers/soc/Makefile | 2 +- drivers/soc/canaan/Kconfig | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index ba8f5b5460e1..fb2bd31387d0 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -7,7 +7,7 @@ obj-y += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ -obj-$(CONFIG_SOC_CANAAN) += canaan/ +obj-$(CONFIG_ARCH_CANAAN) += canaan/ obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/ diff --git a/drivers/soc/canaan/Kconfig b/drivers/soc/canaan/Kconfig index 43ced2bf8444..3121d351fea6 100644 --- a/drivers/soc/canaan/Kconfig +++ b/drivers/soc/canaan/Kconfig @@ -2,9 +2,9 @@ config SOC_K210_SYSCTL bool "Canaan Kendryte K210 SoC system controller" - depends on RISCV && SOC_CANAAN && OF + depends on RISCV && SOC_CANAAN_K210 && OF depends on COMMON_CLK_K210 - default SOC_CANAAN + default SOC_CANAAN_K210 select PM select MFD_SYSCON help From 8e5b7234ded5d2f1de4f4a7960cfebac17c6e656 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Fri, 29 Mar 2024 01:06:11 +0800 Subject: [PATCH 254/969] clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ Signed-off-by: Yangyu Chen Acked-by: Stephen Boyd Signed-off-by: Conor Dooley --- drivers/clk/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 50af5fc7f570..7517a0dfd15c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -451,8 +451,8 @@ config COMMON_CLK_FIXED_MMIO config COMMON_CLK_K210 bool "Clock driver for the Canaan Kendryte K210 SoC" - depends on OF && RISCV && SOC_CANAAN - default SOC_CANAAN + depends on OF && RISCV && SOC_CANAAN_K210 + default SOC_CANAAN_K210 help Support for the Canaan Kendryte K210 RISC-V SoC clocks. From c1556a9b426eb8af5606c67291c7f3025fbe2af9 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Fri, 29 Mar 2024 01:06:12 +0800 Subject: [PATCH 255/969] pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ Signed-off-by: Yangyu Chen Acked-by: Linus Walleij Signed-off-by: Conor Dooley --- drivers/pinctrl/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index d45657aa986a..1be05efccc29 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -235,13 +235,13 @@ config PINCTRL_INGENIC config PINCTRL_K210 bool "Pinctrl driver for the Canaan Kendryte K210 SoC" - depends on RISCV && SOC_CANAAN && OF + depends on RISCV && SOC_CANAAN_K210 && OF select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF select GPIOLIB select OF_GPIO select REGMAP_MMIO - default SOC_CANAAN + default SOC_CANAAN_K210 help Add support for the Canaan Kendryte K210 RISC-V SOC Field Programmable IO Array (FPIOA) controller. From 68f41105ea07d4be68e77666fcebbd34ea3612a8 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Fri, 29 Mar 2024 01:06:13 +0800 Subject: [PATCH 256/969] reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 Since SOC_FOO should be deprecated from patch [1], and cleanup for other SoCs is already in the mailing list [2,3,4,5], we remove the use of SOC_CANAAN and introduced SOC_CANAAN_K210 for K210-specific drivers, Thus, we replace its drivers depends on SOC_CANAAN_K210 and default select when it has the symbol SOC_CANAAN_K210. [1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/ [2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ [3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/ [4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/ [5] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/ Signed-off-by: Yangyu Chen Acked-by: Philipp Zabel Signed-off-by: Conor Dooley --- drivers/reset/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 85b27c42cf65..7112f5932609 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -103,9 +103,9 @@ config RESET_INTEL_GW config RESET_K210 bool "Reset controller driver for Canaan Kendryte K210 SoC" - depends on (SOC_CANAAN || COMPILE_TEST) && OF + depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF select MFD_SYSCON - default SOC_CANAAN + default SOC_CANAAN_K210 help Support for the Canaan Kendryte K210 RISC-V SoC reset controller. Say Y if you want to control reset signals provided by this From 0eea987088a22d73d81e968de7347cdc7e594f72 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 5 Apr 2024 16:46:18 +0100 Subject: [PATCH 257/969] RISC-V: Drop unused SOC_CANAAN All users of SOC_CANAAN are now gone and it is not user-visible, remove it. Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 17340aa4dcfc..a4468deef99f 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -76,10 +76,6 @@ config ARCH_CANAAN help This enables support for Canaan Kendryte series SoC platform hardware. -config SOC_CANAAN - def_bool SOC_CANAAN_K210 - depends on ARCH_CANAAN - config SOC_CANAAN_K210 bool "Canaan Kendryte K210 SoC" depends on !MMU && ARCH_CANAAN From cad23ffd46e2205582f5a9e9014b3d78ec0256db Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 18 Mar 2024 10:24:41 +0100 Subject: [PATCH 258/969] ARM: dts: qcom: msm8974: Add @0 to memory node name Add the @0 from reg to the node name, so that both dtc warning and dt validation failure get resolved. arch/arm/boot/dts/qcom/qcom-msm8974.dtsi:106.9-109.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name [..]/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dtb: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0]]} from schema $id: http://devicetree.org/schemas/root-node.yaml# Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240318-msm8974-misc2-v1-1-f71668a2b8cd@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 233d9bf42298..f9c3726efe74 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -103,7 +103,7 @@ }; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0>; }; From 7018981366d496db4b7d5f6a5c2673683d2b1639 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 18 Mar 2024 10:24:42 +0100 Subject: [PATCH 259/969] ARM: dts: qcom: msm8974: Add empty chosen node Add an empty /chosen node to the dtsi like is common on most other Qualcomm SoC files, so that various pieces of software expecting this node to exist don't complain. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240318-msm8974-misc2-v1-2-f71668a2b8cd@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index f9c3726efe74..5651bb31bd54 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -14,6 +14,8 @@ #size-cells = <1>; interrupt-parent = <&intc>; + chosen { }; + clocks { xo_board: xo_board { compatible = "fixed-clock"; From 4785ec47ec890fe66f31ee886a767dbdf2ea6bae Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Sun, 7 Apr 2024 11:05:10 +0200 Subject: [PATCH 260/969] dt-bindings: arm: qcom: Add Motorola Moto G (2013) Document the Motorola Moto G (2013), which is a smartphone based on the Qualcomm MSM8226 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/32c507337ab80c550fb1df08f7014d1e31eb4c32.1712480582.git.stano.jakubek@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 66beaac60e1d..d2910982ae86 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -137,6 +137,7 @@ properties: - microsoft,dempsey - microsoft,makepeace - microsoft,moneypenny + - motorola,falcon - samsung,s3ve3g - const: qcom,msm8226 From 49481b6a8f35017af23e9fdfb644095f50a474e3 Mon Sep 17 00:00:00 2001 From: Stanislav Jakubek Date: Sun, 7 Apr 2024 11:05:42 +0200 Subject: [PATCH 261/969] ARM: dts: qcom: Add support for Motorola Moto G (2013) Add a device tree for the Motorola Moto G (2013) smartphone based on the Qualcomm MSM8226 SoC. Initially supported features: - Buttons (Volume Down/Up, Power) - eMMC - Hall Effect Sensor - SimpleFB display - TMP108 temperature sensor - Vibrator Note: the dhob and shob reserved-memory regions are seemingly a part of some Motorola specific (firmware?) mechanism, see [1]. [1] https://github.com/LineageOS/android_kernel_motorola_msm8226/blob/cm-14.1/Documentation/devicetree/bindings/misc/hob_ram.txt Reviewed-by: Konrad Dybcio Signed-off-by: Stanislav Jakubek Link: https://lore.kernel.org/r/ef86e9c84b082f7549f2ca825adfb5cbea640637.1712480582.git.stano.jakubek@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8226-motorola-falcon.dts | 359 ++++++++++++++++++ 2 files changed, 360 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index de5b0d282e74..5d5df062b8a0 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += \ + msm8226-motorola-falcon.dtb \ qcom-apq8016-sbc.dtb \ qcom-apq8026-asus-sparrow.dtb \ qcom-apq8026-huawei-sturgeon.dtb \ diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts new file mode 100644 index 000000000000..029e1b1659c9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &smem_region; + +/ { + model = "Motorola Moto G (2013)"; + compatible = "motorola,falcon", "qcom,msm8226"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + vsp-supply = <®_lcd_pos>; + vsn-supply = <®_lcd_neg>; + vddio-supply = <&vddio_disp_vreg>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + vddio_disp_vreg: regulator-vddio-disp { + compatible = "regulator-fixed"; + regulator-name = "vddio_disp"; + gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; + vin-supply = <&pm8226_l8>; + startup-delay-us = <300>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + + dhob@f500000 { + reg = <0x0f500000 0x40000>; + no-map; + }; + + shob@f540000 { + reg = <0x0f540000 0x2000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + /* Actually <0x0fa00000 0x500000>, but first 100000 is smem */ + reserved@fb00000 { + reg = <0x0fb00000 0x400000>; + no-map; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + pinctrl-0 = <®_lcd_default>; + pinctrl-names = "default"; + + reg_lcd_pos: outp { + regulator-name = "outp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + }; + + reg_lcd_neg: outn { + regulator-name = "outn"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>; + }; + }; + + temperature-sensor@48 { + compatible = "ti,tmp108"; + reg = <0x48>; + interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&temp_alert_default>; + pinctrl-names = "default"; + #thermal-sensor-cells = <0>; + }; +}; + +&pm8226_resin { + linux,code = ; + status = "okay"; +}; + +&pm8226_vib { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + pm8226_lvs1: lvs1 { + regulator-always-on; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&smbb { + qcom,fast-charge-safe-current = <2000000>; + qcom,fast-charge-current-limit = <1900000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,minimum-input-voltage = <4300000>; + + status = "okay"; +}; + +&tlmm { + reg_lcd_default: reg-lcd-default-state { + pins = "gpio31", "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + reg_vddio_disp_default: reg-vddio-disp-default-state { + pins = "gpio34"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + temp_alert_default: temp-alert-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; +}; + +&usb { + extcon = <&smbb>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; From 2338f4315f16b937e924ff679b91bb8c0ab53f25 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sun, 11 Feb 2024 21:26:55 +0100 Subject: [PATCH 262/969] ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes Add QCA8075 PHY Package nodes. The PHY nodes that were previously defined never worked and actually never had a driver to correctly setup these PHY. Now that we have a correct driver, correctly add the PHY Package node and set the default value of 300mw for tx driver strength following specification of ipq4019 SoC. Signed-off-by: Christian Marangi Link: https://lore.kernel.org/r/20240211202700.17810-1-ansuelsmth@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 35 +++++++++++++++--------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 681cb3fc8085..b198e2af5158 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -598,24 +598,33 @@ reg = <0x90000 0x64>; status = "disabled"; - ethphy0: ethernet-phy@0 { + ethernet-phy-package@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,qca8075-package"; reg = <0>; - }; - ethphy1: ethernet-phy@1 { - reg = <1>; - }; + qcom,tx-drive-strength-milliwatt = <300>; - ethphy2: ethernet-phy@2 { - reg = <2>; - }; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; - ethphy3: ethernet-phy@3 { - reg = <3>; - }; + ethphy1: ethernet-phy@1 { + reg = <1>; + }; - ethphy4: ethernet-phy@4 { - reg = <4>; + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; + }; }; }; From 428a575dc9038846ad259466d5ba109858c0a023 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Mon, 19 Feb 2024 23:05:26 +0800 Subject: [PATCH 263/969] arm64: dts: hi3798cv200: fix the size of GICR During boot, Linux kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set This SoC is using a regular GIC-400 and the GICR space size should be 8KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240219-cache-v3-1-a33c57534ae9@outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Mon, 19 Feb 2024 23:05:27 +0800 Subject: [PATCH 264/969] arm64: dts: hi3798cv200: add GICH, GICV register space and irq This is needed by KVM to make use of VGIC code. Just like regular GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been verified. Signed-off-by: Yang Xiwen Link: https://lore.kernel.org/r/20240219-cache-v3-2-a33c57534ae9@outlook.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index d01023401d7e..fc64d2fa99eb 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,11 @@ gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x2000>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>, /* GICC */ + <0x0 0xf1004000 0x0 0x2000>, /* GICH */ + <0x0 0xf1006000 0x0 0x2000>; /* GICV */ + interrupts = ; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; From c7a3ad884d1dc1302dcc3295baa18917180b8bec Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Mon, 19 Feb 2024 23:05:28 +0800 Subject: [PATCH 265/969] arm64: dts: hi3798cv200: add cache info During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Signed-off-by: Yang Xiwen Link: https://lore.kernel.org/r/20240219-cache-v3-3-a33c57534ae9@outlook.com [krzysztof: drop Fixes/cc-stable, because this is a missing feature, not a fix] Signed-off-by: Krzysztof Kozlowski --- .../arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index fc64d2fa99eb..f6bc001c3832 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@1 { @@ -38,6 +45,13 @@ device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@2 { @@ -45,6 +59,13 @@ device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@3 { @@ -52,9 +73,25 @@ device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; }; + L2: l2-cache { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ From ec78ed2e157ea6d4b66869c8a3dbe4dbac0593c6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 2 Apr 2024 12:21:52 +0200 Subject: [PATCH 266/969] ARM: shmobile: defconfig: Refresh for v6.9-rc1 Refresh the defconfig for Renesas ARM systems: - Move CONFIG_DRM_PANEL_SIMPLE (moved in commit aaf7f80996834ae5 ("drm/panel: re-alphabetize the menu list")), - Enable warn on W+X mappings at boot (recommended, renamed in commit a90f0a02f139a13d ("arm: ptdump: rename CONFIG_DEBUG_WX to CONFIG_ARM_DEBUG_WX")). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b2e6306a58e18136c05668dbbe9e839efdbe463e.1712053238.git.geert+renesas@glider.be --- arch/arm/configs/shmobile_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 091e1840933c..56925adfe842 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -139,8 +139,8 @@ CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_RCAR_DU=y # CONFIG_DRM_RCAR_USE_MIPI_DSI is not set CONFIG_DRM_SHMOBILE=y -CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_LVDS_CODEC=y CONFIG_DRM_SII902X=y @@ -235,3 +235,4 @@ CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_FS=y +CONFIG_ARM_DEBUG_WX=y From cc0e7a8911f2b2edc96fb343967f019574621eb7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 2 Apr 2024 15:36:42 +0200 Subject: [PATCH 267/969] ARM: dts: renesas: r9a06g032: Remove duplicate interrupt-parent As the "soc" node already specifies the GIC as the interrupt-parent, there is no reason to repeat this in any of its subnodes. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/7ac440ec923f5d781a93c4344d6fedf280c3fa72.1712064816.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index fa63e1afc4ef..45f60eeeaaa1 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -319,7 +319,6 @@ gmac2: ethernet@44002000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44002000 0x2000>; - interrupt-parent = <&gic>; interrupts = , , ; From c16f166229d2a8301b3000d99d6a08120d15696c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 2 Apr 2024 16:34:56 +0200 Subject: [PATCH 268/969] arm64: dts: renesas: gray-hawk-single: Enable nfsroot Extend the default kernel command line for Gray Hawk Single for mounting the root filesystem via NFS, like is done for all other Renesas development boards. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/0c291919071350674648317f8cf3efbd1ca4475f.1712068442.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index acf1d625ec41..cfbe8c8680cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -23,7 +23,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; stdout-path = "serial0:921600n8"; }; From 1552e6ab5ee5e689efe7b35e9305c7bcf95d22f8 Mon Sep 17 00:00:00 2001 From: Thanh Quan Date: Tue, 2 Apr 2024 16:44:16 +0200 Subject: [PATCH 269/969] arm64: dts: renesas: r8a779h0: Add CMT nodes Add device nodes for the Compare Match Timer Type0 (CMT0) and Type1 (CMT1/2/3) instances on the R-Car V4M (R8A779H0) SoC. Signed-off-by: Thanh Quan Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/3c7821e051b880d46be5441dcb571f4c9d0ba408.1712068688.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 3a40b56c4dcf..e192588e0f68 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -303,6 +303,76 @@ resets = <&cpg 917>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a779h0-cmt0", + "renesas,rcar-gen4-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 910>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a779h0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 911>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a779h0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 912>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a779h0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 913>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 913>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779h0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From fdaf6a67806d14a8fd9b0f79416398b59e417861 Mon Sep 17 00:00:00 2001 From: Thanh Quan Date: Tue, 2 Apr 2024 16:44:17 +0200 Subject: [PATCH 270/969] arm64: dts: renesas: r8a779h0: Add TMU nodes Add device nodes for the Timer Units (TMU) on the R-Car V4M (R8A779H0) SoC. Signed-off-by: Thanh Quan Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/9b82bcb345f14ffd740156b6d41088e02d45e72d.1712068688.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 74 +++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index e192588e0f68..0e97799fa55a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -404,6 +404,80 @@ #thermal-sensor-cells = <1>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2"; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779h0", "renesas,rcar-gen4-i2c"; From 5d83b9cbe7cf40746948a419c5018f4d617a86fa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:10 +0200 Subject: [PATCH 271/969] arm64: dts: microchip: sparx5: fix mdio reg Correct the reg address of mdio node to match unit address. Assume the reg is not correct and unit address was correct, because there is already node using the existing reg 0x110102d4. sparx5.dtsi:443.25-451.5: Warning (simple_bus_reg): /axi@600000000/mdio@6110102f8: simple-bus unit address format error, expected "6110102d4" Fixes: d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") Reviewed-by: Horatiu Vultur Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 24075cd91420..5d820da8c69d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -447,7 +447,7 @@ pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; - reg = <0x6 0x110102d4 0x24>; + reg = <0x6 0x110102f8 0x24>; }; mdio3: mdio@61101031c { From 013627825bbe0e911f97b1d4a23f5507bfe1c42c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:11 +0200 Subject: [PATCH 272/969] arm64: dts: microchip: sparx5: correct serdes unit address Unit address should match "reg" property, as reported by dtc W=1 warnings: sparx5.dtsi:463.27-468.5: Warning (simple_bus_reg): /axi@600000000/serdes@10808000: simple-bus unit address format error, expected "610808000" Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 5d820da8c69d..c3029e0abacc 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -460,7 +460,7 @@ reg = <0x6 0x1101031c 0x24>; }; - serdes: serdes@10808000 { + serdes: serdes@610808000 { compatible = "microchip,sparx5-serdes"; #phy-cells = <1>; clocks = <&sys_clk>; From 9dcf4ec577005120bc7f565c0dcbefacbcb3f313 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:12 +0200 Subject: [PATCH 273/969] arm64: dts: microchip: sparx5_pcb134: add missing I2C mux unit addresses The children of I2C mux should be named "i2c", according to DT schema and bindings, and they should have unit address. This fixes dtbs_check warnings like: sparx5_pcb134_emmc.dtb: i2c0-imux@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c_sfp1', ... and dtc W=1 warnings: sparx5_pcb134_board.dtsi:548.23-555.4: Warning (simple_bus_reg): /axi@600000000/sfp-eth12: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- .../dts/microchip/sparx5_pcb134_board.dtsi | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f3e226de5e5e..e816e6e9d62d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -427,62 +427,62 @@ pinctrl-10 = <&i2cmux_10>; pinctrl-11 = <&i2cmux_11>; pinctrl-12 = <&i2cmux_pins_i>; - i2c_sfp1: i2c_sfp1 { + i2c_sfp1: i2c@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp2: i2c_sfp2 { + i2c_sfp2: i2c@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp3: i2c_sfp3 { + i2c_sfp3: i2c@2 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp4: i2c_sfp4 { + i2c_sfp4: i2c@3 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp5: i2c_sfp5 { + i2c_sfp5: i2c@4 { reg = <0x4>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp6: i2c_sfp6 { + i2c_sfp6: i2c@5 { reg = <0x5>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp7: i2c_sfp7 { + i2c_sfp7: i2c@6 { reg = <0x6>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp8: i2c_sfp8 { + i2c_sfp8: i2c@7 { reg = <0x7>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp9: i2c_sfp9 { + i2c_sfp9: i2c@8 { reg = <0x8>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp10: i2c_sfp10 { + i2c_sfp10: i2c@9 { reg = <0x9>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp11: i2c_sfp11 { + i2c_sfp11: i2c@a { reg = <0xa>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp12: i2c_sfp12 { + i2c_sfp12: i2c@b { reg = <0xb>; #address-cells = <1>; #size-cells = <0>; @@ -495,42 +495,42 @@ &gpio 61 GPIO_ACTIVE_HIGH &gpio 54 GPIO_ACTIVE_HIGH>; idle-state = <0x8>; - i2c_sfp13: i2c_sfp13 { + i2c_sfp13: i2c@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp14: i2c_sfp14 { + i2c_sfp14: i2c@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp15: i2c_sfp15 { + i2c_sfp15: i2c@2 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp16: i2c_sfp16 { + i2c_sfp16: i2c@3 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp17: i2c_sfp17 { + i2c_sfp17: i2c@4 { reg = <0x4>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp18: i2c_sfp18 { + i2c_sfp18: i2c@5 { reg = <0x5>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp19: i2c_sfp19 { + i2c_sfp19: i2c@6 { reg = <0x6>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp20: i2c_sfp20 { + i2c_sfp20: i2c@7 { reg = <0x7>; #address-cells = <1>; #size-cells = <0>; From 5150c3df4c2e4570826c96e98f5da2ac7ffd9646 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:13 +0200 Subject: [PATCH 274/969] arm64: dts: microchip: sparx5_pcb135: add missing I2C mux unit addresses The children of I2C mux should be named "i2c", according to DT schema and bindings, and they should have unit address. This fixes dtbs_check warnings like: sparx5_pcb135.dtb: i2c0-imux@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c_sfp1', 'i2c_sfp2', 'i2c_sfp3', 'i2c_sfp4' were unexpected) and dtc W=1 warnings: sparx5_pcb135_board.dtsi:172.23-180.4: Warning (simple_bus_reg): /axi@600000000/sfp-eth60: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 82ce007d9959..bf51a6e11cf1 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -146,22 +146,22 @@ pinctrl-2 = <&i2cmux_s31>; pinctrl-3 = <&i2cmux_s32>; pinctrl-4 = <&i2cmux_pins_i>; - i2c_sfp1: i2c_sfp1 { + i2c_sfp1: i2c@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp2: i2c_sfp2 { + i2c_sfp2: i2c@1 { reg = <0x1>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp3: i2c_sfp3 { + i2c_sfp3: i2c@2 { reg = <0x2>; #address-cells = <1>; #size-cells = <0>; }; - i2c_sfp4: i2c_sfp4 { + i2c_sfp4: i2c@3 { reg = <0x3>; #address-cells = <1>; #size-cells = <0>; From d3dd7bed42102704133b3569a4392f9aab6844ff Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:14 +0200 Subject: [PATCH 275/969] arm64: dts: microchip: sparx5_pcb134: align I2C mux node name with bindings DT schema expects node names to match certain. This fixes dtbs_check warnings like: sparx5_pcb134_emmc.dtb: i2c0-emux@0: $nodename:0: 'i2c0-emux@0' does not match '^(i2c-?)?mux' and dtc W=1 warnings: sparx5_pcb134_board.dtsi:398.25-403.4: Warning (unique_unit_address_if_enabled): /axi@600000000/i2c0-imux@0: duplicate unit-address (also used in node /axi@600000000/i2c0-emux@0) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index e816e6e9d62d..cafec6ef0d0f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -395,13 +395,13 @@ }; &axi { - i2c0_imux: i2c0-imux@0 { + i2c0_imux: i2c-mux-0 { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; #size-cells = <0>; i2c-parent = <&i2c0>; }; - i2c0_emux: i2c0-emux@0 { + i2c0_emux: i2c-mux-1 { compatible = "i2c-mux-gpio"; #address-cells = <1>; #size-cells = <0>; From b0d5a3ce782a5d38091dd5163e17b7100c6289f5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:15 +0200 Subject: [PATCH 276/969] arm64: dts: microchip: sparx5_pcb135: align I2C mux node name with bindings DT schema expects node names to match certain. This fixes dtbs_check warnings like: sparx5_pcb135_emmc.dtb: i2c0-imux@0: $nodename:0: 'i2c0-imux@0' does not match '^(i2c-?)?mux' and dtc W=1 warnings: sparx5_pcb135_board.dtsi:132.25-137.4: Warning (simple_bus_reg): /axi@600000000/i2c0-imux@0: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index bf51a6e11cf1..860975ffe0a1 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -129,7 +129,7 @@ }; &axi { - i2c0_imux: i2c0-imux@0 { + i2c0_imux: i2c-mux { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; #size-cells = <0>; From 55fb5a97ebe0ab763dc0526ac7ff626815a241a3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:16 +0200 Subject: [PATCH 277/969] arm64: dts: microchip: sparx5_pcb134: drop LED unit addresses GPIO leds should not have unit addresses (no "reg" property), as reported by dtc W=1 warnings: sparx5_pcb134_board.dtsi:18.9-21.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- .../dts/microchip/sparx5_pcb134_board.dtsi | 96 +++++++++---------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index cafec6ef0d0f..f165a409bc1d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -15,234 +15,234 @@ leds { compatible = "gpio-leds"; - led@0 { + led-0 { label = "twr0:green"; gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; }; - led@1 { + led-1 { label = "twr0:yellow"; gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; }; - led@2 { + led-2 { label = "twr1:green"; gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; }; - led@3 { + led-3 { label = "twr1:yellow"; gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; }; - led@4 { + led-4 { label = "twr2:green"; gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; }; - led@5 { + led-5 { label = "twr2:yellow"; gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; }; - led@6 { + led-6 { label = "twr3:green"; gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; }; - led@7 { + led-7 { label = "twr3:yellow"; gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; }; - led@8 { + led-8 { label = "eth12:green"; gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@9 { + led-9 { label = "eth12:yellow"; gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@10 { + led-10 { label = "eth13:green"; gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@11 { + led-11 { label = "eth13:yellow"; gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@12 { + led-12 { label = "eth14:green"; gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@13 { + led-13 { label = "eth14:yellow"; gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@14 { + led-14 { label = "eth15:green"; gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@15 { + led-15 { label = "eth15:yellow"; gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@16 { + led-16 { label = "eth48:green"; gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@17 { + led-17 { label = "eth48:yellow"; gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@18 { + led-18 { label = "eth49:green"; gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@19 { + led-19 { label = "eth49:yellow"; gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@20 { + led-20 { label = "eth50:green"; gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@21 { + led-21 { label = "eth50:yellow"; gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@22 { + led-22 { label = "eth51:green"; gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@23 { + led-23 { label = "eth51:yellow"; gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@24 { + led-24 { label = "eth52:green"; gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@25 { + led-25 { label = "eth52:yellow"; gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@26 { + led-26 { label = "eth53:green"; gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@27 { + led-27 { label = "eth53:yellow"; gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@28 { + led-28 { label = "eth54:green"; gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@29 { + led-29 { label = "eth54:yellow"; gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@30 { + led-30 { label = "eth55:green"; gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@31 { + led-31 { label = "eth55:yellow"; gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@32 { + led-32 { label = "eth56:green"; gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@33 { + led-33 { label = "eth56:yellow"; gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@34 { + led-34 { label = "eth57:green"; gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@35 { + led-35 { label = "eth57:yellow"; gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@36 { + led-36 { label = "eth58:green"; gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@37 { + led-37 { label = "eth58:yellow"; gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@38 { + led-38 { label = "eth59:green"; gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@39 { + led-39 { label = "eth59:yellow"; gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@40 { + led-40 { label = "eth60:green"; gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@41 { + led-41 { label = "eth60:yellow"; gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@42 { + led-42 { label = "eth61:green"; gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@43 { + led-43 { label = "eth61:yellow"; gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@44 { + led-44 { label = "eth62:green"; gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@45 { + led-45 { label = "eth62:yellow"; gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@46 { + led-46 { label = "eth63:green"; gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@47 { + led-47 { label = "eth63:yellow"; gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; default-state = "off"; From 5945df4de0e2117edccc65ebbfd6d21f01967cd5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:17 +0200 Subject: [PATCH 278/969] arm64: dts: microchip: sparx5_pcb135: drop LED unit addresses GPIO leds should not have unit addresses (no "reg" property), as reported by dtc W=1 warnings: sparx5_pcb135_board.dtsi:18.9-22.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 860975ffe0a1..20016efb3656 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -15,42 +15,42 @@ leds { compatible = "gpio-leds"; - led@0 { + led-0 { label = "eth60:yellow"; gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@1 { + led-1 { label = "eth60:green"; gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@2 { + led-2 { label = "eth61:yellow"; gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@3 { + led-3 { label = "eth61:green"; gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@4 { + led-4 { label = "eth62:yellow"; gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@5 { + led-5 { label = "eth62:green"; gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@6 { + led-6 { label = "eth63:yellow"; gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@7 { + led-7 { label = "eth63:green"; gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; default-state = "off"; From f1595d501ea49ea49ff0e4a6beec4929c1618cb3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:18 +0200 Subject: [PATCH 279/969] arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash Since beginning the DTS extended the SPI0 in two places adding two SPI muxes, each with same SPI NOR flash. Both used exactly the same chip-selects, so this was clearly buggy code. Then in commit d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI mux was removed, while keeping the SPI NOR flash node. This still leaves duplicated SPI nodes under same chip select 0, reported by dtc W=1 warnings: sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0) Steen Hegelund confirmed that in fact there is a SPI mux, thus remove the duplicated node without the mux. Signed-off-by: Krzysztof Kozlowski Tested-by: Steen Hegelund Reviewed-by: Steen Hegelund Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f165a409bc1d..2c5574734c9e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -272,15 +272,6 @@ }; }; -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0>; - }; -}; - &spi0 { status = "okay"; spi@0 { From 6c7c4b91aa43543c9f967120a6eabd451a0927d4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 21:04:19 +0200 Subject: [PATCH 280/969] arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash Since beginning the DTS extended the SPI0 in two places adding two SPI muxes, each with same SPI NOR flash. Both used exactly the same chip-selects, so this was clearly buggy code. Then in commit d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI mux was removed, while keeping the SPI NOR flash node. This still leaves duplicated SPI nodes under same chip select 0, reported by dtc W=1 warnings: sparx5_pcb135_board.dtsi:92.10-96.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0) Steen Hegelund confirmed that in fact there is a SPI mux, thus remove the duplicated node without the mux. Signed-off-by: Krzysztof Kozlowski Tested-by: Steen Hegelund Reviewed-by: Steen Hegelund Signed-off-by: Conor Dooley --- arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 20016efb3656..af2f1831f07f 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -87,15 +87,6 @@ }; }; -&spi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <8000000>; - reg = <0>; - }; -}; - &spi0 { status = "okay"; spi@0 { From be4e4dd8a1994e5730dfdb8dfaf1f2418f8a199d Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 28 Mar 2024 08:57:38 +0200 Subject: [PATCH 281/969] arm64: dts: renesas: rzg3s-smarc-som: Fix Ethernet aliases Fix typos in the Ethernet aliases. U-Boot uses the ethernetX (X={0, 1, ..., N}) aliases to update the DTB with the MAC addresses. The ethernetX or ethX aliases are not used by the Linux RAVB driver. Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces") Suggested-by: Biju Das Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240328065738.3049316-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index acac4666ae59..1f87150a2e0a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -36,8 +36,8 @@ #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; #else - eth0 = ð0; - eth1 = ð1; + ethernet0 = ð0; + ethernet1 = ð1; #endif }; From 5aa5c7b9a09dfce2761c46579cc421708492e890 Mon Sep 17 00:00:00 2001 From: Sangyun Kim Date: Sat, 6 Apr 2024 16:44:49 +0900 Subject: [PATCH 282/969] mm/slub: remove duplicate initialization for early_kmem_cache_node_alloc() The struct track for every object in a new slab is already set up by new_slab(), so remove the duplicate initialization in early_kmem_cache_node_alloc(). Co-developed-by: Hyunmin Lee Signed-off-by: Hyunmin Lee Co-developed-by: Jeungwoo Yoo Signed-off-by: Jeungwoo Yoo Signed-off-by: Sangyun Kim Cc: Gwan-gyeong Mun Signed-off-by: Vlastimil Babka --- mm/slub.c | 1 - 1 file changed, 1 deletion(-) diff --git a/mm/slub.c b/mm/slub.c index f4fd460854fd..a30bd2157c07 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -4877,7 +4877,6 @@ static void early_kmem_cache_node_alloc(int node) BUG_ON(!n); #ifdef CONFIG_SLUB_DEBUG init_object(kmem_cache_node, n, SLUB_RED_ACTIVE); - init_tracking(kmem_cache_node, n); #endif n = kasan_slab_alloc(kmem_cache_node, n, GFP_KERNEL, false); slab->freelist = get_freepointer(kmem_cache_node, n); From 3183059ad82a0daa8292daf43c325bac57daceb5 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Tue, 27 Feb 2024 15:07:25 -0800 Subject: [PATCH 283/969] rcu: Add lockdep checks and kernel-doc header to rcu_softirq_qs() There is some indications that rcu_softirq_qs() might be more generally used than anticipated. This commit therefore adds some lockdep assertions and some cautionary tales in a new kernel-doc header. Link: https://lore.kernel.org/all/Zd4DXTyCf17lcTfq@debian.debian/ Signed-off-by: Paul E. McKenney Cc: Eric Dumazet Cc: Jakub Kicinski Cc: "David S. Miller" Cc: Yan Zhai Cc: Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index d9642dd06c25..2795a1457acf 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -240,8 +240,36 @@ static long rcu_get_n_cbs_cpu(int cpu) return 0; } +/** + * rcu_softirq_qs - Provide a set of RCU quiescent states in softirq processing + * + * Mark a quiescent state for RCU, Tasks RCU, and Tasks Trace RCU. + * This is a special-purpose function to be used in the softirq + * infrastructure and perhaps the occasional long-running softirq + * handler. + * + * Note that from RCU's viewpoint, a call to rcu_softirq_qs() is + * equivalent to momentarily completely enabling preemption. For + * example, given this code:: + * + * local_bh_disable(); + * do_something(); + * rcu_softirq_qs(); // A + * do_something_else(); + * local_bh_enable(); // B + * + * A call to synchronize_rcu() that began concurrently with the + * call to do_something() would be guaranteed to wait only until + * execution reached statement A. Without that rcu_softirq_qs(), + * that same synchronize_rcu() would instead be guaranteed to wait + * until execution reached statement B. + */ void rcu_softirq_qs(void) { + RCU_LOCKDEP_WARN(lock_is_held(&rcu_bh_lock_map) || + lock_is_held(&rcu_lock_map) || + lock_is_held(&rcu_sched_lock_map), + "Illegal rcu_softirq_qs() in RCU read-side critical section"); rcu_qs(); rcu_preempt_deferred_qs(current); rcu_tasks_qs(current, false); From 1a140b46da8f3be8e55fbd0950653c9a235b6ce9 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Sat, 17 Feb 2024 17:57:35 -0800 Subject: [PATCH 284/969] rcutorture: Enable RCU priority boosting for TREE09 The TREE09 rcutorture scenario exhausts memory from time to time, and this is due to a reader being preempted and blocking grace periods, thus preventing recycling of the memory used in callback-flooding tests. This commit therefore enables RCU priority boosting and sets the boosting delay to 100 milliseconds after grace-period start. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- tools/testing/selftests/rcutorture/configs/rcu/TREE09 | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/rcutorture/configs/rcu/TREE09 b/tools/testing/selftests/rcutorture/configs/rcu/TREE09 index fc45645bb5f4..9ecd1b4e653d 100644 --- a/tools/testing/selftests/rcutorture/configs/rcu/TREE09 +++ b/tools/testing/selftests/rcutorture/configs/rcu/TREE09 @@ -10,8 +10,9 @@ CONFIG_NO_HZ_FULL=n CONFIG_RCU_TRACE=n CONFIG_RCU_NOCB_CPU=n CONFIG_DEBUG_LOCK_ALLOC=n -CONFIG_RCU_BOOST=n +CONFIG_RCU_BOOST=y +CONFIG_RCU_BOOST_DELAY=100 CONFIG_DEBUG_OBJECTS_RCU_HEAD=n -#CHECK#CONFIG_RCU_EXPERT=n +CONFIG_RCU_EXPERT=y CONFIG_KPROBES=n CONFIG_FTRACE=n From 0a0467af0a4d8b4e3832945d1cc287d1cb52573e Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 19 Feb 2024 17:00:31 -0800 Subject: [PATCH 285/969] rcutorture: Dump # online CPUs on insufficient cb-flood laundering This commit adds the number of online CPUs to the state dump following an unsuccesful callback-flood test. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 45d6b4c3d199..6611ef3e71c3 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -2833,12 +2833,12 @@ static void rcu_torture_fwd_prog_cr(struct rcu_fwd *rfp) if (!torture_must_stop() && !READ_ONCE(rcu_fwd_emergency_stop) && !shutdown_time_arrived()) { WARN_ON(n_max_gps < MIN_FWD_CBS_LAUNDERED); - pr_alert("%s Duration %lu barrier: %lu pending %ld n_launders: %ld n_launders_sa: %ld n_max_gps: %ld n_max_cbs: %ld cver %ld gps %ld\n", + pr_alert("%s Duration %lu barrier: %lu pending %ld n_launders: %ld n_launders_sa: %ld n_max_gps: %ld n_max_cbs: %ld cver %ld gps %ld #online %u\n", __func__, stoppedat - rfp->rcu_fwd_startat, jiffies - stoppedat, n_launders + n_max_cbs - n_launders_cb_snap, n_launders, n_launders_sa, - n_max_gps, n_max_cbs, cver, gps); + n_max_gps, n_max_cbs, cver, gps, num_online_cpus()); atomic_long_add(n_max_cbs, &rcu_fwd_max_cbs); mutex_lock(&rcu_fwd_mutex); // Serialize histograms. rcu_torture_fwd_cb_hist(rfp); From f8039457eedc378fa7a186054ee3032b8a41eaee Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Sun, 18 Feb 2024 09:11:08 -0800 Subject: [PATCH 286/969] rcutorture: Dump GP kthread state on insufficient cb-flood laundering If a callback flood prevents grace period from completing, rcutorture does a WARN_ON(). Avoiding this WARN_ON() currently requires that at least three grace periods elapse during an eight-second callback-flood interval. Unfortunately, the current debug information does not include anything about the grace-period state. This commit therefore adds a call to cur_ops->gp_kthread_dbg(), if this function pointer is non-NULL. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 6611ef3e71c3..eff51a26216f 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -2832,7 +2832,8 @@ static void rcu_torture_fwd_prog_cr(struct rcu_fwd *rfp) if (!torture_must_stop() && !READ_ONCE(rcu_fwd_emergency_stop) && !shutdown_time_arrived()) { - WARN_ON(n_max_gps < MIN_FWD_CBS_LAUNDERED); + if (WARN_ON(n_max_gps < MIN_FWD_CBS_LAUNDERED) && cur_ops->gp_kthread_dbg) + cur_ops->gp_kthread_dbg(); pr_alert("%s Duration %lu barrier: %lu pending %ld n_launders: %ld n_launders_sa: %ld n_max_gps: %ld n_max_cbs: %ld cver %ld gps %ld #online %u\n", __func__, stoppedat - rfp->rcu_fwd_startat, jiffies - stoppedat, From c507e195016ccca18e375d14cfeb1186dac60b2c Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 6 Mar 2024 17:00:39 -0800 Subject: [PATCH 287/969] rcutorture: ASSERT_EXCLUSIVE_WRITER() for ->rtort_pipe_count updates It turns out that only one CPU at a time will ever invoke rcu_torture_pipe_update_one() on a given rcu_torture structure. This commit therefore adds three ASSERT_EXCLUSIVE_WRITER() calls to enlist KCSAN's aid in checking this. Signed-off-by: Paul E. McKenney Cc: Linus Torvalds Reviewed-by: Joel Fernandes (Google) Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index eff51a26216f..d8c12eba35b7 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -466,6 +466,7 @@ rcu_torture_pipe_update_one(struct rcu_torture *rp) i = RCU_TORTURE_PIPE_LEN; atomic_inc(&rcu_torture_wcount[i]); WRITE_ONCE(rp->rtort_pipe_count, i + 1); + ASSERT_EXCLUSIVE_WRITER(rp->rtort_pipe_count); if (rp->rtort_pipe_count >= RCU_TORTURE_PIPE_LEN) { rp->rtort_mbtest = 0; return true; @@ -1399,6 +1400,7 @@ rcu_torture_writer(void *arg) if (rp == NULL) continue; rp->rtort_pipe_count = 0; + ASSERT_EXCLUSIVE_WRITER(rp->rtort_pipe_count); rcu_torture_writer_state = RTWS_DELAY; udelay(torture_random(&rand) & 0x3ff); rcu_torture_writer_state = RTWS_REPLACE; @@ -1414,6 +1416,7 @@ rcu_torture_writer(void *arg) atomic_inc(&rcu_torture_wcount[i]); WRITE_ONCE(old_rp->rtort_pipe_count, old_rp->rtort_pipe_count + 1); + ASSERT_EXCLUSIVE_WRITER(old_rp->rtort_pipe_count); // Make sure readers block polled grace periods. if (cur_ops->get_gp_state && cur_ops->poll_gp_state) { From c342b42fa47f4257fccfeadc8e32c51b1be17a1f Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 23 Feb 2024 15:16:20 -0800 Subject: [PATCH 288/969] rcu-tasks: Make Tasks RCU wait idly for grace-period delays Currently, all waits for grace periods sleep at TASK_UNINTERRUPTIBLE, regardless of RCU flavor. This has worked well, but there have been cases where a longer-than-average Tasks RCU grace period has triggered softlockup splats, many of them, before the Tasks RCU CPU stall warning appears. These softlockup splats unnecessarily consume console bandwidth and complicate diagnosis of the underlying problem. Plus a long but not pathologically long Tasks RCU grace period might trigger a few softlockup splats before completing normally, which generates noise for no good reason. This commit therefore causes Tasks RCU grace periods to sleep at TASK_IDLE priority. If there really is a persistent problem, the eventual Tasks RCU CPU stall warning will flag it, and without the extra noise. Reported-by: Breno Leitao Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- include/linux/rcupdate_wait.h | 18 +++++++++--------- kernel/rcu/tasks.h | 6 +++++- kernel/rcu/update.c | 4 ++-- 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/include/linux/rcupdate_wait.h b/include/linux/rcupdate_wait.h index d07f0848802e..303ab9bee155 100644 --- a/include/linux/rcupdate_wait.h +++ b/include/linux/rcupdate_wait.h @@ -19,18 +19,18 @@ struct rcu_synchronize { }; void wakeme_after_rcu(struct rcu_head *head); -void __wait_rcu_gp(bool checktiny, int n, call_rcu_func_t *crcu_array, +void __wait_rcu_gp(bool checktiny, unsigned int state, int n, call_rcu_func_t *crcu_array, struct rcu_synchronize *rs_array); -#define _wait_rcu_gp(checktiny, ...) \ -do { \ - call_rcu_func_t __crcu_array[] = { __VA_ARGS__ }; \ - struct rcu_synchronize __rs_array[ARRAY_SIZE(__crcu_array)]; \ - __wait_rcu_gp(checktiny, ARRAY_SIZE(__crcu_array), \ - __crcu_array, __rs_array); \ +#define _wait_rcu_gp(checktiny, state, ...) \ +do { \ + call_rcu_func_t __crcu_array[] = { __VA_ARGS__ }; \ + struct rcu_synchronize __rs_array[ARRAY_SIZE(__crcu_array)]; \ + __wait_rcu_gp(checktiny, state, ARRAY_SIZE(__crcu_array), __crcu_array, __rs_array); \ } while (0) -#define wait_rcu_gp(...) _wait_rcu_gp(false, __VA_ARGS__) +#define wait_rcu_gp(...) _wait_rcu_gp(false, TASK_UNINTERRUPTIBLE, __VA_ARGS__) +#define wait_rcu_gp_state(state, ...) _wait_rcu_gp(false, state, __VA_ARGS__) /** * synchronize_rcu_mult - Wait concurrently for multiple grace periods @@ -54,7 +54,7 @@ do { \ * grace period. */ #define synchronize_rcu_mult(...) \ - _wait_rcu_gp(IS_ENABLED(CONFIG_TINY_RCU), __VA_ARGS__) + _wait_rcu_gp(IS_ENABLED(CONFIG_TINY_RCU), TASK_UNINTERRUPTIBLE, __VA_ARGS__) static inline void cond_resched_rcu(void) { diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h index 147b5945d67a..82e458ea0728 100644 --- a/kernel/rcu/tasks.h +++ b/kernel/rcu/tasks.h @@ -74,6 +74,7 @@ struct rcu_tasks_percpu { * @holdouts_func: This flavor's holdout-list scan function (optional). * @postgp_func: This flavor's post-grace-period function (optional). * @call_func: This flavor's call_rcu()-equivalent function. + * @wait_state: Task state for synchronous grace-period waits (default TASK_UNINTERRUPTIBLE). * @rtpcpu: This flavor's rcu_tasks_percpu structure. * @percpu_enqueue_shift: Shift down CPU ID this much when enqueuing callbacks. * @percpu_enqueue_lim: Number of per-CPU callback queues in use for enqueuing. @@ -107,6 +108,7 @@ struct rcu_tasks { holdouts_func_t holdouts_func; postgp_func_t postgp_func; call_rcu_func_t call_func; + unsigned int wait_state; struct rcu_tasks_percpu __percpu *rtpcpu; int percpu_enqueue_shift; int percpu_enqueue_lim; @@ -134,6 +136,7 @@ static struct rcu_tasks rt_name = \ .tasks_gp_mutex = __MUTEX_INITIALIZER(rt_name.tasks_gp_mutex), \ .gp_func = gp, \ .call_func = call, \ + .wait_state = TASK_UNINTERRUPTIBLE, \ .rtpcpu = &rt_name ## __percpu, \ .lazy_jiffies = DIV_ROUND_UP(HZ, 4), \ .name = n, \ @@ -638,7 +641,7 @@ static void synchronize_rcu_tasks_generic(struct rcu_tasks *rtp) // If the grace-period kthread is running, use it. if (READ_ONCE(rtp->kthread_ptr)) { - wait_rcu_gp(rtp->call_func); + wait_rcu_gp_state(rtp->wait_state, rtp->call_func); return; } rcu_tasks_one_gp(rtp, true); @@ -1160,6 +1163,7 @@ static int __init rcu_spawn_tasks_kthread(void) rcu_tasks.postscan_func = rcu_tasks_postscan; rcu_tasks.holdouts_func = check_all_holdout_tasks; rcu_tasks.postgp_func = rcu_tasks_postgp; + rcu_tasks.wait_state = TASK_IDLE; rcu_spawn_tasks_kthread_generic(&rcu_tasks); return 0; } diff --git a/kernel/rcu/update.c b/kernel/rcu/update.c index 46aaaa9fe339..f8436969e0c8 100644 --- a/kernel/rcu/update.c +++ b/kernel/rcu/update.c @@ -408,7 +408,7 @@ void wakeme_after_rcu(struct rcu_head *head) } EXPORT_SYMBOL_GPL(wakeme_after_rcu); -void __wait_rcu_gp(bool checktiny, int n, call_rcu_func_t *crcu_array, +void __wait_rcu_gp(bool checktiny, unsigned int state, int n, call_rcu_func_t *crcu_array, struct rcu_synchronize *rs_array) { int i; @@ -440,7 +440,7 @@ void __wait_rcu_gp(bool checktiny, int n, call_rcu_func_t *crcu_array, if (crcu_array[j] == crcu_array[i]) break; if (j == i) { - wait_for_completion(&rs_array[i].completion); + wait_for_completion_state(&rs_array[i].completion, state); destroy_rcu_head_on_stack(&rs_array[i].head); } } From e7d420afb9d9b7dfc3fcfdcbc9bc60d219055d87 Mon Sep 17 00:00:00 2001 From: Zenghui Yu Date: Fri, 16 Feb 2024 23:44:55 +0800 Subject: [PATCH 289/969] doc: Remove references to arrayRCU.rst arrayRCU.rst has been removed since commit ef2555cf68c3 ("doc: Remove arrayRCU.rst") but is still referenced by whatisRCU.rst. Update it to reflect the current state of the documentation. Signed-off-by: Zenghui Yu Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- Documentation/RCU/whatisRCU.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/RCU/whatisRCU.rst b/Documentation/RCU/whatisRCU.rst index 872ac665223f..94838c65c7d9 100644 --- a/Documentation/RCU/whatisRCU.rst +++ b/Documentation/RCU/whatisRCU.rst @@ -427,7 +427,7 @@ their assorted primitives. This section shows a simple use of the core RCU API to protect a global pointer to a dynamically allocated structure. More-typical -uses of RCU may be found in listRCU.rst, arrayRCU.rst, and NMI-RCU.rst. +uses of RCU may be found in listRCU.rst and NMI-RCU.rst. :: struct foo { @@ -510,8 +510,8 @@ So, to sum up: data item. See checklist.rst for additional rules to follow when using RCU. -And again, more-typical uses of RCU may be found in listRCU.rst, -arrayRCU.rst, and NMI-RCU.rst. +And again, more-typical uses of RCU may be found in listRCU.rst +and NMI-RCU.rst. .. _4_whatisRCU: From 179f4ce102eb62b4b8efbd8371ee7d25c1082467 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Sat, 24 Feb 2024 10:27:30 +0530 Subject: [PATCH 290/969] MAINTAINERS: Update Neeraj's email address Update my email-address in MAINTAINERS and .mailmap entries to my kernel.org account. Signed-off-by: Neeraj Upadhyay Reviewed-by: Joel Fernandes Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- .mailmap | 3 ++- MAINTAINERS | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index 59c9a841bf71..32e12c26bdda 100644 --- a/.mailmap +++ b/.mailmap @@ -445,7 +445,8 @@ Nadav Amit Nadia Yvette Chambers William Lee Irwin III Naoya Horiguchi Nathan Chancellor -Neeraj Upadhyay +Neeraj Upadhyay +Neeraj Upadhyay Neil Armstrong Nguyen Anh Quynh Nicholas Piggin diff --git a/MAINTAINERS b/MAINTAINERS index 7c121493f43d..0370e571f312 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18591,7 +18591,7 @@ F: tools/testing/selftests/resctrl/ READ-COPY UPDATE (RCU) M: "Paul E. McKenney" M: Frederic Weisbecker (kernel/rcu/tree_nocb.h) -M: Neeraj Upadhyay (kernel/rcu/tasks.h) +M: Neeraj Upadhyay (kernel/rcu/tasks.h) M: Joel Fernandes M: Josh Triplett M: Boqun Feng From b993115b44d769cb34b394d92658226df81a6c89 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 22 Feb 2024 10:16:17 -0800 Subject: [PATCH 291/969] bpf: Select new NEED_TASKS_RCU Kconfig option Currently, if a Kconfig option depends on TASKS_RCU, it conditionally does "select TASKS_RCU if PREEMPTION". This works, but requires any change in this enablement logic to be replicated across all such "select" clauses. A new NEED_TASKS_RCU Kconfig option has been created to allow this enablement logic to be in one place in kernel/rcu/Kconfig. Therefore, make BPF select the new NEED_TASKS_RCU Kconfig option. Signed-off-by: Paul E. McKenney Cc: Alexei Starovoitov Cc: Daniel Borkmann Cc: Andrii Nakryiko Cc: Martin KaFai Lau Cc: Song Liu Cc: Yonghong Song Cc: John Fastabend Cc: KP Singh Cc: Stanislav Fomichev Cc: Hao Luo Cc: Jiri Olsa Cc: Cc: Ankur Arora Cc: Thomas Gleixner Cc: Steven Rostedt Acked-by: Mark Rutland Signed-off-by: Uladzislau Rezki (Sony) --- kernel/bpf/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/bpf/Kconfig b/kernel/bpf/Kconfig index bc25f5098a25..4100df44c665 100644 --- a/kernel/bpf/Kconfig +++ b/kernel/bpf/Kconfig @@ -28,7 +28,7 @@ config BPF_SYSCALL bool "Enable bpf() system call" select BPF select IRQ_WORK - select TASKS_RCU if PREEMPTION + select NEED_TASKS_RCU select TASKS_TRACE_RCU select BINARY_PRINTF select NET_SOCK_MSG if NET From 900da4d2a57c1a7e63578cb173e16af0ade3cd7b Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 22 Feb 2024 10:22:27 -0800 Subject: [PATCH 292/969] arch: Select new NEED_TASKS_RCU Kconfig option Currently, if a Kconfig option depends on TASKS_RCU, it conditionally does "select TASKS_RCU if PREEMPTION". This works, but requires any change in this enablement logic to be replicated across all such "select" clauses. A new NEED_TASKS_RCU Kconfig option has been created to allow this enablement logic to be in one place in kernel/rcu/Kconfig. Therefore, select the new NEED_TASKS_RCU Kconfig option instead of the old TASKS_RCU option. Signed-off-by: Paul E. McKenney Cc: Andrew Morton Cc: Thomas Gleixner Cc: Heiko Carstens Cc: Arnd Bergmann Cc: Douglas Anderson Cc: Ankur Arora Acked-by: Mark Rutland Reviewed-by: Steven Rostedt (Google) Signed-off-by: Uladzislau Rezki (Sony) --- arch/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 9f066785bb71..ae4a4f37bbf0 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -55,7 +55,7 @@ config KPROBES depends on MODULES depends on HAVE_KPROBES select KALLSYMS - select TASKS_RCU if PREEMPTION + select NEED_TASKS_RCU help Kprobes allows you to trap at almost any kernel address and execute a callback function. register_kprobe() establishes @@ -104,7 +104,7 @@ config STATIC_CALL_SELFTEST config OPTPROBES def_bool y depends on KPROBES && HAVE_OPTPROBES - select TASKS_RCU if PREEMPTION + select NEED_TASKS_RCU config KPROBES_ON_FTRACE def_bool y From 5c94b0b906436aad74e559195007afdd328211f4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 6 Apr 2024 17:27:20 +0200 Subject: [PATCH 293/969] ARM: dts: qcom: msm8974-sony-shinano: Enable vibrator Enable the vibrator connected to PM8941 found on the Sony shinano platform. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240406-shinano-vib-v1-1-fdd02af39d56@z3ntu.xyz Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi index 3a0c0035de09..e129bb1bd6ec 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi @@ -202,6 +202,10 @@ }; }; +&pm8941_vib { + status = "okay"; +}; + &remoteproc_adsp { cx-supply = <&pm8841_s2>; status = "okay"; From 8dec9cb9f525b6c51e3467202b9c627591c472f8 Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Fri, 8 Mar 2024 15:54:43 +0100 Subject: [PATCH 294/969] s390/ap: use static qci information Since qci is available on most of the current machines, move away from the dynamic buffers for qci information and store it instead in a statically defined buffer. The new flags member in struct ap_config_info is now used as an indicator, if qci is available in the system (at least one of these bits is set). Suggested-by: Harald Freudenberger Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/ap.h | 19 +++++---- drivers/s390/crypto/ap_bus.c | 74 +++++++++--------------------------- 2 files changed, 30 insertions(+), 63 deletions(-) diff --git a/arch/s390/include/asm/ap.h b/arch/s390/include/asm/ap.h index 43ac4a64f49b..2c5c907b1517 100644 --- a/arch/s390/include/asm/ap.h +++ b/arch/s390/include/asm/ap.h @@ -223,13 +223,18 @@ static inline struct ap_queue_status ap_zapq(ap_qid_t qid, int fbit) * config info as returned by the ap_qci() function. */ struct ap_config_info { - unsigned int apsc : 1; /* S bit */ - unsigned int apxa : 1; /* N bit */ - unsigned int qact : 1; /* C bit */ - unsigned int rc8a : 1; /* R bit */ - unsigned int : 4; - unsigned int apsb : 1; /* B bit */ - unsigned int : 23; + union { + unsigned int flags; + struct { + unsigned int apsc : 1; /* S bit */ + unsigned int apxa : 1; /* N bit */ + unsigned int qact : 1; /* C bit */ + unsigned int rc8a : 1; /* R bit */ + unsigned int : 4; + unsigned int apsb : 1; /* B bit */ + unsigned int : 23; + }; + }; unsigned char na; /* max # of APs - 1 */ unsigned char nd; /* max # of Domains - 1 */ unsigned char _reserved0[10]; diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index cce0bafd4c92..d8f5882a8eaf 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -90,8 +90,9 @@ static atomic64_t ap_bindings_complete_count = ATOMIC64_INIT(0); /* completion for APQN bindings complete */ static DECLARE_COMPLETION(ap_apqn_bindings_complete); -static struct ap_config_info *ap_qci_info; -static struct ap_config_info *ap_qci_info_old; +static struct ap_config_info qci[2]; +static struct ap_config_info *const ap_qci_info = &qci[0]; +static struct ap_config_info *const ap_qci_info_old = &qci[1]; /* * AP bus related debug feature things. @@ -203,9 +204,7 @@ static int ap_apft_available(void) */ static inline int ap_qact_available(void) { - if (ap_qci_info) - return ap_qci_info->qact; - return 0; + return ap_qci_info->qact; } /* @@ -215,9 +214,7 @@ static inline int ap_qact_available(void) */ int ap_sb_available(void) { - if (ap_qci_info) - return ap_qci_info->apsb; - return 0; + return ap_qci_info->apsb; } /* @@ -229,23 +226,6 @@ bool ap_is_se_guest(void) } EXPORT_SYMBOL(ap_is_se_guest); -/* - * ap_fetch_qci_info(): Fetch cryptographic config info - * - * Returns the ap configuration info fetched via PQAP(QCI). - * On success 0 is returned, on failure a negative errno - * is returned, e.g. if the PQAP(QCI) instruction is not - * available, the return value will be -EOPNOTSUPP. - */ -static inline int ap_fetch_qci_info(struct ap_config_info *info) -{ - if (!ap_qci_available()) - return -EOPNOTSUPP; - if (!info) - return -EINVAL; - return ap_qci(info); -} - /** * ap_init_qci_info(): Allocate and query qci config info. * Does also update the static variables ap_max_domain_id @@ -253,27 +233,12 @@ static inline int ap_fetch_qci_info(struct ap_config_info *info) */ static void __init ap_init_qci_info(void) { - if (!ap_qci_available()) { + if (!ap_qci_available() || + ap_qci(ap_qci_info)) { AP_DBF_INFO("%s QCI not supported\n", __func__); return; } - - ap_qci_info = kzalloc(sizeof(*ap_qci_info), GFP_KERNEL); - if (!ap_qci_info) - return; - ap_qci_info_old = kzalloc(sizeof(*ap_qci_info_old), GFP_KERNEL); - if (!ap_qci_info_old) { - kfree(ap_qci_info); - ap_qci_info = NULL; - return; - } - if (ap_fetch_qci_info(ap_qci_info) != 0) { - kfree(ap_qci_info); - kfree(ap_qci_info_old); - ap_qci_info = NULL; - ap_qci_info_old = NULL; - return; - } + memcpy(ap_qci_info_old, ap_qci_info, sizeof(*ap_qci_info)); AP_DBF_INFO("%s successful fetched initial qci info\n", __func__); if (ap_qci_info->apxa) { @@ -288,8 +253,6 @@ static void __init ap_init_qci_info(void) __func__, ap_max_domain_id); } } - - memcpy(ap_qci_info_old, ap_qci_info, sizeof(*ap_qci_info)); } /* @@ -312,7 +275,7 @@ static inline int ap_test_config_card_id(unsigned int id) { if (id > ap_max_adapter_id) return 0; - if (ap_qci_info) + if (ap_qci_info->flags) return ap_test_config(ap_qci_info->apm, id); return 1; } @@ -329,7 +292,7 @@ int ap_test_config_usage_domain(unsigned int domain) { if (domain > ap_max_domain_id) return 0; - if (ap_qci_info) + if (ap_qci_info->flags) return ap_test_config(ap_qci_info->aqm, domain); return 1; } @@ -1234,7 +1197,7 @@ static BUS_ATTR_RW(ap_domain); static ssize_t ap_control_domain_mask_show(const struct bus_type *bus, char *buf) { - if (!ap_qci_info) /* QCI not supported */ + if (!ap_qci_info->flags) /* QCI not supported */ return sysfs_emit(buf, "not supported\n"); return sysfs_emit(buf, "0x%08x%08x%08x%08x%08x%08x%08x%08x\n", @@ -1248,7 +1211,7 @@ static BUS_ATTR_RO(ap_control_domain_mask); static ssize_t ap_usage_domain_mask_show(const struct bus_type *bus, char *buf) { - if (!ap_qci_info) /* QCI not supported */ + if (!ap_qci_info->flags) /* QCI not supported */ return sysfs_emit(buf, "not supported\n"); return sysfs_emit(buf, "0x%08x%08x%08x%08x%08x%08x%08x%08x\n", @@ -1262,7 +1225,7 @@ static BUS_ATTR_RO(ap_usage_domain_mask); static ssize_t ap_adapter_mask_show(const struct bus_type *bus, char *buf) { - if (!ap_qci_info) /* QCI not supported */ + if (!ap_qci_info->flags) /* QCI not supported */ return sysfs_emit(buf, "not supported\n"); return sysfs_emit(buf, "0x%08x%08x%08x%08x%08x%08x%08x%08x\n", @@ -1595,7 +1558,7 @@ static ssize_t features_show(const struct bus_type *bus, char *buf) { int n = 0; - if (!ap_qci_info) /* QCI not supported */ + if (!ap_qci_info->flags) /* QCI not supported */ return sysfs_emit(buf, "-\n"); if (ap_qci_info->apsc) @@ -2158,11 +2121,11 @@ static inline void ap_scan_adapter(int ap) */ static bool ap_get_configuration(void) { - if (!ap_qci_info) /* QCI not supported */ + if (!ap_qci_info->flags) /* QCI not supported */ return false; memcpy(ap_qci_info_old, ap_qci_info, sizeof(*ap_qci_info)); - ap_fetch_qci_info(ap_qci_info); + ap_qci(ap_qci_info); return memcmp(ap_qci_info, ap_qci_info_old, sizeof(struct ap_config_info)) != 0; @@ -2179,7 +2142,7 @@ static bool ap_config_has_new_aps(void) unsigned long m[BITS_TO_LONGS(AP_DEVICES)]; - if (!ap_qci_info) + if (!ap_qci_info->flags) return false; bitmap_andnot(m, (unsigned long *)ap_qci_info->apm, @@ -2200,7 +2163,7 @@ static bool ap_config_has_new_doms(void) { unsigned long m[BITS_TO_LONGS(AP_DOMAINS)]; - if (!ap_qci_info) + if (!ap_qci_info->flags) return false; bitmap_andnot(m, (unsigned long *)ap_qci_info->aqm, @@ -2427,7 +2390,6 @@ out_bus: out: if (ap_irq_flag) unregister_adapter_interrupt(&ap_airq); - kfree(ap_qci_info); return rc; } device_initcall(ap_module_init); From 170660ccf8806742052028093fb45872d2be4775 Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Fri, 8 Mar 2024 17:13:48 +0100 Subject: [PATCH 295/969] s390/ap: rework ap initialization Rework the ap initialization and add missing cleanups to the error path. Errors during the registration of IRQ handler is now also detected. Suggested-by: Heiko Carstens Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Signed-off-by: Alexander Gordeev --- drivers/s390/crypto/ap_bus.c | 102 ++++++++++++++++++++++++----------- 1 file changed, 72 insertions(+), 30 deletions(-) diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index d8f5882a8eaf..aabaf93004bc 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -2273,7 +2273,66 @@ static void ap_scan_bus_wq_callback(struct work_struct *unused) } } -static int __init ap_debug_init(void) +static inline int __init ap_async_init(void) +{ + int rc; + + /* Setup the AP bus rescan timer. */ + timer_setup(&ap_scan_bus_timer, ap_scan_bus_timer_callback, 0); + + /* + * Setup the high resolution poll timer. + * If we are running under z/VM adjust polling to z/VM polling rate. + */ + if (MACHINE_IS_VM) + poll_high_timeout = 1500000; + hrtimer_init(&ap_poll_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); + ap_poll_timer.function = ap_poll_timeout; + + queue_work(system_long_wq, &ap_scan_bus_work); + + /* Start the low priority AP bus poll thread. */ + if (!ap_thread_flag) + return 0; + + rc = ap_poll_thread_start(); + if (rc) + goto out; + + return 0; + +out: + cancel_work(&ap_scan_bus_work); + hrtimer_cancel(&ap_poll_timer); + timer_delete(&ap_scan_bus_timer); + return rc; +} + +static inline void ap_irq_exit(void) +{ + if (ap_irq_flag) + unregister_adapter_interrupt(&ap_airq); +} + +static inline int __init ap_irq_init(void) +{ + int rc; + + if (!ap_interrupts_available() || !ap_useirq) + return 0; + + rc = register_adapter_interrupt(&ap_airq); + ap_irq_flag = (rc == 0); + + return rc; +} + +static inline void ap_debug_exit(void) +{ + debug_unregister(ap_dbf_info); +} + +static inline int __init ap_debug_init(void) { ap_dbf_info = debug_register("ap", 2, 1, AP_DBF_MAX_SPRINTF_ARGS * sizeof(long)); @@ -2342,15 +2401,14 @@ static int __init ap_module_init(void) } /* enable interrupts if available */ - if (ap_interrupts_available() && ap_useirq) { - rc = register_adapter_interrupt(&ap_airq); - ap_irq_flag = (rc == 0); - } + rc = ap_irq_init(); + if (rc) + goto out; /* Create /sys/bus/ap. */ rc = bus_register(&ap_bus_type); if (rc) - goto out; + goto out_irq; /* Create /sys/devices/ap. */ ap_root_device = root_device_register("ap"); @@ -2359,37 +2417,21 @@ static int __init ap_module_init(void) goto out_bus; ap_root_device->bus = &ap_bus_type; - /* Setup the AP bus rescan timer. */ - timer_setup(&ap_scan_bus_timer, ap_scan_bus_timer_callback, 0); - - /* - * Setup the high resolution poll timer. - * If we are running under z/VM adjust polling to z/VM polling rate. - */ - if (MACHINE_IS_VM) - poll_high_timeout = 1500000; - hrtimer_init(&ap_poll_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); - ap_poll_timer.function = ap_poll_timeout; - - /* Start the low priority AP bus poll thread. */ - if (ap_thread_flag) { - rc = ap_poll_thread_start(); - if (rc) - goto out_work; - } - - queue_work(system_long_wq, &ap_scan_bus_work); + /* Setup asynchronous work (timers, workqueue, etc). */ + rc = ap_async_init(); + if (rc) + goto out_device; return 0; -out_work: - hrtimer_cancel(&ap_poll_timer); +out_device: root_device_unregister(ap_root_device); out_bus: bus_unregister(&ap_bus_type); +out_irq: + ap_irq_exit(); out: - if (ap_irq_flag) - unregister_adapter_interrupt(&ap_airq); + ap_debug_exit(); return rc; } device_initcall(ap_module_init); From 3c7a377324cf9f248041c0e7295728eebd6c9b14 Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Fri, 8 Mar 2024 17:23:25 +0100 Subject: [PATCH 296/969] s390/ap: swap IRQ and bus/device registration The IRQ handler may rely on the bus or the root device. Register the adapter IRQ after setting up the bus and the root device to avoid any race conditions. Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Signed-off-by: Alexander Gordeev --- drivers/s390/crypto/ap_bus.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index aabaf93004bc..cdfaa321b44e 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -2400,15 +2400,10 @@ static int __init ap_module_init(void) ap_domain_index = -1; } - /* enable interrupts if available */ - rc = ap_irq_init(); - if (rc) - goto out; - /* Create /sys/bus/ap. */ rc = bus_register(&ap_bus_type); if (rc) - goto out_irq; + goto out; /* Create /sys/devices/ap. */ ap_root_device = root_device_register("ap"); @@ -2417,19 +2412,24 @@ static int __init ap_module_init(void) goto out_bus; ap_root_device->bus = &ap_bus_type; - /* Setup asynchronous work (timers, workqueue, etc). */ - rc = ap_async_init(); + /* enable interrupts if available */ + rc = ap_irq_init(); if (rc) goto out_device; + /* Setup asynchronous work (timers, workqueue, etc). */ + rc = ap_async_init(); + if (rc) + goto out_irq; + return 0; +out_irq: + ap_irq_exit(); out_device: root_device_unregister(ap_root_device); out_bus: bus_unregister(&ap_bus_type); -out_irq: - ap_irq_exit(); out: ap_debug_exit(); return rc; From 05272aa499c48f230d862577d423de3e2b268e47 Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Thu, 15 Feb 2024 08:59:45 +0100 Subject: [PATCH 297/969] s390/uv: export prot_virt_guest symbol in uv The inline function is_prot_virt_guest() in asm/uv.h makes use of the prot_virt_guest symbol. As this inline function can be called by other parts of the kernel (modules and built-in), the symbol should be exported, similar to the prot_virt_host symbol. One consumer of is_prot_virt_guest() will be the ap bus code. Cc: Janosch Frank Cc: Claudio Imbrenda Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Acked-by: Claudio Imbrenda Signed-off-by: Alexander Gordeev --- arch/s390/kernel/uv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c index fc07bc39e698..2961db043fa4 100644 --- a/arch/s390/kernel/uv.c +++ b/arch/s390/kernel/uv.c @@ -21,6 +21,7 @@ /* the bootdata_preserved fields come from ones in arch/s390/boot/uv.c */ #ifdef CONFIG_PROTECTED_VIRTUALIZATION_GUEST int __bootdata_preserved(prot_virt_guest); +EXPORT_SYMBOL(prot_virt_guest); #endif /* From 2a483d333fd84acc009c7199fdd962af3ffc6b3b Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Mon, 19 Feb 2024 17:32:54 +0100 Subject: [PATCH 298/969] s390/chsc: use notifier for AP configuration changes The direct dependency of chsc and the AP bus prevents the modularization of ap bus. Introduce a notifier interface for AP changes, which decouples the producer of the change events (chsc) from the consumer (ap_bus). Remove the ap_cfg_chg() interface and replace it with the notifier invocation. The ap bus module registers a notification handler, which triggers the AP bus scan. Cc: Vineeth Vijayan Cc: Peter Oberparleiter Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Acked-by: Vineeth Vijayan Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/ap.h | 11 ----------- arch/s390/include/asm/chsc.h | 15 +++++++++++++++ drivers/s390/cio/chsc.c | 18 ++++++++++++++++-- drivers/s390/crypto/ap_bus.c | 21 +++++++++++++++++++-- 4 files changed, 50 insertions(+), 15 deletions(-) diff --git a/arch/s390/include/asm/ap.h b/arch/s390/include/asm/ap.h index 2c5c907b1517..395b02d6a133 100644 --- a/arch/s390/include/asm/ap.h +++ b/arch/s390/include/asm/ap.h @@ -549,15 +549,4 @@ static inline struct ap_queue_status ap_dqap(ap_qid_t qid, return reg1.status; } -/* - * Interface to tell the AP bus code that a configuration - * change has happened. The bus code should at least do - * an ap bus resource rescan. - */ -#if IS_ENABLED(CONFIG_ZCRYPT) -void ap_bus_cfg_chg(void); -#else -static inline void ap_bus_cfg_chg(void){} -#endif - #endif /* _ASM_S390_AP_H_ */ diff --git a/arch/s390/include/asm/chsc.h b/arch/s390/include/asm/chsc.h index bb48ea380c0d..bb78159d8042 100644 --- a/arch/s390/include/asm/chsc.h +++ b/arch/s390/include/asm/chsc.h @@ -11,6 +11,9 @@ #include +/* struct from linux/notifier.h */ +struct notifier_block; + /** * Operation codes for CHSC PNSO: * PNSO_OC_NET_BRIDGE_INFO - only addresses that are visible to a bridgeport @@ -66,4 +69,16 @@ struct chsc_pnso_area { struct chsc_pnso_naid_l2 entries[]; } __packed __aligned(PAGE_SIZE); +/* + * notifier interface - registered notifiers gets called on + * the following events: + * - ap config changed (CHSC_NOTIFY_AP_CFG) + */ +enum chsc_notify_type { + CHSC_NOTIFY_AP_CFG = 3, +}; + +int chsc_notifier_register(struct notifier_block *nb); +int chsc_notifier_unregister(struct notifier_block *nb); + #endif /* _ASM_S390_CHSC_H */ diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c index 44ea76f9e1de..89e51f197cdd 100644 --- a/drivers/s390/cio/chsc.c +++ b/drivers/s390/cio/chsc.c @@ -24,7 +24,6 @@ #include #include #include -#include #include "css.h" #include "cio.h" @@ -40,6 +39,20 @@ static DEFINE_SPINLOCK(chsc_page_lock); #define SEI_VF_FLA 0xc0 /* VF flag for Full Link Address */ #define SEI_RS_CHPID 0x4 /* 4 in RS field indicates CHPID */ +static BLOCKING_NOTIFIER_HEAD(chsc_notifiers); + +int chsc_notifier_register(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&chsc_notifiers, nb); +} +EXPORT_SYMBOL(chsc_notifier_register); + +int chsc_notifier_unregister(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&chsc_notifiers, nb); +} +EXPORT_SYMBOL(chsc_notifier_unregister); + /** * chsc_error_from_response() - convert a chsc response to an error * @response: chsc response code @@ -581,7 +594,8 @@ static void chsc_process_sei_ap_cfg_chg(struct chsc_sei_nt0_area *sei_area) if (sei_area->rs != 5) return; - ap_bus_cfg_chg(); + blocking_notifier_call_chain(&chsc_notifiers, + CHSC_NOTIFY_AP_CFG, NULL); } static void chsc_process_sei_fces_event(struct chsc_sei_nt0_area *sei_area) diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index cdfaa321b44e..9284ae63074d 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -39,6 +39,7 @@ #include #include #include +#include #include "ap_bus.h" #include "ap_debug.h" @@ -1024,13 +1025,23 @@ EXPORT_SYMBOL(ap_bus_force_rescan); /* * A config change has happened, force an ap bus rescan. */ -void ap_bus_cfg_chg(void) +static int ap_bus_cfg_chg(struct notifier_block *nb, + unsigned long action, void *data) { + if (action != CHSC_NOTIFY_AP_CFG) + return NOTIFY_DONE; + pr_debug("%s config change, forcing bus rescan\n", __func__); ap_bus_force_rescan(); + + return NOTIFY_OK; } +static struct notifier_block ap_bus_nb = { + .notifier_call = ap_bus_cfg_chg, +}; + /* * hex2bitmap() - parse hex mask string and set bitmap. * Valid strings are "0x012345678" with at least one valid hex number. @@ -2291,16 +2302,22 @@ static inline int __init ap_async_init(void) queue_work(system_long_wq, &ap_scan_bus_work); + rc = chsc_notifier_register(&ap_bus_nb); + if (rc) + goto out; + /* Start the low priority AP bus poll thread. */ if (!ap_thread_flag) return 0; rc = ap_poll_thread_start(); if (rc) - goto out; + goto out_notifier; return 0; +out_notifier: + chsc_notifier_unregister(&ap_bus_nb); out: cancel_work(&ap_scan_bus_work); hrtimer_cancel(&ap_poll_timer); From 123760841a2e5977d4e97f86999b3784df58801d Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Mon, 19 Feb 2024 18:10:19 +0100 Subject: [PATCH 299/969] s390/ap: modularize ap bus There is no hard requirement to have the ap bus statically in the kernel, so add an option to compile it as module. Cc: Tony Krowiak Cc: Halil Pasic Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Reviewed-by: Anthony Krowiak Signed-off-by: Alexander Gordeev --- Documentation/arch/s390/vfio-ap.rst | 2 +- arch/s390/Kconfig | 15 ++++++++++++++- drivers/crypto/Kconfig | 1 + drivers/s390/char/Makefile | 2 +- drivers/s390/crypto/Makefile | 2 +- drivers/s390/crypto/ap_bus.c | 30 +++++++++++++++++++++++++---- 6 files changed, 44 insertions(+), 8 deletions(-) diff --git a/Documentation/arch/s390/vfio-ap.rst b/Documentation/arch/s390/vfio-ap.rst index 929ee1c1c940..cf8533f2a8b6 100644 --- a/Documentation/arch/s390/vfio-ap.rst +++ b/Documentation/arch/s390/vfio-ap.rst @@ -550,7 +550,7 @@ These are the steps: following Kconfig elements selected: * IOMMU_SUPPORT * S390 - * ZCRYPT + * AP * VFIO * KVM diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 8f01ada6845e..db7eb4d77d38 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -724,6 +724,19 @@ config EADM_SCH To compile this driver as a module, choose M here: the module will be called eadm_sch. +config AP + def_tristate y + prompt "Support for Adjunct Processors (ap)" + help + This driver allows usage to Adjunct Processor (AP) devices via + the ap bus, cards and queues. Supported Adjunct Processors are + the CryptoExpress Cards (CEX). + + To compile this driver as a module, choose M here: the + module will be called ap. + + If unsure, say Y (default). + config VFIO_CCW def_tristate n prompt "Support for VFIO-CCW subchannels" @@ -740,7 +753,7 @@ config VFIO_AP prompt "VFIO support for AP devices" depends on KVM depends on VFIO - depends on ZCRYPT + depends on AP select VFIO_MDEV help This driver grants access to Adjunct Processor (AP) devices diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 3d02702456a5..16385658fd35 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -67,6 +67,7 @@ config CRYPTO_DEV_GEODE config ZCRYPT tristate "Support for s390 cryptographic adapters" depends on S390 + depends on AP select HW_RANDOM help Select this option if you want to enable support for diff --git a/drivers/s390/char/Makefile b/drivers/s390/char/Makefile index b0f6b3201636..81d6744e1861 100644 --- a/drivers/s390/char/Makefile +++ b/drivers/s390/char/Makefile @@ -32,7 +32,7 @@ obj-$(CONFIG_SCLP_VT220_TTY) += sclp_vt220.o obj-$(CONFIG_PCI) += sclp_pci.o -obj-$(subst m,y,$(CONFIG_ZCRYPT)) += sclp_ap.o +obj-$(subst m,y,$(CONFIG_AP)) += sclp_ap.o obj-$(CONFIG_VMLOGRDR) += vmlogrdr.o obj-$(CONFIG_VMCP) += vmcp.o diff --git a/drivers/s390/crypto/Makefile b/drivers/s390/crypto/Makefile index 0edacd101c12..bd94811fd9f1 100644 --- a/drivers/s390/crypto/Makefile +++ b/drivers/s390/crypto/Makefile @@ -4,7 +4,7 @@ # ap-objs := ap_bus.o ap_card.o ap_queue.o -obj-$(subst m,y,$(CONFIG_ZCRYPT)) += ap.o +obj-$(CONFIG_AP) += ap.o # zcrypt_api.o and zcrypt_msgtype*.o depend on ap.o zcrypt-objs := zcrypt_api.o zcrypt_card.o zcrypt_queue.o zcrypt-objs += zcrypt_msgtype6.o zcrypt_msgtype50.o diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index 9284ae63074d..09059b3a3a42 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -44,9 +44,10 @@ #include "ap_bus.h" #include "ap_debug.h" -/* - * Module parameters; note though this file itself isn't modular. - */ +MODULE_AUTHOR("IBM Corporation"); +MODULE_DESCRIPTION("Adjunct Processor Bus driver"); +MODULE_LICENSE("GPL"); + int ap_domain_index = -1; /* Adjunct Processor Domain Index */ static DEFINE_SPINLOCK(ap_domain_lock); module_param_named(domain, ap_domain_index, int, 0440); @@ -2284,6 +2285,16 @@ static void ap_scan_bus_wq_callback(struct work_struct *unused) } } +static inline void __exit ap_async_exit(void) +{ + if (ap_thread_flag) + ap_poll_thread_stop(); + chsc_notifier_unregister(&ap_bus_nb); + cancel_work(&ap_scan_bus_work); + hrtimer_cancel(&ap_poll_timer); + timer_delete(&ap_scan_bus_timer); +} + static inline int __init ap_async_init(void) { int rc; @@ -2451,4 +2462,15 @@ out: ap_debug_exit(); return rc; } -device_initcall(ap_module_init); + +static void __exit ap_module_exit(void) +{ + ap_async_exit(); + ap_irq_exit(); + root_device_unregister(ap_root_device); + bus_unregister(&ap_bus_type); + ap_debug_exit(); +} + +module_init(ap_module_init); +module_exit(ap_module_exit); From b3840c8bfc27c1e8dc3953d6a27960ae390d5d80 Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Tue, 27 Feb 2024 16:49:33 +0100 Subject: [PATCH 300/969] s390/ap: rename ap debug configuration option The configuration option ZCRYPT_DEBUG is used only in ap queue code, so rename it to AP_DEBUG. It also no longer depends on ZCRYPT but on AP. While at it, also update the help text. Signed-off-by: Holger Dengler Reviewed-by: Harald Freudenberger Signed-off-by: Alexander Gordeev --- arch/s390/Kconfig | 14 ++++++++++++++ drivers/crypto/Kconfig | 17 ----------------- drivers/s390/crypto/ap_queue.c | 4 ++-- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index db7eb4d77d38..b9857aacd40b 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -737,6 +737,20 @@ config AP If unsure, say Y (default). +config AP_DEBUG + def_bool n + prompt "Enable debug features for Adjunct Processor (ap) devices" + depends on AP + help + Say 'Y' here to enable some additional debug features for Adjunct + Processor (ap) devices. + + There will be some more sysfs attributes displayed for ap queues. + + Do not enable on production level kernel build. + + If unsure, say N. + config VFIO_CCW def_tristate n prompt "Support for VFIO-CCW subchannels" diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 16385658fd35..bfe18ebc2a98 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -75,23 +75,6 @@ config ZCRYPT to 8 in Coprocessor (CEXxC), EP11 Coprocessor (CEXxP) or Accelerator (CEXxA) mode. -config ZCRYPT_DEBUG - bool "Enable debug features for s390 cryptographic adapters" - default n - depends on DEBUG_KERNEL - depends on ZCRYPT - help - Say 'Y' here to enable some additional debug features on the - s390 cryptographic adapters driver. - - There will be some more sysfs attributes displayed for ap cards - and queues and some flags on crypto requests are interpreted as - debugging messages to force error injection. - - Do not enable on production level kernel build. - - If unsure, say N. - config PKEY tristate "Kernel API for protected key handling" depends on S390 diff --git a/drivers/s390/crypto/ap_queue.c b/drivers/s390/crypto/ap_queue.c index 6e4e8d324a6d..1f647ffd6f4d 100644 --- a/drivers/s390/crypto/ap_queue.c +++ b/drivers/s390/crypto/ap_queue.c @@ -708,7 +708,7 @@ static ssize_t ap_functions_show(struct device *dev, static DEVICE_ATTR_RO(ap_functions); -#ifdef CONFIG_ZCRYPT_DEBUG +#ifdef CONFIG_AP_DEBUG static ssize_t states_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -820,7 +820,7 @@ static struct attribute *ap_queue_dev_attrs[] = { &dev_attr_config.attr, &dev_attr_chkstop.attr, &dev_attr_ap_functions.attr, -#ifdef CONFIG_ZCRYPT_DEBUG +#ifdef CONFIG_AP_DEBUG &dev_attr_states.attr, &dev_attr_last_err_rc.attr, #endif From aaebea959efb2cccd870990f1b6016ff324b0fb6 Mon Sep 17 00:00:00 2001 From: Li Zhijian Date: Thu, 14 Mar 2024 17:52:09 +0800 Subject: [PATCH 301/969] s390/cio: convert sprintf()/snprintf() to sysfs_emit() Per filesystems/sysfs.rst, show() should only use sysfs_emit() or sysfs_emit_at() when formatting the value to be returned to user space. coccinelle complains that there are still a couple of functions that use snprintf(). Convert them to sysfs_emit(). Generally, this patch is generated by make coccicheck M= MODE=patch \ COCCI=scripts/coccinelle/api/device_attr_show.cocci No functional change intended. Cc: Vineeth Vijayan Cc: Peter Oberparleiter Signed-off-by: Li Zhijian Link: https://lore.kernel.org/r/20240314095209.1325229-1-lizhijian@fujitsu.com Signed-off-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- drivers/s390/cio/css.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/s390/cio/css.c b/drivers/s390/cio/css.c index 1d68db1a3d4e..781f84901256 100644 --- a/drivers/s390/cio/css.c +++ b/drivers/s390/cio/css.c @@ -309,7 +309,7 @@ static ssize_t type_show(struct device *dev, struct device_attribute *attr, { struct subchannel *sch = to_subchannel(dev); - return sprintf(buf, "%01x\n", sch->st); + return sysfs_emit(buf, "%01x\n", sch->st); } static DEVICE_ATTR_RO(type); @@ -319,7 +319,7 @@ static ssize_t modalias_show(struct device *dev, struct device_attribute *attr, { struct subchannel *sch = to_subchannel(dev); - return sprintf(buf, "css:t%01X\n", sch->st); + return sysfs_emit(buf, "css:t%01X\n", sch->st); } static DEVICE_ATTR_RO(modalias); @@ -345,7 +345,7 @@ static ssize_t driver_override_show(struct device *dev, ssize_t len; device_lock(dev); - len = snprintf(buf, PAGE_SIZE, "%s\n", sch->driver_override); + len = sysfs_emit(buf, "%s\n", sch->driver_override); device_unlock(dev); return len; } @@ -396,8 +396,8 @@ static ssize_t pimpampom_show(struct device *dev, struct subchannel *sch = to_subchannel(dev); struct pmcw *pmcw = &sch->schib.pmcw; - return sprintf(buf, "%02x %02x %02x\n", - pmcw->pim, pmcw->pam, pmcw->pom); + return sysfs_emit(buf, "%02x %02x %02x\n", + pmcw->pim, pmcw->pam, pmcw->pom); } static DEVICE_ATTR_RO(pimpampom); @@ -881,7 +881,7 @@ static ssize_t real_cssid_show(struct device *dev, struct device_attribute *a, if (!css->id_valid) return -EINVAL; - return sprintf(buf, "%x\n", css->cssid); + return sysfs_emit(buf, "%x\n", css->cssid); } static DEVICE_ATTR_RO(real_cssid); @@ -904,7 +904,7 @@ static ssize_t cm_enable_show(struct device *dev, struct device_attribute *a, int ret; mutex_lock(&css->mutex); - ret = sprintf(buf, "%x\n", css->cm_enabled); + ret = sysfs_emit(buf, "%x\n", css->cm_enabled); mutex_unlock(&css->mutex); return ret; } From 4f00d4ef6634b31d6026b9bf6bb1a90c889e2347 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 26 Mar 2024 11:52:23 +0100 Subject: [PATCH 302/969] s390: adjust indentation of RELOCS command build step out Common pattern in non-verbose build output for quiet commands is that the shorthand of a command including whitespace contains at least eight characters. Adjust this for the RELOCS command, which comes only with seven characters. Before: SORTTAB vmlinux CC arch/s390/boot/version.o RELOCS arch/s390/boot/relocs.S OBJCOPY arch/s390/boot/info.bin After: SORTTAB vmlinux CC arch/s390/boot/version.o RELOCS arch/s390/boot/relocs.S OBJCOPY arch/s390/boot/info.bin Signed-off-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/boot/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/boot/Makefile b/arch/s390/boot/Makefile index 294f08a8811a..bd5d4d37a961 100644 --- a/arch/s390/boot/Makefile +++ b/arch/s390/boot/Makefile @@ -112,7 +112,7 @@ $(obj)/vmlinux.bin: vmlinux FORCE ifndef CONFIG_PIE_BUILD CMD_RELOCS=arch/s390/tools/relocs -quiet_cmd_relocs = RELOCS $@ +quiet_cmd_relocs = RELOCS $@ cmd_relocs = $(CMD_RELOCS) $< > $@ $(obj)/relocs.S: vmlinux FORCE $(call if_changed,relocs) From f10933cbd2dfddf6273698a45f76db9bafd8150f Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Wed, 27 Mar 2024 09:22:43 +0100 Subject: [PATCH 303/969] s390/cpum_cf: make crypto counters upward compatible across machine types The CPU Measurement facility crypto counter set functionality is defined by the Second Counter Version Number. This number varies between machine types, but is upward compatible. Lessen the checks to reflect this behavior. Signed-off-by: Thomas Richter Acked-by: Sumanth Korikkar Signed-off-by: Alexander Gordeev --- arch/s390/kernel/perf_cpum_cf.c | 2 +- arch/s390/kernel/perf_cpum_cf_events.c | 11 +++-------- 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c index 41ed6e0f0a2a..1434642e9cba 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -428,7 +428,7 @@ static void cpum_cf_make_setsize(enum cpumf_ctr_set ctrset) case CPUMF_CTR_SET_CRYPTO: if (cpumf_ctr_info.csvn >= 1 && cpumf_ctr_info.csvn <= 5) ctrset_size = 16; - else if (cpumf_ctr_info.csvn == 6 || cpumf_ctr_info.csvn == 7) + else if (cpumf_ctr_info.csvn >= 6) ctrset_size = 20; break; case CPUMF_CTR_SET_EXT: diff --git a/arch/s390/kernel/perf_cpum_cf_events.c b/arch/s390/kernel/perf_cpum_cf_events.c index 0d64aafd158f..e4a6bfc91080 100644 --- a/arch/s390/kernel/perf_cpum_cf_events.c +++ b/arch/s390/kernel/perf_cpum_cf_events.c @@ -855,16 +855,11 @@ __init const struct attribute_group **cpumf_cf_event_group(void) } /* Determine version specific crypto set */ - switch (ci.csvn) { - case 1 ... 5: + csvn = none; + if (ci.csvn >= 1 && ci.csvn <= 5) csvn = cpumcf_svn_12345_pmu_event_attr; - break; - case 6 ... 7: + else if (ci.csvn >= 6) csvn = cpumcf_svn_67_pmu_event_attr; - break; - default: - csvn = none; - } /* Determine model-specific counter set(s) */ get_cpu_id(&cpu_id); From 259e660d91d0e7261ae0ee37bb37266d6006a546 Mon Sep 17 00:00:00 2001 From: "Matthew Wilcox (Oracle)" Date: Fri, 22 Mar 2024 16:11:46 +0000 Subject: [PATCH 304/969] s390/mm: Convert make_page_secure to use a folio These page APIs are deprecated, so convert the incoming page to a folio and use the folio APIs instead. The ultravisor API cannot handle large folios, so return -EINVAL if one has slipped through. Acked-by: Claudio Imbrenda Signed-off-by: Matthew Wilcox (Oracle) Link: https://lore.kernel.org/r/20240322161149.2327518-2-willy@infradead.org Signed-off-by: Alexander Gordeev --- arch/s390/kernel/uv.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c index 2961db043fa4..4ae1571572d0 100644 --- a/arch/s390/kernel/uv.c +++ b/arch/s390/kernel/uv.c @@ -182,21 +182,21 @@ int uv_convert_owned_from_secure(unsigned long paddr) } /* - * Calculate the expected ref_count for a page that would otherwise have no + * Calculate the expected ref_count for a folio that would otherwise have no * further pins. This was cribbed from similar functions in other places in * the kernel, but with some slight modifications. We know that a secure - * page can not be a huge page for example. + * folio can not be a large folio, for example. */ -static int expected_page_refs(struct page *page) +static int expected_folio_refs(struct folio *folio) { int res; - res = page_mapcount(page); - if (PageSwapCache(page)) { + res = folio_mapcount(folio); + if (folio_test_swapcache(folio)) { res++; - } else if (page_mapping(page)) { + } else if (folio_mapping(folio)) { res++; - if (page_has_private(page)) + if (folio->private) res++; } return res; @@ -204,14 +204,17 @@ static int expected_page_refs(struct page *page) static int make_page_secure(struct page *page, struct uv_cb_header *uvcb) { + struct folio *folio = page_folio(page); int expected, cc = 0; - if (PageWriteback(page)) + if (folio_test_large(folio)) + return -EINVAL; + if (folio_test_writeback(folio)) return -EAGAIN; - expected = expected_page_refs(page); - if (!page_ref_freeze(page, expected)) + expected = expected_folio_refs(folio); + if (!folio_ref_freeze(folio, expected)) return -EBUSY; - set_bit(PG_arch_1, &page->flags); + set_bit(PG_arch_1, &folio->flags); /* * If the UVC does not succeed or fail immediately, we don't want to * loop for long, or we might get stall notifications. @@ -221,9 +224,9 @@ static int make_page_secure(struct page *page, struct uv_cb_header *uvcb) * -EAGAIN and we let the callers deal with it. */ cc = __uv_call(0, (u64)uvcb); - page_ref_unfreeze(page, expected); + folio_ref_unfreeze(folio, expected); /* - * Return -ENXIO if the page was not mapped, -EINVAL for other errors. + * Return -ENXIO if the folio was not mapped, -EINVAL for other errors. * If busy or partially completed, return -EAGAIN. */ if (cc == UVC_CC_OK) From d35c34bb32f2cc4ec0b52e91ad7a8fcab55d7856 Mon Sep 17 00:00:00 2001 From: "Matthew Wilcox (Oracle)" Date: Fri, 22 Mar 2024 16:11:47 +0000 Subject: [PATCH 305/969] s390/mm: Convert gmap_make_secure to use a folio Remove uses of deprecated page APIs, and move the check for large folios to here to avoid taking the folio lock if the folio is too large. We could do better here by attempting to split the large folio, but I'll leave that improvement for someone who can test it. Acked-by: Claudio Imbrenda Signed-off-by: Matthew Wilcox (Oracle) Link: https://lore.kernel.org/r/20240322161149.2327518-3-willy@infradead.org Signed-off-by: Alexander Gordeev --- arch/s390/kernel/uv.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/s390/kernel/uv.c b/arch/s390/kernel/uv.c index 4ae1571572d0..265fea37e030 100644 --- a/arch/s390/kernel/uv.c +++ b/arch/s390/kernel/uv.c @@ -202,13 +202,10 @@ static int expected_folio_refs(struct folio *folio) return res; } -static int make_page_secure(struct page *page, struct uv_cb_header *uvcb) +static int make_folio_secure(struct folio *folio, struct uv_cb_header *uvcb) { - struct folio *folio = page_folio(page); int expected, cc = 0; - if (folio_test_large(folio)) - return -EINVAL; if (folio_test_writeback(folio)) return -EAGAIN; expected = expected_folio_refs(folio); @@ -281,7 +278,7 @@ int gmap_make_secure(struct gmap *gmap, unsigned long gaddr, void *uvcb) bool local_drain = false; spinlock_t *ptelock; unsigned long uaddr; - struct page *page; + struct folio *folio; pte_t *ptep; int rc; @@ -310,15 +307,19 @@ again: if (!ptep) goto out; if (pte_present(*ptep) && !(pte_val(*ptep) & _PAGE_INVALID) && pte_write(*ptep)) { - page = pte_page(*ptep); + folio = page_folio(pte_page(*ptep)); + rc = -EINVAL; + if (folio_test_large(folio)) + goto unlock; rc = -EAGAIN; - if (trylock_page(page)) { + if (folio_trylock(folio)) { if (should_export_before_import(uvcb, gmap->mm)) - uv_convert_from_secure(page_to_phys(page)); - rc = make_page_secure(page, uvcb); - unlock_page(page); + uv_convert_from_secure(PFN_PHYS(folio_pfn(folio))); + rc = make_folio_secure(folio, uvcb); + folio_unlock(folio); } } +unlock: pte_unmap_unlock(ptep, ptelock); out: mmap_read_unlock(gmap->mm); @@ -328,10 +329,10 @@ out: * If we are here because the UVC returned busy or partial * completion, this is just a useless check, but it is safe. */ - wait_on_page_writeback(page); + folio_wait_writeback(folio); } else if (rc == -EBUSY) { /* - * If we have tried a local drain and the page refcount + * If we have tried a local drain and the folio refcount * still does not match our expected safe value, try with a * system wide drain. This is needed if the pagevecs holding * the page are on a different CPU. @@ -342,7 +343,7 @@ out: return -EAGAIN; } /* - * We are here if the page refcount does not match the + * We are here if the folio refcount does not match the * expected safe value. The main culprits are usually * pagevecs. With lru_add_drain() we drain the pagevecs * on the local CPU so that hopefully the refcount will From c0e5a431442d7bbfbd3704212680e49faa8ee46c Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 17:37:27 -0500 Subject: [PATCH 306/969] firmware: ti_sci: Use devm_register_restart_handler() Use device life-cycle managed register function to simplify probe. Signed-off-by: Andrew Davis Reviewed-by: Gabriel Somlo Reviewed-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20240326223730.54639-2-afd@ti.com Signed-off-by: Nishanth Menon --- drivers/firmware/ti_sci.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 8b9a2556de16..9885e1763591 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -87,7 +87,6 @@ struct ti_sci_desc { * struct ti_sci_info - Structure representing a TI SCI instance * @dev: Device pointer * @desc: SoC description for this instance - * @nb: Reboot Notifier block * @d: Debugfs file entry * @debug_region: Memory region where the debug message are available * @debug_region_size: Debug region size @@ -103,7 +102,6 @@ struct ti_sci_desc { */ struct ti_sci_info { struct device *dev; - struct notifier_block nb; const struct ti_sci_desc *desc; struct dentry *d; void __iomem *debug_region; @@ -122,7 +120,6 @@ struct ti_sci_info { #define cl_to_ti_sci_info(c) container_of(c, struct ti_sci_info, cl) #define handle_to_ti_sci_info(h) container_of(h, struct ti_sci_info, handle) -#define reboot_to_ti_sci_info(n) container_of(n, struct ti_sci_info, nb) #ifdef CONFIG_DEBUG_FS @@ -3254,10 +3251,9 @@ devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev, } EXPORT_SYMBOL_GPL(devm_ti_sci_get_resource); -static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode, - void *cmd) +static int tisci_reboot_handler(struct sys_off_data *data) { - struct ti_sci_info *info = reboot_to_ti_sci_info(nb); + struct ti_sci_info *info = data->cb_data; const struct ti_sci_handle *handle = &info->handle; ti_sci_cmd_core_reboot(handle); @@ -3400,10 +3396,9 @@ static int ti_sci_probe(struct platform_device *pdev) ti_sci_setup_ops(info); if (reboot) { - info->nb.notifier_call = tisci_reboot_handler; - info->nb.priority = 128; - - ret = register_restart_handler(&info->nb); + ret = devm_register_restart_handler(dev, + tisci_reboot_handler, + info); if (ret) { dev_err(dev, "reboot registration fail(%d)\n", ret); goto out; From 8c8ff39838e02b6df91b80e086426dcb9ac86908 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 17:37:28 -0500 Subject: [PATCH 307/969] firmware: ti_sci: Unconditionally register reset handler There was once a limitation that there could only be one system reset handler. Due to that we only would register this handler when a non-standard device tree property was found, else we left the default handler in place (usually PSCI). Now that we can have multiple handlers, and TI-SCI reset is always available in the firmware, register this handler unconditionally. This priority is left at the default so higher priority handlers (like PSCI) are still attempted first. Signed-off-by: Andrew Davis Reviewed-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20240326223730.54639-3-afd@ti.com Signed-off-by: Nishanth Menon --- drivers/firmware/ti_sci.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 9885e1763591..160968301b1f 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -3299,7 +3299,6 @@ static int ti_sci_probe(struct platform_device *pdev) struct mbox_client *cl; int ret = -EINVAL; int i; - int reboot = 0; u32 h_id; desc = device_get_match_data(dev); @@ -3323,8 +3322,6 @@ static int ti_sci_probe(struct platform_device *pdev) } } - reboot = of_property_read_bool(dev->of_node, - "ti,system-reboot-controller"); INIT_LIST_HEAD(&info->node); minfo = &info->minfo; @@ -3395,14 +3392,10 @@ static int ti_sci_probe(struct platform_device *pdev) ti_sci_setup_ops(info); - if (reboot) { - ret = devm_register_restart_handler(dev, - tisci_reboot_handler, - info); - if (ret) { - dev_err(dev, "reboot registration fail(%d)\n", ret); - goto out; - } + ret = devm_register_restart_handler(dev, tisci_reboot_handler, info); + if (ret) { + dev_err(dev, "reboot registration fail(%d)\n", ret); + goto out; } dev_info(dev, "ABI: %d.%d (firmware rev 0x%04x '%s')\n", From 345d22f4f45369a33b416a96c92bc273e41d695b Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 17:37:29 -0500 Subject: [PATCH 308/969] ARM: dts: ti: keystone: k2g: Remove ti,system-reboot-controller property The property ti,system-reboot-controller is no longer needed as the reboot handler is now always registered. Remove this property. While here remove the comment about delete-property, all K2G platforms use PMMC, and it wasn't good advice anyway. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326223730.54639-4-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi index 790b29ab0fa2..dafe485dfe19 100644 --- a/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2g.dtsi @@ -256,11 +256,6 @@ pmmc: system-controller@2921c00 { compatible = "ti,k2g-sci"; - /* - * In case of rare platforms that does not use k2g as - * system master, use /delete-property/ - */ - ti,system-reboot-controller; mbox-names = "rx", "tx"; mboxes = <&msgmgr 5 2>, <&msgmgr 0 0>; From 60242b20fe784ef9142050be8b68bd85e94be557 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 17:37:30 -0500 Subject: [PATCH 309/969] dt-bindings: arm: keystone: Remove ti,system-reboot-controller property This property was only ever used in one device. It is no longer needed as what it signaled is now default. Remove this unneeded/unused property. Signed-off-by: Andrew Davis Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240326223730.54639-5-afd@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml index c24ad0968f3e..7f06b1080244 100644 --- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml +++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml @@ -61,10 +61,6 @@ properties: mboxes: minItems: 2 - ti,system-reboot-controller: - description: Determines If system reboot can be triggered by SoC reboot - type: boolean - ti,host-id: $ref: /schemas/types.yaml#/definitions/uint32 description: | @@ -94,7 +90,6 @@ examples: - | pmmc: system-controller@2921800 { compatible = "ti,k2g-sci"; - ti,system-reboot-controller; mbox-names = "rx", "tx"; mboxes = <&msgmgr 5 2>, <&msgmgr 0 0>; From ddbf3204f600a4d1f153498f618369fca352ae00 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 25 Mar 2024 11:55:07 -0500 Subject: [PATCH 310/969] soc: ti: wkup_m3_ipc: Send NULL dummy message instead of pointer message mbox_send_message() sends a u32 bit message, not a pointer to a message. We only convert to a pointer type as a generic type. If we want to send a dummy message of 0, then simply send 0 (NULL). Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240325165507.30323-1-afd@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/wkup_m3_ipc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 6a1c6b34c414..88f774db9208 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -314,7 +313,6 @@ static irqreturn_t wkup_m3_txev_handler(int irq, void *ipc_data) static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc) { struct device *dev = m3_ipc->dev; - mbox_msg_t dummy_msg = 0; int ret; if (!m3_ipc->mbox) { @@ -330,7 +328,7 @@ static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc) * the RX callback to avoid multiple interrupts being received * by the CM3. */ - ret = mbox_send_message(m3_ipc->mbox, &dummy_msg); + ret = mbox_send_message(m3_ipc->mbox, NULL); if (ret < 0) { dev_err(dev, "%s: mbox_send_message() failed: %d\n", __func__, ret); @@ -352,7 +350,6 @@ static int wkup_m3_ping(struct wkup_m3_ipc *m3_ipc) static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc) { struct device *dev = m3_ipc->dev; - mbox_msg_t dummy_msg = 0; int ret; if (!m3_ipc->mbox) { @@ -361,7 +358,7 @@ static int wkup_m3_ping_noirq(struct wkup_m3_ipc *m3_ipc) return -EIO; } - ret = mbox_send_message(m3_ipc->mbox, &dummy_msg); + ret = mbox_send_message(m3_ipc->mbox, NULL); if (ret < 0) { dev_err(dev, "%s: mbox_send_message() failed: %d\n", __func__, ret); From 45ab8daed512258c07fd14536a3633440dabfe84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Feb 2024 11:51:45 +0100 Subject: [PATCH 311/969] arm64: dts: ti: k3-am62p5-sk: minor whitespace cleanup The DTS code coding style expects exactly one space before '{' character. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240208105146.128645-1-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index e86f34e835c1..6694087b3665 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -493,7 +493,7 @@ pinctrl-0 = <&ospi0_pins_default>; bootph-all; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; From a15e5320d91abe68ff1123bb72583d629c49100c Mon Sep 17 00:00:00 2001 From: Andrejs Cainikovs Date: Fri, 15 Mar 2024 11:25:00 +0100 Subject: [PATCH 312/969] arm64: dts: ti: verdin-am62: dahlia: fix audio clock In current configuration, wm8904 codec on Dahlia carrier board provides distorted audio output. This happens due to reference clock is fixed to 25MHz and no FLL is enabled. During playback following parameters are set: 44100Hz: [ 310.276924] wm8904 1-001a: Target BCLK is 1411200Hz [ 310.276990] wm8904 1-001a: Using 25000000Hz MCLK [ 310.277001] wm8904 1-001a: CLK_SYS is 12500000Hz [ 310.277018] wm8904 1-001a: Selected CLK_SYS_RATIO of 256 [ 310.277026] wm8904 1-001a: Selected SAMPLE_RATE of 44100Hz [ 310.277034] wm8904 1-001a: Selected BCLK_DIV of 80 for 1562500Hz BCLK [ 310.277044] wm8904 1-001a: LRCLK_RATE is 35 Deviation = 1411200 vs 1562500 = 10.721% Also, LRCLK_RATE is 35, should be 32. 48000Hz: [ 302.449970] wm8904 1-001a: Target BCLK is 1536000Hz [ 302.450037] wm8904 1-001a: Using 25000000Hz MCLK [ 302.450049] wm8904 1-001a: CLK_SYS is 12500000Hz [ 302.450065] wm8904 1-001a: Selected CLK_SYS_RATIO of 256 [ 302.450074] wm8904 1-001a: Selected SAMPLE_RATE of 48000Hz [ 302.450083] wm8904 1-001a: Selected BCLK_DIV of 80 for 1562500Hz BCLK [ 302.450092] wm8904 1-001a: LRCLK_RATE is 32 Deviation = 1536000 vs 1562500 = 1.725% Enabling wm8904 FLL via providing mclk-fs property to simple-audio-card configures clocks properly, but also adjusts audio reference clock (mclk), which in case of TI AM62 should be avoided, as it only supports 25MHz output [1][2]. This change enables FLL on wm8904 by providing mclk-fs, and drops audio reference clock out of DAI configuration, which prevents simple-audio-card to adjust it before every playback [3]. 41000Hz: [ 111.820533] wm8904 1-001a: FLL configured for 25000000Hz->11289600Hz [ 111.820597] wm8904 1-001a: Clock source is 0 at 11289600Hz [ 111.820651] wm8904 1-001a: Using 11289600Hz FLL clock [ 111.820703] wm8904 1-001a: CLK_SYS is 11289600Hz [ 111.820798] wm8904 1-001a: Target BCLK is 1411200Hz [ 111.820847] wm8904 1-001a: Using 11289600Hz FLL clock [ 111.820894] wm8904 1-001a: CLK_SYS is 11289600Hz [ 111.820933] wm8904 1-001a: Selected CLK_SYS_RATIO of 256 [ 111.820971] wm8904 1-001a: Selected SAMPLE_RATE of 44100Hz [ 111.821009] wm8904 1-001a: Selected BCLK_DIV of 80 for 1411200Hz BCLK [ 111.821051] wm8904 1-001a: LRCLK_RATE is 32 48000Hz: [ 144.119254] wm8904 1-001a: FLL configured for 25000000Hz->12288000Hz [ 144.119309] wm8904 1-001a: Clock source is 0 at 12288000Hz [ 144.119364] wm8904 1-001a: Using 12288000Hz FLL clock [ 144.119413] wm8904 1-001a: CLK_SYS is 12288000Hz [ 144.119512] wm8904 1-001a: Target BCLK is 1536000Hz [ 144.119561] wm8904 1-001a: Using 12288000Hz FLL clock [ 144.119608] wm8904 1-001a: CLK_SYS is 12288000Hz [ 144.119646] wm8904 1-001a: Selected CLK_SYS_RATIO of 256 [ 144.119685] wm8904 1-001a: Selected SAMPLE_RATE of 48000Hz [ 144.119723] wm8904 1-001a: Selected BCLK_DIV of 80 for 1536000Hz BCLK [ 144.119764] wm8904 1-001a: LRCLK_RATE is 32 [1]: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1175479/processor-sdk-am62x-output-audio_ext_refclk0-as-mclk-for-codec-and-mcbsp/4444986#4444986 [2]: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1188051/am625-audio_ext_refclk1-clock-output---dts-support/4476322#4476322 [3]: sound/soc/generic/simple-card-utils.c#L441 Fixes: f5bf894c865b ("arm64: dts: ti: verdin-am62: dahlia: add sound card") Suggested-by: Charles Keepax Signed-off-by: Andrejs Cainikovs Reviewed-by: Charles Keepax Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240315102500.18492-1-andrejs.cainikovs@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 6c4cec8728e4..e42085aa118f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -22,6 +22,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,mclk-fs = <256>; simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", @@ -35,7 +36,6 @@ "Line", "Line In Jack"; codec_dai: simple-audio-card,codec { - clocks = <&audio_refclk1>; sound-dai = <&wm8904_1a>; }; From f70a88829723c1b462ea0fec15fa75809a0d670b Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 20 Mar 2024 15:29:37 +0100 Subject: [PATCH 313/969] arm64: dts: ti: verdin-am62: Set memory size to 2gb The maximum DDR RAM size stuffed on the Verdin AM62 is 2GB, correct the memory node accordingly. Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") Cc: Signed-off-by: Max Krummenacher Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240320142937.2028707-1-max.oss.09@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index e8d8857ad51f..8c837467069b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -76,7 +76,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */ }; opp-table { From ef00a95def6f6f5e2bd18ad3cb73834650768288 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 25 Mar 2024 09:33:40 +0100 Subject: [PATCH 314/969] arm64: dts: ti: verdin-am62: use SD1 CD as GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TI SDHCI instance has a hardware debounce timer of 1 second as described in commit 7ca0f166f5b2 ("mmc: sdhci_am654: Add workaround for card detect debounce timer"), because of this the boot time increases of up to 1 second. Workaround the issue the same way that is done on arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts, using the SD1 CD as GPIO. Suggested-by: Nishanth Menon Reported-by: João Paulo Silva Gonçalves Closes: https://lore.kernel.org/all/0e81af80de3d55e72f79af83fa5db87f5c9938f8.camel@toradex.com/ Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240325083340.89568-1-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 8c837467069b..c5091fa0c240 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -457,6 +457,13 @@ >; }; + /* Verdin SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: main-gpio1-48-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ /* SODIMM 84 */ + >; + }; + /* Verdin DSI_1_INT# (pulled-up as active-low) */ pinctrl_dsi1_int: main-gpio1-49-default-pins { pinctrl-single,pins = < @@ -571,7 +578,6 @@ AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ - AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ >; }; @@ -1441,10 +1447,12 @@ /* Verdin SD_1 */ &sdhci1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>; + pinctrl-0 = <&pinctrl_sdhci1>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; disable-wp; vmmc-supply = <®_sdhc1_vmmc>; vqmmc-supply = <®_sdhc1_vqmmc>; + ti,fails-without-test-cd; status = "disabled"; }; From a2a6bbd108da8dcbf378bc452ce0cf0e5b143f99 Mon Sep 17 00:00:00 2001 From: Sukrut Bellary Date: Mon, 25 Mar 2024 09:35:10 -0500 Subject: [PATCH 315/969] arm64: dts: ti: k3-am625-beagleplay: Use mmc-pwrseq for wl18xx enable BeaglePlay SBC[1] has Texas Instrument's WL18xx WiFi chipset[2]. Currently, WLAN_EN is configured as regulator and regulator-always-on. However, the timing and wlan_en sequencing is not correctly modelled. This causes the sdio access to fail during runtime-pm power operations saving or during system suspend/resume/hibernation/freeze operations. This is because the WLAN_EN line is not deasserted to low '0' to power down the WiFi. So during restore, the WiFi driver tries to load the FW without following correct power sequence. WLAN_EN => '1'/assert (high) to power-up the chipset. Use mmc-pwrseq-simple to drive TI's WiFi (WL18xx) chipset enable 'WLAN_EN'. mmc-pwrseq-simple provides power sequence flexibility with support for post power-on and power-off delays. Typical log signature that indicates this bug is: wl1271_sdio mmc2:0001:2: sdio write failed (-110) Followed by possibly a kernel warning (depending on firmware present): WARNING: CPU: 1 PID: 45 at drivers/net/wireless/ti/wlcore/sdio.c:123 wl12xx_sdio_raw_write+0xe4/0x168 [wlcore_sdio] [1] https://www.beagleboard.org/boards/beagleplay [2] https://www.ti.com/lit/ds/symlink/wl1807mod.pdf Fixes: f5a731f0787f ("arm64: dts: ti: Add k3-am625-beagleplay") Suggested-by: Shengyu Qu Signed-off-by: Sukrut Bellary Tested-by: Robert Nelson Link: https://lore.kernel.org/r/20240325143511.2144768-1-nm@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 27 +++++++++---------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index a34e0df2ab86..84977c1cc85d 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -82,6 +82,17 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pins_default>; + /* Internal power on time(Figure 8-3) * 2 */ + post-power-on-delay-ms = <10>; + /* Re-enable time(Figure 8-2) + 20uS */ + power-off-delay-us = <80>; + reset-gpios = <&main_gpio0 38 GPIO_ACTIVE_LOW>; + }; + vsys_5v0: regulator-1 { bootph-all; compatible = "regulator-fixed"; @@ -104,20 +115,6 @@ regulator-boot-on; }; - wlan_en: regulator-3 { - /* OUTPUT of SN74AVC2T244DQMR */ - compatible = "regulator-fixed"; - regulator-name = "wlan_en"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - vin-supply = <&vdd_3v3>; - gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_en_pins_default>; - }; - vdd_3v3_sd: regulator-4 { /* output of TPS22918DBVR-U21 */ bootph-all; @@ -839,13 +836,13 @@ }; &sdhci2 { - vmmc-supply = <&wlan_en>; pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; non-removable; ti,fails-without-test-cd; cap-power-off-card; keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; assigned-clocks = <&k3_clks 157 158>; assigned-clock-parents = <&k3_clks 157 160>; #address-cells = <1>; From 104996ca7946daf57c2b97f8dde581f042c90118 Mon Sep 17 00:00:00 2001 From: Markus Schneider-Pargmann Date: Mon, 25 Mar 2024 16:20:29 +0100 Subject: [PATCH 316/969] arm64: dts: ti: k3-am62-lp-sk: Remove tps65219 power-button On am62-lp-sk the PMIC is not wired up to a power button. Remove this property. This fixes issues observed when entering a very deep sleep state that is not yet available upstream. Fixes: e6a51ffabfc1 ("arm64: ti: dts: Add support for AM62x LP SK") Signed-off-by: Markus Schneider-Pargmann Link: https://lore.kernel.org/r/20240325152029.2933445-1-msp@baylibre.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index c4149059a4c5..9a17bd3e59c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -166,7 +166,6 @@ interrupt-parent = <&gic500>; interrupts = ; - ti,power-button; regulators { buck1_reg: buck1 { From 2910a4b938d666d85cff44ec443e1a9f720daa5d Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:54:36 -0500 Subject: [PATCH 317/969] arm64: dts: ti: k3-am65: Remove UART baud rate selection As described in the binding document for the "current-speed" property: "This should only be present in case a driver has no chance to know the baud rate of the slave device." This is not the case for the UART used in K3 devices, the current baud-rate can be calculated from the registers. Having this property has the effect of actually skipping the baud-rate setup in some drivers as it assumes it will already be set to this rate, which may not always be the case. It seems this property's purpose was mistaken as selecting the desired baud-rate, which it does not. It would have been wrong to select that here anyway as DT is not the place for configuration, especially when there are already more standard ways to set serial baud-rates. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185441.29656-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index ff857117d719..670557c89f75 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -89,7 +89,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 6ff3ccc39fb4..4f808e508975 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -43,7 +43,6 @@ reg = <0x00 0x40a00000 0x00 0x100>; interrupts = ; clock-frequency = <96000000>; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index 37527890ddea..eee072e44a42 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -59,7 +59,6 @@ reg = <0x42300000 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; From e95c8826eefcdc5a8cc526ebaa561beb13050e44 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:54:37 -0500 Subject: [PATCH 318/969] arm64: dts: ti: k3-am64: Remove UART baud rate selection As described in the binding document for the "current-speed" property: "This should only be present in case a driver has no chance to know the baud rate of the slave device." This is not the case for the UART used in K3 devices, the current baud-rate can be calculated from the registers. Having this property has the effect of actually skipping the baud-rate setup in some drivers as it assumes it will already be set to this rate, which may not always be the case. It seems this property's purpose was mistaken as selecting the desired baud-rate, which it does not. It would have been wrong to select that here anyway as DT is not the place for configuration, especially when there are already more standard ways to set serial baud-rates. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185441.29656-2-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 - arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 -- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 - 3 files changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 53fe1d065ddb..e20e4ffd0f1f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -473,7 +473,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; }; /* main_uart1 is reserved for firmware usage */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8237b8c815b8..dc774f9c7541 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -275,7 +275,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; }; &main_uart1 { @@ -283,7 +282,6 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; - current-speed = <115200>; }; &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 67cd41bf806e..5b028b3a3192 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -381,7 +381,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; - current-speed = <115200>; }; &main_uart1 { From 52f02af997faca4389169f4cca5086228daf4b01 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:54:38 -0500 Subject: [PATCH 319/969] arm64: dts: ti: k3-j7200: Remove UART baud rate selection As described in the binding document for the "current-speed" property: "This should only be present in case a driver has no chance to know the baud rate of the slave device." This is not the case for the UART used in K3 devices, the current baud-rate can be calculated from the registers. Having this property has the effect of actually skipping the baud-rate setup in some drivers as it assumes it will already be set to this rate, which may not always be the case. It seems this property's purpose was mistaken as selecting the desired baud-rate, which it does not. It would have been wrong to select that here anyway as DT is not the place for configuration, especially when there are already more standard ways to set serial baud-rates. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185441.29656-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 10 ---------- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 -- 2 files changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 657f9cc9f4ea..9386bf3ef9f6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -440,7 +440,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; @@ -452,7 +451,6 @@ reg = <0x00 0x02810000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; @@ -464,7 +462,6 @@ reg = <0x00 0x02820000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; @@ -476,7 +473,6 @@ reg = <0x00 0x02830000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; @@ -488,7 +484,6 @@ reg = <0x00 0x02840000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; @@ -500,7 +495,6 @@ reg = <0x00 0x02850000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; @@ -512,7 +506,6 @@ reg = <0x00 0x02860000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; @@ -524,7 +517,6 @@ reg = <0x00 0x02870000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; @@ -536,7 +528,6 @@ reg = <0x00 0x02880000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; @@ -548,7 +539,6 @@ reg = <0x00 0x02890000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 7cf21c99956e..c547bc8fb608 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -259,7 +259,6 @@ reg = <0x00 0x42300000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 2>; clock-names = "fclk"; @@ -271,7 +270,6 @@ reg = <0x00 0x40a00000 0x00 0x100>; interrupts = ; clock-frequency = <96000000>; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 2>; clock-names = "fclk"; From cef23c6b15030f056afbbdddc0323b406c392fa2 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:54:39 -0500 Subject: [PATCH 320/969] arm64: dts: ti: k3-j721e: Remove UART baud rate selection As described in the binding document for the "current-speed" property: "This should only be present in case a driver has no chance to know the baud rate of the slave device." This is not the case for the UART used in K3 devices, the current baud-rate can be calculated from the registers. Having this property has the effect of actually skipping the baud-rate setup in some drivers as it assumes it will already be set to this rate, which may not always be the case. It seems this property's purpose was mistaken as selecting the desired baud-rate, which it does not. It would have been wrong to select that here anyway as DT is not the place for configuration, especially when there are already more standard ways to set serial baud-rates. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185441.29656-4-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ---------- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 -- 2 files changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c7eafbc862f9..0da785be80ff 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1337,7 +1337,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; @@ -1349,7 +1348,6 @@ reg = <0x00 0x02810000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 0>; clock-names = "fclk"; @@ -1361,7 +1359,6 @@ reg = <0x00 0x02820000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 0>; clock-names = "fclk"; @@ -1373,7 +1370,6 @@ reg = <0x00 0x02830000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 0>; clock-names = "fclk"; @@ -1385,7 +1381,6 @@ reg = <0x00 0x02840000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 0>; clock-names = "fclk"; @@ -1397,7 +1392,6 @@ reg = <0x00 0x02850000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 0>; clock-names = "fclk"; @@ -1409,7 +1403,6 @@ reg = <0x00 0x02860000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 0>; clock-names = "fclk"; @@ -1421,7 +1414,6 @@ reg = <0x00 0x02870000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 0>; clock-names = "fclk"; @@ -1433,7 +1425,6 @@ reg = <0x00 0x02880000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 0>; clock-names = "fclk"; @@ -1445,7 +1436,6 @@ reg = <0x00 0x02890000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 0>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 4618b697fbc4..8fc768d84b75 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -243,7 +243,6 @@ reg = <0x00 0x42300000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 0>; clock-names = "fclk"; @@ -255,7 +254,6 @@ reg = <0x00 0x40a00000 0x00 0x100>; interrupts = ; clock-frequency = <96000000>; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; From 2586d87cdaa98443c289a9c65df744021a84267f Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:54:40 -0500 Subject: [PATCH 321/969] arm64: dts: ti: k3-j721s2: Remove UART baud rate selection As described in the binding document for the "current-speed" property: "This should only be present in case a driver has no chance to know the baud rate of the slave device." This is not the case for the UART used in K3 devices, the current baud-rate can be calculated from the registers. Having this property has the effect of actually skipping the baud-rate setup in some drivers as it assumes it will already be set to this rate, which may not always be the case. It seems this property's purpose was mistaken as selecting the desired baud-rate, which it does not. It would have been wrong to select that here anyway as DT is not the place for configuration, especially when there are already more standard ways to set serial baud-rates. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185441.29656-5-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 10 ---------- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 -- 2 files changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index b70c8615e3c1..3cb06a7e4117 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -459,7 +459,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 146 3>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; @@ -470,7 +469,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 350 3>; clock-names = "fclk"; power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; @@ -481,7 +479,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 351 3>; clock-names = "fclk"; power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; @@ -492,7 +489,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 352 3>; clock-names = "fclk"; power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; @@ -503,7 +499,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 353 3>; clock-names = "fclk"; power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; @@ -514,7 +509,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 354 3>; clock-names = "fclk"; power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; @@ -525,7 +519,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 355 3>; clock-names = "fclk"; power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; @@ -536,7 +529,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 356 3>; clock-names = "fclk"; power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; @@ -547,7 +539,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 357 3>; clock-names = "fclk"; power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; @@ -558,7 +549,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 358 3>; clock-names = "fclk"; power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index eaf7f709440e..5ccb04c7c462 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -298,7 +298,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 359 3>; clock-names = "fclk"; power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; @@ -309,7 +308,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 149 3>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; From 7d049a551467556dc7699ba7e71356c03f4fbd6f Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:54:41 -0500 Subject: [PATCH 322/969] arm64: dts: ti: k3-j784s4: Remove UART baud rate selection As described in the binding document for the "current-speed" property: "This should only be present in case a driver has no chance to know the baud rate of the slave device." This is not the case for the UART used in K3 devices, the current baud-rate can be calculated from the registers. Having this property has the effect of actually skipping the baud-rate setup in some drivers as it assumes it will already be set to this rate, which may not always be the case. It seems this property's purpose was mistaken as selecting the desired baud-rate, which it does not. It would have been wrong to select that here anyway as DT is not the place for configuration, especially when there are already more standard ways to set serial baud-rates. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185441.29656-6-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 10 ---------- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 2 -- 2 files changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index b67c37460a73..d42f25cacf23 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -404,7 +404,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; @@ -415,7 +414,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02810000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 388 0>; clock-names = "fclk"; power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; @@ -426,7 +424,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02820000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 389 0>; clock-names = "fclk"; power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; @@ -437,7 +434,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02830000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 390 0>; clock-names = "fclk"; power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; @@ -448,7 +444,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02840000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 391 0>; clock-names = "fclk"; power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; @@ -459,7 +454,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02850000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 392 0>; clock-names = "fclk"; power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; @@ -470,7 +464,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02860000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 393 0>; clock-names = "fclk"; power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; @@ -481,7 +474,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02870000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 394 0>; clock-names = "fclk"; power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; @@ -492,7 +484,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02880000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 395 0>; clock-names = "fclk"; power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; @@ -503,7 +494,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02890000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 396 0>; clock-names = "fclk"; power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 77a8d99139ec..b47338e0f481 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -304,7 +304,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 397 0>; clock-names = "fclk"; power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; @@ -315,7 +314,6 @@ compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x40a00000 0x00 0x200>; interrupts = ; - current-speed = <115200>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; From 3358aedf89944dbbded7609a363ae28bbc0a03eb Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 27 Mar 2024 19:28:00 +0100 Subject: [PATCH 323/969] arm64: dts: ti: verdin-am62: mallow: fix GPIOs pinctrl Generic GPIOs pinctrl nodes are not correct, gpio[1-4] are into the MCU domain and should be into &mcu_gpio0, gpio[5-8] were missing and are added in this commit. Fixes: 7698622fbcf4 ("arm64: dts: ti: Add verdin am62 mallow board") Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240327182801.5997-2-francesco@dolcini.it Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi index 77b1beb638ad..cd81a606c435 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi @@ -81,10 +81,10 @@ &main_gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, - <&pinctrl_gpio_1>, - <&pinctrl_gpio_2>, - <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; }; /* Verdin I2C_1 */ @@ -149,6 +149,14 @@ status = "okay"; }; +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + /* Verdin I2C_3_HDMI */ &mcu_i2c0 { status = "okay"; From 69ef7d9c2905f11475fa2724e3621c95638ce55b Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 27 Mar 2024 19:28:01 +0100 Subject: [PATCH 324/969] arm64: dts: ti: k3-am625-verdin: add PCIe reset gpio hog Add a GPIO hog to release PCIe reset on the carrier board, this is required to use M.2 or mPCIe cards. Verdin AM62 does not have any PCIe interface, however the Verdin family has PCIe and normally an M.2 or mPCIe slot is available in the carrier board that can be used with cards that use only the USB interface toward the host CPU, for example cellular network modem. Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240327182801.5997-3-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 8 +++++++- arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi | 8 +++++++- arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi | 8 +++++++- arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi | 8 +++++++- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 9 +++++++++ 5 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index e42085aa118f..9202181fbd65 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -160,7 +160,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -211,6 +212,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi index be62648e7818..74eec1a1abca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -181,7 +181,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -232,6 +233,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi index cd81a606c435..754216d8ac14 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi @@ -154,7 +154,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -200,6 +201,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi index 997dfafd27eb..7372d392ec8a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -159,7 +159,8 @@ pinctrl-0 = <&pinctrl_gpio_1>, <&pinctrl_gpio_2>, <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; }; /* Verdin I2C_3_HDMI */ @@ -205,6 +206,11 @@ status = "okay"; }; +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + /* Verdin UART_2 */ &wkup_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index c5091fa0c240..ff7cab0ff76c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1413,6 +1413,15 @@ "", "", ""; + + verdin_pcie_1_reset_hog: pcie-1-reset-hog { + gpio-hog; + /* Verdin PCIE_1_RESET# (SODIMM 244) */ + gpios = <0 GPIO_ACTIVE_LOW>; + line-name = "PCIE_1_RESET#"; + output-low; + status = "disabled"; + }; }; /* Verdin CAN_2 */ From 41f6bb20fa4a0415dda75be55d8ec2a0ba7d161e Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Tue, 2 Apr 2024 09:08:24 -0700 Subject: [PATCH 325/969] arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Increase CAN max bitrate The phyBOARD-Lyra has one TCAN1044VDD CAN transceiver which supports CAN FD at 8 Mbps. Increase the maximum bitrate to 8 Mbps. Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240402160825.1516036-2-nmorrisson@phytec.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index a83a90497857..e225d76d02c8 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -31,7 +31,7 @@ can_tc1: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; - max-bitrate = <5000000>; + max-bitrate = <8000000>; standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; }; From 853d39f96c8828ae03d654decc9f162233c0daa8 Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Tue, 2 Apr 2024 09:08:25 -0700 Subject: [PATCH 326/969] arm64: dts: ti: k3-am642-phyboard-electra-rdk: Increase CAN max bitrate The phyBOARD-Electra has two TCAN1044VDD CAN transceivers which support CAN FD at 8 Mbps. Increase the maximum bitrate to 8 Mbps. Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240402160825.1516036-3-nmorrisson@phytec.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index dc774f9c7541..6df331ccb970 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -42,7 +42,7 @@ pinctrl-names = "default"; pinctrl-0 = <&can_tc1_pins_default>; #phy-cells = <0>; - max-bitrate = <5000000>; + max-bitrate = <8000000>; standby-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; }; @@ -51,7 +51,7 @@ pinctrl-names = "default"; pinctrl-0 = <&can_tc2_pins_default>; #phy-cells = <0>; - max-bitrate = <5000000>; + max-bitrate = <8000000>; standby-gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>; }; From ff369c9eb61182aeb66aa9e83c994d025e5ddc31 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 3 Apr 2024 12:15:45 +0200 Subject: [PATCH 327/969] arm64: dts: ti: k3-{am62p,j722s}: Disable ethernet by default Device tree best practice is to disable any external interface in the dtsi and just enable them if needed in the device tree. Thus, disable the ethernet switch and its ports by default and just enable the ones used by the EVMs in their device trees. There is no functional change. Signed-off-by: Michael Walle Acked-by: Andrew Davis Link: https://lore.kernel.org/r/20240403101545.3932437-1-mwalle@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 3 +++ arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 5 +---- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 7337a9e13535..88bc64111234 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -673,6 +673,7 @@ assigned-clock-parents = <&k3_clks 13 11>; clock-names = "fck"; power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; dmas = <&main_pktdma 0xc600 15>, <&main_pktdma 0xc601 15>, @@ -696,6 +697,7 @@ label = "port1"; phys = <&phy_gmii_sel 1>; mac-address = [00 00 00 00 00 00]; + status = "disabled"; }; cpsw_port2: port@2 { @@ -704,6 +706,7 @@ label = "port2"; phys = <&phy_gmii_sel 2>; mac-address = [00 00 00 00 00 00]; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 6694087b3665..6a9c99c5fb2a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -431,16 +431,19 @@ pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; + status = "okay"; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; + status = "okay"; }; &cpsw_port2 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + status = "okay"; }; &cpsw3g_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index cee3a8661d5e..4b36db949a52 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -226,10 +226,7 @@ &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy0>; -}; - -&cpsw_port2 { - status = "disabled"; + status = "okay"; }; &main_gpio1 { From 3cf109df43b3c8c743c20c532c448888964fe4d1 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 3 Apr 2024 12:23:02 +0200 Subject: [PATCH 328/969] arm64: dts: ti: k3-j722s-evm: Enable eMMC support The J722S EVM has an on-board eMMC. Enable the SDHC interface for it. There is no pinmuxing required because the interface has dedicated pins. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20240403102302.3934932-1-mwalle@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 4b36db949a52..78032caeb5fc 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -366,6 +366,13 @@ }; +&sdhci0 { + disable-wp; + bootph-all; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; From cbb97fe18e299ece1c0074924c630de6a19b320f Mon Sep 17 00:00:00 2001 From: Diederik de Haas Date: Sat, 6 Apr 2024 19:28:04 +0200 Subject: [PATCH 329/969] arm64: dts: rockchip: Fix ordering of nodes on rk3588s Fix the ordering of the main nodes by sorting them alphabetically and then the ones with a memory address sequentially by that address. Signed-off-by: Diederik de Haas Link: https://lore.kernel.org/r/20240406172821.34173-1-didi.debian@cknow.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 304 +++++++++++----------- 1 file changed, 152 insertions(+), 152 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 89d40cff635f..ac5bd630f155 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -347,6 +347,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { optee: optee { compatible = "linaro,optee-tz"; @@ -394,11 +399,6 @@ #clock-cells = <0>; }; - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = , @@ -436,6 +436,62 @@ }; }; + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; @@ -501,62 +557,6 @@ status = "disabled"; }; - gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = , - , - ; - interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; - }; - pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; @@ -702,74 +702,6 @@ status = "disabled"; }; - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = ; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>; @@ -1140,6 +1072,87 @@ }; }; + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = ; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1431,6 +1444,16 @@ reg = <0x0 0xfdf82200 0x0 0x20>; }; + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = , + , + , + ; + rockchip,pmu = <&pmu1grf>; + }; + pcie2x1l1: pcie@fe180000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; bus-range = <0x30 0x3f>; @@ -1533,16 +1556,6 @@ }; }; - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = , - , - , - ; - rockchip,pmu = <&pmu1grf>; - }; - gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -2543,19 +2556,6 @@ #interrupt-cells = <2>; }; }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; }; #include "rk3588s-pinctrl.dtsi" From 6eb006d7c8271d4ff811b8f13b40e527d35d88e1 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 5 Apr 2024 12:14:25 +0200 Subject: [PATCH 330/969] dt-bindings: arm: rockchip: Add Protonic MECSBC board MECSBC is a single board computer for blood analysis machines from RR-Mechatronics, designed and manufactured by Protonic Holland, based on the Rockchip RK3568 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20240405-protonic-mecsbc-v2-1-0a6fedc78b9f@pengutronix.de Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 99bd5e2c76a0..a4ae51d0a839 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -700,6 +700,11 @@ properties: - powkiddy,x55 - const: rockchip,rk3566 + - description: Protonic MECSBC board + items: + - const: prt,mecsbc + - const: rockchip,rk3568 + - description: QNAP TS-433-4G 4-Bay NAS items: - const: qnap,ts433 From 6f9dfb7358535136e49d6fe9d31409f20f8cb9a7 Mon Sep 17 00:00:00 2001 From: David Jander Date: Fri, 5 Apr 2024 12:14:26 +0200 Subject: [PATCH 331/969] arm64: dts: rockchip: add Protonic MECSBC device-tree MECSBC is a single board computer for blood analysis machines from RR-Mechatronics, designed and manufactured by Protonic Holland, based on the Rockchip RK3568 SoC. Signed-off-by: David Jander Signed-off-by: Sascha Hauer Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20240405-protonic-mecsbc-v2-2-0a6fedc78b9f@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3568-mecsbc.dts | 404 ++++++++++++++++++ 2 files changed, 405 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 0192980ef37f..28e262e22c4e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts b/arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts new file mode 100644 index 000000000000..c2dfffc638d1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-mecsbc.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Protonic MECSBC"; + compatible = "prt,mecsbc", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + tas2562-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Speaker"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&tas2562>; + }; + }; + + vdd_gpu: regulator-vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <915000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-dutycycle-range = <0 100>; /* dutycycle inverted 0% => 0.915V */ + }; + + p3v3: regulator-p3v3 { + compatible = "regulator-fixed"; + regulator-name = "p3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + p1v8: regulator-p1v8 { + compatible = "regulator-fixed"; + regulator-name = "p1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_sd: regulator-sd { + compatible = "regulator-gpio"; + enable-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-name = "sdcard-gpio-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1>, <3300000 0x0>; + }; + + vdd_npu: regulator-vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <915000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-dutycycle-range = <0 100>; /* dutycycle inverted 0% => 0.915V */ + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_opp_table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <915000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <915000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <915000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <920000>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <950000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + }; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "okay"; + + tas2562: amplifier@4c { + compatible = "ti,tas2562"; + reg = <0x4c>; + #sound-dai-cells = <0>; + shutdown-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tas2562>; + interrupts = ; + ti,imon-slot-no = <0>; + }; +}; + +&i2c5 { + status = "okay"; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + rtc@51 { + compatible = "nxp,pcf85363"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + }; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x2>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20m1_pins>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&p3v3>; + status = "okay"; +}; + +&pinctrl { + ethernet { + eth_phy1_rst: eth-phy1-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tas2562 { + pinctrl_tas2562: tas2562 { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&p3v3>; + pmuio2-supply = <&p3v3>; + vccio1-supply = <&p1v8>; + vccio2-supply = <&p1v8>; + vccio3-supply = <&vcc_sd>; + vccio4-supply = <&p1v8>; + vccio5-supply = <&p3v3>; + vccio6-supply = <&p1v8>; + vccio7-supply = <&p3v3>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; +}; + +&saradc { + vref-supply = <&p1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&p3v3>; + vqmmc-supply = <&p1v8>; + mmc-hs200-1_8v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&p3v3>; + vqmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; From dbda7254e7df661fd4022c07dda3a7c9660eee47 Mon Sep 17 00:00:00 2001 From: Dmitry Yashin Date: Wed, 3 Apr 2024 20:12:27 +0500 Subject: [PATCH 332/969] dt-bindings: arm: rockchip: add Forlinx FET3588-C FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588. This SoM used by OK3588-C Board. FET3588-C features: - Rockchip RK3588 - LPDDR4 4/8 GB - eMMC 32/64 GB Add devicetree binding for Forlinx FET3588-C SoM. Signed-off-by: Dmitry Yashin Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240403151229.30577-2-dmt.yashin@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index a4ae51d0a839..6d4144a921f3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -198,6 +198,13 @@ properties: - const: firefly,rk3568-roc-pc - const: rockchip,rk3568 + - description: Forlinx FET3588-C SoM + items: + - enum: + - forlinx,ok3588-c + - const: forlinx,fet3588-c + - const: rockchip,rk3588 + - description: FriendlyElec NanoPi R2 series boards items: - enum: From f7a9a80da93178fe43b72f13dd55d717b5efff21 Mon Sep 17 00:00:00 2001 From: Dmitry Yashin Date: Wed, 3 Apr 2024 20:12:28 +0500 Subject: [PATCH 333/969] arm64: dts: rockchip: add Forlinx FET3588-C FET3588-C is an System on Module made by Forlinx based on Rockchip RK3588. This SoM used by OK3588-C Board. FET3588-C features: - Rockchip RK3588 - LPDDR4 4/8 GB - eMMC 32/64 GB Add support for Forlinx FET3588-C SoM. Signed-off-by: Dmitry Yashin Link: https://lore.kernel.org/r/20240403151229.30577-3-dmt.yashin@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-fet3588-c.dtsi | 558 ++++++++++++++++++ 1 file changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi new file mode 100644 index 000000000000..47e64d547ea9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include "rk3588.dtsi" + +/ { + compatible = "forlinx,fet3588-c", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + io-led { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc4v0_sys: vcc4v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pinctrl { + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; From ae914513b2f566d995a41638b643ac8589b6275e Mon Sep 17 00:00:00 2001 From: Dmitry Yashin Date: Wed, 3 Apr 2024 20:12:29 +0500 Subject: [PATCH 334/969] arm64: dts: rockchip: add Forlinx OK3588-C OK3588-C is the carrier board for FET3588-C System on Module. OK3588-C features: - 2x 1GbE Realtek RTL8211F Ethernet - 1x HDMI Type A out - 1x HDMI Type A in - 3x USB 3.1 Type C (2x OTG and 1x serial console) - 1x USB 2.0 Type A - 1x USB 3.0 & USB 2.0 Combo M.2 M Key (4G/5G modem) - 1x PCIE 2.0 M.2 E Key (1 lane) - 1x PCIE 2.0 PCIe (1 lane) - 1x PCIE 3.0 PCIe (4 lanes) - 1x TF scard slot - 5x MIPI CSI - 2x MIP DSI - 2x CAN2.0B - 1x RS485 - 1x NAU8822 onboard audio - 1x FAN connector - 1x RTC - 20-pin expansion header - ADC keys Add support for Forlinx OK3588-C board. Signed-off-by: Dmitry Yashin Link: https://lore.kernel.org/r/20240403151229.30577-4-dmt.yashin@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-ok3588-c.dts | 409 ++++++++++++++++++ 2 files changed, 410 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 28e262e22c4e..df28f1ba3a1a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-jaguar.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts new file mode 100644 index 000000000000..009566d881f3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include "rk3588-fet3588-c.dtsi" + +/ { + model = "Forlinx OK3588-C Board"; + compatible = "forlinx,ok3588-c", "forlinx,fet3588-c", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc1 = &sdmmc; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = ; + press-threshold-microvolt = <400>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-volume-up { + label = "V+/Recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + button-volume-down { + label = "V-"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "ESC"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 50000 0>; + #cooling-cells = <2>; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "RK3588 OK3588-C Audio"; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,pin-switches = "Headphones", "Speaker"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Speaker", "Speaker", + "Microphone", "Internal Microphone", + "Microphone", "Headset Microphone"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "LMICP", "Headset Microphone", + "RMICP", "Internal Microphone"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&nau8822>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v8_sys: vcc1v8-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3_pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + tx_delay = <0x44>; + rx_delay = <0x00>; + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + tx_delay = <0x44>; + rx_delay = <0x00>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + tca6424a: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio1>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&tca6424a_int>; + vcc-supply = <&vcc3v3_sys>; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + nau8822: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@2 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x2>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_0_rst: rtl8211f-0-rst { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rtl8211f_1_rst: rtl8211f-1-rst { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tca6424a { + tca6424a_int: tca6424a-int { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; From 2f528020a29021a9e5da1b85488993e8d9808a38 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 21:58:50 -0400 Subject: [PATCH 335/969] sparc32: make __cmpxchg_u32() return u32 Conversion between u32 and unsigned long is tautological there, and the only use of return value is to return it from __cmpxchg() (which return unsigned long). Get rid of explicit casts in __cmpxchg_u32() call, while we are at it - normal conversions for arguments will do just fine. Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/sparc/include/asm/cmpxchg_32.h | 4 ++-- arch/sparc/lib/atomic32.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/sparc/include/asm/cmpxchg_32.h b/arch/sparc/include/asm/cmpxchg_32.h index d0af82c240b7..2a05cb236480 100644 --- a/arch/sparc/include/asm/cmpxchg_32.h +++ b/arch/sparc/include/asm/cmpxchg_32.h @@ -39,7 +39,7 @@ static __always_inline unsigned long __arch_xchg(unsigned long x, __volatile__ v /* bug catcher for when unsupported size is used - won't link */ void __cmpxchg_called_with_bad_pointer(void); /* we only need to support cmpxchg of a u32 on sparc */ -unsigned long __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_); +u32 __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_); /* don't worry...optimizer will get rid of most of this */ static inline unsigned long @@ -47,7 +47,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) { switch (size) { case 4: - return __cmpxchg_u32((u32 *)ptr, (u32)old, (u32)new_); + return __cmpxchg_u32(ptr, old, new_); default: __cmpxchg_called_with_bad_pointer(); break; diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index cf80d1ae352b..d90d756123d8 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -159,7 +159,7 @@ unsigned long sp32___change_bit(unsigned long *addr, unsigned long mask) } EXPORT_SYMBOL(sp32___change_bit); -unsigned long __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) +u32 __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) { unsigned long flags; u32 prev; @@ -169,7 +169,7 @@ unsigned long __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) *ptr = new; spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags); - return (unsigned long)prev; + return prev; } EXPORT_SYMBOL(__cmpxchg_u32); From b7e2a6389e146325227d90eb3ee47bf11647cde6 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 22:07:58 -0400 Subject: [PATCH 336/969] sparc32: make the first argument of __cmpxchg_u64() volatile u64 * ... to match all cmpxchg variants. Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/sparc/include/asm/cmpxchg_32.h | 2 +- arch/sparc/lib/atomic32.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sparc/include/asm/cmpxchg_32.h b/arch/sparc/include/asm/cmpxchg_32.h index 2a05cb236480..05d5f86a56dc 100644 --- a/arch/sparc/include/asm/cmpxchg_32.h +++ b/arch/sparc/include/asm/cmpxchg_32.h @@ -63,7 +63,7 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) (unsigned long)_n_, sizeof(*(ptr))); \ }) -u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new); +u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new); #define arch_cmpxchg64(ptr, old, new) __cmpxchg_u64(ptr, old, new) #include diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index d90d756123d8..e15affbbb523 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -173,7 +173,7 @@ u32 __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) } EXPORT_SYMBOL(__cmpxchg_u32); -u64 __cmpxchg_u64(u64 *ptr, u64 old, u64 new) +u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new) { unsigned long flags; u64 prev; From d7b52b48f006ea3dd2e682097a91eeda9dfb3df9 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 22:12:30 -0400 Subject: [PATCH 337/969] sparc32: unify __cmpxchg_u{32,64} Add a macro that expands to one of those when given u32 or u64 as an argument - atomic32.c has a lot of similar stuff already. Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/sparc/lib/atomic32.c | 39 +++++++++++++++------------------------ 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index e15affbbb523..0d215a772428 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -159,32 +159,23 @@ unsigned long sp32___change_bit(unsigned long *addr, unsigned long mask) } EXPORT_SYMBOL(sp32___change_bit); -u32 __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) -{ - unsigned long flags; - u32 prev; +#define CMPXCHG(T) \ + T __cmpxchg_##T(volatile T *ptr, T old, T new) \ + { \ + unsigned long flags; \ + T prev; \ + \ + spin_lock_irqsave(ATOMIC_HASH(ptr), flags); \ + if ((prev = *ptr) == old) \ + *ptr = new; \ + spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags);\ + \ + return prev; \ + } - spin_lock_irqsave(ATOMIC_HASH(ptr), flags); - if ((prev = *ptr) == old) - *ptr = new; - spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags); - - return prev; -} +CMPXCHG(u32) +CMPXCHG(u64) EXPORT_SYMBOL(__cmpxchg_u32); - -u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new) -{ - unsigned long flags; - u64 prev; - - spin_lock_irqsave(ATOMIC_HASH(ptr), flags); - if ((prev = *ptr) == old) - *ptr = new; - spin_unlock_irqrestore(ATOMIC_HASH(ptr), flags); - - return prev; -} EXPORT_SYMBOL(__cmpxchg_u64); unsigned long __xchg_u32(volatile u32 *ptr, u32 new) From dbc93fdcdc0d4df7abad10aac14326a4a9975997 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 22:17:49 -0400 Subject: [PATCH 338/969] sparc32: add __cmpxchg_u{8,16}() and teach __cmpxchg() to handle those sizes trivial now Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/sparc/include/asm/cmpxchg_32.h | 16 +++++++--------- arch/sparc/lib/atomic32.c | 4 ++++ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/sparc/include/asm/cmpxchg_32.h b/arch/sparc/include/asm/cmpxchg_32.h index 05d5f86a56dc..8c1a3ca34eeb 100644 --- a/arch/sparc/include/asm/cmpxchg_32.h +++ b/arch/sparc/include/asm/cmpxchg_32.h @@ -38,21 +38,19 @@ static __always_inline unsigned long __arch_xchg(unsigned long x, __volatile__ v /* bug catcher for when unsupported size is used - won't link */ void __cmpxchg_called_with_bad_pointer(void); -/* we only need to support cmpxchg of a u32 on sparc */ +u8 __cmpxchg_u8(volatile u8 *m, u8 old, u8 new_); +u16 __cmpxchg_u16(volatile u16 *m, u16 old, u16 new_); u32 __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_); /* don't worry...optimizer will get rid of most of this */ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) { - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new_); - default: - __cmpxchg_called_with_bad_pointer(); - break; - } - return old; + return + size == 1 ? __cmpxchg_u8(ptr, old, new_) : + size == 2 ? __cmpxchg_u16(ptr, old, new_) : + size == 4 ? __cmpxchg_u32(ptr, old, new_) : + (__cmpxchg_called_with_bad_pointer(), old); } #define arch_cmpxchg(ptr, o, n) \ diff --git a/arch/sparc/lib/atomic32.c b/arch/sparc/lib/atomic32.c index 0d215a772428..8ae880ebf07a 100644 --- a/arch/sparc/lib/atomic32.c +++ b/arch/sparc/lib/atomic32.c @@ -173,8 +173,12 @@ EXPORT_SYMBOL(sp32___change_bit); return prev; \ } +CMPXCHG(u8) +CMPXCHG(u16) CMPXCHG(u32) CMPXCHG(u64) +EXPORT_SYMBOL(__cmpxchg_u8); +EXPORT_SYMBOL(__cmpxchg_u16); EXPORT_SYMBOL(__cmpxchg_u32); EXPORT_SYMBOL(__cmpxchg_u64); From 29b8e53c1274f0ffda915ac6c0e5c59d14ee208e Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 22:22:50 -0400 Subject: [PATCH 339/969] parisc: __cmpxchg_u32(): lift conversion into the callers __cmpxchg_u32() return value is unsigned int explicitly cast to unsigned long. Both callers are returns from functions that return unsigned long; might as well have __cmpxchg_u32() return that unsigned int (aka u32) and let the callers convert implicitly. Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/parisc/include/asm/cmpxchg.h | 3 +-- arch/parisc/lib/bitops.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/parisc/include/asm/cmpxchg.h b/arch/parisc/include/asm/cmpxchg.h index c1d776bb16b4..0924ebc576d2 100644 --- a/arch/parisc/include/asm/cmpxchg.h +++ b/arch/parisc/include/asm/cmpxchg.h @@ -57,8 +57,7 @@ __arch_xchg(unsigned long x, volatile void *ptr, int size) extern void __cmpxchg_called_with_bad_pointer(void); /* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */ -extern unsigned long __cmpxchg_u32(volatile unsigned int *m, unsigned int old, - unsigned int new_); +extern u32 __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_); extern u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new_); extern u8 __cmpxchg_u8(volatile u8 *ptr, u8 old, u8 new_); diff --git a/arch/parisc/lib/bitops.c b/arch/parisc/lib/bitops.c index 36a314199074..ae2231d92198 100644 --- a/arch/parisc/lib/bitops.c +++ b/arch/parisc/lib/bitops.c @@ -68,16 +68,16 @@ u64 notrace __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new) return prev; } -unsigned long notrace __cmpxchg_u32(volatile unsigned int *ptr, unsigned int old, unsigned int new) +u32 notrace __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) { unsigned long flags; - unsigned int prev; + u32 prev; _atomic_spin_lock_irqsave(ptr, flags); if ((prev = *ptr) == old) *ptr = new; _atomic_spin_unlock_irqrestore(ptr, flags); - return (unsigned long)prev; + return prev; } u8 notrace __cmpxchg_u8(volatile u8 *ptr, u8 old, u8 new) From 7e00072915b3eb4739c57e716031f40de05e7a64 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 22:29:44 -0400 Subject: [PATCH 340/969] parisc: unify implementations of __cmpxchg_u{8,32,64} identical except for type name involved Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/parisc/lib/bitops.c | 49 ++++++++++++---------------------------- 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/arch/parisc/lib/bitops.c b/arch/parisc/lib/bitops.c index ae2231d92198..cae30a3eb6d9 100644 --- a/arch/parisc/lib/bitops.c +++ b/arch/parisc/lib/bitops.c @@ -56,38 +56,19 @@ unsigned long notrace __xchg8(char x, volatile char *ptr) } -u64 notrace __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new) -{ - unsigned long flags; - u64 prev; +#define CMPXCHG(T) \ + T notrace __cmpxchg_##T(volatile T *ptr, T old, T new) \ + { \ + unsigned long flags; \ + T prev; \ + \ + _atomic_spin_lock_irqsave(ptr, flags); \ + if ((prev = *ptr) == old) \ + *ptr = new; \ + _atomic_spin_unlock_irqrestore(ptr, flags); \ + return prev; \ + } - _atomic_spin_lock_irqsave(ptr, flags); - if ((prev = *ptr) == old) - *ptr = new; - _atomic_spin_unlock_irqrestore(ptr, flags); - return prev; -} - -u32 notrace __cmpxchg_u32(volatile u32 *ptr, u32 old, u32 new) -{ - unsigned long flags; - u32 prev; - - _atomic_spin_lock_irqsave(ptr, flags); - if ((prev = *ptr) == old) - *ptr = new; - _atomic_spin_unlock_irqrestore(ptr, flags); - return prev; -} - -u8 notrace __cmpxchg_u8(volatile u8 *ptr, u8 old, u8 new) -{ - unsigned long flags; - u8 prev; - - _atomic_spin_lock_irqsave(ptr, flags); - if ((prev = *ptr) == old) - *ptr = new; - _atomic_spin_unlock_irqrestore(ptr, flags); - return prev; -} +CMPXCHG(u64) +CMPXCHG(u32) +CMPXCHG(u8) From c57e5dccb06decf3cb6c272ab138c033727149b5 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 22:35:54 -0400 Subject: [PATCH 341/969] parisc: add missing export of __cmpxchg_u8() __cmpxchg_u8() had been added (initially) for the sake of drivers/phy/ti/phy-tusb1210.c; the thing is, that drivers is modular, so we need an export Fixes: b344d6a83d01 "parisc: add support for cmpxchg on u8 pointers" Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/parisc/kernel/parisc_ksyms.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/parisc/kernel/parisc_ksyms.c b/arch/parisc/kernel/parisc_ksyms.c index 6f0c92e8149d..dcf61cbd3147 100644 --- a/arch/parisc/kernel/parisc_ksyms.c +++ b/arch/parisc/kernel/parisc_ksyms.c @@ -22,6 +22,7 @@ EXPORT_SYMBOL(memset); #include EXPORT_SYMBOL(__xchg8); EXPORT_SYMBOL(__xchg32); +EXPORT_SYMBOL(__cmpxchg_u8); EXPORT_SYMBOL(__cmpxchg_u32); EXPORT_SYMBOL(__cmpxchg_u64); #ifdef CONFIG_SMP From d428032b3524e8fc75cf0bcc86b409df8ddf532b Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 1 Apr 2024 23:13:17 -0400 Subject: [PATCH 342/969] parisc: add u16 support to cmpxchg() Add (and export) __cmpxchg_u16(), teach __cmpxchg() to use it. And get rid of manual truncation down to u8, etc. in there - the only reason for those is to avoid bogus warnings about constant truncation from sparse, and those are easy to avoid by turning that switch into conditional expression. Signed-off-by: Al Viro Signed-off-by: Paul E. McKenney --- arch/parisc/include/asm/cmpxchg.h | 19 +++++++++---------- arch/parisc/kernel/parisc_ksyms.c | 1 + arch/parisc/lib/bitops.c | 1 + 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/parisc/include/asm/cmpxchg.h b/arch/parisc/include/asm/cmpxchg.h index 0924ebc576d2..bf0a0f1189eb 100644 --- a/arch/parisc/include/asm/cmpxchg.h +++ b/arch/parisc/include/asm/cmpxchg.h @@ -56,25 +56,24 @@ __arch_xchg(unsigned long x, volatile void *ptr, int size) /* bug catcher for when unsupported size is used - won't link */ extern void __cmpxchg_called_with_bad_pointer(void); -/* __cmpxchg_u32/u64 defined in arch/parisc/lib/bitops.c */ +/* __cmpxchg_u... defined in arch/parisc/lib/bitops.c */ +extern u8 __cmpxchg_u8(volatile u8 *ptr, u8 old, u8 new_); +extern u16 __cmpxchg_u16(volatile u16 *ptr, u16 old, u16 new_); extern u32 __cmpxchg_u32(volatile u32 *m, u32 old, u32 new_); extern u64 __cmpxchg_u64(volatile u64 *ptr, u64 old, u64 new_); -extern u8 __cmpxchg_u8(volatile u8 *ptr, u8 old, u8 new_); /* don't worry...optimizer will get rid of most of this */ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new_, int size) { - switch (size) { + return #ifdef CONFIG_64BIT - case 8: return __cmpxchg_u64((u64 *)ptr, old, new_); + size == 8 ? __cmpxchg_u64(ptr, old, new_) : #endif - case 4: return __cmpxchg_u32((unsigned int *)ptr, - (unsigned int)old, (unsigned int)new_); - case 1: return __cmpxchg_u8((u8 *)ptr, old & 0xff, new_ & 0xff); - } - __cmpxchg_called_with_bad_pointer(); - return old; + size == 4 ? __cmpxchg_u32(ptr, old, new_) : + size == 2 ? __cmpxchg_u16(ptr, old, new_) : + size == 1 ? __cmpxchg_u8(ptr, old, new_) : + (__cmpxchg_called_with_bad_pointer(), old); } #define arch_cmpxchg(ptr, o, n) \ diff --git a/arch/parisc/kernel/parisc_ksyms.c b/arch/parisc/kernel/parisc_ksyms.c index dcf61cbd3147..c1587aa35beb 100644 --- a/arch/parisc/kernel/parisc_ksyms.c +++ b/arch/parisc/kernel/parisc_ksyms.c @@ -23,6 +23,7 @@ EXPORT_SYMBOL(memset); EXPORT_SYMBOL(__xchg8); EXPORT_SYMBOL(__xchg32); EXPORT_SYMBOL(__cmpxchg_u8); +EXPORT_SYMBOL(__cmpxchg_u16); EXPORT_SYMBOL(__cmpxchg_u32); EXPORT_SYMBOL(__cmpxchg_u64); #ifdef CONFIG_SMP diff --git a/arch/parisc/lib/bitops.c b/arch/parisc/lib/bitops.c index cae30a3eb6d9..9df810050642 100644 --- a/arch/parisc/lib/bitops.c +++ b/arch/parisc/lib/bitops.c @@ -71,4 +71,5 @@ unsigned long notrace __xchg8(char x, volatile char *ptr) CMPXCHG(u64) CMPXCHG(u32) +CMPXCHG(u16) CMPXCHG(u8) From a88d970c8bb55dc20f319ce3e33c7ce0e9647480 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Sun, 17 Mar 2024 14:44:38 -0700 Subject: [PATCH 343/969] lib: Add one-byte emulation function Architectures are required to provide four-byte cmpxchg() and 64-bit architectures are additionally required to provide eight-byte cmpxchg(). However, there are cases where one-byte cmpxchg() would be extremely useful. Therefore, provide cmpxchg_emu_u8() that emulates one-byte cmpxchg() in terms of four-byte cmpxchg(). Note that this emulations is fully ordered, and can (for example) cause one-byte cmpxchg_relaxed() to incur the overhead of full ordering. If this causes problems for a given architecture, that architecture is free to provide its own lighter-weight primitives. [ paulmck: Apply Marco Elver feedback. ] [ paulmck: Apply kernel test robot feedback. ] [ paulmck: Drop two-byte support per Arnd Bergmann feedback. ] Link: https://lore.kernel.org/all/0733eb10-5e7a-4450-9b8a-527b97c842ff@paulmck-laptop/ Signed-off-by: Paul E. McKenney Acked-by: Marco Elver Cc: Andrew Morton Cc: Thomas Gleixner Cc: "Peter Zijlstra (Intel)" Cc: Douglas Anderson Cc: Petr Mladek Cc: Arnd Bergmann Cc: --- arch/Kconfig | 3 +++ include/linux/cmpxchg-emu.h | 15 +++++++++++++ lib/Makefile | 1 + lib/cmpxchg-emu.c | 45 +++++++++++++++++++++++++++++++++++++ 4 files changed, 64 insertions(+) create mode 100644 include/linux/cmpxchg-emu.h create mode 100644 lib/cmpxchg-emu.c diff --git a/arch/Kconfig b/arch/Kconfig index 9f066785bb71..284663392eef 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1609,4 +1609,7 @@ config CC_HAS_SANE_FUNCTION_ALIGNMENT # strict alignment always, even with -falign-functions. def_bool CC_HAS_MIN_FUNCTION_ALIGNMENT || CC_IS_CLANG +config ARCH_NEED_CMPXCHG_1_EMU + bool + endmenu diff --git a/include/linux/cmpxchg-emu.h b/include/linux/cmpxchg-emu.h new file mode 100644 index 000000000000..998deec67740 --- /dev/null +++ b/include/linux/cmpxchg-emu.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Emulated 1-byte and 2-byte cmpxchg operations for architectures + * lacking direct support for these sizes. These are implemented in terms + * of 4-byte cmpxchg operations. + * + * Copyright (C) 2024 Paul E. McKenney. + */ + +#ifndef __LINUX_CMPXCHG_EMU_H +#define __LINUX_CMPXCHG_EMU_H + +uintptr_t cmpxchg_emu_u8(volatile u8 *p, uintptr_t old, uintptr_t new); + +#endif /* __LINUX_CMPXCHG_EMU_H */ diff --git a/lib/Makefile b/lib/Makefile index ffc6b2341b45..cc3d52fdb477 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -236,6 +236,7 @@ obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o lib-$(CONFIG_GENERIC_BUG) += bug.o obj-$(CONFIG_HAVE_ARCH_TRACEHOOK) += syscall.o +obj-$(CONFIG_ARCH_NEED_CMPXCHG_1_EMU) += cmpxchg-emu.o obj-$(CONFIG_DYNAMIC_DEBUG_CORE) += dynamic_debug.o #ensure exported functions have prototypes diff --git a/lib/cmpxchg-emu.c b/lib/cmpxchg-emu.c new file mode 100644 index 000000000000..27f6f97cb60d --- /dev/null +++ b/lib/cmpxchg-emu.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Emulated 1-byte cmpxchg operation for architectures lacking direct + * support for this size. This is implemented in terms of 4-byte cmpxchg + * operations. + * + * Copyright (C) 2024 Paul E. McKenney. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +union u8_32 { + u8 b[4]; + u32 w; +}; + +/* Emulate one-byte cmpxchg() in terms of 4-byte cmpxchg. */ +uintptr_t cmpxchg_emu_u8(volatile u8 *p, uintptr_t old, uintptr_t new) +{ + u32 *p32 = (u32 *)(((uintptr_t)p) & ~0x3); + int i = ((uintptr_t)p) & 0x3; + union u8_32 old32; + union u8_32 new32; + u32 ret; + + ret = READ_ONCE(*p32); + do { + old32.w = ret; + if (old32.b[i] != old) + return old32.b[i]; + new32.w = old32.w; + new32.b[i] = new; + instrument_atomic_read_write(p, 1); + ret = data_race(cmpxchg(p32, old32.w, new32.w)); // Overridden above. + } while (ret != old32.w); + return old; +} +EXPORT_SYMBOL_GPL(cmpxchg_emu_u8); From 4bad3598a8a685ea7a0953cdb9cc2e2ac69ae26b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 344/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 06466d36caa9..10f452152b0c 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -285,13 +285,21 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_core_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x012c>; + /* CM_CLKSEL_DPLL_CORE */ + clock@12c { + compatible = "ti,clksel"; + reg = <0x12c>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_core_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_core_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + #clock-cells = <0>; + }; }; dpll_core_ck: clock@120 { From de36994d7639024cde1f7d1dd6d9d69e7243572f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 345/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 10f452152b0c..e4f15453adfa 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -376,13 +376,21 @@ clock-div = <1>; }; - dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_dsp_byp_mux"; - clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0240>; + /* CM_CLKSEL_DPLL_DSP */ + clock@240 { + compatible = "ti,clksel"; + reg = <0x240>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_dsp_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_dsp_byp_mux"; + clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_dsp_ck: clock@234 { From a0a621533fe796d5a92ece5573663cb25bec470c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 346/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index e4f15453adfa..88c14c172b0f 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -426,13 +426,21 @@ clock-div = <1>; }; - dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_iva_byp_mux"; - clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x01ac>; + /* CM_CLKSEL_DPLL_IVA */ + clock@1ac { + compatible = "ti,clksel"; + reg = <0x1ac>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_iva_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_iva_byp_mux"; + clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_iva_ck: clock@1a0 { From d3c9a44103e98f2722c8b8c48b604995f5063034 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 347/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 88c14c172b0f..a7667d954ec5 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -476,13 +476,21 @@ clock-div = <1>; }; - dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_gpu_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02e4>; + /* CM_CLKSEL_DPLL_GPU */ + clock@2e4 { + compatible = "ti,clksel"; + reg = <0x2e4>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_gpu_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_gpu_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + #clock-cells = <0>; + }; }; dpll_gpu_ck: clock@2d8 { From 6c95cd7a40c460373a42e6f617f3e4d756f5acbd Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 348/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index a7667d954ec5..7fa9a7bcb0f2 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -538,13 +538,21 @@ clock-div = <1>; }; - dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_ddr_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x021c>; + /* CM_CLKSEL_DPLL_DDR */ + clock@21c { + compatible = "ti,clksel"; + reg = <0x21c>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_ddr_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_ddr_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + #clock-cells = <0>; + }; }; dpll_ddr_ck: clock@210 { From 99a27be0caac26013e23ed64012cb7098f9cc401 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 349/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 7fa9a7bcb0f2..0385535c8bc7 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -575,13 +575,21 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_gmac_byp_mux"; - clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; - ti,bit-shift = <23>; - reg = <0x02b4>; + /* CM_CLKSEL_DPLL_GMAC */ + clock@2b4 { + compatible = "ti,clksel"; + reg = <0x2b4>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_gmac_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_gmac_byp_mux"; + clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; + #clock-cells = <0>; + }; }; dpll_gmac_ck: clock@2a8 { From 8d0cd4fe16eca187017d1a192095d75b4fc21ad2 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 350/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 0385535c8bc7..e021632a18ef 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -666,13 +666,21 @@ clock-div = <1>; }; - dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_eve_byp_mux"; - clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x0290>; + /* CM_CLKSEL_DPLL_EVE */ + clock@290 { + compatible = "ti,clksel"; + reg = <0x290>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_eve_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_eve_byp_mux"; + clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_eve_ck: clock@284 { From a65ae2810439472543f18cacf35d5c1241a05a22 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 351/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 26 +++++++++++++------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index e021632a18ef..2c037a8ce94e 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -894,15 +894,23 @@ clock-div = <1>; }; - l3_iclk_div: clock-l3-iclk-div-4@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "l3_iclk_div"; - ti,max-div = <2>; - ti,bit-shift = <4>; - reg = <0x0100>; - clocks = <&dpll_core_h12x2_ck>; - ti,index-power-of-two; + /* CM_CLKSEL_CORE */ + clock@100 { + compatible = "ti,clksel"; + reg = <0x100>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + l3_iclk_div: clock@4 { + reg = <4>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_iclk_div"; + ti,max-div = <2>; + clocks = <&dpll_core_h12x2_ck>; + ti,index-power-of-two; + #clock-cells = <0>; + }; }; l4_root_clk_div: clock-l4-root-clk-div { From 151cd9452b77bb04adc6209b763f37a6f99ea6a5 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 352/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 21 ++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 2c037a8ce94e..632878479798 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -975,12 +975,21 @@ ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "abe_dpll_sys_clk_mux"; - clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x0118>; + /* CM_CLKSEL_ABE_PLL_SYS */ + clock@118 { + compatible = "ti,clksel"; + reg = <0x118>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + abe_dpll_sys_clk_mux: clock@0 { + reg = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "abe_dpll_sys_clk_mux"; + clocks = <&sys_clkin1>, <&sys_clkin2>; + #clock-cells = <0>; + }; }; abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 { From 2fc35aa0923b899ac2f873d6ae57b99d035a793c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 353/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 632878479798..3c8de5ddb0cb 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -1399,13 +1399,21 @@ clock-div = <1>; }; - dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_per_byp_mux"; - clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; + /* CM_CLKSEL_DPLL_PER */ + clock@14c { + compatible = "ti,clksel"; + reg = <0x14c>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_per_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; + clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_per_ck: clock@140 { From bb5f690d5ebc6ea911dac0c327744f2af1ff674d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 354/969] ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 47 +++++++++++++------- 1 file changed, 32 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 3c8de5ddb0cb..04f08b8c64d2 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -1091,14 +1091,23 @@ ti,index-power-of-two; }; - dsp_gclk_div: clock-dsp-gclk-div@18c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clock-output-names = "dsp_gclk_div"; - clocks = <&dpll_dsp_m2_ck>; - ti,max-div = <64>; - reg = <0x018c>; - ti,index-power-of-two; + /* CM_CLKSEL_DPLL_USB */ + clock@18c { + compatible = "ti,clksel"; + reg = <0x18c>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dsp_gclk_div: clock@0 { + reg = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dsp_gclk_div"; + clocks = <&dpll_dsp_m2_ck>; + ti,max-div = <64>; + ti,index-power-of-two; + #clock-cells = <0>; + }; }; gpu_dclk: clock-gpu-dclk@1a0 { @@ -1445,13 +1454,21 @@ clock-div = <1>; }; - dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_usb_byp_mux"; - clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x018c>; + /* CM_CLKSEL_DPLL_USB */ + clock@18c { + compatible = "ti,clksel"; + reg = <0x18c>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_usb_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_usb_byp_mux"; + clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_usb_ck: clock@180 { From 32f4c19f6a52bdfa6ec73a067b6e7382b8d6653e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: [PATCH 355/969] ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0 On dra76x, most dpll_gmac output clksel clocks are in registers from CM_CLKSEL_DPLL_GMAC to CM_DIV_H13_DPLL_GMAC. In addition to that, there are there more clocks in the CTRL_CORE_SMA_SW_0 register. Let's group the CTRL_CORE_SMA_SW_0 clocks using the clksel binding to reduce make W=1 dtbs unique_unit_address warnings, and stop using the custom the ti,bit-shift property in favor of the standard reg property. Let's also add a comment for the CTRL_CORE_SMA_SW_0 clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra76x.dtsi | 63 +++++++++++++++------------ 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi index 1045eb24aa0d..50a02c393ea2 100644 --- a/arch/arm/boot/dts/ti/omap/dra76x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra76x.dtsi @@ -84,35 +84,44 @@ }; &scm_conf_clocks { - dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck@3fc { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_x2_ck>; - ti,max-div = <63>; - reg = <0x03fc>; - ti,bit-shift = <20>; - ti,latch-bit = <26>; - assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; - assigned-clock-rates = <80000000>; - }; - - dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck@3fc { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; + /* CTRL_CORE_SMA_SW_0 */ + clock@3fc { + compatible = "ti,clksel"; reg = <0x3fc>; - ti,bit-shift = <29>; - ti,latch-bit = <26>; - assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; - assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; - }; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; - mcan_clk: mcan_clk@3fc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; - ti,bit-shift = <27>; - reg = <0x3fc>; + dpll_gmac_h14x2_ctrl_ck: clock@20 { + reg = <20>; + clock-output-names = "dpll_gmac_h14x2_ctrl_ck"; + compatible = "ti,divider-clock"; + clocks = <&dpll_gmac_x2_ck>; + ti,max-div = <63>; + ti,latch-bit = <26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>; + assigned-clock-rates = <80000000>; + #clock-cells = <0>; + }; + + mcan_clk: clock@27 { + reg = <27>; + clock-output-names = "mcan_clk"; + compatible = "ti,gate-clock"; + clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + #clock-cells = <0>; + }; + + dpll_gmac_h14x2_ctrl_mux_ck: clock@29 { + reg = <29>; + clock-output-names = "dpll_gmac_h14x2_ctrl_mux_ck"; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>; + ti,latch-bit = <26>; + assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>; + assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>; + #clock-cells = <0>; + }; }; }; From 71413bcb66e018e54afec47a9ce1199130d6fa38 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 8 Feb 2024 11:51:46 +0100 Subject: [PATCH 356/969] ARM: dts: ti: omap: minor whitespace cleanup The DTS code coding style expects exactly one space before '{' character. Acked-by: Tony Lindgren Link: https://lore.kernel.org/r/20240208105146.128645-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/ti/omap/am33xx.dtsi | 8 ++++---- arch/arm/boot/dts/ti/omap/am4372.dtsi | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi index 989d5a6edeed..0614ffdc1578 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -80,7 +80,7 @@ * because the can not be enabled simultaneously on a * single SoC. */ - opp-50-300000000{ + opp-50-300000000 { /* OPP50 */ opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; @@ -88,7 +88,7 @@ opp-suspend; }; - opp-100-275000000{ + opp-100-275000000 { /* OPP100-1 */ opp-hz = /bits/ 64 <275000000>; opp-microvolt = <1100000 1078000 1122000>; @@ -96,7 +96,7 @@ opp-suspend; }; - opp-100-300000000{ + opp-100-300000000 { /* OPP100-2 */ opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000 1078000 1122000>; @@ -104,7 +104,7 @@ opp-suspend; }; - opp-100-500000000{ + opp-100-500000000 { /* OPP100-3 */ opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1100000 1078000 1122000>; diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi index 5fd1b380ece6..0a1df30f2818 100644 --- a/arch/arm/boot/dts/ti/omap/am4372.dtsi +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -92,7 +92,7 @@ opp-supported-hw = <0xFF 0x08>; }; - opp-800000000{ + opp-800000000 { /* OPP Turbo */ opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; From 6bc8e01c7284ea1f56c6506f38c2ba9474db497a Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 09:37:26 -0500 Subject: [PATCH 357/969] arm64: dts: rockchip: Add additional properties for WiFi on Anbernic rgxx3 Add additional properties for the SDMMC2 node. Based on user feedback these help correct some issues with probing the WiFi hardware. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240325143729.83852-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi index 18b8c2e7befa..c8fdb1b817f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -623,9 +623,12 @@ cap-sdio-irq; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; non-removable; pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; pinctrl-names = "default"; + sd-uhs-sdr50; vmmc-supply = <&vcc_wifi>; vqmmc-supply = <&vcca1v8_pmu>; status = "okay"; From 8db673210ae24ed44acf15642f4abd6d4b4cae52 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 09:37:27 -0500 Subject: [PATCH 358/969] arm64: dts: rockchip: Add optional node for chasis-type on Anbernic rgxx3 Add optional node for chasis-type defining this device as a handset. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240325143729.83852-3-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi index c8fdb1b817f5..233eade30f21 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -10,6 +10,8 @@ #include "rk3566.dtsi" / { + chassis-type = "handset"; + chosen: chosen { stdout-path = "serial2:1500000n8"; }; From b41b83b701056421bdc494c8e1488d38f2990c3d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 09:37:29 -0500 Subject: [PATCH 359/969] arm64: dts: rockchip: Correct model name for Anbernic RGxx3 Devices Some Anbernic model names begin with the company "Anbernic" and others simply list the model number. Make this consistent across the device lineup by including the manufacturer in the model name. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240325143729.83852-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts index 8aa93c646bec..a73cf30801ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts @@ -8,7 +8,7 @@ #include "rk3566-anbernic-rg353x.dtsi" / { - model = "RG353P"; + model = "Anbernic RG353P"; compatible = "anbernic,rg353p", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts index b211973e36c2..ca5284e4807d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts @@ -8,7 +8,7 @@ #include "rk3566-anbernic-rg353x.dtsi" / { - model = "RG353PS"; + model = "Anbernic RG353PS"; compatible = "anbernic,rg353ps", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts index f49ce29ba597..e9954a33e8cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts @@ -8,7 +8,7 @@ #include "rk3566-anbernic-rg353x.dtsi" / { - model = "RG353V"; + model = "Anbernic RG353V"; compatible = "anbernic,rg353v", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts index a7dc462fe21f..90da43855d1c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts @@ -8,7 +8,7 @@ #include "rk3566-anbernic-rg353x.dtsi" / { - model = "RG353VS"; + model = "Anbernic RG353VS"; compatible = "anbernic,rg353vs", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts index 94e6dd61a2db..74cf313e0635 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts @@ -8,7 +8,7 @@ #include "rk3566-anbernic-rgxx3.dtsi" / { - model = "RG503"; + model = "Anbernic RG503"; compatible = "anbernic,rg503", "rockchip,rk3566"; aliases { From 9d3d2be86c7d4b1bc16b65a06ba06886913de7e8 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 12:51:30 -0500 Subject: [PATCH 360/969] arm64: dts: rockchip: Add chasis-type for Powkiddy rk3566 devices Add the optional node of chasis-type for Powkiddy RK3566 based devices. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240325175133.19393-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi | 2 ++ arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi index 3ab751a01cb2..bd332714a023 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dtsi @@ -10,6 +10,8 @@ #include "rk3566.dtsi" / { + chassis-type = "handset"; + aliases { mmc1 = &sdmmc0; mmc2 = &sdmmc1; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts index 4786b19fd017..5a648db41f35 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-x55.dts @@ -11,6 +11,7 @@ / { model = "Powkiddy x55"; + chassis-type = "handset"; compatible = "powkiddy,x55", "rockchip,rk3566"; aliases { From 1b76d86dbc5faf907d74343e1b15daa84ab8322c Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 12:51:32 -0500 Subject: [PATCH 361/969] arm64: dts: rockchip: Correct model name for Powkiddy RK3566 Devices Some Powkiddy model names begin with the company "Powkiddy" and others simply list the model number. Make this consistent across the device lineup by including the manufacturer in the model name. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240325175133.19393-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts index 1f567a14ac84..952b1b285f3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts @@ -8,7 +8,7 @@ #include "rk3566-powkiddy-rk2023.dtsi" / { - model = "RGB30"; + model = "Powkiddy RGB30"; compatible = "powkiddy,rgb30", "rockchip,rk3566"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts index bc9933d9e262..72890f747ee3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rk2023.dts @@ -8,7 +8,7 @@ #include "rk3566-powkiddy-rk2023.dtsi" / { - model = "RK2023"; + model = "Powkiddy RK2023"; compatible = "powkiddy,rk2023", "rockchip,rk3566"; }; From c1bc09960d05cfbfb94cfdfb66b4733e3ddf1638 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 08:49:58 -0500 Subject: [PATCH 362/969] dt-bindings: arm: rockchip: Add GameForce Chi The GameForce Chi is a handheld gaming device from GameForce powered by the Rockchip RK3326 SoC. Signed-off-by: Chris Morgan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240325134959.11807-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 6d4144a921f3..4bd033adeee4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -243,6 +243,11 @@ properties: - const: friendlyarm,nanopc-t6 - const: rockchip,rk3588 + - description: GameForce Chi + items: + - const: gameforce,chi + - const: rockchip,rk3326 + - description: GeekBuying GeekBox items: - const: geekbuying,geekbox From ad59da1ab997e81061ec980300fb7ce2d5e4bc5d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Mon, 25 Mar 2024 08:49:59 -0500 Subject: [PATCH 363/969] arm64: dts: rockchip: Add GameForce Chi Add support for the GameForce Chi, which is a handheld gaming console from GameForce with a Rockchip RK3326 SoC. The device has a 640x480 3.5" dual-lane DSI display, one analog joystick connected to the SoC SARADC controller and a second analog joystick connected to an unknown UART based ADC, a single SD card slot, a single USB-C port for charging, and onboard RTL8723BS WiFi/Bluetooth combo, multiple face buttons, and an array of R/G/B LEDs used for key backlighting. The vendor was unable to provide details on the unknown UART based ADC which I have documented via a comment in the device-tree, and the vendor also does not have available Bluetooth firmware (the BT was not previously working on the vendor's OS, this has also been noted in a device-tree comment). Aside from the right analog ADC joystick and bluetooth all hardware has been tested and is working as expected. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240325134959.11807-6-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3326-gameforce-chi.dts | 809 ++++++++++++++++++ 2 files changed, 810 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index df28f1ba3a1a..7da198be8787 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351v.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-gameforce-chi.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts b/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts new file mode 100644 index 000000000000..579261b3a474 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326-gameforce-chi.dts @@ -0,0 +1,809 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Chris Morgan + */ + +/dts-v1/; +#include +#include +#include +#include +#include "rk3326.dtsi" + +/ { + model = "GameForce Chi"; + compatible = "gameforce,chi", "rockchip,rk3326"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + adc_joystick: adc-joystick { + compatible = "adc-joystick"; + io-channels = <&saradc 0>, + <&saradc 1>; + poll-interval = <100>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <850 175>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <800 190>; + linux,code = ; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <60>; + + button-1 { + label = "HAPPY1"; + linux,code = ; + press-threshold-microvolt = <15000>; + }; + + button-2 { + label = "HAPPY2"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_bl>; + pwms = <&pwm1 0 25000 0>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <180000>; + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>, + <3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>, + <3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>, + <3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>, + <3718000 20>, <3697000 15>, <3685000 10>, <3625000 5>, + <3400000 0>; + voltage-max-design-microvolt = <4250000>; + voltage-min-design-microvolt = <3400000>; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + red_led: led-0 { + color = ; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + green_led: led-1 { + color = ; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + + blue_led: led-2 { + color = ; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + }; + + white_led: led-3 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + chg_led: led-4 { + color = ; + function = LED_FUNCTION_CHARGING; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + }; + + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&btn_pins_ctrl>; + pinctrl-names = "default"; + + button-a { + gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + label = "EAST"; + linux,code = ; + }; + + button-b { + gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + label = "SOUTH"; + linux,code = ; + }; + + button-down { + gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = ; + }; + + button-home { + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "HOME"; + linux,code = ; + }; + + button-l1 { + gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TL"; + linux,code = ; + }; + + button-l2 { + gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; + label = "TL2"; + linux,code = ; + }; + + button-left { + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + + button-r1 { + gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = ; + }; + + button-r2 { + gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = ; + }; + + button-right { + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + + button-select { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + label = "SELECT"; + linux,code = ; + }; + + button-start { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + label = "START"; + linux,code = ; + }; + + button-up { + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = ; + }; + + button-x { + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + label = "NORTH"; + linux,code = ; + }; + + button-y { + gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + label = "WEST"; + linux,code = ; + }; + }; + + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_KBD_BACKLIGHT; + leds = <&red_led>, <&green_led>, <&blue_led>; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + }; + + vibrator_left: pwm-vibrator-l { + compatible = "pwm-vibrator"; + pwm-names = "enable"; + pwms = <&pwm4 0 25000 0>; + }; + + vibrator_right: pwm-vibrator-r { + compatible = "pwm-vibrator"; + pwm-names = "enable"; + pwms = <&pwm5 0 25000 0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + vccsys: vccsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + internal_display: panel@0 { + reg = <0>; + compatible = "gameforce,chi-panel"; + backlight = <&backlight>; + iovcc-supply = <&vcc_lcd>; + vcc-supply = <&vcc_lcd>; + reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <16>; + i2c-scl-rising-time-ns = <280>; + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + #clock-cells = <1>; + clock-names = "mclk"; + clock-output-names = "rk808-clkout1", "xin32k"; + clocks = <&cru SCLK_I2S1_OUT>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <950000>; + regulator-name = "vdd_logic"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <950000>; + regulator-name = "vdd_arm"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "vdd_1v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v0_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_bl"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc_lcd"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc_wifi: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_wifi"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + dcdc_boost: BOOST { + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "dcdc_boost"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + vccio1-supply = <&vcc_3v0_pmu>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; + vccio6-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + bluetooth-pins { + bt_reset: bt-reset { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-btns { + btn_pins_ctrl: btn-pins-ctrl { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + led_pins: led-pins { + rockchip,pins = + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + speaker { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_1v8>; + pmuio2-supply = <&vcc_3v0_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; + pinctrl-names = "default"; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +/* + * The right ADC joystick exists connected to an unknown ADC + * controller which can be communicated with via uart0. This ADC device + * is an 8-pin SOIC with no markings located right next to the left ADC + * joystick ribbon cable. The pinout for this ADC controller appears to + * be pin 1 - VCC (2.8v), pin 2 - 1.8v (clk maybe?), pin 3 - GPIO 10, + * pin 4 - unknown, pin 5 - unknown, pin 6 - analog in, pin 7 - analog in, + * pin 8 - ground. There is currently a userspace UART driver for this + * device but it only works with the BSP joystick driver. + */ +&uart0 { + status = "okay"; +}; + +/* + * Bluetooth was not working on BSP and is not currently working on + * mainline due to missing firmware. Bluetooth requires removal of DMA + * or else it will not probe. + */ +&uart1 { + /delete-property/ dma-names; + /delete-property/ dmas; + uart-has-rtscts; + status = "okay"; + + bluetooth: bluetooth { + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>; + pinctrl-names = "default"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m1_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; From 925273ba9e71184a6dcde0f902b4245ed64885d1 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:17 +0300 Subject: [PATCH 364/969] arm64: dts: rockchip: Add cpu regulators and vcc5v0_sys to Khadas Edge 2 This commit adds 5V fixed power regulator and CPU regulators to Khadas Edge 2. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/5a7bd2cd8703e51382abfc11242de59d45286477.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index f53e993c785e..1d1ce70a0f3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -17,6 +17,87 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; }; &sdhci { From 3b5d2327cb749017322ce09f7107cdc82f1a92fa Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:18 +0300 Subject: [PATCH 365/969] arm64: dts: rockchip: Add PMIC to Khadas Edge 2 This commit adds PMIC to Khadas Edge 2 board. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/617faf64a68f5af560267d77fd23fc9fb23e6c88.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 332 ++++++++++++++++++ 1 file changed, 332 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 1d1ce70a0f3a..cf2e6edf3c10 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -26,6 +26,16 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; }; &cpu_b0 { @@ -110,6 +120,328 @@ status = "okay"; }; +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_log_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_vdenc_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_ddr_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; From 4a3afe9cf3711f222a9dadf50bd2e9770bb6a095 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:19 +0300 Subject: [PATCH 366/969] arm64: dts: rockchip: Add TF card to Khadas Edge 2 Add TF card support to Khadas Edge 2. The board exposes sdmmc pins via EXTIO. TF card can be used with IO module. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/6e9062feb40bbad304f2e5bb300601034e805081.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index cf2e6edf3c10..cf47ee81498c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -12,6 +12,7 @@ aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; }; chosen { @@ -36,6 +37,19 @@ regulator-max-microvolt = <1100000>; vin-supply = <&vcc5v0_sys>; }; + + vdd_3v3_sd: vdd-3v3-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sd"; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_en>; + }; }; &cpu_b0 { @@ -110,6 +124,14 @@ }; }; +&pinctrl { + vdd_sd { + vdd_sd_en: vdd-sd-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + &sdhci { bus-width = <8>; no-sdio; @@ -120,6 +142,18 @@ status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vdd_3v3_sd>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; From f786eda805aa91340e151322ccc6c0ba4a591f9f Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:20 +0300 Subject: [PATCH 367/969] arm64: dts: rockchip: USB2, USB3 Host, PCIe2 to Khadas Edge 2 Khadas Edge 2 has 1x USB2 with hub, 1x USB3 Host and 1x USB-C. This commit adds support for PCIe2, USB3 Host and USB2. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/4d22afd70e5583458f405f5170f67690584e7efa.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index cf47ee81498c..1f75ec75be22 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -19,6 +19,33 @@ stdout-path = "serial2:1500000n8"; }; + vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_vcc3v3_en>; + regulator-name = "vcc3v3_pcie_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -84,6 +111,14 @@ cpu-supply = <&vdd_cpu_lit_s0>; }; +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -130,6 +165,30 @@ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + pcie2 { + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_vcc3v3_en: pcie2-2-vcc-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_wl>; + status = "okay"; }; &sdhci { @@ -480,3 +539,41 @@ pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; From af6943f502b6db1ba3bc5199069c662218e23261 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:21 +0300 Subject: [PATCH 368/969] arm64: dts: rockchip: Add ir receiver and leds to Khadas Edge 2 Khadas Edge 2 exposes IR receiver pins as same as TF card via EXTIO. The IR receiver is connected to MCU and SoC. The board also has 2 PWM RGB leds. One is controlled by MCU and the other is controlled by SoC. This commit adds support for the led controlled by SoC using pwm-leds. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/335629f57e593e20418a4a55a1e662505640cbde.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 1f75ec75be22..8f012ce7a5c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -4,6 +4,7 @@ #include #include +#include #include "rk3588s.dtsi" / { @@ -19,6 +20,47 @@ stdout-path = "serial2:1500000n8"; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + + leds { + compatible = "pwm-leds"; + + red_led: led-0 { + label = "red_led"; + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "none"; + max-brightness = <255>; + pwms = <&pwm11 0 25000 0>; + }; + + green_led: led-1 { + label = "green_led"; + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + linux,default-trigger = "default-on"; + max-brightness = <255>; + pwms = <&pwm14 0 25000 0>; + }; + + blue_led: led-2 { + label = "blue_led"; + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "none"; + max-brightness = <255>; + pwms = <&pwm15 0 25000 0>; + }; + }; + vcc3v3_pcie_wl: vcc3v3-pcie-wl-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -181,6 +223,12 @@ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pcie2x1l2 { @@ -191,6 +239,24 @@ status = "okay"; }; +&pwm11 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm11m1_pins>; + status = "okay"; +}; + +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m1_pins>; + status = "okay"; +}; + +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m1_pins>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; From 25e31aaebed4b0e242d9a71170f8dfdf9cc8a304 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:22 +0300 Subject: [PATCH 369/969] arm64: dts: rockchip: Add saradc and adc buttons to Khadas Edge 2 and enable tsadc This commit enables tsadc, saradc and the function button on saradc line for Khadas Edge 2. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/03feaafefd0c13268ba1630251558749654a567d.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 8f012ce7a5c4..4600ed2f232b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -3,6 +3,7 @@ /dts-v1/; #include +#include #include #include #include "rk3588s.dtsi" @@ -20,6 +21,20 @@ stdout-path = "serial2:1500000n8"; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-function { + label = "Function"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; @@ -257,6 +272,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; @@ -601,6 +621,10 @@ }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; From 8711dca3b5f7a3834ae1129512f98a2367940a07 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:23 +0300 Subject: [PATCH 370/969] arm64: dts: rockchip: Add SFC to Khadas Edge 2 This commit adds SPI flash support for Khadas Edge 2. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/00942603f7e61ecb2a0067bebf6795dab3571613.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-khadas-edge2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 4600ed2f232b..1bd6cb9c6111 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -299,6 +299,20 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; From 37c09ed41925492667baa0586dc1c5de2a50ba90 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Mar 2024 19:20:28 +0000 Subject: [PATCH 371/969] RISC-V: drop SOC_MICROCHIP_POLARFIRE for ARCH_MICROCHIP SOC_MICROCHIP_POLARFIRE doesn't have any remaining in-kernel users, so time has come to remove it. Foolish auld me left the "POLARFIRE" in the new, hidden, config option when I renamed it and changed all of the users however. As HPSC has been announced, and is not a PolarFire, drop mention of that specific FPGA family from the new user-visible config option. Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 8 ++++---- arch/riscv/configs/defconfig | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a4468deef99f..3915985c83e4 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,12 +1,12 @@ menu "SoC selection" config ARCH_MICROCHIP_POLARFIRE - def_bool SOC_MICROCHIP_POLARFIRE + def_bool ARCH_MICROCHIP -config SOC_MICROCHIP_POLARFIRE - bool "Microchip PolarFire SoCs" +config ARCH_MICROCHIP + bool "Microchip SoCs" help - This enables support for Microchip PolarFire SoC platforms. + This enables support for Microchip SoC platforms. config ARCH_RENESAS bool "Renesas RISC-V SoCs" diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fc0ec2ee13bc..936015d9288e 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,7 +25,7 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=y -CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_RENESAS=y CONFIG_SOC_SIFIVE=y CONFIG_ARCH_SOPHGO=y From d2a351e637794e3511ea35ef8109768c6efd89b4 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Mar 2024 18:37:05 +0000 Subject: [PATCH 372/969] RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE All the users in the kernel are gone and generated .config files from previous LTS kernels will contain ARCH_SIFIVE. Drop SOC_SIFIVE and update the defconfig. Reviewed-by: Samuel Holland Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 3 --- arch/riscv/configs/defconfig | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 3915985c83e4..2797412a7ec9 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -14,9 +14,6 @@ config ARCH_RENESAS This enables support for the RISC-V based Renesas SoCs. config ARCH_SIFIVE - def_bool SOC_SIFIVE - -config SOC_SIFIVE bool "SiFive SoCs" select ERRATA_SIFIVE if !XIP_KERNEL help diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 936015d9288e..8f2bec476af2 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,7 +27,7 @@ CONFIG_EXPERT=y CONFIG_PROFILING=y CONFIG_ARCH_MICROCHIP=y CONFIG_ARCH_RENESAS=y -CONFIG_SOC_SIFIVE=y +CONFIG_ARCH_SIFIVE=y CONFIG_ARCH_SOPHGO=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y From 1553a1c48281243359a9529a10ddb551f3b967ab Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 5 Mar 2024 18:37:06 +0000 Subject: [PATCH 373/969] RISC-V: drop SOC_VIRT for ARCH_VIRT The ARCH_ and SOC_ versions of this symbol have persisted for quite a while now in parallel. Generated .config files from previous LTS kernels should have both. Finally remove SOC_VIRT and update all config files using it. Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/Kconfig.socs | 3 --- arch/riscv/configs/defconfig | 2 +- arch/riscv/configs/nommu_virt_defconfig | 2 +- tools/testing/kunit/qemu_configs/riscv.py | 2 +- tools/testing/selftests/wireguard/qemu/arch/riscv32.config | 2 +- tools/testing/selftests/wireguard/qemu/arch/riscv64.config | 2 +- 6 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 2797412a7ec9..f51bb24bc84c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -52,9 +52,6 @@ config ARCH_THEAD This enables support for the RISC-V based T-HEAD SoCs. config ARCH_VIRT - def_bool SOC_VIRT - -config SOC_VIRT bool "QEMU Virt Machine" select CLINT_TIMER if RISCV_M_MODE select POWER_RESET diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 8f2bec476af2..d485e1de8a78 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,7 +32,7 @@ CONFIG_ARCH_SOPHGO=y CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_THEAD=y -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y diff --git a/arch/riscv/configs/nommu_virt_defconfig b/arch/riscv/configs/nommu_virt_defconfig index b794e2f8144e..de8143d1f738 100644 --- a/arch/riscv/configs/nommu_virt_defconfig +++ b/arch/riscv/configs/nommu_virt_defconfig @@ -24,7 +24,7 @@ CONFIG_EXPERT=y CONFIG_SLUB=y CONFIG_SLUB_TINY=y # CONFIG_MMU is not set -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_NONPORTABLE=y CONFIG_SMP=y CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0" diff --git a/tools/testing/kunit/qemu_configs/riscv.py b/tools/testing/kunit/qemu_configs/riscv.py index 12a1d525978a..c87758030ff7 100644 --- a/tools/testing/kunit/qemu_configs/riscv.py +++ b/tools/testing/kunit/qemu_configs/riscv.py @@ -13,7 +13,7 @@ if not os.path.isfile(OPENSBI_PATH): QEMU_ARCH = QemuArchParams(linux_arch='riscv', kconfig=''' -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config index a7f8e8a95625..66290cf289a9 100644 --- a/tools/testing/selftests/wireguard/qemu/arch/riscv32.config +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv32.config @@ -2,7 +2,7 @@ CONFIG_NONPORTABLE=y CONFIG_ARCH_RV32I=y CONFIG_MMU=y CONFIG_FPU=y -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_RISCV_ISA_FALLBACK=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y diff --git a/tools/testing/selftests/wireguard/qemu/arch/riscv64.config b/tools/testing/selftests/wireguard/qemu/arch/riscv64.config index daeb3e5e0965..db1aa9f388b9 100644 --- a/tools/testing/selftests/wireguard/qemu/arch/riscv64.config +++ b/tools/testing/selftests/wireguard/qemu/arch/riscv64.config @@ -1,7 +1,7 @@ CONFIG_ARCH_RV64I=y CONFIG_MMU=y CONFIG_FPU=y -CONFIG_SOC_VIRT=y +CONFIG_ARCH_VIRT=y CONFIG_RISCV_ISA_FALLBACK=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y From cd899f85b1e454188fa2f14c3396a894f440b15f Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:35 +0800 Subject: [PATCH 374/969] riscv: config: enable ARCH_CANAAN in defconfig Since K230 has been supported, allow ARCH_CANAAN to be selected to build dt and drivers for it in defconfig. Signed-off-by: Yangyu Chen Reviewed-by: Conor Dooley Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d485e1de8a78..3cae018f9315 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -33,6 +33,7 @@ CONFIG_SOC_STARFIVE=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_THEAD=y CONFIG_ARCH_VIRT=y +CONFIG_ARCH_CANAAN=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y From 4cf39b01c1745439197532f3d736875630d93cb3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 10 Apr 2024 19:26:54 +0200 Subject: [PATCH 375/969] bus: brcmstb_gisb: fix module autoloading Add MODULE_DEVICE_TABLE(), so the module could be properly autoloaded based on the alias from of_device_id table. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240410172654.255525-1-krzk@kernel.org Signed-off-by: Florian Fainelli --- drivers/bus/brcmstb_gisb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index 65ae758f3194..ee29162da4ee 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -410,6 +410,7 @@ static const struct of_device_id brcmstb_gisb_arb_of_match[] = { { .compatible = "brcm,bcm74165-gisb-arb", .data = gisb_offsets_bcm74165 }, { }, }; +MODULE_DEVICE_TABLE(of, brcmstb_gisb_arb_of_match); static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev) { From 1e596d5eff3ddbaf2c5446adcc999b2516949556 Mon Sep 17 00:00:00 2001 From: Akira Yokosawa Date: Sat, 6 Apr 2024 11:04:16 +0900 Subject: [PATCH 376/969] docs: Detect variable fonts and suggest denylisting them MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fedora and openSUSE has started deploying "variable font" [1] format Noto CJK fonts [2, 3]. "CJK" here stands for "Chinese, Japanese, and Korean". Unfortunately, XeTeX/XeLaTeX doesn't understand those fonts for historical reasons and builds of translations.pdf end up in errors if such fonts are present on the build host. To help developers work around the issue, add a script to check the presence of "variable font" Noto CJK fonts and to emit suggestions. The script is invoked in the error path of "make pdfdocs" so that the suggestions are made only when a PDF build actually fails. The first suggestion is to denylist those "variable font" files by activating a per-user and command-local fontconfig setting. For further info and backgrounds, please refer to the header comment of scripts/check-variable-font.sh newly added in this commit. Link: [1] https://en.wikipedia.org/wiki/Variable_font Link: [2] https://fedoraproject.org/wiki/Changes/Noto_CJK_Variable_Fonts Link: [3] https://build.opensuse.org/request/show/1157217 Reported-by: Jonathan Corbet Link: https://lore.kernel.org/r/8734tqsrt7.fsf@meer.lwn.net/ Reported-by: Иван Иванович Link: https://lore.kernel.org/linux-doc/1708585803.600323099@f111.i.mail.ru/ Cc: Randy Dunlap Signed-off-by: Akira Yokosawa Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240406020416.25096-1-akiyks@gmail.com --- Documentation/Makefile | 7 +- Documentation/sphinx/kerneldoc-preamble.sty | 9 +- MAINTAINERS | 1 + scripts/check-variable-fonts.sh | 117 ++++++++++++++++++++ 4 files changed, 129 insertions(+), 5 deletions(-) create mode 100755 scripts/check-variable-fonts.sh diff --git a/Documentation/Makefile b/Documentation/Makefile index b68f8c816897..a961692baa12 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -28,6 +28,10 @@ BUILDDIR = $(obj)/output PDFLATEX = xelatex LATEXOPTS = -interaction=batchmode -no-shell-escape +# For denylisting "variable font" files +# Can be overridden by setting as an env variable +FONTS_CONF_DENY_VF ?= $(HOME)/deny-vf + ifeq ($(findstring 1, $(KBUILD_VERBOSE)),) SPHINXOPTS += "-q" endif @@ -151,10 +155,11 @@ pdfdocs: else # HAVE_PDFLATEX +pdfdocs: DENY_VF = XDG_CONFIG_HOME=$(FONTS_CONF_DENY_VF) pdfdocs: latexdocs @$(srctree)/scripts/sphinx-pre-install --version-check $(foreach var,$(SPHINXDIRS), \ - $(MAKE) PDFLATEX="$(PDFLATEX)" LATEXOPTS="$(LATEXOPTS)" -C $(BUILDDIR)/$(var)/latex || exit; \ + $(MAKE) PDFLATEX="$(PDFLATEX)" LATEXOPTS="$(LATEXOPTS)" $(DENY_VF) -C $(BUILDDIR)/$(var)/latex || sh $(srctree)/scripts/check-variable-fonts.sh || exit; \ mkdir -p $(BUILDDIR)/$(var)/pdf; \ mv $(subst .tex,.pdf,$(wildcard $(BUILDDIR)/$(var)/latex/*.tex)) $(BUILDDIR)/$(var)/pdf/; \ ) diff --git a/Documentation/sphinx/kerneldoc-preamble.sty b/Documentation/sphinx/kerneldoc-preamble.sty index 3092df051c95..d479cfa73658 100644 --- a/Documentation/sphinx/kerneldoc-preamble.sty +++ b/Documentation/sphinx/kerneldoc-preamble.sty @@ -215,11 +215,12 @@ due to the lack of suitable font families and/or the texlive-xecjk package. - If you want them, please install ``Noto Sans CJK'' font families - along with the texlive-xecjk package by following instructions from + If you want them, please install non-variable ``Noto Sans CJK'' + font families along with the texlive-xecjk package by following + instructions from \sphinxcode{./scripts/sphinx-pre-install}. - Having optional ``Noto Serif CJK'' font families will improve - the looks of those translations. + Having optional non-variable ``Noto Serif CJK'' font families will + improve the looks of those translations. \end{sphinxadmonition}} \newcommand{\kerneldocEndSC}{} \newcommand{\kerneldocBeginTC}[1]{} diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..3a4768c2f712 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6406,6 +6406,7 @@ S: Maintained P: Documentation/doc-guide/maintainer-profile.rst T: git git://git.lwn.net/linux.git docs-next F: Documentation/ +F: scripts/check-variable-font.sh F: scripts/documentation-file-ref-check F: scripts/kernel-doc F: scripts/sphinx-pre-install diff --git a/scripts/check-variable-fonts.sh b/scripts/check-variable-fonts.sh new file mode 100755 index 000000000000..12765e54e4f3 --- /dev/null +++ b/scripts/check-variable-fonts.sh @@ -0,0 +1,117 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (C) Akira Yokosawa, 2024 +# +# For "make pdfdocs", reports of build errors of translations.pdf started +# arriving early 2024 [1, 2]. It turned out that Fedora and openSUSE +# tumbleweed have started deploying variable-font [3] format of "Noto CJK" +# fonts [4, 5]. For PDF, a LaTeX package named xeCJK is used for CJK +# (Chinese, Japanese, Korean) pages. xeCJK requires XeLaTeX/XeTeX, which +# does not (and likely never will) understand variable fonts for historical +# reasons. +# +# The build error happens even when both of variable- and non-variable-format +# fonts are found on the build system. To make matters worse, Fedora enlists +# variable "Noto CJK" fonts in the requirements of langpacks-ja, -ko, -zh_CN, +# -zh_TW, etc. Hence developers who have interest in CJK pages are more +# likely to encounter the build errors. +# +# This script is invoked from the error path of "make pdfdocs" and emits +# suggestions if variable-font files of "Noto CJK" fonts are in the list of +# fonts accessible from XeTeX. +# +# Assumption: +# File names are not modified from those of upstream Noto CJK fonts: +# https://github.com/notofonts/noto-cjk/ +# +# References: +# [1]: https://lore.kernel.org/r/8734tqsrt7.fsf@meer.lwn.net/ +# [2]: https://lore.kernel.org/r/1708585803.600323099@f111.i.mail.ru/ +# [3]: https://en.wikipedia.org/wiki/Variable_font +# [4]: https://fedoraproject.org/wiki/Changes/Noto_CJK_Variable_Fonts +# [5]: https://build.opensuse.org/request/show/1157217 +# +#=========================================================================== +# Workarounds for building translations.pdf +#=========================================================================== +# +# * Denylist "variable font" Noto CJK fonts. +# - Create $HOME/deny-vf/fontconfig/fonts.conf from template below, with +# tweaks if necessary. Remove leading "# ". +# - Path of fontconfig/fonts.conf can be overridden by setting an env +# variable FONTS_CONF_DENY_VF. +# +# * Template: +# ----------------------------------------------------------------- +# +# +# +# +# +# +# +# /usr/share/fonts/google-noto-*-cjk-vf-fonts +# +# /usr/share/fonts/truetype/Noto*CJK*-VF.otf +# +# +# +# ----------------------------------------------------------------- +# +# The denylisting is activated for "make pdfdocs". +# +# * For skipping CJK pages in PDF +# - Uninstall texlive-xecjk. +# Denylisting is not needed in this case. +# +# * For printing CJK pages in PDF +# - Need non-variable "Noto CJK" fonts. +# * Fedora +# - google-noto-sans-cjk-fonts +# - google-noto-serif-cjk-fonts +# * openSUSE tumbleweed +# - Non-variable "Noto CJK" fonts are not available as distro packages +# as of April, 2024. Fetch a set of font files from upstream Noto +# CJK Font released at: +# https://github.com/notofonts/noto-cjk/tree/main/Sans#super-otc +# and at: +# https://github.com/notofonts/noto-cjk/tree/main/Serif#super-otc +# , then uncompress and deploy them. +# - Remember to update fontconfig cache by running fc-cache. +# +# !!! Caution !!! +# Uninstalling "variable font" packages can be dangerous. +# They might be depended upon by other packages important for your work. +# Denylisting should be less invasive, as it is effective only while +# XeLaTeX runs in "make pdfdocs". + +# Default per-user fontconfig path (overridden by env variable) +: ${FONTS_CONF_DENY_VF:=$HOME/deny-vf} + +export XDG_CONFIG_HOME=${FONTS_CONF_DENY_VF} + +vffonts=`fc-list -b | grep -iE 'file: .*noto.*cjk.*-vf' | \ + sed -e 's/\tfile:/ file:/' -e 's/(s)$//' | sort | uniq` + +if [ "x$vffonts" != "x" ] ; then + echo '=============================================================================' + echo 'XeTeX is confused by "variable font" files listed below:' + echo "$vffonts" + echo + echo 'For CJK pages in PDF, they need to be hidden from XeTeX by denylisting.' + echo 'Or, CJK pages can be skipped by uninstalling texlive-xecjk.' + echo + echo 'For more info on denylisting, other options, and variable font, see header' + echo 'comments of scripts/check-variable-fonts.sh.' + echo '=============================================================================' +fi + +# As this script is invoked from Makefile's error path, always error exit +# regardless of whether any variable font is discovered or not. +exit 1 From 9e66f74ce769b395cb5ccac104e33f9f41a11a9b Mon Sep 17 00:00:00 2001 From: Karel Balej Date: Thu, 28 Mar 2024 20:29:15 +0100 Subject: [PATCH 377/969] docs: *-regressions.rst: unify quoting, add missing word Quoting of the '"no regressions" rule' expression differs between occurrences, sometimes being presented as '"no regressions rule"'. Unify the quoting using the first form which seems semantically correct or is at least used dominantly, albeit marginally. One of the occurrences is obviously missing the 'rule' part -- add it. Signed-off-by: Karel Balej Reviewed-by: Thorsten Leemhuis Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240328194342.11760-2-balejk@matfyz.cz --- Documentation/admin-guide/reporting-regressions.rst | 10 +++++----- Documentation/process/handling-regressions.rst | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/admin-guide/reporting-regressions.rst b/Documentation/admin-guide/reporting-regressions.rst index 76b246ecf21b..946518355a2c 100644 --- a/Documentation/admin-guide/reporting-regressions.rst +++ b/Documentation/admin-guide/reporting-regressions.rst @@ -42,12 +42,12 @@ The important basics -------------------- -What is a "regression" and what is the "no regressions rule"? +What is a "regression" and what is the "no regressions" rule? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ It's a regression if some application or practical use case running fine with one Linux kernel works worse or not at all with a newer version compiled using a -similar configuration. The "no regressions rule" forbids this to take place; if +similar configuration. The "no regressions" rule forbids this to take place; if it happens by accident, developers that caused it are expected to quickly fix the issue. @@ -173,7 +173,7 @@ Additional details about regressions ------------------------------------ -What is the goal of the "no regressions rule"? +What is the goal of the "no regressions" rule? ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Users should feel safe when updating kernel versions and not have to worry @@ -199,8 +199,8 @@ Exceptions to this rule are extremely rare; in the past developers almost always turned out to be wrong when they assumed a particular situation was warranting an exception. -Who ensures the "no regressions" is actually followed? -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Who ensures the "no regressions" rule is actually followed? +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The subsystem maintainers should take care of that, which are watched and supported by the tree maintainers -- e.g. Linus Torvalds for mainline and diff --git a/Documentation/process/handling-regressions.rst b/Documentation/process/handling-regressions.rst index ce6753a674f3..49ba1410cfce 100644 --- a/Documentation/process/handling-regressions.rst +++ b/Documentation/process/handling-regressions.rst @@ -284,7 +284,7 @@ What else is there to known about regressions? Check out Documentation/admin-guide/reporting-regressions.rst, it covers a lot of other aspects you want might want to be aware of: - * the purpose of the "no regressions rule" + * the purpose of the "no regressions" rule * what issues actually qualify as regression From 8819b60eed720819ea392d2b6d955e332caf703d Mon Sep 17 00:00:00 2001 From: Haoyang Liu Date: Sat, 6 Apr 2024 16:36:43 +0800 Subject: [PATCH 378/969] docs/zh_CN: Add dev-tools/kmemleak Chinese translation Translate dev-tools/kmemleak.rst into Chinese and add it into zh_CN/dev-tools/index.rst. Signed-off-by: Haoyang Liu Reviewed-by: Yanteng Si Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240406083643.5056-1-tttturtleruss@hust.edu.cn --- .../translations/zh_CN/dev-tools/index.rst | 2 +- .../translations/zh_CN/dev-tools/kmemleak.rst | 229 ++++++++++++++++++ 2 files changed, 230 insertions(+), 1 deletion(-) create mode 100644 Documentation/translations/zh_CN/dev-tools/kmemleak.rst diff --git a/Documentation/translations/zh_CN/dev-tools/index.rst b/Documentation/translations/zh_CN/dev-tools/index.rst index c4463f0750f0..51e5b3e724c1 100644 --- a/Documentation/translations/zh_CN/dev-tools/index.rst +++ b/Documentation/translations/zh_CN/dev-tools/index.rst @@ -23,13 +23,13 @@ Documentation/translations/zh_CN/dev-tools/testing-overview.rst gcov kasan ubsan + kmemleak gdb-kernel-debugging Todolist: - coccinelle - kcov - - kmemleak - kcsan - kfence - kgdb diff --git a/Documentation/translations/zh_CN/dev-tools/kmemleak.rst b/Documentation/translations/zh_CN/dev-tools/kmemleak.rst new file mode 100644 index 000000000000..d248c8428095 --- /dev/null +++ b/Documentation/translations/zh_CN/dev-tools/kmemleak.rst @@ -0,0 +1,229 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../disclaimer-zh_CN.rst + +:Original: Documentation/dev-tools/kmemleak.rst +:Translator: 刘浩阳 Haoyang Liu + +内核内存泄露检测器 +================== + +Kmemleak 提供了一个类似 `可追踪的垃圾收集器 `_ 的方法来检测可能的内核内存泄漏，不同的是孤立对象不会 +被释放，而是仅通过 /sys/kernel/debug/kmemleak 报告。Valgrind 工具 +（``memcheck --leak-check``）使用了一种相似的方法来检测用户空间应用中的内存泄 +露。 + +用法 +---- + +"Kernel hacking" 中的 CONFIG_DEBUG_KMEMLEAK 必须被启用。一个内核线程每10分钟 +（默认情况下）扫描一次内存，并且打印出新发现的未被引用的对象个数。 +如果 ``debugfs`` 没有挂载，则执行:: + + # mount -t debugfs nodev /sys/kernel/debug/ + +显示所有扫描出的可能的内存泄漏的细节信息:: + + # cat /sys/kernel/debug/kmemleak + +启动一次中等程度的内存扫描:: + + # echo scan > /sys/kernel/debug/kmemleak + +清空当前所有可能的内存泄露列表:: + + # echo clear > /sys/kernel/debug/kmemleak + +当再次读取 ``/sys/kernel/debug/kmemleak`` 文件时，将会输出自上次扫描以来检测到的 +新的内存泄露。 + +注意，孤立目标是通过被分配时间来排序的，列表开始的对象可能会导致后续的对象都被 +识别为孤立对象。 + +可以通过写入 ``/sys/kernel/debug/kmemleak`` 文件在运行时修改内存扫描参数。下面是 +支持的参数： + + +* off + 禁用 kmemleak（不可逆） +* stack=on + 开启任务栈扫描（默认） +* stack=off + 禁用任务栈扫描 +* scan=on + 开启自动内存扫描线程（默认） +* scan=off + 关闭自动内存扫描线程 +* scan=; + 设定自动内存扫描间隔，以秒为单位（默认值为 600，设置为 0 表示停 + 止自动扫描） +* scan + 触发一次内存扫描 +* clear + 通过标记所有当前已报告的未被引用对象为灰，从而清空当前可能的内存泄露列 + 表；如果 kmemleak 被禁用，则释放所有 kmemleak 对象，。 +* dump= + 输出存储在 中的对象信息 + +可以通过在内核命令行中传递 ``kmemleak=off`` 参数从而在启动时禁用 Kmemleak。 + +在 kmemleak 初始化之前就可能会有内存分配或释放，这些操作被存储在一个早期日志缓 +冲区中。缓冲区的大小通过 CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE 选项配置。 + +如果 CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF 被启用，则 kmemleak 默认被禁用。在内核命 +令行中传递 ``kmemleak=on`` 参数来开启这个功能。 + +如果出现 "Error while writing to stdout" 或 "write_loop: Invalid argument" 这样 +的错误，请确认 kmemleak 被正确启用。 + +基础算法 +-------- + +通过 :c:func:`kmalloc`, :c:func:`vmalloc`, :c:func:`kmem_cache_alloc` 以及同类 +函数均被跟踪，指针，包括一些额外的信息如大小和栈追踪等，都被存储在红黑树中。 +对应的释放函数调用也被追踪，并从 kmemleak 数据结构中移除相应指针。 + +对于一个已分配的内存块，如果通过扫描内存（包括保存寄存器）没有发现任何指针指向 +它的起始地址或者其中的任何位置，则认为这块内存是孤立的。这意味着内核无法将该内 +存块的地址传递给一个释放内存函数，这块内存便被认为泄露了。 + +扫描算法步骤： + + 1. 标记所有对象为白色（最后剩下的白色对象被认为是孤立的） + 2. 从数据节和栈开始扫描内存，检测每个值是否是红黑树中存储的地址。如果一个指向 + 白色对象的指针被检测到，则将该对象标记为灰色。 + 3. 扫描灰色对象引用的其他对象（有些白色对象可能会变为灰色并被添加到灰名单末尾 + ）直到灰名单为空。 + 4. 剩余的白色对象就被认为是孤立的并通过 /sys/kernel/debug/kmemleak 报告。 + +有些指向已分配的内存块的指针存储在内核内部的数据结构中，它们不能被检测为孤立。 +为了避免这种情况，kmemleak 也存储了指向需要被查找的内存块范围内的任意地址的地址 +数量，如此一来这些内存便不会被认为泄露。一个例子是 __vmalloc()。 + +用 kmemleak 测试特定部分 +------------------------ + +在初始化启动阶段 /sys/kernel/debug/kmemleak 的输出可能会很多，这也可能是你在开发 +时编写的漏洞百出的代码导致的。为了解决这种情况你可以使用 'clear' 命令来清除 +/sys/kernel/debug/kmemleak 输出的所有的未引用对象。在执行 'clear' 后执行 'scan' +可以发现新的未引用对象，这将会有利你测试代码的特定部分。 + +为了用一个空的 kmemleak 测试一个特定部分，执行:: + + # echo clear > /sys/kernel/debug/kmemleak + ... 测试你的内核或者模块 ... + # echo scan > /sys/kernel/debug/kmemleak + +然后像平常一样获得报告:: + + # cat /sys/kernel/debug/kmemleak + +释放 kmemleak 内核对象 +---------------------- + +为了允许访问先前发现的内存泄露，当用户禁用或发生致命错误导致 kmemleak +被禁用时，内核中的 kmemleak 对象不会被释放。这些对象可能会占用很大 +一部分物理内存。 + +在这种情况下，你可以用如下命令回收这些内存:: + + # echo clear > /sys/kernel/debug/kmemleak + +Kmemleak API +------------ + +在 include/linux/kmemleak.h 头文件中查看函数原型： + +- ``kmemleak_init`` - 初始化 kmemleak +- ``kmemleak_alloc`` - 通知一个内存块的分配 +- ``kmemleak_alloc_percpu`` - 通知一个 percpu 类型的内存分配 +- ``kmemleak_vmalloc`` - 通知一个使用 vmalloc() 的内存分配 +- ``kmemleak_free`` - 通知一个内存块的释放 +- ``kmemleak_free_part`` - 通知一个部分的内存释放 +- ``kmemleak_free_percpu`` - 通知一个 percpu 类型的内存释放 +- ``kmemleak_update_trace`` - 更新分配对象过程的栈追踪 +- ``kmemleak_not_leak`` - 标记一个对象内存为未泄露的 +- ``kmemleak_ignore`` - 不要扫描或报告某个对象未泄露的 +- ``kmemleak_scan_area`` - 在内存块中添加扫描区域 +- ``kmemleak_no_scan`` - 不扫描某个内存块 +- ``kmemleak_erase`` - 在指针变量中移除某个旧的值 +- ``kmemleak_alloc_recursive`` - 和 kmemleak_alloc 效果相同但会检查是否有递归的 + 内存分配 +- ``kmemleak_free_recursive`` - 和 kmemleak_free 效果相同但会检查是否有递归的 + 内存释放 + +下列函数使用一个物理地址作为对象指针并且只在地址有一个 lowmem 映射时做出相应的 +行为： + +- ``kmemleak_alloc_phys`` +- ``kmemleak_free_part_phys`` +- ``kmemleak_ignore_phys`` + +解决假阳性/假阴性 +----------------- + +假阴性是指由于在内存扫描中有值指向该对象导致 kmemleak 没有报告的实际存在的内存 +泄露（孤立对象）。为了减少假阴性的出现次数，kmemleak 提供了 kmemleak_ignore， +kmemleak_scan_area，kmemleak_no_scan 和 kmemleak_erase 函数（见上）。 +任务栈也会增加假阴性的数量并且默认不开启对它们的扫描。 + +假阳性是对象被误报为内存泄露（孤立对象）。对于已知未泄露的对象，kmemleak +提供了 kmemleak_not_leak 函数。同时 kmemleak_ignore 可以用于标记已知不包含任何 +其他指针的内存块，标记后该内存块不会再被扫描。 + +一些被报告的泄露仅仅是暂时的，尤其是在 SMP（对称多处理）系统中，因为其指针 +暂存在 CPU 寄存器或栈中。Kmemleak 定义了 MSECS_MIN_AGE（默认值为 1000） +来表示一个被报告为内存泄露的对象的最小存活时间。 + +限制和缺点 +---------- + +主要的缺点是内存分配和释放的性能下降。为了避免其他的损失，只有当 +/sys/kernel/debug/kmemleak 文件被读取时才会进行内存扫描。无论如何，这个工具是出于 +调试的目标，性能表现可能不是最重要的。 + +为了保持算法简单，kmemleak 寻找指向某个内存块范围中的任何值。这可能会引发假阴性 +现象的出现。但是，最后一个真正的内存泄露也会变得明显。 + +非指针值的数据是假阴性的另一个来源。在将来的版本中，kmemleak 仅仅会扫 +描已分配结构体中的指针成员。这个特性会解决上述很多的假阴性情况。 + +Kmemleak 会报告假阳性。这可能发生在某些被分配的内存块不需要被释放的情况下 +（某些 init_call 函数中），指针的计算是通过其他方法而不是常规的 container_of 宏 +或是指针被存储在 kmemleak 没有扫描的地方。 + +页分配和 ioremap 不会被追踪。 + +使用 kmemleak-test 测试 +----------------------- + +为了检测是否成功启用了 kmemleak，你可以使用一个故意制造内存泄露的模块 +kmemleak-test。设置 CONFIG_SAMPLE_KMEMLEAK 为模块（不能作为内建模块使用） +并且启动启用了 kmemleak 的内核。加载模块并执行一次扫描:: + + # modprobe kmemleak-test + # echo scan > /sys/kernel/debug/kmemleak + +注意你可能无法立刻或在第一次扫描后得到结果。当 kmemleak 得到结果，将会输出日 +志 ``kmemleak: new suspected memory leaks`` 。然后通过读取文件 +获取信息:: + + # cat /sys/kernel/debug/kmemleak + unreferenced object 0xffff89862ca702e8 (size 32): + comm "modprobe", pid 2088, jiffies 4294680594 (age 375.486s) + hex dump (first 32 bytes): + 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b kkkkkkkkkkkkkkkk + 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 kkkkkkkkkkkkkkk. + backtrace: + [<00000000e0a73ec7>] 0xffffffffc01d2036 + [<000000000c5d2a46>] do_one_initcall+0x41/0x1df + [<0000000046db7e0a>] do_init_module+0x55/0x200 + [<00000000542b9814>] load_module+0x203c/0x2480 + [<00000000c2850256>] __do_sys_finit_module+0xba/0xe0 + [<000000006564e7ef>] do_syscall_64+0x43/0x110 + [<000000007c873fa6>] entry_SYSCALL_64_after_hwframe+0x44/0xa9 + ... + +用 ``rmmod kmemleak_test`` 移除模块时也会触发 +kmemleak 的结果输出。 From 7a40c60c8acb71eb2b5196b0e675ba9e58af1b69 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 10 Apr 2024 19:02:41 +0200 Subject: [PATCH 379/969] memory: brcmstb_memc: fix module autoloading Add MODULE_DEVICE_TABLE(), so the module could be properly autoloaded based on the alias from of_device_id table. Signed-off-by: Krzysztof Kozlowski Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/20240410170241.248626-1-krzk@kernel.org --- drivers/memory/brcmstb_memc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index ea9213f7152e..4f17a93aa028 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -243,6 +243,7 @@ static const struct of_device_id brcmstb_memc_of_match[] = { }, {} }; +MODULE_DEVICE_TABLE(of, brcmstb_memc_of_match); static int brcmstb_memc_suspend(struct device *dev) { From bf11908757eeab716536d16a32693b5dcd6990de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Apr 2024 22:46:15 +0200 Subject: [PATCH 380/969] memory: mtk-smi: fix module autoloading Add MODULE_DEVICE_TABLE(), so the module could be properly autoloaded based on the alias from of_device_id table. Reviewed-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240409204615.83928-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/memory/mtk-smi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 572c7fbdcfd3..fbe52ecc0eca 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -450,6 +450,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, {} }; +MODULE_DEVICE_TABLE(of, mtk_smi_larb_of_ids); static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) { @@ -735,6 +736,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365}, {} }; +MODULE_DEVICE_TABLE(of, mtk_smi_common_of_ids); static int mtk_smi_common_probe(struct platform_device *pdev) { From bb7b3419627eb34f3466022d1f4b3c942c09712d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sat, 9 Mar 2024 17:02:55 +0800 Subject: [PATCH 381/969] riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC Add clock generator node for CV1800B and CV1812H. Until now, It uses DT override to minimize duplication. This may change in the future. See the last link for the discussion on maintaining DT of CV1800 series. Link: https://github.com/milkv-duo/duo-files/blob/6f4e9b8ecb459e017cca1a8df248a19ca70837a3/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/ Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/IA1PR20MB4953ED6A4B57773865F49D6DBB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++ arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 4 ++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index 165e9e320a8c..baf641829e72 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -16,3 +16,7 @@ &clint { compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; }; + +&clk { + compatible = "sophgo,cv1800-clk"; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi index 3e7a942f5c1a..7fa4c1e2d1da 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -22,3 +22,7 @@ &clint { compatible = "sophgo,cv1812h-clint", "thead,c900-clint"; }; + +&clk { + compatible = "sophgo,cv1810-clk"; +}; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 405f4ba18392..c744c442304c 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -61,6 +61,12 @@ dma-noncoherent; ranges; + clk: clock-controller@3002000 { + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; From 18e8c6d2cced6c57d62813f49b57eeb8ee02f984 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sat, 9 Mar 2024 17:02:56 +0800 Subject: [PATCH 382/969] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC Add missing clocks of uart node for CV1800B and CV1812H. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/IA1PR20MB4953198222C3ABC2A2B6DE21BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index c744c442304c..dc6452a2fe01 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2023 Inochi Amaoto */ +#include #include #include @@ -143,7 +144,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -153,7 +155,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04150000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -163,7 +166,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04160000 0x100>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -173,7 +177,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x04170000 0x100>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -183,7 +188,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; + clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; From 4281f8f1489951a97af856e360c5d0bb8dc43096 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 8 Feb 2024 08:22:11 +0800 Subject: [PATCH 383/969] riscv: dts: sophgo: cv18xx: Add spi devices Add spi devices for the CV180x, CV181x and SG200x soc. Link: https://lore.kernel.org/r/IA1PR20MB49532705DE532BCF81CCEFD0BB442@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index dc6452a2fe01..dcb219d9d2fa 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -184,6 +184,50 @@ status = "disabled"; }; + spi0: spi@4180000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x04180000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; + clock-names = "ssi_clk", "pclk"; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi1: spi@4190000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x04190000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; + clock-names = "ssi_clk", "pclk"; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi2: spi@41a0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x041a0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; + clock-names = "ssi_clk", "pclk"; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi3: spi@41b0000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x041b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; + clock-names = "ssi_clk", "pclk"; + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + uart4: serial@41c0000 { compatible = "snps,dw-apb-uart"; reg = <0x041c0000 0x100>; From 65fcc08b4cfe92d5d2c39710b3145d0b56e8391d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 8 Feb 2024 08:22:12 +0800 Subject: [PATCH 384/969] riscv: dts: sophgo: cv18xx: Add i2c devices Add i2c devices for the CV180x, CV181x and SG200x soc. Link: https://lore.kernel.org/r/IA1PR20MB49531AA2DBD4832B7926D4A8BB442@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 55 ++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index dcb219d9d2fa..75d0c57f4ffb 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -140,6 +140,61 @@ }; }; + i2c0: i2c@4000000 { + compatible = "snps,designware-i2c"; + reg = <0x04000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; + clock-names = "ref", "pclk"; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@4010000 { + compatible = "snps,designware-i2c"; + reg = <0x04010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; + clock-names = "ref", "pclk"; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c2: i2c@4020000 { + compatible = "snps,designware-i2c"; + reg = <0x04020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; + clock-names = "ref", "pclk"; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c3: i2c@4030000 { + compatible = "snps,designware-i2c"; + reg = <0x04030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; + clock-names = "ref", "pclk"; + interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c4: i2c@4040000 { + compatible = "snps,designware-i2c"; + reg = <0x04040000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; + clock-names = "ref", "pclk"; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; From dfd458a95d78ce31855fe06bbfde4f4fe60c40db Mon Sep 17 00:00:00 2001 From: "Uladzislau Rezki (Sony)" Date: Fri, 8 Mar 2024 18:34:04 +0100 Subject: [PATCH 385/969] rcu: Add data structures for synchronize_rcu() The synchronize_rcu() call is going to be reworked, thus this patch adds dedicated fields into the rcu_state structure. Reviewed-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/kernel/rcu/tree.h b/kernel/rcu/tree.h index df48160b3136..b942b9437438 100644 --- a/kernel/rcu/tree.h +++ b/kernel/rcu/tree.h @@ -315,6 +315,13 @@ do { \ __set_current_state(TASK_RUNNING); \ } while (0) +#define SR_NORMAL_GP_WAIT_HEAD_MAX 5 + +struct sr_wait_node { + atomic_t inuse; + struct llist_node node; +}; + /* * RCU global state, including node hierarchy. This hierarchy is * represented in "heap" form in a dense array. The root (first level) @@ -400,6 +407,13 @@ struct rcu_state { /* Synchronize offline with */ /* GP pre-initialization. */ int nocb_is_setup; /* nocb is setup from boot */ + + /* synchronize_rcu() part. */ + struct llist_head srs_next; /* request a GP users. */ + struct llist_node *srs_wait_tail; /* wait for GP users. */ + struct llist_node *srs_done_tail; /* ready for GP users. */ + struct sr_wait_node srs_wait_nodes[SR_NORMAL_GP_WAIT_HEAD_MAX]; + struct work_struct srs_cleanup_work; }; /* Values for rcu_state structure's gp_flags field. */ From 02b3c5fcdfe46f9c9dd5d3fc199612b13bf47c06 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 22 Feb 2024 10:25:44 -0800 Subject: [PATCH 386/969] tracing: Select new NEED_TASKS_RCU Kconfig option Currently, if a Kconfig option depends on TASKS_RCU, it conditionally does "select TASKS_RCU if PREEMPTION". This works, but requires any change in this enablement logic to be replicated across all such "select" clauses. A new NEED_TASKS_RCU Kconfig option has been created to allow this enablement logic to be in one place in kernel/rcu/Kconfig. Therefore, select the new NEED_TASKS_RCU Kconfig option instead of the old TASKS_RCU option. Signed-off-by: Paul E. McKenney Cc: Steven Rostedt Cc: Masami Hiramatsu Cc: Mathieu Desnoyers Cc: Cc: Ankur Arora Cc: Thomas Gleixner Acked-by: Mark Rutland Signed-off-by: Uladzislau Rezki (Sony) --- kernel/trace/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/trace/Kconfig b/kernel/trace/Kconfig index 61c541c36596..6cdc5ff919b0 100644 --- a/kernel/trace/Kconfig +++ b/kernel/trace/Kconfig @@ -163,7 +163,7 @@ config TRACING select BINARY_PRINTF select EVENT_TRACING select TRACE_CLOCK - select TASKS_RCU if PREEMPTION + select NEED_TASKS_RCU config GENERIC_TRACER bool @@ -204,7 +204,7 @@ config FUNCTION_TRACER select GENERIC_TRACER select CONTEXT_SWITCH_TRACER select GLOB - select TASKS_RCU if PREEMPTION + select NEED_TASKS_RCU select TASKS_RUDE_RCU help Enable the kernel to trace every kernel function. This is done From e438acfda8a0088a3c7f450a7ffefeb56074e41e Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:24 +0300 Subject: [PATCH 387/969] arm64: dts: rockchip: Add UART9 (bluetooth) to Khadas Edge 2 Khadas Edge 2 has onboard AP6275P Wi-Fi6 (PCIe2) and BT5 (UART9) module. This commit enables UART9. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/0a10afeff3aec3a8bccca2dbe4e65f7b4a2c4666.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-khadas-edge2.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 1bd6cb9c6111..4173afb78f9b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -244,6 +244,20 @@ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wireless-bluetooth { + bt_reset_pin: bt-reset-pin { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_pin: bt-wake-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &pcie2x1l2 { @@ -644,6 +658,12 @@ status = "okay"; }; +&uart9 { + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; + status = "okay"; +}; + &u2phy2 { status = "okay"; }; From c0b3c764b64a5c8eee056e62580de0f44e7dcd0f Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Tue, 20 Feb 2024 01:34:25 +0300 Subject: [PATCH 388/969] arm64: dts: rockchip: Add RTC to Khadas Edge 2 Khadas Edge 2 has PT7C4363 RTC that compatible with HYM8563. The RTC pinctrl is also connected to MCU. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/4c4c9140ff36f290ba64ecc8b3e218df6a5ab273.1708381247.git.efectn@protonmail.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 4173afb78f9b..ea085abb98ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -216,6 +216,18 @@ }; }; +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + wakeup-source; + }; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { From 6c747d0fe72a85157ec9b95a3100fb98c81ad456 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Mon, 1 Apr 2024 21:22:40 +0300 Subject: [PATCH 389/969] arm64: dts: qcom: sc7180: Fix UFS PHY clocks QMP PHY used in SC7180 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Signed-off-by: Danila Tikhonov Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20240401182240.55282-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3215709a7001..4774a859bd7e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1585,9 +1585,12 @@ compatible = "qcom,sc7180-qmp-ufs-phy", "qcom,sm7150-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; From 1e52af7f023c44859868306fac1a4b6b556cf47b Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 28 Feb 2024 11:17:28 -0800 Subject: [PATCH 390/969] bpf: Choose RCU Tasks based on TASKS_RCU rather than PREEMPTION The advent of CONFIG_PREEMPT_AUTO, AKA lazy preemption, will mean that even kernels built with CONFIG_PREEMPT_NONE or CONFIG_PREEMPT_VOLUNTARY might see the occasional preemption, and that this preemption just might happen within a trampoline. Therefore, update bpf_tramp_image_put() to choose call_rcu_tasks() based on CONFIG_TASKS_RCU instead of CONFIG_PREEMPTION. This change might enable further simplifications, but the goal of this effort is to make the code safe, not necessarily optimal. Signed-off-by: Paul E. McKenney Cc: Alexei Starovoitov Cc: Daniel Borkmann Cc: John Fastabend Cc: Andrii Nakryiko Cc: Martin KaFai Lau Cc: Song Liu Cc: Yonghong Song Cc: KP Singh Cc: Stanislav Fomichev Cc: Hao Luo Cc: Jiri Olsa Cc: Ankur Arora Cc: Thomas Gleixner Cc: Signed-off-by: Uladzislau Rezki (Sony) --- kernel/bpf/trampoline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/bpf/trampoline.c b/kernel/bpf/trampoline.c index db7599c59c78..88673a4267eb 100644 --- a/kernel/bpf/trampoline.c +++ b/kernel/bpf/trampoline.c @@ -333,7 +333,7 @@ static void bpf_tramp_image_put(struct bpf_tramp_image *im) int err = bpf_arch_text_poke(im->ip_after_call, BPF_MOD_JUMP, NULL, im->ip_epilogue); WARN_ON(err); - if (IS_ENABLED(CONFIG_PREEMPTION)) + if (IS_ENABLED(CONFIG_TASKS_RCU)) call_rcu_tasks(&im->rcu, __bpf_tramp_image_put_rcu_tasks); else percpu_ref_kill(&im->pcref); From 64ec8b6ad61997262fb3373970377f5fb709454b Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 28 Feb 2024 11:30:43 -0800 Subject: [PATCH 391/969] ftrace: Choose RCU Tasks based on TASKS_RCU rather than PREEMPTION The advent of CONFIG_PREEMPT_AUTO, AKA lazy preemption, will mean that even kernels built with CONFIG_PREEMPT_NONE or CONFIG_PREEMPT_VOLUNTARY might see the occasional preemption, and that this preemption just might happen within a trampoline. Therefore, update ftrace_shutdown() to invoke synchronize_rcu_tasks() based on CONFIG_TASKS_RCU instead of CONFIG_PREEMPTION. [ paulmck: Apply Steven Rostedt feedback. ] Signed-off-by: Paul E. McKenney Cc: Steven Rostedt Cc: Masami Hiramatsu Cc: Mark Rutland Cc: Mathieu Desnoyers Cc: Ankur Arora Cc: Thomas Gleixner Cc: Signed-off-by: Uladzislau Rezki (Sony) --- kernel/trace/ftrace.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index da1710499698..6c96b30f3d63 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -3157,8 +3157,7 @@ out: * synchronize_rcu_tasks() will wait for those tasks to * execute and either schedule voluntarily or enter user space. */ - if (IS_ENABLED(CONFIG_PREEMPTION)) - synchronize_rcu_tasks(); + synchronize_rcu_tasks(); ftrace_trampoline_free(ops); } From 4e07a95f7402de092cd71b2cb96c69f85c98f251 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:31 +0200 Subject: [PATCH 392/969] arm64: dts: rockchip: fix usb2phy nodename for rk3588 usb2-phy should be named usb2phy according to the DT binding, so let's fix it up accordingly. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index ac5bd630f155..87df09022735 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -599,7 +599,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy2: usb2-phy@8000 { + u2phy2: usb2phy@8000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x8000 0x10>; interrupts = ; @@ -624,7 +624,7 @@ #address-cells = <1>; #size-cells = <1>; - u2phy3: usb2-phy@c000 { + u2phy3: usb2phy@c000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0xc000 0x10>; interrupts = ; From abe68e0ca71dddce0e5419e35507cb464d61870d Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:32 +0200 Subject: [PATCH 393/969] arm64: dts: rockchip: reorder usb2phy properties for rk3588 Reorder common DT properties alphabetically for usb2phy, according to latest DT style rules. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 87df09022735..58d12969b7ee 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -602,13 +602,13 @@ u2phy2: usb2phy@8000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0x8000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy2"; - #clock-cells = <0>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy2_host: host-port { @@ -627,13 +627,13 @@ u2phy3: usb2phy@c000 { compatible = "rockchip,rk3588-usb2phy"; reg = <0xc000 0x10>; - interrupts = ; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; + #clock-cells = <0>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; clock-names = "phyclk"; clock-output-names = "usb480m_phy3"; - #clock-cells = <0>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; status = "disabled"; u2phy3_host: host-port { From e18e5e8188f2671abf63abe7db5f21555705130f Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:33 +0200 Subject: [PATCH 394/969] arm64: dts: rockchip: add USBDP phys on rk3588 Add both USB3-DisplayPort PHYs to RK3588 SoC DT. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 52 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 63 +++++++++++++++++++++++ 2 files changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5519c1430cb7..4fdd047c9eb9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -17,6 +17,36 @@ reg = <0x0 0xfd5c0000 0x0 0x100>; }; + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -310,6 +340,28 @@ }; }; + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + combphy1_ps: phy@fee10000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee10000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 58d12969b7ee..9063c0bb0f02 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -572,12 +572,23 @@ reg = <0x0 0xfd5a4000 0x0 0x2000>; }; + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + vo1_grf: syscon@fd5a8000 { compatible = "rockchip,rk3588-vo-grf", "syscon"; reg = <0x0 0xfd5a8000 0x0 0x100>; clocks = <&cru PCLK_VO1GRF>; }; + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -593,6 +604,36 @@ reg = <0x0 0xfd5c4000 0x0 0x100>; }; + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + usb2phy2_grf: syscon@fd5d8000 { compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; reg = <0x0 0xfd5d8000 0x0 0x4000>; @@ -2449,6 +2490,28 @@ status = "disabled"; }; + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:34 +0200 Subject: [PATCH 395/969] arm64: dts: rockchip: add USB3 DRD controllers on rk3588 Add both USB3 dual-role controllers to the RK3588 devicetree. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 4fdd047c9eb9..5984016b5f96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,26 @@ #include "rk3588-pinctrl.dtsi" / { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + pcie30_phy_grf: syscon@fd5b8000 { compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; reg = <0x0 0xfd5b8000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 9063c0bb0f02..b0a59ec5183b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -492,6 +492,28 @@ }; }; + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + usb_host0_ehci: usb@fc800000 { compatible = "rockchip,rk3588-ehci", "generic-ehci"; reg = <0x0 0xfc800000 0x0 0x40000>; From a817d98dc2e8f9c252bd3e31d86dfe61ec76d23f Mon Sep 17 00:00:00 2001 From: Peter Oberparleiter Date: Tue, 26 Mar 2024 17:03:20 +0100 Subject: [PATCH 396/969] s390/cio: rework channel-utilization-block handling Convert channel-utilization-block (CUB) address variables from separate named fields to arrays of addresses. Also simplify error handling and introduce named constants. This is done in preparation of introducing additional CUBs. Note: With this change the __packed annotation of secm_area is required to prevent an alignment hole that would otherwise occur due to the switch from u32 to dma64_t. Reviewed-by: Vineeth Vijayan Acked-by: Heiko Carstens Signed-off-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev --- drivers/s390/cio/chp.c | 8 +++--- drivers/s390/cio/chsc.c | 56 +++++++++++++++++++++++++++-------------- drivers/s390/cio/css.h | 10 ++++++-- 3 files changed, 49 insertions(+), 25 deletions(-) diff --git a/drivers/s390/cio/chp.c b/drivers/s390/cio/chp.c index 675d7ed82356..0edb6dd0f105 100644 --- a/drivers/s390/cio/chp.c +++ b/drivers/s390/cio/chp.c @@ -161,12 +161,12 @@ static void chp_measurement_copy_block(struct cmg_entry *buf, struct cmg_entry *entry, reference_buf; int idx; - if (chpid.id < 128) { - area = css->cub_addr1; + if (chpid.id < CSS_CUES_PER_PAGE) { + area = css->cub[0]; idx = chpid.id; } else { - area = css->cub_addr2; - idx = chpid.id - 128; + area = css->cub[1]; + idx = chpid.id - CSS_CUES_PER_PAGE; } entry = area + (idx * sizeof(struct cmg_entry)); do { diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c index 89e51f197cdd..3344fa996ec4 100644 --- a/drivers/s390/cio/chsc.c +++ b/drivers/s390/cio/chsc.c @@ -874,19 +874,16 @@ int __chsc_do_secm(struct channel_subsystem *css, int enable) u32 : 30; u32 key : 4; u32 : 28; - u32 zeroes1; - dma32_t cub_addr1; - u32 zeroes2; - dma32_t cub_addr2; + dma64_t cub[CSS_NUM_CUB_PAGES]; u32 reserved[13]; struct chsc_header response; u32 status : 8; u32 : 4; u32 fmt : 4; u32 : 16; - } *secm_area; + } __packed *secm_area; unsigned long flags; - int ret, ccode; + int ret, ccode, i; spin_lock_irqsave(&chsc_page_lock, flags); memset(chsc_page, 0, PAGE_SIZE); @@ -895,8 +892,9 @@ int __chsc_do_secm(struct channel_subsystem *css, int enable) secm_area->request.code = 0x0016; secm_area->key = PAGE_DEFAULT_KEY >> 4; - secm_area->cub_addr1 = virt_to_dma32(css->cub_addr1); - secm_area->cub_addr2 = virt_to_dma32(css->cub_addr2); + + for (i = 0; i < CSS_NUM_CUB_PAGES; i++) + secm_area->cub[i] = (__force dma64_t)virt_to_dma32(css->cub[i]); secm_area->operation_code = enable ? 0 : 1; @@ -922,19 +920,38 @@ out: return ret; } +static int cub_alloc(struct channel_subsystem *css) +{ + int i; + + for (i = 0; i < CSS_NUM_CUB_PAGES; i++) { + css->cub[i] = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); + if (!css->cub[i]) + return -ENOMEM; + } + + return 0; +} + +static void cub_free(struct channel_subsystem *css) +{ + int i; + + for (i = 0; i < CSS_NUM_CUB_PAGES; i++) { + free_page((unsigned long)css->cub[i]); + css->cub[i] = NULL; + } +} + int chsc_secm(struct channel_subsystem *css, int enable) { int ret; if (enable && !css->cm_enabled) { - css->cub_addr1 = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); - css->cub_addr2 = (void *)get_zeroed_page(GFP_KERNEL | GFP_DMA); - if (!css->cub_addr1 || !css->cub_addr2) { - free_page((unsigned long)css->cub_addr1); - free_page((unsigned long)css->cub_addr2); - return -ENOMEM; - } + ret = cub_alloc(css); + if (ret) + goto out; } ret = __chsc_do_secm(css, enable); if (!ret) { @@ -948,10 +965,11 @@ chsc_secm(struct channel_subsystem *css, int enable) } else chsc_remove_cmg_attr(css); } - if (!css->cm_enabled) { - free_page((unsigned long)css->cub_addr1); - free_page((unsigned long)css->cub_addr2); - } + +out: + if (!css->cm_enabled) + cub_free(css); + return ret; } diff --git a/drivers/s390/cio/css.h b/drivers/s390/cio/css.h index ea5550554297..aca11dacb224 100644 --- a/drivers/s390/cio/css.h +++ b/drivers/s390/cio/css.h @@ -34,6 +34,13 @@ #define SNID_STATE3_MULTI_PATH 1 #define SNID_STATE3_SINGLE_PATH 0 +/* + * Miscellaneous constants + */ + +#define CSS_NUM_CUB_PAGES 2 +#define CSS_CUES_PER_PAGE 128 + /* * Conditions used to specify which subchannels need evaluation */ @@ -122,8 +129,7 @@ struct channel_subsystem { struct mutex mutex; /* channel measurement related */ int cm_enabled; - void *cub_addr1; - void *cub_addr2; + void *cub[CSS_NUM_CUB_PAGES]; /* for orphaned ccw devices */ struct subchannel *pseudo_subchannel; }; From b4691baaeef07bdc4c3524a0702d7dd6899610b4 Mon Sep 17 00:00:00 2001 From: Peter Oberparleiter Date: Tue, 26 Mar 2024 17:03:21 +0100 Subject: [PATCH 397/969] s390/cio: simplify measurement attribute registration Use attribute groups to simplify registration, removal and extension of measurement related sysfs attributes. Reviewed-by: Vineeth Vijayan Acked-by: Heiko Carstens Signed-off-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev --- drivers/s390/cio/chp.c | 49 +++++++++++++----------------------------- 1 file changed, 15 insertions(+), 34 deletions(-) diff --git a/drivers/s390/cio/chp.c b/drivers/s390/cio/chp.c index 0edb6dd0f105..e4a9ce5cacbb 100644 --- a/drivers/s390/cio/chp.c +++ b/drivers/s390/cio/chp.c @@ -127,10 +127,9 @@ static int s390_vary_chpid(struct chp_id chpid, int on) /* * Channel measurement related functions */ -static ssize_t chp_measurement_chars_read(struct file *filp, - struct kobject *kobj, - struct bin_attribute *bin_attr, - char *buf, loff_t off, size_t count) +static ssize_t measurement_chars_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) { struct channel_path *chp; struct device *device; @@ -143,15 +142,7 @@ static ssize_t chp_measurement_chars_read(struct file *filp, return memory_read_from_buffer(buf, count, &off, &chp->cmg_chars, sizeof(chp->cmg_chars)); } - -static const struct bin_attribute chp_measurement_chars_attr = { - .attr = { - .name = "measurement_chars", - .mode = S_IRUSR, - }, - .size = sizeof(struct cmg_chars), - .read = chp_measurement_chars_read, -}; +static BIN_ATTR_ADMIN_RO(measurement_chars, sizeof(struct cmg_chars)); static void chp_measurement_copy_block(struct cmg_entry *buf, struct channel_subsystem *css, @@ -175,9 +166,9 @@ static void chp_measurement_copy_block(struct cmg_entry *buf, } while (reference_buf.values[0] != buf->values[0]); } -static ssize_t chp_measurement_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *bin_attr, - char *buf, loff_t off, size_t count) +static ssize_t measurement_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) { struct channel_path *chp; struct channel_subsystem *css; @@ -197,33 +188,23 @@ static ssize_t chp_measurement_read(struct file *filp, struct kobject *kobj, count = size; return count; } +static BIN_ATTR_ADMIN_RO(measurement, sizeof(struct cmg_entry)); -static const struct bin_attribute chp_measurement_attr = { - .attr = { - .name = "measurement", - .mode = S_IRUSR, - }, - .size = sizeof(struct cmg_entry), - .read = chp_measurement_read, +static struct bin_attribute *measurement_attrs[] = { + &bin_attr_measurement_chars, + &bin_attr_measurement, + NULL, }; +BIN_ATTRIBUTE_GROUPS(measurement); void chp_remove_cmg_attr(struct channel_path *chp) { - device_remove_bin_file(&chp->dev, &chp_measurement_chars_attr); - device_remove_bin_file(&chp->dev, &chp_measurement_attr); + device_remove_groups(&chp->dev, measurement_groups); } int chp_add_cmg_attr(struct channel_path *chp) { - int ret; - - ret = device_create_bin_file(&chp->dev, &chp_measurement_chars_attr); - if (ret) - return ret; - ret = device_create_bin_file(&chp->dev, &chp_measurement_attr); - if (ret) - device_remove_bin_file(&chp->dev, &chp_measurement_chars_attr); - return ret; + return device_add_groups(&chp->dev, measurement_groups); } /* From 2dc8903af775ecd51e42c0a2e7afa0e98d1bde45 Mon Sep 17 00:00:00 2001 From: Peter Oberparleiter Date: Tue, 26 Mar 2024 17:03:22 +0100 Subject: [PATCH 398/969] s390/cio: export extended channel-path-measurement data Add a per-CHPID binary sysfs attribute named "ext_measurement" that provides access to extended channel-path-measurement data for the associated channel path. Note that while not all channel-paths provide extended measurement data this attribute is created unconditionally for all channel paths because channel-path measurement capabilities might change during run-time. Reading from the attribute will only return data for channel-paths that support extended measurement data. Example: $ echo 1 > /sys/devices/css0/cm_enable $ xxd /sys/devices/css0/chp0.32/ext_measurement 00000000: 53e0 8002 0000 0095 0000 0000 59cc e034 S...........Y..4 00000010: 38b8 cc45 0000 0000 0000 0000 3e24 fe94 8..E........>$.. 00000020: 0000 0000 0000 0000 0000 0000 0000 0000 ................ 00000030: 0000 0000 0000 0000 0000 0000 0000 0000 ................ Reviewed-by: Vineeth Vijayan Tested-by: Vineeth Vijayan Acked-by: Heiko Carstens Signed-off-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev --- drivers/s390/cio/chp.c | 76 +++++++++++++++++++++++------------------ drivers/s390/cio/chp.h | 1 + drivers/s390/cio/chsc.c | 24 +++++++++++-- drivers/s390/cio/chsc.h | 5 +++ drivers/s390/cio/css.h | 3 ++ 5 files changed, 73 insertions(+), 36 deletions(-) diff --git a/drivers/s390/cio/chp.c b/drivers/s390/cio/chp.c index e4a9ce5cacbb..fd7d34ed6ea9 100644 --- a/drivers/s390/cio/chp.c +++ b/drivers/s390/cio/chp.c @@ -144,55 +144,65 @@ static ssize_t measurement_chars_read(struct file *filp, struct kobject *kobj, } static BIN_ATTR_ADMIN_RO(measurement_chars, sizeof(struct cmg_chars)); -static void chp_measurement_copy_block(struct cmg_entry *buf, - struct channel_subsystem *css, - struct chp_id chpid) +static ssize_t chp_measurement_copy_block(void *buf, loff_t off, size_t count, + struct kobject *kobj, bool extended) { - void *area; - struct cmg_entry *entry, reference_buf; - int idx; + struct channel_path *chp; + struct channel_subsystem *css; + struct device *device; + unsigned int size; + void *area, *entry; + int id, idx; - if (chpid.id < CSS_CUES_PER_PAGE) { - area = css->cub[0]; - idx = chpid.id; + device = kobj_to_dev(kobj); + chp = to_channelpath(device); + css = to_css(chp->dev.parent); + id = chp->chpid.id; + + if (extended) { + /* Check if extended measurement data is available. */ + if (!chp->extended) + return 0; + + size = sizeof(struct cmg_ext_entry); + area = css->ecub[id / CSS_ECUES_PER_PAGE]; + idx = id % CSS_ECUES_PER_PAGE; } else { - area = css->cub[1]; - idx = chpid.id - CSS_CUES_PER_PAGE; + size = sizeof(struct cmg_entry); + area = css->cub[id / CSS_CUES_PER_PAGE]; + idx = id % CSS_CUES_PER_PAGE; } - entry = area + (idx * sizeof(struct cmg_entry)); - do { - memcpy(buf, entry, sizeof(*entry)); - memcpy(&reference_buf, entry, sizeof(*entry)); - } while (reference_buf.values[0] != buf->values[0]); + entry = area + (idx * size); + + /* Only allow single reads. */ + if (off || count < size) + return 0; + + memcpy(buf, entry, size); + + return size; } static ssize_t measurement_read(struct file *filp, struct kobject *kobj, struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { - struct channel_path *chp; - struct channel_subsystem *css; - struct device *device; - unsigned int size; - - device = kobj_to_dev(kobj); - chp = to_channelpath(device); - css = to_css(chp->dev.parent); - - size = sizeof(struct cmg_entry); - - /* Only allow single reads. */ - if (off || count < size) - return 0; - chp_measurement_copy_block((struct cmg_entry *)buf, css, chp->chpid); - count = size; - return count; + return chp_measurement_copy_block(buf, off, count, kobj, false); } static BIN_ATTR_ADMIN_RO(measurement, sizeof(struct cmg_entry)); +static ssize_t ext_measurement_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + return chp_measurement_copy_block(buf, off, count, kobj, true); +} +static BIN_ATTR_ADMIN_RO(ext_measurement, sizeof(struct cmg_ext_entry)); + static struct bin_attribute *measurement_attrs[] = { &bin_attr_measurement_chars, &bin_attr_measurement, + &bin_attr_ext_measurement, NULL, }; BIN_ATTRIBUTE_GROUPS(measurement); diff --git a/drivers/s390/cio/chp.h b/drivers/s390/cio/chp.h index 7ee9eba0abcb..1241033ccd62 100644 --- a/drivers/s390/cio/chp.h +++ b/drivers/s390/cio/chp.h @@ -51,6 +51,7 @@ struct channel_path { /* Channel-measurement related stuff: */ int cmg; int shared; + int extended; struct cmg_chars cmg_chars; }; diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c index 3344fa996ec4..f2f4c7e19048 100644 --- a/drivers/s390/cio/chsc.c +++ b/drivers/s390/cio/chsc.c @@ -871,11 +871,14 @@ int __chsc_do_secm(struct channel_subsystem *css, int enable) struct { struct chsc_header request; u32 operation_code : 2; - u32 : 30; + u32 : 1; + u32 e : 1; + u32 : 28; u32 key : 4; u32 : 28; dma64_t cub[CSS_NUM_CUB_PAGES]; - u32 reserved[13]; + dma64_t ecub[CSS_NUM_ECUB_PAGES]; + u32 reserved[5]; struct chsc_header response; u32 status : 8; u32 : 4; @@ -892,9 +895,12 @@ int __chsc_do_secm(struct channel_subsystem *css, int enable) secm_area->request.code = 0x0016; secm_area->key = PAGE_DEFAULT_KEY >> 4; + secm_area->e = 1; for (i = 0; i < CSS_NUM_CUB_PAGES; i++) secm_area->cub[i] = (__force dma64_t)virt_to_dma32(css->cub[i]); + for (i = 0; i < CSS_NUM_ECUB_PAGES; i++) + secm_area->ecub[i] = virt_to_dma64(css->ecub[i]); secm_area->operation_code = enable ? 0 : 1; @@ -929,6 +935,11 @@ static int cub_alloc(struct channel_subsystem *css) if (!css->cub[i]) return -ENOMEM; } + for (i = 0; i < CSS_NUM_ECUB_PAGES; i++) { + css->ecub[i] = (void *)get_zeroed_page(GFP_KERNEL); + if (!css->ecub[i]) + return -ENOMEM; + } return 0; } @@ -941,6 +952,10 @@ static void cub_free(struct channel_subsystem *css) free_page((unsigned long)css->cub[i]); css->cub[i] = NULL; } + for (i = 0; i < CSS_NUM_ECUB_PAGES; i++) { + free_page((unsigned long)css->ecub[i]); + css->ecub[i] = NULL; + } } int @@ -1067,7 +1082,8 @@ int chsc_get_channel_measurement_chars(struct channel_path *chp) u32 zeroes2; u32 not_valid : 1; u32 shared : 1; - u32 : 22; + u32 extended : 1; + u32 : 21; u32 chpid : 8; u32 cmcv : 5; u32 : 11; @@ -1079,6 +1095,7 @@ int chsc_get_channel_measurement_chars(struct channel_path *chp) chp->shared = -1; chp->cmg = -1; + chp->extended = 0; if (!css_chsc_characteristics.scmc || !css_chsc_characteristics.secm) return -EINVAL; @@ -1108,6 +1125,7 @@ int chsc_get_channel_measurement_chars(struct channel_path *chp) chp->cmg = scmc_area->cmg; chp->shared = scmc_area->shared; + chp->extended = scmc_area->extended; if (chp->cmg != 2 && chp->cmg != 3) { /* No cmg-dependent data. */ goto out; diff --git a/drivers/s390/cio/chsc.h b/drivers/s390/cio/chsc.h index 03602295f335..24cd65dbc5a7 100644 --- a/drivers/s390/cio/chsc.h +++ b/drivers/s390/cio/chsc.h @@ -22,6 +22,11 @@ struct cmg_entry { u32 values[NR_MEASUREMENT_ENTRIES]; }; +#define NR_EXT_MEASUREMENT_ENTRIES 16 +struct cmg_ext_entry { + u32 values[NR_EXT_MEASUREMENT_ENTRIES]; +}; + struct channel_path_desc_fmt1 { u8 flags; u8 lsn; diff --git a/drivers/s390/cio/css.h b/drivers/s390/cio/css.h index aca11dacb224..c2b175592bb7 100644 --- a/drivers/s390/cio/css.h +++ b/drivers/s390/cio/css.h @@ -40,6 +40,8 @@ #define CSS_NUM_CUB_PAGES 2 #define CSS_CUES_PER_PAGE 128 +#define CSS_NUM_ECUB_PAGES 4 +#define CSS_ECUES_PER_PAGE 64 /* * Conditions used to specify which subchannels need evaluation @@ -130,6 +132,7 @@ struct channel_subsystem { /* channel measurement related */ int cm_enabled; void *cub[CSS_NUM_CUB_PAGES]; + void *ecub[CSS_NUM_ECUB_PAGES]; /* for orphaned ccw devices */ struct subchannel *pseudo_subchannel; }; From 5e6bb10ee523d85d688aacaa13405d651ad16214 Mon Sep 17 00:00:00 2001 From: Peter Oberparleiter Date: Tue, 26 Mar 2024 17:03:23 +0100 Subject: [PATCH 399/969] s390/cio: export measurement data for all CMGs A channel-path's channel-measurement-group value (CMG) determines the format of associated measurement data and characteristics blocks. Both blocks are of fixed size and contain a generic and CMG-dependent part. Currently CIO exports these data blocks via sysfs only for a specific list of CMGs even though the kernel itself does not interpret CMG-dependent data. Change CIO to export measurement data and characteristics for all CMGs. This enables supporting new CMG data formats in userspace without the need for kernel changes. Reviewed-by: Vineeth Vijayan Acked-by: Heiko Carstens Signed-off-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev --- drivers/s390/cio/chsc.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c index f2f4c7e19048..bfc663889fbd 100644 --- a/drivers/s390/cio/chsc.c +++ b/drivers/s390/cio/chsc.c @@ -1126,10 +1126,6 @@ int chsc_get_channel_measurement_chars(struct channel_path *chp) chp->cmg = scmc_area->cmg; chp->shared = scmc_area->shared; chp->extended = scmc_area->extended; - if (chp->cmg != 2 && chp->cmg != 3) { - /* No cmg-dependent data. */ - goto out; - } chsc_initialize_cmg_chars(chp, scmc_area->cmcv, (struct cmg_chars *) &scmc_area->data); out: From 0f987e6caa3c93f36e277624234880459848fa34 Mon Sep 17 00:00:00 2001 From: Peter Oberparleiter Date: Tue, 26 Mar 2024 17:03:24 +0100 Subject: [PATCH 400/969] s390/cio: export CHPID operating speed Add a per-CHPID sysfs attribute named "speed_bps" that provides the operating speed of the associated channel path in bits per second, or 0 if the operating speed is not available. Example: $ cat /sys/devices/css0/chp0.32/speed_bps 32G Reviewed-by: Vineeth Vijayan Acked-by: Heiko Carstens Signed-off-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev --- drivers/s390/cio/chp.c | 30 ++++++++++++++++++++++++++++++ drivers/s390/cio/chp.h | 1 + drivers/s390/cio/chsc.c | 20 ++++++++++++++++++-- 3 files changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/s390/cio/chp.c b/drivers/s390/cio/chp.c index fd7d34ed6ea9..a07bbecba61c 100644 --- a/drivers/s390/cio/chp.c +++ b/drivers/s390/cio/chp.c @@ -392,6 +392,35 @@ static ssize_t chp_esc_show(struct device *dev, } static DEVICE_ATTR(esc, 0444, chp_esc_show, NULL); +static char apply_max_suffix(unsigned long *value, unsigned long base) +{ + static char suffixes[] = { 0, 'K', 'M', 'G', 'T' }; + int i; + + for (i = 0; i < ARRAY_SIZE(suffixes) - 1; i++) { + if (*value < base || *value % base != 0) + break; + *value /= base; + } + + return suffixes[i]; +} + +static ssize_t speed_bps_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct channel_path *chp = to_channelpath(dev); + unsigned long speed = chp->speed; + char suffix; + + suffix = apply_max_suffix(&speed, 1000); + + return suffix ? sysfs_emit(buf, "%lu%c\n", speed, suffix) : + sysfs_emit(buf, "%lu\n", speed); +} + +static DEVICE_ATTR_RO(speed_bps); + static ssize_t util_string_read(struct file *filp, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t off, size_t count) @@ -423,6 +452,7 @@ static struct attribute *chp_attrs[] = { &dev_attr_chid.attr, &dev_attr_chid_external.attr, &dev_attr_esc.attr, + &dev_attr_speed_bps.attr, NULL, }; static struct attribute_group chp_attr_group = { diff --git a/drivers/s390/cio/chp.h b/drivers/s390/cio/chp.h index 1241033ccd62..a15324a43aa3 100644 --- a/drivers/s390/cio/chp.h +++ b/drivers/s390/cio/chp.h @@ -52,6 +52,7 @@ struct channel_path { int cmg; int shared; int extended; + unsigned long speed; struct cmg_chars cmg_chars; }; diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c index bfc663889fbd..dcc1e1c34ca2 100644 --- a/drivers/s390/cio/chsc.c +++ b/drivers/s390/cio/chsc.c @@ -1066,6 +1066,18 @@ chsc_initialize_cmg_chars(struct channel_path *chp, u8 cmcv, } } +static unsigned long scmc_get_speed(u32 s, u32 p) +{ + unsigned long speed = s; + + if (!p) + p = 8; + while (p--) + speed *= 10; + + return speed; +} + int chsc_get_channel_measurement_chars(struct channel_path *chp) { unsigned long flags; @@ -1086,16 +1098,19 @@ int chsc_get_channel_measurement_chars(struct channel_path *chp) u32 : 21; u32 chpid : 8; u32 cmcv : 5; - u32 : 11; + u32 : 7; + u32 cmgp : 4; u32 cmgq : 8; u32 cmg : 8; - u32 zeroes3; + u32 : 16; + u32 cmgs : 16; u32 data[NR_MEASUREMENT_CHARS]; } *scmc_area; chp->shared = -1; chp->cmg = -1; chp->extended = 0; + chp->speed = 0; if (!css_chsc_characteristics.scmc || !css_chsc_characteristics.secm) return -EINVAL; @@ -1126,6 +1141,7 @@ int chsc_get_channel_measurement_chars(struct channel_path *chp) chp->cmg = scmc_area->cmg; chp->shared = scmc_area->shared; chp->extended = scmc_area->extended; + chp->speed = scmc_get_speed(scmc_area->cmgs, scmc_area->cmgp); chsc_initialize_cmg_chars(chp, scmc_area->cmcv, (struct cmg_chars *) &scmc_area->data); out: From 8692a24d0fae19f674d51726d179ad04ba95d958 Mon Sep 17 00:00:00 2001 From: Peter Oberparleiter Date: Tue, 26 Mar 2024 17:04:56 +0100 Subject: [PATCH 401/969] s390/cio: fix tracepoint subchannel type field The subchannel-type field "st" of s390_cio_stsch and s390_cio_msch tracepoints is incorrectly filled with the subchannel-enabled SCHIB value "ena". Fix this by assigning the correct value. Fixes: d1de8633d96a ("s390 cio: Rewrite trace point class s390_class_schib") Reviewed-by: Heiko Carstens Signed-off-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev --- drivers/s390/cio/trace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/s390/cio/trace.h b/drivers/s390/cio/trace.h index 86993de25345..a4c5c6736b31 100644 --- a/drivers/s390/cio/trace.h +++ b/drivers/s390/cio/trace.h @@ -50,7 +50,7 @@ DECLARE_EVENT_CLASS(s390_class_schib, __entry->devno = schib->pmcw.dev; __entry->schib = *schib; __entry->pmcw_ena = schib->pmcw.ena; - __entry->pmcw_st = schib->pmcw.ena; + __entry->pmcw_st = schib->pmcw.st; __entry->pmcw_dnv = schib->pmcw.dnv; __entry->pmcw_dev = schib->pmcw.dev; __entry->pmcw_lpm = schib->pmcw.lpm; From b37146b5a555dd871cb0805446826ab2fc8d285a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:35 +0200 Subject: [PATCH 402/969] arm64: dts: rockchip: add USB3 to rk3588-evb1 Add support for the board's USB3 connectors. It has 1x USB Type-A and 1x USB Type-C. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-9-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-evb1-v10.dts | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 56c019b25fa8..7be2190244ba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "rk3588.dtsi" / { @@ -159,6 +160,18 @@ vin-supply = <&avcc_1v8_s0>; }; + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -290,6 +303,59 @@ &i2c2 { status = "okay"; + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "source"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; @@ -416,6 +482,16 @@ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb-typec { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &pwm2 { @@ -1055,6 +1131,22 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -1093,3 +1185,58 @@ &usb_host1_ohci { status = "okay"; }; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + /* + * USBDP PHY1 is wired to a female USB3 Type-A connector. Additionally + * the differential pairs 2+3 and the aux channel are wired to a RTD2166, + * which converts the DP signal into VGA. This is exposed on the + * board via a female VGA connector. + */ + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; From af7ec140ddc1815bc462109792d95bcad05cfbc4 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:36 +0200 Subject: [PATCH 403/969] arm64: dts: rockchip: add upper USB3 port to rock-5a Enable full support (XHCI, EHCI, OHCI) for the upper USB3 port from Radxa Rock 5 Model A. The lower one is already supported. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-10-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-rock-5a.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 00afb90d4eb1..b8ca3ee4c89a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -697,6 +697,14 @@ }; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -720,6 +728,11 @@ status = "okay"; }; +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = <2 3>; +}; + &usb_host0_ehci { status = "okay"; pinctrl-names = "default"; @@ -730,6 +743,11 @@ status = "okay"; }; +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; From 494532921aacb496529d544fedfdb3a7b43dfef0 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:37 +0200 Subject: [PATCH 404/969] arm64: dts: rockchip: add lower USB3 port to rock-5b Enable full support (XHCI, EHCI, OHCI) for the lower USB3 port from Radxa Rock 5 Model B. The upper one is already supported. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-11-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index d6bf2ee07e87..b67b6c50d0dc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -747,6 +747,14 @@ status = "okay"; }; +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -766,6 +774,10 @@ status = "okay"; }; +&usbdp_phy1 { + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; @@ -782,6 +794,11 @@ status = "okay"; }; +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + &usb_host2_xhci { status = "okay"; }; From 7cdf7efefc02189cf9a228d4c5c4253d273e9b1a Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 9 Apr 2024 00:50:30 +0200 Subject: [PATCH 405/969] arm64: defconfig: enable Rockchip Samsung USBDP PHY The USBDP Phy is used by RK3588 to handle the Dual-Role USB3 controllers. The Phy also supports Displayport Alt-Mode, but the necessary DRM driver has not yet been merged. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20240408225109.128953-4-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d30e234803c2..c475028be467 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1519,6 +1519,7 @@ CONFIG_PHY_ROCKCHIP_PCIE=m CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y CONFIG_PHY_ROCKCHIP_TYPEC=y +CONFIG_PHY_ROCKCHIP_USBDP=m CONFIG_PHY_SAMSUNG_UFS=y CONFIG_PHY_UNIPHIER_USB2=y CONFIG_PHY_UNIPHIER_USB3=y From 4627297653db327b4afbc0be947f98b046647369 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:40 +0200 Subject: [PATCH 406/969] arm64: dts: hisilicon: hip05: move non-MMIO node out of soc Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: hip05.dtsi:301.30-305.5: Warning (simple_bus_reg): /soc/refclk200mhz: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 65ddc0698f82..d0912ca5f237 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -279,6 +279,12 @@ }; }; + refclk200mhz: refclk200mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -298,12 +304,6 @@ #size-cells = <2>; ranges; - refclk200mhz: refclk200mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - uart0: serial@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; From 3a391d21be02552deaae1c845ff1121b873fd480 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:41 +0200 Subject: [PATCH 407/969] arm64: dts: hisilicon: hip05-d02: correct local-bus unit addresses Correct local-bus children unit addresses to fix dtc W=1 warnings: hip05-d02.dts:57.16-76.4: Warning (simple_bus_reg): /soc/local-bus@80380000/nor-flash@0,0: simple-bus unit address format error, expected "0" hip05-d02.dts:78.11-81.4: Warning (simple_bus_reg): /soc/local-bus@80380000/cpld@1,0: simple-bus unit address format error, expected "100000000" Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index c4eaebbb448f..b7792d443189 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -54,7 +54,7 @@ ranges = <0 0 0x0 0x90000000 0x08000000>, <1 0 0x0 0x98000000 0x08000000>; - nor-flash@0,0 { + nor-flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "numonyx,js28f00a", "cfi-flash"; @@ -75,7 +75,7 @@ }; }; - cpld@1,0 { + cpld@100000000 { compatible = "hisilicon,hip05-cpld"; reg = <1 0x0 0x100>; }; From 4889c8e01112429216ae63631300b81f6e02ced8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:42 +0200 Subject: [PATCH 408/969] arm64: dts: hisilicon: hip06: move non-MMIO node out of soc Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: hip06.dtsi:377.18-381.5: Warning (simple_bus_reg): /soc/refclk: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 84 ++++++++++++------------ 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index f46c33d10750..249ca3b4b703 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -258,6 +258,48 @@ }; }; + eth2: ethernet-0 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet-1 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth0: ethernet-4 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet-5 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + refclk: refclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -374,12 +416,6 @@ }; }; - refclk: refclk { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - #clock-cells = <0>; - }; - usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; @@ -570,42 +606,6 @@ }; }; - eth0: ethernet-4 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet-5 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet-0 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet-1 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - sas0: sas@c3000000 { compatible = "hisilicon,hip06-sas-v2"; reg = <0 0xc3000000 0 0x10000>; From a2c4daf44f4217f2cf4e876babea58e258976157 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:43 +0200 Subject: [PATCH 409/969] arm64: dts: hisilicon: hip06: correct unit addresses Correct dsa and pcie unit addresses to fix dtc W=1 warnings: hip06.dtsi:439.23-571.5: Warning (simple_bus_reg): /soc/dsa@c7000000: simple-bus unit address format error, expected "c5000000" Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 249ca3b4b703..3d7285e6700e 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -472,7 +472,7 @@ }; }; - dsaf0: dsa@c7000000 { + dsaf0: dsa@c5000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; @@ -733,7 +733,7 @@ status = "disabled"; }; - pcie0: pcie@a0090000 { + pcie0: pcie@b0000000 { compatible = "hisilicon,hip06-pcie-ecam"; reg = <0 0xb0000000 0 0x2000000>, <0 0xa0090000 0 0x10000>; From 4b792989c64f008d74a8a071280752660bb99d27 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 14 Apr 2024 15:20:52 +0200 Subject: [PATCH 410/969] arm64: defconfig: build snd_bcm2835 as module Recently the VCHIQ driver which provides a kernel interface to the BCM2835 VideoCore made a decent progress in staging. But the build coverage is currently limited to bcm2835_defconfig (ARM 32 bit). So build the most valueable driver which uses VCHIQ and enable cinch audio support for Raspberry Pi on arm64. Signed-off-by: Stefan Wahren Link: https://lore.kernel.org/r/20240414132052.11811-1-wahrenst@gmx.net Signed-off-by: Florian Fainelli --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..db51ec37dd22 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1217,6 +1217,7 @@ CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_MAX96712=m CONFIG_VIDEO_MESON_VDEC=m +CONFIG_SND_BCM2835=m CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y From 412f2224b3b63f3d553aa82b54f762245acd4398 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 9 Apr 2024 09:33:28 +0200 Subject: [PATCH 411/969] arm64: dts: renesas: s4sk: Fix ethernet0 alias U-Boot uses "ethernet0", not "eth0". While at it, fix nearby whitespace errors (TAB instead of space before equal sign). Fixes: 93be50c7ff8e8087 ("arm64: dts: renesas: Add R-Car S4 Starter Kit support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/2f62c29e4222387a95ebadc65ba90a0cdea9b78c.1712647914.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts index abfda5c6ca16..bc65a7b4d999 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f4-s4sk.dts @@ -14,9 +14,9 @@ compatible = "renesas,s4sk", "renesas,r8a779f4", "renesas,r8a779f0"; aliases { - serial0 = &hscif0; - serial1 = &hscif1; - eth0 = &rswitch; + serial0 = &hscif0; + serial1 = &hscif1; + ethernet0 = &rswitch; }; chosen { From 058e87782c91696020bdb0aa28ddf77d89aed266 Mon Sep 17 00:00:00 2001 From: "Uladzislau Rezki (Sony)" Date: Wed, 14 Feb 2024 14:45:53 -0800 Subject: [PATCH 412/969] rcu: Update lockdep while in RCU read-side critical section With Ankur's lazy-/auto-preemption patches applied and with a lazy-preemptible kernel in combination with a non-preemptible RCU, lockdep sometimes complains about context switches within RCU read-side critical sections. This is a false positive due to rcu_read_unlock() updating lockdep state too late: __release(RCU); __rcu_read_unlock(); // Context switch here results in lockdep false positive!!! rcu_lock_release(&rcu_lock_map); /* Keep acq info for rls diags. */ Although this complaint could also happen with preemptible RCU in a preemptible kernel, the odds of that happening aer quite low. In constrast, with non-preemptible RCU, a long critical section has a high probability of performing a context switch from the preempt_enable() in __rcu_read_unlock(). The fix is straightforward, just move the rcu_lock_release() within rcu_read_unlock() to obtain the reverse order from that of rcu_read_lock(): rcu_lock_release(&rcu_lock_map); /* Keep acq info for rls diags. */ __release(RCU); __rcu_read_unlock(); This commit makes this change. Co-developed-by: Frederic Weisbecker Signed-off-by: Frederic Weisbecker Co-developed-by: Joel Fernandes (Google) Signed-off-by: Joel Fernandes (Google) Co-developed-by: Boqun Feng Signed-off-by: Boqun Feng Signed-off-by: Uladzislau Rezki (Sony) Reviewed-by: Paul E. McKenney Cc: Ankur Arora Cc: Thomas Gleixner --- include/linux/rcupdate.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 17d7ed5f3ae6..2c54750e36a0 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -809,9 +809,9 @@ static inline void rcu_read_unlock(void) { RCU_LOCKDEP_WARN(!rcu_is_watching(), "rcu_read_unlock() used illegally while idle"); + rcu_lock_release(&rcu_lock_map); /* Keep acq info for rls diags. */ __release(RCU); __rcu_read_unlock(); - rcu_lock_release(&rcu_lock_map); /* Keep acq info for rls diags. */ } /** From c1ec7c158090ab968ab9022a9f67e7d88d66ee61 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 14 Feb 2024 15:33:55 -0800 Subject: [PATCH 413/969] rcu: Make TINY_RCU depend on !PREEMPT_RCU rather than !PREEMPTION Right now, TINY_RCU depends on (!PREEMPTION && !SMP), which has served the kernel well for many years due to the fact that PREEMPT_RCU is normally a synonym for PREEMPTION. But with the advent of lazy preemption, it will be possible to have non-preemptible RCU in a preemptible kernel, so that kernels could be built with PREEMPT_RCU=n and PREEMPTION=y. This commit therefore makes TINY_RCU depend on (!PREEMPT_RCU && !SMP), thus allowing for a non-preemptible RCU in preemptible kernels. Signed-off-by: Paul E. McKenney Cc: Ankur Arora Cc: Thomas Gleixner Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rcu/Kconfig b/kernel/rcu/Kconfig index e7d2dd267593..7dca0138260c 100644 --- a/kernel/rcu/Kconfig +++ b/kernel/rcu/Kconfig @@ -31,7 +31,7 @@ config PREEMPT_RCU config TINY_RCU bool - default y if !PREEMPTION && !SMP + default y if !PREEMPT_RCU && !SMP help This option selects the RCU implementation that is designed for UP systems from which real-time response From 65b4a59557f6fb5d4355093ad5a2c1bd5598ee41 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 15 Feb 2024 09:04:30 -0800 Subject: [PATCH 414/969] srcu: Make Tiny SRCU explicitly disable preemption Because Tiny SRCU is used only in kernels built with either CONFIG_PREEMPT_NONE=y or CONFIG_PREEMPT_VOLUNTARY=y, there has not been any need for TINY SRCU to explicitly disable preemption. However, the prospect of lazy preemption changes that, and the lazy-preemption patches do result in rcutorture runs finding both too-short grace periods and grace-period hangs for Tiny SRCU. This commit therefore adds the needed preempt_disable() and preempt_enable() calls to Tiny SRCU. Signed-off-by: Paul E. McKenney Cc: Ankur Arora Cc: Thomas Gleixner Signed-off-by: Uladzislau Rezki (Sony) --- include/linux/srcutiny.h | 2 ++ kernel/rcu/srcutiny.c | 31 ++++++++++++++++++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/include/linux/srcutiny.h b/include/linux/srcutiny.h index 447133171d95..4d96bbdb45f0 100644 --- a/include/linux/srcutiny.h +++ b/include/linux/srcutiny.h @@ -64,8 +64,10 @@ static inline int __srcu_read_lock(struct srcu_struct *ssp) { int idx; + preempt_disable(); // Needed for PREEMPT_AUTO idx = ((READ_ONCE(ssp->srcu_idx) + 1) & 0x2) >> 1; WRITE_ONCE(ssp->srcu_lock_nesting[idx], READ_ONCE(ssp->srcu_lock_nesting[idx]) + 1); + preempt_enable(); return idx; } diff --git a/kernel/rcu/srcutiny.c b/kernel/rcu/srcutiny.c index c38e5933a5d6..5afd5cf494db 100644 --- a/kernel/rcu/srcutiny.c +++ b/kernel/rcu/srcutiny.c @@ -96,9 +96,12 @@ EXPORT_SYMBOL_GPL(cleanup_srcu_struct); */ void __srcu_read_unlock(struct srcu_struct *ssp, int idx) { - int newval = READ_ONCE(ssp->srcu_lock_nesting[idx]) - 1; + int newval; + preempt_disable(); // Needed for PREEMPT_AUTO + newval = READ_ONCE(ssp->srcu_lock_nesting[idx]) - 1; WRITE_ONCE(ssp->srcu_lock_nesting[idx], newval); + preempt_enable(); if (!newval && READ_ONCE(ssp->srcu_gp_waiting) && in_task()) swake_up_one(&ssp->srcu_wq); } @@ -117,8 +120,11 @@ void srcu_drive_gp(struct work_struct *wp) struct srcu_struct *ssp; ssp = container_of(wp, struct srcu_struct, srcu_work); - if (ssp->srcu_gp_running || ULONG_CMP_GE(ssp->srcu_idx, READ_ONCE(ssp->srcu_idx_max))) + preempt_disable(); // Needed for PREEMPT_AUTO + if (ssp->srcu_gp_running || ULONG_CMP_GE(ssp->srcu_idx, READ_ONCE(ssp->srcu_idx_max))) { return; /* Already running or nothing to do. */ + preempt_enable(); + } /* Remove recently arrived callbacks and wait for readers. */ WRITE_ONCE(ssp->srcu_gp_running, true); @@ -130,9 +136,12 @@ void srcu_drive_gp(struct work_struct *wp) idx = (ssp->srcu_idx & 0x2) / 2; WRITE_ONCE(ssp->srcu_idx, ssp->srcu_idx + 1); WRITE_ONCE(ssp->srcu_gp_waiting, true); /* srcu_read_unlock() wakes! */ + preempt_enable(); swait_event_exclusive(ssp->srcu_wq, !READ_ONCE(ssp->srcu_lock_nesting[idx])); + preempt_disable(); // Needed for PREEMPT_AUTO WRITE_ONCE(ssp->srcu_gp_waiting, false); /* srcu_read_unlock() cheap. */ WRITE_ONCE(ssp->srcu_idx, ssp->srcu_idx + 1); + preempt_enable(); /* Invoke the callbacks we removed above. */ while (lh) { @@ -150,8 +159,11 @@ void srcu_drive_gp(struct work_struct *wp) * at interrupt level, but the ->srcu_gp_running checks will * straighten that out. */ + preempt_disable(); // Needed for PREEMPT_AUTO WRITE_ONCE(ssp->srcu_gp_running, false); - if (ULONG_CMP_LT(ssp->srcu_idx, READ_ONCE(ssp->srcu_idx_max))) + idx = ULONG_CMP_LT(ssp->srcu_idx, READ_ONCE(ssp->srcu_idx_max)); + preempt_enable(); + if (idx) schedule_work(&ssp->srcu_work); } EXPORT_SYMBOL_GPL(srcu_drive_gp); @@ -160,9 +172,12 @@ static void srcu_gp_start_if_needed(struct srcu_struct *ssp) { unsigned long cookie; + preempt_disable(); // Needed for PREEMPT_AUTO cookie = get_state_synchronize_srcu(ssp); - if (ULONG_CMP_GE(READ_ONCE(ssp->srcu_idx_max), cookie)) + if (ULONG_CMP_GE(READ_ONCE(ssp->srcu_idx_max), cookie)) { + preempt_enable(); return; + } WRITE_ONCE(ssp->srcu_idx_max, cookie); if (!READ_ONCE(ssp->srcu_gp_running)) { if (likely(srcu_init_done)) @@ -170,6 +185,7 @@ static void srcu_gp_start_if_needed(struct srcu_struct *ssp) else if (list_empty(&ssp->srcu_work.entry)) list_add(&ssp->srcu_work.entry, &srcu_boot_list); } + preempt_enable(); } /* @@ -183,11 +199,13 @@ void call_srcu(struct srcu_struct *ssp, struct rcu_head *rhp, rhp->func = func; rhp->next = NULL; + preempt_disable(); // Needed for PREEMPT_AUTO local_irq_save(flags); *ssp->srcu_cb_tail = rhp; ssp->srcu_cb_tail = &rhp->next; local_irq_restore(flags); srcu_gp_start_if_needed(ssp); + preempt_enable(); } EXPORT_SYMBOL_GPL(call_srcu); @@ -241,9 +259,12 @@ EXPORT_SYMBOL_GPL(get_state_synchronize_srcu); */ unsigned long start_poll_synchronize_srcu(struct srcu_struct *ssp) { - unsigned long ret = get_state_synchronize_srcu(ssp); + unsigned long ret; + preempt_disable(); // Needed for PREEMPT_AUTO + ret = get_state_synchronize_srcu(ssp); srcu_gp_start_if_needed(ssp); + preempt_enable(); return ret; } EXPORT_SYMBOL_GPL(start_poll_synchronize_srcu); From 1b4e9fdf9ed489c779259734e0b47f408c7786f2 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 22 Feb 2024 10:09:19 -0800 Subject: [PATCH 415/969] rcu: Create NEED_TASKS_RCU to factor out enablement logic Currently, if a Kconfig option depends on TASKS_RCU, it conditionally does "select TASKS_RCU if PREEMPTION". This works, but requires any change in this enablement logic to be replicated across all such "select" clauses. This commit therefore creates a new NEED_TASKS_RCU Kconfig option so that the default value of TASKS_RCU can depend on a combination of this new option and any needed enablement logic, so that this logic is in one place. While in the area, also anticipate a likely future change by adding PREEMPT_AUTO to that logic. Signed-off-by: Paul E. McKenney Cc: Ankur Arora Cc: Thomas Gleixner Cc: Steven Rostedt Acked-by: Mark Rutland Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/Kconfig b/kernel/rcu/Kconfig index 7dca0138260c..3e079de0f5b4 100644 --- a/kernel/rcu/Kconfig +++ b/kernel/rcu/Kconfig @@ -85,9 +85,13 @@ config FORCE_TASKS_RCU idle, and user-mode execution as quiescent states. Not for manual selection in most cases. -config TASKS_RCU +config NEED_TASKS_RCU bool default n + +config TASKS_RCU + bool + default NEED_TASKS_RCU && (PREEMPTION || PREEMPT_AUTO) select IRQ_WORK config FORCE_TASKS_RUDE_RCU From 3dbd8652f87b81fccb766bddb985ef46a1502f04 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 1 Mar 2024 17:16:53 -0800 Subject: [PATCH 416/969] rcu: Remove redundant BH disabling in TINY_RCU The TINY_RCU rcu_process_callbacks() function is only ever invoked from a softirq handler, which means that BH is already disabled. This commit therefore removes the redundant local_bh_disable() and local_bh_ennable() from this function. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tiny.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/kernel/rcu/tiny.c b/kernel/rcu/tiny.c index 705c0d16850a..4470af926a34 100644 --- a/kernel/rcu/tiny.c +++ b/kernel/rcu/tiny.c @@ -130,9 +130,7 @@ static __latent_entropy void rcu_process_callbacks(struct softirq_action *unused next = list->next; prefetch(next); debug_rcu_head_unqueue(list); - local_bh_disable(); rcu_reclaim_tiny(list); - local_bh_enable(); list = next; } } From 11b8b378c58bdaf076c2724bee03157e3160af5f Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 4 Mar 2024 15:33:33 -0800 Subject: [PATCH 417/969] rcu: Make Tiny RCU explicitly disable preemption Because Tiny RCU is used only in kernels built with either CONFIG_PREEMPT_NONE=y or CONFIG_PREEMPT_VOLUNTARY=y, there has not been any need for TINY RCU to explicitly disable preemption. However, the prospect of lazy preemption changes that, and preemption means that the non-atomic increment in synchronize_rcu() can be preempted, with the possibility that one of the increments is lost. This could cause failures for users of the APIs that poll RCU grace periods. This commit therefore adds the needed preempt_disable() and preempt_enable() call to Tiny RCU. Signed-off-by: Paul E. McKenney Cc: Ankur Arora Cc: Thomas Gleixner Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tiny.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/rcu/tiny.c b/kernel/rcu/tiny.c index 4470af926a34..4402d6f5f857 100644 --- a/kernel/rcu/tiny.c +++ b/kernel/rcu/tiny.c @@ -153,7 +153,9 @@ void synchronize_rcu(void) lock_is_held(&rcu_lock_map) || lock_is_held(&rcu_sched_lock_map), "Illegal synchronize_rcu() in RCU read-side critical section"); + preempt_disable(); WRITE_ONCE(rcu_ctrlblk.gp_seq, rcu_ctrlblk.gp_seq + 2); + preempt_enable(); } EXPORT_SYMBOL_GPL(synchronize_rcu); From 62bb24c4b022b9ba9cf2e4a72f6cd8c3086f0cf8 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 7 Mar 2024 15:01:54 -0800 Subject: [PATCH 418/969] rcu: Remove redundant READ_ONCE() of rcu_state.gp_flags in tree.c Although it is functionally OK to do READ_ONCE() of a variable that cannot change, it is confusing and at best an accident waiting to happen. This commit therefore removes a number of READ_ONCE(rcu_state.gp_flags) instances from kernel/rcu/tree.c that are not needed due to updates to this field being excluded by virtue of holding the root rcu_node structure's ->lock. Reported-by: Linus Torvalds Closes: https://lore.kernel.org/lkml/4857c5ef-bd8f-4670-87ac-0600a1699d05@paulmck-laptop/T/#mccb23c2a4902da4d3c750165329f8de056903c58 Reported-by: Julia Lawall Closes: https://lore.kernel.org/lkml/4857c5ef-bd8f-4670-87ac-0600a1699d05@paulmck-laptop/T/#md1b5c026584f9c3c7b0fbc9240dd7de584597b73 Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 2795a1457acf..559f2d0d271f 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -1463,7 +1463,7 @@ static noinline_for_stack bool rcu_gp_init(void) WRITE_ONCE(rcu_state.gp_activity, jiffies); raw_spin_lock_irq_rcu_node(rnp); - if (!READ_ONCE(rcu_state.gp_flags)) { + if (!rcu_state.gp_flags) { /* Spurious wakeup, tell caller to go back to sleep. */ raw_spin_unlock_irq_rcu_node(rnp); return false; @@ -1648,8 +1648,7 @@ static void rcu_gp_fqs(bool first_time) /* Clear flag to prevent immediate re-entry. */ if (READ_ONCE(rcu_state.gp_flags) & RCU_GP_FLAG_FQS) { raw_spin_lock_irq_rcu_node(rnp); - WRITE_ONCE(rcu_state.gp_flags, - READ_ONCE(rcu_state.gp_flags) & ~RCU_GP_FLAG_FQS); + WRITE_ONCE(rcu_state.gp_flags, rcu_state.gp_flags & ~RCU_GP_FLAG_FQS); raw_spin_unlock_irq_rcu_node(rnp); } } @@ -1910,8 +1909,7 @@ static void rcu_report_qs_rsp(unsigned long flags) { raw_lockdep_assert_held_rcu_node(rcu_get_root()); WARN_ON_ONCE(!rcu_gp_in_progress()); - WRITE_ONCE(rcu_state.gp_flags, - READ_ONCE(rcu_state.gp_flags) | RCU_GP_FLAG_FQS); + WRITE_ONCE(rcu_state.gp_flags, rcu_state.gp_flags | RCU_GP_FLAG_FQS); raw_spin_unlock_irqrestore_rcu_node(rcu_get_root(), flags); rcu_gp_kthread_wake(); } @@ -2426,8 +2424,7 @@ void rcu_force_quiescent_state(void) raw_spin_unlock_irqrestore_rcu_node(rnp_old, flags); return; /* Someone beat us to it. */ } - WRITE_ONCE(rcu_state.gp_flags, - READ_ONCE(rcu_state.gp_flags) | RCU_GP_FLAG_FQS); + WRITE_ONCE(rcu_state.gp_flags, rcu_state.gp_flags | RCU_GP_FLAG_FQS); raw_spin_unlock_irqrestore_rcu_node(rnp_old, flags); rcu_gp_kthread_wake(); } From c90b9e49782424623e0006abbcab98f835c1f1d8 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 7 Mar 2024 15:06:19 -0800 Subject: [PATCH 419/969] rcu: Bring diagnostic read of rcu_state.gp_flags into alignment This commit adds READ_ONCE() to a lockless diagnostic read from rcu_state.gp_flags to avoid giving the compiler any chance whatsoever of confusing the diagnostic state printed. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree_stall.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rcu/tree_stall.h b/kernel/rcu/tree_stall.h index 5d666428546b..62b2c4858028 100644 --- a/kernel/rcu/tree_stall.h +++ b/kernel/rcu/tree_stall.h @@ -579,7 +579,7 @@ static void rcu_check_gp_kthread_expired_fqs_timer(void) pr_err("%s kthread timer wakeup didn't happen for %ld jiffies! g%ld f%#x %s(%d) ->state=%#x\n", rcu_state.name, (jiffies - jiffies_fqs), (long)rcu_seq_current(&rcu_state.gp_seq), - data_race(rcu_state.gp_flags), + data_race(READ_ONCE(rcu_state.gp_flags)), // Diagnostic read gp_state_getname(RCU_GP_WAIT_FQS), RCU_GP_WAIT_FQS, data_race(READ_ONCE(gpk->__state))); pr_err("\tPossible timer handling issue on cpu=%d timer-softirq=%u\n", From a542d116bab28b4bcade2f41488f4617373c620f Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 7 Mar 2024 20:11:21 -0800 Subject: [PATCH 420/969] rcu: Mark writes to rcu_sync ->gp_count field The rcu_sync structure's ->gp_count field is updated under the protection of ->rss_lock, but read locklessly, and KCSAN noted the data race. This commit therefore uses WRITE_ONCE() to do this update to clearly document its racy nature. Signed-off-by: Paul E. McKenney Cc: Oleg Nesterov Cc: Peter Zijlstra Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/sync.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/kernel/rcu/sync.c b/kernel/rcu/sync.c index 86df878a2fee..6c2bd9001adc 100644 --- a/kernel/rcu/sync.c +++ b/kernel/rcu/sync.c @@ -122,7 +122,7 @@ void rcu_sync_enter(struct rcu_sync *rsp) * we are called at early boot time but this shouldn't happen. */ } - rsp->gp_count++; + WRITE_ONCE(rsp->gp_count, rsp->gp_count + 1); spin_unlock_irq(&rsp->rss_lock); if (gp_state == GP_IDLE) { @@ -151,11 +151,15 @@ void rcu_sync_enter(struct rcu_sync *rsp) */ void rcu_sync_exit(struct rcu_sync *rsp) { + int gpc; + WARN_ON_ONCE(READ_ONCE(rsp->gp_state) == GP_IDLE); WARN_ON_ONCE(READ_ONCE(rsp->gp_count) == 0); spin_lock_irq(&rsp->rss_lock); - if (!--rsp->gp_count) { + gpc = rsp->gp_count - 1; + WRITE_ONCE(rsp->gp_count, gpc); + if (!gpc) { if (rsp->gp_state == GP_PASSED) { WRITE_ONCE(rsp->gp_state, GP_EXIT); rcu_sync_call(rsp); From 09e077cf22c4302ab4ca7932f56c5a8b20c9e32b Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 7 Mar 2024 20:14:55 -0800 Subject: [PATCH 421/969] rcu: Mark loads from rcu_state.n_online_cpus The rcu_state.n_online_cpus value is only ever updated by CPU-hotplug operations, which are serialized. However, this value is read locklessly. This commit therefore marks those reads. While in the area, it also adds ASSERT_EXCLUSIVE_WRITER() calls just in case parallel CPU hotplug becomes a thing. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.c | 4 +++- kernel/rcu/tree_stall.h | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 559f2d0d271f..7149b2d5cdd6 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -4328,7 +4328,7 @@ EXPORT_SYMBOL_GPL(rcu_lockdep_current_cpu_online); // whether spinlocks may be acquired safely. static bool rcu_init_invoked(void) { - return !!rcu_state.n_online_cpus; + return !!READ_ONCE(rcu_state.n_online_cpus); } /* @@ -4538,6 +4538,7 @@ int rcutree_prepare_cpu(unsigned int cpu) raw_spin_unlock_irqrestore_rcu_node(rnp, flags); rcu_spawn_rnp_kthreads(rnp); rcu_spawn_cpu_nocb_kthread(cpu); + ASSERT_EXCLUSIVE_WRITER(rcu_state.n_online_cpus); WRITE_ONCE(rcu_state.n_online_cpus, rcu_state.n_online_cpus + 1); return 0; @@ -4806,6 +4807,7 @@ void rcutree_migrate_callbacks(int cpu) */ int rcutree_dead_cpu(unsigned int cpu) { + ASSERT_EXCLUSIVE_WRITER(rcu_state.n_online_cpus); WRITE_ONCE(rcu_state.n_online_cpus, rcu_state.n_online_cpus - 1); // Stop-machine done, so allow nohz_full to disable tick. tick_dep_clear(TICK_DEP_BIT_RCU); diff --git a/kernel/rcu/tree_stall.h b/kernel/rcu/tree_stall.h index 62b2c4858028..8a2edf6a1ef5 100644 --- a/kernel/rcu/tree_stall.h +++ b/kernel/rcu/tree_stall.h @@ -628,7 +628,8 @@ static void print_other_cpu_stall(unsigned long gp_seq, unsigned long gps) totqlen += rcu_get_n_cbs_cpu(cpu); pr_err("\t(detected by %d, t=%ld jiffies, g=%ld, q=%lu ncpus=%d)\n", smp_processor_id(), (long)(jiffies - gps), - (long)rcu_seq_current(&rcu_state.gp_seq), totqlen, rcu_state.n_online_cpus); + (long)rcu_seq_current(&rcu_state.gp_seq), totqlen, + data_race(rcu_state.n_online_cpus)); // Diagnostic read if (ndetected) { rcu_dump_cpu_stacks(); @@ -689,7 +690,8 @@ static void print_cpu_stall(unsigned long gps) totqlen += rcu_get_n_cbs_cpu(cpu); pr_err("\t(t=%lu jiffies g=%ld q=%lu ncpus=%d)\n", jiffies - gps, - (long)rcu_seq_current(&rcu_state.gp_seq), totqlen, rcu_state.n_online_cpus); + (long)rcu_seq_current(&rcu_state.gp_seq), totqlen, + data_race(rcu_state.n_online_cpus)); // Diagnostic read rcu_check_gp_kthread_expired_fqs_timer(); rcu_check_gp_kthread_starvation(); From ae2b217ab542d0db0ca1a6de4f442201a1982f00 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 8 Mar 2024 11:15:01 -0800 Subject: [PATCH 422/969] rcu: Make hotplug operations track GP state, not flags Currently, there are rcu_data structure fields named ->rcu_onl_gp_seq and ->rcu_ofl_gp_seq that track the rcu_state.gp_flags field at the time of the corresponding CPU's last online or offline operation, respectively. However, this information is not particularly useful. It would be better to instead track the grace period state kept in rcu_state.gp_state. This would also be consistent with the initialization in rcu_boot_init_percpu_data(), which is to RCU_GP_CLEANED (an rcu_state.gp_state value), and also with the diagnostics in rcu_implicit_dynticks_qs(), whose format is consistent with an integer, not a bitmask. This commit therefore makes this change and changes the names to ->rcu_onl_gp_flags and ->rcu_ofl_gp_flags, respectively. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.c | 12 ++++++------ kernel/rcu/tree.h | 4 ++-- kernel/rcu/tree_plugin.h | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 7149b2d5cdd6..306f55b81d10 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -841,8 +841,8 @@ static int rcu_implicit_dynticks_qs(struct rcu_data *rdp) __func__, rnp1->grplo, rnp1->grphi, rnp1->qsmask, rnp1->qsmaskinit, rnp1->qsmaskinitnext, rnp1->rcu_gp_init_mask); pr_info("%s %d: %c online: %ld(%d) offline: %ld(%d)\n", __func__, rdp->cpu, ".o"[rcu_rdp_cpu_online(rdp)], - (long)rdp->rcu_onl_gp_seq, rdp->rcu_onl_gp_flags, - (long)rdp->rcu_ofl_gp_seq, rdp->rcu_ofl_gp_flags); + (long)rdp->rcu_onl_gp_seq, rdp->rcu_onl_gp_state, + (long)rdp->rcu_ofl_gp_seq, rdp->rcu_ofl_gp_state); return 1; /* Break things loose after complaining. */ } @@ -4420,9 +4420,9 @@ rcu_boot_init_percpu_data(int cpu) WARN_ON_ONCE(rcu_dynticks_in_eqs(rcu_dynticks_snap(cpu))); rdp->barrier_seq_snap = rcu_state.barrier_sequence; rdp->rcu_ofl_gp_seq = rcu_state.gp_seq; - rdp->rcu_ofl_gp_flags = RCU_GP_CLEANED; + rdp->rcu_ofl_gp_state = RCU_GP_CLEANED; rdp->rcu_onl_gp_seq = rcu_state.gp_seq; - rdp->rcu_onl_gp_flags = RCU_GP_CLEANED; + rdp->rcu_onl_gp_state = RCU_GP_CLEANED; rdp->last_sched_clock = jiffies; rdp->cpu = cpu; rcu_boot_init_nocb_percpu_data(rdp); @@ -4682,7 +4682,7 @@ void rcutree_report_cpu_starting(unsigned int cpu) ASSERT_EXCLUSIVE_WRITER(rcu_state.ncpus); rcu_gpnum_ovf(rnp, rdp); /* Offline-induced counter wrap? */ rdp->rcu_onl_gp_seq = READ_ONCE(rcu_state.gp_seq); - rdp->rcu_onl_gp_flags = READ_ONCE(rcu_state.gp_flags); + rdp->rcu_onl_gp_state = READ_ONCE(rcu_state.gp_state); /* An incoming CPU should never be blocking a grace period. */ if (WARN_ON_ONCE(rnp->qsmask & mask)) { /* RCU waiting on incoming CPU? */ @@ -4733,7 +4733,7 @@ void rcutree_report_cpu_dead(void) arch_spin_lock(&rcu_state.ofl_lock); raw_spin_lock_irqsave_rcu_node(rnp, flags); /* Enforce GP memory-order guarantee. */ rdp->rcu_ofl_gp_seq = READ_ONCE(rcu_state.gp_seq); - rdp->rcu_ofl_gp_flags = READ_ONCE(rcu_state.gp_flags); + rdp->rcu_ofl_gp_state = READ_ONCE(rcu_state.gp_state); if (rnp->qsmask & mask) { /* RCU waiting on outgoing CPU? */ /* Report quiescent state -before- changing ->qsmaskinitnext! */ rcu_disable_urgency_upon_qs(rdp); diff --git a/kernel/rcu/tree.h b/kernel/rcu/tree.h index df48160b3136..ff4d8b60554b 100644 --- a/kernel/rcu/tree.h +++ b/kernel/rcu/tree.h @@ -273,9 +273,9 @@ struct rcu_data { bool rcu_iw_pending; /* Is ->rcu_iw pending? */ unsigned long rcu_iw_gp_seq; /* ->gp_seq associated with ->rcu_iw. */ unsigned long rcu_ofl_gp_seq; /* ->gp_seq at last offline. */ - short rcu_ofl_gp_flags; /* ->gp_flags at last offline. */ + short rcu_ofl_gp_state; /* ->gp_state at last offline. */ unsigned long rcu_onl_gp_seq; /* ->gp_seq at last online. */ - short rcu_onl_gp_flags; /* ->gp_flags at last online. */ + short rcu_onl_gp_state; /* ->gp_state at last online. */ unsigned long last_fqs_resched; /* Time of last rcu_resched(). */ unsigned long last_sched_clock; /* Jiffies of last rcu_sched_clock_irq(). */ struct rcu_snap_record snap_record; /* Snapshot of core stats at half of */ diff --git a/kernel/rcu/tree_plugin.h b/kernel/rcu/tree_plugin.h index 36a8b5dbf5b5..340bbefe5f65 100644 --- a/kernel/rcu/tree_plugin.h +++ b/kernel/rcu/tree_plugin.h @@ -805,8 +805,8 @@ dump_blkd_tasks(struct rcu_node *rnp, int ncheck) rdp = per_cpu_ptr(&rcu_data, cpu); pr_info("\t%d: %c online: %ld(%d) offline: %ld(%d)\n", cpu, ".o"[rcu_rdp_cpu_online(rdp)], - (long)rdp->rcu_onl_gp_seq, rdp->rcu_onl_gp_flags, - (long)rdp->rcu_ofl_gp_seq, rdp->rcu_ofl_gp_flags); + (long)rdp->rcu_onl_gp_seq, rdp->rcu_onl_gp_state, + (long)rdp->rcu_ofl_gp_seq, rdp->rcu_ofl_gp_state); } } From 5b15f3fb89fc23b52c3cf33e76a1ada83108b438 Mon Sep 17 00:00:00 2001 From: Haifeng Xu Date: Sat, 13 Apr 2024 15:56:03 +0000 Subject: [PATCH 423/969] slub: Set __GFP_COMP in kmem_cache by default Now the __GFP_COMP is set only if the higher-order is not 0. However, __GFP_COMP flag can be set unconditionally because compound page can not be created in the order-0 case. And this can also simplify the code a bit (no need to check the order is 0 or not). Signed-off-by: Haifeng Xu Reviewed-by: Matthew Wilcox (Oracle) Signed-off-by: Vlastimil Babka --- mm/slub.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/mm/slub.c b/mm/slub.c index a30bd2157c07..62a0bb2c3147 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -5089,9 +5089,7 @@ static int calculate_sizes(struct kmem_cache *s) if ((int)order < 0) return 0; - s->allocflags = 0; - if (order) - s->allocflags |= __GFP_COMP; + s->allocflags = __GFP_COMP; if (s->flags & SLAB_CACHE_DMA) s->allocflags |= GFP_DMA; From 2b9c66d1abacbef91bdadc47fa8b9a3bd3a8fe99 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Thu, 11 Apr 2024 13:57:32 +0100 Subject: [PATCH 424/969] firmware: arm_ffa: Skip creation of the notification bitmaps When the FF-A driver is running inside a guest VM under an hypervisor, the driver/guest VM doesn't have the permission/capability to request the creation of notification bitmaps. For a VM, the hypervisor reserves memory for its VM and hypervisor framework notification bitmaps and the SPMC reserves memory for its SP and SPMC framework notification bitmaps before the hypervisor initializes it. The hypervisor does not initialize a VM if memory cannot be reserved for all its notification bitmaps. So the creation of all the necessary bitmaps are already done when the driver initialises and hence it can be skipped. We rely on FFA_FEATURES(FFA_NOTIFICATION_BITMAP_CREATE) to fail when running in the guest to handle this in the driver. Signed-off-by: Jens Wiklander Link: https://lore.kernel.org/r/20240411-ffa_npi_support-v2-1-927a670254e6@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index f2556a8e9401..a2818b69c8aa 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -1442,17 +1442,15 @@ static void ffa_notifications_setup(void) int ret, irq; ret = ffa_features(FFA_NOTIFICATION_BITMAP_CREATE, 0, NULL, NULL); - if (ret) { - pr_info("Notifications not supported, continuing with it ..\n"); - return; - } + if (!ret) { + ret = ffa_notification_bitmap_create(); + if (ret) { + pr_err("Notification bitmap create error %d\n", ret); + return; + } - ret = ffa_notification_bitmap_create(); - if (ret) { - pr_info("Notification bitmap create error %d\n", ret); - return; + drv_info->bitmap_created = true; } - drv_info->bitmap_created = true; irq = ffa_sched_recv_irq_map(); if (irq <= 0) { From f936c242553febd5052c6178c1ac555adf837fec Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 11 Apr 2024 13:57:33 +0100 Subject: [PATCH 425/969] firmware: arm_ffa: Refactor SRI handling in prepartion to add NPI support In preparation to support handling of Notification Pending Interrupt(NPI) in addition to the existing support for Schedule Receiver Interrupt(SRI), refactor the code around SRI handling so that NPI support can reuse some of it. This change shouldn't have any functionality impact. It neither adds the support for NPIs nor changes any SRI support. Tested-by: Jens Wiklander Link: https://lore.kernel.org/r/20240411-ffa_npi_support-v2-2-927a670254e6@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 47 ++++++++++++++++++------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index a2818b69c8aa..58cc017332c9 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -105,7 +105,7 @@ struct ffa_drv_info { struct ffa_pcpu_irq __percpu *irq_pcpu; struct workqueue_struct *notif_pcpu_wq; struct work_struct notif_pcpu_work; - struct work_struct irq_work; + struct work_struct sched_recv_irq_work; struct xarray partition_info; DECLARE_HASHTABLE(notifier_hash, ilog2(FFA_MAX_NOTIFICATIONS)); struct mutex notify_lock; /* lock to protect notifier hashtable */ @@ -1291,12 +1291,12 @@ static void ffa_partitions_cleanup(void) #define FFA_FEAT_SCHEDULE_RECEIVER_INT (2) #define FFA_FEAT_MANAGED_EXIT_INT (3) -static irqreturn_t irq_handler(int irq, void *irq_data) +static irqreturn_t ffa_sched_recv_irq_handler(int irq, void *irq_data) { struct ffa_pcpu_irq *pcpu = irq_data; struct ffa_drv_info *info = pcpu->info; - queue_work(info->notif_pcpu_wq, &info->irq_work); + queue_work(info->notif_pcpu_wq, &info->sched_recv_irq_work); return IRQ_HANDLED; } @@ -1306,15 +1306,23 @@ static void ffa_sched_recv_irq_work_fn(struct work_struct *work) ffa_notification_info_get(); } -static int ffa_sched_recv_irq_map(void) +static int ffa_irq_map(u32 id) { - int ret, irq, sr_intid; + char *err_str; + int ret, irq, intid; - /* The returned sr_intid is assumed to be SGI donated to NS world */ - ret = ffa_features(FFA_FEAT_SCHEDULE_RECEIVER_INT, 0, &sr_intid, NULL); + if (id == FFA_FEAT_NOTIFICATION_PENDING_INT) + err_str = "Notification Pending Interrupt"; + else if (id == FFA_FEAT_SCHEDULE_RECEIVER_INT) + err_str = "Schedule Receiver Interrupt"; + else + err_str = "Unknown ID"; + + /* The returned intid is assumed to be SGI donated to NS world */ + ret = ffa_features(id, 0, &intid, NULL); if (ret < 0) { if (ret != -EOPNOTSUPP) - pr_err("Failed to retrieve scheduler Rx interrupt\n"); + pr_err("Failed to retrieve FF-A %s %u\n", err_str, id); return ret; } @@ -1329,12 +1337,12 @@ static int ffa_sched_recv_irq_map(void) oirq.np = gic; oirq.args_count = 1; - oirq.args[0] = sr_intid; + oirq.args[0] = intid; irq = irq_create_of_mapping(&oirq); of_node_put(gic); #ifdef CONFIG_ACPI } else { - irq = acpi_register_gsi(NULL, sr_intid, ACPI_EDGE_SENSITIVE, + irq = acpi_register_gsi(NULL, intid, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_HIGH); #endif } @@ -1347,12 +1355,11 @@ static int ffa_sched_recv_irq_map(void) return irq; } -static void ffa_sched_recv_irq_unmap(void) +static void ffa_irq_unmap(unsigned int irq) { - if (drv_info->sched_recv_irq) { - irq_dispose_mapping(drv_info->sched_recv_irq); - drv_info->sched_recv_irq = 0; - } + if (!irq) + return; + irq_dispose_mapping(irq); } static int ffa_cpuhp_pcpu_irq_enable(unsigned int cpu) @@ -1402,13 +1409,14 @@ static int ffa_init_pcpu_irq(unsigned int irq) drv_info->irq_pcpu = irq_pcpu; - ret = request_percpu_irq(irq, irq_handler, "ARM-FFA", irq_pcpu); + ret = request_percpu_irq(irq, ffa_sched_recv_irq_handler, "ARM-FFA-SRI", + irq_pcpu); if (ret) { pr_err("Error registering notification IRQ %d: %d\n", irq, ret); return ret; } - INIT_WORK(&drv_info->irq_work, ffa_sched_recv_irq_work_fn); + INIT_WORK(&drv_info->sched_recv_irq_work, ffa_sched_recv_irq_work_fn); INIT_WORK(&drv_info->notif_pcpu_work, notif_pcpu_irq_work_fn); drv_info->notif_pcpu_wq = create_workqueue("ffa_pcpu_irq_notification"); if (!drv_info->notif_pcpu_wq) @@ -1428,7 +1436,8 @@ static int ffa_init_pcpu_irq(unsigned int irq) static void ffa_notifications_cleanup(void) { ffa_uninit_pcpu_irq(); - ffa_sched_recv_irq_unmap(); + ffa_irq_unmap(drv_info->sched_recv_irq); + drv_info->sched_recv_irq = 0; if (drv_info->bitmap_created) { ffa_notification_bitmap_destroy(); @@ -1452,7 +1461,7 @@ static void ffa_notifications_setup(void) drv_info->bitmap_created = true; } - irq = ffa_sched_recv_irq_map(); + irq = ffa_irq_map(FFA_FEAT_SCHEDULE_RECEIVER_INT); if (irq <= 0) { ret = irq; goto cleanup; From 08530a2aa9214932a7e830f31af68881411c3335 Mon Sep 17 00:00:00 2001 From: Jens Wiklander Date: Thu, 11 Apr 2024 13:57:34 +0100 Subject: [PATCH 426/969] firmware: arm_ffa: Add support for handling notification pending interrupt(NPI) The FF-A uses the notification pending interrupt to inform the receiver that it has a pending notification. This is a virtual interrupt and is used by the following type of receivers: 1. A guest/VM running under a hypervisor. 2. An S-EL1 SP running under a S-EL2 SPMC. The rules that govern the properties of the NPI are the same as the rules for the SRI with couple of exceptions. Both SRI and NPI can be supported simultaneously. The handling of NPI is also same as the handling of notification for the self/primary VM with ID 0 except the absence of global notification. Signed-off-by: Jens Wiklander Link: https://lore.kernel.org/r/20240411-ffa_npi_support-v2-3-927a670254e6@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 71 ++++++++++++++++++++++++------- 1 file changed, 55 insertions(+), 16 deletions(-) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index 58cc017332c9..018eddf40ca2 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -101,6 +101,7 @@ struct ffa_drv_info { bool bitmap_created; bool notif_enabled; unsigned int sched_recv_irq; + unsigned int notif_pend_irq; unsigned int cpuhp_state; struct ffa_pcpu_irq __percpu *irq_pcpu; struct workqueue_struct *notif_pcpu_wq; @@ -1301,6 +1302,15 @@ static irqreturn_t ffa_sched_recv_irq_handler(int irq, void *irq_data) return IRQ_HANDLED; } +static irqreturn_t notif_pend_irq_handler(int irq, void *irq_data) +{ + struct ffa_pcpu_irq *pcpu = irq_data; + + ffa_self_notif_handle(smp_processor_id(), true, pcpu->info); + + return IRQ_HANDLED; +} + static void ffa_sched_recv_irq_work_fn(struct work_struct *work) { ffa_notification_info_get(); @@ -1364,13 +1374,19 @@ static void ffa_irq_unmap(unsigned int irq) static int ffa_cpuhp_pcpu_irq_enable(unsigned int cpu) { - enable_percpu_irq(drv_info->sched_recv_irq, IRQ_TYPE_NONE); + if (drv_info->sched_recv_irq) + enable_percpu_irq(drv_info->sched_recv_irq, IRQ_TYPE_NONE); + if (drv_info->notif_pend_irq) + enable_percpu_irq(drv_info->notif_pend_irq, IRQ_TYPE_NONE); return 0; } static int ffa_cpuhp_pcpu_irq_disable(unsigned int cpu) { - disable_percpu_irq(drv_info->sched_recv_irq); + if (drv_info->sched_recv_irq) + disable_percpu_irq(drv_info->sched_recv_irq); + if (drv_info->notif_pend_irq) + disable_percpu_irq(drv_info->notif_pend_irq); return 0; } @@ -1389,13 +1405,16 @@ static void ffa_uninit_pcpu_irq(void) if (drv_info->sched_recv_irq) free_percpu_irq(drv_info->sched_recv_irq, drv_info->irq_pcpu); + if (drv_info->notif_pend_irq) + free_percpu_irq(drv_info->notif_pend_irq, drv_info->irq_pcpu); + if (drv_info->irq_pcpu) { free_percpu(drv_info->irq_pcpu); drv_info->irq_pcpu = NULL; } } -static int ffa_init_pcpu_irq(unsigned int irq) +static int ffa_init_pcpu_irq(void) { struct ffa_pcpu_irq __percpu *irq_pcpu; int ret, cpu; @@ -1409,11 +1428,26 @@ static int ffa_init_pcpu_irq(unsigned int irq) drv_info->irq_pcpu = irq_pcpu; - ret = request_percpu_irq(irq, ffa_sched_recv_irq_handler, "ARM-FFA-SRI", - irq_pcpu); - if (ret) { - pr_err("Error registering notification IRQ %d: %d\n", irq, ret); - return ret; + if (drv_info->sched_recv_irq) { + ret = request_percpu_irq(drv_info->sched_recv_irq, + ffa_sched_recv_irq_handler, + "ARM-FFA-SRI", irq_pcpu); + if (ret) { + pr_err("Error registering percpu SRI nIRQ %d : %d\n", + drv_info->sched_recv_irq, ret); + return ret; + } + } + + if (drv_info->notif_pend_irq) { + ret = request_percpu_irq(drv_info->notif_pend_irq, + notif_pend_irq_handler, + "ARM-FFA-NPI", irq_pcpu); + if (ret) { + pr_err("Error registering percpu NPI nIRQ %d : %d\n", + drv_info->notif_pend_irq, ret); + return ret; + } } INIT_WORK(&drv_info->sched_recv_irq_work, ffa_sched_recv_irq_work_fn); @@ -1438,6 +1472,8 @@ static void ffa_notifications_cleanup(void) ffa_uninit_pcpu_irq(); ffa_irq_unmap(drv_info->sched_recv_irq); drv_info->sched_recv_irq = 0; + ffa_irq_unmap(drv_info->notif_pend_irq); + drv_info->notif_pend_irq = 0; if (drv_info->bitmap_created) { ffa_notification_bitmap_destroy(); @@ -1448,7 +1484,7 @@ static void ffa_notifications_cleanup(void) static void ffa_notifications_setup(void) { - int ret, irq; + int ret; ret = ffa_features(FFA_NOTIFICATION_BITMAP_CREATE, 0, NULL, NULL); if (!ret) { @@ -1461,15 +1497,18 @@ static void ffa_notifications_setup(void) drv_info->bitmap_created = true; } - irq = ffa_irq_map(FFA_FEAT_SCHEDULE_RECEIVER_INT); - if (irq <= 0) { - ret = irq; + ret = ffa_irq_map(FFA_FEAT_SCHEDULE_RECEIVER_INT); + if (ret > 0) + drv_info->sched_recv_irq = ret; + + ret = ffa_irq_map(FFA_FEAT_NOTIFICATION_PENDING_INT); + if (ret > 0) + drv_info->notif_pend_irq = ret; + + if (!drv_info->sched_recv_irq && !drv_info->notif_pend_irq) goto cleanup; - } - drv_info->sched_recv_irq = irq; - - ret = ffa_init_pcpu_irq(irq); + ret = ffa_init_pcpu_irq(); if (ret) goto cleanup; From fc2897d2abe5a307e3b28943bcb4c1401432ea26 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 8 Mar 2024 13:26:26 -0800 Subject: [PATCH 427/969] rcu: Inform KCSAN of one-byte cmpxchg() in rcu_trc_cmpxchg_need_qs() Tasks Trace RCU needs a single-byte cmpxchg(), but no such thing exists. Therefore, rcu_trc_cmpxchg_need_qs() emulates one using field substitution and a four-byte cmpxchg(), such that the other three bytes are always atomically updated to their old values. This works, but results in false-positive KCSAN failures because as far as KCSAN knows, this cmpxchg() operation is updating all four bytes. This commit therefore encloses the cmpxchg() in a data_race() and adds a single-byte instrument_atomic_read_write(), thus telling KCSAN exactly what is going on so as to avoid the false positives. Signed-off-by: Paul E. McKenney Cc: Marco Elver Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tasks.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h index 147b5945d67a..327fbfc999c8 100644 --- a/kernel/rcu/tasks.h +++ b/kernel/rcu/tasks.h @@ -1457,6 +1457,7 @@ static void rcu_st_need_qs(struct task_struct *t, u8 v) /* * Do a cmpxchg() on ->trc_reader_special.b.need_qs, allowing for * the four-byte operand-size restriction of some platforms. + * * Returns the old value, which is often ignored. */ u8 rcu_trc_cmpxchg_need_qs(struct task_struct *t, u8 old, u8 new) @@ -1468,7 +1469,14 @@ u8 rcu_trc_cmpxchg_need_qs(struct task_struct *t, u8 old, u8 new) if (trs_old.b.need_qs != old) return trs_old.b.need_qs; trs_new.b.need_qs = new; - ret.s = cmpxchg(&t->trc_reader_special.s, trs_old.s, trs_new.s); + + // Although cmpxchg() appears to KCSAN to update all four bytes, + // only the .b.need_qs byte actually changes. + instrument_atomic_read_write(&t->trc_reader_special.b.need_qs, + sizeof(t->trc_reader_special.b.need_qs)); + // Avoid false-positive KCSAN failures. + ret.s = data_race(cmpxchg(&t->trc_reader_special.s, trs_old.s, trs_new.s)); + return ret.b.need_qs; } EXPORT_SYMBOL_GPL(rcu_trc_cmpxchg_need_qs); From 10c9e40f297d3f1b0d4df6e73618d4466a0b2cfc Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 15 Mar 2024 23:29:59 -0700 Subject: [PATCH 428/969] rcu: Remove redundant CONFIG_PROVE_RCU #if condition The #if condition controlling the rcu_preempt_sleep_check() definition has a redundant check for CONFIG_PREEMPT_RCU, which is already checked for by an enclosing #ifndef. This commit therefore removes this redundant condition from the inner #if. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- include/linux/rcupdate.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 2c54750e36a0..382780bb60f4 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -401,15 +401,15 @@ static inline int debug_lockdep_rcu_enabled(void) } \ } while (0) -#if defined(CONFIG_PROVE_RCU) && !defined(CONFIG_PREEMPT_RCU) +#ifndef CONFIG_PREEMPT_RCU static inline void rcu_preempt_sleep_check(void) { RCU_LOCKDEP_WARN(lock_is_held(&rcu_lock_map), "Illegal context switch in RCU read-side critical section"); } -#else /* #ifdef CONFIG_PROVE_RCU */ +#else // #ifndef CONFIG_PREEMPT_RCU static inline void rcu_preempt_sleep_check(void) { } -#endif /* #else #ifdef CONFIG_PROVE_RCU */ +#endif // #else // #ifndef CONFIG_PREEMPT_RCU #define rcu_sleep_check() \ do { \ From 8db610c3bd93e6929348f6e5271f2f905f80d82e Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 23 Feb 2024 17:07:24 -0800 Subject: [PATCH 429/969] rcu-tasks: Replace exit_tasks_rcu_start() initialization with WARN_ON_ONCE() Because the Tasks RCU ->rtp_exit_list is initialized at rcu_init() time while there is only one CPU running with interrupts disabled, it is not possible for an exiting task to encounter an uninitialized list. This commit therefore replaces the conditional initialization with a WARN_ON_ONCE(). Reported-by: Frederic Weisbecker Closes: https://lore.kernel.org/all/ZdiNXmO3wRvmzPsr@lothringen/ Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tasks.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h index 82e458ea0728..78d74c81cc24 100644 --- a/kernel/rcu/tasks.h +++ b/kernel/rcu/tasks.h @@ -1203,8 +1203,7 @@ void exit_tasks_rcu_start(void) rtpcp = this_cpu_ptr(rcu_tasks.rtpcpu); t->rcu_tasks_exit_cpu = smp_processor_id(); raw_spin_lock_irqsave_rcu_node(rtpcp, flags); - if (!rtpcp->rtp_exit_list.next) - INIT_LIST_HEAD(&rtpcp->rtp_exit_list); + WARN_ON_ONCE(!rtpcp->rtp_exit_list.next); list_add(&t->rcu_tasks_exit_list, &rtpcp->rtp_exit_list); raw_spin_unlock_irqrestore_rcu_node(rtpcp, flags); preempt_enable(); From 5f48fa85fdb92569f58374b6e040c956628fdcf5 Mon Sep 17 00:00:00 2001 From: Zqiang Date: Mon, 26 Feb 2024 11:24:39 +0800 Subject: [PATCH 430/969] rcu-tasks: Fix the comments for tasks_rcu_exit_srcu_stall_timer The synchronize_srcu() has been removed by commit("rcu-tasks: Eliminate deadlocks involving do_exit() and RCU tasks") in rcu_tasks_postscan. This commit therefore fixes the tasks_rcu_exit_srcu_stall_timer comment. Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tasks.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h index 78d74c81cc24..d5319bbe8c98 100644 --- a/kernel/rcu/tasks.h +++ b/kernel/rcu/tasks.h @@ -150,7 +150,7 @@ static struct rcu_tasks rt_name = \ #ifdef CONFIG_TASKS_RCU -/* Report delay in synchronize_srcu() completion in rcu_tasks_postscan(). */ +/* Report delay of scan exiting tasklist in rcu_tasks_postscan(). */ static void tasks_rcu_exit_srcu_stall(struct timer_list *unused); static DEFINE_TIMER(tasks_rcu_exit_srcu_stall_timer, tasks_rcu_exit_srcu_stall); #endif From cc5645fddb0ce28492b15520306d092730dffa48 Mon Sep 17 00:00:00 2001 From: Nikita Kiryushin Date: Wed, 27 Mar 2024 20:47:47 +0300 Subject: [PATCH 431/969] rcu-tasks: Fix show_rcu_tasks_trace_gp_kthread buffer overflow There is a possibility of buffer overflow in show_rcu_tasks_trace_gp_kthread() if counters, passed to sprintf() are huge. Counter numbers, needed for this are unrealistically high, but buffer overflow is still possible. Use snprintf() with buffer size instead of sprintf(). Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: edf3775f0ad6 ("rcu-tasks: Add count for idle tasks on offline CPUs") Signed-off-by: Nikita Kiryushin Reviewed-by: Steven Rostedt (Google) Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tasks.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h index d5319bbe8c98..08a92bffeb84 100644 --- a/kernel/rcu/tasks.h +++ b/kernel/rcu/tasks.h @@ -1997,7 +1997,7 @@ void show_rcu_tasks_trace_gp_kthread(void) { char buf[64]; - sprintf(buf, "N%lu h:%lu/%lu/%lu", + snprintf(buf, sizeof(buf), "N%lu h:%lu/%lu/%lu", data_race(n_trc_holdouts), data_race(n_heavy_reader_ofl_updates), data_race(n_heavy_reader_updates), From 80cd613a9ae091dbf52e27a409d58da988ffc8f3 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Mon, 25 Mar 2024 18:39:08 +0100 Subject: [PATCH 432/969] rcu: Mollify sparse with RCU guard When using "guard(rcu)();" sparse will complain, because even though it now understands the cleanup attribute, it doesn't evaluate the calls from it at function exit, and thus doesn't count the context correctly. Given that there's a conditional in the resulting code: static inline void class_rcu_destructor(class_rcu_t *_T) { if (_T->lock) { rcu_read_unlock(); } } it seems that even trying to teach sparse to evalulate the cleanup attribute function it'd still be difficult to really make it understand the full context here. Suppress the sparse warning by just releasing the context in the acquisition part of the function, after all we know it's safe with the guard, that's the whole point of it. Signed-off-by: Johannes Berg Reviewed-by: Boqun Feng Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- include/linux/rcupdate.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 382780bb60f4..dfd2399f2cde 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -1090,6 +1090,18 @@ rcu_head_after_call_rcu(struct rcu_head *rhp, rcu_callback_t f) extern int rcu_expedited; extern int rcu_normal; -DEFINE_LOCK_GUARD_0(rcu, rcu_read_lock(), rcu_read_unlock()) +DEFINE_LOCK_GUARD_0(rcu, + do { + rcu_read_lock(); + /* + * sparse doesn't call the cleanup function, + * so just release immediately and don't track + * the context. We don't need to anyway, since + * the whole point of the guard is to not need + * the explicit unlock. + */ + __release(RCU); + } while (0), + rcu_read_unlock()) #endif /* __LINUX_RCUPDATE_H */ From 3758f7d9917bd7ef0482c4184c0ad673b4c4e069 Mon Sep 17 00:00:00 2001 From: Nikita Kiryushin Date: Mon, 1 Apr 2024 22:43:15 +0300 Subject: [PATCH 433/969] rcu: Fix buffer overflow in print_cpu_stall_info() The rcuc-starvation output from print_cpu_stall_info() might overflow the buffer if there is a huge difference in jiffies difference. The situation might seem improbable, but computers sometimes get very confused about time, which can result in full-sized integers, and, in this case, buffer overflow. Also, the unsigned jiffies difference is printed using %ld, which is normally for signed integers. This is intentional for debugging purposes, but it is not obvious from the code. This commit therefore changes sprintf() to snprintf() and adds a clarifying comment about intention of %ld format. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 245a62982502 ("rcu: Dump rcuc kthread status for CPUs not reporting quiescent state") Signed-off-by: Nikita Kiryushin Reviewed-by: Steven Rostedt (Google) Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree_stall.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/tree_stall.h b/kernel/rcu/tree_stall.h index 8a2edf6a1ef5..460efecd077b 100644 --- a/kernel/rcu/tree_stall.h +++ b/kernel/rcu/tree_stall.h @@ -504,7 +504,8 @@ static void print_cpu_stall_info(int cpu) rcu_dynticks_in_eqs(rcu_dynticks_snap(cpu)); rcuc_starved = rcu_is_rcuc_kthread_starving(rdp, &j); if (rcuc_starved) - sprintf(buf, " rcuc=%ld jiffies(starved)", j); + // Print signed value, as negative values indicate a probable bug. + snprintf(buf, sizeof(buf), " rcuc=%ld jiffies(starved)", j); pr_err("\t%d-%c%c%c%c: (%lu %s) idle=%04x/%ld/%#lx softirq=%u/%u fqs=%ld%s%s\n", cpu, "O."[!!cpu_online(cpu)], From 988f569ae041ccc93a79d98d1b0043dff4d7e9b7 Mon Sep 17 00:00:00 2001 From: "Uladzislau Rezki (Sony)" Date: Fri, 8 Mar 2024 18:34:05 +0100 Subject: [PATCH 434/969] rcu: Reduce synchronize_rcu() latency A call to a synchronize_rcu() can be optimized from a latency point of view. Workloads which depend on this can benefit of it. The delay of wakeme_after_rcu() callback, which unblocks a waiter, depends on several factors: - how fast a process of offloading is started. Combination of: - !CONFIG_RCU_NOCB_CPU/CONFIG_RCU_NOCB_CPU; - !CONFIG_RCU_LAZY/CONFIG_RCU_LAZY; - other. - when started, invoking path is interrupted due to: - time limit; - need_resched(); - if limit is reached. - where in a nocb list it is located; - how fast previous callbacks completed; Example: 1. On our embedded devices i can easily trigger the scenario when it is a last in the list out of ~3600 callbacks: <...>-29 [001] d..1. 21950.145313: rcu_batch_start: rcu_preempt CBs=3613 bl=28 ... <...>-29 [001] ..... 21950.152578: rcu_invoke_callback: rcu_preempt rhp=00000000b2d6dee8 func=__free_vm_area_struct.cfi_jt <...>-29 [001] ..... 21950.152579: rcu_invoke_callback: rcu_preempt rhp=00000000a446f607 func=__free_vm_area_struct.cfi_jt <...>-29 [001] ..... 21950.152580: rcu_invoke_callback: rcu_preempt rhp=00000000a5cab03b func=__free_vm_area_struct.cfi_jt <...>-29 [001] ..... 21950.152581: rcu_invoke_callback: rcu_preempt rhp=0000000013b7e5ee func=__free_vm_area_struct.cfi_jt <...>-29 [001] ..... 21950.152582: rcu_invoke_callback: rcu_preempt rhp=000000000a8ca6f9 func=__free_vm_area_struct.cfi_jt <...>-29 [001] ..... 21950.152583: rcu_invoke_callback: rcu_preempt rhp=000000008f162ca8 func=wakeme_after_rcu.cfi_jt <...>-29 [001] d..1. 21950.152625: rcu_batch_end: rcu_preempt CBs-invoked=3612 idle=.... 2. We use cpuset/cgroup to classify tasks and assign them into different cgroups. For example "backgrond" group which binds tasks only to little CPUs or "foreground" which makes use of all CPUs. Tasks can be migrated between groups by a request if an acceleration is needed. See below an example how "surfaceflinger" task gets migrated. Initially it is located in the "system-background" cgroup which allows to run only on little cores. In order to speed it up it can be temporary moved into "foreground" cgroup which allows to use big/all CPUs: cgroup_attach_task(): -> cgroup_migrate_execute() -> cpuset_can_attach() -> percpu_down_write() -> rcu_sync_enter() -> synchronize_rcu() -> now move tasks to the new cgroup. -> cgroup_migrate_finish() rcuop/1-29 [000] ..... 7030.528570: rcu_invoke_callback: rcu_preempt rhp=00000000461605e0 func=wakeme_after_rcu.cfi_jt PERFD-SERVER-1855 [000] d..1. 7030.530293: cgroup_attach_task: dst_root=3 dst_id=22 dst_level=1 dst_path=/foreground pid=1900 comm=surfaceflinger TimerDispatch-2768 [002] d..5. 7030.537542: sched_migrate_task: comm=surfaceflinger pid=1900 prio=98 orig_cpu=0 dest_cpu=4 "Boosting a task" depends on synchronize_rcu() latency: - first trace shows a completion of synchronize_rcu(); - second shows attaching a task to a new group; - last shows a final step when migration occurs. 3. To address this drawback, maintain a separate track that consists of synchronize_rcu() callers only. After completion of a grace period users are deferred to a dedicated worker to process requests. 4. This patch reduces the latency of synchronize_rcu() approximately by ~30-40% on synthetic tests. The real test case, camera launch time, shows(time is in milliseconds): 1-run 542 vs 489 improvement 9% 2-run 540 vs 466 improvement 13% 3-run 518 vs 468 improvement 9% 4-run 531 vs 457 improvement 13% 5-run 548 vs 475 improvement 13% 6-run 509 vs 484 improvement 4% Synthetic test(no "noise" from other callbacks): Hardware: x86_64 64 CPUs, 64GB of memory Linux-6.6 - 10K tasks(simultaneous); - each task does(1000 loops) synchronize_rcu(); kfree(p); default: CONFIG_RCU_NOCB_CPU: takes 54 seconds to complete all users; patch: CONFIG_RCU_NOCB_CPU: takes 35 seconds to complete all users. Running 60K gives approximately same results on my setup. Please note it is without any interaction with another type of callbacks, otherwise it will impact a lot a default case. 5. By default it is disabled. To enable this perform one of the below sequence: echo 1 > /sys/module/rcutree/parameters/rcu_normal_wake_from_gp or pass a boot parameter "rcutree.rcu_normal_wake_from_gp=1" Reviewed-by: Paul E. McKenney Reviewed-by: Frederic Weisbecker Co-developed-by: Neeraj Upadhyay (AMD) Signed-off-by: Neeraj Upadhyay (AMD) Signed-off-by: Uladzislau Rezki (Sony) --- .../admin-guide/kernel-parameters.txt | 14 + kernel/rcu/tree.c | 331 +++++++++++++++++- kernel/rcu/tree_exp.h | 2 +- 3 files changed, 345 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index bb884c14b2f6..0a3b0fd1910e 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5091,6 +5091,20 @@ delay, memory pressure or callback list growing too big. + rcutree.rcu_normal_wake_from_gp= [KNL] + Reduces a latency of synchronize_rcu() call. This approach + maintains its own track of synchronize_rcu() callers, so it + does not interact with regular callbacks because it does not + use a call_rcu[_hurry]() path. Please note, this is for a + normal grace period. + + How to enable it: + + echo 1 > /sys/module/rcutree/parameters/rcu_normal_wake_from_gp + or pass a boot parameter "rcutree.rcu_normal_wake_from_gp=1" + + Default is 0. + rcuscale.gp_async= [KNL] Measure performance of asynchronous grace-period primitives such as call_rcu(). diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index d9642dd06c25..f65255205e44 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -75,6 +75,7 @@ #define MODULE_PARAM_PREFIX "rcutree." /* Data structures. */ +static void rcu_sr_normal_gp_cleanup_work(struct work_struct *); static DEFINE_PER_CPU_SHARED_ALIGNED(struct rcu_data, rcu_data) = { .gpwrap = true, @@ -93,6 +94,8 @@ static struct rcu_state rcu_state = { .exp_mutex = __MUTEX_INITIALIZER(rcu_state.exp_mutex), .exp_wake_mutex = __MUTEX_INITIALIZER(rcu_state.exp_wake_mutex), .ofl_lock = __ARCH_SPIN_LOCK_UNLOCKED, + .srs_cleanup_work = __WORK_INITIALIZER(rcu_state.srs_cleanup_work, + rcu_sr_normal_gp_cleanup_work), }; /* Dump rcu_node combining tree at boot to verify correct setup. */ @@ -1422,6 +1425,282 @@ static void rcu_poll_gp_seq_end_unlocked(unsigned long *snap) raw_spin_unlock_irqrestore_rcu_node(rnp, flags); } +/* + * There is a single llist, which is used for handling + * synchronize_rcu() users' enqueued rcu_synchronize nodes. + * Within this llist, there are two tail pointers: + * + * wait tail: Tracks the set of nodes, which need to + * wait for the current GP to complete. + * done tail: Tracks the set of nodes, for which grace + * period has elapsed. These nodes processing + * will be done as part of the cleanup work + * execution by a kworker. + * + * At every grace period init, a new wait node is added + * to the llist. This wait node is used as wait tail + * for this new grace period. Given that there are a fixed + * number of wait nodes, if all wait nodes are in use + * (which can happen when kworker callback processing + * is delayed) and additional grace period is requested. + * This means, a system is slow in processing callbacks. + * + * TODO: If a slow processing is detected, a first node + * in the llist should be used as a wait-tail for this + * grace period, therefore users which should wait due + * to a slow process are handled by _this_ grace period + * and not next. + * + * Below is an illustration of how the done and wait + * tail pointers move from one set of rcu_synchronize nodes + * to the other, as grace periods start and finish and + * nodes are processed by kworker. + * + * + * a. Initial llist callbacks list: + * + * +----------+ +--------+ +-------+ + * | | | | | | + * | head |---------> | cb2 |--------->| cb1 | + * | | | | | | + * +----------+ +--------+ +-------+ + * + * + * + * b. New GP1 Start: + * + * WAIT TAIL + * | + * | + * v + * +----------+ +--------+ +--------+ +-------+ + * | | | | | | | | + * | head ------> wait |------> cb2 |------> | cb1 | + * | | | head1 | | | | | + * +----------+ +--------+ +--------+ +-------+ + * + * + * + * c. GP completion: + * + * WAIT_TAIL == DONE_TAIL + * + * DONE TAIL + * | + * | + * v + * +----------+ +--------+ +--------+ +-------+ + * | | | | | | | | + * | head ------> wait |------> cb2 |------> | cb1 | + * | | | head1 | | | | | + * +----------+ +--------+ +--------+ +-------+ + * + * + * + * d. New callbacks and GP2 start: + * + * WAIT TAIL DONE TAIL + * | | + * | | + * v v + * +----------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ + * | | | | | | | | | | | | | | + * | head ------> wait |--->| cb4 |--->| cb3 |--->|wait |--->| cb2 |--->| cb1 | + * | | | head2| | | | | |head1| | | | | + * +----------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ + * + * + * + * e. GP2 completion: + * + * WAIT_TAIL == DONE_TAIL + * DONE TAIL + * | + * | + * v + * +----------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ + * | | | | | | | | | | | | | | + * | head ------> wait |--->| cb4 |--->| cb3 |--->|wait |--->| cb2 |--->| cb1 | + * | | | head2| | | | | |head1| | | | | + * +----------+ +------+ +------+ +------+ +-----+ +-----+ +-----+ + * + * + * While the llist state transitions from d to e, a kworker + * can start executing rcu_sr_normal_gp_cleanup_work() and + * can observe either the old done tail (@c) or the new + * done tail (@e). So, done tail updates and reads need + * to use the rel-acq semantics. If the concurrent kworker + * observes the old done tail, the newly queued work + * execution will process the updated done tail. If the + * concurrent kworker observes the new done tail, then + * the newly queued work will skip processing the done + * tail, as workqueue semantics guarantees that the new + * work is executed only after the previous one completes. + * + * f. kworker callbacks processing complete: + * + * + * DONE TAIL + * | + * | + * v + * +----------+ +--------+ + * | | | | + * | head ------> wait | + * | | | head2 | + * +----------+ +--------+ + * + */ +static bool rcu_sr_is_wait_head(struct llist_node *node) +{ + return &(rcu_state.srs_wait_nodes)[0].node <= node && + node <= &(rcu_state.srs_wait_nodes)[SR_NORMAL_GP_WAIT_HEAD_MAX - 1].node; +} + +static struct llist_node *rcu_sr_get_wait_head(void) +{ + struct sr_wait_node *sr_wn; + int i; + + for (i = 0; i < SR_NORMAL_GP_WAIT_HEAD_MAX; i++) { + sr_wn = &(rcu_state.srs_wait_nodes)[i]; + + if (!atomic_cmpxchg_acquire(&sr_wn->inuse, 0, 1)) + return &sr_wn->node; + } + + return NULL; +} + +static void rcu_sr_put_wait_head(struct llist_node *node) +{ + struct sr_wait_node *sr_wn = container_of(node, struct sr_wait_node, node); + + atomic_set_release(&sr_wn->inuse, 0); +} + +/* Disabled by default. */ +static int rcu_normal_wake_from_gp; +module_param(rcu_normal_wake_from_gp, int, 0644); + +static void rcu_sr_normal_complete(struct llist_node *node) +{ + struct rcu_synchronize *rs = container_of( + (struct rcu_head *) node, struct rcu_synchronize, head); + unsigned long oldstate = (unsigned long) rs->head.func; + + WARN_ONCE(IS_ENABLED(CONFIG_PROVE_RCU) && + !poll_state_synchronize_rcu(oldstate), + "A full grace period is not passed yet: %lu", + rcu_seq_diff(get_state_synchronize_rcu(), oldstate)); + + /* Finally. */ + complete(&rs->completion); +} + +static void rcu_sr_normal_gp_cleanup_work(struct work_struct *work) +{ + struct llist_node *done, *rcu, *next, *head; + + /* + * This work execution can potentially execute + * while a new done tail is being updated by + * grace period kthread in rcu_sr_normal_gp_cleanup(). + * So, read and updates of done tail need to + * follow acq-rel semantics. + * + * Given that wq semantics guarantees that a single work + * cannot execute concurrently by multiple kworkers, + * the done tail list manipulations are protected here. + */ + done = smp_load_acquire(&rcu_state.srs_done_tail); + if (!done) + return; + + WARN_ON_ONCE(!rcu_sr_is_wait_head(done)); + head = done->next; + done->next = NULL; + + /* + * The dummy node, which is pointed to by the + * done tail which is acq-read above is not removed + * here. This allows lockless additions of new + * rcu_synchronize nodes in rcu_sr_normal_add_req(), + * while the cleanup work executes. The dummy + * nodes is removed, in next round of cleanup + * work execution. + */ + llist_for_each_safe(rcu, next, head) { + if (!rcu_sr_is_wait_head(rcu)) { + rcu_sr_normal_complete(rcu); + continue; + } + + rcu_sr_put_wait_head(rcu); + } +} + +/* + * Helper function for rcu_gp_cleanup(). + */ +static void rcu_sr_normal_gp_cleanup(void) +{ + struct llist_node *wait_tail; + + wait_tail = rcu_state.srs_wait_tail; + if (wait_tail == NULL) + return; + + rcu_state.srs_wait_tail = NULL; + ASSERT_EXCLUSIVE_WRITER(rcu_state.srs_wait_tail); + + // concurrent sr_normal_gp_cleanup work might observe this update. + smp_store_release(&rcu_state.srs_done_tail, wait_tail); + ASSERT_EXCLUSIVE_WRITER(rcu_state.srs_done_tail); + + schedule_work(&rcu_state.srs_cleanup_work); +} + +/* + * Helper function for rcu_gp_init(). + */ +static bool rcu_sr_normal_gp_init(void) +{ + struct llist_node *first; + struct llist_node *wait_head; + bool start_new_poll = false; + + first = READ_ONCE(rcu_state.srs_next.first); + if (!first || rcu_sr_is_wait_head(first)) + return start_new_poll; + + wait_head = rcu_sr_get_wait_head(); + if (!wait_head) { + // Kick another GP to retry. + start_new_poll = true; + return start_new_poll; + } + + /* Inject a wait-dummy-node. */ + llist_add(wait_head, &rcu_state.srs_next); + + /* + * A waiting list of rcu_synchronize nodes should be empty on + * this step, since a GP-kthread, rcu_gp_init() -> gp_cleanup(), + * rolls it over. If not, it is a BUG, warn a user. + */ + WARN_ON_ONCE(rcu_state.srs_wait_tail != NULL); + rcu_state.srs_wait_tail = wait_head; + ASSERT_EXCLUSIVE_WRITER(rcu_state.srs_wait_tail); + + return start_new_poll; +} + +static void rcu_sr_normal_add_req(struct rcu_synchronize *rs) +{ + llist_add((struct llist_node *) &rs->head, &rcu_state.srs_next); +} + /* * Initialize a new grace period. Return false if no grace period required. */ @@ -1432,6 +1711,7 @@ static noinline_for_stack bool rcu_gp_init(void) unsigned long mask; struct rcu_data *rdp; struct rcu_node *rnp = rcu_get_root(); + bool start_new_poll; WRITE_ONCE(rcu_state.gp_activity, jiffies); raw_spin_lock_irq_rcu_node(rnp); @@ -1456,10 +1736,24 @@ static noinline_for_stack bool rcu_gp_init(void) /* Record GP times before starting GP, hence rcu_seq_start(). */ rcu_seq_start(&rcu_state.gp_seq); ASSERT_EXCLUSIVE_WRITER(rcu_state.gp_seq); + start_new_poll = rcu_sr_normal_gp_init(); trace_rcu_grace_period(rcu_state.name, rcu_state.gp_seq, TPS("start")); rcu_poll_gp_seq_start(&rcu_state.gp_seq_polled_snap); raw_spin_unlock_irq_rcu_node(rnp); + /* + * The "start_new_poll" is set to true, only when this GP is not able + * to handle anything and there are outstanding users. It happens when + * the rcu_sr_normal_gp_init() function was not able to insert a dummy + * separator to the llist, because there were no left any dummy-nodes. + * + * Number of dummy-nodes is fixed, it could be that we are run out of + * them, if so we start a new pool request to repeat a try. It is rare + * and it means that a system is doing a slow processing of callbacks. + */ + if (start_new_poll) + (void) start_poll_synchronize_rcu(); + /* * Apply per-leaf buffered online and offline operations to * the rcu_node tree. Note that this new grace period need not @@ -1825,6 +2119,9 @@ static noinline void rcu_gp_cleanup(void) } raw_spin_unlock_irq_rcu_node(rnp); + // Make synchronize_rcu() users aware of the end of old grace period. + rcu_sr_normal_gp_cleanup(); + // If strict, make all CPUs aware of the end of the old grace period. if (IS_ENABLED(CONFIG_RCU_STRICT_GRACE_PERIOD)) on_each_cpu(rcu_strict_gp_boundary, NULL, 0); @@ -3559,6 +3856,38 @@ static int rcu_blocking_is_gp(void) return true; } +/* + * Helper function for the synchronize_rcu() API. + */ +static void synchronize_rcu_normal(void) +{ + struct rcu_synchronize rs; + + if (!READ_ONCE(rcu_normal_wake_from_gp)) { + wait_rcu_gp(call_rcu_hurry); + return; + } + + init_rcu_head_on_stack(&rs.head); + init_completion(&rs.completion); + + /* + * This code might be preempted, therefore take a GP + * snapshot before adding a request. + */ + if (IS_ENABLED(CONFIG_PROVE_RCU)) + rs.head.func = (void *) get_state_synchronize_rcu(); + + rcu_sr_normal_add_req(&rs); + + /* Kick a GP and start waiting. */ + (void) start_poll_synchronize_rcu(); + + /* Now we can wait. */ + wait_for_completion(&rs.completion); + destroy_rcu_head_on_stack(&rs.head); +} + /** * synchronize_rcu - wait until a grace period has elapsed. * @@ -3610,7 +3939,7 @@ void synchronize_rcu(void) if (rcu_gp_is_expedited()) synchronize_rcu_expedited(); else - wait_rcu_gp(call_rcu_hurry); + synchronize_rcu_normal(); return; } diff --git a/kernel/rcu/tree_exp.h b/kernel/rcu/tree_exp.h index 6b83537480b1..8a1d9c8bd9f7 100644 --- a/kernel/rcu/tree_exp.h +++ b/kernel/rcu/tree_exp.h @@ -930,7 +930,7 @@ void synchronize_rcu_expedited(void) /* If expedited grace periods are prohibited, fall back to normal. */ if (rcu_gp_is_normal()) { - wait_rcu_gp(call_rcu_hurry); + synchronize_rcu_normal(); return; } From 2053937a310a3982de9d33af3db2dbd2b32b66e4 Mon Sep 17 00:00:00 2001 From: "Uladzislau Rezki (Sony)" Date: Fri, 8 Mar 2024 18:34:06 +0100 Subject: [PATCH 435/969] rcu: Add a trace event for synchronize_rcu_normal() Add an rcu_sr_normal() trace event. It takes three arguments first one is the name of RCU flavour, second one is a user id which triggeres synchronize_rcu_normal() and last one is an event. There are two traces in the synchronize_rcu_normal(). On entry, when a new request is registered and on exit point when request is completed. Please note, CONFIG_RCU_TRACE=y is required to activate traces. Reviewed-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- include/trace/events/rcu.h | 27 +++++++++++++++++++++++++++ kernel/rcu/tree.c | 7 ++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/include/trace/events/rcu.h b/include/trace/events/rcu.h index 2ef9c719772a..31b3e0d3e65f 100644 --- a/include/trace/events/rcu.h +++ b/include/trace/events/rcu.h @@ -707,6 +707,33 @@ TRACE_EVENT_RCU(rcu_invoke_kfree_bulk_callback, __entry->rcuname, __entry->p, __entry->nr_records) ); +/* + * Tracepoint for a normal synchronize_rcu() states. The first argument + * is the RCU flavor, the second argument is a pointer to rcu_head the + * last one is an event. + */ +TRACE_EVENT_RCU(rcu_sr_normal, + + TP_PROTO(const char *rcuname, struct rcu_head *rhp, const char *srevent), + + TP_ARGS(rcuname, rhp, srevent), + + TP_STRUCT__entry( + __field(const char *, rcuname) + __field(void *, rhp) + __field(const char *, srevent) + ), + + TP_fast_assign( + __entry->rcuname = rcuname; + __entry->rhp = rhp; + __entry->srevent = srevent; + ), + + TP_printk("%s rhp=0x%p event=%s", + __entry->rcuname, __entry->rhp, __entry->srevent) +); + /* * Tracepoint for exiting rcu_do_batch after RCU callbacks have been * invoked. The first argument is the name of the RCU flavor, diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index f65255205e44..2e1c5be6d64b 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -3863,9 +3863,11 @@ static void synchronize_rcu_normal(void) { struct rcu_synchronize rs; + trace_rcu_sr_normal(rcu_state.name, &rs.head, TPS("request")); + if (!READ_ONCE(rcu_normal_wake_from_gp)) { wait_rcu_gp(call_rcu_hurry); - return; + goto trace_complete_out; } init_rcu_head_on_stack(&rs.head); @@ -3886,6 +3888,9 @@ static void synchronize_rcu_normal(void) /* Now we can wait. */ wait_for_completion(&rs.completion); destroy_rcu_head_on_stack(&rs.head); + +trace_complete_out: + trace_rcu_sr_normal(rcu_state.name, &rs.head, TPS("complete")); } /** From 462df2f543ae360e79fcaa1b498d2a1a0c2a5b63 Mon Sep 17 00:00:00 2001 From: "Uladzislau Rezki (Sony)" Date: Fri, 8 Mar 2024 18:34:07 +0100 Subject: [PATCH 436/969] rcu: Support direct wake-up of synchronize_rcu() users This patch introduces a small enhancement which allows to do a direct wake-up of synchronize_rcu() callers. It occurs after a completion of grace period, thus by the gp-kthread. Number of clients is limited by the hard-coded maximum allowed threshold. The remaining part, if still exists is deferred to a main worker. Link: https://lore.kernel.org/lkml/Zd0ZtNu+Rt0qXkfS@lothringen/ Reviewed-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.c | 24 +++++++++++++++++++++++- kernel/rcu/tree.h | 6 ++++++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 2e1c5be6d64b..2a270abade4d 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -1645,7 +1645,8 @@ static void rcu_sr_normal_gp_cleanup_work(struct work_struct *work) */ static void rcu_sr_normal_gp_cleanup(void) { - struct llist_node *wait_tail; + struct llist_node *wait_tail, *next, *rcu; + int done = 0; wait_tail = rcu_state.srs_wait_tail; if (wait_tail == NULL) @@ -1653,11 +1654,32 @@ static void rcu_sr_normal_gp_cleanup(void) rcu_state.srs_wait_tail = NULL; ASSERT_EXCLUSIVE_WRITER(rcu_state.srs_wait_tail); + WARN_ON_ONCE(!rcu_sr_is_wait_head(wait_tail)); + + /* + * Process (a) and (d) cases. See an illustration. + */ + llist_for_each_safe(rcu, next, wait_tail->next) { + if (rcu_sr_is_wait_head(rcu)) + break; + + rcu_sr_normal_complete(rcu); + // It can be last, update a next on this step. + wait_tail->next = next; + + if (++done == SR_MAX_USERS_WAKE_FROM_GP) + break; + } // concurrent sr_normal_gp_cleanup work might observe this update. smp_store_release(&rcu_state.srs_done_tail, wait_tail); ASSERT_EXCLUSIVE_WRITER(rcu_state.srs_done_tail); + /* + * We schedule a work in order to perform a final processing + * of outstanding users(if still left) and releasing wait-heads + * added by rcu_sr_normal_gp_init() call. + */ schedule_work(&rcu_state.srs_cleanup_work); } diff --git a/kernel/rcu/tree.h b/kernel/rcu/tree.h index b942b9437438..2832787cee1d 100644 --- a/kernel/rcu/tree.h +++ b/kernel/rcu/tree.h @@ -315,6 +315,12 @@ do { \ __set_current_state(TASK_RUNNING); \ } while (0) +/* + * A max threshold for synchronize_rcu() users which are + * awaken directly by the rcu_gp_kthread(). Left part is + * deferred to the main worker. + */ +#define SR_MAX_USERS_WAKE_FROM_GP 5 #define SR_NORMAL_GP_WAIT_HEAD_MAX 5 struct sr_wait_node { From 0fd210baa07a9e3f15df1bc687293eafb119283a Mon Sep 17 00:00:00 2001 From: "Uladzislau Rezki (Sony)" Date: Fri, 8 Mar 2024 18:34:09 +0100 Subject: [PATCH 437/969] rcu: Allocate WQ with WQ_MEM_RECLAIM bit set synchronize_rcu() users have to be processed regardless of memory pressure so our private WQ needs to have at least one execution context what WQ_MEM_RECLAIM flag guarantees. Reviewed-by: Paul E. McKenney Reviewed-by: Joel Fernandes (Google) Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/tree.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index 2a270abade4d..1d5c000e5c7a 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -1582,6 +1582,7 @@ static void rcu_sr_put_wait_head(struct llist_node *node) /* Disabled by default. */ static int rcu_normal_wake_from_gp; module_param(rcu_normal_wake_from_gp, int, 0644); +static struct workqueue_struct *sync_wq; static void rcu_sr_normal_complete(struct llist_node *node) { @@ -1680,7 +1681,7 @@ static void rcu_sr_normal_gp_cleanup(void) * of outstanding users(if still left) and releasing wait-heads * added by rcu_sr_normal_gp_init() call. */ - schedule_work(&rcu_state.srs_cleanup_work); + queue_work(sync_wq, &rcu_state.srs_cleanup_work); } /* @@ -5585,6 +5586,9 @@ void __init rcu_init(void) rcu_gp_wq = alloc_workqueue("rcu_gp", WQ_MEM_RECLAIM, 0); WARN_ON(!rcu_gp_wq); + sync_wq = alloc_workqueue("sync_wq", WQ_MEM_RECLAIM, 0); + WARN_ON(!sync_wq); + /* Fill in default value for rcutree.qovld boot parameter. */ /* -After- the rcu_node ->lock fields are initialized! */ if (qovld < 0) From 4625810361d659a16de821199b77f4bc057f07d5 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Wed, 3 Apr 2024 13:11:06 +0200 Subject: [PATCH 438/969] dt-bindings: firmware: arm,scmi: Update examples for protocol@13 Recently we extended the binding for protocol@13 to allow it to be modelled as a generic performance domain. In a way to promote using the new binding, let's update the examples. Signed-off-by: Ulf Hansson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20240403111106.1110940-1-ulf.hansson@linaro.org Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 4591523b51a0..93fb7d05f849 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -355,7 +355,7 @@ examples: scmi_dvfs: protocol@13 { reg = <0x13>; - #clock-cells = <1>; + #power-domain-cells = <1>; mboxes = <&mhuB 1 0>, <&mhuB 1 1>; @@ -468,7 +468,7 @@ examples: reg = <0x13>; linaro,optee-channel-id = <1>; shmem = <&cpu_optee_lpri0>; - #clock-cells = <1>; + #power-domain-cells = <1>; }; scmi_clk0: protocol@14 { From 943e6cdc1d77df0cb2687446aa691bc6863d8498 Mon Sep 17 00:00:00 2001 From: Miles Alan Date: Sat, 16 Mar 2024 20:39:28 -0400 Subject: [PATCH 439/969] arm64: dts: allwinner: pinephone: Retain LEDs state in suspend Allows user to set a LED before entering suspend to know that the phone is still on (or could be used for notifications etc). Signed-off-by: Miles Alan Signed-off-by: Ondrej Jirman Signed-off-by: Aren Moynihan Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240317004116.1473967-1-aren@peacevolution.org Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 87847116ab6d..ad2476ee01e4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -43,18 +43,21 @@ function = LED_FUNCTION_INDICATOR; color = ; gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + retain-state-suspended; }; led-1 { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ + retain-state-suspended; }; led-2 { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + retain-state-suspended; }; }; From c603327e3eef62b1e71a1b74c364893966e18249 Mon Sep 17 00:00:00 2001 From: Aren Moynihan Date: Sat, 16 Mar 2024 20:39:29 -0400 Subject: [PATCH 440/969] arm64: dts: allwinner: pinephone: add multicolor LED node The red, green, and blue LEDs currently in the device tree represent a single RGB LED on the front of the PinePhone. Signed-off-by: Aren Moynihan Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240317004116.1473967-2-aren@peacevolution.org Signed-off-by: Jernej Skrabec --- .../boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index ad2476ee01e4..6eab61a12cd8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -39,21 +39,21 @@ leds { compatible = "gpio-leds"; - led-0 { + led0: led-0 { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ retain-state-suspended; }; - led-1 { + led1: led-1 { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ retain-state-suspended; }; - led-2 { + led2: led-2 { function = LED_FUNCTION_INDICATOR; color = ; gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ @@ -61,6 +61,13 @@ }; }; + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_INDICATOR; + leds = <&led0>, <&led1>, <&led2>; + }; + reg_ps: ps-regulator { compatible = "regulator-fixed"; regulator-name = "ps"; From 67347f893aec8c0c5a3eed8929d39c528371b357 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 17 Mar 2024 19:41:27 +0100 Subject: [PATCH 441/969] arm64: dts: allwinner: Pine H64: correctly remove reg_gmac_3v3 There is no "reg_gmac_3v3" device node in sun50i-h6-pine-h64.dts, although there is "gmac-3v3" with "reg_gmac_3v3" label, so let's assume author wanted to remove that node. Delete node via phandle, not via full node path, to fix this. Fixes: f33a91175029 ("arm64: dts: allwinner: add pineh64 model B") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240317184130.157695-1-krzysztof.kozlowski@linaro.org Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index b710f1a0f53a..1b6e5595ac6e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -5,12 +5,12 @@ #include "sun50i-h6-pine-h64.dts" +/delete-node/ ®_gmac_3v3; + / { model = "Pine H64 model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - /delete-node/ reg_gmac_3v3; - wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ From 5dfdedf0de9a7c942a76284d0b40345c666a3151 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 17 Mar 2024 19:41:28 +0100 Subject: [PATCH 442/969] arm64: dts: allwinner: drop underscore in node names Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for pwrseq node, because generic naming is favored by Devicetree spec. All the clocks affected by this change use clock-output-names, so resulting clock name should not change. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240317184130.157695-2-krzysztof.kozlowski@linaro.org Signed-off-by: Jernej Skrabec --- .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 2 +- .../arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 2 +- .../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 +++++----- .../boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 2 +- .../boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 4 ++-- .../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 2 +- .../dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 2 +- .../dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts | 2 +- .../arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 +- .../boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 2 +- .../boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +- .../dts/allwinner/sun50i-h618-transpeed-8k618-t.dts | 2 +- .../boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts | 2 +- 22 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index e6d5bc0f7a61..d1f415acd7b5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -53,7 +53,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index 0af6dcdf7515..dec9960a7440 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -41,7 +41,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index bfb806cf6d7a..fd3794678c33 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -52,7 +52,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index 4f8529d5ac00..c8303a66438d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -68,7 +68,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 50ed2e9f10ed..6c65d5bc16ba 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -79,7 +79,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts index 0a5607f73049..c6007df99938 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts @@ -98,7 +98,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index 1128030e4c25..b407e1dd08a7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -74,7 +74,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 57ac18738c99..7b01f68cf7f0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -120,14 +120,14 @@ }; }; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -216,21 +216,21 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_alert1: cpu_alert1 { + cpu_alert1: cpu-alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts index 4c3921ac236c..b69032c44557 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -68,7 +68,7 @@ states = <1100000 0>, <1300000 1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts index a3e040da38a0..3a7ee44708a2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -103,7 +103,7 @@ states = <1100000 0x0>, <1300000 0x1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ post-power-on-delay-ms = <200>; @@ -170,7 +170,7 @@ non-removable; status = "okay"; - rtl8189etv: sdio_wifi@1 { + rtl8189etv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index d7f8bad6bb98..b699bb900e13 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -85,7 +85,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts index 7ec5ac850a0d..ae85131aac9c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts @@ -97,7 +97,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts index 22530ace12d5..734481e998b8 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts @@ -52,7 +52,7 @@ regulator-max-microvolt = <3300000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 381d58cea092..3be1e8c2fdb9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -34,7 +34,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 6fc65e8db220..6c3bfe3d09d9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -33,7 +33,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts index fb31dcb1cb6d..a3f65a45bd26 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts @@ -11,7 +11,7 @@ serial1 = &uart1; /* BT-UART */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi index 92745128fcfe..13b07141c334 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi @@ -32,7 +32,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index 1b6e5595ac6e..66fe03910d5e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -11,7 +11,7 @@ model = "Pine H64 model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 1ffd68f43f87..3910393be1f9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -22,7 +22,7 @@ stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index d11e5041bae9..8a8591c4e7dd 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -68,7 +68,7 @@ status = "disabled"; }; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts index ac0a2b7ea6f3..a1d0cac4d244 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-transpeed-8k618-t.dts @@ -41,7 +41,7 @@ regulator-always-on; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts index b6e3c169797f..c204dd43c726 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h64-remix-mini-pc.dts @@ -42,7 +42,7 @@ regulator-always-on; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ post-power-on-delay-ms = <200>; From f5217bc4c94ee0ac846a9fabd63e69d658f44ccc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 17 Mar 2024 19:41:29 +0100 Subject: [PATCH 443/969] arm64: dts: allwinner: Orange Pi: delete node by phandle Delete node via phandle, not via full node path, to avoid easy mistakes - if original node name changes, such deletion would be ineffective and not reported by the dtc as error. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240317184130.157695-3-krzysztof.kozlowski@linaro.org Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts index 3356f4210d45..067a2ecbc0a4 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts @@ -43,11 +43,12 @@ /* Orange Pi R1 is based on Orange Pi Zero design */ #include "sun8i-h2-plus-orangepi-zero.dts" +/delete-node/ ®_vcc_wifi; + / { model = "Xunlong Orange Pi R1"; compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; - /delete-node/ reg_vcc_wifi; /* * Ths pin of this regulator is the same with the Wi-Fi extra From 0f47ef3ff1bdd743940325136c42164f283bf588 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 17 Mar 2024 19:41:30 +0100 Subject: [PATCH 444/969] arm: dts: allwinner: drop underscore in node names Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for pwrseq node, because generic naming is favored by Devicetree spec. All the clocks affected by this change use clock-output-names, so resulting clock name should not change. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240317184130.157695-4-krzysztof.kozlowski@linaro.org Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/allwinner/sun5i-a13.dtsi | 4 ++-- .../boot/dts/allwinner/sun5i-gr8-chip-pro.dts | 2 +- arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts | 2 +- .../boot/dts/allwinner/sun6i-a31-hummingbird.dts | 4 ++-- arch/arm/boot/dts/allwinner/sun6i-a31.dtsi | 16 ++++++++-------- .../dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts | 2 +- .../dts/allwinner/sun7i-a20-bananapi-m1-plus.dts | 2 +- .../boot/dts/allwinner/sun7i-a20-cubietruck.dts | 2 +- .../boot/dts/allwinner/sun7i-a20-hummingbird.dts | 4 ++-- .../allwinner/sun7i-a20-olimex-som-evb-emmc.dts | 2 +- .../sun7i-a20-olimex-som204-evb-emmc.dts | 2 +- .../allwinner/sun7i-a20-olimex-som204-evb.dts | 4 ++-- .../dts/allwinner/sun7i-a20-olinuxino-lime2.dts | 2 +- .../dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts | 2 +- arch/arm/boot/dts/allwinner/sun7i-a20.dtsi | 4 ++-- arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi | 14 +++++++------- .../sun8i-a23-polaroid-mid2407pxe03.dts | 4 ++-- .../sun8i-a23-polaroid-mid2809pxe04.dts | 4 ++-- .../boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts | 2 +- .../dts/allwinner/sun8i-a33-inet-d978-rev2.dts | 2 +- arch/arm/boot/dts/allwinner/sun8i-a33.dtsi | 10 +++++----- .../dts/allwinner/sun8i-a83t-bananapi-m3.dts | 2 +- .../dts/allwinner/sun8i-a83t-cubietruck-plus.dts | 2 +- .../boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 2 +- arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 8 ++++---- .../allwinner/sun8i-h2-plus-bananapi-m2-zero.dts | 2 +- .../dts/allwinner/sun8i-h2-plus-orangepi-r1.dts | 2 +- .../allwinner/sun8i-h2-plus-orangepi-zero.dts | 6 +++--- .../boot/dts/allwinner/sun8i-h3-beelink-x2.dts | 4 ++-- .../boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 4 ++-- .../dts/allwinner/sun8i-h3-nanopi-m1-plus.dts | 4 ++-- .../dts/allwinner/sun8i-h3-nanopi-neo-air.dts | 2 +- .../boot/dts/allwinner/sun8i-h3-nanopi-r1.dts | 2 +- .../boot/dts/allwinner/sun8i-h3-orangepi-2.dts | 4 ++-- .../dts/allwinner/sun8i-h3-orangepi-lite.dts | 2 +- .../dts/allwinner/sun8i-h3-orangepi-pc-plus.dts | 2 +- .../allwinner/sun8i-h3-orangepi-zero-plus2.dts | 2 +- arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi | 4 ++-- .../dts/allwinner/sun8i-r16-bananapi-m2m.dts | 2 +- arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts | 2 +- .../allwinner/sun8i-r40-bananapi-m2-ultra.dts | 2 +- .../boot/dts/allwinner/sun8i-r40-oka40i-c.dts | 2 +- .../arm/boot/dts/allwinner/sun8i-s3-pinecube.dts | 2 +- arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 4 ++-- .../allwinner/sun8i-v40-bananapi-m2-berry.dts | 2 +- arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 4 ++-- .../dts/allwinner/sunxi-bananapi-m2-plus.dtsi | 2 +- .../dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi | 2 +- arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 4 ++-- 49 files changed, 86 insertions(+), 86 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi b/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi index 3325ab07094a..2c9152b151be 100644 --- a/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/allwinner/sun5i-a13.dtsi @@ -62,14 +62,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; diff --git a/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts index 5c3562b85a5b..ffbd99c176db 100644 --- a/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/allwinner/sun5i-gr8-chip-pro.dts @@ -77,7 +77,7 @@ }; }; - mmc0_pwrseq: mmc0_pwrseq { + mmc0_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ }; diff --git a/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts index 4192c23848c3..8c784a2c086e 100644 --- a/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/allwinner/sun5i-r8-chip.dts @@ -77,7 +77,7 @@ }; }; - mmc0_pwrseq: mmc0_pwrseq { + mmc0_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ }; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts index 236ebfc06192..5bce7a32651e 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts @@ -109,7 +109,7 @@ }; }; - reg_vga_3v3: vga_3v3_regulator { + reg_vga_3v3: vga-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "vga-3v3"; regulator-min-microvolt = <3300000>; @@ -119,7 +119,7 @@ gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ }; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi index 5cce4918f84c..f0145d6b9c53 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/allwinner/sun6i-a31.dtsi @@ -179,14 +179,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <70000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; @@ -1318,7 +1318,7 @@ compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; - ar100: ar100_clk { + ar100: ar100-clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; clocks = <&rtc CLK_OSC32K>, <&osc24M>, @@ -1327,7 +1327,7 @@ clock-output-names = "ar100"; }; - ahb0: ahb0_clk { + ahb0: ahb0-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -1336,14 +1336,14 @@ clock-output-names = "ahb0"; }; - apb0: apb0_clk { + apb0: apb0-clk { compatible = "allwinner,sun6i-a31-apb0-clk"; #clock-cells = <0>; clocks = <&ahb0>; clock-output-names = "apb0"; }; - apb0_gates: apb0_gates_clk { + apb0_gates: apb0-gates-clk { compatible = "allwinner,sun6i-a31-apb0-gates-clk"; #clock-cells = <1>; clocks = <&apb0>; @@ -1353,14 +1353,14 @@ "apb0_i2c"; }; - ir_clk: ir_clk { + ir_clk: ir-clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; clocks = <&rtc CLK_OSC32K>, <&osc24M>; clock-output-names = "ir"; }; - apb0_rst: apb0_rst { + apb0_rst: apb0-rst { compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts index 96554ab4f6d3..f63d67ec9887 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-sinovoip-bpi-m2.dts @@ -75,7 +75,7 @@ }; }; - mmc2_pwrseq: mmc2_pwrseq { + mmc2_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ }; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts index caa935ca4f19..f2d7fab9978d 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapi-m1-plus.dts @@ -86,7 +86,7 @@ }; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ }; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts index 52160e368304..be9b31d0f4b5 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts @@ -96,7 +96,7 @@ }; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ clocks = <&ccu CLK_OUT_A>; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts index 3def2a330598..f1e26b75cd90 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-hummingbird.dts @@ -65,7 +65,7 @@ stdout-path = "serial0:115200n8"; }; - reg_mmc3_vdd: mmc3_vdd { + reg_mmc3_vdd: regulator-mmc3-vdd { compatible = "regulator-fixed"; regulator-name = "mmc3_vdd"; regulator-min-microvolt = <3000000>; @@ -74,7 +74,7 @@ gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ }; - reg_gmac_vdd: gmac_vdd { + reg_gmac_vdd: regulator-gmac-vdd { compatible = "regulator-fixed"; regulator-name = "gmac_vdd"; regulator-min-microvolt = <3000000>; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts index 20bf09b2226c..fb835730bbc4 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb-emmc.dts @@ -14,7 +14,7 @@ model = "Olimex A20-Olimex-SOM-EVB-eMMC"; compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20"; - mmc2_pwrseq: mmc2_pwrseq { + mmc2_pwrseq: pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts index a59755a2e7a9..e8977c2fe798 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb-emmc.dts @@ -13,7 +13,7 @@ model = "Olimex A20-SOM204-EVB-eMMC"; compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; - mmc2_pwrseq: mmc2_pwrseq { + mmc2_pwrseq: pwrseq-1 { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts index 54af6c18075b..a55406657449 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts @@ -65,7 +65,7 @@ }; }; - rtl_pwrseq: rtl_pwrseq { + rtl_pwrseq: pwrseq-0 { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; }; @@ -177,7 +177,7 @@ non-removable; status = "okay"; - rtl8723bs: sdio_wifi@1 { + rtl8723bs: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts index ecb91fb899ff..435a189332e8 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts @@ -82,7 +82,7 @@ }; }; - reg_axp_ipsout: axp_ipsout { + reg_axp_ipsout: regulator-axp-ipsout { compatible = "regulator-fixed"; regulator-name = "axp-ipsout"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts index 3bfae98f3cc3..29199b6a3b4a 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/boot/dts/allwinner/sun7i-a20-wits-pro-a20-dkt.dts @@ -60,7 +60,7 @@ stdout-path = "serial0:115200n8"; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi b/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi index 5574299685ab..5f44f09c5545 100644 --- a/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/allwinner/sun7i-a20.dtsi @@ -153,14 +153,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi index cd4bf60dbb3c..2af8382ccdf5 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-a33.dtsi @@ -108,7 +108,7 @@ #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -116,7 +116,7 @@ clock-output-names = "osc24M"; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -733,7 +733,7 @@ compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; - ar100: ar100_clk { + ar100: ar100-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -742,7 +742,7 @@ clock-output-names = "ar100"; }; - ahb0: ahb0_clk { + ahb0: ahb0-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -751,14 +751,14 @@ clock-output-names = "ahb0"; }; - apb0: apb0_clk { + apb0: apb0-clk { compatible = "allwinner,sun8i-a23-apb0-clk"; #clock-cells = <0>; clocks = <&ahb0>; clock-output-names = "apb0"; }; - apb0_gates: apb0_gates_clk { + apb0_gates: apb0-gates-clk { compatible = "allwinner,sun8i-a23-apb0-gates-clk"; #clock-cells = <1>; clocks = <&apb0>; @@ -767,7 +767,7 @@ "apb0_i2c"; }; - apb0_rst: apb0_rst { + apb0_rst: apb0-rst { compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts index d5f6aebd7216..0c585a6d990d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2407pxe03.dts @@ -52,7 +52,7 @@ ethernet0 = &esp8089; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ /* The esp8089 needs 200 ms after driving wifi-en high */ @@ -76,7 +76,7 @@ non-removable; status = "okay"; - esp8089: sdio_wifi@1 { + esp8089: wifi@1 { compatible = "esp,esp8089"; reg = <1>; esp,crystal-26M-en = <2>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts index 9f9232a2fefb..63cb4e194a03 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a23-polaroid-mid2809pxe04.dts @@ -52,7 +52,7 @@ ethernet0 = &esp8089; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ /* The esp8089 needs 200 ms after driving wifi-en high */ @@ -69,7 +69,7 @@ non-removable; status = "okay"; - esp8089: sdio_wifi@1 { + esp8089: wifi@1 { compatible = "esp,esp8089"; reg = <1>; esp,crystal-26M-en = <2>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts index 2dfdd0a3151e..f00ce03ffc84 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-ga10h-v1.1.dts @@ -85,7 +85,7 @@ non-removable; status = "okay"; - rtl8703as: sdio_wifi@1 { + rtl8703as: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts index 065cb620aa99..162ba93f7484 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a33-inet-d978-rev2.dts @@ -78,7 +78,7 @@ non-removable; status = "okay"; - rtl8723bs: sdio_wifi@1 { + rtl8723bs: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi index 30fdd2703b1f..36b2d78cdab9 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a33.dtsi @@ -323,35 +323,35 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - gpu_alert0: gpu_alert0 { + gpu_alert0: gpu-alert0 { /* milliCelsius */ temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_alert1: cpu_alert1 { + cpu_alert1: cpu-alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; - gpu_alert1: gpu_alert1 { + gpu_alert1: gpu-alert1 { /* milliCelsius */ temperature = <95000>; hysteresis = <2000>; type = "hot"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts index 8d56b103f063..32e811fa23e2 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts @@ -95,7 +95,7 @@ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts index 870993393fc2..d5e6ddaffbce 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts @@ -144,7 +144,7 @@ compatible = "linux,spdif-dit"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts index a7d4ca308990..43982b106a4d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts @@ -123,7 +123,7 @@ vin-supply = <®_vbat>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi index 94eb3bfc989e..addf0cb0f465 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi @@ -164,7 +164,7 @@ ranges; /* TODO: PRCM block has a mux for this. */ - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -177,14 +177,14 @@ * It is an internal RC-based oscillator. * TODO: Its controls are in the PRCM block. */ - osc16M: osc16M_clk { + osc16M: osc16M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16000000>; clock-output-names = "osc16M"; }; - osc16Md512: osc16Md512_clk { + osc16Md512: osc16Md512-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <512>; @@ -1127,7 +1127,7 @@ #reset-cells = <1>; }; - r_cpucfg@1f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun8i-a83t-r-cpucfg"; reg = <0x1f01c00 0x400>; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts index d729b7c705db..d3a7c9fa23e4 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts @@ -103,7 +103,7 @@ cpu-supply = <®_vcc1v2>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts index 067a2ecbc0a4..79b03b31c5eb 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-r1.dts @@ -90,7 +90,7 @@ vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; - rtl8189etv: sdio_wifi@1 { + rtl8189etv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts index 3706216ffb40..1b001f2ad0ef 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts @@ -80,7 +80,7 @@ }; }; - reg_vcc_wifi: reg_vcc_wifi { + reg_vcc_wifi: reg-vcc-wifi { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -105,7 +105,7 @@ states = <1100000 0>, <1300000 1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; post-power-on-delay-ms = <200>; @@ -149,7 +149,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - xr819: sdio_wifi@1 { + xr819: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts index a6d38ecee141..5b77300307de 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts @@ -122,7 +122,7 @@ compatible = "linux,spdif-dit"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; @@ -185,7 +185,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - sdiowifi: sdio_wifi@1 { + sdiowifi: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts index 343b02b97155..2b0566d4b386 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts @@ -87,7 +87,7 @@ vin-supply = <®_vcc5v0>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; @@ -119,7 +119,7 @@ non-removable; status = "okay"; - sdio_wifi: sdio_wifi@1 { + sdio_wifi: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts index 4ba533b0340f..59bd0746acf8 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts @@ -62,7 +62,7 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; @@ -132,7 +132,7 @@ non-removable; status = "okay"; - sdio_wifi: sdio_wifi@1 { + sdio_wifi: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts index 9e1a33f94cad..6d85370e04f1 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts @@ -73,7 +73,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts index 42cd1131adf3..870649760f70 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-r1.dts @@ -43,7 +43,7 @@ <1300000 0x1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts index f1f9dbead32a..d2ae47b074bf 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts @@ -105,7 +105,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ }; @@ -169,7 +169,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189: sdio_wifi@1 { + rtl8189: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts index 305b34a321f5..6a4316a52469 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts @@ -143,7 +143,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts index babf4cf1b2f6..8a49b3376dfc 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts @@ -63,7 +63,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts index 561ea1d2f861..7a6444a10e25 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts @@ -92,7 +92,7 @@ regulator-max-microvolt = <3300000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi b/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi index 3d9a1524e17e..272584881bb2 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-q8-common.dtsi @@ -62,7 +62,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; /* * Q8 boards use various PL# pins as wifi-en. On other boards @@ -94,7 +94,7 @@ non-removable; status = "okay"; - sdio_wifi: sdio_wifi@1 { + sdio_wifi: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts index bc394686fedb..f4bf46b35bec 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-r16-bananapi-m2m.dts @@ -88,7 +88,7 @@ regulator-max-microvolt = <5000000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts b/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts index 95543a9c2118..75067522ff59 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-r16-parrot.dts @@ -75,7 +75,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts index 28197bbcb1d5..cd2351acc32f 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts @@ -100,7 +100,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ clocks = <&ccu CLK_OUTA>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts index 0bd1336206b8..15b0b4de626a 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-oka40i-c.dts @@ -62,7 +62,7 @@ regulator-max-microvolt = <5000000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN clocks = <&ccu CLK_OUTA>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts index 20966e954eda..e0d4404b5957 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts @@ -51,7 +51,7 @@ startup-delay-us = <200000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi index e8a04476b776..9e13c2aa8911 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi @@ -98,7 +98,7 @@ #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -106,7 +106,7 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts index 434871040aca..6575ef274453 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts @@ -94,7 +94,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ clocks = <&ccu CLK_OUTA>; diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi index 7d3f3300f431..a1ae0929cec9 100644 --- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi @@ -196,14 +196,14 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: mii_phy_tx_clk { + mii_phy_tx_clk: mii-phy-tx-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: gmac_int_tx_clk { + gmac_int_tx_clk: gmac-int-tx-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; diff --git a/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi index 1d1d127cf38f..873817ddb4ea 100644 --- a/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/allwinner/sunxi-bananapi-m2-plus.dtsi @@ -98,7 +98,7 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi index 60804b0e6c56..be5f5528a118 100644 --- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi +++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5-emlid-neutis.dtsi @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi index ade1cd50e445..7df60515a903 100644 --- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi @@ -83,7 +83,7 @@ #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -91,7 +91,7 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; From 1428f0c19f9ce06c33f79fff783788444f27ac31 Mon Sep 17 00:00:00 2001 From: Frank Oltmanns Date: Sun, 10 Mar 2024 14:21:15 +0100 Subject: [PATCH 445/969] arm64: dts: allwinner: a64: Run GPU at 432 MHz The Allwinner A64's GPU has currently three operating points. However, the BSP runs the GPU fixed at 432 MHz. In addition, at least one of the devices using that SoC - the pinephone - shows unstabilities (see link) that can be circumvented by running the GPU at a fixed rate. Therefore, remove the other two operating points from the GPU OPP table, so that the GPU runs at a fixed rate of 432 MHz. Link: https://gitlab.com/postmarketOS/pmaports/-/issues/805 Acked-by: Erico Nunes Signed-off-by: Frank Oltmanns Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-5-46fc80c83637@oltmanns.dev Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 7b01f68cf7f0..ce4aa44c3353 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -107,14 +107,6 @@ gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - }; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - }; - opp-432000000 { opp-hz = /bits/ 64 <432000000>; }; From 5bdeb3d2e240e599a9cb4315a013e3bd5436447d Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 29 Mar 2024 10:38:25 +0000 Subject: [PATCH 446/969] arm64: dts: allwinner: h616: Fix I2C0 pins Currently we specify the pins for the I2C0 function as PI6 and PI7, even though they are actually PI5 and PI6. Linux' pinctrl driver and the H616 user manual confirm this. Fix the pin names in the pins property. None of the existing DTs in the tree seems to use I2C0, which explains why this went unnoticed. Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file") Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240329103825.25463-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index b2e85e52d1a1..a061b69c07c2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -194,7 +194,7 @@ }; i2c0_pins: i2c0-pins { - pins = "PI6", "PI7"; + pins = "PI5", "PI6"; function = "i2c0"; }; From deff401b14e2d832b25b55862ad6c73378fe034e Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 3 Apr 2024 12:56:23 +0200 Subject: [PATCH 447/969] ARM: configs: sunxi: Enable DRM_DW_HDMI Commit 4fc8cb47fcfd ("drm/display: Move HDMI helpers into display-helper module") turned the DRM_DW_HDMI dependency of DRM_SUN8I_DW_HDMI into a depends on which ended up disabling the driver in the defconfig. Make sure it's still enabled. Fixes: 4fc8cb47fcfd ("drm/display: Move HDMI helpers into display-helper module") Reported-by: Mark Brown Reported-by: Alexander Stein Signed-off-by: Maxime Ripard Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240403-fix-dw-hdmi-kconfig-v1-5-afbc4a835c38@kernel.org Signed-off-by: Jernej Skrabec --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index bddc82f78942..a83d29fed175 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -110,6 +110,7 @@ CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_SIMPLE_BRIDGE=y +CONFIG_DRM_DW_HDMI=y CONFIG_DRM_LIMA=y CONFIG_FB_SIMPLE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y From fa4c4df71498cd69fe01c831f60470d1622a4a33 Mon Sep 17 00:00:00 2001 From: Denis Burkov Date: Mon, 15 Apr 2024 22:34:15 +0500 Subject: [PATCH 448/969] dt-bindings: arm: sunxi: Add PocketBook 614 Plus Add a new board name. Signed-off-by: Denis Burkov Acked-by: Rob Herring Link: https://lore.kernel.org/r/20240415173416.13838-1-hitechshell@mail.ru Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 09d835db6db5..43491e7f8a5e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -774,6 +774,11 @@ properties: - const: pocketbook,touch-lux-3 - const: allwinner,sun5i-a13 + - description: PocketBook 614 Plus + items: + - const: pocketbook,614-plus + - const: allwinner,sun5i-a13 + - description: Point of View Protab2-IPS9 items: - const: pov,protab2-ips9 From caa67b061f60bc0d44e0bb53179a5415da7a913d Mon Sep 17 00:00:00 2001 From: Denis Burkov Date: Mon, 15 Apr 2024 22:34:16 +0500 Subject: [PATCH 449/969] ARM: dts: sun5i: Add PocketBook 614 Plus support What works: - Serial console - mmc0, mmc2 (both microSD card slots on the board) - All buttons (gpio and lradc based) - Power LED - PMIC - RTC - USB OTG/gadgets mode Signed-off-by: Denis Burkov Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240415173416.13838-2-hitechshell@mail.ru Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/allwinner/Makefile | 1 + .../sun5i-a13-pocketbook-614-plus.dts | 218 ++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-614-plus.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 2d26c3397f14..4247f19b1adc 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb \ sun5i-a13-pocketbook-touch-lux-3.dtb \ + sun5i-a13-pocketbook-614-plus.dtb \ sun5i-a13-q8-tablet.dtb \ sun5i-a13-utoo-p66.dtb \ sun5i-gr8-chip-pro.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-614-plus.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-614-plus.dts new file mode 100644 index 000000000000..ab8d138dc11d --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-614-plus.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 Denis Burkov + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include +#include + +/ { + model = "PocketBook 614 Plus"; + compatible = "pocketbook,614-plus", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + linux,default-trigger = "default-on"; + gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "Right"; + linux,code = ; + gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; /* PG9 */ + }; + + key-1 { + label = "Left"; + linux,code = ; + gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ + }; + }; + + reg_3v3_mmc0: regulator-mmc0 { + compatible = "regulator-fixed"; + regulator-name = "vdd-mmc0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */ + vin-supply = <®_vcc3v3>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-300 { + label = "Down"; + linux,code = ; + channel = <0>; + voltage = <300000>; + }; + + button-700 { + label = "Up"; + linux,code = ; + channel = <0>; + voltage = <700000>; + }; + + button-1000 { + label = "Left"; + linux,code = ; + channel = <0>; + voltage = <1000000>; + }; + + button-1200 { + label = "Menu"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; + + button-1500 { + label = "Right"; + linux,code = ; + channel = <0>; + voltage = <1500000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_3v3_mmc0>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pc_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ +}; + +®_usb1_vbus { + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&battery_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; From 212729551c4186a1a1cbd80379375b1b54488369 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:10 +0100 Subject: [PATCH 450/969] dt-bindings: arm: qcom: Add Xperia 1 V Document the SM8550 SONY Xperia 1 V (PDX234) board. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240210-topic-1v-v1-2-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1646e5bd23d8..bdc4a8d5388c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -996,6 +996,7 @@ properties: - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd + - sony,pdx234 - const: qcom,sm8550 - items: From 91fc74458d833dbc999aa04ca34c2a197711a0b6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:11 +0100 Subject: [PATCH 451/969] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-3-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5cae8d773cec..463fc1e8bc91 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -812,6 +812,7 @@ dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -823,6 +824,7 @@ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1322,6 +1324,7 @@ dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1335,6 +1338,7 @@ iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; From 93395f9a8d52b89868d75e278adaf002f99dec22 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:12 +0100 Subject: [PATCH 452/969] arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent. Mark it as such. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-4-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 463fc1e8bc91..d60984d5ae4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3972,6 +3972,7 @@ , , ; + dma-coherent; }; intc: interrupt-controller@17100000 { From d18b5477dcea7775a562b3ba7aaa68772c8980ba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:13 +0100 Subject: [PATCH 453/969] arm64: dts: qcom: sm8550: Add missing DWC3 quirks As expected, Qualcomm DWC3 implementation come with a sizable number of quirks. Make sure to account for all of them. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-5-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d60984d5ae4d..a72627f4d8cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3231,12 +3231,20 @@ reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x40 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; ports { #address-cells = <1>; From 6e4f7e53991ca7e70dc7d5d9d66c833091e1f6ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:14 +0100 Subject: [PATCH 454/969] arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent In a fairly new development, Qualcomm somehow made the DWC3 block cache-coherent. Annotate that. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-6-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a72627f4d8cd..5adb9b178b05 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3245,6 +3245,7 @@ snps,usb2-lpm-disable; snps,has-lpm-erratum; tx-fifo-resize; + dma-coherent; ports { #address-cells = <1>; From 39c596304e44781c1950ea0cbf178d6433ff9c71 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:15 +0100 Subject: [PATCH 455/969] arm64: dts: qcom: Add SM8550 Xperia 1 V Add support for Sony Xperia 1 V, a.k.a PDX234. This device is a part of the SoMC SM8550 Yodo platform. This commit brings support for: * Remoteprocs (sans modem for now) * Flash LED (the notification LED is gone :((((() * SD Card * USB (*including SuperSpeed*) + PMIC_GLINK (it's funky, requires a replug with an cable flip sometimes..) * Most regulators * Part of I2C-connected peripherals (notably no touch due to a driver bug) * PCIe0 (PCIe1 is unused) Do note display via simplefb is not supported, as the display is blanked upon exiting XBL. To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8550-sony-xperia-\ yodo-pdx234.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 2 \ -o boot.img-sony-xperia-pdx234 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system \ vbmeta_system.img fastboot flash boot boot.img-sony-xperia-pdx234 fastboot erase vendor_boot fastboot erase recovery fastboot flash dtbo emptydtbo.img fastboot erase init_boot // ? I don't remember if it's necessary, sorry fastboot continue Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-7-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm8550-sony-xperia-yodo-pdx234.dts | 779 ++++++++++++++++++ 2 files changed, 780 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7d40ec5e7d21..f63abb43e9fe 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts new file mode 100644 index 000000000000..85e0d3d66e16 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +/* TODO: Only one SID of PMR735D seems accessible? */ + +/delete-node/ &hwfence_shbuf; +/delete-node/ &mpss_mem; +/delete-node/ &rmtfs_mem; +/ { + model = "Sony Xperia 1 V"; + compatible = "sony,pdx234", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c16 = &i2c_hub_2; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + pinctrl-names = "default"; + + key-camera-focus { + label = "Camera Focus"; + linux,code = ; + gpios = <&pm8550b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + mpss_mem: mpss-region@89800000 { + reg = <0x0 0x89800000 0x0 0x10800000>; + no-map; + }; + + splash@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0x0 0xe6440000 0x0 0x2dd000>; + no-map; + }; + + rmtfs_mem: memory@f8b00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8b00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + + ramoops@ffd00000 { + compatible = "ramoops"; + reg = <0x0 0xffd00000 0x0 0xc0000>; + console-size = <0x40000>; + record-size = <0x1000>; + pmsg-size = <0x40000>; + ecc-size = <16>; + }; + + rdtag-store-region@ffdc0000 { + reg = <0x0 0xffdc0000 0x0 0x40000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + pm8550_bob1: bob1 { + regulator-name = "pm8550_bob1"; + regulator-min-microvolt = <3416000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + /* TODO: bob2 @ 2.704-3.008V doesn't fall into the vreg driver constraints */ + + pm8550_l1: ldo1 { + regulator-name = "pm8550_l1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l2: ldo2 { + regulator-name = "pm8550_l2"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + /* L4 exists in cmd-db, but the board seems to crash on access */ + + pm8550_l5: ldo5 { + regulator-name = "pm8550_l5"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + pm8550_l6: ldo6 { + regulator-name = "pm8550_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l7: ldo7 { + regulator-name = "pm8550_l7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l8: ldo8 { + regulator-name = "pm8550_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l9: ldo9 { + regulator-name = "pm8550_l9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l10: ldo10 { + regulator-name = "pm8550_l10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l11: ldo11 { + regulator-name = "pm8550_l11"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + pm8550_l12: ldo12 { + regulator-name = "pm8550_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l13: ldo13 { + regulator-name = "pm8550_l13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + pm8550_l14: ldo14 { + regulator-name = "pm8550_l14"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + pm8550_l15: ldo15 { + regulator-name = "pm8550_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l16: ldo16 { + regulator-name = "pm8550_l16"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + pm8550_l17: ldo17 { + regulator-name = "pm8550_l17"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + pm8550vs_0_l1: ldo1 { + regulator-name = "pm8550vs_0_l1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8550vs_0_l3: ldo3 { + regulator-name = "pm8550vs_0_l3"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + pm8550vs_1_l1: ldo1 { + regulator-name = "pm8550vs_1_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + /* L3 exists in cmd-db, but the board seems to crash on access */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + pm8550vs_2_s4: smps4 { + regulator-name = "pm8550vs_2_s4"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_s5: smps5 { + regulator-name = "pm8550vs_2_s5"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l1: ldo1 { + regulator-name = "pm8550vs_2_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l2: ldo2 { + regulator-name = "pm8550vs_2_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <968000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l3: ldo3 { + regulator-name = "pm8550vs_2_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + pm8550ve_s4: smps4 { + regulator-name = "pm8550ve_s4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + pm8550ve_l1: ldo1 { + regulator-name = "pm8550ve_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550ve_l2: ldo2 { + regulator-name = "pm8550ve_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550ve_l3: ldo3 { + regulator-name = "pm8550ve_l3"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + pm8550vs_3_s1: smps1 { + regulator-name = "pm8550vs_3_s1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s2: smps2 { + regulator-name = "pm8550vs_3_s2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s3: smps3 { + regulator-name = "pm8550vs_3_s3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s4: smps4 { + regulator-name = "pm8550vs_3_s4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s5: smps5 { + regulator-name = "pm8550vs_3_s5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s6: smps6 { + regulator-name = "pm8550vs_3_s6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l1: ldo1 { + regulator-name = "pm8550vs_3_l1"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l2: ldo2 { + regulator-name = "pm8550vs_3_l2"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l3: ldo3 { + regulator-name = "pm8550vs_3_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* TODO: Unknown PMIC @ k, l, PM8010 @ m, n */ +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&i2c_hub_2 { + clock-frequency = <400000>; + status = "okay"; + + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&cam_pwr_a_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <1000000>; + status = "okay"; + + /* NXP NFC @ 28 */ +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + /* LX Semi SW82907 touchscreen @ 28 */ +}; + +&i2c10 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + +&i2c11 { + clock-frequency = <1000000>; + status = "okay"; + + cs35l41_l: speaker-amp@30 { + compatible = "cirrus,cs35l45"; + reg = <0x30>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; + + cs35l41_r: speaker-amp@31 { + compatible = "cirrus,cs35l45"; + reg = <0x31>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&pm8550vs_2_l1>; + vdda-pll-supply = <&pm8550vs_2_l3>; + + status = "okay"; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + +&pm8550_gpios { + vol_down_n: volume-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio12"; + function = "normal"; + power-source = <1>; + bias-pull-down; + output-disable; + input-enable; + }; +}; + +&pm8550b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio7"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550vs_g_gpios { + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio4"; + function = "normal"; + power-source = <0x01>; + drive-push-pull; + output-low; + qcom,drive-strength = ; + }; +}; + +&pm8550b_eusb2_repeater { + qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>; + qcom,tune-usb2-amplitude = /bits/ 8 <0xf>; + qcom,tune-usb2-preem = /bits/ 8 <0x7>; + vdd18-supply = <&pm8550_l15>; + vdd3-supply = <&pm8550_l5>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/Sony/yodo/adsp.mbn", + "qcom/sm8550/Sony/yodo/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/Sony/yodo/cdsp.mbn", + "qcom/sm8550/Sony/yodo/cdsp_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&pm8550_l9>; + vqmmc-supply = <&pm8550_l8>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&pm8550vs_2_l1>; + vdda12-supply = <&pm8550vs_2_l3>; + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&pm8550vs_2_l3>; + vdda-pll-supply = <&pm8550ve_l3>; + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; From 8d0f9a6639f5083453602375ce9d3b71ef93ac73 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 6 Mar 2024 19:14:46 -0800 Subject: [PATCH 456/969] rcutorture: Remove extraneous rcu_torture_pipe_update_one() READ_ONCE() The rcu_torture_pipe_update_one() cannot run concurrently with any updates of ->rtort_pipe_count, so this commit removes the extraneous READ_ONCE() from the read from this field. Reported-by: Linus Torvalds Closes: https://lore.kernel.org/lkml/CAHk-=wiX_zF5Mpt8kUm_LFQpYY-mshrXJPOe+wKNwiVhEUcU9g@mail.gmail.com/ Signed-off-by: Paul E. McKenney Reviewed-by: Joel Fernandes (Google) Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index d8c12eba35b7..6b821a7037b0 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -461,7 +461,7 @@ rcu_torture_pipe_update_one(struct rcu_torture *rp) WRITE_ONCE(rp->rtort_chkp, NULL); smp_store_release(&rtrcp->rtc_ready, 1); // Pair with smp_load_acquire(). } - i = READ_ONCE(rp->rtort_pipe_count); + i = rp->rtort_pipe_count; if (i > RCU_TORTURE_PIPE_LEN) i = RCU_TORTURE_PIPE_LEN; atomic_inc(&rcu_torture_wcount[i]); From 8b9b443fa860276822b25057cb3ff3b28734dec0 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 6 Mar 2024 19:21:47 -0800 Subject: [PATCH 457/969] rcutorture: Fix rcu_torture_one_read() pipe_count overflow comment The "pipe_count > RCU_TORTURE_PIPE_LEN" check has a comment saying "Should not happen, but...". This is only true when testing an RCU whose grace periods are always long enough. This commit therefore fixes this comment. Reported-by: Linus Torvalds Closes: https://lore.kernel.org/lkml/CAHk-=wi7rJ-eGq+xaxVfzFEgbL9tdf6Kc8Z89rCpfcQOKm74Tw@mail.gmail.com/ Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 6b821a7037b0..0cb5452ecd94 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -2000,7 +2000,8 @@ static bool rcu_torture_one_read(struct torture_random_state *trsp, long myid) preempt_disable(); pipe_count = READ_ONCE(p->rtort_pipe_count); if (pipe_count > RCU_TORTURE_PIPE_LEN) { - /* Should not happen, but... */ + // Should not happen in a correct RCU implementation, + // happens quite often for torture_type=busted. pipe_count = RCU_TORTURE_PIPE_LEN; } completed = cur_ops->get_gp_seq(); From a10e3cbf32786cae437e4f370573318721e47c2c Mon Sep 17 00:00:00 2001 From: linke li Date: Wed, 6 Mar 2024 19:51:10 -0800 Subject: [PATCH 458/969] rcutorture: Re-use value stored to ->rtort_pipe_count instead of re-reading Currently, the rcu_torture_pipe_update_one() writes the value (i + 1) to rp->rtort_pipe_count, then immediately re-reads it in order to compare it to RCU_TORTURE_PIPE_LEN. This re-read is pointless because no other update to rp->rtort_pipe_count can occur at this point. This commit therefore instead re-uses the (i + 1) value stored in the comparison instead of re-reading rp->rtort_pipe_count. Signed-off-by: linke li Reviewed-by: Joel Fernandes (Google) Signed-off-by: Paul E. McKenney Cc: Linus Torvalds Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 0cb5452ecd94..dd7d5ba45740 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -467,7 +467,7 @@ rcu_torture_pipe_update_one(struct rcu_torture *rp) atomic_inc(&rcu_torture_wcount[i]); WRITE_ONCE(rp->rtort_pipe_count, i + 1); ASSERT_EXCLUSIVE_WRITER(rp->rtort_pipe_count); - if (rp->rtort_pipe_count >= RCU_TORTURE_PIPE_LEN) { + if (i + 1 >= RCU_TORTURE_PIPE_LEN) { rp->rtort_mbtest = 0; return true; } From e38bf06d509a90c9fc185129ec913beb6de3d428 Mon Sep 17 00:00:00 2001 From: Zqiang Date: Fri, 15 Mar 2024 15:17:10 +0800 Subject: [PATCH 459/969] rcutorture: Use the gp_kthread_dbg operation specified by cur_ops Despite there being a cur_ops->gp_kthread_dbg(), rcu_torture_writer() unconditionally invokes vanilla RCU's show_rcu_gp_kthreads(). This is not at all helpful when some other flavor of RCU is being tested. This commit therefore makes rcu_torture_writer() invoke cur_ops->gp_kthread_dbg() for RCU implementations providing this function. Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index dd7d5ba45740..2f43d31fb7a5 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -1589,7 +1589,8 @@ rcu_torture_writer(void *arg) if (list_empty(&rcu_tortures[i].rtort_free) && rcu_access_pointer(rcu_torture_current) != &rcu_tortures[i]) { tracing_off(); - show_rcu_gp_kthreads(); + if (cur_ops->gp_kthread_dbg) + cur_ops->gp_kthread_dbg(); WARN(1, "%s: rtort_pipe_count: %d\n", __func__, rcu_tortures[i].rtort_pipe_count); rcu_ftrace_dump(DUMP_ALL); } From dddcddef1414be3ebc37a40d13fcc0f6a672ba9f Mon Sep 17 00:00:00 2001 From: Zqiang Date: Mon, 18 Mar 2024 17:34:11 +0800 Subject: [PATCH 460/969] rcutorture: Make rcutorture support print rcu-tasks gp state This commit make rcu-tasks related rcutorture test support rcu-tasks gp state printing when the writer stall occurs or the at the end of rcutorture test, and generate rcu_ops->get_gp_data() operation to simplify the acquisition of gp state for different types of rcutorture tests. Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcu.h | 20 ++++++++++---------- kernel/rcu/rcutorture.c | 26 ++++++++++++++++++-------- kernel/rcu/srcutree.c | 5 +---- kernel/rcu/tasks.h | 21 +++++++++++++++++++++ kernel/rcu/tree.c | 13 +++---------- 5 files changed, 53 insertions(+), 32 deletions(-) diff --git a/kernel/rcu/rcu.h b/kernel/rcu/rcu.h index 86fce206560e..38238e595a61 100644 --- a/kernel/rcu/rcu.h +++ b/kernel/rcu/rcu.h @@ -522,12 +522,18 @@ static inline void show_rcu_tasks_gp_kthreads(void) {} #ifdef CONFIG_TASKS_RCU struct task_struct *get_rcu_tasks_gp_kthread(void); +void rcu_tasks_get_gp_data(int *flags, unsigned long *gp_seq); #endif // # ifdef CONFIG_TASKS_RCU #ifdef CONFIG_TASKS_RUDE_RCU struct task_struct *get_rcu_tasks_rude_gp_kthread(void); +void rcu_tasks_rude_get_gp_data(int *flags, unsigned long *gp_seq); #endif // # ifdef CONFIG_TASKS_RUDE_RCU +#ifdef CONFIG_TASKS_TRACE_RCU +void rcu_tasks_trace_get_gp_data(int *flags, unsigned long *gp_seq); +#endif + #ifdef CONFIG_TASKS_RCU_GENERIC void tasks_cblist_init_generic(void); #else /* #ifdef CONFIG_TASKS_RCU_GENERIC */ @@ -557,8 +563,7 @@ static inline void rcu_set_jiffies_lazy_flush(unsigned long j) { } #endif #if defined(CONFIG_TREE_RCU) -void rcutorture_get_gp_data(enum rcutorture_type test_type, int *flags, - unsigned long *gp_seq); +void rcutorture_get_gp_data(int *flags, unsigned long *gp_seq); void do_trace_rcu_torture_read(const char *rcutorturename, struct rcu_head *rhp, unsigned long secs, @@ -566,8 +571,7 @@ void do_trace_rcu_torture_read(const char *rcutorturename, unsigned long c); void rcu_gp_set_torture_wait(int duration); #else -static inline void rcutorture_get_gp_data(enum rcutorture_type test_type, - int *flags, unsigned long *gp_seq) +static inline void rcutorture_get_gp_data(int *flags, unsigned long *gp_seq) { *flags = 0; *gp_seq = 0; @@ -587,20 +591,16 @@ static inline void rcu_gp_set_torture_wait(int duration) { } #ifdef CONFIG_TINY_SRCU -static inline void srcutorture_get_gp_data(enum rcutorture_type test_type, - struct srcu_struct *sp, int *flags, +static inline void srcutorture_get_gp_data(struct srcu_struct *sp, int *flags, unsigned long *gp_seq) { - if (test_type != SRCU_FLAVOR) - return; *flags = 0; *gp_seq = sp->srcu_idx; } #elif defined(CONFIG_TREE_SRCU) -void srcutorture_get_gp_data(enum rcutorture_type test_type, - struct srcu_struct *sp, int *flags, +void srcutorture_get_gp_data(struct srcu_struct *sp, int *flags, unsigned long *gp_seq); #endif diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 2f43d31fb7a5..85ff8a32f75a 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -381,6 +381,7 @@ struct rcu_torture_ops { void (*gp_kthread_dbg)(void); bool (*check_boost_failed)(unsigned long gp_state, int *cpup); int (*stall_dur)(void); + void (*get_gp_data)(int *flags, unsigned long *gp_seq); long cbflood_max; int irq_capable; int can_boost; @@ -569,6 +570,7 @@ static struct rcu_torture_ops rcu_ops = { .gp_kthread_dbg = show_rcu_gp_kthreads, .check_boost_failed = rcu_check_boost_fail, .stall_dur = rcu_jiffies_till_stall_check, + .get_gp_data = rcutorture_get_gp_data, .irq_capable = 1, .can_boost = IS_ENABLED(CONFIG_RCU_BOOST), .extendables = RCUTORTURE_MAX_EXTEND, @@ -628,6 +630,11 @@ static struct srcu_struct srcu_ctld; static struct srcu_struct *srcu_ctlp = &srcu_ctl; static struct rcu_torture_ops srcud_ops; +static void srcu_get_gp_data(int *flags, unsigned long *gp_seq) +{ + srcutorture_get_gp_data(srcu_ctlp, flags, gp_seq); +} + static int srcu_torture_read_lock(void) { if (cur_ops == &srcud_ops) @@ -736,6 +743,7 @@ static struct rcu_torture_ops srcu_ops = { .call = srcu_torture_call, .cb_barrier = srcu_torture_barrier, .stats = srcu_torture_stats, + .get_gp_data = srcu_get_gp_data, .cbflood_max = 50000, .irq_capable = 1, .no_pi_lock = IS_ENABLED(CONFIG_TINY_SRCU), @@ -774,6 +782,7 @@ static struct rcu_torture_ops srcud_ops = { .call = srcu_torture_call, .cb_barrier = srcu_torture_barrier, .stats = srcu_torture_stats, + .get_gp_data = srcu_get_gp_data, .cbflood_max = 50000, .irq_capable = 1, .no_pi_lock = IS_ENABLED(CONFIG_TINY_SRCU), @@ -882,6 +891,7 @@ static struct rcu_torture_ops tasks_ops = { .call = call_rcu_tasks, .cb_barrier = rcu_barrier_tasks, .gp_kthread_dbg = show_rcu_tasks_classic_gp_kthread, + .get_gp_data = rcu_tasks_get_gp_data, .fqs = NULL, .stats = NULL, .irq_capable = 1, @@ -922,6 +932,7 @@ static struct rcu_torture_ops tasks_rude_ops = { .call = call_rcu_tasks_rude, .cb_barrier = rcu_barrier_tasks_rude, .gp_kthread_dbg = show_rcu_tasks_rude_gp_kthread, + .get_gp_data = rcu_tasks_rude_get_gp_data, .cbflood_max = 50000, .fqs = NULL, .stats = NULL, @@ -974,6 +985,7 @@ static struct rcu_torture_ops tasks_tracing_ops = { .call = call_rcu_tasks_trace, .cb_barrier = rcu_barrier_tasks_trace, .gp_kthread_dbg = show_rcu_tasks_trace_gp_kthread, + .get_gp_data = rcu_tasks_trace_get_gp_data, .cbflood_max = 50000, .fqs = NULL, .stats = NULL, @@ -2264,10 +2276,8 @@ rcu_torture_stats_print(void) int __maybe_unused flags = 0; unsigned long __maybe_unused gp_seq = 0; - rcutorture_get_gp_data(cur_ops->ttype, - &flags, &gp_seq); - srcutorture_get_gp_data(cur_ops->ttype, srcu_ctlp, - &flags, &gp_seq); + if (cur_ops->get_gp_data) + cur_ops->get_gp_data(&flags, &gp_seq); wtp = READ_ONCE(writer_task); pr_alert("??? Writer stall state %s(%d) g%lu f%#x ->state %#x cpu %d\n", rcu_torture_writer_state_getname(), @@ -3390,8 +3400,8 @@ rcu_torture_cleanup(void) fakewriter_tasks = NULL; } - rcutorture_get_gp_data(cur_ops->ttype, &flags, &gp_seq); - srcutorture_get_gp_data(cur_ops->ttype, srcu_ctlp, &flags, &gp_seq); + if (cur_ops->get_gp_data) + cur_ops->get_gp_data(&flags, &gp_seq); pr_alert("%s: End-test grace-period state: g%ld f%#x total-gps=%ld\n", cur_ops->name, (long)gp_seq, flags, rcutorture_seq_diff(gp_seq, start_gp_seq)); @@ -3762,8 +3772,8 @@ rcu_torture_init(void) nrealreaders = 1; } rcu_torture_print_module_parms(cur_ops, "Start of test"); - rcutorture_get_gp_data(cur_ops->ttype, &flags, &gp_seq); - srcutorture_get_gp_data(cur_ops->ttype, srcu_ctlp, &flags, &gp_seq); + if (cur_ops->get_gp_data) + cur_ops->get_gp_data(&flags, &gp_seq); start_gp_seq = gp_seq; pr_alert("%s: Start-test grace-period state: g%ld f%#x\n", cur_ops->name, (long)gp_seq, flags); diff --git a/kernel/rcu/srcutree.c b/kernel/rcu/srcutree.c index e4d673fc30f4..bc4b58b0204e 100644 --- a/kernel/rcu/srcutree.c +++ b/kernel/rcu/srcutree.c @@ -1826,12 +1826,9 @@ static void process_srcu(struct work_struct *work) srcu_reschedule(ssp, curdelay); } -void srcutorture_get_gp_data(enum rcutorture_type test_type, - struct srcu_struct *ssp, int *flags, +void srcutorture_get_gp_data(struct srcu_struct *ssp, int *flags, unsigned long *gp_seq) { - if (test_type != SRCU_FLAVOR) - return; *flags = 0; *gp_seq = rcu_seq_current(&ssp->srcu_sup->srcu_gp_seq); } diff --git a/kernel/rcu/tasks.h b/kernel/rcu/tasks.h index 147b5945d67a..a1af7dadc0f7 100644 --- a/kernel/rcu/tasks.h +++ b/kernel/rcu/tasks.h @@ -1178,6 +1178,13 @@ struct task_struct *get_rcu_tasks_gp_kthread(void) } EXPORT_SYMBOL_GPL(get_rcu_tasks_gp_kthread); +void rcu_tasks_get_gp_data(int *flags, unsigned long *gp_seq) +{ + *flags = 0; + *gp_seq = rcu_seq_current(&rcu_tasks.tasks_gp_seq); +} +EXPORT_SYMBOL_GPL(rcu_tasks_get_gp_data); + /* * Protect against tasklist scan blind spot while the task is exiting and * may be removed from the tasklist. Do this by adding the task to yet @@ -1358,6 +1365,13 @@ struct task_struct *get_rcu_tasks_rude_gp_kthread(void) } EXPORT_SYMBOL_GPL(get_rcu_tasks_rude_gp_kthread); +void rcu_tasks_rude_get_gp_data(int *flags, unsigned long *gp_seq) +{ + *flags = 0; + *gp_seq = rcu_seq_current(&rcu_tasks_rude.tasks_gp_seq); +} +EXPORT_SYMBOL_GPL(rcu_tasks_rude_get_gp_data); + #endif /* #ifdef CONFIG_TASKS_RUDE_RCU */ //////////////////////////////////////////////////////////////////////// @@ -2010,6 +2024,13 @@ struct task_struct *get_rcu_tasks_trace_gp_kthread(void) } EXPORT_SYMBOL_GPL(get_rcu_tasks_trace_gp_kthread); +void rcu_tasks_trace_get_gp_data(int *flags, unsigned long *gp_seq) +{ + *flags = 0; + *gp_seq = rcu_seq_current(&rcu_tasks_trace.tasks_gp_seq); +} +EXPORT_SYMBOL_GPL(rcu_tasks_trace_get_gp_data); + #else /* #ifdef CONFIG_TASKS_TRACE_RCU */ static void exit_tasks_rcu_finish_trace(struct task_struct *t) { } #endif /* #else #ifdef CONFIG_TASKS_TRACE_RCU */ diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c index d9642dd06c25..60e79ed73700 100644 --- a/kernel/rcu/tree.c +++ b/kernel/rcu/tree.c @@ -508,17 +508,10 @@ static struct rcu_node *rcu_get_root(void) /* * Send along grace-period-related data for rcutorture diagnostics. */ -void rcutorture_get_gp_data(enum rcutorture_type test_type, int *flags, - unsigned long *gp_seq) +void rcutorture_get_gp_data(int *flags, unsigned long *gp_seq) { - switch (test_type) { - case RCU_FLAVOR: - *flags = READ_ONCE(rcu_state.gp_flags); - *gp_seq = rcu_seq_current(&rcu_state.gp_seq); - break; - default: - break; - } + *flags = READ_ONCE(rcu_state.gp_flags); + *gp_seq = rcu_seq_current(&rcu_state.gp_seq); } EXPORT_SYMBOL_GPL(rcutorture_get_gp_data); From 710cf51d3722012988b2b8d35dee3c553dcc5649 Mon Sep 17 00:00:00 2001 From: Zqiang Date: Mon, 18 Mar 2024 17:34:12 +0800 Subject: [PATCH 461/969] rcutorture: Removing redundant function pointer initialization For these rcu_torture_ops structure's objects defined by using static, if the value of the function pointer in its member is not set, the default value will be NULL, this commit therefore remove the pre-existing initialization of function pointers to NULL. Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 85ff8a32f75a..3f9c3766f52b 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -566,7 +566,6 @@ static struct rcu_torture_ops rcu_ops = { .call = call_rcu_hurry, .cb_barrier = rcu_barrier, .fqs = rcu_force_quiescent_state, - .stats = NULL, .gp_kthread_dbg = show_rcu_gp_kthreads, .check_boost_failed = rcu_check_boost_fail, .stall_dur = rcu_jiffies_till_stall_check, @@ -614,9 +613,6 @@ static struct rcu_torture_ops rcu_busted_ops = { .sync = synchronize_rcu_busted, .exp_sync = synchronize_rcu_busted, .call = call_rcu_busted, - .cb_barrier = NULL, - .fqs = NULL, - .stats = NULL, .irq_capable = 1, .name = "busted" }; @@ -847,8 +843,6 @@ static struct rcu_torture_ops trivial_ops = { .get_gp_seq = rcu_no_completed, .sync = synchronize_rcu_trivial, .exp_sync = synchronize_rcu_trivial, - .fqs = NULL, - .stats = NULL, .irq_capable = 1, .name = "trivial" }; @@ -892,8 +886,6 @@ static struct rcu_torture_ops tasks_ops = { .cb_barrier = rcu_barrier_tasks, .gp_kthread_dbg = show_rcu_tasks_classic_gp_kthread, .get_gp_data = rcu_tasks_get_gp_data, - .fqs = NULL, - .stats = NULL, .irq_capable = 1, .slow_gps = 1, .name = "tasks" @@ -934,8 +926,6 @@ static struct rcu_torture_ops tasks_rude_ops = { .gp_kthread_dbg = show_rcu_tasks_rude_gp_kthread, .get_gp_data = rcu_tasks_rude_get_gp_data, .cbflood_max = 50000, - .fqs = NULL, - .stats = NULL, .irq_capable = 1, .name = "tasks-rude" }; @@ -987,8 +977,6 @@ static struct rcu_torture_ops tasks_tracing_ops = { .gp_kthread_dbg = show_rcu_tasks_trace_gp_kthread, .get_gp_data = rcu_tasks_trace_get_gp_data, .cbflood_max = 50000, - .fqs = NULL, - .stats = NULL, .irq_capable = 1, .slow_gps = 1, .name = "tasks-tracing" From 431315a563015f259b28e34c5842f6166439e969 Mon Sep 17 00:00:00 2001 From: Zqiang Date: Thu, 21 Mar 2024 16:28:50 +0800 Subject: [PATCH 462/969] rcutorture: Make stall-tasks directly exit when rcutorture tests end When the rcutorture tests start to exit, the rcu_torture_cleanup() is invoked to stop kthreads and release resources, if the stall-task kthreads exist, cpu-stall has started and the rcutorture.stall_cpu is set to a larger value, the rcu_torture_cleanup() will be blocked for a long time and the hung-task may occur, this commit therefore add kthread_should_stop() to the loop of cpu-stall operation, when rcutorture tests ends, no need to wait for cpu-stall to end, exit directly. Use the following command to test: insmod rcutorture.ko torture_type=srcu fwd_progress=0 stat_interval=4 stall_cpu_block=1 stall_cpu=200 stall_cpu_holdoff=10 read_exit_burst=0 object_debug=1 rmmod rcutorture [15361.918610] INFO: task rmmod:878 blocked for more than 122 seconds. [15361.918613] Tainted: G W 6.8.0-rc2-yoctodev-standard+ #25 [15361.918615] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [15361.918616] task:rmmod state:D stack:0 pid:878 tgid:878 ppid:773 flags:0x00004002 [15361.918621] Call Trace: [15361.918623] [15361.918626] __schedule+0xc0d/0x28f0 [15361.918631] ? __pfx___schedule+0x10/0x10 [15361.918635] ? rcu_is_watching+0x19/0xb0 [15361.918638] ? schedule+0x1f6/0x290 [15361.918642] ? __pfx_lock_release+0x10/0x10 [15361.918645] ? schedule+0xc9/0x290 [15361.918648] ? schedule+0xc9/0x290 [15361.918653] ? trace_preempt_off+0x54/0x100 [15361.918657] ? schedule+0xc9/0x290 [15361.918661] schedule+0xd0/0x290 [15361.918665] schedule_timeout+0x56d/0x7d0 [15361.918669] ? debug_smp_processor_id+0x1b/0x30 [15361.918672] ? rcu_is_watching+0x19/0xb0 [15361.918676] ? __pfx_schedule_timeout+0x10/0x10 [15361.918679] ? debug_smp_processor_id+0x1b/0x30 [15361.918683] ? rcu_is_watching+0x19/0xb0 [15361.918686] ? wait_for_completion+0x179/0x4c0 [15361.918690] ? __pfx_lock_release+0x10/0x10 [15361.918693] ? __kasan_check_write+0x18/0x20 [15361.918696] ? wait_for_completion+0x9d/0x4c0 [15361.918700] ? _raw_spin_unlock_irq+0x36/0x50 [15361.918703] ? wait_for_completion+0x179/0x4c0 [15361.918707] ? _raw_spin_unlock_irq+0x36/0x50 [15361.918710] ? wait_for_completion+0x179/0x4c0 [15361.918714] ? trace_preempt_on+0x54/0x100 [15361.918718] ? wait_for_completion+0x179/0x4c0 [15361.918723] wait_for_completion+0x181/0x4c0 [15361.918728] ? __pfx_wait_for_completion+0x10/0x10 [15361.918738] kthread_stop+0x152/0x470 [15361.918742] _torture_stop_kthread+0x44/0xc0 [torture 7af7f9cbba28271a10503b653f9e05d518fbc8c3] [15361.918752] rcu_torture_cleanup+0x2ac/0xe90 [rcutorture f2cb1f556ee7956270927183c4c2c7749a336529] [15361.918766] ? __pfx_rcu_torture_cleanup+0x10/0x10 [rcutorture f2cb1f556ee7956270927183c4c2c7749a336529] [15361.918777] ? __kasan_check_write+0x18/0x20 [15361.918781] ? __mutex_unlock_slowpath+0x17c/0x670 [15361.918789] ? __might_fault+0xcd/0x180 [15361.918793] ? find_module_all+0x104/0x1d0 [15361.918799] __x64_sys_delete_module+0x2a4/0x3f0 [15361.918803] ? __pfx___x64_sys_delete_module+0x10/0x10 [15361.918807] ? syscall_exit_to_user_mode+0x149/0x280 Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 3f9c3766f52b..456185d9e6c0 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -2489,8 +2489,8 @@ static int rcu_torture_stall(void *args) preempt_disable(); pr_alert("%s start on CPU %d.\n", __func__, raw_smp_processor_id()); - while (ULONG_CMP_LT((unsigned long)ktime_get_seconds(), - stop_at)) + while (ULONG_CMP_LT((unsigned long)ktime_get_seconds(), stop_at) && + !kthread_should_stop()) if (stall_cpu_block) { #ifdef CONFIG_PREEMPTION preempt_schedule(); From 668c0406d887467d53f8fe79261dda1d22d5b671 Mon Sep 17 00:00:00 2001 From: Zqiang Date: Mon, 25 Mar 2024 15:52:19 +0800 Subject: [PATCH 463/969] rcutorture: Fix invalid context warning when enable srcu barrier testing When the torture_type is set srcu or srcud and cb_barrier is non-zero, running the rcutorture test will trigger the following warning: [ 163.910989][ C1] BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:48 [ 163.910994][ C1] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 0, name: swapper/1 [ 163.910999][ C1] preempt_count: 10001, expected: 0 [ 163.911002][ C1] RCU nest depth: 0, expected: 0 [ 163.911005][ C1] INFO: lockdep is turned off. [ 163.911007][ C1] irq event stamp: 30964 [ 163.911010][ C1] hardirqs last enabled at (30963): [] do_idle+0x362/0x500 [ 163.911018][ C1] hardirqs last disabled at (30964): [] sysvec_call_function_single+0xf/0xd0 [ 163.911025][ C1] softirqs last enabled at (0): [] copy_process+0x16ff/0x6580 [ 163.911033][ C1] softirqs last disabled at (0): [<0000000000000000>] 0x0 [ 163.911038][ C1] Preemption disabled at: [ 163.911039][ C1] [] stack_depot_save_flags+0x24b/0x6c0 [ 163.911063][ C1] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G W 6.8.0-rc4-rt4-yocto-preempt-rt+ #3 1e39aa9a737dd024a3275c4f835a872f673a7d3a [ 163.911071][ C1] Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS rel-1.16.2-0-gea1b7a073390-prebuilt.qemu.org 04/01/2014 [ 163.911075][ C1] Call Trace: [ 163.911078][ C1] [ 163.911080][ C1] dump_stack_lvl+0x88/0xd0 [ 163.911089][ C1] dump_stack+0x10/0x20 [ 163.911095][ C1] __might_resched+0x36f/0x530 [ 163.911105][ C1] rt_spin_lock+0x82/0x1c0 [ 163.911112][ C1] spin_lock_irqsave_ssp_contention+0xb8/0x100 [ 163.911121][ C1] srcu_gp_start_if_needed+0x782/0xf00 [ 163.911128][ C1] ? _raw_spin_unlock_irqrestore+0x46/0x70 [ 163.911136][ C1] ? debug_object_active_state+0x336/0x470 [ 163.911148][ C1] ? __pfx_srcu_gp_start_if_needed+0x10/0x10 [ 163.911156][ C1] ? __pfx_lock_release+0x10/0x10 [ 163.911165][ C1] ? __pfx_rcu_torture_barrier_cbf+0x10/0x10 [ 163.911188][ C1] __call_srcu+0x9f/0xe0 [ 163.911196][ C1] call_srcu+0x13/0x20 [ 163.911201][ C1] srcu_torture_call+0x1b/0x30 [ 163.911224][ C1] rcu_torture_barrier1cb+0x4a/0x60 [ 163.911247][ C1] __flush_smp_call_function_queue+0x267/0xca0 [ 163.911256][ C1] ? __pfx_rcu_torture_barrier1cb+0x10/0x10 [ 163.911281][ C1] generic_smp_call_function_single_interrupt+0x13/0x20 [ 163.911288][ C1] __sysvec_call_function_single+0x7d/0x280 [ 163.911295][ C1] sysvec_call_function_single+0x93/0xd0 [ 163.911302][ C1] [ 163.911304][ C1] [ 163.911308][ C1] asm_sysvec_call_function_single+0x1b/0x20 [ 163.911313][ C1] RIP: 0010:default_idle+0x17/0x20 [ 163.911326][ C1] RSP: 0018:ffff888001997dc8 EFLAGS: 00000246 [ 163.911333][ C1] RAX: 0000000000000000 RBX: dffffc0000000000 RCX: ffffffffae618b51 [ 163.911337][ C1] RDX: 0000000000000000 RSI: ffffffffaea80920 RDI: ffffffffaec2de80 [ 163.911342][ C1] RBP: ffff888001997dc8 R08: 0000000000000001 R09: ffffed100d740cad [ 163.911346][ C1] R10: ffffed100d740cac R11: ffff88806ba06563 R12: 0000000000000001 [ 163.911350][ C1] R13: ffffffffafe460c0 R14: ffffffffafe460c0 R15: 0000000000000000 [ 163.911358][ C1] ? ct_kernel_exit.constprop.3+0x121/0x160 [ 163.911369][ C1] ? lockdep_hardirqs_on+0xc4/0x150 [ 163.911376][ C1] arch_cpu_idle+0x9/0x10 [ 163.911383][ C1] default_idle_call+0x7a/0xb0 [ 163.911390][ C1] do_idle+0x362/0x500 [ 163.911398][ C1] ? __pfx_do_idle+0x10/0x10 [ 163.911404][ C1] ? complete_with_flags+0x8b/0xb0 [ 163.911416][ C1] cpu_startup_entry+0x58/0x70 [ 163.911423][ C1] start_secondary+0x221/0x280 [ 163.911430][ C1] ? __pfx_start_secondary+0x10/0x10 [ 163.911440][ C1] secondary_startup_64_no_verify+0x17f/0x18b [ 163.911455][ C1] This commit therefore use smp_call_on_cpu() instead of smp_call_function_single(), make rcu_torture_barrier1cb() invoked happens on task-context. Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 456185d9e6c0..8654e99bd4a3 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -3044,11 +3044,12 @@ static void rcu_torture_barrier_cbf(struct rcu_head *rcu) } /* IPI handler to get callback posted on desired CPU, if online. */ -static void rcu_torture_barrier1cb(void *rcu_void) +static int rcu_torture_barrier1cb(void *rcu_void) { struct rcu_head *rhp = rcu_void; cur_ops->call(rhp, rcu_torture_barrier_cbf); + return 0; } /* kthread function to register callbacks used to test RCU barriers. */ @@ -3074,11 +3075,9 @@ static int rcu_torture_barrier_cbs(void *arg) * The above smp_load_acquire() ensures barrier_phase load * is ordered before the following ->call(). */ - if (smp_call_function_single(myid, rcu_torture_barrier1cb, - &rcu, 1)) { - // IPI failed, so use direct call from current CPU. + if (smp_call_on_cpu(myid, rcu_torture_barrier1cb, &rcu, 1)) cur_ops->call(&rcu, rcu_torture_barrier_cbf); - } + if (atomic_dec_and_test(&barrier_cbs_count)) wake_up(&barrier_wq); } while (!torture_must_stop()); From 39988fdc126b5148f102fc2afbc9fd92d8249f53 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 28 Mar 2024 19:51:34 -0700 Subject: [PATCH 464/969] torture: Scale --do-kvfree test time Currently, the torture.sh --do-kvfree testing is hard-coded to ten minutes, ignoring the --duration argument. This commit therefore scales this test duration the same as for the rcutorture tests. Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- tools/testing/selftests/rcutorture/bin/torture.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/rcutorture/bin/torture.sh b/tools/testing/selftests/rcutorture/bin/torture.sh index 13875ee7b050..990d24696fd3 100755 --- a/tools/testing/selftests/rcutorture/bin/torture.sh +++ b/tools/testing/selftests/rcutorture/bin/torture.sh @@ -559,7 +559,7 @@ do_kcsan="$do_kcsan_save" if test "$do_kvfree" = "yes" then torture_bootargs="rcuscale.kfree_rcu_test=1 rcuscale.kfree_nthreads=16 rcuscale.holdoff=20 rcuscale.kfree_loops=10000 torture.disable_onoff_at_boot" - torture_set "rcuscale-kvfree" tools/testing/selftests/rcutorture/bin/kvm.sh --torture rcuscale --allcpus --duration 10 --kconfig "CONFIG_NR_CPUS=$HALF_ALLOTED_CPUS" --memory 2G --trust-make + torture_set "rcuscale-kvfree" tools/testing/selftests/rcutorture/bin/kvm.sh --torture rcuscale --allcpus --duration $duration_rcutorture --kconfig "CONFIG_NR_CPUS=$HALF_ALLOTED_CPUS" --memory 2G --trust-make fi if test "$do_clocksourcewd" = "yes" From 1c67318b3d72e63c51646cf26aa4425ed6f34bc5 Mon Sep 17 00:00:00 2001 From: Zqiang Date: Fri, 29 Mar 2024 12:52:45 +0800 Subject: [PATCH 465/969] rcutorture: Use rcu_gp_slow_register/unregister() only for rcutype test The rcu_gp_slow_register/unregister() is only useful in tests where torture_type=rcu, so this commit therefore generates ->gp_slow_register() and ->gp_slow_unregister() function pointers in the rcu_torture_ops structure, and slows grace periods only when these function pointers exist. Signed-off-by: Zqiang Signed-off-by: Paul E. McKenney Signed-off-by: Uladzislau Rezki (Sony) --- kernel/rcu/rcutorture.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/kernel/rcu/rcutorture.c b/kernel/rcu/rcutorture.c index 8654e99bd4a3..807fbf6123a7 100644 --- a/kernel/rcu/rcutorture.c +++ b/kernel/rcu/rcutorture.c @@ -382,6 +382,8 @@ struct rcu_torture_ops { bool (*check_boost_failed)(unsigned long gp_state, int *cpup); int (*stall_dur)(void); void (*get_gp_data)(int *flags, unsigned long *gp_seq); + void (*gp_slow_register)(atomic_t *rgssp); + void (*gp_slow_unregister)(atomic_t *rgssp); long cbflood_max; int irq_capable; int can_boost; @@ -570,6 +572,8 @@ static struct rcu_torture_ops rcu_ops = { .check_boost_failed = rcu_check_boost_fail, .stall_dur = rcu_jiffies_till_stall_check, .get_gp_data = rcutorture_get_gp_data, + .gp_slow_register = rcu_gp_slow_register, + .gp_slow_unregister = rcu_gp_slow_unregister, .irq_capable = 1, .can_boost = IS_ENABLED(CONFIG_RCU_BOOST), .extendables = RCUTORTURE_MAX_EXTEND, @@ -3343,12 +3347,12 @@ rcu_torture_cleanup(void) pr_info("%s: Invoking %pS().\n", __func__, cur_ops->cb_barrier); cur_ops->cb_barrier(); } - rcu_gp_slow_unregister(NULL); + if (cur_ops->gp_slow_unregister) + cur_ops->gp_slow_unregister(NULL); return; } if (!cur_ops) { torture_cleanup_end(); - rcu_gp_slow_unregister(NULL); return; } @@ -3447,7 +3451,8 @@ rcu_torture_cleanup(void) else rcu_torture_print_module_parms(cur_ops, "End of test: SUCCESS"); torture_cleanup_end(); - rcu_gp_slow_unregister(&rcu_fwd_cb_nodelay); + if (cur_ops->gp_slow_unregister) + cur_ops->gp_slow_unregister(NULL); } #ifdef CONFIG_DEBUG_OBJECTS_RCU_HEAD @@ -3929,7 +3934,8 @@ rcu_torture_init(void) if (object_debug) rcu_test_debug_objects(); torture_init_end(); - rcu_gp_slow_register(&rcu_fwd_cb_nodelay); + if (cur_ops->gp_slow_register && !WARN_ON_ONCE(!cur_ops->gp_slow_unregister)) + cur_ops->gp_slow_register(&rcu_fwd_cb_nodelay); return 0; unwind: From 94e181a5703717f4244a4301498b594844317fd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sun, 14 Apr 2024 20:01:21 +0300 Subject: [PATCH 466/969] ARM: dts: BCM5301X: use color and function on ASUS RT-AC3100 and RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As the label property for LEDs is deprecated, use the color and function properties to describe the LEDs on the device tree file for ASUS RT-AC3100 and ASUS RT-AC88U. Reorder the LED and button nodes in alphabetical order. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20240414-for-soc-asus-rt-ac3100-improvements-v1-1-0e40caf1a70a@arinc9.com Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcm47094-asus-rt-ac3100.dtsi | 54 +++++++++++-------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi index 09cefce27fb1..9271792a9e44 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi @@ -6,6 +6,8 @@ #include "bcm47094.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" +#include + / { chosen { bootargs = "earlycon"; @@ -25,38 +27,46 @@ leds { compatible = "gpio-leds"; + led-lan { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + led-power { - label = "white:power"; + color = ; + function = LED_FUNCTION_POWER; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - led-wan-red { - label = "red:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-lan { - label = "white:lan"; - gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; - }; - led-usb2 { - label = "white:usb2"; + color = ; + function = LED_FUNCTION_USB; + function-enumerator = <1>; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; trigger-sources = <&ehci_port2>; linux,default-trigger = "usbport"; }; led-usb3 { - label = "white:usb3"; + color = ; + function = LED_FUNCTION_USB; + function-enumerator = <2>; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; trigger-sources = <&ehci_port1>, <&xhci_port1>; linux,default-trigger = "usbport"; }; + led-wan-red { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + led-wps { - label = "white:wps"; + color = ; + function = LED_FUNCTION_WPS; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; }; }; @@ -64,10 +74,10 @@ gpio-keys { compatible = "gpio-keys"; - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + button-led { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; button-reset { @@ -82,10 +92,10 @@ gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; - button-led { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; }; }; }; From 1acb48eeebaae68330f7c9782ce2c17b565b47b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sun, 14 Apr 2024 20:01:22 +0300 Subject: [PATCH 467/969] ARM: dts: BCM5301X: provide address for SoC MACs on ASUS RT-AC3100 & AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not leave the providing of a MAC address for an SoC MAC to a driver. Describe it on the bindings. Provide a distinct MAC address for each SoC MAC. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20240414-for-soc-asus-rt-ac3100-improvements-v1-2-0e40caf1a70a@arinc9.com Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts | 13 ++++++++++++- .../boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts | 8 +++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts index 5f089307cd8c..1655ac95769c 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts @@ -13,11 +13,22 @@ nvram@1c080000 { et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; }; }; }; &gmac0 { - nvmem-cells = <&et0macaddr>; + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + nvmem-cells = <&et0macaddr 2>; nvmem-cell-names = "mac-address"; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts index fd344b55087e..c78f0c7b137d 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts @@ -13,6 +13,7 @@ nvram@1c080000 { et1macaddr: et1macaddr { + #nvmem-cell-cells = <1>; }; }; @@ -117,6 +118,11 @@ }; &gmac1 { - nvmem-cells = <&et1macaddr>; + nvmem-cells = <&et1macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + nvmem-cells = <&et1macaddr 1>; nvmem-cell-names = "mac-address"; }; From a0ad4fe7eff91e80a92f10b54361f91a948f8ee4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sun, 14 Apr 2024 20:01:23 +0300 Subject: [PATCH 468/969] ARM: dts: BCM5301X: remove duplicate compatible on ASUS RT-AC3100 & AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The compatible property on the node with the srab handle is already described with the same value on the included device tree. Remove it. Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20240414-for-soc-asus-rt-ac3100-improvements-v1-3-0e40caf1a70a@arinc9.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi index 9271792a9e44..84d583168d81 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi @@ -101,7 +101,6 @@ }; &srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; status = "okay"; ports { From dd5c56cd065e6f7ac5f87b939e8a3c499a62d463 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sun, 14 Apr 2024 20:01:24 +0300 Subject: [PATCH 469/969] ARM: dts: BCM5301X: remove earlycon on ASUS RT-AC3100 and ASUS RT-AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the earlycon boot argument. As Krzysztof pointed out, earlycon is for debugging, not regular mainline usage. Signed-off-by: Arınç ÜNAL Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240414-for-soc-asus-rt-ac3100-improvements-v1-4-0e40caf1a70a@arinc9.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi index 84d583168d81..9c7efb1c44f1 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi @@ -9,10 +9,6 @@ #include / { - chosen { - bootargs = "earlycon"; - }; - memory@0 { device_type = "memory"; reg = <0x00000000 0x08000000>, From 22fdd8ba61187582843f090f100284d9e826adca Mon Sep 17 00:00:00 2001 From: Nina Schoetterl-Glausch Date: Tue, 19 Mar 2024 17:44:20 +0100 Subject: [PATCH 470/969] KVM: s390: vsie: Use virt_to_phys for facility control block In order for SIE to interpretively execute STFLE, it requires the real or absolute address of a facility-list control block. Before writing the location into the shadow SIE control block, convert it from a virtual address. We currently do not run into this bug because the lower 31 bits are the same for virtual and physical addresses. Signed-off-by: Nina Schoetterl-Glausch Link: https://lore.kernel.org/r/20240319164420.4053380-3-nsg@linux.ibm.com Signed-off-by: Janosch Frank Message-Id: <20240319164420.4053380-3-nsg@linux.ibm.com> Signed-off-by: Alexander Gordeev --- arch/s390/kvm/vsie.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c index b2c9f010f0fe..d8527a046cf7 100644 --- a/arch/s390/kvm/vsie.c +++ b/arch/s390/kvm/vsie.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -1005,7 +1006,7 @@ static int handle_stfle(struct kvm_vcpu *vcpu, struct vsie_page *vsie_page) if (read_guest_real(vcpu, fac, &vsie_page->fac, stfle_size() * sizeof(u64))) return set_validity_icpt(scb_s, 0x1090U); - scb_s->fac = (__u32)(__u64) &vsie_page->fac; + scb_s->fac = (u32)virt_to_phys(&vsie_page->fac); } return 0; } From 47bf81767277b5abb87f7e86e15310f0e9d4d06c Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Tue, 11 Jul 2023 12:21:39 +0200 Subject: [PATCH 471/969] s390/boot: Do not force vmemmap to start at MAX_PHYSMEM_BITS vmemmap is forcefully set to start at MAX_PHYSMEM_BITS at most. That could be needed in the past to limit ident_map_size to MAX_PHYSMEM_BITS. However since commit 75eba6ec0de1 ("s390: unify identity mapping limits handling") ident_map_size is limited in setup_ident_map_size() function, which is called earlier. Another reason to limit vmemmap start to MAX_PHYSMEM_BITS is because it was returned by arch_get_mappable_range() as the maximum mappable physical address. Since commit f641679dfe55 ("s390/mm: rework arch_get_mappable_range() callback") that is not required anymore. As result, there is no neccessity to limit vmemmap starting address with MAX_PHYSMEM_BITS. Reviewed-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/boot/startup.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 6cf89314209a..bb5d26f0ff41 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -313,9 +313,8 @@ static unsigned long setup_kernel_memory_layout(void) pages = SECTION_ALIGN_UP(pages); /* keep vmemmap_start aligned to a top level region table entry */ vmemmap_start = round_down(VMALLOC_START - pages * sizeof(struct page), rte_size); - vmemmap_start = min(vmemmap_start, 1UL << MAX_PHYSMEM_BITS); - /* maximum mappable address as seen by arch_get_mappable_range() */ - max_mappable = vmemmap_start; + /* maximum address for which linear mapping could be created (DCSS, memory) */ + max_mappable = min(vmemmap_start, 1UL << MAX_PHYSMEM_BITS); /* make sure identity map doesn't overlay with vmemmap */ ident_map_size = min(ident_map_size, vmemmap_start); vmemmap_size = SECTION_ALIGN_UP(ident_map_size / PAGE_SIZE) * sizeof(struct page); From b2b15f079c4c19e3a73a8b0cf4f901186f12098f Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 1 Mar 2024 07:03:49 +0100 Subject: [PATCH 472/969] s390/boot: Consider DCSS segments on memory layout setup The maximum mappable physical address (as returned by arch_get_mappable_range() callback) is limited by the value of (1UL << MAX_PHYSMEM_BITS). The maximum physical address available to a DCSS segment is 512GB. In case the available online or offline memory size is less than the DCSS limit arch_get_mappable_range() would include never used [512GB..(1UL << MAX_PHYSMEM_BITS)] range. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/boot/startup.c | 7 +++++-- arch/s390/include/asm/extmem.h | 7 +++++++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index bb5d26f0ff41..eee742b88cc8 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -313,14 +314,16 @@ static unsigned long setup_kernel_memory_layout(void) pages = SECTION_ALIGN_UP(pages); /* keep vmemmap_start aligned to a top level region table entry */ vmemmap_start = round_down(VMALLOC_START - pages * sizeof(struct page), rte_size); - /* maximum address for which linear mapping could be created (DCSS, memory) */ - max_mappable = min(vmemmap_start, 1UL << MAX_PHYSMEM_BITS); /* make sure identity map doesn't overlay with vmemmap */ ident_map_size = min(ident_map_size, vmemmap_start); vmemmap_size = SECTION_ALIGN_UP(ident_map_size / PAGE_SIZE) * sizeof(struct page); /* make sure vmemmap doesn't overlay with vmalloc area */ VMALLOC_START = max(vmemmap_start + vmemmap_size, VMALLOC_START); vmemmap = (struct page *)vmemmap_start; + /* maximum address for which linear mapping could be created (DCSS, memory) */ + BUILD_BUG_ON(MAX_DCSS_ADDR > (1UL << MAX_PHYSMEM_BITS)); + max_mappable = max(ident_map_size, MAX_DCSS_ADDR); + max_mappable = min(max_mappable, vmemmap_start); return asce_limit; } diff --git a/arch/s390/include/asm/extmem.h b/arch/s390/include/asm/extmem.h index 568fd81bb77b..e0a06060afdd 100644 --- a/arch/s390/include/asm/extmem.h +++ b/arch/s390/include/asm/extmem.h @@ -8,6 +8,13 @@ #define _ASM_S390X_DCSS_H #ifndef __ASSEMBLY__ +/* + * DCSS segment is defined as a contiguous range of pages using DEFSEG command. + * The range start and end is a page number with a value less than or equal to + * 0x7ffffff (see CP Commands and Utilities Reference). + */ +#define MAX_DCSS_ADDR (512UL * SZ_1G) + /* possible values for segment type as returned by segment_info */ #define SEG_TYPE_SW 0 #define SEG_TYPE_EW 1 From ecf74da64defe9e7f1862d86b4f3d4041e22dc4a Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Tue, 11 Jul 2023 07:58:24 +0200 Subject: [PATCH 473/969] s390/boot: Reduce size of identity mapping on overlap In case vmemmap array could overlap with vmalloc area on virtual memory layout setup, the size of vmalloc area is decreased. That could result in less memory than user requested with vmalloc= kernel command line parameter. Instead, reduce the size of identity mapping (and the size of vmemmap array as result) to avoid such overlap. Further, currently the virtual memmory allocation "rolls" from top to bottom and it is only VMALLOC_START that could get increased due to the overlap. Change that to decrease- only, which makes the whole allocation algorithm more easy to comprehend. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/boot/startup.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index eee742b88cc8..069ecc81332f 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -318,7 +318,10 @@ static unsigned long setup_kernel_memory_layout(void) ident_map_size = min(ident_map_size, vmemmap_start); vmemmap_size = SECTION_ALIGN_UP(ident_map_size / PAGE_SIZE) * sizeof(struct page); /* make sure vmemmap doesn't overlay with vmalloc area */ - VMALLOC_START = max(vmemmap_start + vmemmap_size, VMALLOC_START); + if (vmemmap_start + vmemmap_size > VMALLOC_START) { + vmemmap_size = SECTION_ALIGN_DOWN(ident_map_size / PAGE_SIZE) * sizeof(struct page); + ident_map_size = vmemmap_size / sizeof(struct page) * PAGE_SIZE; + } vmemmap = (struct page *)vmemmap_start; /* maximum address for which linear mapping could be created (DCSS, memory) */ BUILD_BUG_ON(MAX_DCSS_ADDR > (1UL << MAX_PHYSMEM_BITS)); From c8aef260c86ec86c4d6065b6cd67ce7161d1ca10 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 1 Mar 2024 07:05:39 +0100 Subject: [PATCH 474/969] s390/boot: Swap vmalloc and Lowcore/Real Memory Copy areas This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. Currently the order of virtual memory areas is (the lowcore and .amode31 section are skipped, as it is irrelevant): identity mapping (the kernel is contained within) vmemmap vmalloc modules Absolute Lowcore Real Memory Copy In the future the kernel will be mapped separately and placed to the end of the virtual address space, so the layout would turn like this: identity mapping vmemmap vmalloc modules Absolute Lowcore Real Memory Copy kernel However, the distance between kernel and modules needs to be as little as possible, ideally - none. Thus, the Absolute Lowcore and Real Memory Copy areas would stay in the way and therefore need to be moved as well: identity mapping vmemmap Absolute Lowcore Real Memory Copy vmalloc modules kernel To facilitate such layout swap the vmalloc and Absolute Lowcore together with Real Memory Copy areas. As result, the current layout turns into: identity mapping (the kernel is contained within) vmemmap Absolute Lowcore Real Memory Copy vmalloc modules This will allow to locate the kernel directly next to the modules once it gets mapped separately. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/boot/startup.c | 20 +++++++++++--------- arch/s390/mm/vmem.c | 3 ++- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 069ecc81332f..ebd8d8dc3bea 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -297,28 +297,30 @@ static unsigned long setup_kernel_memory_layout(void) /* force vmalloc and modules below kasan shadow */ vmax = min(vmax, KASAN_SHADOW_START); #endif - __memcpy_real_area = round_down(vmax - MEMCPY_REAL_SIZE, PAGE_SIZE); - __abs_lowcore = round_down(__memcpy_real_area - ABS_LOWCORE_MAP_SIZE, - sizeof(struct lowcore)); - MODULES_END = round_down(__abs_lowcore, _SEGMENT_SIZE); + MODULES_END = round_down(vmax, _SEGMENT_SIZE); MODULES_VADDR = MODULES_END - MODULES_LEN; VMALLOC_END = MODULES_VADDR; /* allow vmalloc area to occupy up to about 1/2 of the rest virtual space left */ - vsize = round_down(VMALLOC_END / 2, _SEGMENT_SIZE); + vsize = (VMALLOC_END - (MEMCPY_REAL_SIZE + ABS_LOWCORE_MAP_SIZE)) / 2; + vsize = round_down(vsize, _SEGMENT_SIZE); vmalloc_size = min(vmalloc_size, vsize); VMALLOC_START = VMALLOC_END - vmalloc_size; + __memcpy_real_area = round_down(VMALLOC_START - MEMCPY_REAL_SIZE, PAGE_SIZE); + __abs_lowcore = round_down(__memcpy_real_area - ABS_LOWCORE_MAP_SIZE, + sizeof(struct lowcore)); + /* split remaining virtual space between 1:1 mapping & vmemmap array */ - pages = VMALLOC_START / (PAGE_SIZE + sizeof(struct page)); + pages = __abs_lowcore / (PAGE_SIZE + sizeof(struct page)); pages = SECTION_ALIGN_UP(pages); /* keep vmemmap_start aligned to a top level region table entry */ - vmemmap_start = round_down(VMALLOC_START - pages * sizeof(struct page), rte_size); + vmemmap_start = round_down(__abs_lowcore - pages * sizeof(struct page), rte_size); /* make sure identity map doesn't overlay with vmemmap */ ident_map_size = min(ident_map_size, vmemmap_start); vmemmap_size = SECTION_ALIGN_UP(ident_map_size / PAGE_SIZE) * sizeof(struct page); - /* make sure vmemmap doesn't overlay with vmalloc area */ - if (vmemmap_start + vmemmap_size > VMALLOC_START) { + /* make sure vmemmap doesn't overlay with absolute lowcore area */ + if (vmemmap_start + vmemmap_size > __abs_lowcore) { vmemmap_size = SECTION_ALIGN_DOWN(ident_map_size / PAGE_SIZE) * sizeof(struct page); ident_map_size = vmemmap_size / sizeof(struct page) * PAGE_SIZE; } diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c index 85cddf904cb2..917b8a37383a 100644 --- a/arch/s390/mm/vmem.c +++ b/arch/s390/mm/vmem.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -436,7 +437,7 @@ static int modify_pagetable(unsigned long start, unsigned long end, bool add, if (WARN_ON_ONCE(!PAGE_ALIGNED(start | end))) return -EINVAL; /* Don't mess with any tables not fully in 1:1 mapping & vmemmap area */ - if (WARN_ON_ONCE(end > VMALLOC_START)) + if (WARN_ON_ONCE(end > __abs_lowcore)) return -EINVAL; for (addr = start; addr < end; addr = next) { next = pgd_addr_end(addr, end); From bbe72f39022270c40dc1e991b4dadf6f32eed86a Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Sat, 2 Dec 2023 08:50:45 +0100 Subject: [PATCH 475/969] s390/mm: Move KASLR related to Move everyting KASLR related to , similarly to many other architectures. Acked-by: Heiko Carstens Suggested-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/page.h | 14 ++++++++++++++ arch/s390/include/asm/setup.h | 14 -------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 9381879f7ecf..602e8056b7cc 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -178,6 +178,20 @@ int arch_make_page_accessible(struct page *page); #define HAVE_ARCH_MAKE_PAGE_ACCESSIBLE #endif +extern unsigned long __kaslr_offset; +static inline unsigned long kaslr_offset(void) +{ + return __kaslr_offset; +} + +extern int __kaslr_enabled; +static inline int kaslr_enabled(void) +{ + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) + return __kaslr_enabled; + return 0; +} + #define __PAGE_OFFSET 0x0UL #define PAGE_OFFSET 0x0UL diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h index 03bcaa8effb2..32f70873e2b7 100644 --- a/arch/s390/include/asm/setup.h +++ b/arch/s390/include/asm/setup.h @@ -127,20 +127,6 @@ extern void (*_machine_restart)(char *command); extern void (*_machine_halt)(void); extern void (*_machine_power_off)(void); -extern unsigned long __kaslr_offset; -static inline unsigned long kaslr_offset(void) -{ - return __kaslr_offset; -} - -extern int __kaslr_enabled; -static inline int kaslr_enabled(void) -{ - if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) - return __kaslr_enabled; - return 0; -} - struct oldmem_data { unsigned long start; unsigned long size; From 236f324b747370b97030c9582591f459353e3589 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Sat, 2 Dec 2023 10:57:15 +0100 Subject: [PATCH 476/969] s390/mm: Create virtual memory layout structure This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. Put virtual memory layout information into a structure to improve code generation when accessing the structure members, which are currently only ident_map_size and __kaslr_offset. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/boot/startup.c | 3 +-- arch/s390/include/asm/page.h | 11 ++++++++++- arch/s390/kernel/setup.c | 3 +-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index ebd8d8dc3bea..8afb232d7c96 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -19,7 +19,7 @@ #include "boot.h" #include "uv.h" -unsigned long __bootdata_preserved(__kaslr_offset); +struct vm_layout __bootdata_preserved(vm_layout); unsigned long __bootdata_preserved(__abs_lowcore); unsigned long __bootdata_preserved(__memcpy_real_area); pte_t *__bootdata_preserved(memcpy_real_ptep); @@ -30,7 +30,6 @@ unsigned long __bootdata_preserved(vmemmap_size); unsigned long __bootdata_preserved(MODULES_VADDR); unsigned long __bootdata_preserved(MODULES_END); unsigned long __bootdata_preserved(max_mappable); -unsigned long __bootdata(ident_map_size); u64 __bootdata_preserved(stfle_fac_list[16]); u64 __bootdata_preserved(alt_stfle_fac_list[16]); diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 602e8056b7cc..f13a4527bf2d 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -178,7 +178,16 @@ int arch_make_page_accessible(struct page *page); #define HAVE_ARCH_MAKE_PAGE_ACCESSIBLE #endif -extern unsigned long __kaslr_offset; +struct vm_layout { + unsigned long kaslr_offset; + unsigned long identity_size; +}; + +extern struct vm_layout vm_layout; + +#define __kaslr_offset vm_layout.kaslr_offset +#define ident_map_size vm_layout.identity_size + static inline unsigned long kaslr_offset(void) { return __kaslr_offset; diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 24ed33f044ec..b9d70869bc36 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -146,10 +146,9 @@ static u32 __amode31_ref *__ctl_linkage_stack = __ctl_linkage_stack_amode31; static u32 __amode31_ref *__ctl_duct = __ctl_duct_amode31; unsigned long __bootdata_preserved(max_mappable); -unsigned long __bootdata(ident_map_size); struct physmem_info __bootdata(physmem_info); -unsigned long __bootdata_preserved(__kaslr_offset); +struct vm_layout __bootdata_preserved(vm_layout); int __bootdata_preserved(__kaslr_enabled); unsigned int __bootdata_preserved(zlib_dfltcc_support); EXPORT_SYMBOL(zlib_dfltcc_support); From 3bb11234b1d17236ba479f7d0eaa9bd12f2f2493 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Tue, 20 Feb 2024 14:35:43 +0100 Subject: [PATCH 477/969] s390/boot: Uncouple virtual and physical kernel offsets This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. Currently __kaslr_offset is the kernel offset in both physical memory on boot and in virtual memory after DAT mode is enabled. Uncouple these offsets and rename the physical address space variant to __kaslr_offset_phys while keep the name __kaslr_offset for the offset in virtual address space. Do not use __kaslr_offset_phys after DAT mode is enabled just yet, but still make it a persistent boot variable for later use. Use __kaslr_offset and __kaslr_offset_phys offsets in proper contexts and alter handle_relocs() function to distinguish between the two. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/Kconfig | 3 +++ arch/s390/boot/pgm_check_info.c | 4 +++- arch/s390/boot/startup.c | 20 ++++++++++++-------- arch/s390/include/asm/page.h | 2 ++ 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index b9857aacd40b..9515d4bf1683 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -17,6 +17,9 @@ config ARCH_HAS_ILOG2_U32 config ARCH_HAS_ILOG2_U64 def_bool n +config ARCH_PROC_KCORE_TEXT + def_bool y + config GENERIC_HWEIGHT def_bool y diff --git a/arch/s390/boot/pgm_check_info.c b/arch/s390/boot/pgm_check_info.c index 97244cd7a206..ea96275b0380 100644 --- a/arch/s390/boot/pgm_check_info.c +++ b/arch/s390/boot/pgm_check_info.c @@ -153,8 +153,10 @@ void print_pgm_check_info(void) decompressor_printk("Kernel command line: %s\n", early_command_line); decompressor_printk("Kernel fault: interruption code %04x ilc:%x\n", S390_lowcore.pgm_code, S390_lowcore.pgm_ilc >> 1); - if (kaslr_enabled()) + if (kaslr_enabled()) { decompressor_printk("Kernel random base: %lx\n", __kaslr_offset); + decompressor_printk("Kernel random base phys: %lx\n", __kaslr_offset_phys); + } decompressor_printk("PSW : %016lx %016lx (%pS)\n", S390_lowcore.psw_save_area.mask, S390_lowcore.psw_save_area.addr, diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 8afb232d7c96..44ef08518f37 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -142,7 +142,8 @@ static void copy_bootdata(void) } #ifdef CONFIG_PIE_BUILD -static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, unsigned long offset) +static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, + unsigned long offset, unsigned long phys_offset) { Elf64_Rela *rela_start, *rela_end, *rela; int r_type, r_sym, rc; @@ -153,7 +154,7 @@ static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, rela_end = (Elf64_Rela *) vmlinux.rela_dyn_end; dynsym = (Elf64_Sym *) vmlinux.dynsym_start; for (rela = rela_start; rela < rela_end; rela++) { - loc = rela->r_offset + offset; + loc = rela->r_offset + phys_offset; val = rela->r_addend; r_sym = ELF64_R_SYM(rela->r_info); if (r_sym) { @@ -194,7 +195,8 @@ static void free_relocs(void) physmem_free(RR_RELOC); } -static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, unsigned long offset) +static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, + unsigned long offset, unsigned long phys_offset) { int *reloc; long loc; @@ -428,8 +430,9 @@ void startup_kernel(void) THREAD_SIZE, vmlinux.default_lma, ident_map_size); if (vmlinux_lma) { - __kaslr_offset = vmlinux_lma - vmlinux.default_lma; - kaslr_adjust_vmlinux_info(__kaslr_offset); + __kaslr_offset_phys = vmlinux_lma - vmlinux.default_lma; + kaslr_adjust_vmlinux_info(__kaslr_offset_phys); + __kaslr_offset = __kaslr_offset_phys; } } vmlinux_lma = vmlinux_lma ?: vmlinux.default_lma; @@ -438,7 +441,7 @@ void startup_kernel(void) if (!IS_ENABLED(CONFIG_KERNEL_UNCOMPRESSED)) { img = decompress_kernel(); memmove((void *)vmlinux_lma, img, vmlinux.image_size); - } else if (__kaslr_offset) { + } else if (__kaslr_offset_phys) { img = (void *)vmlinux.default_lma; memmove((void *)vmlinux_lma, img, vmlinux.image_size); memset(img, 0, vmlinux.image_size); @@ -465,7 +468,8 @@ void startup_kernel(void) * to bootdata made by setup_vmem() */ clear_bss_section(vmlinux_lma); - kaslr_adjust_relocs(vmlinux_lma, vmlinux_lma + vmlinux.image_size, __kaslr_offset); + kaslr_adjust_relocs(vmlinux_lma, vmlinux_lma + vmlinux.image_size, + __kaslr_offset, __kaslr_offset_phys); kaslr_adjust_got(__kaslr_offset); free_relocs(); setup_vmem(asce_limit); @@ -475,7 +479,7 @@ void startup_kernel(void) * Save KASLR offset for early dumps, before vmcore_info is set. * Mark as uneven to distinguish from real vmcore_info pointer. */ - S390_lowcore.vmcore_info = __kaslr_offset ? __kaslr_offset | 0x1UL : 0; + S390_lowcore.vmcore_info = __kaslr_offset_phys ? __kaslr_offset_phys | 0x1UL : 0; /* * Jump to the decompressed kernel entry point and switch DAT mode on. diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index f13a4527bf2d..e2137b6ec2ed 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -180,12 +180,14 @@ int arch_make_page_accessible(struct page *page); struct vm_layout { unsigned long kaslr_offset; + unsigned long kaslr_offset_phys; unsigned long identity_size; }; extern struct vm_layout vm_layout; #define __kaslr_offset vm_layout.kaslr_offset +#define __kaslr_offset_phys vm_layout.kaslr_offset_phys #define ident_map_size vm_layout.identity_size static inline unsigned long kaslr_offset(void) From 7de0446f0b26589fa80e384d8edaa2c279583652 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Thu, 10 Aug 2023 21:40:19 +0200 Subject: [PATCH 478/969] s390/boot: Make identity mapping base address explicit This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. Currently the identity mapping base address is implicit and is always set to zero. Make it explicit by putting into __identity_base persistent boot variable and use it in proper context - which is the value of PAGE_OFFSET. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/page.h | 6 ++++-- arch/s390/kernel/setup.c | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index e2137b6ec2ed..95403750d25a 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -181,6 +181,7 @@ int arch_make_page_accessible(struct page *page); struct vm_layout { unsigned long kaslr_offset; unsigned long kaslr_offset_phys; + unsigned long identity_base; unsigned long identity_size; }; @@ -188,6 +189,7 @@ extern struct vm_layout vm_layout; #define __kaslr_offset vm_layout.kaslr_offset #define __kaslr_offset_phys vm_layout.kaslr_offset_phys +#define __identity_base vm_layout.identity_base #define ident_map_size vm_layout.identity_size static inline unsigned long kaslr_offset(void) @@ -203,8 +205,8 @@ static inline int kaslr_enabled(void) return 0; } -#define __PAGE_OFFSET 0x0UL -#define PAGE_OFFSET 0x0UL +#define __PAGE_OFFSET __identity_base +#define PAGE_OFFSET __PAGE_OFFSET #define __pa_nodebug(x) ((unsigned long)(x)) diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index b9d70869bc36..0544830ffb90 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -149,6 +149,7 @@ unsigned long __bootdata_preserved(max_mappable); struct physmem_info __bootdata(physmem_info); struct vm_layout __bootdata_preserved(vm_layout); +EXPORT_SYMBOL_GPL(vm_layout); int __bootdata_preserved(__kaslr_enabled); unsigned int __bootdata_preserved(zlib_dfltcc_support); EXPORT_SYMBOL(zlib_dfltcc_support); From 5fb50fa66ab94141c0692dc5043ed30e6159a81b Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 11 Aug 2023 09:49:27 +0200 Subject: [PATCH 479/969] s390/boot: Make .amode31 section address range explicit This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. Introduce .amode31 section address range AMODE31_START and AMODE31_END macros for later use. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/physmem_info.h | 3 +++ arch/s390/kernel/setup.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/s390/include/asm/physmem_info.h b/arch/s390/include/asm/physmem_info.h index e747b067f8db..d2f1cc742695 100644 --- a/arch/s390/include/asm/physmem_info.h +++ b/arch/s390/include/asm/physmem_info.h @@ -170,4 +170,7 @@ static inline unsigned long get_physmem_reserved(enum reserved_range_type type, return *size; } +#define AMODE31_START (physmem_info.reserved[RR_AMODE31].start) +#define AMODE31_END (physmem_info.reserved[RR_AMODE31].end) + #endif diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index 0544830ffb90..cbd5290939df 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -765,7 +765,7 @@ static void __init relocate_amode31_section(void) unsigned long amode31_size = __eamode31 - __samode31; long amode31_offset, *ptr; - amode31_offset = physmem_info.reserved[RR_AMODE31].start - (unsigned long)__samode31; + amode31_offset = AMODE31_START - (unsigned long)__samode31; pr_info("Relocating AMODE31 section of size 0x%08lx\n", amode31_size); /* Move original AMODE31 section to the new one */ From 88702793c5b4ef127a1f57d76920a80f70d081a7 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Thu, 27 Jan 2022 14:28:49 +0100 Subject: [PATCH 480/969] s390/os_info: Introduce value entries Introduce entries that do not reference any data in memory, but rather provide values. Set the size of such entries to zero and do not compute checksum for them, since there is no data which integrity needs to be checked. The integrity of the value entries itself is still covered by the os_info checksum. Reserve the lowest unused entry index OS_INFO_RESERVED for future use - presumably for the number of entries present. That could later be used by user level tools. The existing tools would not notice any difference. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/os_info.h | 19 +++++++++++++++---- arch/s390/kernel/ipl.c | 6 +++--- arch/s390/kernel/os_info.c | 15 +++++++++++++-- 3 files changed, 31 insertions(+), 9 deletions(-) diff --git a/arch/s390/include/asm/os_info.h b/arch/s390/include/asm/os_info.h index a4d2e103f116..d2f4ba67c006 100644 --- a/arch/s390/include/asm/os_info.h +++ b/arch/s390/include/asm/os_info.h @@ -17,11 +17,15 @@ #define OS_INFO_VMCOREINFO 0 #define OS_INFO_REIPL_BLOCK 1 #define OS_INFO_FLAGS_ENTRY 2 +#define OS_INFO_RESERVED 3 #define OS_INFO_FLAG_REIPL_CLEAR (1UL << 0) struct os_info_entry { - u64 addr; + union { + u64 addr; + u64 val; + }; u64 size; u32 csum; } __packed; @@ -33,17 +37,24 @@ struct os_info { u16 version_minor; u64 crashkernel_addr; u64 crashkernel_size; - struct os_info_entry entry[3]; - u8 reserved[4004]; + struct os_info_entry entry[4]; + u8 reserved[3984]; } __packed; void os_info_init(void); -void os_info_entry_add(int nr, void *ptr, u64 len); +void os_info_entry_add_data(int nr, void *ptr, u64 len); +void os_info_entry_add_val(int nr, u64 val); void os_info_crashkernel_add(unsigned long base, unsigned long size); u32 os_info_csum(struct os_info *os_info); #ifdef CONFIG_CRASH_DUMP void *os_info_old_entry(int nr, unsigned long *size); +static inline unsigned long os_info_old_value(int nr) +{ + unsigned long size; + + return (unsigned long)os_info_old_entry(nr, &size); +} #else static inline void *os_info_old_entry(int nr, unsigned long *size) { diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c index 1486350a4177..7dc54571f18e 100644 --- a/arch/s390/kernel/ipl.c +++ b/arch/s390/kernel/ipl.c @@ -1209,8 +1209,8 @@ static struct attribute_group reipl_nss_attr_group = { void set_os_info_reipl_block(void) { - os_info_entry_add(OS_INFO_REIPL_BLOCK, reipl_block_actual, - reipl_block_actual->hdr.len); + os_info_entry_add_data(OS_INFO_REIPL_BLOCK, reipl_block_actual, + reipl_block_actual->hdr.len); } /* reipl type */ @@ -1940,7 +1940,7 @@ static void dump_reipl_run(struct shutdown_trigger *trigger) reipl_type == IPL_TYPE_NSS || reipl_type == IPL_TYPE_UNKNOWN) os_info_flags |= OS_INFO_FLAG_REIPL_CLEAR; - os_info_entry_add(OS_INFO_FLAGS_ENTRY, &os_info_flags, sizeof(os_info_flags)); + os_info_entry_add_data(OS_INFO_FLAGS_ENTRY, &os_info_flags, sizeof(os_info_flags)); csum = (__force unsigned int)cksm(reipl_block_actual, reipl_block_actual->hdr.len, 0); abs_lc = get_abs_lowcore(); abs_lc->ipib = __pa(reipl_block_actual); diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c index a801e6bd5341..3800824f8466 100644 --- a/arch/s390/kernel/os_info.c +++ b/arch/s390/kernel/os_info.c @@ -43,9 +43,9 @@ void os_info_crashkernel_add(unsigned long base, unsigned long size) } /* - * Add OS info entry and update checksum + * Add OS info data entry and update checksum */ -void os_info_entry_add(int nr, void *ptr, u64 size) +void os_info_entry_add_data(int nr, void *ptr, u64 size) { os_info.entry[nr].addr = __pa(ptr); os_info.entry[nr].size = size; @@ -53,6 +53,17 @@ void os_info_entry_add(int nr, void *ptr, u64 size) os_info.csum = os_info_csum(&os_info); } +/* + * Add OS info value entry and update checksum + */ +void os_info_entry_add_val(int nr, u64 value) +{ + os_info.entry[nr].val = value; + os_info.entry[nr].size = 0; + os_info.entry[nr].csum = 0; + os_info.csum = os_info_csum(&os_info); +} + /* * Initialize OS info structure and set lowcore pointer */ From 8572f52518f69842d983b45eefa7d4efccd233de Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 11 Aug 2023 10:07:31 +0200 Subject: [PATCH 481/969] s390/os_info: Store virtual memory layout This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. The virtual memory layout will be read out by makedumpfile, crash and other user tools for virtual address translation. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/os_info.h | 10 ++++++++-- arch/s390/kernel/os_info.c | 7 +++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/os_info.h b/arch/s390/include/asm/os_info.h index d2f4ba67c006..621d49aa9c8d 100644 --- a/arch/s390/include/asm/os_info.h +++ b/arch/s390/include/asm/os_info.h @@ -18,6 +18,12 @@ #define OS_INFO_REIPL_BLOCK 1 #define OS_INFO_FLAGS_ENTRY 2 #define OS_INFO_RESERVED 3 +#define OS_INFO_IDENTITY_BASE 4 +#define OS_INFO_KASLR_OFFSET 5 +#define OS_INFO_KASLR_OFF_PHYS 6 +#define OS_INFO_VMEMMAP 7 +#define OS_INFO_AMODE31_START 8 +#define OS_INFO_AMODE31_END 9 #define OS_INFO_FLAG_REIPL_CLEAR (1UL << 0) @@ -37,8 +43,8 @@ struct os_info { u16 version_minor; u64 crashkernel_addr; u64 crashkernel_size; - struct os_info_entry entry[4]; - u8 reserved[3984]; + struct os_info_entry entry[10]; + u8 reserved[3864]; } __packed; void os_info_init(void); diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c index 3800824f8466..25bcda341630 100644 --- a/arch/s390/kernel/os_info.c +++ b/arch/s390/kernel/os_info.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -74,6 +75,12 @@ void __init os_info_init(void) os_info.version_major = OS_INFO_VERSION_MAJOR; os_info.version_minor = OS_INFO_VERSION_MINOR; os_info.magic = OS_INFO_MAGIC; + os_info_entry_add_val(OS_INFO_IDENTITY_BASE, __identity_base); + os_info_entry_add_val(OS_INFO_KASLR_OFFSET, kaslr_offset()); + os_info_entry_add_val(OS_INFO_KASLR_OFF_PHYS, __kaslr_offset_phys); + os_info_entry_add_val(OS_INFO_VMEMMAP, (unsigned long)vmemmap); + os_info_entry_add_val(OS_INFO_AMODE31_START, AMODE31_START); + os_info_entry_add_val(OS_INFO_AMODE31_END, AMODE31_END); os_info.csum = os_info_csum(&os_info); abs_lc = get_abs_lowcore(); abs_lc->os_info = __pa(&os_info); From 378e32aa81971e8f5594372c6a9d75aa3cf52c99 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 11 Aug 2023 10:10:53 +0200 Subject: [PATCH 482/969] s390/vmcoreinfo: Store virtual memory layout This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. The virtual memory layout is needed for address translation by crash tool when /proc/kcore device is used as the memory image. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/kernel/vmcore_info.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/s390/kernel/vmcore_info.c b/arch/s390/kernel/vmcore_info.c index d296dfc22191..23f7d7619a99 100644 --- a/arch/s390/kernel/vmcore_info.c +++ b/arch/s390/kernel/vmcore_info.c @@ -14,7 +14,9 @@ void arch_crash_save_vmcoreinfo(void) VMCOREINFO_LENGTH(lowcore_ptr, NR_CPUS); vmcoreinfo_append_str("SAMODE31=%lx\n", (unsigned long)__samode31); vmcoreinfo_append_str("EAMODE31=%lx\n", (unsigned long)__eamode31); + vmcoreinfo_append_str("IDENTITYBASE=%lx\n", __identity_base); vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); + vmcoreinfo_append_str("KERNELOFFPHYS=%lx\n", __kaslr_offset_phys); abs_lc = get_abs_lowcore(); abs_lc->vmcore_info = paddr_vmcoreinfo_note(); put_abs_lowcore(abs_lc); From f4cac27dc0d6ba9640c0ce1c42749cfa086cdfb2 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Sat, 30 Sep 2023 10:37:49 +0200 Subject: [PATCH 483/969] s390/crash: Use old os_info to create PT_LOAD headers This is a preparatory rework to allow uncoupling virtual and physical addresses spaces. The vmcore ELF program headers describe virtual memory regions of a crashed kernel. User level tools use that information for the kernel text and data analysis (e.g vmcore-dmesg extracts the kernel log). Currently the kernel image is covered by program headers describing the identity mapping regions. But in the future the kernel image will be mapped into separate region outside of the identity mapping. Create the additional ELF program header that covers kernel image only, so that vmcore tools could locate kernel text and data. Further, the identity mapping in crashed and capture kernels will have different base address. Due to that __va() macro can not be used in the capture kernel. Instead, read crashed kernel identity mapping base address from os_info and use it for PT_LOAD type program headers creation. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/os_info.h | 3 +++ arch/s390/kernel/crash_dump.c | 41 +++++++++++++++++++++++++++++---- arch/s390/kernel/os_info.c | 3 +++ 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/s390/include/asm/os_info.h b/arch/s390/include/asm/os_info.h index 621d49aa9c8d..dea2b37b635e 100644 --- a/arch/s390/include/asm/os_info.h +++ b/arch/s390/include/asm/os_info.h @@ -24,6 +24,9 @@ #define OS_INFO_VMEMMAP 7 #define OS_INFO_AMODE31_START 8 #define OS_INFO_AMODE31_END 9 +#define OS_INFO_IMAGE_START 10 +#define OS_INFO_IMAGE_END 11 +#define OS_INFO_IMAGE_PHYS 12 #define OS_INFO_FLAG_REIPL_CLEAR (1UL << 0) diff --git a/arch/s390/kernel/crash_dump.c b/arch/s390/kernel/crash_dump.c index d09ebb6f5262..9863ebe75019 100644 --- a/arch/s390/kernel/crash_dump.c +++ b/arch/s390/kernel/crash_dump.c @@ -465,7 +465,11 @@ static void *ehdr_init(Elf64_Ehdr *ehdr, int mem_chunk_cnt) ehdr->e_phoff = sizeof(Elf64_Ehdr); ehdr->e_ehsize = sizeof(Elf64_Ehdr); ehdr->e_phentsize = sizeof(Elf64_Phdr); - ehdr->e_phnum = mem_chunk_cnt + 1; + /* + * Number of memory chunk PT_LOAD program headers plus one kernel + * image PT_LOAD program header plus one PT_NOTE program header. + */ + ehdr->e_phnum = mem_chunk_cnt + 1 + 1; return ehdr + 1; } @@ -501,15 +505,16 @@ static int get_mem_chunk_cnt(void) */ static void loads_init(Elf64_Phdr *phdr) { + unsigned long old_identity_base = os_info_old_value(OS_INFO_IDENTITY_BASE); phys_addr_t start, end; u64 idx; for_each_physmem_range(idx, &oldmem_type, &start, &end) { - phdr->p_filesz = end - start; phdr->p_type = PT_LOAD; + phdr->p_vaddr = old_identity_base + start; phdr->p_offset = start; - phdr->p_vaddr = (unsigned long)__va(start); phdr->p_paddr = start; + phdr->p_filesz = end - start; phdr->p_memsz = end - start; phdr->p_flags = PF_R | PF_W | PF_X; phdr->p_align = PAGE_SIZE; @@ -517,6 +522,25 @@ static void loads_init(Elf64_Phdr *phdr) } } +/* + * Prepare PT_LOAD type program header for kernel image region + */ +static void text_init(Elf64_Phdr *phdr) +{ + unsigned long start_phys = os_info_old_value(OS_INFO_IMAGE_PHYS); + unsigned long start = os_info_old_value(OS_INFO_IMAGE_START); + unsigned long end = os_info_old_value(OS_INFO_IMAGE_END); + + phdr->p_type = PT_LOAD; + phdr->p_vaddr = start; + phdr->p_filesz = end - start; + phdr->p_memsz = end - start; + phdr->p_offset = start_phys; + phdr->p_paddr = start_phys; + phdr->p_flags = PF_R | PF_W | PF_X; + phdr->p_align = PAGE_SIZE; +} + /* * Initialize notes (new kernel) */ @@ -557,6 +581,8 @@ static size_t get_elfcorehdr_size(int mem_chunk_cnt) size += nt_vmcoreinfo_size(); /* nt_final */ size += sizeof(Elf64_Nhdr); + /* PT_LOAD type program header for kernel text region */ + size += sizeof(Elf64_Phdr); /* PT_LOADS */ size += mem_chunk_cnt * sizeof(Elf64_Phdr); @@ -568,7 +594,7 @@ static size_t get_elfcorehdr_size(int mem_chunk_cnt) */ int elfcorehdr_alloc(unsigned long long *addr, unsigned long long *size) { - Elf64_Phdr *phdr_notes, *phdr_loads; + Elf64_Phdr *phdr_notes, *phdr_loads, *phdr_text; size_t alloc_size; int mem_chunk_cnt; void *ptr, *hdr; @@ -606,14 +632,19 @@ int elfcorehdr_alloc(unsigned long long *addr, unsigned long long *size) /* Init program headers */ phdr_notes = ptr; ptr = PTR_ADD(ptr, sizeof(Elf64_Phdr)); + phdr_text = ptr; + ptr = PTR_ADD(ptr, sizeof(Elf64_Phdr)); phdr_loads = ptr; ptr = PTR_ADD(ptr, sizeof(Elf64_Phdr) * mem_chunk_cnt); /* Init notes */ hdr_off = PTR_DIFF(ptr, hdr); ptr = notes_init(phdr_notes, ptr, ((unsigned long) hdr) + hdr_off); + /* Init kernel text program header */ + text_init(phdr_text); /* Init loads */ - hdr_off = PTR_DIFF(ptr, hdr); loads_init(phdr_loads); + /* Finalize program headers */ + hdr_off = PTR_DIFF(ptr, hdr); *addr = (unsigned long long) hdr; *size = (unsigned long long) hdr_off; BUG_ON(elfcorehdr_size > alloc_size); diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c index 25bcda341630..3f4dc045a894 100644 --- a/arch/s390/kernel/os_info.c +++ b/arch/s390/kernel/os_info.c @@ -81,6 +81,9 @@ void __init os_info_init(void) os_info_entry_add_val(OS_INFO_VMEMMAP, (unsigned long)vmemmap); os_info_entry_add_val(OS_INFO_AMODE31_START, AMODE31_START); os_info_entry_add_val(OS_INFO_AMODE31_END, AMODE31_END); + os_info_entry_add_val(OS_INFO_IMAGE_START, (unsigned long)_stext); + os_info_entry_add_val(OS_INFO_IMAGE_END, (unsigned long)_end); + os_info_entry_add_val(OS_INFO_IMAGE_PHYS, __pa_symbol(_stext)); os_info.csum = os_info_csum(&os_info); abs_lc = get_abs_lowcore(); abs_lc->os_info = __pa(&os_info); From c98d2ecae08f02bd2dccd24e7e485e9f0211db65 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 1 Mar 2024 07:15:22 +0100 Subject: [PATCH 484/969] s390/mm: Uncouple physical vs virtual address spaces The uncoupling physical vs virtual address spaces brings the following benefits to s390: - virtual memory layout flexibility; - closes the address gap between kernel and modules, it caused s390-only problems in the past (e.g. 'perf' bugs); - allows getting rid of trampolines used for module calls into kernel; - allows simplifying BPF trampoline; - minor performance improvement in branch prediction; - kernel randomization entropy is magnitude bigger, as it is derived from the amount of available virtual, not physical memory; The whole change could be described in two pictures below: before and after the change. Some aspects of the virtual memory layout setup are not clarified (number of page levels, alignment, DMA memory), since these are not a part of this change or secondary with regard to how the uncoupling itself is implemented. The focus of the pictures is to explain why __va() and __pa() macros are implemented the way they are. Memory layout in V==R mode: | Physical | Virtual | +- 0 --------------+- 0 --------------+ identity mapping start | | S390_lowcore | Low-address memory | +- 8 KB -----------+ | | | | | identity | phys == virt | | mapping | virt == phys | | | +- AMODE31_START --+- AMODE31_START --+ .amode31 rand. phys/virt start |.amode31 text/data|.amode31 text/data| +- AMODE31_END ----+- AMODE31_END ----+ .amode31 rand. phys/virt start | | | | | | +- __kaslr_offset, __kaslr_offset_phys| kernel rand. phys/virt start | | | | kernel text/data | kernel text/data | phys == kvirt | | | +------------------+------------------+ kernel phys/virt end | | | | | | | | | | | | +- ident_map_size -+- ident_map_size -+ identity mapping end | | | ... unused gap | | | +---- vmemmap -----+ 'struct page' array start | | | virtually mapped | | memory map | | | +- __abs_lowcore --+ | | | Absolute Lowcore | | | +- __memcpy_real_area | | | Real Memory Copy| | | +- VMALLOC_START --+ vmalloc area start | | | vmalloc area | | | +- MODULES_VADDR --+ modules area start | | | modules area | | | +------------------+ UltraVisor Secure Storage limit | | | ... unused gap | | | +KASAN_SHADOW_START+ KASAN shadow memory start | | | KASAN shadow | | | +------------------+ ASCE limit Memory layout in V!=R mode: | Physical | Virtual | +- 0 --------------+- 0 --------------+ | | S390_lowcore | Low-address memory | +- 8 KB -----------+ | | | | | | | | ... unused gap | | | | +- AMODE31_START --+- AMODE31_START --+ .amode31 rand. phys/virt start |.amode31 text/data|.amode31 text/data| +- AMODE31_END ----+- AMODE31_END ----+ .amode31 rand. phys/virt end (<2GB) | | | | | | +- __kaslr_offset_phys | kernel rand. phys start | | | | kernel text/data | | | | | +------------------+ | kernel phys end | | | | | | | | | | | | +- ident_map_size -+ | | | | ... unused gap | | | +- __identity_base + identity mapping start (>= 2GB) | | | identity | phys == virt - __identity_base | mapping | virt == phys + __identity_base | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +---- vmemmap -----+ 'struct page' array start | | | virtually mapped | | memory map | | | +- __abs_lowcore --+ | | | Absolute Lowcore | | | +- __memcpy_real_area | | | Real Memory Copy| | | +- VMALLOC_START --+ vmalloc area start | | | vmalloc area | | | +- MODULES_VADDR --+ modules area start | | | modules area | | | +- __kaslr_offset -+ kernel rand. virt start | | | kernel text/data | phys == (kvirt - __kaslr_offset) + | | __kaslr_offset_phys +- kernel .bss end + kernel rand. virt end | | | ... unused gap | | | +------------------+ UltraVisor Secure Storage limit | | | ... unused gap | | | +KASAN_SHADOW_START+ KASAN shadow memory start | | | KASAN shadow | | | +------------------+ ASCE limit Unused gaps in the virtual memory layout could be present or not - depending on how partucular system is configured. No page tables are created for the unused gaps. The relative order of vmalloc, modules and kernel image in virtual memory is defined by following considerations: - start of the modules area and end of the kernel should reside within 4GB to accommodate relative 32-bit jumps. The best way to achieve that is to place kernel next to modules; - vmalloc and module areas should locate next to each other to prevent failures and extra reworks in user level tools (makedumpfile, crash, etc.) which treat vmalloc and module addresses similarily; - kernel needs to be the last area in the virtual memory layout to easily distinguish between kernel and non-kernel virtual addresses. That is needed to (again) simplify handling of addresses in user level tools and make __pa() macro faster (see below); Concluding the above, the relative order of the considered virtual areas in memory is: vmalloc - modules - kernel. Therefore, the only change to the current memory layout is moving kernel to the end of virtual address space. With that approach the implementation of __pa() macro is straightforward - all linear virtual addresses less than kernel base are considered identity mapping: phys == virt - __identity_base All addresses greater than kernel base are kernel ones: phys == (kvirt - __kaslr_offset) + __kaslr_offset_phys By contrast, __va() macro deals only with identity mapping addresses: virt == phys + __identity_base .amode31 section is mapped separately and is not covered by __pa() macro. In fact, it could have been handled easily by checking whether a virtual address is within the section or not, but there is no need for that. Thus, let __pa() code do as little machine cycles as possible. The KASAN shadow memory is located at the very end of the virtual memory layout, at addresses higher than the kernel. However, that is not a linear mapping and no code other than KASAN instrumentation or API is expected to access it. When KASLR mode is enabled the kernel base address randomized within a memory window that spans whole unused virtual address space. The size of that window depends from the amount of physical memory available to the system, the limit imposed by UltraVisor (if present) and the vmalloc area size as provided by vmalloc= kernel command line parameter. In case the virtual memory is exhausted the minimum size of the randomization window is forcefully set to 2GB, which amounts to in 15 bits of entropy if KASAN is enabled or 17 bits of entropy in default configuration. The default kernel offset 0x100000 is used as a magic value both in the decompressor code and vmlinux linker script, but it will be removed with a follow-up change. Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- Documentation/arch/s390/index.rst | 1 + Documentation/arch/s390/mm.rst | 111 ++++++++++++++++++++++++++++++ arch/s390/boot/boot.h | 7 +- arch/s390/boot/kaslr.c | 2 +- arch/s390/boot/startup.c | 55 +++++++++++---- arch/s390/boot/vmem.c | 111 ++++++++++++++++-------------- arch/s390/include/asm/page.h | 14 ++-- arch/s390/include/asm/pgtable.h | 6 ++ arch/s390/mm/vmem.c | 2 + 9 files changed, 241 insertions(+), 68 deletions(-) create mode 100644 Documentation/arch/s390/mm.rst diff --git a/Documentation/arch/s390/index.rst b/Documentation/arch/s390/index.rst index 73c79bf586fd..e75a6e5d2505 100644 --- a/Documentation/arch/s390/index.rst +++ b/Documentation/arch/s390/index.rst @@ -8,6 +8,7 @@ s390 Architecture cds 3270 driver-model + mm monreader qeth s390dbf diff --git a/Documentation/arch/s390/mm.rst b/Documentation/arch/s390/mm.rst new file mode 100644 index 000000000000..084adad5eef9 --- /dev/null +++ b/Documentation/arch/s390/mm.rst @@ -0,0 +1,111 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================= +Memory Management +================= + +Virtual memory layout +===================== + +.. note:: + + - Some aspects of the virtual memory layout setup are not + clarified (number of page levels, alignment, DMA memory). + + - Unused gaps in the virtual memory layout could be present + or not - depending on how partucular system is configured. + No page tables are created for the unused gaps. + + - The virtual memory regions are tracked or untracked by KASAN + instrumentation, as well as the KASAN shadow memory itself is + created only when CONFIG_KASAN configuration option is enabled. + +:: + + ============================================================================= + | Physical | Virtual | VM area description + ============================================================================= + +- 0 --------------+- 0 --------------+ + | | S390_lowcore | Low-address memory + | +- 8 KB -----------+ + | | | + | | | + | | ... unused gap | KASAN untracked + | | | + +- AMODE31_START --+- AMODE31_START --+ .amode31 rand. phys/virt start + |.amode31 text/data|.amode31 text/data| KASAN untracked + +- AMODE31_END ----+- AMODE31_END ----+ .amode31 rand. phys/virt end (<2GB) + | | | + | | | + +- __kaslr_offset_phys | kernel rand. phys start + | | | + | kernel text/data | | + | | | + +------------------+ | kernel phys end + | | | + | | | + | | | + | | | + +- ident_map_size -+ | + | | + | ... unused gap | KASAN untracked + | | + +- __identity_base + identity mapping start (>= 2GB) + | | + | identity | phys == virt - __identity_base + | mapping | virt == phys + __identity_base + | | + | | KASAN tracked + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + | | + +---- vmemmap -----+ 'struct page' array start + | | + | virtually mapped | + | memory map | KASAN untracked + | | + +- __abs_lowcore --+ + | | + | Absolute Lowcore | KASAN untracked + | | + +- __memcpy_real_area + | | + | Real Memory Copy| KASAN untracked + | | + +- VMALLOC_START --+ vmalloc area start + | | KASAN untracked or + | vmalloc area | KASAN shallowly populated in case + | | CONFIG_KASAN_VMALLOC=y + +- MODULES_VADDR --+ modules area start + | | KASAN allocated per module or + | modules area | KASAN shallowly populated in case + | | CONFIG_KASAN_VMALLOC=y + +- __kaslr_offset -+ kernel rand. virt start + | | KASAN tracked + | kernel text/data | phys == (kvirt - __kaslr_offset) + + | | __kaslr_offset_phys + +- kernel .bss end + kernel rand. virt end + | | + | ... unused gap | KASAN untracked + | | + +------------------+ UltraVisor Secure Storage limit + | | + | ... unused gap | KASAN untracked + | | + +KASAN_SHADOW_START+ KASAN shadow memory start + | | + | KASAN shadow | KASAN untracked + | | + +------------------+ ASCE limit diff --git a/arch/s390/boot/boot.h b/arch/s390/boot/boot.h index 567d60f78bbc..412cdd490403 100644 --- a/arch/s390/boot/boot.h +++ b/arch/s390/boot/boot.h @@ -74,10 +74,11 @@ void sclp_early_setup_buffer(void); void print_pgm_check_info(void); unsigned long randomize_within_range(unsigned long size, unsigned long align, unsigned long min, unsigned long max); -void setup_vmem(unsigned long asce_limit); +void setup_vmem(unsigned long kernel_start, unsigned long kernel_end, unsigned long asce_limit); void __printf(1, 2) decompressor_printk(const char *fmt, ...); void print_stacktrace(unsigned long sp); void error(char *m); +int get_random(unsigned long limit, unsigned long *value); extern struct machine_info machine; @@ -98,6 +99,10 @@ extern struct vmlinux_info _vmlinux_info; #define vmlinux _vmlinux_info #define __abs_lowcore_pa(x) (((unsigned long)(x) - __abs_lowcore) % sizeof(struct lowcore)) +#define __kernel_va(x) ((void *)((unsigned long)(x) - __kaslr_offset_phys + __kaslr_offset)) +#define __kernel_pa(x) ((unsigned long)(x) - __kaslr_offset + __kaslr_offset_phys) +#define __identity_va(x) ((void *)((unsigned long)(x) + __identity_base)) +#define __identity_pa(x) ((unsigned long)(x) - __identity_base) static inline bool intersects(unsigned long addr0, unsigned long size0, unsigned long addr1, unsigned long size1) diff --git a/arch/s390/boot/kaslr.c b/arch/s390/boot/kaslr.c index 90602101e2ae..bd3bf5ef472d 100644 --- a/arch/s390/boot/kaslr.c +++ b/arch/s390/boot/kaslr.c @@ -43,7 +43,7 @@ static int check_prng(void) return PRNG_MODE_TDES; } -static int get_random(unsigned long limit, unsigned long *value) +int get_random(unsigned long limit, unsigned long *value) { struct prng_parm prng = { /* initial parameter block for tdes mode, copied from libica */ diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 44ef08518f37..3efa1f457451 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -203,7 +203,7 @@ static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, /* Adjust R_390_64 relocations */ for (reloc = vmlinux_relocs_64_start; reloc < vmlinux_relocs_64_end; reloc++) { - loc = (long)*reloc + offset; + loc = (long)*reloc + phys_offset; if (loc < min_addr || loc > max_addr) error("64-bit relocation outside of kernel!\n"); *(u64 *)loc += offset; @@ -263,8 +263,25 @@ static void setup_ident_map_size(unsigned long max_physmem_end) #endif } -static unsigned long setup_kernel_memory_layout(void) +#define FIXMAP_SIZE round_up(MEMCPY_REAL_SIZE + ABS_LOWCORE_MAP_SIZE, sizeof(struct lowcore)) + +static unsigned long get_vmem_size(unsigned long identity_size, + unsigned long vmemmap_size, + unsigned long vmalloc_size, + unsigned long rte_size) { + unsigned long max_mappable, vsize; + + max_mappable = max(identity_size, MAX_DCSS_ADDR); + vsize = round_up(SZ_2G + max_mappable, rte_size) + + round_up(vmemmap_size, rte_size) + + FIXMAP_SIZE + MODULES_LEN + KASLR_LEN; + return size_add(vsize, vmalloc_size); +} + +static unsigned long setup_kernel_memory_layout(unsigned long kernel_size) +{ + unsigned long kernel_start, kernel_end; unsigned long vmemmap_start; unsigned long asce_limit; unsigned long rte_size; @@ -277,12 +294,11 @@ static unsigned long setup_kernel_memory_layout(void) vmemmap_size = SECTION_ALIGN_UP(pages) * sizeof(struct page); /* choose kernel address space layout: 4 or 3 levels. */ - vsize = round_up(ident_map_size, _REGION3_SIZE) + vmemmap_size + - MODULES_LEN + MEMCPY_REAL_SIZE + ABS_LOWCORE_MAP_SIZE; - vsize = size_add(vsize, vmalloc_size); + vsize = get_vmem_size(ident_map_size, vmemmap_size, vmalloc_size, _REGION3_SIZE); if (IS_ENABLED(CONFIG_KASAN) || (vsize > _REGION2_SIZE)) { asce_limit = _REGION1_SIZE; rte_size = _REGION2_SIZE; + vsize = get_vmem_size(ident_map_size, vmemmap_size, vmalloc_size, _REGION2_SIZE); } else { asce_limit = _REGION2_SIZE; rte_size = _REGION3_SIZE; @@ -298,12 +314,26 @@ static unsigned long setup_kernel_memory_layout(void) /* force vmalloc and modules below kasan shadow */ vmax = min(vmax, KASAN_SHADOW_START); #endif - MODULES_END = round_down(vmax, _SEGMENT_SIZE); + kernel_end = vmax; + if (kaslr_enabled()) { + unsigned long kaslr_len, slots, pos; + + vsize = min(vsize, vmax); + kaslr_len = max(KASLR_LEN, vmax - vsize); + slots = DIV_ROUND_UP(kaslr_len - kernel_size, THREAD_SIZE); + if (get_random(slots, &pos)) + pos = 0; + kernel_end -= pos * THREAD_SIZE; + } + kernel_start = round_down(kernel_end - kernel_size, THREAD_SIZE); + __kaslr_offset = kernel_start; + + MODULES_END = round_down(kernel_start, _SEGMENT_SIZE); MODULES_VADDR = MODULES_END - MODULES_LEN; VMALLOC_END = MODULES_VADDR; /* allow vmalloc area to occupy up to about 1/2 of the rest virtual space left */ - vsize = (VMALLOC_END - (MEMCPY_REAL_SIZE + ABS_LOWCORE_MAP_SIZE)) / 2; + vsize = (VMALLOC_END - FIXMAP_SIZE) / 2; vsize = round_down(vsize, _SEGMENT_SIZE); vmalloc_size = min(vmalloc_size, vsize); VMALLOC_START = VMALLOC_END - vmalloc_size; @@ -330,6 +360,7 @@ static unsigned long setup_kernel_memory_layout(void) BUILD_BUG_ON(MAX_DCSS_ADDR > (1UL << MAX_PHYSMEM_BITS)); max_mappable = max(ident_map_size, MAX_DCSS_ADDR); max_mappable = min(max_mappable, vmemmap_start); + __identity_base = round_down(vmemmap_start - max_mappable, rte_size); return asce_limit; } @@ -358,7 +389,6 @@ static void setup_vmalloc_size(void) static void kaslr_adjust_vmlinux_info(unsigned long offset) { - *(unsigned long *)(&vmlinux.entry) += offset; vmlinux.bootdata_off += offset; vmlinux.bootdata_preserved_off += offset; #ifdef CONFIG_PIE_BUILD @@ -386,6 +416,7 @@ void startup_kernel(void) unsigned long max_physmem_end; unsigned long vmlinux_lma = 0; unsigned long amode31_lma = 0; + unsigned long kernel_size; unsigned long asce_limit; unsigned long safe_addr; void *img; @@ -417,7 +448,8 @@ void startup_kernel(void) max_physmem_end = detect_max_physmem_end(); setup_ident_map_size(max_physmem_end); setup_vmalloc_size(); - asce_limit = setup_kernel_memory_layout(); + kernel_size = vmlinux.default_lma + vmlinux.image_size + vmlinux.bss_size; + asce_limit = setup_kernel_memory_layout(kernel_size); /* got final ident_map_size, physmem allocations could be performed now */ physmem_set_usable_limit(ident_map_size); detect_physmem_online_ranges(max_physmem_end); @@ -432,7 +464,6 @@ void startup_kernel(void) if (vmlinux_lma) { __kaslr_offset_phys = vmlinux_lma - vmlinux.default_lma; kaslr_adjust_vmlinux_info(__kaslr_offset_phys); - __kaslr_offset = __kaslr_offset_phys; } } vmlinux_lma = vmlinux_lma ?: vmlinux.default_lma; @@ -472,7 +503,7 @@ void startup_kernel(void) __kaslr_offset, __kaslr_offset_phys); kaslr_adjust_got(__kaslr_offset); free_relocs(); - setup_vmem(asce_limit); + setup_vmem(__kaslr_offset, __kaslr_offset + kernel_size, asce_limit); copy_bootdata(); /* @@ -484,7 +515,7 @@ void startup_kernel(void) /* * Jump to the decompressed kernel entry point and switch DAT mode on. */ - psw.addr = vmlinux.entry; + psw.addr = __kaslr_offset + vmlinux.entry; psw.mask = PSW_KERNEL_BITS; __load_psw(psw); } diff --git a/arch/s390/boot/vmem.c b/arch/s390/boot/vmem.c index 09b10bb6e4d0..86edd432e593 100644 --- a/arch/s390/boot/vmem.c +++ b/arch/s390/boot/vmem.c @@ -27,6 +27,8 @@ enum populate_mode { POPULATE_NONE, POPULATE_DIRECT, POPULATE_ABS_LOWCORE, + POPULATE_IDENTITY, + POPULATE_KERNEL, #ifdef CONFIG_KASAN POPULATE_KASAN_MAP_SHADOW, POPULATE_KASAN_ZERO_SHADOW, @@ -54,7 +56,7 @@ static inline void kasan_populate(unsigned long start, unsigned long end, enum p pgtable_populate(start, end, mode); } -static void kasan_populate_shadow(void) +static void kasan_populate_shadow(unsigned long kernel_start, unsigned long kernel_end) { pmd_t pmd_z = __pmd(__pa(kasan_early_shadow_pte) | _SEGMENT_ENTRY); pud_t pud_z = __pud(__pa(kasan_early_shadow_pmd) | _REGION3_ENTRY); @@ -76,44 +78,20 @@ static void kasan_populate_shadow(void) __arch_set_page_dat(kasan_early_shadow_pmd, 1UL << CRST_ALLOC_ORDER); __arch_set_page_dat(kasan_early_shadow_pte, 1); - /* - * Current memory layout: - * +- 0 -------------+ +- shadow start -+ - * |1:1 ident mapping| /|1/8 of ident map| - * | | / | | - * +-end of ident map+ / +----------------+ - * | ... gap ... | / | kasan | - * | | / | zero page | - * +- vmalloc area -+ / | mapping | - * | vmalloc_size | / | (untracked) | - * +- modules vaddr -+ / +----------------+ - * | 2Gb |/ | unmapped | allocated per module - * +- shadow start -+ +----------------+ - * | 1/8 addr space | | zero pg mapping| (untracked) - * +- shadow end ----+---------+- shadow end ---+ - * - * Current memory layout (KASAN_VMALLOC): - * +- 0 -------------+ +- shadow start -+ - * |1:1 ident mapping| /|1/8 of ident map| - * | | / | | - * +-end of ident map+ / +----------------+ - * | ... gap ... | / | kasan zero page| (untracked) - * | | / | mapping | - * +- vmalloc area -+ / +----------------+ - * | vmalloc_size | / |shallow populate| - * +- modules vaddr -+ / +----------------+ - * | 2Gb |/ |shallow populate| - * +- shadow start -+ +----------------+ - * | 1/8 addr space | | zero pg mapping| (untracked) - * +- shadow end ----+---------+- shadow end ---+ - */ - for_each_physmem_usable_range(i, &start, &end) { - kasan_populate(start, end, POPULATE_KASAN_MAP_SHADOW); - if (memgap_start && physmem_info.info_source == MEM_DETECT_DIAG260) - kasan_populate(memgap_start, start, POPULATE_KASAN_ZERO_SHADOW); + kasan_populate((unsigned long)__identity_va(start), + (unsigned long)__identity_va(end), + POPULATE_KASAN_MAP_SHADOW); + if (memgap_start && physmem_info.info_source == MEM_DETECT_DIAG260) { + kasan_populate((unsigned long)__identity_va(memgap_start), + (unsigned long)__identity_va(start), + POPULATE_KASAN_ZERO_SHADOW); + } memgap_start = end; } + kasan_populate(kernel_start, kernel_end, POPULATE_KASAN_MAP_SHADOW); + kasan_populate(0, (unsigned long)__identity_va(0), POPULATE_KASAN_ZERO_SHADOW); + kasan_populate(AMODE31_START, AMODE31_END, POPULATE_KASAN_ZERO_SHADOW); if (IS_ENABLED(CONFIG_KASAN_VMALLOC)) { untracked_end = VMALLOC_START; /* shallowly populate kasan shadow for vmalloc and modules */ @@ -122,8 +100,9 @@ static void kasan_populate_shadow(void) untracked_end = MODULES_VADDR; } /* populate kasan shadow for untracked memory */ - kasan_populate(ident_map_size, untracked_end, POPULATE_KASAN_ZERO_SHADOW); - kasan_populate(MODULES_END, _REGION1_SIZE, POPULATE_KASAN_ZERO_SHADOW); + kasan_populate((unsigned long)__identity_va(ident_map_size), untracked_end, + POPULATE_KASAN_ZERO_SHADOW); + kasan_populate(kernel_end, _REGION1_SIZE, POPULATE_KASAN_ZERO_SHADOW); } static bool kasan_pgd_populate_zero_shadow(pgd_t *pgd, unsigned long addr, @@ -180,7 +159,9 @@ static bool kasan_pte_populate_zero_shadow(pte_t *pte, enum populate_mode mode) } #else -static inline void kasan_populate_shadow(void) {} +static inline void kasan_populate_shadow(unsigned long kernel_start, unsigned long kernel_end) +{ +} static inline bool kasan_pgd_populate_zero_shadow(pgd_t *pgd, unsigned long addr, unsigned long end, enum populate_mode mode) @@ -263,6 +244,10 @@ static unsigned long _pa(unsigned long addr, unsigned long size, enum populate_m return addr; case POPULATE_ABS_LOWCORE: return __abs_lowcore_pa(addr); + case POPULATE_KERNEL: + return __kernel_pa(addr); + case POPULATE_IDENTITY: + return __identity_pa(addr); #ifdef CONFIG_KASAN case POPULATE_KASAN_MAP_SHADOW: addr = physmem_alloc_top_down(RR_VMEM, size, size); @@ -274,15 +259,22 @@ static unsigned long _pa(unsigned long addr, unsigned long size, enum populate_m } } -static bool can_large_pud(pud_t *pu_dir, unsigned long addr, unsigned long end) +static bool large_allowed(enum populate_mode mode) { - return machine.has_edat2 && + return (mode == POPULATE_DIRECT) || (mode == POPULATE_IDENTITY); +} + +static bool can_large_pud(pud_t *pu_dir, unsigned long addr, unsigned long end, + enum populate_mode mode) +{ + return machine.has_edat2 && large_allowed(mode) && IS_ALIGNED(addr, PUD_SIZE) && (end - addr) >= PUD_SIZE; } -static bool can_large_pmd(pmd_t *pm_dir, unsigned long addr, unsigned long end) +static bool can_large_pmd(pmd_t *pm_dir, unsigned long addr, unsigned long end, + enum populate_mode mode) { - return machine.has_edat1 && + return machine.has_edat1 && large_allowed(mode) && IS_ALIGNED(addr, PMD_SIZE) && (end - addr) >= PMD_SIZE; } @@ -322,7 +314,7 @@ static void pgtable_pmd_populate(pud_t *pud, unsigned long addr, unsigned long e if (pmd_none(*pmd)) { if (kasan_pmd_populate_zero_shadow(pmd, addr, next, mode)) continue; - if (can_large_pmd(pmd, addr, next)) { + if (can_large_pmd(pmd, addr, next, mode)) { entry = __pmd(_pa(addr, _SEGMENT_SIZE, mode)); entry = set_pmd_bit(entry, SEGMENT_KERNEL); if (!machine.has_nx) @@ -355,7 +347,7 @@ static void pgtable_pud_populate(p4d_t *p4d, unsigned long addr, unsigned long e if (pud_none(*pud)) { if (kasan_pud_populate_zero_shadow(pud, addr, next, mode)) continue; - if (can_large_pud(pud, addr, next)) { + if (can_large_pud(pud, addr, next, mode)) { entry = __pud(_pa(addr, _REGION3_SIZE, mode)); entry = set_pud_bit(entry, REGION3_KERNEL); if (!machine.has_nx) @@ -418,11 +410,12 @@ static void pgtable_populate(unsigned long addr, unsigned long end, enum populat } } -void setup_vmem(unsigned long asce_limit) +void setup_vmem(unsigned long kernel_start, unsigned long kernel_end, unsigned long asce_limit) { unsigned long start, end; unsigned long asce_type; unsigned long asce_bits; + pgd_t *init_mm_pgd; int i; /* @@ -433,6 +426,15 @@ void setup_vmem(unsigned long asce_limit) for_each_physmem_online_range(i, &start, &end) __arch_set_page_nodat((void *)start, (end - start) >> PAGE_SHIFT); + /* + * init_mm->pgd contains virtual address of swapper_pg_dir. + * It is unusable at this stage since DAT is yet off. Swap + * it for physical address of swapper_pg_dir and restore + * the virtual address after all page tables are created. + */ + init_mm_pgd = init_mm.pgd; + init_mm.pgd = (pgd_t *)swapper_pg_dir; + if (asce_limit == _REGION1_SIZE) { asce_type = _REGION2_ENTRY_EMPTY; asce_bits = _ASCE_TYPE_REGION2 | _ASCE_TABLE_LENGTH; @@ -451,17 +453,25 @@ void setup_vmem(unsigned long asce_limit) * To allow prefixing the lowcore must be mapped with 4KB pages. * To prevent creation of a large page at address 0 first map * the lowcore and create the identity mapping only afterwards. + * + * Skip 0x100000 bytes for kernel pgtables, as per the linker script: + * . = 0x100000; */ pgtable_populate(0, sizeof(struct lowcore), POPULATE_DIRECT); - for_each_physmem_usable_range(i, &start, &end) - pgtable_populate(start, end, POPULATE_DIRECT); + for_each_physmem_usable_range(i, &start, &end) { + pgtable_populate((unsigned long)__identity_va(start), + (unsigned long)__identity_va(end), + POPULATE_IDENTITY); + } + pgtable_populate(kernel_start + 0x100000, kernel_end, POPULATE_KERNEL); + pgtable_populate(AMODE31_START, AMODE31_END, POPULATE_DIRECT); pgtable_populate(__abs_lowcore, __abs_lowcore + sizeof(struct lowcore), POPULATE_ABS_LOWCORE); pgtable_populate(__memcpy_real_area, __memcpy_real_area + PAGE_SIZE, POPULATE_NONE); - memcpy_real_ptep = __virt_to_kpte(__memcpy_real_area); + memcpy_real_ptep = __identity_va(__virt_to_kpte(__memcpy_real_area)); - kasan_populate_shadow(); + kasan_populate_shadow(kernel_start + 0x100000, kernel_end); S390_lowcore.kernel_asce.val = swapper_pg_dir | asce_bits; S390_lowcore.user_asce = s390_invalid_asce; @@ -471,4 +481,5 @@ void setup_vmem(unsigned long asce_limit) local_ctl_load(13, &S390_lowcore.kernel_asce); init_mm.context.asce = S390_lowcore.kernel_asce.val; + init_mm.pgd = init_mm_pgd; } diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 95403750d25a..b39d724ab6f6 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -208,16 +208,22 @@ static inline int kaslr_enabled(void) #define __PAGE_OFFSET __identity_base #define PAGE_OFFSET __PAGE_OFFSET -#define __pa_nodebug(x) ((unsigned long)(x)) - #ifdef __DECOMPRESSOR +#define __pa_nodebug(x) ((unsigned long)(x)) #define __pa(x) __pa_nodebug(x) #define __pa32(x) __pa(x) #define __va(x) ((void *)(unsigned long)(x)) #else /* __DECOMPRESSOR */ +static inline unsigned long __pa_nodebug(unsigned long x) +{ + if (x < __kaslr_offset) + return x - __identity_base; + return x - __kaslr_offset + __kaslr_offset_phys; +} + #ifdef CONFIG_DEBUG_VIRTUAL unsigned long __phys_addr(unsigned long x, bool is_31bit); @@ -233,7 +239,7 @@ static inline unsigned long __phys_addr(unsigned long x, bool is_31bit) #define __pa(x) __phys_addr((unsigned long)(x), false) #define __pa32(x) __phys_addr((unsigned long)(x), true) -#define __va(x) ((void *)(unsigned long)(x)) +#define __va(x) ((void *)((unsigned long)(x) + __identity_base)) #endif /* __DECOMPRESSOR */ @@ -258,7 +264,7 @@ static inline unsigned long virt_to_pfn(const void *kaddr) #define virt_to_page(kaddr) pfn_to_page(virt_to_pfn(kaddr)) #define page_to_virt(page) pfn_to_virt(page_to_pfn(page)) -#define virt_addr_valid(kaddr) pfn_valid(phys_to_pfn(__pa_nodebug(kaddr))) +#define virt_addr_valid(kaddr) pfn_valid(phys_to_pfn(__pa_nodebug((unsigned long)(kaddr)))) #define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_NON_EXEC diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 60950e7a25f5..0f6321ff427b 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -107,6 +107,12 @@ static inline int is_module_addr(void *addr) return 1; } +#ifdef CONFIG_RANDOMIZE_BASE +#define KASLR_LEN (1UL << 31) +#else +#define KASLR_LEN 0UL +#endif + /* * A 64 bit pagetable entry of S390 has following format: * | PFRA |0IPC| OS | diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c index 917b8a37383a..41c714e21292 100644 --- a/arch/s390/mm/vmem.c +++ b/arch/s390/mm/vmem.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include static DEFINE_MUTEX(vmem_mutex); From 54f2ecc3188f78723267826f634e0747169f8685 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Tue, 26 Sep 2023 15:58:51 +0200 Subject: [PATCH 485/969] s390: Map kernel at fixed location when KASLR is disabled Since kernel virtual and physical address spaces are uncoupled the kernel is mapped at the top of the virtual address space in case KASLR is disabled. That does not pose any issue with regard to the kernel booting and operation, but makes it difficult to use a generated vmlinux with some debugging tools (e.g. gdb), because the exact location of the kernel image in virtual memory is unknown. Make that location known and introduce CONFIG_KERNEL_IMAGE_BASE configuration option. A custom CONFIG_KERNEL_IMAGE_BASE value that would break the virtual memory layout leads to a build error. The kernel image size is defined by KERNEL_IMAGE_SIZE macro and set to 512 MB, by analogy with x86. Suggested-by: Vasily Gorbik Signed-off-by: Alexander Gordeev --- .../admin-guide/kernel-parameters.txt | 4 ++- arch/s390/Kconfig | 19 +++++++++++ arch/s390/boot/startup.c | 33 ++++++++++++++----- arch/s390/include/asm/page.h | 4 +++ arch/s390/tools/relocs.c | 2 +- 5 files changed, 51 insertions(+), 11 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index bb884c14b2f6..b74741e0a053 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4780,7 +4780,9 @@ prot_virt= [S390] enable hosting protected virtual machines isolated from the hypervisor (if hardware supports - that). + that). If enabled, the default kernel base address + might be overridden even when Kernel Address Space + Layout Randomization is disabled. Format: psi= [KNL] Enable or disable pressure stall information diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 9515d4bf1683..df6b371ed214 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -614,6 +614,25 @@ config RANDOMIZE_BASE as a security feature that deters exploit attempts relying on knowledge of the location of kernel internals. +config KERNEL_IMAGE_BASE + hex "Kernel image base address" + range 0x100000 0x1FFFFFE0000000 if !KASAN + range 0x100000 0x1BFFFFE0000000 if KASAN + default 0x3FFE0000000 if !KASAN + default 0x7FFFE0000000 if KASAN + help + This is the address at which the kernel image is loaded in case + Kernel Address Space Layout Randomization (KASLR) is disabled. + + In case the Protected virtualization guest support is enabled the + Ultravisor imposes a virtual address limit. If the value of this + option leads to the kernel image exceeding the Ultravisor limit, + this option is ignored and the image is loaded below the limit. + + If the value of this option leads to the kernel image overlapping + the virtual memory where other data structures are located, this + option is ignored and the image is loaded above the structures. + endmenu menu "Memory setup" diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 3efa1f457451..fc9c1d51ef8d 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -281,8 +281,8 @@ static unsigned long get_vmem_size(unsigned long identity_size, static unsigned long setup_kernel_memory_layout(unsigned long kernel_size) { - unsigned long kernel_start, kernel_end; unsigned long vmemmap_start; + unsigned long kernel_start; unsigned long asce_limit; unsigned long rte_size; unsigned long pages; @@ -294,11 +294,18 @@ static unsigned long setup_kernel_memory_layout(unsigned long kernel_size) vmemmap_size = SECTION_ALIGN_UP(pages) * sizeof(struct page); /* choose kernel address space layout: 4 or 3 levels. */ + BUILD_BUG_ON(!IS_ALIGNED(__NO_KASLR_START_KERNEL, THREAD_SIZE)); + BUILD_BUG_ON(__NO_KASLR_END_KERNEL > _REGION1_SIZE); vsize = get_vmem_size(ident_map_size, vmemmap_size, vmalloc_size, _REGION3_SIZE); - if (IS_ENABLED(CONFIG_KASAN) || (vsize > _REGION2_SIZE)) { + if (IS_ENABLED(CONFIG_KASAN) || __NO_KASLR_END_KERNEL > _REGION2_SIZE || + (vsize > _REGION2_SIZE && kaslr_enabled())) { asce_limit = _REGION1_SIZE; - rte_size = _REGION2_SIZE; - vsize = get_vmem_size(ident_map_size, vmemmap_size, vmalloc_size, _REGION2_SIZE); + if (__NO_KASLR_END_KERNEL > _REGION2_SIZE) { + rte_size = _REGION2_SIZE; + vsize = get_vmem_size(ident_map_size, vmemmap_size, vmalloc_size, _REGION2_SIZE); + } else { + rte_size = _REGION3_SIZE; + } } else { asce_limit = _REGION2_SIZE; rte_size = _REGION3_SIZE; @@ -308,24 +315,32 @@ static unsigned long setup_kernel_memory_layout(unsigned long kernel_size) * Forcing modules and vmalloc area under the ultravisor * secure storage limit, so that any vmalloc allocation * we do could be used to back secure guest storage. + * + * Assume the secure storage limit always exceeds _REGION2_SIZE, + * otherwise asce_limit and rte_size would have been adjusted. */ vmax = adjust_to_uv_max(asce_limit); #ifdef CONFIG_KASAN + BUILD_BUG_ON(__NO_KASLR_END_KERNEL > KASAN_SHADOW_START); /* force vmalloc and modules below kasan shadow */ vmax = min(vmax, KASAN_SHADOW_START); #endif - kernel_end = vmax; + vsize = min(vsize, vmax); if (kaslr_enabled()) { - unsigned long kaslr_len, slots, pos; + unsigned long kernel_end, kaslr_len, slots, pos; - vsize = min(vsize, vmax); kaslr_len = max(KASLR_LEN, vmax - vsize); slots = DIV_ROUND_UP(kaslr_len - kernel_size, THREAD_SIZE); if (get_random(slots, &pos)) pos = 0; - kernel_end -= pos * THREAD_SIZE; + kernel_end = vmax - pos * THREAD_SIZE; + kernel_start = round_down(kernel_end - kernel_size, THREAD_SIZE); + } else if (vmax < __NO_KASLR_END_KERNEL || vsize > __NO_KASLR_END_KERNEL) { + kernel_start = round_down(vmax - kernel_size, THREAD_SIZE); + decompressor_printk("The kernel base address is forced to %lx\n", kernel_start); + } else { + kernel_start = __NO_KASLR_START_KERNEL; } - kernel_start = round_down(kernel_end - kernel_size, THREAD_SIZE); __kaslr_offset = kernel_start; MODULES_END = round_down(kernel_start, _SEGMENT_SIZE); diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index b39d724ab6f6..e1b6355ddbef 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -273,4 +273,8 @@ static inline unsigned long virt_to_pfn(const void *kaddr) #include #include +#define KERNEL_IMAGE_SIZE (512 * 1024 * 1024) +#define __NO_KASLR_START_KERNEL CONFIG_KERNEL_IMAGE_BASE +#define __NO_KASLR_END_KERNEL (__NO_KASLR_START_KERNEL + KERNEL_IMAGE_SIZE) + #endif /* _S390_PAGE_H */ diff --git a/arch/s390/tools/relocs.c b/arch/s390/tools/relocs.c index 30a732c808f3..b4f35506779b 100644 --- a/arch/s390/tools/relocs.c +++ b/arch/s390/tools/relocs.c @@ -280,7 +280,7 @@ static int do_reloc(struct section *sec, Elf_Rel *rel) case R_390_GOTOFF64: break; case R_390_64: - add_reloc(&relocs64, offset); + add_reloc(&relocs64, offset - (ehdr.e_entry - 0x100000)); break; default: die("Unsupported relocation type: %d\n", r_type); From 56b1069c40c777e9cba595a62857293628067d65 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Fri, 22 Mar 2024 14:39:57 +0100 Subject: [PATCH 486/969] s390/boot: Rework deployment of the kernel image Rework deployment of kernel image for both compressed and uncompressed variants as defined by CONFIG_KERNEL_UNCOMPRESSED kernel configuration variable. In case CONFIG_KERNEL_UNCOMPRESSED is disabled avoid uncompressing the kernel to a temporary buffer and copying it to the target address. Instead, uncompress it directly to the target destination. In case CONFIG_KERNEL_UNCOMPRESSED is enabled avoid moving the kernel to default 0x100000 location when KASLR is disabled or failed. Instead, use the uncompressed kernel image directly. In case KASLR is disabled or failed .amode31 section location in memory is not randomized and precedes the kernel image. In case CONFIG_KERNEL_UNCOMPRESSED is disabled that location overlaps the area used by the decompression algorithm. That is fine, since that area is not used after the decompression finished and the size of .amode31 section is not expected to exceed BOOT_HEAP_SIZE ever. There is no decompression in case CONFIG_KERNEL_UNCOMPRESSED is enabled. Therefore, rename decompress_kernel() to deploy_kernel(), which better describes both uncompressed and compressed cases. Introduce AMODE31_SIZE macro to avoid immediate value of 0x3000 (the size of .amode31 section) in the decompressor linker script. Modify the vmlinux linker script to force the size of .amode31 section to AMODE31_SIZE (the value of (_eamode31 - _samode31) could otherwise differ as result of compiler options used). Introduce __START_KERNEL macro that defines the kernel ELF image entry point and set it to the currrent value of 0x100000. Signed-off-by: Alexander Gordeev --- arch/s390/boot/boot.h | 1 - arch/s390/boot/decompressor.c | 15 +----- arch/s390/boot/decompressor.h | 8 ++- arch/s390/boot/startup.c | 90 ++++++++++++++++++---------------- arch/s390/boot/vmem.c | 7 +-- arch/s390/boot/vmlinux.lds.S | 3 +- arch/s390/include/asm/page.h | 3 ++ arch/s390/kernel/vmlinux.lds.S | 5 +- arch/s390/tools/relocs.c | 2 +- 9 files changed, 62 insertions(+), 72 deletions(-) diff --git a/arch/s390/boot/boot.h b/arch/s390/boot/boot.h index 412cdd490403..85da1c6cef4f 100644 --- a/arch/s390/boot/boot.h +++ b/arch/s390/boot/boot.h @@ -17,7 +17,6 @@ struct machine_info { }; struct vmlinux_info { - unsigned long default_lma; unsigned long entry; unsigned long image_size; /* does not include .bss */ unsigned long bss_size; /* uncompressed image .bss size */ diff --git a/arch/s390/boot/decompressor.c b/arch/s390/boot/decompressor.c index d762733a0753..f478e8e9cbda 100644 --- a/arch/s390/boot/decompressor.c +++ b/arch/s390/boot/decompressor.c @@ -63,24 +63,13 @@ static unsigned long free_mem_end_ptr = (unsigned long) _end + BOOT_HEAP_SIZE; #include "../../../../lib/decompress_unzstd.c" #endif -#define decompress_offset ALIGN((unsigned long)_end + BOOT_HEAP_SIZE, PAGE_SIZE) - unsigned long mem_safe_offset(void) { - /* - * due to 4MB HEAD_SIZE for bzip2 - * 'decompress_offset + vmlinux.image_size' could be larger than - * kernel at final position + its .bss, so take the larger of two - */ - return max(decompress_offset + vmlinux.image_size, - vmlinux.default_lma + vmlinux.image_size + vmlinux.bss_size); + return ALIGN(free_mem_end_ptr, PAGE_SIZE); } -void *decompress_kernel(void) +void deploy_kernel(void *output) { - void *output = (void *)decompress_offset; - __decompress(_compressed_start, _compressed_end - _compressed_start, NULL, NULL, output, vmlinux.image_size, NULL, error); - return output; } diff --git a/arch/s390/boot/decompressor.h b/arch/s390/boot/decompressor.h index 92b81d2ea35d..4f966f06bd65 100644 --- a/arch/s390/boot/decompressor.h +++ b/arch/s390/boot/decompressor.h @@ -2,11 +2,9 @@ #ifndef BOOT_COMPRESSED_DECOMPRESSOR_H #define BOOT_COMPRESSED_DECOMPRESSOR_H -#ifdef CONFIG_KERNEL_UNCOMPRESSED -static inline void *decompress_kernel(void) { return NULL; } -#else -void *decompress_kernel(void); -#endif +#ifndef CONFIG_KERNEL_UNCOMPRESSED unsigned long mem_safe_offset(void); +void deploy_kernel(void *output); +#endif #endif /* BOOT_COMPRESSED_DECOMPRESSOR_H */ diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index fc9c1d51ef8d..949eff7107cc 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -109,9 +109,19 @@ static void setup_lpp(void) } #ifdef CONFIG_KERNEL_UNCOMPRESSED -unsigned long mem_safe_offset(void) +static unsigned long mem_safe_offset(void) { - return vmlinux.default_lma + vmlinux.image_size + vmlinux.bss_size; + return (unsigned long)_compressed_start; +} + +static void deploy_kernel(void *output) +{ + void *uncompressed_start = (void *)_compressed_start; + + if (output == uncompressed_start) + return; + memmove(output, uncompressed_start, vmlinux.image_size); + memset(uncompressed_start, 0, vmlinux.image_size); } #endif @@ -154,18 +164,18 @@ static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, rela_end = (Elf64_Rela *) vmlinux.rela_dyn_end; dynsym = (Elf64_Sym *) vmlinux.dynsym_start; for (rela = rela_start; rela < rela_end; rela++) { - loc = rela->r_offset + phys_offset; + loc = rela->r_offset + phys_offset - __START_KERNEL; val = rela->r_addend; r_sym = ELF64_R_SYM(rela->r_info); if (r_sym) { if (dynsym[r_sym].st_shndx != SHN_UNDEF) - val += dynsym[r_sym].st_value + offset; + val += dynsym[r_sym].st_value + offset - __START_KERNEL; } else { /* - * 0 == undefined symbol table index (STN_UNDEF), + * 0 == undefined symbol table index (SHN_UNDEF), * used for R_390_RELATIVE, only add KASLR offset */ - val += offset; + val += offset - __START_KERNEL; } r_type = ELF64_R_TYPE(rela->r_info); rc = arch_kexec_do_relocs(r_type, (void *) loc, val, 0); @@ -206,7 +216,7 @@ static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, loc = (long)*reloc + phys_offset; if (loc < min_addr || loc > max_addr) error("64-bit relocation outside of kernel!\n"); - *(u64 *)loc += offset; + *(u64 *)loc += offset - __START_KERNEL; } } @@ -219,7 +229,7 @@ static void kaslr_adjust_got(unsigned long offset) * reason. Adjust the GOT entries. */ for (entry = (u64 *)vmlinux.got_start; entry < (u64 *)vmlinux.got_end; entry++) - *entry += offset; + *entry += offset - __START_KERNEL; } #endif @@ -294,6 +304,7 @@ static unsigned long setup_kernel_memory_layout(unsigned long kernel_size) vmemmap_size = SECTION_ALIGN_UP(pages) * sizeof(struct page); /* choose kernel address space layout: 4 or 3 levels. */ + BUILD_BUG_ON(!IS_ALIGNED(__START_KERNEL, THREAD_SIZE)); BUILD_BUG_ON(!IS_ALIGNED(__NO_KASLR_START_KERNEL, THREAD_SIZE)); BUILD_BUG_ON(__NO_KASLR_END_KERNEL > _REGION1_SIZE); vsize = get_vmem_size(ident_map_size, vmemmap_size, vmalloc_size, _REGION3_SIZE); @@ -383,9 +394,9 @@ static unsigned long setup_kernel_memory_layout(unsigned long kernel_size) /* * This function clears the BSS section of the decompressed Linux kernel and NOT the decompressor's. */ -static void clear_bss_section(unsigned long vmlinux_lma) +static void clear_bss_section(unsigned long kernel_start) { - memset((void *)vmlinux_lma + vmlinux.image_size, 0, vmlinux.bss_size); + memset((void *)kernel_start + vmlinux.image_size, 0, vmlinux.bss_size); } /* @@ -402,7 +413,7 @@ static void setup_vmalloc_size(void) vmalloc_size = max(size, vmalloc_size); } -static void kaslr_adjust_vmlinux_info(unsigned long offset) +static void kaslr_adjust_vmlinux_info(long offset) { vmlinux.bootdata_off += offset; vmlinux.bootdata_preserved_off += offset; @@ -426,24 +437,30 @@ static void kaslr_adjust_vmlinux_info(unsigned long offset) #endif } +static void fixup_vmlinux_info(void) +{ + vmlinux.entry -= __START_KERNEL; + kaslr_adjust_vmlinux_info(-__START_KERNEL); +} + void startup_kernel(void) { - unsigned long max_physmem_end; - unsigned long vmlinux_lma = 0; + unsigned long kernel_size = vmlinux.image_size + vmlinux.bss_size; + unsigned long nokaslr_offset_phys = mem_safe_offset(); unsigned long amode31_lma = 0; - unsigned long kernel_size; + unsigned long max_physmem_end; unsigned long asce_limit; unsigned long safe_addr; - void *img; psw_t psw; + fixup_vmlinux_info(); setup_lpp(); - safe_addr = mem_safe_offset(); + safe_addr = PAGE_ALIGN(nokaslr_offset_phys + kernel_size); /* - * Reserve decompressor memory together with decompression heap, buffer and - * memory which might be occupied by uncompressed kernel at default 1Mb - * position (if KASLR is off or failed). + * Reserve decompressor memory together with decompression heap, + * buffer and memory which might be occupied by uncompressed kernel + * (if KASLR is off or failed). */ physmem_reserve(RR_DECOMPRESSOR, 0, safe_addr); if (IS_ENABLED(CONFIG_BLK_DEV_INITRD) && parmarea.initrd_size) @@ -463,7 +480,6 @@ void startup_kernel(void) max_physmem_end = detect_max_physmem_end(); setup_ident_map_size(max_physmem_end); setup_vmalloc_size(); - kernel_size = vmlinux.default_lma + vmlinux.image_size + vmlinux.bss_size; asce_limit = setup_kernel_memory_layout(kernel_size); /* got final ident_map_size, physmem allocations could be performed now */ physmem_set_usable_limit(ident_map_size); @@ -472,32 +488,20 @@ void startup_kernel(void) rescue_initrd(safe_addr, ident_map_size); rescue_relocs(); - if (kaslr_enabled()) { - vmlinux_lma = randomize_within_range(vmlinux.image_size + vmlinux.bss_size, - THREAD_SIZE, vmlinux.default_lma, - ident_map_size); - if (vmlinux_lma) { - __kaslr_offset_phys = vmlinux_lma - vmlinux.default_lma; - kaslr_adjust_vmlinux_info(__kaslr_offset_phys); - } - } - vmlinux_lma = vmlinux_lma ?: vmlinux.default_lma; - physmem_reserve(RR_VMLINUX, vmlinux_lma, vmlinux.image_size + vmlinux.bss_size); - - if (!IS_ENABLED(CONFIG_KERNEL_UNCOMPRESSED)) { - img = decompress_kernel(); - memmove((void *)vmlinux_lma, img, vmlinux.image_size); - } else if (__kaslr_offset_phys) { - img = (void *)vmlinux.default_lma; - memmove((void *)vmlinux_lma, img, vmlinux.image_size); - memset(img, 0, vmlinux.image_size); - } + if (kaslr_enabled()) + __kaslr_offset_phys = randomize_within_range(kernel_size, THREAD_SIZE, 0, ident_map_size); + if (!__kaslr_offset_phys) + __kaslr_offset_phys = nokaslr_offset_phys; + kaslr_adjust_vmlinux_info(__kaslr_offset_phys); + physmem_reserve(RR_VMLINUX, __kaslr_offset_phys, kernel_size); + deploy_kernel((void *)__kaslr_offset_phys); /* vmlinux decompression is done, shrink reserved low memory */ physmem_reserve(RR_DECOMPRESSOR, 0, (unsigned long)_decompressor_end); if (kaslr_enabled()) amode31_lma = randomize_within_range(vmlinux.amode31_size, PAGE_SIZE, 0, SZ_2G); - amode31_lma = amode31_lma ?: vmlinux.default_lma - vmlinux.amode31_size; + if (!amode31_lma) + amode31_lma = __kaslr_offset_phys - vmlinux.amode31_size; physmem_reserve(RR_AMODE31, amode31_lma, vmlinux.amode31_size); /* @@ -513,8 +517,8 @@ void startup_kernel(void) * - copy_bootdata() must follow setup_vmem() to propagate changes * to bootdata made by setup_vmem() */ - clear_bss_section(vmlinux_lma); - kaslr_adjust_relocs(vmlinux_lma, vmlinux_lma + vmlinux.image_size, + clear_bss_section(__kaslr_offset_phys); + kaslr_adjust_relocs(__kaslr_offset_phys, __kaslr_offset_phys + vmlinux.image_size, __kaslr_offset, __kaslr_offset_phys); kaslr_adjust_got(__kaslr_offset); free_relocs(); diff --git a/arch/s390/boot/vmem.c b/arch/s390/boot/vmem.c index 86edd432e593..96d48b7112d4 100644 --- a/arch/s390/boot/vmem.c +++ b/arch/s390/boot/vmem.c @@ -453,9 +453,6 @@ void setup_vmem(unsigned long kernel_start, unsigned long kernel_end, unsigned l * To allow prefixing the lowcore must be mapped with 4KB pages. * To prevent creation of a large page at address 0 first map * the lowcore and create the identity mapping only afterwards. - * - * Skip 0x100000 bytes for kernel pgtables, as per the linker script: - * . = 0x100000; */ pgtable_populate(0, sizeof(struct lowcore), POPULATE_DIRECT); for_each_physmem_usable_range(i, &start, &end) { @@ -463,7 +460,7 @@ void setup_vmem(unsigned long kernel_start, unsigned long kernel_end, unsigned l (unsigned long)__identity_va(end), POPULATE_IDENTITY); } - pgtable_populate(kernel_start + 0x100000, kernel_end, POPULATE_KERNEL); + pgtable_populate(kernel_start, kernel_end, POPULATE_KERNEL); pgtable_populate(AMODE31_START, AMODE31_END, POPULATE_DIRECT); pgtable_populate(__abs_lowcore, __abs_lowcore + sizeof(struct lowcore), POPULATE_ABS_LOWCORE); @@ -471,7 +468,7 @@ void setup_vmem(unsigned long kernel_start, unsigned long kernel_end, unsigned l POPULATE_NONE); memcpy_real_ptep = __identity_va(__virt_to_kpte(__memcpy_real_area)); - kasan_populate_shadow(kernel_start + 0x100000, kernel_end); + kasan_populate_shadow(kernel_start, kernel_end); S390_lowcore.kernel_asce.val = swapper_pg_dir | asce_bits; S390_lowcore.user_asce = s390_invalid_asce; diff --git a/arch/s390/boot/vmlinux.lds.S b/arch/s390/boot/vmlinux.lds.S index 3d7ea585ab99..9d6d26908355 100644 --- a/arch/s390/boot/vmlinux.lds.S +++ b/arch/s390/boot/vmlinux.lds.S @@ -100,7 +100,8 @@ SECTIONS _decompressor_end = .; #ifdef CONFIG_KERNEL_UNCOMPRESSED - . = 0x100000; + . = ALIGN(PAGE_SIZE); + . += AMODE31_SIZE; /* .amode31 section */ #else . = ALIGN(8); #endif diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index e1b6355ddbef..224ff9d433ea 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -273,7 +273,10 @@ static inline unsigned long virt_to_pfn(const void *kaddr) #include #include +#define AMODE31_SIZE (3 * PAGE_SIZE) + #define KERNEL_IMAGE_SIZE (512 * 1024 * 1024) +#define __START_KERNEL 0x100000 #define __NO_KASLR_START_KERNEL CONFIG_KERNEL_IMAGE_BASE #define __NO_KASLR_END_KERNEL (__NO_KASLR_START_KERNEL + KERNEL_IMAGE_SIZE) diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index 48de296e8905..023fade1da3b 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -39,7 +39,7 @@ PHDRS { SECTIONS { - . = 0x100000; + . = __START_KERNEL; .text : { _stext = .; /* Start of text section */ _text = .; /* Text and read-only data */ @@ -183,7 +183,7 @@ SECTIONS .amode31.data : { *(.amode31.data) } - . = ALIGN(PAGE_SIZE); + . = _samode31 + AMODE31_SIZE; _eamode31 = .; /* early.c uses stsi, which requires page aligned data. */ @@ -230,7 +230,6 @@ SECTIONS * it should match struct vmlinux_info */ .vmlinux.info 0 (INFO) : { - QUAD(_stext) /* default_lma */ QUAD(startup_continue) /* entry */ QUAD(__bss_start - _stext) /* image_size */ QUAD(__bss_stop - __bss_start) /* bss_size */ diff --git a/arch/s390/tools/relocs.c b/arch/s390/tools/relocs.c index b4f35506779b..a74dbd5c9896 100644 --- a/arch/s390/tools/relocs.c +++ b/arch/s390/tools/relocs.c @@ -280,7 +280,7 @@ static int do_reloc(struct section *sec, Elf_Rel *rel) case R_390_GOTOFF64: break; case R_390_64: - add_reloc(&relocs64, offset - (ehdr.e_entry - 0x100000)); + add_reloc(&relocs64, offset - ehdr.e_entry); break; default: die("Unsupported relocation type: %d\n", r_type); From 236d70f82bec6e1f3ab50a5242fc1c7f779e941e Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Mon, 26 Feb 2024 11:47:40 +0100 Subject: [PATCH 487/969] s390/boot: Do not rescue .vmlinux.relocs section The .vmlinux.relocs section is moved in front of the compressed kernel. The interim section rescue step is avoided as result. Suggested-by: Sumanth Korikkar Signed-off-by: Alexander Gordeev --- arch/s390/boot/startup.c | 35 +++++++++++----------------- arch/s390/boot/vmlinux.lds.S | 27 +++++++-------------- arch/s390/include/asm/physmem_info.h | 1 - 3 files changed, 22 insertions(+), 41 deletions(-) diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 949eff7107cc..246d54499c20 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -185,26 +185,7 @@ static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, } static void kaslr_adjust_got(unsigned long offset) {} -static void rescue_relocs(void) {} -static void free_relocs(void) {} #else -static int *vmlinux_relocs_64_start; -static int *vmlinux_relocs_64_end; - -static void rescue_relocs(void) -{ - unsigned long size = __vmlinux_relocs_64_end - __vmlinux_relocs_64_start; - - vmlinux_relocs_64_start = (void *)physmem_alloc_top_down(RR_RELOC, size, 0); - vmlinux_relocs_64_end = (void *)vmlinux_relocs_64_start + size; - memmove(vmlinux_relocs_64_start, __vmlinux_relocs_64_start, size); -} - -static void free_relocs(void) -{ - physmem_free(RR_RELOC); -} - static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, unsigned long offset, unsigned long phys_offset) { @@ -212,7 +193,7 @@ static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, long loc; /* Adjust R_390_64 relocations */ - for (reloc = vmlinux_relocs_64_start; reloc < vmlinux_relocs_64_end; reloc++) { + for (reloc = (int *)__vmlinux_relocs_64_start; reloc < (int *)__vmlinux_relocs_64_end; reloc++) { loc = (long)*reloc + phys_offset; if (loc < min_addr || loc > max_addr) error("64-bit relocation outside of kernel!\n"); @@ -486,7 +467,6 @@ void startup_kernel(void) detect_physmem_online_ranges(max_physmem_end); save_ipl_cert_comp_list(); rescue_initrd(safe_addr, ident_map_size); - rescue_relocs(); if (kaslr_enabled()) __kaslr_offset_phys = randomize_within_range(kernel_size, THREAD_SIZE, 0, ident_map_size); @@ -498,6 +478,18 @@ void startup_kernel(void) /* vmlinux decompression is done, shrink reserved low memory */ physmem_reserve(RR_DECOMPRESSOR, 0, (unsigned long)_decompressor_end); + + /* + * In case KASLR is enabled the randomized location of .amode31 + * section might overlap with .vmlinux.relocs section. To avoid that + * the below randomize_within_range() could have been called with + * __vmlinux_relocs_64_end as the lower range address. However, + * .amode31 section is written to by the decompressed kernel - at + * that time the contents of .vmlinux.relocs is not needed anymore. + * Conversly, .vmlinux.relocs is read only by the decompressor, even + * before the kernel started. Therefore, in case the two sections + * overlap there is no risk of corrupting any data. + */ if (kaslr_enabled()) amode31_lma = randomize_within_range(vmlinux.amode31_size, PAGE_SIZE, 0, SZ_2G); if (!amode31_lma) @@ -521,7 +513,6 @@ void startup_kernel(void) kaslr_adjust_relocs(__kaslr_offset_phys, __kaslr_offset_phys + vmlinux.image_size, __kaslr_offset, __kaslr_offset_phys); kaslr_adjust_got(__kaslr_offset); - free_relocs(); setup_vmem(__kaslr_offset, __kaslr_offset + kernel_size, asce_limit); copy_bootdata(); diff --git a/arch/s390/boot/vmlinux.lds.S b/arch/s390/boot/vmlinux.lds.S index 9d6d26908355..d6454ec01e22 100644 --- a/arch/s390/boot/vmlinux.lds.S +++ b/arch/s390/boot/vmlinux.lds.S @@ -99,6 +99,15 @@ SECTIONS _decompressor_end = .; +#ifndef CONFIG_PIE_BUILD + . = ALIGN(4); + .vmlinux.relocs : { + __vmlinux_relocs_64_start = .; + *(.vmlinux.relocs_64) + __vmlinux_relocs_64_end = .; + } +#endif + #ifdef CONFIG_KERNEL_UNCOMPRESSED . = ALIGN(PAGE_SIZE); . += AMODE31_SIZE; /* .amode31 section */ @@ -111,24 +120,6 @@ SECTIONS _compressed_end = .; } -#ifndef CONFIG_PIE_BUILD - /* - * When the kernel is built with CONFIG_KERNEL_UNCOMPRESSED, the entire - * uncompressed vmlinux.bin is positioned in the bzImage decompressor - * image at the default kernel LMA of 0x100000, enabling it to be - * executed in-place. However, the size of .vmlinux.relocs could be - * large enough to cause an overlap with the uncompressed kernel at the - * address 0x100000. To address this issue, .vmlinux.relocs is - * positioned after the .rodata.compressed. - */ - . = ALIGN(4); - .vmlinux.relocs : { - __vmlinux_relocs_64_start = .; - *(.vmlinux.relocs_64) - __vmlinux_relocs_64_end = .; - } -#endif - #define SB_TRAILER_SIZE 32 /* Trailer needed for Secure Boot */ . += SB_TRAILER_SIZE; /* make sure .sb.trailer does not overwrite the previous section */ diff --git a/arch/s390/include/asm/physmem_info.h b/arch/s390/include/asm/physmem_info.h index d2f1cc742695..f45cfc8bc233 100644 --- a/arch/s390/include/asm/physmem_info.h +++ b/arch/s390/include/asm/physmem_info.h @@ -22,7 +22,6 @@ enum reserved_range_type { RR_DECOMPRESSOR, RR_INITRD, RR_VMLINUX, - RR_RELOC, RR_AMODE31, RR_IPLREPORT, RR_CERT_COMP_LIST, From ea84f14d2a6b1a4fde17d2713dbdfdef7b84da87 Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Wed, 17 Jan 2024 11:50:46 +0100 Subject: [PATCH 488/969] s390/nospec: Correct modules thunk offset calculation Fix offset calculation when branch target is more then 2Gb away. Signed-off-by: Vasily Gorbik Signed-off-by: Alexander Gordeev --- arch/s390/kernel/nospec-branch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/s390/kernel/nospec-branch.c b/arch/s390/kernel/nospec-branch.c index d1b16d83e49a..9b8c24ebb008 100644 --- a/arch/s390/kernel/nospec-branch.c +++ b/arch/s390/kernel/nospec-branch.c @@ -114,10 +114,10 @@ static void __init_or_module __nospec_revert(s32 *start, s32 *end) type = BRASL_EXPOLINE; /* brasl instruction */ else continue; - thunk = instr + (*(int *)(instr + 2)) * 2; + thunk = instr + (long)(*(int *)(instr + 2)) * 2; if (thunk[0] == 0xc6 && thunk[1] == 0x00) /* exrl %r0, */ - br = thunk + (*(int *)(thunk + 2)) * 2; + br = thunk + (long)(*(int *)(thunk + 2)) * 2; else continue; if (br[0] != 0x07 || (br[1] & 0xf0) != 0xf0) From ba05b39d54eef78043b5c8ee90545cb06a98ae6f Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Wed, 17 Jan 2024 11:50:49 +0100 Subject: [PATCH 489/969] s390/expoline: Make modules use kernel expolines Currently, kernel modules contain their own set of expoline thunks. In the case of EXPOLINE_EXTERN, this involves postlinking of precompiled expoline.o. expoline.o is also necessary for out-of-source tree module builds. Now that the kernel modules area is less than 4 GB away from kernel expoline thunks, make modules use kernel expolines. Also make EXPOLINE_EXTERN the default if the compiler supports it. This simplifies build and aligns with the approach adopted by other architectures. Signed-off-by: Vasily Gorbik Signed-off-by: Alexander Gordeev --- arch/s390/Kconfig | 2 +- arch/s390/Makefile | 6 ------ arch/s390/include/asm/asm-prototypes.h | 1 + arch/s390/include/asm/nospec-branch.h | 20 ++++++++++++++++++++ arch/s390/include/asm/nospec-insn.h | 13 +++++++------ arch/s390/lib/Makefile | 2 +- arch/s390/lib/{expoline => }/expoline.S | 0 arch/s390/lib/expoline/Makefile | 3 --- scripts/mod/modpost.c | 5 ----- 9 files changed, 30 insertions(+), 22 deletions(-) rename arch/s390/lib/{expoline => }/expoline.S (100%) delete mode 100644 arch/s390/lib/expoline/Makefile diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index df6b371ed214..a077ded1b9e6 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -555,7 +555,7 @@ config EXPOLINE If unsure, say N. config EXPOLINE_EXTERN - def_bool n + def_bool y if EXPOLINE depends on EXPOLINE depends on CC_IS_GCC && GCC_VERSION >= 110200 depends on $(success,$(srctree)/arch/s390/tools/gcc-thunk-extern.sh $(CC)) diff --git a/arch/s390/Makefile b/arch/s390/Makefile index 2dbb2d2f22f9..64821f54f1e0 100644 --- a/arch/s390/Makefile +++ b/arch/s390/Makefile @@ -88,7 +88,6 @@ endif ifdef CONFIG_EXPOLINE ifdef CONFIG_EXPOLINE_EXTERN - KBUILD_LDFLAGS_MODULE += arch/s390/lib/expoline/expoline.o CC_FLAGS_EXPOLINE := -mindirect-branch=thunk-extern CC_FLAGS_EXPOLINE += -mfunction-return=thunk-extern else @@ -167,11 +166,6 @@ vdso_prepare: prepare0 vdso-install-y += arch/s390/kernel/vdso64/vdso64.so.dbg vdso-install-$(CONFIG_COMPAT) += arch/s390/kernel/vdso32/vdso32.so.dbg -ifdef CONFIG_EXPOLINE_EXTERN -modules_prepare: expoline_prepare -expoline_prepare: scripts - $(Q)$(MAKE) $(build)=arch/s390/lib/expoline arch/s390/lib/expoline/expoline.o -endif endif # Don't use tabs in echo arguments diff --git a/arch/s390/include/asm/asm-prototypes.h b/arch/s390/include/asm/asm-prototypes.h index 56096ae26f29..f662eb4b9246 100644 --- a/arch/s390/include/asm/asm-prototypes.h +++ b/arch/s390/include/asm/asm-prototypes.h @@ -4,6 +4,7 @@ #include #include #include +#include #include __int128_t __ashlti3(__int128_t a, int b); diff --git a/arch/s390/include/asm/nospec-branch.h b/arch/s390/include/asm/nospec-branch.h index 82725cf783c7..b9c1f3cae842 100644 --- a/arch/s390/include/asm/nospec-branch.h +++ b/arch/s390/include/asm/nospec-branch.h @@ -17,6 +17,26 @@ static inline bool nospec_uses_trampoline(void) return __is_defined(CC_USING_EXPOLINE) && !nospec_disable; } +#ifdef CONFIG_EXPOLINE_EXTERN + +void __s390_indirect_jump_r1(void); +void __s390_indirect_jump_r2(void); +void __s390_indirect_jump_r3(void); +void __s390_indirect_jump_r4(void); +void __s390_indirect_jump_r5(void); +void __s390_indirect_jump_r6(void); +void __s390_indirect_jump_r7(void); +void __s390_indirect_jump_r8(void); +void __s390_indirect_jump_r9(void); +void __s390_indirect_jump_r10(void); +void __s390_indirect_jump_r11(void); +void __s390_indirect_jump_r12(void); +void __s390_indirect_jump_r13(void); +void __s390_indirect_jump_r14(void); +void __s390_indirect_jump_r15(void); + +#endif + #endif /* __ASSEMBLY__ */ #endif /* _ASM_S390_EXPOLINE_H */ diff --git a/arch/s390/include/asm/nospec-insn.h b/arch/s390/include/asm/nospec-insn.h index 7a946c42ad13..cb15dd25bf21 100644 --- a/arch/s390/include/asm/nospec-insn.h +++ b/arch/s390/include/asm/nospec-insn.h @@ -16,24 +16,25 @@ */ .macro __THUNK_PROLOG_NAME name #ifdef CONFIG_EXPOLINE_EXTERN - .pushsection .text,"ax",@progbits - __ALIGN + SYM_CODE_START(\name) #else .pushsection .text.\name,"axG",@progbits,\name,comdat -#endif .globl \name .hidden \name .type \name,@function \name: CFI_STARTPROC +#endif .endm .macro __THUNK_EPILOG_NAME name - CFI_ENDPROC #ifdef CONFIG_EXPOLINE_EXTERN - .size \name, .-\name -#endif + SYM_CODE_END(\name) + EXPORT_SYMBOL(\name) +#else + CFI_ENDPROC .popsection +#endif .endm .macro __THUNK_PROLOG_BR r1 diff --git a/arch/s390/lib/Makefile b/arch/s390/lib/Makefile index 90eac15ea62a..f43f897d3fc0 100644 --- a/arch/s390/lib/Makefile +++ b/arch/s390/lib/Makefile @@ -23,4 +23,4 @@ obj-$(CONFIG_S390_MODULES_SANITY_TEST_HELPERS) += test_modules_helpers.o lib-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o -obj-$(CONFIG_EXPOLINE_EXTERN) += expoline/ +obj-$(CONFIG_EXPOLINE_EXTERN) += expoline.o diff --git a/arch/s390/lib/expoline/expoline.S b/arch/s390/lib/expoline.S similarity index 100% rename from arch/s390/lib/expoline/expoline.S rename to arch/s390/lib/expoline.S diff --git a/arch/s390/lib/expoline/Makefile b/arch/s390/lib/expoline/Makefile deleted file mode 100644 index 854631d9cb03..000000000000 --- a/arch/s390/lib/expoline/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-y += expoline.o diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index 2f5b91da5afa..937294ff164f 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -601,11 +601,6 @@ static int ignore_undef_symbol(struct elf_info *info, const char *symname) strstarts(symname, "_savevr_") || strcmp(symname, ".TOC.") == 0) return 1; - - if (info->hdr->e_machine == EM_S390) - /* Expoline thunks are linked on all kernel modules during final link of .ko */ - if (strstarts(symname, "__s390_indirect_jump_r")) - return 1; /* Do not ignore this symbol */ return 0; } From fc110108b98305efa24bb8c355e90b5cc2a01a5f Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 18 Apr 2024 10:51:20 +0100 Subject: [PATCH 490/969] firmware: arm_scmi: Add support for multiple vendors custom protocols Add a mechanism to be able to tag vendor protocol modules at compile-time with a vendor/sub_vendor string and an implementation version and then to choose to load, at run-time, only those vendor protocol modules matching as close as possible the vendor/subvendor identification advertised by the SCMI platform server. In this way, any in-tree existent vendor protocol module can be build and shipped by default in a single kernel image, even when using the same clashing protocol identification numbers, since the SCMI core will take care at run-time to load only the ones pertinent to the running system. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20240418095121.3238820-2-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 169 ++++++++++++++++++++++---- drivers/firmware/arm_scmi/protocols.h | 15 +++ 2 files changed, 162 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 36e3eb50a8d4..36c4ff41dee1 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -33,6 +33,7 @@ #include #include #include +#include #include "common.h" #include "notify.h" @@ -44,8 +45,7 @@ static DEFINE_IDA(scmi_id); -static DEFINE_IDR(scmi_protocols); -static DEFINE_SPINLOCK(protocol_lock); +static DEFINE_XARRAY(scmi_protocols); /* List of all SCMI devices active in system */ static LIST_HEAD(scmi_list); @@ -194,11 +194,94 @@ struct scmi_info { #define bus_nb_to_scmi_info(nb) container_of(nb, struct scmi_info, bus_nb) #define req_nb_to_scmi_info(nb) container_of(nb, struct scmi_info, dev_req_nb) -static const struct scmi_protocol *scmi_protocol_get(int protocol_id) +static unsigned long +scmi_vendor_protocol_signature(unsigned int protocol_id, char *vendor_id, + char *sub_vendor_id, u32 impl_ver) { - const struct scmi_protocol *proto; + char *signature, *p; + unsigned long hash = 0; - proto = idr_find(&scmi_protocols, protocol_id); + /* vendor_id/sub_vendor_id guaranteed <= SCMI_SHORT_NAME_MAX_SIZE */ + signature = kasprintf(GFP_KERNEL, "%02X|%s|%s|0x%08X", protocol_id, + vendor_id ?: "", sub_vendor_id ?: "", impl_ver); + if (!signature) + return 0; + + p = signature; + while (*p) + hash = partial_name_hash(tolower(*p++), hash); + hash = end_name_hash(hash); + + kfree(signature); + + return hash; +} + +static unsigned long +scmi_protocol_key_calculate(int protocol_id, char *vendor_id, + char *sub_vendor_id, u32 impl_ver) +{ + if (protocol_id < SCMI_PROTOCOL_VENDOR_BASE) + return protocol_id; + else + return scmi_vendor_protocol_signature(protocol_id, vendor_id, + sub_vendor_id, impl_ver); +} + +static const struct scmi_protocol * +__scmi_vendor_protocol_lookup(int protocol_id, char *vendor_id, + char *sub_vendor_id, u32 impl_ver) +{ + unsigned long key; + struct scmi_protocol *proto = NULL; + + key = scmi_protocol_key_calculate(protocol_id, vendor_id, + sub_vendor_id, impl_ver); + if (key) + proto = xa_load(&scmi_protocols, key); + + return proto; +} + +static const struct scmi_protocol * +scmi_vendor_protocol_lookup(int protocol_id, char *vendor_id, + char *sub_vendor_id, u32 impl_ver) +{ + const struct scmi_protocol *proto = NULL; + + /* Searching for closest match ...*/ + proto = __scmi_vendor_protocol_lookup(protocol_id, vendor_id, + sub_vendor_id, impl_ver); + if (proto) + return proto; + + /* Any match just on vendor/sub_vendor ? */ + if (impl_ver) { + proto = __scmi_vendor_protocol_lookup(protocol_id, vendor_id, + sub_vendor_id, 0); + if (proto) + return proto; + } + + /* Any match just on the vendor ? */ + if (sub_vendor_id) + proto = __scmi_vendor_protocol_lookup(protocol_id, vendor_id, + NULL, 0); + return proto; +} + +static const struct scmi_protocol * +scmi_protocol_get(int protocol_id, struct scmi_revision_info *version) +{ + const struct scmi_protocol *proto = NULL; + + if (protocol_id < SCMI_PROTOCOL_VENDOR_BASE) + proto = xa_load(&scmi_protocols, protocol_id); + else + proto = scmi_vendor_protocol_lookup(protocol_id, + version->vendor_id, + version->sub_vendor_id, + version->impl_ver); if (!proto || !try_module_get(proto->owner)) { pr_warn("SCMI Protocol 0x%x not found!\n", protocol_id); return NULL; @@ -206,21 +289,46 @@ static const struct scmi_protocol *scmi_protocol_get(int protocol_id) pr_debug("Found SCMI Protocol 0x%x\n", protocol_id); + if (protocol_id >= SCMI_PROTOCOL_VENDOR_BASE) + pr_info("Loaded SCMI Vendor Protocol 0x%x - %s %s %X\n", + protocol_id, proto->vendor_id ?: "", + proto->sub_vendor_id ?: "", proto->impl_ver); + return proto; } -static void scmi_protocol_put(int protocol_id) +static void scmi_protocol_put(const struct scmi_protocol *proto) { - const struct scmi_protocol *proto; - - proto = idr_find(&scmi_protocols, protocol_id); if (proto) module_put(proto->owner); } +static int scmi_vendor_protocol_check(const struct scmi_protocol *proto) +{ + if (!proto->vendor_id) { + pr_err("missing vendor_id for protocol 0x%x\n", proto->id); + return -EINVAL; + } + + if (strlen(proto->vendor_id) >= SCMI_SHORT_NAME_MAX_SIZE) { + pr_err("malformed vendor_id for protocol 0x%x\n", proto->id); + return -EINVAL; + } + + if (proto->sub_vendor_id && + strlen(proto->sub_vendor_id) >= SCMI_SHORT_NAME_MAX_SIZE) { + pr_err("malformed sub_vendor_id for protocol 0x%x\n", + proto->id); + return -EINVAL; + } + + return 0; +} + int scmi_protocol_register(const struct scmi_protocol *proto) { int ret; + unsigned long key; if (!proto) { pr_err("invalid protocol\n"); @@ -232,12 +340,23 @@ int scmi_protocol_register(const struct scmi_protocol *proto) return -EINVAL; } - spin_lock(&protocol_lock); - ret = idr_alloc(&scmi_protocols, (void *)proto, - proto->id, proto->id + 1, GFP_ATOMIC); - spin_unlock(&protocol_lock); - if (ret != proto->id) { - pr_err("unable to allocate SCMI idr slot for 0x%x - err %d\n", + if (proto->id >= SCMI_PROTOCOL_VENDOR_BASE && + scmi_vendor_protocol_check(proto)) + return -EINVAL; + + /* + * Calculate a protocol key to register this protocol with the core; + * key value 0 is considered invalid. + */ + key = scmi_protocol_key_calculate(proto->id, proto->vendor_id, + proto->sub_vendor_id, + proto->impl_ver); + if (!key) + return -EINVAL; + + ret = xa_insert(&scmi_protocols, key, (void *)proto, GFP_KERNEL); + if (ret) { + pr_err("unable to allocate SCMI protocol slot for 0x%x - err %d\n", proto->id, ret); return ret; } @@ -250,9 +369,15 @@ EXPORT_SYMBOL_GPL(scmi_protocol_register); void scmi_protocol_unregister(const struct scmi_protocol *proto) { - spin_lock(&protocol_lock); - idr_remove(&scmi_protocols, proto->id); - spin_unlock(&protocol_lock); + unsigned long key; + + key = scmi_protocol_key_calculate(proto->id, proto->vendor_id, + proto->sub_vendor_id, + proto->impl_ver); + if (!key) + return; + + xa_erase(&scmi_protocols, key); pr_debug("Unregistered SCMI Protocol 0x%x\n", proto->id); } @@ -1940,7 +2065,7 @@ scmi_alloc_init_protocol_instance(struct scmi_info *info, /* Protocol specific devres group */ gid = devres_open_group(handle->dev, NULL, GFP_KERNEL); if (!gid) { - scmi_protocol_put(proto->id); + scmi_protocol_put(proto); goto out; } @@ -2004,7 +2129,7 @@ scmi_alloc_init_protocol_instance(struct scmi_info *info, clean: /* Take care to put the protocol module's owner before releasing all */ - scmi_protocol_put(proto->id); + scmi_protocol_put(proto); devres_release_group(handle->dev, gid); out: return ERR_PTR(ret); @@ -2038,7 +2163,7 @@ scmi_get_protocol_instance(const struct scmi_handle *handle, u8 protocol_id) const struct scmi_protocol *proto; /* Fails if protocol not registered on bus */ - proto = scmi_protocol_get(protocol_id); + proto = scmi_protocol_get(protocol_id, &info->version); if (proto) pi = scmi_alloc_init_protocol_instance(info, proto); else @@ -2093,7 +2218,7 @@ void scmi_protocol_release(const struct scmi_handle *handle, u8 protocol_id) idr_remove(&info->protocols, protocol_id); - scmi_protocol_put(protocol_id); + scmi_protocol_put(pi->proto); devres_release_group(handle->dev, gid); dev_dbg(handle->dev, "De-Initialized protocol: 0x%X\n", diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h index 317d3fb32676..e17dbcfbf299 100644 --- a/drivers/firmware/arm_scmi/protocols.h +++ b/drivers/firmware/arm_scmi/protocols.h @@ -29,6 +29,8 @@ #define PROTOCOL_REV_MAJOR(x) ((u16)(FIELD_GET(PROTOCOL_REV_MAJOR_MASK, (x)))) #define PROTOCOL_REV_MINOR(x) ((u16)(FIELD_GET(PROTOCOL_REV_MINOR_MASK, (x)))) +#define SCMI_PROTOCOL_VENDOR_BASE 0x80 + enum scmi_common_cmd { PROTOCOL_VERSION = 0x0, PROTOCOL_ATTRIBUTES = 0x1, @@ -323,6 +325,16 @@ typedef int (*scmi_prot_init_ph_fn_t)(const struct scmi_protocol_handle *); * protocol by the agent. Each protocol implementation * in the agent is supposed to downgrade to match the * protocol version supported by the platform. + * @vendor_id: A firmware vendor string for vendor protocols matching. + * Ignored when @id identifies a standard protocol, cannot be NULL + * otherwise. + * @sub_vendor_id: A firmware sub_vendor string for vendor protocols matching. + * Ignored if NULL or when @id identifies a standard protocol. + * @impl_ver: A firmware implementation version for vendor protocols matching. + * Ignored if zero or if @id identifies a standard protocol. + * + * Note that vendor protocols matching at load time is performed by attempting + * the closest match first against the tuple (vendor, sub_vendor, impl_ver) */ struct scmi_protocol { const u8 id; @@ -332,6 +344,9 @@ struct scmi_protocol { const void *ops; const struct scmi_protocol_events *events; unsigned int supported_version; + char *vendor_id; + char *sub_vendor_id; + u32 impl_ver; }; #define DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(name, proto) \ From 0370fb127ce3432a4081fe1415a947308cb827f1 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 18 Apr 2024 11:29:32 +0100 Subject: [PATCH 491/969] firmware: arm_ffa: Fix kernel warning about incorrect SRI/NPI If the firmware returns incorrect SRI/NRI number, we fail to set it up in the kernel which is absolutely fine. However, we don't reset the stashed value of sched_recv or notif_pend IRQs. When we call ffa_notifications_cleanup() in case of failures to setup the notifications, we end up calling free_percpu_irq() from ffa_uninit_pcpu_irq() which results in the following warning: | genirq: Flags mismatch irq 6. 00004401 (ARM-FFA-NPI) vs. 00004400 (IPI) | ARM FF-A: Error registering percpu NPI nIRQ 6 : -16 | ARM FF-A: Notification setup failed -16, not enabled | ------------[ cut here ]------------ | Trying to free already-free IRQ 6 | WARNING: CPU: 2 PID: 1 at kernel/irq/manage.c:2476 __free_percpu_irq+0x6c/0x138 | Modules linked in: | CPU: 2 PID: 1 Comm: swapper/0 Not tainted 6.9.0-rc3 #211 | Hardware name: FVP Base RevC (DT) | pstate: 614000c9 (nZCv daIF +PAN -UAO -TCO +DIT -SSBS BTYPE=--) | pc : __free_percpu_irq+0x6c/0x138 | lr : __free_percpu_irq+0x6c/0x138 | Call trace: | __free_percpu_irq+0x6c/0x138 | free_percpu_irq+0x48/0x84 | ffa_notifications_cleanup+0x78/0x164 | ffa_notifications_setup+0x368/0x3c0 | ffa_init+0x2b4/0x36c | do_one_initcall+0xe0/0x258 | do_initcall_level+0x8c/0xac | do_initcalls+0x54/0x94 | do_basic_setup+0x1c/0x28 | kernel_init_freeable+0x108/0x174 | kernel_init+0x20/0x1a4 | ret_from_fork+0x10/0x20 Fix the same by resetting the stashed copy of IRQ values to 0 in case of any failure to set them up properly. Cc: Jens Wiklander Link: https://lore.kernel.org/r/20240418102932.3093576-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index 018eddf40ca2..b64e8ee64bc2 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -1435,6 +1435,7 @@ static int ffa_init_pcpu_irq(void) if (ret) { pr_err("Error registering percpu SRI nIRQ %d : %d\n", drv_info->sched_recv_irq, ret); + drv_info->sched_recv_irq = 0; return ret; } } @@ -1446,6 +1447,7 @@ static int ffa_init_pcpu_irq(void) if (ret) { pr_err("Error registering percpu NPI nIRQ %d : %d\n", drv_info->notif_pend_irq, ret); + drv_info->notif_pend_irq = 0; return ret; } } From 90a7592da14951bd21f74a53246ba30955a648aa Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 11 Apr 2024 18:14:40 +0200 Subject: [PATCH 492/969] mm/userfaultfd: Do not place zeropages when zeropages are disallowed s390x must disable shared zeropages for processes running VMs, because the VMs could end up making use of "storage keys" or protected virtualization, which are incompatible with shared zeropages. Yet, with userfaultfd it is possible to insert shared zeropages into such processes. Let's fallback to simply allocating a fresh zeroed anonymous folio and insert that instead. mm_forbids_zeropage() was introduced in commit 593befa6ab74 ("mm: introduce mm_forbids_zeropage function"), briefly before userfaultfd went upstream. Note that we don't want to fail the UFFDIO_ZEROPAGE request like we do for hugetlb, it would be rather unexpected. Further, we also cannot really indicated "not supported" to user space ahead of time: it could be that the MM disallows zeropages after userfaultfd was already registered. [ agordeev: Fixed checkpatch complaints ] Fixes: c1a4de99fada ("userfaultfd: mcopy_atomic|mfill_zeropage: UFFDIO_COPY|UFFDIO_ZEROPAGE preparation") Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/20240411161441.910170-2-david@redhat.com Signed-off-by: David Hildenbrand Signed-off-by: Alexander Gordeev --- mm/userfaultfd.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c index 3c3539c573e7..829f7b1089fc 100644 --- a/mm/userfaultfd.c +++ b/mm/userfaultfd.c @@ -316,6 +316,38 @@ out_release: goto out; } +static int mfill_atomic_pte_zeroed_folio(pmd_t *dst_pmd, + struct vm_area_struct *dst_vma, + unsigned long dst_addr) +{ + struct folio *folio; + int ret = -ENOMEM; + + folio = vma_alloc_zeroed_movable_folio(dst_vma, dst_addr); + if (!folio) + return ret; + + if (mem_cgroup_charge(folio, dst_vma->vm_mm, GFP_KERNEL)) + goto out_put; + + /* + * The memory barrier inside __folio_mark_uptodate makes sure that + * zeroing out the folio become visible before mapping the page + * using set_pte_at(). See do_anonymous_page(). + */ + __folio_mark_uptodate(folio); + + ret = mfill_atomic_install_pte(dst_pmd, dst_vma, dst_addr, + &folio->page, true, 0); + if (ret) + goto out_put; + + return 0; +out_put: + folio_put(folio); + return ret; +} + static int mfill_atomic_pte_zeropage(pmd_t *dst_pmd, struct vm_area_struct *dst_vma, unsigned long dst_addr) @@ -324,6 +356,9 @@ static int mfill_atomic_pte_zeropage(pmd_t *dst_pmd, spinlock_t *ptl; int ret; + if (mm_forbids_zeropage(dst_vma->vm_mm)) + return mfill_atomic_pte_zeroed_folio(dst_pmd, dst_vma, dst_addr); + _dst_pte = pte_mkspecial(pfn_pte(my_zero_pfn(dst_addr), dst_vma->vm_page_prot)); ret = -EAGAIN; From 06201e00ee3e4beacac48aab2b83eff64ebf0bc0 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 11 Apr 2024 18:14:41 +0200 Subject: [PATCH 493/969] s390/mm: Re-enable the shared zeropage for !PV and !skeys KVM guests commit fa41ba0d08de ("s390/mm: avoid empty zero pages for KVM guests to avoid postcopy hangs") introduced an undesired side effect when combined with memory ballooning and VM migration: memory part of the inflated memory balloon will consume memory. Assuming we have a 100GiB VM and inflated the balloon to 40GiB. Our VM will consume ~60GiB of memory. If we now trigger a VM migration, hypervisors like QEMU will read all VM memory. As s390x does not support the shared zeropage, we'll end up allocating for all previously-inflated memory part of the memory balloon: 50 GiB. So we might easily (unexpectedly) crash the VM on the migration source. Even worse, hypervisors like QEMU optimize for zeropage migration to not consume memory on the migration destination: when migrating a "page full of zeroes", on the migration destination they check whether the target memory is already zero (by reading the destination memory) and avoid writing to the memory to not allocate memory: however, s390x will also allocate memory here, implying that also on the migration destination, we will end up allocating all previously-inflated memory part of the memory balloon. This is especially bad if actual memory overcommit was not desired, when memory ballooning is used for dynamic VM memory resizing, setting aside some memory during boot that can be added later on demand. Alternatives like virtio-mem that would avoid this issue are not yet available on s390x. There could be ways to optimize some cases in user space: before reading memory in an anonymous private mapping on the migration source, check via /proc/self/pagemap if anything is already populated. Similarly check on the migration destination before reading. While that would avoid populating tables full of shared zeropages on all architectures, it's harder to get right and performant, and requires user space changes. Further, with posctopy live migration we must place a page, so there, "avoid touching memory to avoid allocating memory" is not really possible. (Note that a previously we would have falsely inserted shared zeropages into processes using UFFDIO_ZEROPAGE where mm_forbids_zeropage() would have actually forbidden it) PV is currently incompatible with memory ballooning, and in the common case, KVM guests don't make use of storage keys. Instead of zapping zeropages when enabling storage keys / PV, that turned out to be problematic in the past, let's do exactly the same we do with KSM pages: trigger unsharing faults to replace the shared zeropages by proper anonymous folios. What about added latency when enabling storage kes? Having a lot of zeropages in applicable environments (PV, legacy guests, unittests) is unexpected. Further, KSM could today already unshare the zeropages and unmerging KSM pages when enabling storage kets would unshare the KSM-placed zeropages in the same way, resulting in the same latency. [ agordeev: Fixed sparse and checkpatch complaints and error handling ] Reviewed-by: Christian Borntraeger Tested-by: Christian Borntraeger Fixes: fa41ba0d08de ("s390/mm: avoid empty zero pages for KVM guests to avoid postcopy hangs") Signed-off-by: David Hildenbrand Link: https://lore.kernel.org/r/20240411161441.910170-3-david@redhat.com Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/gmap.h | 2 +- arch/s390/include/asm/mmu.h | 5 + arch/s390/include/asm/mmu_context.h | 1 + arch/s390/include/asm/pgtable.h | 16 ++- arch/s390/kvm/kvm-s390.c | 4 +- arch/s390/mm/gmap.c | 165 +++++++++++++++++++++------- 6 files changed, 146 insertions(+), 47 deletions(-) diff --git a/arch/s390/include/asm/gmap.h b/arch/s390/include/asm/gmap.h index 5cc46e0dde62..9725586f4259 100644 --- a/arch/s390/include/asm/gmap.h +++ b/arch/s390/include/asm/gmap.h @@ -146,7 +146,7 @@ int gmap_mprotect_notify(struct gmap *, unsigned long start, void gmap_sync_dirty_log_pmd(struct gmap *gmap, unsigned long dirty_bitmap[4], unsigned long gaddr, unsigned long vmaddr); -int gmap_mark_unmergeable(void); +int s390_disable_cow_sharing(void); void s390_unlist_old_asce(struct gmap *gmap); int s390_replace_asce(struct gmap *gmap); void s390_uv_destroy_pfns(unsigned long count, unsigned long *pfns); diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h index bb1b4bef1878..4c2dc7abc285 100644 --- a/arch/s390/include/asm/mmu.h +++ b/arch/s390/include/asm/mmu.h @@ -32,6 +32,11 @@ typedef struct { unsigned int uses_skeys:1; /* The mmu context uses CMM. */ unsigned int uses_cmm:1; + /* + * The mmu context allows COW-sharing of memory pages (KSM, zeropage). + * Note that COW-sharing during fork() is currently always allowed. + */ + unsigned int allow_cow_sharing:1; /* The gmaps associated with this context are allowed to use huge pages. */ unsigned int allow_gmap_hpage_1m:1; } mm_context_t; diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index 929af18b0908..a7789a9f6218 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -35,6 +35,7 @@ static inline int init_new_context(struct task_struct *tsk, mm->context.has_pgste = 0; mm->context.uses_skeys = 0; mm->context.uses_cmm = 0; + mm->context.allow_cow_sharing = 1; mm->context.allow_gmap_hpage_1m = 0; #endif switch (mm->context.asce_limit) { diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h index 60950e7a25f5..259c2439c251 100644 --- a/arch/s390/include/asm/pgtable.h +++ b/arch/s390/include/asm/pgtable.h @@ -566,10 +566,20 @@ static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot) } /* - * In the case that a guest uses storage keys - * faults should no longer be backed by zero pages + * As soon as the guest uses storage keys or enables PV, we deduplicate all + * mapped shared zeropages and prevent new shared zeropages from getting + * mapped. */ -#define mm_forbids_zeropage mm_has_pgste +#define mm_forbids_zeropage mm_forbids_zeropage +static inline int mm_forbids_zeropage(struct mm_struct *mm) +{ +#ifdef CONFIG_PGSTE + if (!mm->context.allow_cow_sharing) + return 1; +#endif + return 0; +} + static inline int mm_uses_skeys(struct mm_struct *mm) { #ifdef CONFIG_PGSTE diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 5147b943a864..db3392f0be21 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -2631,9 +2631,7 @@ static int kvm_s390_handle_pv(struct kvm *kvm, struct kvm_pv_cmd *cmd) if (r) break; - mmap_write_lock(current->mm); - r = gmap_mark_unmergeable(); - mmap_write_unlock(current->mm); + r = s390_disable_cow_sharing(); if (r) break; diff --git a/arch/s390/mm/gmap.c b/arch/s390/mm/gmap.c index 094b43b121cd..f2988bbcebbe 100644 --- a/arch/s390/mm/gmap.c +++ b/arch/s390/mm/gmap.c @@ -2549,41 +2549,6 @@ static inline void thp_split_mm(struct mm_struct *mm) } #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ -/* - * Remove all empty zero pages from the mapping for lazy refaulting - * - This must be called after mm->context.has_pgste is set, to avoid - * future creation of zero pages - * - This must be called after THP was disabled. - * - * mm contracts with s390, that even if mm were to remove a page table, - * racing with the loop below and so causing pte_offset_map_lock() to fail, - * it will never insert a page table containing empty zero pages once - * mm_forbids_zeropage(mm) i.e. mm->context.has_pgste is set. - */ -static int __zap_zero_pages(pmd_t *pmd, unsigned long start, - unsigned long end, struct mm_walk *walk) -{ - unsigned long addr; - - for (addr = start; addr != end; addr += PAGE_SIZE) { - pte_t *ptep; - spinlock_t *ptl; - - ptep = pte_offset_map_lock(walk->mm, pmd, addr, &ptl); - if (!ptep) - break; - if (is_zero_pfn(pte_pfn(*ptep))) - ptep_xchg_direct(walk->mm, addr, ptep, __pte(_PAGE_INVALID)); - pte_unmap_unlock(ptep, ptl); - } - return 0; -} - -static const struct mm_walk_ops zap_zero_walk_ops = { - .pmd_entry = __zap_zero_pages, - .walk_lock = PGWALK_WRLOCK, -}; - /* * switch on pgstes for its userspace process (for kvm) */ @@ -2601,22 +2566,142 @@ int s390_enable_sie(void) mm->context.has_pgste = 1; /* split thp mappings and disable thp for future mappings */ thp_split_mm(mm); - walk_page_range(mm, 0, TASK_SIZE, &zap_zero_walk_ops, NULL); mmap_write_unlock(mm); return 0; } EXPORT_SYMBOL_GPL(s390_enable_sie); -int gmap_mark_unmergeable(void) +static int find_zeropage_pte_entry(pte_t *pte, unsigned long addr, + unsigned long end, struct mm_walk *walk) { + unsigned long *found_addr = walk->private; + + /* Return 1 of the page is a zeropage. */ + if (is_zero_pfn(pte_pfn(*pte))) { + /* + * Shared zeropage in e.g., a FS DAX mapping? We cannot do the + * right thing and likely don't care: FAULT_FLAG_UNSHARE + * currently only works in COW mappings, which is also where + * mm_forbids_zeropage() is checked. + */ + if (!is_cow_mapping(walk->vma->vm_flags)) + return -EFAULT; + + *found_addr = addr; + return 1; + } + return 0; +} + +static const struct mm_walk_ops find_zeropage_ops = { + .pte_entry = find_zeropage_pte_entry, + .walk_lock = PGWALK_WRLOCK, +}; + +/* + * Unshare all shared zeropages, replacing them by anonymous pages. Note that + * we cannot simply zap all shared zeropages, because this could later + * trigger unexpected userfaultfd missing events. + * + * This must be called after mm->context.allow_cow_sharing was + * set to 0, to avoid future mappings of shared zeropages. + * + * mm contracts with s390, that even if mm were to remove a page table, + * and racing with walk_page_range_vma() calling pte_offset_map_lock() + * would fail, it will never insert a page table containing empty zero + * pages once mm_forbids_zeropage(mm) i.e. + * mm->context.allow_cow_sharing is set to 0. + */ +static int __s390_unshare_zeropages(struct mm_struct *mm) +{ + struct vm_area_struct *vma; + VMA_ITERATOR(vmi, mm, 0); + unsigned long addr; + vm_fault_t fault; + int rc; + + for_each_vma(vmi, vma) { + /* + * We could only look at COW mappings, but it's more future + * proof to catch unexpected zeropages in other mappings and + * fail. + */ + if ((vma->vm_flags & VM_PFNMAP) || is_vm_hugetlb_page(vma)) + continue; + addr = vma->vm_start; + +retry: + rc = walk_page_range_vma(vma, addr, vma->vm_end, + &find_zeropage_ops, &addr); + if (rc < 0) + return rc; + else if (!rc) + continue; + + /* addr was updated by find_zeropage_pte_entry() */ + fault = handle_mm_fault(vma, addr, + FAULT_FLAG_UNSHARE | FAULT_FLAG_REMOTE, + NULL); + if (fault & VM_FAULT_OOM) + return -ENOMEM; + /* + * See break_ksm(): even after handle_mm_fault() returned 0, we + * must start the lookup from the current address, because + * handle_mm_fault() may back out if there's any difficulty. + * + * VM_FAULT_SIGBUS and VM_FAULT_SIGSEGV are unexpected but + * maybe they could trigger in the future on concurrent + * truncation. In that case, the shared zeropage would be gone + * and we can simply retry and make progress. + */ + cond_resched(); + goto retry; + } + + return 0; +} + +static int __s390_disable_cow_sharing(struct mm_struct *mm) +{ + int rc; + + if (!mm->context.allow_cow_sharing) + return 0; + + mm->context.allow_cow_sharing = 0; + + /* Replace all shared zeropages by anonymous pages. */ + rc = __s390_unshare_zeropages(mm); /* * Make sure to disable KSM (if enabled for the whole process or * individual VMAs). Note that nothing currently hinders user space * from re-enabling it. */ - return ksm_disable(current->mm); + if (!rc) + rc = ksm_disable(mm); + if (rc) + mm->context.allow_cow_sharing = 1; + return rc; } -EXPORT_SYMBOL_GPL(gmap_mark_unmergeable); + +/* + * Disable most COW-sharing of memory pages for the whole process: + * (1) Disable KSM and unmerge/unshare any KSM pages. + * (2) Disallow shared zeropages and unshare any zerpages that are mapped. + * + * Not that we currently don't bother with COW-shared pages that are shared + * with parent/child processes due to fork(). + */ +int s390_disable_cow_sharing(void) +{ + int rc; + + mmap_write_lock(current->mm); + rc = __s390_disable_cow_sharing(current->mm); + mmap_write_unlock(current->mm); + return rc; +} +EXPORT_SYMBOL_GPL(s390_disable_cow_sharing); /* * Enable storage key handling from now on and initialize the storage @@ -2685,7 +2770,7 @@ int s390_enable_skey(void) goto out_up; mm->context.uses_skeys = 1; - rc = gmap_mark_unmergeable(); + rc = __s390_disable_cow_sharing(mm); if (rc) { mm->context.uses_skeys = 0; goto out_up; From 3c258bf6bf29d8c9f9b358c64f6e9f4510c91ff9 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 17 Apr 2024 10:09:21 +0100 Subject: [PATCH 494/969] firmware: arm_ffa: Stash the partition properties for query purposes The properies obtained from the partition information descriptor as part of initial partitions discovery is useful as it contain info if the partition - Runs in AArch64 or AArch32 execution state - Can send and/or receive direct requests - Can send and receive indirect message - Does support receipt of notifications. These can be used for querying before attempting to do any of the above operations. Link: https://lore.kernel.org/r/20240417090921.2866447-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 2 ++ include/linux/arm_ffa.h | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index b64e8ee64bc2..99a23dd3d189 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -1228,6 +1228,8 @@ static int ffa_setup_partitions(void) continue; } + ffa_dev->properties = tpbuf->properties; + if (drv_info->version > FFA_VERSION_1_0 && !(tpbuf->properties & FFA_PARTITION_AARCH64_EXEC)) ffa_mode_32bit_set(ffa_dev); diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h index c906f666ff5d..94a49612ecec 100644 --- a/include/linux/arm_ffa.h +++ b/include/linux/arm_ffa.h @@ -126,6 +126,7 @@ /* FFA Bus/Device/Driver related */ struct ffa_device { u32 id; + u32 properties; int vm_id; bool mode_32bit; uuid_t uuid; @@ -221,12 +222,29 @@ struct ffa_partition_info { #define FFA_PARTITION_DIRECT_SEND BIT(1) /* partition can send and receive indirect messages. */ #define FFA_PARTITION_INDIRECT_MSG BIT(2) +/* partition can receive notifications */ +#define FFA_PARTITION_NOTIFICATION_RECV BIT(3) /* partition runs in the AArch64 execution state. */ #define FFA_PARTITION_AARCH64_EXEC BIT(8) u32 properties; u32 uuid[4]; }; +static inline +bool ffa_partition_check_property(struct ffa_device *dev, u32 property) +{ + return dev->properties & property; +} + +#define ffa_partition_supports_notify_recv(dev) \ + ffa_partition_check_property(dev, FFA_PARTITION_NOTIFICATION_RECV) + +#define ffa_partition_supports_indirect_msg(dev) \ + ffa_partition_check_property(dev, FFA_PARTITION_INDIRECT_MSG) + +#define ffa_partition_supports_direct_recv(dev) \ + ffa_partition_check_property(dev, FFA_PARTITION_DIRECT_RECV) + /* For use with FFA_MSG_SEND_DIRECT_{REQ,RESP} which pass data via registers */ struct ffa_send_direct_data { unsigned long data0; /* w3/x3 */ From 02c19d84c7c5026624d181b8e4cdc8488134d013 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 17 Apr 2024 10:09:31 +0100 Subject: [PATCH 495/969] firmware: arm_ffa: Add support for FFA_MSG_SEND2 The FFA_MSG_SEND2 can be used to transmit a partition message from the Tx buffer of the sender(the driver in this case) endpoint to the Rx buffer of the receiver endpoint. An invocation of the FFA_MSG_SEND2 transfers the ownership of the Tx buffer to the receiver endpoint(or any intermediate consumer). Completion of an FFA_MSG_SEND2 invocation transfers the ownership of the buffer back to the sender endpoint. The framework defines the FFA_MSG_SEND2 interface to transmit a partition message from the Tx buffer of the sender to the Rx buffer of a receiver and inform the scheduler that the receiver must be run. Link: https://lore.kernel.org/r/20240417090931.2866487-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 38 +++++++++++++++++++++++++++++++ include/linux/arm_ffa.h | 9 ++++++++ 2 files changed, 47 insertions(+) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index 99a23dd3d189..26968edac5b2 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -345,6 +345,38 @@ static int ffa_msg_send_direct_req(u16 src_id, u16 dst_id, bool mode_32bit, return -EINVAL; } +static int ffa_msg_send2(u16 src_id, u16 dst_id, void *buf, size_t sz) +{ + u32 src_dst_ids = PACK_TARGET_INFO(src_id, dst_id); + struct ffa_indirect_msg_hdr *msg; + ffa_value_t ret; + int retval = 0; + + if (sz > (RXTX_BUFFER_SIZE - sizeof(*msg))) + return -ERANGE; + + mutex_lock(&drv_info->tx_lock); + + msg = drv_info->tx_buffer; + msg->flags = 0; + msg->res0 = 0; + msg->offset = sizeof(*msg); + msg->send_recv_id = src_dst_ids; + msg->size = sz; + memcpy(msg + msg->offset, buf, sz); + + /* flags = 0, sender VMID = 0 works for both physical/virtual NS */ + invoke_ffa_fn((ffa_value_t){ + .a0 = FFA_MSG_SEND2, .a1 = 0, .a2 = 0 + }, &ret); + + if (ret.a0 == FFA_ERROR) + retval = ffa_to_linux_errno((int)ret.a2); + + mutex_unlock(&drv_info->tx_lock); + return retval; +} + static int ffa_mem_first_frag(u32 func_id, phys_addr_t buf, u32 buf_sz, u32 frag_len, u32 len, u64 *handle) { @@ -871,6 +903,11 @@ static int ffa_sync_send_receive(struct ffa_device *dev, dev->mode_32bit, data); } +static int ffa_indirect_msg_send(struct ffa_device *dev, void *buf, size_t sz) +{ + return ffa_msg_send2(drv_info->vm_id, dev->vm_id, buf, sz); +} + static int ffa_memory_share(struct ffa_mem_ops_args *args) { if (drv_info->mem_ops_native) @@ -1146,6 +1183,7 @@ static const struct ffa_info_ops ffa_drv_info_ops = { static const struct ffa_msg_ops ffa_drv_msg_ops = { .mode_32bit_set = ffa_mode_32bit_set, .sync_send_receive = ffa_sync_send_receive, + .indirect_send = ffa_indirect_msg_send, }; static const struct ffa_mem_ops ffa_drv_mem_ops = { diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h index 94a49612ecec..c82d56768101 100644 --- a/include/linux/arm_ffa.h +++ b/include/linux/arm_ffa.h @@ -254,6 +254,14 @@ struct ffa_send_direct_data { unsigned long data4; /* w7/x7 */ }; +struct ffa_indirect_msg_hdr { + u32 flags; + u32 res0; + u32 offset; + u32 send_recv_id; + u32 size; +}; + struct ffa_mem_region_addr_range { /* The base IPA of the constituent memory region, aligned to 4 kiB */ u64 address; @@ -414,6 +422,7 @@ struct ffa_msg_ops { void (*mode_32bit_set)(struct ffa_device *dev); int (*sync_send_receive)(struct ffa_device *dev, struct ffa_send_direct_data *data); + int (*indirect_send)(struct ffa_device *dev, void *buf, size_t sz); }; struct ffa_mem_ops { From 352b1d1889835d27c73ae288d6138cb95db64440 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:44 +0200 Subject: [PATCH 496/969] arm64: dts: hisilicon: hip07: move non-MMIO node out of soc Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: hip07.dtsi:1486.20-1493.5: Warning (unit_address_vs_reg): /soc/ethernet@4: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 72 ++++++++++++------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 81d907ef43ed..9d1e86553ea8 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1013,6 +1013,42 @@ }; }; + eth0: ethernet-0 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <4>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth1: ethernet-1 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <5>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth2: ethernet-2 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <0>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + + eth3: ethernet-3 { + compatible = "hisilicon,hns-nic-v2"; + ae-handle = <&dsaf0>; + port-idx-in-ae = <1>; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + dma-coherent; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -1483,42 +1519,6 @@ }; }; - eth0: ethernet@4 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <4>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth1: ethernet@5 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <5>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth2: ethernet@0 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <0>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - - eth3: ethernet@1 { - compatible = "hisilicon,hns-nic-v2"; - ae-handle = <&dsaf0>; - port-idx-in-ae = <1>; - local-mac-address = [00 00 00 00 00 00]; - status = "disabled"; - dma-coherent; - }; - infiniband@c4000000 { compatible = "hisilicon,hns-roce-v1"; reg = <0x0 0xc4000000 0x0 0x100000>; From 14431365eed8c760b90d91aaebe8f1d0001cd71f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:45 +0200 Subject: [PATCH 497/969] arm64: dts: hisilicon: hip07: correct unit addresses Correct several nodes' unit addresses to fix dtc W=1 warnings: arch/arm64/boot/dts/hisilicon/hip07.dtsi:1382.23-1520.5: Warning (simple_bus_reg): /soc/dsa@c7000000: simple-bus unit address format error, expected "c5000000" arch/arm64/boot/dts/hisilicon/hip07.dtsi:1727.29-1747.5: Warning (simple_bus_reg): /soc/pcie@a00a0000: simple-bus unit address format error, expected "af800000" arch/arm64/boot/dts/hisilicon/hip07.dtsi:1748.29-1788.5: Warning (simple_bus_reg): /soc/crypto@d2000000: simple-bus unit address format error, expected "d0000000" Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 9d1e86553ea8..00a6bfa7478c 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1379,7 +1379,7 @@ }; }; - dsaf0: dsa@c7000000 { + dsaf0: dsa@c5000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; @@ -1724,7 +1724,7 @@ status = "disabled"; }; - p0_pcie2_a: pcie@a00a0000 { + p0_pcie2_a: pcie@af800000 { compatible = "hisilicon,hip07-pcie-ecam"; reg = <0 0xaf800000 0 0x800000>, <0 0xa00a0000 0 0x10000>; @@ -1745,7 +1745,7 @@ 0x0 0 0 4 &mbigen_pcie2_a 671 4>; status = "disabled"; }; - p0_sec_a: crypto@d2000000 { + p0_sec_a: crypto@d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x0 0xd0000000 0x0 0x10000>, <0x0 0xd2000000 0x0 0x10000>, @@ -1786,7 +1786,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p0_sec_b: crypto@8,d2000000 { + p0_sec_b: crypto@8d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x8 0xd0000000 0x0 0x10000>, <0x8 0xd2000000 0x0 0x10000>, @@ -1827,7 +1827,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_a: crypto@400,d2000000 { + p1_sec_a: crypto@400d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x400 0xd0000000 0x0 0x10000>, <0x400 0xd2000000 0x0 0x10000>, @@ -1868,7 +1868,7 @@ <605 1>, <606 4>, <607 1>, <608 4>; }; - p1_sec_b: crypto@408,d2000000 { + p1_sec_b: crypto@408d0000000 { compatible = "hisilicon,hip07-sec"; reg = <0x408 0xd0000000 0x0 0x10000>, <0x408 0xd2000000 0x0 0x10000>, From 55687ef52db14bc5f072340cb6adb4288817259c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:46 +0200 Subject: [PATCH 498/969] arm64: dts: hisilicon: hi6220-hikey: add missing port@0 reg adv7533 ports should have "reg" propeties, as reported by dtc W=1 warnings: hi6220-hikey.dts:516.11-520.6: Warning (unit_address_vs_reg): /soc/i2c@f7102000/adv7533@39/ports/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index f0672ec65b26..a2aa17e4dfdf 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -514,6 +514,7 @@ #address-cells = <1>; #size-cells = <0>; port@0 { + reg = <0>; adv7533_in: endpoint { remote-endpoint = <&dsi_out0>; }; From 8fafd368fd34a9cf97af9cd73a6346565dd5fe7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:47 +0200 Subject: [PATCH 499/969] arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulators Fixed regulators are not part of any MMIO bus, so they should not have unit addresses. This fixes dtc W=1 warnings: hi6220-hikey.dts:85.26-92.4: Warning (unit_address_vs_reg): /regulator@0: node has a unit name, but no reg or ranges property hi6220-hikey.dts:94.27-102.4: Warning (unit_address_vs_reg): /regulator@1: node has a unit name, but no reg or ranges property hi6220-hikey.dts:104.26-113.4: Warning (unit_address_vs_reg): /regulator@2: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index a2aa17e4dfdf..2d304efe081d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -82,7 +82,7 @@ }; }; - reg_sys_5v: regulator@0 { + reg_sys_5v: regulator-0 { compatible = "regulator-fixed"; regulator-name = "SYS_5V"; regulator-min-microvolt = <5000000>; @@ -91,7 +91,7 @@ regulator-always-on; }; - reg_vdd_3v3: regulator@1 { + reg_vdd_3v3: regulator-1 { compatible = "regulator-fixed"; regulator-name = "VDD_3V3"; regulator-min-microvolt = <3300000>; @@ -101,7 +101,7 @@ vin-supply = <®_sys_5v>; }; - reg_5v_hub: regulator@2 { + reg_5v_hub: regulator-2 { compatible = "regulator-fixed"; regulator-name = "5V_HUB"; regulator-min-microvolt = <5000000>; From 5cff1135585f5f7d88ad1bbd67ca0f519714a809 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:31:48 +0200 Subject: [PATCH 500/969] arm64: dts: hisilicon: hi6220: correct tsensor unit addresses Correct unit address to fix dtc W=1 warnings: hi6220.dtsi:855.31-862.5: Warning (simple_bus_reg): /soc/tsensor@0,f7030700: simple-bus unit address format error, expected "f7030700" Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index be808bb2544e..a589954c29e2 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -852,7 +852,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - tsensor: tsensor@0,f7030700 { + tsensor: tsensor@f7030700 { compatible = "hisilicon,tsensor"; reg = <0x0 0xf7030700 0x0 0x1000>; interrupts = ; From 4869b5cc9641c0cdc100315f324a73f64576ee66 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Apr 2024 09:32:28 +0800 Subject: [PATCH 501/969] firmware: arm_scmi: Introduce get_max_msg_size() helper/accessor When the agent is sending data to the SCMI platform, the drivers in the agent could check the maximum message size supported to avoid potential protocol buffer overflow. Introduce the helper/accessor function get_max_msg_size() for the same. Reviewed-by: Cristian Marussi Reviewed-by: Dhruva Gole Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20240418-pinctrl-scmi-v11-1-499dca9864a7@nxp.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 15 +++++++++++++++ drivers/firmware/arm_scmi/protocols.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index 36c4ff41dee1..ab5c138e0d09 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -1662,6 +1662,20 @@ out: return ret; } +/** + * scmi_common_get_max_msg_size - Get maximum message size + * @ph: A protocol handle reference. + * + * Return: Maximum message size for the current protocol. + */ +static int scmi_common_get_max_msg_size(const struct scmi_protocol_handle *ph) +{ + const struct scmi_protocol_instance *pi = ph_to_pi(ph); + struct scmi_info *info = handle_to_scmi_info(pi->handle); + + return info->desc->max_msg_size; +} + /** * struct scmi_iterator - Iterator descriptor * @msg: A reference to the message TX buffer; filled by @prepare_message with @@ -1973,6 +1987,7 @@ static int scmi_protocol_msg_check(const struct scmi_protocol_handle *ph, static const struct scmi_proto_helpers_ops helpers_ops = { .extended_name_get = scmi_common_extended_name_get, + .get_max_msg_size = scmi_common_get_max_msg_size, .iter_response_init = scmi_iterator_init, .iter_response_run = scmi_iterator_run, .protocol_msg_check = scmi_protocol_msg_check, diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h index e17dbcfbf299..314371dc0f65 100644 --- a/drivers/firmware/arm_scmi/protocols.h +++ b/drivers/firmware/arm_scmi/protocols.h @@ -260,6 +260,7 @@ struct scmi_fc_info { * @fastchannel_init: A common helper used to initialize FC descriptors by * gathering FC descriptions from the SCMI platform server. * @fastchannel_db_ring: A common helper to ring a FC doorbell. + * @get_max_msg_size: A common helper to get the maximum message size. */ struct scmi_proto_helpers_ops { int (*extended_name_get)(const struct scmi_protocol_handle *ph, @@ -279,6 +280,7 @@ struct scmi_proto_helpers_ops { struct scmi_fc_db_info **p_db, u32 *rate_limit); void (*fastchannel_db_ring)(struct scmi_fc_db_info *db); + int (*get_max_msg_size)(const struct scmi_protocol_handle *ph); }; /** From 1b403075e6cdd9e3bb35046c588cd513d1ef170b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Apr 2024 09:32:29 +0800 Subject: [PATCH 502/969] dt-bindings: firmware: Support SCMI pinctrl protocol Add SCMI v3.2 pinctrl protocol bindings with an example. Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Reviewed-by: Dhruva Gole Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20240418-pinctrl-scmi-v11-2-499dca9864a7@nxp.com Signed-off-by: Sudeep Holla --- .../bindings/firmware/arm,scmi.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 93fb7d05f849..7de2c29606e5 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -247,6 +247,37 @@ properties: reg: const: 0x18 + protocol@19: + type: object + allOf: + - $ref: '#/$defs/protocol-node' + - $ref: /schemas/pinctrl/pinctrl.yaml + + unevaluatedProperties: false + + properties: + reg: + const: 0x19 + + patternProperties: + '-pins$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + unevaluatedProperties: false + + description: + A pin multiplexing sub-node describes how to configure a + set of pins in some desired function. + A single sub-node may define several pin configurations. + This sub-node is using the default pinctrl bindings to configure + pin multiplexing and using SCMI protocol to apply a specified + configuration. + + required: + - reg + additionalProperties: false $defs: @@ -401,6 +432,25 @@ examples: scmi_powercap: protocol@18 { reg = <0x18>; }; + + scmi_pinctrl: protocol@19 { + reg = <0x19>; + + i2c2-pins { + groups = "g_i2c2_a", "g_i2c2_b"; + function = "f_i2c2"; + }; + + mdio-pins { + groups = "g_avb_mdio"; + drive-strength = <24>; + }; + + keys_pins: keys-pins { + pins = "gpio_5_17", "gpio_5_20", "gpio_5_22", "gpio_2_1"; + bias-pull-up; + }; + }; }; }; From 2145af01b9cb326b7dd202a4281976fae614183e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Apr 2024 09:32:30 +0800 Subject: [PATCH 503/969] firmware: arm_scmi: Add basic support for SCMI v3.2 pincontrol protocol Add basic implementation of the SCMI v3.2 pincontrol protocol. Co-developed-by: Oleksii Moisieiev Signed-off-by: Oleksii Moisieiev Co-developed-by: Cristian Marussi Signed-off-by: Cristian Marussi Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20240418-pinctrl-scmi-v11-3-499dca9864a7@nxp.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/Makefile | 3 +- drivers/firmware/arm_scmi/driver.c | 2 + drivers/firmware/arm_scmi/pinctrl.c | 916 ++++++++++++++++++++++++++ drivers/firmware/arm_scmi/protocols.h | 1 + include/linux/scmi_protocol.h | 84 +++ 5 files changed, 1005 insertions(+), 1 deletion(-) create mode 100644 drivers/firmware/arm_scmi/pinctrl.c diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index a7bc4796519c..fd59f58ce8a2 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -10,7 +10,8 @@ scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_SMC) += smc.o scmi-transport-$(CONFIG_ARM_SCMI_HAVE_MSG) += msg.o scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO) += virtio.o scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_OPTEE) += optee.o -scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o powercap.o +scmi-protocols-y := base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o powercap.o +scmi-protocols-y += pinctrl.o scmi-module-objs := $(scmi-driver-y) $(scmi-protocols-y) $(scmi-transport-y) obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-core.o diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index ab5c138e0d09..6b6957f4743f 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -3334,6 +3334,7 @@ static int __init scmi_driver_init(void) scmi_voltage_register(); scmi_system_register(); scmi_powercap_register(); + scmi_pinctrl_register(); return platform_driver_register(&scmi_driver); } @@ -3351,6 +3352,7 @@ static void __exit scmi_driver_exit(void) scmi_voltage_unregister(); scmi_system_unregister(); scmi_powercap_unregister(); + scmi_pinctrl_unregister(); scmi_transports_exit(); diff --git a/drivers/firmware/arm_scmi/pinctrl.c b/drivers/firmware/arm_scmi/pinctrl.c new file mode 100644 index 000000000000..a2a7f880d6a3 --- /dev/null +++ b/drivers/firmware/arm_scmi/pinctrl.c @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Management Interface (SCMI) Pinctrl Protocol + * + * Copyright (C) 2024 EPAM + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "protocols.h" + +/* Updated only after ALL the mandatory features for that version are merged */ +#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x10000 + +#define GET_GROUPS_NR(x) le32_get_bits((x), GENMASK(31, 16)) +#define GET_PINS_NR(x) le32_get_bits((x), GENMASK(15, 0)) +#define GET_FUNCTIONS_NR(x) le32_get_bits((x), GENMASK(15, 0)) + +#define EXT_NAME_FLAG(x) le32_get_bits((x), BIT(31)) +#define NUM_ELEMS(x) le32_get_bits((x), GENMASK(15, 0)) + +#define REMAINING(x) le32_get_bits((x), GENMASK(31, 16)) +#define RETURNED(x) le32_get_bits((x), GENMASK(11, 0)) + +#define CONFIG_FLAG_MASK GENMASK(19, 18) +#define SELECTOR_MASK GENMASK(17, 16) +#define SKIP_CONFIGS_MASK GENMASK(15, 8) +#define CONFIG_TYPE_MASK GENMASK(7, 0) + +enum scmi_pinctrl_protocol_cmd { + PINCTRL_ATTRIBUTES = 0x3, + PINCTRL_LIST_ASSOCIATIONS = 0x4, + PINCTRL_SETTINGS_GET = 0x5, + PINCTRL_SETTINGS_CONFIGURE = 0x6, + PINCTRL_REQUEST = 0x7, + PINCTRL_RELEASE = 0x8, + PINCTRL_NAME_GET = 0x9, + PINCTRL_SET_PERMISSIONS = 0xa, +}; + +struct scmi_msg_settings_conf { + __le32 identifier; + __le32 function_id; + __le32 attributes; + __le32 configs[]; +}; + +struct scmi_msg_settings_get { + __le32 identifier; + __le32 attributes; +}; + +struct scmi_resp_settings_get { + __le32 function_selected; + __le32 num_configs; + __le32 configs[]; +}; + +struct scmi_msg_pinctrl_protocol_attributes { + __le32 attributes_low; + __le32 attributes_high; +}; + +struct scmi_msg_pinctrl_attributes { + __le32 identifier; + __le32 flags; +}; + +struct scmi_resp_pinctrl_attributes { + __le32 attributes; + u8 name[SCMI_SHORT_NAME_MAX_SIZE]; +}; + +struct scmi_msg_pinctrl_list_assoc { + __le32 identifier; + __le32 flags; + __le32 index; +}; + +struct scmi_resp_pinctrl_list_assoc { + __le32 flags; + __le16 array[]; +}; + +struct scmi_msg_request { + __le32 identifier; + __le32 flags; +}; + +struct scmi_group_info { + char name[SCMI_MAX_STR_SIZE]; + bool present; + u32 *group_pins; + u32 nr_pins; +}; + +struct scmi_function_info { + char name[SCMI_MAX_STR_SIZE]; + bool present; + u32 *groups; + u32 nr_groups; +}; + +struct scmi_pin_info { + char name[SCMI_MAX_STR_SIZE]; + bool present; +}; + +struct scmi_pinctrl_info { + u32 version; + int nr_groups; + int nr_functions; + int nr_pins; + struct scmi_group_info *groups; + struct scmi_function_info *functions; + struct scmi_pin_info *pins; +}; + +static int scmi_pinctrl_attributes_get(const struct scmi_protocol_handle *ph, + struct scmi_pinctrl_info *pi) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_pinctrl_protocol_attributes *attr; + + ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES, 0, sizeof(*attr), &t); + if (ret) + return ret; + + attr = t->rx.buf; + + ret = ph->xops->do_xfer(ph, t); + if (!ret) { + pi->nr_functions = GET_FUNCTIONS_NR(attr->attributes_high); + pi->nr_groups = GET_GROUPS_NR(attr->attributes_low); + pi->nr_pins = GET_PINS_NR(attr->attributes_low); + if (pi->nr_pins == 0) { + dev_warn(ph->dev, "returned zero pins\n"); + ret = -EINVAL; + } + } + + ph->xops->xfer_put(ph, t); + return ret; +} + +static int scmi_pinctrl_count_get(const struct scmi_protocol_handle *ph, + enum scmi_pinctrl_selector_type type) +{ + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + switch (type) { + case PIN_TYPE: + return pi->nr_pins; + case GROUP_TYPE: + return pi->nr_groups; + case FUNCTION_TYPE: + return pi->nr_functions; + default: + return -EINVAL; + } +} + +static int scmi_pinctrl_validate_id(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type) +{ + int value; + + value = scmi_pinctrl_count_get(ph, type); + if (value < 0) + return value; + + if (selector >= value || value == 0) + return -EINVAL; + + return 0; +} + +static int scmi_pinctrl_attributes(const struct scmi_protocol_handle *ph, + enum scmi_pinctrl_selector_type type, + u32 selector, char *name, + u32 *n_elems) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_pinctrl_attributes *tx; + struct scmi_resp_pinctrl_attributes *rx; + bool ext_name_flag; + + if (!name) + return -EINVAL; + + ret = scmi_pinctrl_validate_id(ph, selector, type); + if (ret) + return ret; + + ret = ph->xops->xfer_get_init(ph, PINCTRL_ATTRIBUTES, sizeof(*tx), + sizeof(*rx), &t); + if (ret) + return ret; + + tx = t->tx.buf; + rx = t->rx.buf; + tx->identifier = cpu_to_le32(selector); + tx->flags = cpu_to_le32(type); + + ret = ph->xops->do_xfer(ph, t); + if (!ret) { + if (n_elems) + *n_elems = NUM_ELEMS(rx->attributes); + + strscpy(name, rx->name, SCMI_SHORT_NAME_MAX_SIZE); + + ext_name_flag = !!EXT_NAME_FLAG(rx->attributes); + } + + ph->xops->xfer_put(ph, t); + + if (ret) + return ret; + /* + * If supported overwrite short name with the extended one; + * on error just carry on and use already provided short name. + */ + if (ext_name_flag) + ret = ph->hops->extended_name_get(ph, PINCTRL_NAME_GET, + selector, (u32 *)&type, name, + SCMI_MAX_STR_SIZE); + return ret; +} + +struct scmi_pinctrl_ipriv { + u32 selector; + enum scmi_pinctrl_selector_type type; + u32 *array; +}; + +static void iter_pinctrl_assoc_prepare_message(void *message, + u32 desc_index, + const void *priv) +{ + struct scmi_msg_pinctrl_list_assoc *msg = message; + const struct scmi_pinctrl_ipriv *p = priv; + + msg->identifier = cpu_to_le32(p->selector); + msg->flags = cpu_to_le32(p->type); + msg->index = cpu_to_le32(desc_index); +} + +static int iter_pinctrl_assoc_update_state(struct scmi_iterator_state *st, + const void *response, void *priv) +{ + const struct scmi_resp_pinctrl_list_assoc *r = response; + + st->num_returned = RETURNED(r->flags); + st->num_remaining = REMAINING(r->flags); + + return 0; +} + +static int +iter_pinctrl_assoc_process_response(const struct scmi_protocol_handle *ph, + const void *response, + struct scmi_iterator_state *st, void *priv) +{ + const struct scmi_resp_pinctrl_list_assoc *r = response; + struct scmi_pinctrl_ipriv *p = priv; + + p->array[st->desc_index + st->loop_idx] = + le16_to_cpu(r->array[st->loop_idx]); + + return 0; +} + +static int scmi_pinctrl_list_associations(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + u16 size, u32 *array) +{ + int ret; + void *iter; + struct scmi_iterator_ops ops = { + .prepare_message = iter_pinctrl_assoc_prepare_message, + .update_state = iter_pinctrl_assoc_update_state, + .process_response = iter_pinctrl_assoc_process_response, + }; + struct scmi_pinctrl_ipriv ipriv = { + .selector = selector, + .type = type, + .array = array, + }; + + if (!array || !size || type == PIN_TYPE) + return -EINVAL; + + ret = scmi_pinctrl_validate_id(ph, selector, type); + if (ret) + return ret; + + iter = ph->hops->iter_response_init(ph, &ops, size, + PINCTRL_LIST_ASSOCIATIONS, + sizeof(struct scmi_msg_pinctrl_list_assoc), + &ipriv); + if (IS_ERR(iter)) + return PTR_ERR(iter); + + return ph->hops->iter_response_run(iter); +} + +struct scmi_settings_get_ipriv { + u32 selector; + enum scmi_pinctrl_selector_type type; + bool get_all; + unsigned int *nr_configs; + enum scmi_pinctrl_conf_type *config_types; + u32 *config_values; +}; + +static void +iter_pinctrl_settings_get_prepare_message(void *message, u32 desc_index, + const void *priv) +{ + struct scmi_msg_settings_get *msg = message; + const struct scmi_settings_get_ipriv *p = priv; + u32 attributes; + + attributes = FIELD_PREP(SELECTOR_MASK, p->type); + + if (p->get_all) { + attributes |= FIELD_PREP(CONFIG_FLAG_MASK, 1) | + FIELD_PREP(SKIP_CONFIGS_MASK, desc_index); + } else { + attributes |= FIELD_PREP(CONFIG_TYPE_MASK, p->config_types[0]); + } + + msg->attributes = cpu_to_le32(attributes); + msg->identifier = cpu_to_le32(p->selector); +} + +static int +iter_pinctrl_settings_get_update_state(struct scmi_iterator_state *st, + const void *response, void *priv) +{ + const struct scmi_resp_settings_get *r = response; + struct scmi_settings_get_ipriv *p = priv; + + if (p->get_all) { + st->num_returned = le32_get_bits(r->num_configs, GENMASK(7, 0)); + st->num_remaining = le32_get_bits(r->num_configs, GENMASK(31, 24)); + } else { + st->num_returned = 1; + st->num_remaining = 0; + } + + return 0; +} + +static int +iter_pinctrl_settings_get_process_response(const struct scmi_protocol_handle *ph, + const void *response, + struct scmi_iterator_state *st, + void *priv) +{ + const struct scmi_resp_settings_get *r = response; + struct scmi_settings_get_ipriv *p = priv; + u32 type = le32_get_bits(r->configs[st->loop_idx * 2], GENMASK(7, 0)); + u32 val = le32_to_cpu(r->configs[st->loop_idx * 2 + 1]); + + if (p->get_all) { + p->config_types[st->desc_index + st->loop_idx] = type; + } else { + if (p->config_types[0] != type) + return -EINVAL; + } + + p->config_values[st->desc_index + st->loop_idx] = val; + ++*p->nr_configs; + + return 0; +} + +static int +scmi_pinctrl_settings_get(const struct scmi_protocol_handle *ph, u32 selector, + enum scmi_pinctrl_selector_type type, + unsigned int *nr_configs, + enum scmi_pinctrl_conf_type *config_types, + u32 *config_values) +{ + int ret; + void *iter; + unsigned int max_configs = *nr_configs; + struct scmi_iterator_ops ops = { + .prepare_message = iter_pinctrl_settings_get_prepare_message, + .update_state = iter_pinctrl_settings_get_update_state, + .process_response = iter_pinctrl_settings_get_process_response, + }; + struct scmi_settings_get_ipriv ipriv = { + .selector = selector, + .type = type, + .get_all = (max_configs > 1), + .nr_configs = nr_configs, + .config_types = config_types, + .config_values = config_values, + }; + + if (!config_types || !config_values || type == FUNCTION_TYPE) + return -EINVAL; + + ret = scmi_pinctrl_validate_id(ph, selector, type); + if (ret) + return ret; + + /* Prepare to count returned configs */ + *nr_configs = 0; + iter = ph->hops->iter_response_init(ph, &ops, max_configs, + PINCTRL_SETTINGS_GET, + sizeof(struct scmi_msg_settings_get), + &ipriv); + if (IS_ERR(iter)) + return PTR_ERR(iter); + + return ph->hops->iter_response_run(iter); +} + +static int scmi_pinctrl_settings_get_one(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + enum scmi_pinctrl_conf_type config_type, + u32 *config_value) +{ + unsigned int nr_configs = 1; + + return scmi_pinctrl_settings_get(ph, selector, type, &nr_configs, + &config_type, config_value); +} + +static int scmi_pinctrl_settings_get_all(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + unsigned int *nr_configs, + enum scmi_pinctrl_conf_type *config_types, + u32 *config_values) +{ + if (!nr_configs || *nr_configs == 0) + return -EINVAL; + + return scmi_pinctrl_settings_get(ph, selector, type, nr_configs, + config_types, config_values); +} + +static int +scmi_pinctrl_settings_conf(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + u32 nr_configs, + enum scmi_pinctrl_conf_type *config_type, + u32 *config_value) +{ + struct scmi_xfer *t; + struct scmi_msg_settings_conf *tx; + u32 attributes; + int ret, i; + u32 configs_in_chunk, conf_num = 0; + u32 chunk; + int max_msg_size = ph->hops->get_max_msg_size(ph); + + if (!config_type || !config_value || type == FUNCTION_TYPE) + return -EINVAL; + + ret = scmi_pinctrl_validate_id(ph, selector, type); + if (ret) + return ret; + + configs_in_chunk = (max_msg_size - sizeof(*tx)) / (sizeof(__le32) * 2); + while (conf_num < nr_configs) { + chunk = (nr_configs - conf_num > configs_in_chunk) ? + configs_in_chunk : nr_configs - conf_num; + + ret = ph->xops->xfer_get_init(ph, PINCTRL_SETTINGS_CONFIGURE, + sizeof(*tx) + + chunk * 2 * sizeof(__le32), 0, &t); + if (ret) + break; + + tx = t->tx.buf; + tx->identifier = cpu_to_le32(selector); + tx->function_id = cpu_to_le32(0xFFFFFFFF); + attributes = FIELD_PREP(GENMASK(1, 0), type) | + FIELD_PREP(GENMASK(9, 2), chunk); + tx->attributes = cpu_to_le32(attributes); + + for (i = 0; i < chunk; i++) { + tx->configs[i * 2] = + cpu_to_le32(config_type[conf_num + i]); + tx->configs[i * 2 + 1] = + cpu_to_le32(config_value[conf_num + i]); + } + + ret = ph->xops->do_xfer(ph, t); + + ph->xops->xfer_put(ph, t); + + if (ret) + break; + + conf_num += chunk; + } + + return ret; +} + +static int scmi_pinctrl_function_select(const struct scmi_protocol_handle *ph, + u32 group, + enum scmi_pinctrl_selector_type type, + u32 function_id) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_settings_conf *tx; + u32 attributes; + + ret = scmi_pinctrl_validate_id(ph, group, type); + if (ret) + return ret; + + ret = ph->xops->xfer_get_init(ph, PINCTRL_SETTINGS_CONFIGURE, + sizeof(*tx), 0, &t); + if (ret) + return ret; + + tx = t->tx.buf; + tx->identifier = cpu_to_le32(group); + tx->function_id = cpu_to_le32(function_id); + attributes = FIELD_PREP(GENMASK(1, 0), type) | BIT(10); + tx->attributes = cpu_to_le32(attributes); + + ret = ph->xops->do_xfer(ph, t); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int scmi_pinctrl_request_free(const struct scmi_protocol_handle *ph, + u32 identifier, + enum scmi_pinctrl_selector_type type, + enum scmi_pinctrl_protocol_cmd cmd) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_request *tx; + + if (type == FUNCTION_TYPE) + return -EINVAL; + + if (cmd != PINCTRL_REQUEST && cmd != PINCTRL_RELEASE) + return -EINVAL; + + ret = scmi_pinctrl_validate_id(ph, identifier, type); + if (ret) + return ret; + + ret = ph->xops->xfer_get_init(ph, cmd, sizeof(*tx), 0, &t); + if (ret) + return ret; + + tx = t->tx.buf; + tx->identifier = cpu_to_le32(identifier); + tx->flags = cpu_to_le32(type); + + ret = ph->xops->do_xfer(ph, t); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int scmi_pinctrl_pin_request(const struct scmi_protocol_handle *ph, + u32 pin) +{ + return scmi_pinctrl_request_free(ph, pin, PIN_TYPE, PINCTRL_REQUEST); +} + +static int scmi_pinctrl_pin_free(const struct scmi_protocol_handle *ph, u32 pin) +{ + return scmi_pinctrl_request_free(ph, pin, PIN_TYPE, PINCTRL_RELEASE); +} + +static int scmi_pinctrl_get_group_info(const struct scmi_protocol_handle *ph, + u32 selector, + struct scmi_group_info *group) +{ + int ret; + + ret = scmi_pinctrl_attributes(ph, GROUP_TYPE, selector, group->name, + &group->nr_pins); + if (ret) + return ret; + + if (!group->nr_pins) { + dev_err(ph->dev, "Group %d has 0 elements", selector); + return -ENODATA; + } + + group->group_pins = kmalloc_array(group->nr_pins, + sizeof(*group->group_pins), + GFP_KERNEL); + if (!group->group_pins) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(ph, selector, GROUP_TYPE, + group->nr_pins, group->group_pins); + if (ret) { + kfree(group->group_pins); + return ret; + } + + group->present = true; + return 0; +} + +static int scmi_pinctrl_get_group_name(const struct scmi_protocol_handle *ph, + u32 selector, const char **name) +{ + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + if (!name) + return -EINVAL; + + if (selector >= pi->nr_groups || pi->nr_groups == 0) + return -EINVAL; + + if (!pi->groups[selector].present) { + int ret; + + ret = scmi_pinctrl_get_group_info(ph, selector, + &pi->groups[selector]); + if (ret) + return ret; + } + + *name = pi->groups[selector].name; + + return 0; +} + +static int scmi_pinctrl_group_pins_get(const struct scmi_protocol_handle *ph, + u32 selector, const u32 **pins, + u32 *nr_pins) +{ + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + if (!pins || !nr_pins) + return -EINVAL; + + if (selector >= pi->nr_groups || pi->nr_groups == 0) + return -EINVAL; + + if (!pi->groups[selector].present) { + int ret; + + ret = scmi_pinctrl_get_group_info(ph, selector, + &pi->groups[selector]); + if (ret) + return ret; + } + + *pins = pi->groups[selector].group_pins; + *nr_pins = pi->groups[selector].nr_pins; + + return 0; +} + +static int scmi_pinctrl_get_function_info(const struct scmi_protocol_handle *ph, + u32 selector, + struct scmi_function_info *func) +{ + int ret; + + ret = scmi_pinctrl_attributes(ph, FUNCTION_TYPE, selector, func->name, + &func->nr_groups); + if (ret) + return ret; + + if (!func->nr_groups) { + dev_err(ph->dev, "Function %d has 0 elements", selector); + return -ENODATA; + } + + func->groups = kmalloc_array(func->nr_groups, sizeof(*func->groups), + GFP_KERNEL); + if (!func->groups) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(ph, selector, FUNCTION_TYPE, + func->nr_groups, func->groups); + if (ret) { + kfree(func->groups); + return ret; + } + + func->present = true; + return 0; +} + +static int scmi_pinctrl_get_function_name(const struct scmi_protocol_handle *ph, + u32 selector, const char **name) +{ + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + if (!name) + return -EINVAL; + + if (selector >= pi->nr_functions || pi->nr_functions == 0) + return -EINVAL; + + if (!pi->functions[selector].present) { + int ret; + + ret = scmi_pinctrl_get_function_info(ph, selector, + &pi->functions[selector]); + if (ret) + return ret; + } + + *name = pi->functions[selector].name; + return 0; +} + +static int +scmi_pinctrl_function_groups_get(const struct scmi_protocol_handle *ph, + u32 selector, u32 *nr_groups, + const u32 **groups) +{ + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + if (!groups || !nr_groups) + return -EINVAL; + + if (selector >= pi->nr_functions || pi->nr_functions == 0) + return -EINVAL; + + if (!pi->functions[selector].present) { + int ret; + + ret = scmi_pinctrl_get_function_info(ph, selector, + &pi->functions[selector]); + if (ret) + return ret; + } + + *groups = pi->functions[selector].groups; + *nr_groups = pi->functions[selector].nr_groups; + + return 0; +} + +static int scmi_pinctrl_mux_set(const struct scmi_protocol_handle *ph, + u32 selector, u32 group) +{ + return scmi_pinctrl_function_select(ph, group, GROUP_TYPE, selector); +} + +static int scmi_pinctrl_get_pin_info(const struct scmi_protocol_handle *ph, + u32 selector, struct scmi_pin_info *pin) +{ + int ret; + + if (!pin) + return -EINVAL; + + ret = scmi_pinctrl_attributes(ph, PIN_TYPE, selector, pin->name, NULL); + if (ret) + return ret; + + pin->present = true; + return 0; +} + +static int scmi_pinctrl_get_pin_name(const struct scmi_protocol_handle *ph, + u32 selector, const char **name) +{ + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + if (!name) + return -EINVAL; + + if (selector >= pi->nr_pins) + return -EINVAL; + + if (!pi->pins[selector].present) { + int ret; + + ret = scmi_pinctrl_get_pin_info(ph, selector, &pi->pins[selector]); + if (ret) + return ret; + } + + *name = pi->pins[selector].name; + + return 0; +} + +static int scmi_pinctrl_name_get(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + const char **name) +{ + switch (type) { + case PIN_TYPE: + return scmi_pinctrl_get_pin_name(ph, selector, name); + case GROUP_TYPE: + return scmi_pinctrl_get_group_name(ph, selector, name); + case FUNCTION_TYPE: + return scmi_pinctrl_get_function_name(ph, selector, name); + default: + return -EINVAL; + } +} + +static const struct scmi_pinctrl_proto_ops pinctrl_proto_ops = { + .count_get = scmi_pinctrl_count_get, + .name_get = scmi_pinctrl_name_get, + .group_pins_get = scmi_pinctrl_group_pins_get, + .function_groups_get = scmi_pinctrl_function_groups_get, + .mux_set = scmi_pinctrl_mux_set, + .settings_get_one = scmi_pinctrl_settings_get_one, + .settings_get_all = scmi_pinctrl_settings_get_all, + .settings_conf = scmi_pinctrl_settings_conf, + .pin_request = scmi_pinctrl_pin_request, + .pin_free = scmi_pinctrl_pin_free, +}; + +static int scmi_pinctrl_protocol_init(const struct scmi_protocol_handle *ph) +{ + int ret; + u32 version; + struct scmi_pinctrl_info *pinfo; + + ret = ph->xops->version_get(ph, &version); + if (ret) + return ret; + + dev_dbg(ph->dev, "Pinctrl Version %d.%d\n", + PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version)); + + pinfo = devm_kzalloc(ph->dev, sizeof(*pinfo), GFP_KERNEL); + if (!pinfo) + return -ENOMEM; + + ret = scmi_pinctrl_attributes_get(ph, pinfo); + if (ret) + return ret; + + pinfo->pins = devm_kcalloc(ph->dev, pinfo->nr_pins, + sizeof(*pinfo->pins), GFP_KERNEL); + if (!pinfo->pins) + return -ENOMEM; + + pinfo->groups = devm_kcalloc(ph->dev, pinfo->nr_groups, + sizeof(*pinfo->groups), GFP_KERNEL); + if (!pinfo->groups) + return -ENOMEM; + + pinfo->functions = devm_kcalloc(ph->dev, pinfo->nr_functions, + sizeof(*pinfo->functions), GFP_KERNEL); + if (!pinfo->functions) + return -ENOMEM; + + pinfo->version = version; + + return ph->set_priv(ph, pinfo, version); +} + +static int scmi_pinctrl_protocol_deinit(const struct scmi_protocol_handle *ph) +{ + int i; + struct scmi_pinctrl_info *pi = ph->get_priv(ph); + + /* Free groups_pins allocated in scmi_pinctrl_get_group_info */ + for (i = 0; i < pi->nr_groups; i++) { + if (pi->groups[i].present) { + kfree(pi->groups[i].group_pins); + pi->groups[i].present = false; + } + } + + /* Free groups allocated in scmi_pinctrl_get_function_info */ + for (i = 0; i < pi->nr_functions; i++) { + if (pi->functions[i].present) { + kfree(pi->functions[i].groups); + pi->functions[i].present = false; + } + } + + return 0; +} + +static const struct scmi_protocol scmi_pinctrl = { + .id = SCMI_PROTOCOL_PINCTRL, + .owner = THIS_MODULE, + .instance_init = &scmi_pinctrl_protocol_init, + .instance_deinit = &scmi_pinctrl_protocol_deinit, + .ops = &pinctrl_proto_ops, + .supported_version = SCMI_PROTOCOL_SUPPORTED_VERSION, +}; +DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(pinctrl, scmi_pinctrl) diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h index 314371dc0f65..8e95f53bd7b7 100644 --- a/drivers/firmware/arm_scmi/protocols.h +++ b/drivers/firmware/arm_scmi/protocols.h @@ -370,6 +370,7 @@ void __exit scmi_##name##_unregister(void) \ DECLARE_SCMI_REGISTER_UNREGISTER(base); DECLARE_SCMI_REGISTER_UNREGISTER(clock); DECLARE_SCMI_REGISTER_UNREGISTER(perf); +DECLARE_SCMI_REGISTER_UNREGISTER(pinctrl); DECLARE_SCMI_REGISTER_UNREGISTER(power); DECLARE_SCMI_REGISTER_UNREGISTER(reset); DECLARE_SCMI_REGISTER_UNREGISTER(sensors); diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index a3addb07e00a..3a9bb5b9a9e8 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -737,6 +737,89 @@ struct scmi_powercap_proto_ops { u32 *power_thresh_high); }; +enum scmi_pinctrl_selector_type { + PIN_TYPE = 0, + GROUP_TYPE, + FUNCTION_TYPE, +}; + +enum scmi_pinctrl_conf_type { + SCMI_PIN_DEFAULT = 0, + SCMI_PIN_BIAS_BUS_HOLD = 1, + SCMI_PIN_BIAS_DISABLE = 2, + SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3, + SCMI_PIN_BIAS_PULL_UP = 4, + SCMI_PIN_BIAS_PULL_DEFAULT = 5, + SCMI_PIN_BIAS_PULL_DOWN = 6, + SCMI_PIN_DRIVE_OPEN_DRAIN = 7, + SCMI_PIN_DRIVE_OPEN_SOURCE = 8, + SCMI_PIN_DRIVE_PUSH_PULL = 9, + SCMI_PIN_DRIVE_STRENGTH = 10, + SCMI_PIN_INPUT_DEBOUNCE = 11, + SCMI_PIN_INPUT_MODE = 12, + SCMI_PIN_PULL_MODE = 13, + SCMI_PIN_INPUT_VALUE = 14, + SCMI_PIN_INPUT_SCHMITT = 15, + SCMI_PIN_LOW_POWER_MODE = 16, + SCMI_PIN_OUTPUT_MODE = 17, + SCMI_PIN_OUTPUT_VALUE = 18, + SCMI_PIN_POWER_SOURCE = 19, + SCMI_PIN_SLEW_RATE = 20, + SCMI_PIN_OEM_START = 192, + SCMI_PIN_OEM_END = 255, +}; + +/** + * struct scmi_pinctrl_proto_ops - represents the various operations provided + * by SCMI Pinctrl Protocol + * + * @count_get: returns count of the registered elements in given type + * @name_get: returns name by index of given type + * @group_pins_get: returns the set of pins, assigned to the specified group + * @function_groups_get: returns the set of groups, assigned to the specified + * function + * @mux_set: set muxing function for groups of pins + * @settings_get_one: returns one configuration parameter for pin or group + * specified by config_type + * @settings_get_all: returns all configuration parameters for pin or group + * @settings_conf: sets the configuration parameter for pin or group + * @pin_request: aquire pin before selecting mux setting + * @pin_free: frees pin, acquired by request_pin call + */ +struct scmi_pinctrl_proto_ops { + int (*count_get)(const struct scmi_protocol_handle *ph, + enum scmi_pinctrl_selector_type type); + int (*name_get)(const struct scmi_protocol_handle *ph, u32 selector, + enum scmi_pinctrl_selector_type type, + const char **name); + int (*group_pins_get)(const struct scmi_protocol_handle *ph, + u32 selector, const unsigned int **pins, + unsigned int *nr_pins); + int (*function_groups_get)(const struct scmi_protocol_handle *ph, + u32 selector, unsigned int *nr_groups, + const unsigned int **groups); + int (*mux_set)(const struct scmi_protocol_handle *ph, u32 selector, + u32 group); + int (*settings_get_one)(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + enum scmi_pinctrl_conf_type config_type, + u32 *config_value); + int (*settings_get_all)(const struct scmi_protocol_handle *ph, + u32 selector, + enum scmi_pinctrl_selector_type type, + unsigned int *nr_configs, + enum scmi_pinctrl_conf_type *config_types, + u32 *config_values); + int (*settings_conf)(const struct scmi_protocol_handle *ph, + u32 selector, enum scmi_pinctrl_selector_type type, + unsigned int nr_configs, + enum scmi_pinctrl_conf_type *config_type, + u32 *config_value); + int (*pin_request)(const struct scmi_protocol_handle *ph, u32 pin); + int (*pin_free)(const struct scmi_protocol_handle *ph, u32 pin); +}; + /** * struct scmi_notify_ops - represents notifications' operations provided by * SCMI core @@ -842,6 +925,7 @@ enum scmi_std_protocol { SCMI_PROTOCOL_RESET = 0x16, SCMI_PROTOCOL_VOLTAGE = 0x17, SCMI_PROTOCOL_POWERCAP = 0x18, + SCMI_PROTOCOL_PINCTRL = 0x19, }; enum scmi_system_events { From eb524cb651b794f2529e36deb6b18523adc9ecaa Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 18 Apr 2024 09:32:31 +0800 Subject: [PATCH 504/969] pinctrl: Implementation of the generic scmi-pinctrl driver scmi-pinctrl driver implements pinctrl driver interface and using SCMI protocol to redirect messages from pinctrl subsystem SDK to SCMI platform firmware, which does the changes in HW. Co-developed-by: Oleksii Moisieiev Signed-off-by: Oleksii Moisieiev Reviewed-by: Dhruva Gole Reviewed-by: Andy Shevchenko Acked-by: Linus Walleij Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20240418-pinctrl-scmi-v11-4-499dca9864a7@nxp.com Signed-off-by: Sudeep Holla --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-scmi.c | 571 +++++++++++++++++++++++++++++++++ 4 files changed, 584 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-scmi.c diff --git a/MAINTAINERS b/MAINTAINERS index aa3b947fb080..a32f0b879b06 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21453,6 +21453,7 @@ F: drivers/cpufreq/sc[mp]i-cpufreq.c F: drivers/firmware/arm_scmi/ F: drivers/firmware/arm_scpi.c F: drivers/hwmon/scmi-hwmon.c +F: drivers/pinctrl/pinctrl-scmi.c F: drivers/pmdomain/arm/ F: drivers/powercap/arm_scmi_powercap.c F: drivers/regulator/scmi-regulator.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index d45657aa986a..4e6f65cf0e76 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -450,6 +450,17 @@ config PINCTRL_ROCKCHIP help This support pinctrl and GPIO driver for Rockchip SoCs. +config PINCTRL_SCMI + tristate "Pinctrl driver using SCMI protocol interface" + depends on ARM_SCMI_PROTOCOL || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + help + This driver provides support for pinctrl which is controlled + by firmware that implements the SCMI interface. + It uses SCMI Message Protocol to interact with the + firmware providing all the pinctrl controls. + config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 2152539b53d5..cc809669405a 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c new file mode 100644 index 000000000000..036bc1e3fc6c --- /dev/null +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * System Control and Power Interface (SCMI) Protocol based pinctrl driver + * + * Copyright (C) 2024 EPAM + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" +#include "core.h" +#include "pinconf.h" + +#define DRV_NAME "scmi-pinctrl" + +/* Define num configs, if not large than 4 use stack, else use kcalloc() */ +#define SCMI_NUM_CONFIGS 4 + +static const struct scmi_pinctrl_proto_ops *pinctrl_ops; + +struct scmi_pinctrl { + struct device *dev; + struct scmi_protocol_handle *ph; + struct pinctrl_dev *pctldev; + struct pinctrl_desc pctl_desc; + struct pinfunction *functions; + unsigned int nr_functions; + struct pinctrl_pin_desc *pins; + unsigned int nr_pins; +}; + +static int pinctrl_scmi_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl_ops->count_get(pmx->ph, GROUP_TYPE); +} + +static const char *pinctrl_scmi_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + int ret; + const char *name; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + ret = pinctrl_ops->name_get(pmx->ph, selector, GROUP_TYPE, &name); + if (ret) { + dev_err(pmx->dev, "get name failed with err %d", ret); + return NULL; + } + + return name; +} + +static int pinctrl_scmi_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl_ops->group_pins_get(pmx->ph, selector, pins, num_pins); +} + +static const struct pinctrl_ops pinctrl_scmi_pinctrl_ops = { + .get_groups_count = pinctrl_scmi_get_groups_count, + .get_group_name = pinctrl_scmi_get_group_name, + .get_group_pins = pinctrl_scmi_get_group_pins, +#ifdef CONFIG_OF + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +#endif +}; + +static int pinctrl_scmi_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl_ops->count_get(pmx->ph, FUNCTION_TYPE); +} + +static const char *pinctrl_scmi_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + int ret; + const char *name; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + ret = pinctrl_ops->name_get(pmx->ph, selector, FUNCTION_TYPE, &name); + if (ret) { + dev_err(pmx->dev, "get name failed with err %d", ret); + return NULL; + } + + return name; +} + +static int pinctrl_scmi_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **p_groups, + unsigned int * const p_num_groups) +{ + struct pinfunction *func; + const unsigned int *group_ids; + unsigned int num_groups; + const char **groups; + int ret, i; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + if (!p_groups || !p_num_groups) + return -EINVAL; + + if (selector >= pmx->nr_functions) + return -EINVAL; + + func = &pmx->functions[selector]; + if (func->ngroups) + goto done; + + ret = pinctrl_ops->function_groups_get(pmx->ph, selector, &num_groups, + &group_ids); + if (ret) { + dev_err(pmx->dev, "Unable to get function groups, err %d", ret); + return ret; + } + if (!num_groups) + return -EINVAL; + + groups = kcalloc(num_groups, sizeof(*groups), GFP_KERNEL); + if (!groups) + return -ENOMEM; + + for (i = 0; i < num_groups; i++) { + groups[i] = pinctrl_scmi_get_group_name(pctldev, group_ids[i]); + if (!groups[i]) { + ret = -EINVAL; + goto err_free; + } + } + + func->ngroups = num_groups; + func->groups = groups; +done: + *p_groups = func->groups; + *p_num_groups = func->ngroups; + + return 0; + +err_free: + kfree(groups); + + return ret; +} + +static int pinctrl_scmi_func_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl_ops->mux_set(pmx->ph, selector, group); +} + +static int pinctrl_scmi_request(struct pinctrl_dev *pctldev, + unsigned int offset) +{ + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl_ops->pin_request(pmx->ph, offset); +} + +static int pinctrl_scmi_free(struct pinctrl_dev *pctldev, unsigned int offset) +{ + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + + return pinctrl_ops->pin_free(pmx->ph, offset); +} + +static const struct pinmux_ops pinctrl_scmi_pinmux_ops = { + .request = pinctrl_scmi_request, + .free = pinctrl_scmi_free, + .get_functions_count = pinctrl_scmi_get_functions_count, + .get_function_name = pinctrl_scmi_get_function_name, + .get_function_groups = pinctrl_scmi_get_function_groups, + .set_mux = pinctrl_scmi_func_set_mux, +}; + +static int pinctrl_scmi_map_pinconf_type(enum pin_config_param param, + enum scmi_pinctrl_conf_type *type) +{ + u32 arg = param; + + switch (arg) { + case PIN_CONFIG_BIAS_BUS_HOLD: + *type = SCMI_PIN_BIAS_BUS_HOLD; + break; + case PIN_CONFIG_BIAS_DISABLE: + *type = SCMI_PIN_BIAS_DISABLE; + break; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + *type = SCMI_PIN_BIAS_HIGH_IMPEDANCE; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + *type = SCMI_PIN_BIAS_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + *type = SCMI_PIN_BIAS_PULL_DEFAULT; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *type = SCMI_PIN_BIAS_PULL_UP; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + *type = SCMI_PIN_DRIVE_OPEN_DRAIN; + break; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + *type = SCMI_PIN_DRIVE_OPEN_SOURCE; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + *type = SCMI_PIN_DRIVE_PUSH_PULL; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + *type = SCMI_PIN_DRIVE_STRENGTH; + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + *type = SCMI_PIN_DRIVE_STRENGTH; + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + *type = SCMI_PIN_INPUT_DEBOUNCE; + break; + case PIN_CONFIG_INPUT_ENABLE: + *type = SCMI_PIN_INPUT_MODE; + break; + case PIN_CONFIG_INPUT_SCHMITT: + *type = SCMI_PIN_INPUT_SCHMITT; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *type = SCMI_PIN_INPUT_MODE; + break; + case PIN_CONFIG_MODE_LOW_POWER: + *type = SCMI_PIN_LOW_POWER_MODE; + break; + case PIN_CONFIG_OUTPUT: + *type = SCMI_PIN_OUTPUT_VALUE; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + *type = SCMI_PIN_OUTPUT_MODE; + break; + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: + *type = SCMI_PIN_OUTPUT_VALUE; + break; + case PIN_CONFIG_POWER_SOURCE: + *type = SCMI_PIN_POWER_SOURCE; + break; + case PIN_CONFIG_SLEW_RATE: + *type = SCMI_PIN_SLEW_RATE; + break; + case SCMI_PIN_OEM_START ... SCMI_PIN_OEM_END: + *type = arg; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int pinctrl_scmi_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + int ret; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param config_type; + enum scmi_pinctrl_conf_type type; + u32 config_value; + + if (!config) + return -EINVAL; + + config_type = pinconf_to_config_param(*config); + + ret = pinctrl_scmi_map_pinconf_type(config_type, &type); + if (ret) + return ret; + + ret = pinctrl_ops->settings_get_one(pmx->ph, pin, PIN_TYPE, type, + &config_value); + /* Convert SCMI error code to PINCTRL expected error code */ + if (ret == -EOPNOTSUPP) + return -ENOTSUPP; + if (ret) + return ret; + + *config = pinconf_to_config_packed(config_type, config_value); + + return 0; +} + +static int +pinctrl_scmi_alloc_configs(struct pinctrl_dev *pctldev, u32 num_configs, + u32 **p_config_value, + enum scmi_pinctrl_conf_type **p_config_type) +{ + if (num_configs <= SCMI_NUM_CONFIGS) + return 0; + + *p_config_value = kcalloc(num_configs, sizeof(**p_config_value), GFP_KERNEL); + if (!*p_config_value) + return -ENOMEM; + + *p_config_type = kcalloc(num_configs, sizeof(**p_config_type), GFP_KERNEL); + if (!*p_config_type) { + kfree(*p_config_value); + return -ENOMEM; + } + + return 0; +} + +static void +pinctrl_scmi_free_configs(struct pinctrl_dev *pctldev, u32 num_configs, + u32 **p_config_value, + enum scmi_pinctrl_conf_type **p_config_type) +{ + if (num_configs <= SCMI_NUM_CONFIGS) + return; + + kfree(*p_config_value); + kfree(*p_config_type); +} + +static int pinctrl_scmi_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, + unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS]; + u32 config_value[SCMI_NUM_CONFIGS]; + enum scmi_pinctrl_conf_type *p_config_type = config_type; + u32 *p_config_value = config_value; + enum pin_config_param param; + + if (!configs || !num_configs) + return -EINVAL; + + ret = pinctrl_scmi_alloc_configs(pctldev, num_configs, &p_config_type, + &p_config_value); + if (ret) + return ret; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + ret = pinctrl_scmi_map_pinconf_type(param, &p_config_type[i]); + if (ret) { + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret); + goto free_config; + } + p_config_value[i] = pinconf_to_config_argument(configs[i]); + } + + ret = pinctrl_ops->settings_conf(pmx->ph, pin, PIN_TYPE, num_configs, + p_config_type, p_config_value); + if (ret) + dev_err(pmx->dev, "Error parsing config %d\n", ret); + +free_config: + pinctrl_scmi_free_configs(pctldev, num_configs, &p_config_type, + &p_config_value); + return ret; +} + +static int pinctrl_scmi_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + int i, ret; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + enum scmi_pinctrl_conf_type config_type[SCMI_NUM_CONFIGS]; + u32 config_value[SCMI_NUM_CONFIGS]; + enum scmi_pinctrl_conf_type *p_config_type = config_type; + u32 *p_config_value = config_value; + enum pin_config_param param; + + if (!configs || !num_configs) + return -EINVAL; + + ret = pinctrl_scmi_alloc_configs(pctldev, num_configs, &p_config_type, + &p_config_value); + if (ret) + return ret; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + ret = pinctrl_scmi_map_pinconf_type(param, &p_config_type[i]); + if (ret) { + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret); + goto free_config; + } + + p_config_value[i] = pinconf_to_config_argument(configs[i]); + } + + ret = pinctrl_ops->settings_conf(pmx->ph, group, GROUP_TYPE, + num_configs, p_config_type, + p_config_value); + if (ret) + dev_err(pmx->dev, "Error parsing config %d", ret); + +free_config: + pinctrl_scmi_free_configs(pctldev, num_configs, &p_config_type, + &p_config_value); + return ret; +}; + +static int pinctrl_scmi_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *config) +{ + int ret; + struct scmi_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param config_type; + enum scmi_pinctrl_conf_type type; + u32 config_value; + + if (!config) + return -EINVAL; + + config_type = pinconf_to_config_param(*config); + ret = pinctrl_scmi_map_pinconf_type(config_type, &type); + if (ret) { + dev_err(pmx->dev, "Error map pinconf_type %d\n", ret); + return ret; + } + + ret = pinctrl_ops->settings_get_one(pmx->ph, group, GROUP_TYPE, type, + &config_value); + /* Convert SCMI error code to PINCTRL expected error code */ + if (ret == -EOPNOTSUPP) + return -ENOTSUPP; + if (ret) + return ret; + + *config = pinconf_to_config_packed(config_type, config_value); + + return 0; +} + +static const struct pinconf_ops pinctrl_scmi_pinconf_ops = { + .is_generic = true, + .pin_config_get = pinctrl_scmi_pinconf_get, + .pin_config_set = pinctrl_scmi_pinconf_set, + .pin_config_group_set = pinctrl_scmi_pinconf_group_set, + .pin_config_group_get = pinctrl_scmi_pinconf_group_get, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx, + struct pinctrl_desc *desc) +{ + struct pinctrl_pin_desc *pins; + unsigned int npins; + int ret, i; + + npins = pinctrl_ops->count_get(pmx->ph, PIN_TYPE); + /* + * npins will never be zero, the scmi pinctrl driver has bailed out + * if npins is zero. + */ + pins = devm_kmalloc_array(pmx->dev, npins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < npins; i++) { + pins[i].number = i; + /* + * The memory for name is handled by the scmi firmware driver, + * no need free here + */ + ret = pinctrl_ops->name_get(pmx->ph, i, PIN_TYPE, &pins[i].name); + if (ret) + return dev_err_probe(pmx->dev, ret, + "Can't get name for pin %d", i); + } + + desc->npins = npins; + desc->pins = pins; + dev_dbg(pmx->dev, "got pins %u", npins); + + return 0; +} + +static int scmi_pinctrl_probe(struct scmi_device *sdev) +{ + int ret; + struct device *dev = &sdev->dev; + struct scmi_pinctrl *pmx; + const struct scmi_handle *handle; + struct scmi_protocol_handle *ph; + + if (!sdev->handle) + return -EINVAL; + + handle = sdev->handle; + + pinctrl_ops = handle->devm_protocol_get(sdev, SCMI_PROTOCOL_PINCTRL, &ph); + if (IS_ERR(pinctrl_ops)) + return PTR_ERR(pinctrl_ops); + + pmx = devm_kzalloc(dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->ph = ph; + + pmx->dev = dev; + pmx->pctl_desc.name = DRV_NAME; + pmx->pctl_desc.owner = THIS_MODULE; + pmx->pctl_desc.pctlops = &pinctrl_scmi_pinctrl_ops; + pmx->pctl_desc.pmxops = &pinctrl_scmi_pinmux_ops; + pmx->pctl_desc.confops = &pinctrl_scmi_pinconf_ops; + + ret = pinctrl_scmi_get_pins(pmx, &pmx->pctl_desc); + if (ret) + return ret; + + ret = devm_pinctrl_register_and_init(dev, &pmx->pctl_desc, pmx, + &pmx->pctldev); + if (ret) + return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); + + pmx->nr_functions = pinctrl_scmi_get_functions_count(pmx->pctldev); + pmx->functions = devm_kcalloc(dev, pmx->nr_functions, + sizeof(*pmx->functions), GFP_KERNEL); + if (!pmx->functions) + return -ENOMEM; + + return pinctrl_enable(pmx->pctldev); +} + +static const struct scmi_device_id scmi_id_table[] = { + { SCMI_PROTOCOL_PINCTRL, "pinctrl" }, + { } +}; +MODULE_DEVICE_TABLE(scmi, scmi_id_table); + +static struct scmi_driver scmi_pinctrl_driver = { + .name = DRV_NAME, + .probe = scmi_pinctrl_probe, + .id_table = scmi_id_table, +}; +module_scmi_driver(scmi_pinctrl_driver); + +MODULE_AUTHOR("Oleksii Moisieiev "); +MODULE_AUTHOR("Peng Fan "); +MODULE_DESCRIPTION("ARM SCMI pin controller driver"); +MODULE_LICENSE("GPL"); From 8a2a43a978e51bcddfe8a89bb2acebcf24f1d767 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Apr 2024 19:13:56 +0300 Subject: [PATCH 505/969] arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in The link-frequencies belong in mdss_dp3_out. Drop them from mdss_dp3_in. Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-1-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index fa04a24173a7..a8dfd8146706 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4095,8 +4095,6 @@ mdss_dp3_in: endpoint { remote-endpoint = <&mdss_intf5_out>; - - link-frequencies = /bits/ 64 <8100000000>; }; }; From 2351d205081cf4e7d960c0dbc5891e5fbda0b1f0 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Apr 2024 19:13:57 +0300 Subject: [PATCH 506/969] arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3 The data-lanes are a property of the out remote endpoint, so move them from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to mdss_dp3_out and make sure to include all frequencies. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-2-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index d4198fa204fd..c5c2895b37c7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -599,8 +599,6 @@ compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; - data-lanes = <0 1 2 3>; - status = "okay"; aux-bus { @@ -620,6 +618,9 @@ port@1 { reg = <1>; mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&edp_panel_in>; }; }; From 78a4407ca834cc448cb015e714ca230ec6bb4503 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Apr 2024 19:13:58 +0300 Subject: [PATCH 507/969] arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3 The data-lanes are a property of the out remote endpoint, so move them from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to mdss_dp3_out and make sure to include all frequencies. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-3-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 35580ac3430d..2061fbe7b75a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -410,8 +410,6 @@ compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; - data-lanes = <0 1 2 3>; - status = "okay"; aux-bus { @@ -431,6 +429,9 @@ port@1 { reg = <1>; mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&edp_panel_in>; }; }; From 5927bc586a3f2a81abcf8134fda5f7639abeeefd Mon Sep 17 00:00:00 2001 From: Volodymyr Babchuk Date: Fri, 12 Apr 2024 19:03:26 +0000 Subject: [PATCH 508/969] arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator Voltage regulator L13C is used by SD card IO interface. In order to support UHS modes, IO interface voltage needs to be set to 1.8V. This patch extends minimum voltage range of L13C regulator to allow this. Signed-off-by: Volodymyr Babchuk Fixes: 0deb2624e2d0 ("arm64: dts: qcom: sa8155p-adp: Add support for uSD card") Suggested-by: Stephan Gerhold Link: https://lore.kernel.org/r/20240412190310.1647893-2-volodymyr_babchuk@epam.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 5e4287f8c8cd..4f805c47fbfd 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -283,7 +283,7 @@ vreg_l13c_2p96: ldo13 { regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2960000>; regulator-initial-mode = ; }; From 776c5f3c9c9a28f5eea0f8fc2a49e83bb87fe7d2 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Fri, 12 Apr 2024 18:02:37 +0530 Subject: [PATCH 509/969] arm64: dts: qcom: qcm6490-idp: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making it impossible to reason debug prints and regulator_summary. Signed-off-by: Umang Chheda Link: https://lore.kernel.org/r/20240412123237.2633000-1-quic_uchheda@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index f8f8a43f638d..ac6d741868ca 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -195,129 +195,151 @@ vdd-l14-l16-supply = <&vreg_s8b_1p272>; vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; regulator-min-microvolt = <570070>; regulator-max-microvolt = <1050000>; }; vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = ; }; vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = ; }; vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = ; }; vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; regulator-min-microvolt = <752000>; regulator-max-microvolt = <820000>; regulator-initial-mode = ; }; reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; regulator-min-microvolt = <552000>; regulator-max-microvolt = <832000>; regulator-initial-mode = ; }; vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = ; }; vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = ; }; vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = ; }; vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -349,109 +371,128 @@ vdd-bob-supply = <&vph_pwr>; vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; }; vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <800000>; }; vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <1050000>; }; vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <800000>; }; vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; }; vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3540000>; regulator-initial-mode = ; }; vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <35440000>; regulator-initial-mode = ; }; vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = ; }; vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; }; From e788ef2bdac7fdbd61b626f65fdf7528a1c6fd3b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 11 Apr 2024 09:06:11 +0200 Subject: [PATCH 510/969] arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. On PCB level this is the signal from PM7250B (pin CC_OUT) which is called USB_PHY_PS. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240411-fp5-usb-c-gpio-v1-1-78f11deb940a@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 4ff9fc24e50e..f3432701945f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -77,6 +77,8 @@ #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + connector@0 { compatible = "usb-c-connector"; reg = <0>; From 254c101efde79ecf1264ba49be9cb9366542f150 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:11 +0300 Subject: [PATCH 511/969] dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios The orientation GPIOs are not limited to sm8450/sm8550/x1e8000 platforms. Allow corresponding property to be used on all Qualcom platforms. Fixes: 65682407f8f4 ("dt-bindings: soc: qcom: qcom,pmic-glink: add a gpio used to determine the Type-C port plug orientation") Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-1-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/soc/qcom/qcom,pmic-glink.yaml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 4310bae6c58e..4512390f90f0 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -58,20 +58,6 @@ patternProperties: required: - compatible -allOf: - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,sm8450-pmic-glink - - qcom,sm8550-pmic-glink - - qcom,x1e80100-pmic-glink - then: - properties: - orientation-gpios: false - additionalProperties: false examples: From defac2c098965534e36e257cf80712c54207d99b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:12 +0300 Subject: [PATCH 512/969] arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO Define the USB-C orientation GPIO so that the USB-C port orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-2-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index b43d264ed42b..4c25ab2f5670 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -42,6 +42,7 @@ compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From 70b47e7b764ce0c31ed81fdb483738e3d9135e22 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:13 +0300 Subject: [PATCH 513/969] arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO Define the USB-C orientation GPIO so that the USB-C port orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-3-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 0786cff07b89..3be46b56c723 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -95,6 +95,7 @@ compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From e34d83d968165841250cc4e780921f4bb33247d9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:14 +0300 Subject: [PATCH 514/969] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-4-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 15ae94c1602d..2806aa8ec497 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -100,6 +100,8 @@ #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From d2dbb1047e05d68b4f031fd50717cf3d2016268f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:15 +0300 Subject: [PATCH 515/969] arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-5-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6f2e1c732ed3..6af99116c715 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -51,6 +51,8 @@ #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>, + <&tlmm 58 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From bfff021ebf0beadc4fe8eeba252b35a188db2c6e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 3 Apr 2024 11:44:22 +0200 Subject: [PATCH 516/969] arm64: defconfig: qcom: enable X1E80100 sound card Enable the sound machine driver for Qualcomm X1E80100 sound card, used on several boards with X1E80100 (e.g. X1E80100 CRD). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240403094422.15140-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 546af6b8ce2c..9c5ecba12c37 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -951,6 +951,7 @@ CONFIG_SND_SOC_SM8250=m CONFIG_SND_SOC_SC8280XP=m CONFIG_SND_SOC_SC7180=m CONFIG_SND_SOC_SC7280=m +CONFIG_SND_SOC_X1E80100=m CONFIG_SND_SOC_ROCKCHIP=m CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m From 99a1c9eedf6098826c0f9dcbda2c23e5dad20244 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 17 Apr 2024 17:39:27 +0530 Subject: [PATCH 517/969] arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC. Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20240417120928.32344-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index ac6d741868ca..47ca2d000341 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -621,6 +621,26 @@ status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/modem.mbn"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcm6490/wpss.mbn"; + status = "okay"; +}; + &sdhc_1 { non-removable; no-sd; From ac6d35b9b74c113753bd266e01d6b853618a1e37 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 17 Apr 2024 17:39:28 +0530 Subject: [PATCH 518/969] arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs Enable the ADSP, CDSP and WPSS that are found on qcs6490-rb3gen2. Signed-off-by: Komal Bajaj Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240417120928.32344-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index c98c41f8f3b1..a085ff5b5fb2 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -17,7 +17,6 @@ #include "pmk8350.dtsi" /delete-node/ &ipa_fw_mem; -/delete-node/ &remoteproc_mpss; /delete-node/ &rmtfs_mem; /delete-node/ &adsp_mem; /delete-node/ &cdsp_mem; @@ -617,6 +616,16 @@ status = "okay"; }; +&remoteproc_mpss { + firmware-name = "qcom/qcs6490/modem.mdt"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcs6490/wpss.mbn"; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From 77706838f837785189578bd8fd768e646e63f8c2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 10 Apr 2024 20:45:22 +0200 Subject: [PATCH 519/969] soc: qcom: mention intentionally broken module autoloading Qualcomm PMIC ChargerPD ULOG and RPM Master Statistics drivers are solely for debugging purposes and should not be autoloaded as modules. Add comments to annotate missing MODULE_DEVICE_TABLE. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240410184522.271889-1-krzk@kernel.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_pdcharger_ulog.c | 4 ++++ drivers/soc/qcom/rpm_master_stats.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/soc/qcom/pmic_pdcharger_ulog.c b/drivers/soc/qcom/pmic_pdcharger_ulog.c index 238cd38589dc..39f412bbf2c1 100644 --- a/drivers/soc/qcom/pmic_pdcharger_ulog.c +++ b/drivers/soc/qcom/pmic_pdcharger_ulog.c @@ -150,6 +150,10 @@ static const struct rpmsg_device_id pmic_pdcharger_ulog_rpmsg_id_match[] = { { "PMIC_LOGS_ADSP_APPS" }, {} }; +/* + * No MODULE_DEVICE_TABLE intentionally: that's a debugging module, to be + * loaded manually only. + */ static struct rpmsg_driver pmic_pdcharger_ulog_rpmsg_driver = { .probe = pmic_pdcharger_ulog_rpmsg_probe, diff --git a/drivers/soc/qcom/rpm_master_stats.c b/drivers/soc/qcom/rpm_master_stats.c index 9ca13bcf67d3..086fe4ba6707 100644 --- a/drivers/soc/qcom/rpm_master_stats.c +++ b/drivers/soc/qcom/rpm_master_stats.c @@ -148,6 +148,10 @@ static const struct of_device_id rpm_master_table[] = { { .compatible = "qcom,rpm-master-stats" }, { }, }; +/* + * No MODULE_DEVICE_TABLE intentionally: that's a debugging module, to be + * loaded manually only. + */ static struct platform_driver master_stats_driver = { .probe = master_stats_probe, From 635ce0db89567ba62f64b79e8c6664ba3eff6516 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Apr 2024 06:10:57 +0300 Subject: [PATCH 520/969] soc: qcom: pmic_glink: don't traverse clients list without a lock Take the client_lock before traversing the clients list at the pmic_glink_state_notify_clients() function. This is required to keep the list traversal safe from concurrent modification. Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Signed-off-by: Dmitry Baryshkov Reviewed-by: Andrew Halaney Reviewed-by: Mukesh Ojha Tested-by: Xilin Wu # on QCS8550 AYN Odin 2 Link: https://lore.kernel.org/r/20240403-pmic-glink-fix-clients-v2-1-aed4e02baacc@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index f913e9bd57ed..2b2cdf479654 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -115,10 +115,12 @@ static int pmic_glink_rpmsg_callback(struct rpmsg_device *rpdev, void *data, hdr = data; + mutex_lock(&pg->client_lock); list_for_each_entry(client, &pg->clients, node) { if (client->id == le32_to_cpu(hdr->owner)) client->cb(data, len, client->priv); } + mutex_unlock(&pg->client_lock); return 0; } @@ -168,8 +170,10 @@ static void pmic_glink_state_notify_clients(struct pmic_glink *pg) } if (new_state != pg->client_state) { + mutex_lock(&pg->client_lock); list_for_each_entry(client, &pg->clients, node) client->pdr_notify(client->priv, new_state); + mutex_unlock(&pg->client_lock); pg->client_state = new_state; } } From d6cbce2cd354c9a37a558f290a8f1dfd20584f99 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Apr 2024 06:10:58 +0300 Subject: [PATCH 521/969] soc: qcom: pmic_glink: notify clients about the current state In case the client is registered after the pmic-glink recived a response from the Protection Domain mapper, it is going to miss the notification about the state. Notify clients about the current state upon registration. Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Reviewed-by: Andrew Halaney Signed-off-by: Dmitry Baryshkov Reviewed-by: Mukesh Ojha Tested-by: Xilin Wu # on QCS8550 AYN Odin 2 Link: https://lore.kernel.org/r/20240403-pmic-glink-fix-clients-v2-2-aed4e02baacc@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 2b2cdf479654..e85a12ec2aab 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -83,9 +83,14 @@ struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, client->pdr_notify = pdr; client->priv = priv; + mutex_lock(&pg->state_lock); mutex_lock(&pg->client_lock); + list_add(&client->node, &pg->clients); + client->pdr_notify(client->priv, pg->client_state); + mutex_unlock(&pg->client_lock); + mutex_unlock(&pg->state_lock); devres_add(dev, client); From 62f87a3cac4e70fa916914a359d3f045a5ad8b9b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 29 Mar 2024 08:45:56 +0100 Subject: [PATCH 522/969] arm64: dts: qcom: sm6350: Add DisplayPort controller Add the node for the DisplayPort controller found on the SM6350 SoC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 88 ++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 4864bd33e448..ad704f4e147c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2064,6 +2064,14 @@ remote-endpoint = <&mdss_dsi0_in>; }; }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2101,6 +2109,86 @@ }; }; + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; From 6754fecd3bdf82cbd6eedefeb0cdb7e86aac2208 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Mar 2024 11:29:24 +0100 Subject: [PATCH 523/969] arm64: dts: qcom: sdx75: add unit address to soc node Soc node has ranges, thus it must have an unit address. This fixes W=1 dtc warning: sdx75.dtsi:399.11-736.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240325102924.26820-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7dbdf8ca6de6..f58da999a72d 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -411,7 +411,7 @@ hwlocks = <&tcsr_mutex 3>; }; - soc: soc { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From 6aeeb9456943ce166211231f72e8723731ad116b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 25 Mar 2024 09:34:33 +0100 Subject: [PATCH 524/969] arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp The MDP/DPU device is not disabled by default, so there is not point in enabling it in the board DTS file. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240325-topic-sm8x50-upstream-leave-mdss-enabled-by-default-v1-1-f1b380132075@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 4450273f9667..d04ceaa73c2b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -641,10 +641,6 @@ status = "okay"; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..e0e4587f08c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -827,10 +827,6 @@ remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; From 0a8ab4a834507fd5432168ddda7fd3f9eab239f0 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Sat, 23 Mar 2024 18:04:43 +0800 Subject: [PATCH 525/969] arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp Fix the dtb check warnings: sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-min-microamp' is a required property sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-max-microamp' is a required property Fixes: 69652787279d ("arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg") Signed-off-by: Jianhua Lu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240323100443.2478-1-lujianhua000@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 2042020eb0dd..41f117474872 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -668,6 +668,8 @@ }; &pm8150b_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; status = "okay"; }; From 3de990f7895906a7a18d2dff63e3e525acaa4ecc Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 21 Mar 2024 20:53:59 +0530 Subject: [PATCH 526/969] firmware: qcom: scm: Remove log reporting memory allocation failure Remove redundant memory allocation failure. WARNING: Possible unnecessary 'out of memory' message + if (!mdata_buf) { + dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); Signed-off-by: Mukesh Ojha Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1711034642-22860-1-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 81c15aeff934..137bda5a0a63 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -554,10 +554,9 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, */ mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, GFP_KERNEL); - if (!mdata_buf) { - dev_err(__scm->dev, "Allocation of metadata buffer failed.\n"); + if (!mdata_buf) return -ENOMEM; - } + memcpy(mdata_buf, metadata, size); ret = qcom_scm_clk_enable(); From 000636d91d605f6209a635a29d0487af5b12b237 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 21 Mar 2024 20:54:00 +0530 Subject: [PATCH 527/969] firmware: qcom: scm: Remove redundant scm argument from qcom_scm_waitq_wakeup() Remove redundant scm argument from qcom_scm_waitq_wakeup(). Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1711034642-22860-2-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 137bda5a0a63..d32fae53be1c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1771,7 +1771,7 @@ int qcom_scm_wait_for_wq_completion(u32 wq_ctx) return 0; } -static int qcom_scm_waitq_wakeup(struct qcom_scm *scm, unsigned int wq_ctx) +static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { int ret; @@ -1803,7 +1803,7 @@ static irqreturn_t qcom_scm_irq_handler(int irq, void *data) goto out; } - ret = qcom_scm_waitq_wakeup(scm, wq_ctx); + ret = qcom_scm_waitq_wakeup(wq_ctx); if (ret) goto out; } while (more_pending); From 398a4c58f3f29ac3ff4d777dc91fe40a07bbca8c Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 21 Mar 2024 20:54:01 +0530 Subject: [PATCH 528/969] firmware: qcom: scm: Rework dload mode availability check QCOM_SCM_BOOT_SET_DLOAD_MODE scm command is applicable for very older SoCs where this command is supported from firmware and for newer SoCs, dload mode tcsr registers is used for setting the download mode. Currently, qcom_scm_set_download_mode() checks for availability of QCOM_SCM_BOOT_SET_DLOAD_MODE command even for SoCs where this is not used. Fix this by switching the condition to keep the command availability check only if dload mode registers are not available. Signed-off-by: Mukesh Ojha Reviewed-by: Elliot Berman Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1711034642-22860-3-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index d32fae53be1c..d9cee441d81c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -495,17 +495,14 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) static void qcom_scm_set_download_mode(bool enable) { - bool avail; int ret = 0; - avail = __qcom_scm_is_call_available(__scm->dev, - QCOM_SCM_SVC_BOOT, - QCOM_SCM_BOOT_SET_DLOAD_MODE); - if (avail) { - ret = __qcom_scm_set_dload_mode(__scm->dev, enable); - } else if (__scm->dload_mode_addr) { + if (__scm->dload_mode_addr) { ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + } else if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_BOOT, + QCOM_SCM_BOOT_SET_DLOAD_MODE)) { + ret = __qcom_scm_set_dload_mode(__scm->dev, enable); } else { dev_err(__scm->dev, "No available mechanism for setting download mode\n"); From 2e4955167ec5c04534cebea9e8273a907e7a75e1 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 21 Mar 2024 20:54:02 +0530 Subject: [PATCH 529/969] firmware: qcom: scm: Fix __scm and waitq completion variable initialization It is possible qcom_scm_is_available() gives wrong indication that if __scm is initialized while __scm->dev is not and similar issue is also possible with __scm->waitq_comp. Fix this appropriately by the use of release barrier and read barrier that will make sure if __scm is initialized so, is all of its field variable. Fixes: d0f6fa7ba2d6 ("firmware: qcom: scm: Convert SCM to platform driver") Fixes: 6bf325992236 ("firmware: qcom: scm: Add wait-queue handling logic") Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/1711034642-22860-4-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index d9cee441d81c..84aa30b5a19e 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1737,7 +1737,7 @@ static int qcom_scm_qseecom_init(struct qcom_scm *scm) */ bool qcom_scm_is_available(void) { - return !!__scm; + return !!READ_ONCE(__scm); } EXPORT_SYMBOL_GPL(qcom_scm_is_available); @@ -1818,10 +1818,12 @@ static int qcom_scm_probe(struct platform_device *pdev) if (!scm) return -ENOMEM; + scm->dev = &pdev->dev; ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr); if (ret < 0) return ret; + init_completion(&scm->waitq_comp); mutex_init(&scm->scm_bw_lock); scm->path = devm_of_icc_get(&pdev->dev, NULL); @@ -1853,10 +1855,8 @@ static int qcom_scm_probe(struct platform_device *pdev) if (ret) return ret; - __scm = scm; - __scm->dev = &pdev->dev; - - init_completion(&__scm->waitq_comp); + /* Let all above stores be available after this */ + smp_store_release(&__scm, scm); irq = platform_get_irq_optional(pdev, 0); if (irq < 0) { From b9718298e028f9edbe0fcdf48c02a1c355409410 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 21 Mar 2024 23:07:35 +0530 Subject: [PATCH 530/969] firmware: qcom: scm: Modify only the download bits in TCSR register Crashdump collection is done based on DLOAD bits of TCSR register. To retain other bits, scm driver need to read the register and modify only the DLOAD bits, as other bits in TCSR may have their own significance. Co-developed-by: Poovendhan Selvaraj Signed-off-by: Poovendhan Selvaraj Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 Reviewed-by: Dmitry Baryshkov Reviewed-by: Elliot Berman Link: https://lore.kernel.org/r/1711042655-31948-1-git-send-email-quic_mojha@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 84aa30b5a19e..5ff62f57aa55 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -114,6 +116,10 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { #define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0) #define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1) +#define QCOM_DLOAD_MASK GENMASK(5, 4) +#define QCOM_DLOAD_NODUMP 0 +#define QCOM_DLOAD_FULLDUMP 1 + static const char * const qcom_scm_convention_names[] = { [SMC_CONVENTION_UNKNOWN] = "unknown", [SMC_CONVENTION_ARM_32] = "smc arm 32", @@ -493,13 +499,29 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) return qcom_scm_call_atomic(__scm->dev, &desc, NULL); } +static int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val) +{ + unsigned int old; + unsigned int new; + int ret; + + ret = qcom_scm_io_readl(addr, &old); + if (ret) + return ret; + + new = (old & ~mask) | (val & mask); + + return qcom_scm_io_writel(addr, new); +} + static void qcom_scm_set_download_mode(bool enable) { + u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP; int ret = 0; if (__scm->dload_mode_addr) { - ret = qcom_scm_io_writel(__scm->dload_mode_addr, - enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0); + ret = qcom_scm_io_rmw(__scm->dload_mode_addr, QCOM_DLOAD_MASK, + FIELD_PREP(QCOM_DLOAD_MASK, val)); } else if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE)) { ret = __qcom_scm_set_dload_mode(__scm->dev, enable); From f592cc5794747b81e53b53dd6e80219ee25f0611 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 15 Feb 2024 10:55:44 +0530 Subject: [PATCH 531/969] soc: qcom: rpmh-rsc: Enhance check for VRM in-flight request Each RPMh VRM accelerator resource has 3 or 4 contiguous 4-byte aligned addresses associated with it. These control voltage, enable state, mode, and in legacy targets, voltage headroom. The current in-flight request checking logic looks for exact address matches. Requests for different addresses of the same RPMh resource as thus not detected as in-flight. Add new cmd-db API cmd_db_match_resource_addr() to enhance the in-flight request check for VRM requests by ignoring the address offset. This ensures that only one request is allowed to be in-flight for a given VRM resource. This is needed to avoid scenarios where request commands are carried out by RPMh hardware out-of-order leading to LDO regulator over-current protection triggering. Fixes: 658628e7ef78 ("drivers: qcom: rpmh-rsc: add RPMH controller for QCOM SoCs") Cc: stable@vger.kernel.org Reviewed-by: Konrad Dybcio Tested-by: Elliot Berman # sm8650-qrd Signed-off-by: Maulik Shah Link: https://lore.kernel.org/r/20240215-rpmh-rsc-fixes-v4-1-9cbddfcba05b@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/cmd-db.c | 32 +++++++++++++++++++++++++++++++- drivers/soc/qcom/rpmh-rsc.c | 3 ++- include/soc/qcom/cmd-db.h | 10 +++++++++- 3 files changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index c344107bc36c..b4e613c34a5c 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -1,6 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved. */ +/* + * Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include #include #include #include @@ -17,6 +21,8 @@ #define MAX_SLV_ID 8 #define SLAVE_ID_MASK 0x7 #define SLAVE_ID_SHIFT 16 +#define SLAVE_ID(addr) FIELD_GET(GENMASK(19, 16), addr) +#define VRM_ADDR(addr) FIELD_GET(GENMASK(19, 4), addr) /** * struct entry_header: header for each entry in cmddb @@ -220,6 +226,30 @@ const void *cmd_db_read_aux_data(const char *id, size_t *len) } EXPORT_SYMBOL_GPL(cmd_db_read_aux_data); +/** + * cmd_db_match_resource_addr() - Compare if both Resource addresses are same + * + * @addr1: Resource address to compare + * @addr2: Resource address to compare + * + * Return: true if two addresses refer to the same resource, false otherwise + */ +bool cmd_db_match_resource_addr(u32 addr1, u32 addr2) +{ + /* + * Each RPMh VRM accelerator resource has 3 or 4 contiguous 4-byte + * aligned addresses associated with it. Ignore the offset to check + * for VRM requests. + */ + if (addr1 == addr2) + return true; + else if (SLAVE_ID(addr1) == CMD_DB_HW_VRM && VRM_ADDR(addr1) == VRM_ADDR(addr2)) + return true; + + return false; +} +EXPORT_SYMBOL_GPL(cmd_db_match_resource_addr); + /** * cmd_db_read_slave_id - Get the slave ID for a given resource address * diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index c4c7aad957e6..561d8037b50a 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "%s " fmt, KBUILD_MODNAME @@ -557,7 +558,7 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs, for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) { addr = read_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], i, j); for (k = 0; k < msg->num_cmds; k++) { - if (addr == msg->cmds[k].addr) + if (cmd_db_match_resource_addr(msg->cmds[k].addr, addr)) return -EBUSY; } } diff --git a/include/soc/qcom/cmd-db.h b/include/soc/qcom/cmd-db.h index c8bb56e6852a..47a6cab75e63 100644 --- a/include/soc/qcom/cmd-db.h +++ b/include/soc/qcom/cmd-db.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ #ifndef __QCOM_COMMAND_DB_H__ #define __QCOM_COMMAND_DB_H__ @@ -21,6 +24,8 @@ u32 cmd_db_read_addr(const char *resource_id); const void *cmd_db_read_aux_data(const char *resource_id, size_t *len); +bool cmd_db_match_resource_addr(u32 addr1, u32 addr2); + enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id); int cmd_db_ready(void); @@ -31,6 +36,9 @@ static inline u32 cmd_db_read_addr(const char *resource_id) static inline const void *cmd_db_read_aux_data(const char *resource_id, size_t *len) { return ERR_PTR(-ENODEV); } +static inline bool cmd_db_match_resource_addr(u32 addr1, u32 addr2) +{ return false; } + static inline enum cmd_db_hw_type cmd_db_read_slave_id(const char *resource_id) { return -ENODEV; } From 7c4b3191b3cdb01f69bb5c1323fe67e018e7b9f9 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Thu, 15 Feb 2024 12:26:17 +0000 Subject: [PATCH 532/969] arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used for RT5033 charger. Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240215122605.3817-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 2937495940ea..4bbbee80b5e4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -128,6 +128,12 @@ pinctrl-names = "default"; pinctrl-0 = <&muic_int_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index 3c49dac92d2d..c50f81a68897 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -23,6 +23,12 @@ pinctrl-names = "default"; pinctrl-0 = <&muic_int_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index aa6c39482a2f..0c599e71a464 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -286,6 +286,12 @@ pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; From 11525960fcf40fcb772b62dd5117c59fdc27eb57 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Wed, 6 Mar 2024 20:27:10 +0300 Subject: [PATCH 533/969] arm64: dts: qcom: pm6150l: add Light Pulse Generator device node Add device node defining LPG/PWM block on PM6150L PMIC chip. Signed-off-by: Danila Tikhonov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306172710.59780-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index d13a1ab7c20b..0fce45276e5c 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -118,6 +118,16 @@ status = "disabled"; }; + pm6150l_lpg: pwm { + compatible = "qcom,pm6150l-lpg", "qcom,pm8150l-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; From db33633b05c0b57aef197f072826127f65f59ee9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 18 Mar 2024 11:09:45 +0100 Subject: [PATCH 534/969] arm64: dts: qcom: sm8650: add GPU nodes Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Acked-by: Jun Nie Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-1-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 181 +++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index fc057ea41d56..3d69e13ce87b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2591,6 +2591,143 @@ #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-level = ; + }; + + opp-770000000 { + opp-hz = /bits/ 64 <770000000>; + opp-level = ; + }; + + opp-834000000 { + opp-hz = /bits/ 64 <834000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2604,6 +2741,50 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From b8cf87ca7827388ed8d817fadec7ea65aef2a172 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 18 Mar 2024 11:09:46 +0100 Subject: [PATCH 535/969] arm64: dts: qcom: sm8650-qrd: enable GPU Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Reviewed-by: Jun Nie Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-2-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index e0e4587f08c4..4e94f7fe4d2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21"; From dae8cdb0a9e18f0cc7bda75e42d0da750e05ca77 Mon Sep 17 00:00:00 2001 From: Ling Xu Date: Tue, 19 Mar 2024 08:58:16 +0530 Subject: [PATCH 536/969] arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes Add three missing cDSP fastrpc compute-cb nodes for the SM8650 SoC. Signed-off-by: Ling Xu Link: https://lore.kernel.org/r/20240319032816.27070-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 3d69e13ce87b..89d6424a2b05 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5271,6 +5271,38 @@ <&apps_smmu 0x19c8 0x0>; dma-coherent; }; + + /* note: secure cb9 in downstream */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c0c 0x20>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x20>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + + iommus = <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x0c0e 0x20>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; }; }; }; From 365e19c466a57ff17093cf6e9f8ad362dd122602 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 19 Mar 2024 16:23:33 +0100 Subject: [PATCH 537/969] arm64: dts: qcom: sc8280xp: Fill in EAS properties Replace the bogus capacity-dmips-mhz values and add the measured dynamic-power-coefficient values. The power numbers were measured by matters much more precise than the laggy and cache-y pmic_glink battery data, though the reported values were only accurate to 10mA. But that shouldn't be an issue, especially for the fat and power-hungry X1Cs and given that *each SoC unit* has somewhat different frequency-voltage maps. X1C cluster: 940 kHz, 596 mV, 434 mW, 663 Cx 1056 kHz, 612 mV, 463 mW, 565 Cx 1171 kHz, 628 mV, 502 mW, 574 Cx 1286 kHz, 644 mV, 534 mW, 540 Cx 1401 kHz, 660 mV, 580 mW, 550 Cx 1516 kHz, 688 mV, 630 mW, 529 Cx 1632 kHz, 712 mV, 690 mW, 533 Cx 1747 kHz, 728 mV, 722 mW, 503 Cx 1862 kHz, 752 mV, 787 mW, 504 Cx 1977 kHz, 776 mV, 855 mW, 503 Cx 2073 kHz, 792 mV, 913 mW, 504 Cx 2169 kHz, 812 mV, 989 mW, 514 Cx 2284 kHz, 856 mV, 1250 mW, 611 Cx 2400 kHz, 900 mV, 1441 mW, 626 Cx 2496 kHz, 932 mV, 1600 mW, 636 Cx 2592 kHz, 964 mV, 1790 mW, 653 Cx 2688 kHz, 1000 mV, 2020 mW, 673 Cx 2803 kHz, 1040 mV, 2292 mW, 687 Cx 2899 kHz, 1076 mV, 2572 mW, 706 Cx 2995 kHz, 1108 mV, 2850 mW, 721 Cx A78C cluster: 403 kHz, 576 mV, 180 mW, 584 Cx 499 kHz, 576 mV, 200 mW, 605 Cx 595 kHz, 576 mV, 220 mW, 612 Cx 691 kHz, 576 mV, 230 mW, 541 Cx 806 kHz, 600 mV, 250 mW, 471 Cx 902 kHz, 620 mV, 270 mW, 444 Cx 1017 kHz, 640 mV, 290 mW, 409 Cx 1113 kHz, 652 mV, 310 mW, 401 Cx 1209 kHz, 668 mV, 320 mW, 363 Cx 1324 kHz, 700 mV, 490 mW, 600 Cx 1440 kHz, 724 mV, 523 mW, 554 Cx 1555 kHz, 800 mV, 660 mW, 558 Cx 1670 kHz, 800 mV, 780 mW, 639 Cx 1785 kHz, 804 mV, 910 mW, 711 Cx 1881 kHz, 824 mV, 941 mW, 663 Cx 1996 kHz, 856 mV, 980 mW, 601 Cx 2112 kHz, 880 mV, 1020 mW, 559 Cx 2227 kHz, 908 mV, 1090 mW, 535 Cx 2342 kHz, 932 mV, 1230 mW, 552 Cx 2438 kHz, 956 mV, 1351 mW, 559 Cx Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240319-topic-8280_eas-v1-1-c605b4ea063d@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 75fa7ac5b60a..4c77f69a24a7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -50,7 +50,8 @@ reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -77,7 +78,8 @@ reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -99,7 +101,8 @@ reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -121,7 +124,8 @@ reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -144,6 +148,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; @@ -166,6 +171,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; @@ -188,6 +194,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; @@ -210,6 +217,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; From 166db01007ea802ff9933ac73ec8f140ca0cf5d5 Mon Sep 17 00:00:00 2001 From: Justin Stitt Date: Tue, 19 Mar 2024 21:19:59 +0000 Subject: [PATCH 538/969] soc: qcom: cmd-db: replace deprecated strncpy with strtomem strncpy() is an ambiguous and potentially dangerous interface [1]. We should prefer more robust and less ambiguous alternatives. @query is marked as __nonstring and doesn't need to be NUL-terminated. Since we are doing a string to memory copy, we can use the aptly named "strtomem" -- specifically, the "pad" variant to also ensure NUL-padding throughout the destination buffer. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#strncpy-on-nul-terminated-strings [1] Link: https://manpages.debian.org/testing/linux-manual-4.8/strscpy.9.en.html [2] Link: https://github.com/KSPP/linux/issues/90 Cc: linux-hardening@vger.kernel.org Reviewed-by: Kees Cook Signed-off-by: Justin Stitt Link: https://lore.kernel.org/r/20240319-strncpy-drivers-soc-qcom-cmd-db-c-v3-1-aeb5c5180c32@google.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/cmd-db.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index b4e613c34a5c..d84572662017 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -153,12 +153,7 @@ static int cmd_db_get_header(const char *id, const struct entry_header **eh, if (ret) return ret; - /* - * Pad out query string to same length as in DB. NOTE: the output - * query string is not necessarily '\0' terminated if it bumps up - * against the max size. That's OK and expected. - */ - strncpy(query, id, sizeof(query)); + strtomem_pad(query, id, 0); for (i = 0; i < MAX_SLV_ID; i++) { rsc_hdr = &cmd_db_header->header[i]; From 17a188d927f772663f8929bd5f2a990004af5917 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Thu, 21 Mar 2024 11:58:34 +0530 Subject: [PATCH 539/969] arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform Update SNPS Phy tuning parameters for sm8450 QRD platform to fix electrical compliance failures. Signed-off-by: Udipto Goswami Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321062834.21510-1-quic_ugoswami@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index c7d05945aa51..7b62ead68e77 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -467,6 +467,14 @@ vdda-pll-supply = <&vreg_l5b_0p88>; vdda18-supply = <&vreg_l1c_1p8>; vdda33-supply = <&vreg_l2b_3p07>; + qcom,squelch-detector-bp = <(-2090)>; + qcom,hs-disconnect-bp = <1743>; + qcom,pre-emphasis-amplitude-bp = <40000>; + qcom,pre-emphasis-duration-bp = <20000>; + qcom,hs-amplitude-bp = <2000>; + qcom,hs-output-impedance-micro-ohms = <2600000>; + qcom,hs-crossover-voltage-microvolt = <(-31000)>; + qcom,hs-rise-fall-time-bp = <(-4100)>; }; &usb_1_qmpphy { From 0c4d19b125401957123989a25094972cf0e77670 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:37 +0530 Subject: [PATCH 540/969] ARM: dts: qcom: ipq8064: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-17-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 2eb6758b6a3a..f128510d8445 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -1121,6 +1121,16 @@ status = "disabled"; perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1: pcie@1b700000 { @@ -1172,6 +1182,16 @@ status = "disabled"; perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@1b900000 { @@ -1223,6 +1243,16 @@ status = "disabled"; perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; qsgmii_csr: syscon@1bb00000 { From ed9b196418d4e2fa4f6c27b61a92c2038e1ba04d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:38 +0530 Subject: [PATCH 541/969] ARM: dts: qcom: ipq4019: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-18-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index b198e2af5158..0fb65f2bbcdf 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -470,6 +470,16 @@ "phy_ahb"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; qpic_bam: dma-controller@7984000 { From 27cb9eccf94cb163f9bf3b945f249ab7c42861db Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:39 +0530 Subject: [PATCH 542/969] ARM: dts: qcom: apq8064: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-19-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index c428a5c16c65..11e60b74c3c9 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -1334,6 +1334,16 @@ <&gcc PCIE_PHY_RESET>; reset-names = "axi", "ahb", "por", "pci", "phy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; hdmi: hdmi-tx@4a00000 { From 669841a2eff4c0132841dea3ae40d9148a36f257 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:40 +0530 Subject: [PATCH 543/969] ARM: dts: qcom: sdx55: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-20-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index edc9aaf828c8..68fa5859d263 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -378,6 +378,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_ep: pcie-ep@1c00000 { From d73ed58d7f2793df161d0afb66afab3d1b862945 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Wed, 20 Mar 2024 12:25:11 +0000 Subject: [PATCH 544/969] arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on This regulator is responsible not just for the PCIe 3.3v rail, but also for 5v VBUS on the left USB port. There is currently no way to correctly model this dependency on the USB controller, as a result when the PCIe driver is not available (for example when in the initramfs) USB is non-functional. Until support is added for modelling this property (likely by referencing it as a supply under a usb-connector node), let's just make it always on. We don't target any power constrained usecases and this regulator is required for USB to function correctly. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Suggested-by: Bjorn Andersson Signed-off-by: Caleb Connolly Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240320122515.3243711-1-caleb.connolly@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 1f517328199b..9a6d3d0c0ee4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -195,6 +195,12 @@ gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; enable-active-high; + /* + * FIXME: this regulator is responsible for VBUS on the left USB + * port. Keep it always on until we can correctly model this + * relationship. + */ + regulator-always-on; pinctrl-names = "default"; pinctrl-0 = <&pcie0_pwren_state>; From 83d2a0a1e2b9fe1032630e0e560dee6ddd89d942 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:21 +0530 Subject: [PATCH 545/969] arm64: dts: qcom: sm8250: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-1-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 39bd8f0eba1e..fe5485256b22 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2203,6 +2203,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2318,6 +2328,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2433,6 +2453,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c16000 { From b8347ba382ef334aeff256892229c0d6f818fd53 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:22 +0530 Subject: [PATCH 546/969] arm64: dts: qcom: sdm845: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-2-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f20be99ee7e..10de2bd46ffc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2375,6 +2375,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2479,6 +2489,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0a000 { From 8e0a95add7e3f3838d5b494ce645c48759ba4168 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:23 +0530 Subject: [PATCH 547/969] arm64: dts: qcom: sm8150: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-3-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a35c0852b5a1..ff22e4346660 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1901,6 +1901,16 @@ pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2011,6 +2021,16 @@ pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From 3b743d532eac3cd1ab8fb21e8bf0390715237d8b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:24 +0530 Subject: [PATCH 548/969] arm64: dts: qcom: sm8350: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a878f5ac5bb5..f7c4700f00c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1573,6 +1573,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1670,6 +1680,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From 4261fd53582df00dc7d3a384a552c35d76ab0ace Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:25 +0530 Subject: [PATCH 549/969] arm64: dts: qcom: sm8450: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 92b052f7b20e..7f32035aab7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1850,6 +1850,16 @@ pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1971,6 +1981,16 @@ pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From cc2ad77882fb9ff54d9f626df73057558dcd8322 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:26 +0530 Subject: [PATCH 550/969] arm64: dts: qcom: sm8550: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-6-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5adb9b178b05..171fdb213cd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1774,6 +1774,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1887,6 +1897,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From cf3e010d7f4c20d3a82fb07feb937fd771cb1b53 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:27 +0530 Subject: [PATCH 551/969] arm64: dts: qcom: sm8650: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-7-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 89d6424a2b05..434ad2f12332 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2294,6 +2294,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2422,6 +2432,16 @@ <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From 3c3abb944d3ecce10738c73c94b300974da7b81b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:28 +0530 Subject: [PATCH 552/969] arm64: dts: qcom: sa8775p: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 231cea1f0fa8..31de73594839 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3677,6 +3677,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c04000 { @@ -3777,6 +3787,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c14000 { From e6bbf39055e347e486cbb0820f2a50a27dbf5a08 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:29 +0530 Subject: [PATCH 553/969] arm64: dts: qcom: sc8280xp: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, let's remove the bridge properties from board dts as they are now redundant. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +++----- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 50 +++++++++++++++++++ 2 files changed, 56 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 2806aa8ec497..f325066e24d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -733,22 +733,14 @@ pinctrl-0 = <&pcie4_default>; status = "okay"; +}; - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - wifi@0 { - compatible = "pci17cb,1103"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - qcom,ath11k-calibration-variant = "LE_X13S"; - }; + qcom,ath11k-calibration-variant = "LE_X13S"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 4c77f69a24a7..0403811264d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1803,6 +1803,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c06000 { @@ -1904,6 +1914,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3b_phy: phy@1c0e000 { @@ -2005,6 +2025,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3a_phy: phy@1c14000 { @@ -2109,6 +2139,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie2b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2b_phy: phy@1c1e000 { @@ -2210,6 +2250,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie2a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2a_phy: phy@1c24000 { From b328bf2595db3bdba87df52ca1a9db431ee99c34 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:30 +0530 Subject: [PATCH 554/969] arm64: dts: qcom: msm8998: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-10-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 4dfe2d09ac28..d795b2bbe133 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -972,6 +972,16 @@ power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_phy: phy@1c06000 { From df307c906c48d1c8c6ffb9022907bfb6cb041da6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:31 +0530 Subject: [PATCH 555/969] arm64: dts: qcom: sc7280: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-11-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bd9b1898d7a7..cea294a4ecfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2273,6 +2273,16 @@ <0x100 &apps_smmu 0x1c81 0x1>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From ed2f87cf51b4ffab1585553b798773c9131efa6e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:32 +0530 Subject: [PATCH 556/969] arm64: dts: qcom: qcs404: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-12-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a05d0234f7fc..ac451f378056 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1516,6 +1516,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From a92af45c40f06b651f0773bf7ffb3d77c7a467f1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:33 +0530 Subject: [PATCH 557/969] arm64: dts: qcom: sc8180x: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-13-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 019104bd70fb..6d5878f3b26d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1777,6 +1777,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1888,6 +1898,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1c0c000 { @@ -2000,6 +2020,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c16000 { @@ -2112,6 +2142,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c1c000 { From 71756c44f178d91bf021b51e72e111f96c715d14 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:34 +0530 Subject: [PATCH 558/969] arm64: dts: qcom: msm8996: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-14-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1601e46549e7..8d2cb6f41095 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1929,6 +1929,16 @@ "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1: pcie@608000 { @@ -1982,6 +1992,16 @@ "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@610000 { @@ -2032,6 +2052,16 @@ "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From ed3893f6f9b800ca774f63810c5f8838bc7cee78 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:35 +0530 Subject: [PATCH 559/969] arm64: dts: qcom: ipq8074: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index bed405559866..5d42de829e75 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -883,6 +883,16 @@ "ahb", "axi_m_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0: pcie@20000000 { @@ -948,6 +958,16 @@ "axi_m_sticky", "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From 52358c64937e982d3cdcf64be58f08f30d8e518c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:36 +0530 Subject: [PATCH 560/969] arm64: dts: qcom: ipq6018: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e29adea570a..17ab6c475958 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -907,6 +907,16 @@ "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From 8ee9a40d05641acb3db0250c1392e008e11753cb Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 18 Apr 2024 11:49:41 +0100 Subject: [PATCH 561/969] dt-bindings: arm: sunxi: document Tanix TX1 name The Tanix TX1 is a tiny TV box with the Allwinner H313 SoC, a lower bin version of the Allwinner H616. It comes with no SD card slot or Ethernet port. Add the board/SoC compatible string pair to the list of known boards. Since the H313 does not look different from a software point of view, we keep the H616 compatible string. Signed-off-by: Andre Przywara Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240418104942.1556914-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 43491e7f8a5e..f465f3a59c80 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -865,6 +865,11 @@ properties: - const: allwinner,sl631 - const: allwinner,sun8i-v3 + - description: Tanix TX1 + items: + - const: oranth,tanix-tx1 + - const: allwinner,sun50i-h616 + - description: Tanix TX6 items: - const: oranth,tanix-tx6 From 04a9963b4aa5f1f0b7714a28471e0c67ee0d864c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 18 Apr 2024 11:49:42 +0100 Subject: [PATCH 562/969] arm64: dts: allwinner: Add Tanix TX1 support The Tanix TX1 is a tiny TV box with the Allwinner H313 SoC. The box features no Ethernet or an SD card slot, which makes booting from it somewhat interesting: Pressing the hidden FEL button and using a USB-A to USB-A cable to upload code from a host PC is one way to run mainline. The box features: - Allwinner H313 SoC (4 * Arm Cortex-A53 cores) - 1 or 2 GB DRAM - 8 or 16 GB eMMC flash - SCI S9082H WiFi chip - HDMI port - one USB 2.0 port - 3.5mm AV port - barrel plug 5V DC input via barrel plug The devicetree covers most peripherals. The eMMC did not work properly in HS200 speed mode, so this mode property is omitted. HS-DDR seems to work fine. The blue LED is connected to the same GPIO pin as the red LED, just using the opposite polarity. Apparently there is no way of describing this in DT, so the red LED is omitted. Next to the FEL button is a hidden button, that can be pushed by using something like a paperclip, through the ventilation vents of the case. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240418104942.1556914-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun50i-h313-tanix-tx1.dts | 183 ++++++++++++++++++ 2 files changed, 184 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 21149b346a60..c571971f2fac 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts new file mode 100644 index 000000000000..bb2cde59bd03 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-tanix-tx1.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include +#include + +/ { + model = "Tanix TX1"; + compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + ethernet0 = &sdio_wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "hidden"; + linux,code = ; + gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + default-state = "on"; + }; + }; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + max-frequency = <100000000>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1120000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; /* USB A type receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From eff12fdfd208ebf35b82d6df72285508f85dcea8 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 11 Apr 2024 10:03:28 +0200 Subject: [PATCH 563/969] arm64: defconfig: enable ext4 security labels Enable ext4 security labels so that setcap works as expected. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20240411080328.9230-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9c5ecba12c37..254198352f37 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1605,6 +1605,7 @@ CONFIG_HTE_TEGRA194=y CONFIG_HTE_TEGRA194_TEST=m CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_FANOTIFY=y From 886776ca23f2433eb69c0f95e0abadb7dfffd789 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 11 Apr 2024 20:21:35 +0800 Subject: [PATCH 564/969] riscv: dts: sophgo: use real clock for sdhci As the clk patch is merged, Use real clocks for sdhci0. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/IA1PR20MB4953CA5D46EA8913B130D502BB052@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 75d0c57f4ffb..891932ae470f 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -47,13 +47,6 @@ #clock-cells = <0>; }; - sdhci_clk: sdhci-clock { - compatible = "fixed-clock"; - clock-frequency = <375000000>; - clock-output-names = "sdhci_clk"; - #clock-cells = <0>; - }; - soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -298,8 +291,9 @@ compatible = "sophgo,cv1800b-dwcmshc"; reg = <0x4310000 0x1000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; - clock-names = "core"; + clocks = <&clk CLK_AXI4_SD0>, + <&clk CLK_SD0>; + clock-names = "core", "bus"; status = "disabled"; }; From 78f6fecdd962b564bf2cc8e2636de9e7d41ade84 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 3 Apr 2024 10:38:12 +0200 Subject: [PATCH 565/969] arm64: dts: ls1028a: sl28: split variant 3/ads2 carrier The devicetree files can be (re-)used in u-boot now, they are imported on a regular basis (see OF_UPSTREAM option) there. Up until now, it didn't matter for linux and there was just a combined devicetree "-var3-ads2" (with ads2 being the carrier board). But if the devicetree files are now reused in u-boot, we need to have an individual "-var3" variant, because the bootloader is just using the bare "varN" devicetree files. Split the "var3" off of the "-var3-ads2" devicetree. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../fsl-ls1028a-kontron-sl28-var3-ads2.dts | 2 +- .../fsl-ls1028a-kontron-sl28-var3.dts | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ee2b28d76c44..b4247093a4de 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts index ed4e69e87e30..195bdbafdf7c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts @@ -10,7 +10,7 @@ /dts-v1/; #include -#include "fsl-ls1028a-kontron-sl28.dts" +#include "fsl-ls1028a-kontron-sl28-var3.dts" / { model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts new file mode 100644 index 000000000000..08851ca407a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the Kontron SMARC-sAL28 board. + * + * This is for the network variant 3 which has one ethernet ports. + * + * Copyright (C) 2024 Michael Walle + * + */ + +/dts-v1/; + +#include "fsl-ls1028a-kontron-sl28.dts" + +/ { + model = "Kontron SMARC-sAL28 (Single PHY)"; + compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a"; +}; From 6bea37186e622a9875d2872f2040f0eeadb89fda Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Tue, 2 Apr 2024 16:35:09 -0300 Subject: [PATCH 566/969] arm64: dts: freescale: Add i.MX8DX dtsi Add DTSI for i.MX8DX processor. According to 'i.MX 8DualX Industrial Applications Processors Data Sheet', the GPU and shader use a clock of 372MHz. Therefore, this dtsi includes the imx8dxp.dtsi and changes the clock accordingly. Signed-off-by: Hiago De Franco Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dx.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dx.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dx.dtsi b/arch/arm64/boot/dts/freescale/imx8dx.dtsi new file mode 100644 index 000000000000..ce76efc1a041 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + */ + +/dts-v1/; + +#include "imx8dxp.dtsi" + +&gpu_3d0 { + assigned-clock-rates = <372000000>, <372000000>; +}; From a92a74691b216004e3a9257774e74b171655bb70 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Tue, 2 Apr 2024 16:35:12 -0300 Subject: [PATCH 567/969] arm64: dts: freescale: Add Toradex Colibri iMX8DX Add support for Toradex Colibri iMX8DX SoM and Aster, Evaluation Board v3, Iris and Iris v2 carrier boards the module can be mated in. This SoM is a variant of the already supported Colibri iMX8QXP, using an NXP i.MX8DX SoC instead of i.MX8QXP. Link: https://www.toradex.com/computer-on-modules/colibri-arm-family/nxp-imx-8x Signed-off-by: Hiago De Franco Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ .../boot/dts/freescale/imx8dx-colibri-aster.dts | 16 ++++++++++++++++ .../dts/freescale/imx8dx-colibri-eval-v3.dts | 16 ++++++++++++++++ .../dts/freescale/imx8dx-colibri-iris-v2.dts | 16 ++++++++++++++++ .../boot/dts/freescale/imx8dx-colibri-iris.dts | 16 ++++++++++++++++ .../arm64/boot/dts/freescale/imx8dx-colibri.dtsi | 11 +++++++++++ 6 files changed, 79 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b4247093a4de..bd443c2bc5a4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -99,6 +99,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-aster.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts new file mode 100644 index 000000000000..c974f5dc0283 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Aster Board"; + compatible = "toradex,colibri-imx8x-aster", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts new file mode 100644 index 000000000000..f2bf15463ae8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx8x-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts new file mode 100644 index 000000000000..fd425c70cf2b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board"; + compatible = "toradex,colibri-imx8x-iris-v2", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts new file mode 100644 index 000000000000..e5e2346ce4f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Iris Board"; + compatible = "toradex,colibri-imx8x-iris", + "toradex,colibri-imx8x", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi new file mode 100644 index 000000000000..66b0fcc6687d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +#include "imx8dx.dtsi" +#include "imx8x-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8DX Module"; +}; From 6930b76e685c9c5ab84880f49e5024a7cdb96d86 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Tue, 2 Apr 2024 16:35:10 -0300 Subject: [PATCH 568/969] dt-bindings: arm: fsl: remove reduntant toradex,colibri-imx8x 'toradex,colibri-imx8x' is already present as a constant value for 'i.MX8QP Board with Toradex Colibri iMX8X Modules', so there is no need to keep it twice as a enum value for 'i.MX8QXP based Boards'. Signed-off-by: Hiago De Franco Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 304db8f302aa..b5188330b2c0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1227,7 +1227,6 @@ properties: - enum: - einfochips,imx8qxp-ai_ml # i.MX8QXP AI_ML Board - fsl,imx8qxp-mek # i.MX8QXP MEK Board - - toradex,colibri-imx8x # Colibri iMX8X Modules - const: fsl,imx8qxp - description: i.MX8DXL based Boards From 6f4154f0acdcae79ff120a37c34addee673685c3 Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Tue, 2 Apr 2024 16:35:11 -0300 Subject: [PATCH 569/969] dt-bindings: arm: fsl: Add Colibri iMX8DX Add support for Toradex Colibri iMX8DX SoM. As the i.MX8QXP variant is already supported, update the description with i.MX8DX and add 'fsl,imx8dx' item as well. Signed-off-by: Hiago De Franco Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b5188330b2c0..6d185d09cb6a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1235,7 +1235,7 @@ properties: - fsl,imx8dxl-evk # i.MX8DXL EVK Board - const: fsl,imx8dxl - - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules + - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules items: - enum: - toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board @@ -1243,7 +1243,9 @@ properties: - toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board - toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2 - const: toradex,colibri-imx8x - - const: fsl,imx8qxp + - enum: + - fsl,imx8qxp + - fsl,imx8dx - description: TQMa8Xx is a series of SOM featuring NXP i.MX8X system-on-chip From e8e47a04dc98805214bd9baa253462fd662e04d8 Mon Sep 17 00:00:00 2001 From: Michael Grzeschik Date: Wed, 3 Apr 2024 10:18:27 +0200 Subject: [PATCH 570/969] ARM: dts: imx27-phytec: Add USB support This patch adds the pinmux and nodes for usbotg and usbh2. In v6 revision of the pca100 the usb phys were changed to usb3320 which are connected by their reset pins. We add the phy configuration to the description. Signed-off-by: Michael Grzeschik Signed-off-by: Shawn Guo --- .../nxp/imx/imx27-phytec-phycard-s-som.dtsi | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi index abc9233c5a1b..31b3fc972abb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi @@ -15,6 +15,22 @@ device_type = "memory"; reg = <0xa0000000 0x08000000>; /* 128MB */ }; + + usbotgphy: usbotgphy { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgphy>; + reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + #phy-cells = <0>; + }; + + usbh2phy: usbh2phy { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2phy>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + #phy-cells = <0>; + }; }; &cspi1 { @@ -84,6 +100,52 @@ MX27_PAD_NFWE_B__NFWE_B 0x0 >; }; + + pinctrl_usbotgphy: usbotgphygrp { + fsl,pins = < + MX27_PAD_USBH1_RCV__GPIO2_25 0x1 /* reset gpio */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; + + pinctrl_usbh2phy: usbh2phygrp { + fsl,pins = < + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 /* reset gpio */ + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; }; }; @@ -95,3 +157,19 @@ nand-on-flash-bbt; status = "okay"; }; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "ulpi"; + phys = <&usbotgphy>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + phy_type = "ulpi"; + phys = <&usbh2phy>; + status = "okay"; +}; From 6687155ffc6671514f2ef874ac8be41d9d131918 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:32 +0800 Subject: [PATCH 571/969] dt-bindings: usb: usbmisc-imx: add fsl,imx8ulp-usbmisc compatible Add "fsl,imx8ulp-usbmisc" compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml b/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml index 2d3589d284b2..0a6e7ac1b37e 100644 --- a/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml +++ b/Documentation/devicetree/bindings/usb/fsl,usbmisc.yaml @@ -33,6 +33,7 @@ properties: - fsl,imx7ulp-usbmisc - fsl,imx8mm-usbmisc - fsl,imx8mn-usbmisc + - fsl,imx8ulp-usbmisc - const: fsl,imx7d-usbmisc - const: fsl,imx6q-usbmisc - items: From e59cf6e0e70e9931b979c44262b0b19b7cc766a3 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:35 +0800 Subject: [PATCH 572/969] ARM: dts: imx6: remove fsl,anatop property from usb controller node This property is not needed for usb controller. The usb phy needs it instead. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sll.dtsi | 1 - arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi index 3659fd5ecfa6..ddeb5b37fb78 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi @@ -683,7 +683,6 @@ clocks = <&clks IMX6SLL_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 0de359d62a47..6d3deba60de5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -929,7 +929,6 @@ clocks = <&clks IMX6SX_CLK_USBOH3>; fsl,usbphy = <&usbphy1>; fsl,usbmisc = <&usbmisc 0>; - fsl,anatop = <&anatop>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; @@ -957,7 +956,6 @@ fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; - fsl,anatop = <&anatop>; dr_mode = "host"; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; From 95049bf5e63f4f7b17d7af7a0675057f035b0b98 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:33 +0800 Subject: [PATCH 573/969] arm64: dts: imx8ulp: add usb nodes Add USB nodes on i.MX8ULP platform which has 2 USB controllers. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c4a0082f30d3..cbed01bb8cc0 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -472,6 +472,68 @@ status = "disabled"; }; + usbotg1: usb@29900000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; + reg = <0x29900000 0x200>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB0>; + power-domains = <&scmi_devpd IMX8ULP_PD_USB0>; + phys = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc1: usbmisc@29900200 { + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x29900200 0x200>; + #index-cells = <1>; + status = "disabled"; + }; + + usbphy1: usb-phy@29910000 { + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; + reg = <0x29910000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbotg2: usb@29920000 { + compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; + reg = <0x29920000 0x200>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB1>; + power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + phys = <&usbphy2>; + fsl,usbmisc = <&usbmisc2 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x8>; + rx-burst-size-dword = <0x8>; + status = "disabled"; + }; + + usbmisc2: usbmisc@29920200 { + compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x29920200 0x200>; + #index-cells = <1>; + status = "disabled"; + }; + + usbphy2: usb-phy@29930000 { + compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy"; + reg = <0x29930000 0x10000>; + interrupts = ; + clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + fec: ethernet@29950000 { compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; reg = <0x29950000 0x10000>; From c4b4593ecb0b0ff8949652d5604140e080b7623e Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:34 +0800 Subject: [PATCH 574/969] arm64: dts: imx8ulp-evk: enable usb nodes and add ptn5150 nodes Enable 2 USB nodes and add 2 PTN5150 nodes on i.MX8ULP evk board. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 24bb253b938d..e937e5f8fa8b 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -127,12 +127,70 @@ pinctrl-1 = <&pinctrl_lpi2c7>; status = "okay"; + ptn5150_1: typec@1d { + compatible = "nxp,ptn5150"; + reg = <0x1d>; + int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + status = "disabled"; + }; + pcal6408: gpio@21 { compatible = "nxp,pcal9554b"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; + + ptn5150_2: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec2>; + status = "disabled"; + }; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <110>; + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <110>; + status = "okay"; +}; + +&usbmisc2 { + status = "okay"; }; &usdhc0 { @@ -224,6 +282,32 @@ >; }; + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8ULP_PAD_PTF3__PTF3 0x3 + >; + }; + + pinctrl_typec2: typec2grp { + fsl,pins = < + MX8ULP_PAD_PTF5__PTF5 0x3 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8ULP_PAD_PTF2__USB0_ID 0x10003 + MX8ULP_PAD_PTF4__USB0_OC 0x10003 + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTF6__USB1_OC 0x10003 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 From cb040019c0e131a49c1351d5d3db3f4c462ca3ab Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:36 +0800 Subject: [PATCH 575/969] arm64: dts: imx93: add usb nodes There are 2 USB controllers on i.MX93. Add them. Acked-by: Alexander Stein Tested-by: Alexander Stein # TQMa9352LA/CA Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index b8ef9b938856..95128932abda 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -183,6 +183,20 @@ status = "disabled"; }; + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -1166,6 +1180,50 @@ status = "disabled"; }; + usbotg1: usb@4c100000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c100000 0x200>; + interrupts = ; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c100200 0x200>; + #index-cells = <1>; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c200000 0x200>; + interrupts = ; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c200200 0x200>; + #index-cells = <1>; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; From 13df8b3a2f06382d852dc51503032f88a2d8ab42 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:37 +0800 Subject: [PATCH 576/969] arm64: dts: imx93-11x11-evk: enable usb and typec nodes There are 2 Type-C ports and 2 USB controllers on i.MX93. Enable them. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 07e85a30a25f..2211922c1826 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx93.dtsi" / { @@ -104,6 +105,81 @@ status = "okay"; }; +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -156,6 +232,42 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -320,6 +432,13 @@ >; }; + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e From 0923c18fc54383078ae422d87e799a0b73745d19 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Wed, 3 Apr 2024 17:04:38 +0800 Subject: [PATCH 577/969] arm64: dts: imx8mm/n remove clock-names property from usb controller node The clock-names property is not needed by usb controller node on imx8mm/n. This will remove it. Signed-off-by: Xu Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 -- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 - 2 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 46473950e926..9535dedcef59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1260,7 +1260,6 @@ reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; @@ -1281,7 +1280,6 @@ reg = <0x32e50000 0x200>; interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b901ee0d2d03..a5f9cfb46e5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1220,7 +1220,6 @@ reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; From 9745922474a8b1129a1852b7fc916f91607072de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2024 16:40:19 -0300 Subject: [PATCH 578/969] arm64: dts: imx8m/qxp: Pass the tcpci compatible Per nxp,ptn5110.yaml, also pass the fallback "tcpci" compatible to fix the following dt-schema warning: usb-typec@50: compatible: ['nxp,ptn5110'] is too short from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml# Signed-off-by: Fabio Estevam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 2 +- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index bd5b365867fd..ff128d25cab9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -381,7 +381,7 @@ }; ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec1>; reg = <0x50>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 269e70f66a13..152b0eafc6f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -227,7 +227,7 @@ }; ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec1>; reg = <0x50>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index a08057410bde..e5d3901f2913 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -340,7 +340,7 @@ &i2c3 { /* Connected to USB Hub */ usb-typec@52 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts index 366693f31992..e92b5d5a66b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts @@ -42,7 +42,7 @@ status = "okay"; typec_ptn5100: usb-typec@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x50>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 8055a2c23035..b268ba7a0e12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -429,7 +429,7 @@ }; typec_ptn5100: usb-typec@52 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; reg = <0x52>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 8360bb851ac0..83d298c2bfd3 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -149,7 +149,7 @@ }; ptn5110: tcpc@50 { - compatible = "nxp,ptn5110"; + compatible = "nxp,ptn5110", "tcpci"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec>; reg = <0x50>; From d157e889846e9482d198b975f69ecd43990c4b12 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2024 16:31:23 -0300 Subject: [PATCH 579/969] arm64: dts: imx8mn-evk: Fix ADV7535 dt-schema warnings Currently, there are several ADV7535 dt-schema warnings. Fx them the same way as in commit efa97aed071e060 ("arm64: dts: imx8mm-evk: Fix hdmi@3d node"). As there are two different PMICs used on the imx8mn-evk variants, describe the ADV7535 power supplies in each board devicetree. Fixes: 5aafda608f73 ("arm64: dts: imx8mn-evk: Add camera support") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mn-ddr3l-evk.dts | 10 +++++++ .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 10 +++++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 10 +++++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 27 ++++++++++--------- 4 files changed, 45 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts index 000e2c0596df..9ebd81e7eb7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -112,3 +112,13 @@ }; }; }; + +&i2c2 { + hdmi@3d { + avdd-supply = <&buck5>; + dvdd-supply = <&buck5>; + pvdd-supply = <&buck5>; + a2vdd-supply = <&buck5>; + v1p2-supply = <&buck5>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index cc2ff59ac53b..1a4ac39ebde8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -158,3 +158,13 @@ }; }; }; + +&i2c2 { + hdmi@3d { + avdd-supply = <&buck5_reg>; + dvdd-supply = <&buck5_reg>; + pvdd-supply = <&buck5_reg>; + a2vdd-supply = <&buck5_reg>; + v1p2-supply = <&buck5_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 0b71f50d936e..6f7f409c4181 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -125,3 +125,13 @@ }; }; }; + +&i2c2 { + hdmi@3d { + avdd-supply = <&buck5>; + dvdd-supply = <&buck5>; + pvdd-supply = <&buck5>; + a2vdd-supply = <&buck5>; + v1p2-supply = <&buck5>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 152b0eafc6f0..b65e5c583805 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -30,7 +30,7 @@ port { hdmi_connector_in: endpoint { - remote-endpoint = <&adv7533_out>; + remote-endpoint = <&adv7535_out>; }; }; }; @@ -52,6 +52,13 @@ enable-active-high; }; + reg_vddext_3v3: regulator-vddext-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; @@ -193,15 +200,11 @@ hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; + v3p3-supply = <®_vddext_3v3>; ports { #address-cells = <1>; @@ -210,7 +213,7 @@ port@0 { reg = <0>; - adv7533_in: endpoint { + adv7535_in: endpoint { remote-endpoint = <&dsi_out>; }; }; @@ -218,7 +221,7 @@ port@1 { reg = <1>; - adv7533_out: endpoint { + adv7535_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; @@ -335,7 +338,7 @@ reg = <1>; dsi_out: endpoint { - remote-endpoint = <&adv7533_in>; + remote-endpoint = <&adv7535_in>; data-lanes = <1 2 3 4>; }; }; From 8deb080fc9924eb7e1d0b517391be5a5c91da420 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2024 16:31:24 -0300 Subject: [PATCH 580/969] arm64: dts: imx8mn-evk: Describe the OV5640 supplies Per ovti,ov5640.yaml, the OV5640 power supplies are mandatory properties. Describe them to fix dt-schema warnings. As there are two different PMICs used on the imx8mn-evk variants, describe the DOVDD OV5640 power supply in each board devicetree. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mn-ddr3l-evk.dts | 6 ++++++ .../arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 16 ++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts index 9ebd81e7eb7c..d25032e3ceab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -122,3 +122,9 @@ v1p2-supply = <&buck5>; }; }; + +&i2c3 { + camera@3c { + DOVDD-supply = <&buck5>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 1a4ac39ebde8..6d85a0b052c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -168,3 +168,9 @@ v1p2-supply = <&buck5_reg>; }; }; + +&i2c3 { + camera@3c { + DOVDD-supply = <&buck5_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 6f7f409c4181..41330210a05f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -135,3 +135,9 @@ v1p2-supply = <&buck5>; }; }; + +&i2c3 { + camera@3c { + DOVDD-supply = <&buck5>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index b65e5c583805..9e0259ddf4bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -52,6 +52,20 @@ enable-active-high; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + reg_vddext_3v3: regulator-vddext-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDEXT_3V3"; @@ -287,6 +301,8 @@ assigned-clock-rates = <24000000>; powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_1v8>; + DVDD-supply = <®_1v5>; port { ov5640_to_mipi_csi2: endpoint { From ef07b2246cf2fa940ba646218216d0220263adda Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2024 16:31:25 -0300 Subject: [PATCH 581/969] arm64: dts: imx8mm-evk: Describe the OV5640 supplies Per ovti,ov5640.yaml, the OV5640 power supplies are mandatory properties. Describe them to fix dt-schema warnings. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index ff128d25cab9..90d1901df2b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -72,6 +72,20 @@ enable-active-high; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + reg_vddext_3v3: regulator-vddext-3v3 { compatible = "regulator-fixed"; regulator-name = "VDDEXT_3V3"; @@ -441,6 +455,9 @@ assigned-clock-rates = <24000000>; powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + DOVDD-supply = <&buck5_reg>; + AVDD-supply = <®_1v8>; + DVDD-supply = <®_1v5>; port { ov5640_to_mipi_csi2: endpoint { From 8de98a319a2b4b091b8723b4af9d639bfcff8b7c Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 4 Apr 2024 03:20:09 +0300 Subject: [PATCH 582/969] arm64: dts: debix-a: Disable i2c2 in base .dts The I2C2 bus is used for the CSI and DSI connectors only, no devices are connected to it on neither the Debix Model A nor its IO board. Disable the bus in the board's .dts and remove its clock frequency settings, as the value depends solely on the devices conncted to the CSI and DSI connectors. Display panel or camera sensor overlays will configure and enable the bus when necessary. Signed-off-by: Jacopo Mondi Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 2c19766ebf09..9b8f97a84e61 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -197,10 +197,8 @@ }; &i2c2 { - clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; }; &i2c3 { From a4db43062f1167f623b282e082826fb814e06178 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2024 23:08:31 -0300 Subject: [PATCH 583/969] arm64: dts: imx8mp-debix-som-a-bmb-08: Remove 'phy-supply' from eqos Per nxp,dwmac-imx.yaml, it is not valid to pass 'phy-supply'. Remove it to fix the following dt-schema warning: ethernet@30bf0000: Unevaluated properties are not allowed ('phy-supply' was unexpected) from schema $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml# Signed-off-by: Fabio Estevam Reviewed-by: Umang Jain Tested-by: Umang Jain Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts index b11d694b98e1..d241db3743a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -144,7 +144,6 @@ pinctrl-0 = <&pinctrl_eqos>; nvmem-cells = <ðmac1>; nvmem-cell-names = "mac-address"; - phy-supply = <®_baseboard_vdd3v3>; phy-handle = <ðphy0>; phy-mode = "rgmii-id"; status = "okay"; From 39870d24020c91e8d87d525bd528920f44853815 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 11:28:18 +0200 Subject: [PATCH 584/969] arm64: dts: imx8mm-var-som-symphony: drop redundant status from typec "okay" is the default status, so drop redundant property from the typec node. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index d643381417f1..affbc67c2ef6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -117,7 +117,6 @@ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; }; }; From c0d1f78e5b2076548e155953656e49b25620942c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 5 Apr 2024 11:28:19 +0200 Subject: [PATCH 585/969] arm64: dts: imx8mn-var-som-symphony: drop redundant status from typec "okay" is the default status, so drop redundant property from the typec node. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index a6b94d1957c9..3434b189fa58 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -126,7 +126,6 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; - status = "okay"; port { typec1_dr_sw: endpoint { From 9d071e1889a578162ced6a6c9062653f9bcb442c Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Fri, 5 Apr 2024 18:07:17 +0200 Subject: [PATCH 586/969] arm64: dts: freescale: imx8mp-verdin: replace sleep-moci hog with regulator The Verdin family has a signal called sleep-moci which can be used to turn off peripherals on the carrier board when the SoM goes into suspend. So far we have hogged this signal, which means the peripherals are always on and it is not possible to add peripherals that depend on the sleep-moci to be on. With this change, we replace the hog with a regulator so that peripherals can add their own regulators that use the same gpio. Carrier boards that allow peripherals to be powered off in suspend can disable this regulator and implement their own regulator to control the sleep-moci. Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-verdin-dahlia.dtsi | 5 ++++ .../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 5 ++++ .../dts/freescale/imx8mp-verdin-yavia.dtsi | 5 ++++ .../boot/dts/freescale/imx8mp-verdin.dtsi | 26 ++++++++++++------- 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 8d954259085f..718004fe983f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -70,6 +70,11 @@ status = "okay"; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + /* Current measurement into module VCC */ &hwmon { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index e5400140e5c6..c2721e9f5797 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -93,6 +93,11 @@ status = "okay"; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &gpio_expander_21 { status = "okay"; vcc-supply = <®_1p8v>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index 3a8542266d85..a7b261ff3e4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -100,6 +100,11 @@ status = "okay"; }; +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &hwmon_temp { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index f033d4310305..aef4bef4bccd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -116,6 +116,22 @@ vin-supply = <®_vdd_3v3>; }; + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + reg_usb1_vbus: regulator-usb1-vbus { compatible = "regulator-fixed"; enable-active-high; @@ -439,16 +455,6 @@ "SODIMM_256", "SODIMM_48", "SODIMM_44"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <29 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; }; /* On-module I2C */ From 25b3af5395b5b07d8e656c932b7f694daa14b384 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Fri, 5 Apr 2024 18:07:18 +0200 Subject: [PATCH 587/969] arm64: dts: freescale: imx8mp-verdin-dahlia: support sleep-moci Previously, we had the sleep-moci pin set to always on. However, the Dahlia carrier board supports disabling the sleep-moci when the system is suspended to power down peripherals that support it. This reduces overall power consumption. This commit adds support for this feature by disabling the reg_force_sleep_moci regulator and adding two new regulators for the USB hub and PCIe that can be turned off when the system is suspended. Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-verdin-dahlia.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 718004fe983f..b62d6482da66 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -32,6 +32,25 @@ sound-dai = <&sai1>; }; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "PCIE_1_PWR_EN"; + startup-delay-us = <100000>; + }; }; &backlight { @@ -122,6 +141,7 @@ /* Verdin PCIE_1 */ &pcie { + vpcie-supply = <®_pcie>; status = "okay"; }; @@ -148,6 +168,11 @@ vin-supply = <®_3p3v>; }; +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + /* Verdin I2S_1 */ &sai1 { assigned-clocks = <&clk IMX8MP_CLK_SAI1>; @@ -191,6 +216,25 @@ status = "okay"; }; +&usb_dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_3_0: usb-hub@1 { + compatible = "usb424,5744"; + reg = <1>; + peer-hub = <&usb_hub_2_0>; + vdd-supply = <®_usb_hub>; + }; + + usb_hub_2_0: usb-hub@2 { + compatible = "usb424,2744"; + reg = <2>; + peer-hub = <&usb_hub_3_0>; + vdd-supply = <®_usb_hub>; + }; +}; + /* Verdin SD_1 */ &usdhc2 { status = "okay"; From 9f06926ef1b22a52e3c8ceea394cf7408c4e66b2 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Fri, 5 Apr 2024 18:07:19 +0200 Subject: [PATCH 588/969] arm64: dts: freescale: imx8mm-verdin: replace sleep-moci hog with regulator The Verdin family has a signal called sleep-moci which can be used to turn off peripherals on the carrier board when the SoM goes into suspend. So far we have hogged this signal, which means the peripherals are always on and it is not possible to add peripherals that depend on the sleep-moci to be on. With this change, we replace the hog with a regulator so that peripherals can add their own regulators that use the same gpio. Carrier boards that allow peripherals to be powered off in suspend can disable this regulator and implement their own regulator to control the sleep-moci. Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-verdin-dahlia.dtsi | 5 ++++ .../boot/dts/freescale/imx8mm-verdin-dev.dtsi | 5 ++++ .../dts/freescale/imx8mm-verdin-yavia.dtsi | 5 ++++ .../boot/dts/freescale/imx8mm-verdin.dtsi | 26 ++++++++++++------- 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index 1cff0b829357..b64dac4f29c2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -58,6 +58,11 @@ status = "okay"; }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + /* Current measurement into module VCC */ &hwmon { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi index 3c4b8ca125e3..95b7c9a03a23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -78,6 +78,11 @@ status = "okay"; }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &gpio_expander_21 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi index 1e28c78e381f..763f069e8405 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi @@ -81,6 +81,11 @@ pinctrl-0 = <&pinctrl_gpios_ext_yavia>; }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + &hwmon_temp { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 6f0811587142..4768b05fd765 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -110,6 +110,22 @@ startup-delay-us = <200000>; }; + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + reg_usb_otg1_vbus: regulator-usb-otg1 { compatible = "regulator-fixed"; enable-active-high; @@ -333,16 +349,6 @@ "SODIMM_212", "SODIMM_151", "SODIMM_153"; - - ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <1 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; - }; }; /* On-module I2C */ From 1288f819d6c7e3dc2e301728cb7fa9a99a718234 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Fri, 5 Apr 2024 18:07:20 +0200 Subject: [PATCH 589/969] arm64: dts: freescale: imx8mm-verdin-dahlia: support sleep-moci Previously, we had the sleep-moci pin set to always on. However, the Dahlia carrier board supports disabling the sleep-moci when the system is suspended to power down peripherals that support it. This reduces overall power consumption. This commit adds support for this feature by disabling the reg_force_sleep_moci regulator and adding two new regulators for the USB hub and PCIe that can be turned off when the system is suspended. Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-verdin-dahlia.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index b64dac4f29c2..393fc9e20423 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -32,6 +32,25 @@ sound-dai = <&sai2>; }; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "PCIE_1_PWR_EN"; + startup-delay-us = <100000>; + }; }; /* Verdin SPI_1 */ @@ -98,6 +117,7 @@ /* Verdin PCIE_1 */ &pcie0 { + vpcie-supply = <®_pcie>; status = "okay"; }; @@ -120,6 +140,11 @@ status = "okay"; }; +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + /* Verdin I2S_1 */ &sai2 { status = "okay"; @@ -148,8 +173,16 @@ /* Verdin USB_2 */ &usbotg2 { + #address-cells = <1>; + #size-cells = <0>; disable-over-current; status = "okay"; + + usb-hub@1 { + compatible = "usb424,2744"; + reg = <1>; + vdd-supply = <®_usb_hub>; + }; }; /* Verdin SD_1 */ From 2682f4ed024f72171367579a020d46b887eea683 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 8 Apr 2024 15:06:54 +0300 Subject: [PATCH 590/969] arm64: dts: imx8-ss-img: Remove JPEG clock-names Per nxp,imx8-jpeg.yaml, the clock-names entry is not valid. Remove them. Signed-off-by: Fabio Estevam Signed-off-by: Mirela Rabulea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index e7783cc2d830..77d2928997b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -21,7 +21,6 @@ img_subsys: bus@58000000 { interrupts = ; clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; - clock-names = "per", "ipg"; assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; assigned-clock-rates = <200000000>, <200000000>; @@ -35,7 +34,6 @@ img_subsys: bus@58000000 { interrupts = ; clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; - clock-names = "per", "ipg"; assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; assigned-clock-rates = <200000000>, <200000000>; From 833fae0594374bd8c24e7066c65db148e659d68b Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 10 Apr 2024 13:56:10 +0300 Subject: [PATCH 591/969] arm64: dts: imx8mp-msc-sm2s: correct i2c{1..6} pad drive strength Adjust i2c drive strength based on latest Avnet BSP. Signed-off-by: Ian Ray Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-msc-sm2s.dtsi | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi index 61c2a63efc6d..e794f05cf5aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi @@ -602,38 +602,38 @@ pinctrl_i2c1: i2c1grp { fsl,pins = - , - ; + , + ; }; pinctrl_i2c2: i2c2grp { fsl,pins = - , - ; + , + ; }; pinctrl_i2c3: i2c3grp { fsl,pins = - , - ; + , + ; }; pinctrl_i2c4: i2c4grp { fsl,pins = - , - ; + , + ; }; pinctrl_i2c5: i2c5grp { fsl,pins = - , - ; + , + ; }; pinctrl_i2c6: i2c6grp { fsl,pins = - , - ; + , + ; }; pinctrl_lcd0_backlight: lcd0-backlightgrp { From 3927060f922c541eb715b160276044956fee8302 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 10 Apr 2024 13:56:11 +0300 Subject: [PATCH 592/969] arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios Add i2c{1,6} sda-/scl-gpios with the corresponding pinmux entries. Signed-off-by: Ian Ray Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-msc-sm2s.dtsi | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi index e794f05cf5aa..0fd5c3abcdb7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi @@ -200,8 +200,11 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -241,8 +244,11 @@ }; &i2c6 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -606,6 +612,12 @@ ; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + , + ; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = , @@ -636,6 +648,12 @@ ; }; + pinctrl_i2c6_gpio: i2c6gpiogrp { + fsl,pins = + , + ; + }; + pinctrl_lcd0_backlight: lcd0-backlightgrp { fsl,pins = ; From 40d691a6dc880d0f201902520cfc38b2ead3910a Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 12 Apr 2024 11:56:52 +0800 Subject: [PATCH 593/969] ARM: dts: imx6: exchange fallback and specific compatible string Exchange fallback and specific compatible string for spdif sound card. The specific compatible string needs to be in first place, the fallback compatible string needs to be in the end. Signed-off-by: Shengjiu Wang Reviewed-by: Krzysztof Kozlowski Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index 68e97180d33e..51517e27418c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -144,8 +144,8 @@ }; sound-spdif { - compatible = "fsl,imx-audio-spdif", - "fsl,imx-sabreauto-spdif"; + compatible = "fsl,imx-sabreauto-spdif", + "fsl,imx-audio-spdif"; model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index c6e85e4a0883..67872c16372a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -184,8 +184,8 @@ }; sound-spdif { - compatible = "fsl,imx-audio-spdif", - "fsl,imx6sx-sdb-spdif"; + compatible = "fsl,imx6sx-sdb-spdif", + "fsl,imx-audio-spdif"; model = "imx-spdif"; spdif-controller = <&spdif>; spdif-out; From da8fc156d76c3b4b4a49ef65cf6b5cd1767ff17e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 8 Apr 2024 11:09:05 -0300 Subject: [PATCH 594/969] ARM: imx_v6_v7_defconfig: Update ONBOARD_USB_HUB to ONBOAD_USB_DEV The onboard_usb_hub driver has been updated to support non-hub devices, which has led to some renaming. Update to the new name (ONBOARD_USB_DEV) accordingly. Based on similar fixes done by Javier Carrasco for other defconfigs. Fixes: 0bb36055c049 ("ARM: imx_v6_v7_defconfig: Select CONFIG_USB_ONBOARD_HUB") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index b06128da94e5..cf2480dce285 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -336,7 +336,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_TEST=m CONFIG_USB_EHSET_TEST_FIXTURE=m -CONFIG_USB_ONBOARD_HUB=y +CONFIG_USB_ONBOARD_DEV=y CONFIG_NOP_USB_XCEIV=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y From e6b73eb23f0b6e589710c3b25b1d58b6dba4a02b Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Tue, 9 Apr 2024 14:50:40 +0530 Subject: [PATCH 595/969] arm64: dts: imx8ulp: add caam jr Add crypto node in device tree for: - CAAM job-ring Signed-off-by: Varun Sethi Signed-off-by: Pankaj Gupta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index cbed01bb8cc0..e32d5afcf4a9 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -252,6 +252,38 @@ #reset-cells = <1>; }; + crypto: crypto@292e0000 { + compatible = "fsl,sec-v4.0"; + reg = <0x292e0000 0x10000>; + ranges = <0 0x292e0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + }; + tpm5: tpm@29340000 { compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; reg = <0x29340000 0x1000>; From 3e67a1ddd56d14a3b6dcc55aec25b743ed34801d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 10 Apr 2024 08:37:05 +0200 Subject: [PATCH 596/969] arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL Enable HDMI nodes and add the output connector. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 86d3da36e4f3..c51ed7d991d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -135,6 +135,18 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "X44"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + display: display { /* * Display is not fixed, so compatible has to be added from @@ -470,6 +482,28 @@ "", "", "", ""; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c2 { clock-frequency = <384000>; pinctrl-names = "default", "gpio"; @@ -531,6 +565,10 @@ status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + &pcf85063 { /* RTC_EVENT# is connected on MBa8MPxL */ pinctrl-names = "default"; From 7f699ed1df872faf09a0978476e19c4a2fa7757a Mon Sep 17 00:00:00 2001 From: Hiago De Franco Date: Thu, 11 Apr 2024 13:14:41 -0300 Subject: [PATCH 597/969] arm64: dts: freescale: imx8m[mp]-verdin: Update audio card name On the Dahlia and Development carrier boards for the Verdin family (iMX8MM and iMX8MP), WM8904 and NAU8822 codecs are used. Instead of module-specific names, switch to more generic names based on the codec employed on the carrier board itself. This modification facilitates access to ALSA card names, ensuring consistency across iMX8MP and iMX8MM, as they share the same carrier board. Signed-off-by: Hiago De Franco Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index 393fc9e20423..ce20de259805 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -10,7 +10,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,name = "verdin-wm8904"; simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi index 95b7c9a03a23..1d8d146d9eeb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -10,7 +10,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mm-nau8822"; + simple-audio-card,name = "verdin-nau8822"; simple-audio-card,routing = "Headphones", "LHP", "Headphones", "RHP", diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index b62d6482da66..6e6b9c2c4640 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -10,7 +10,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mp-wm8904"; + simple-audio-card,name = "verdin-wm8904"; simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index c2721e9f5797..42ed44a11711 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -22,7 +22,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&codec_dai>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "imx8mp-nau8822"; + simple-audio-card,name = "verdin-nau8822"; simple-audio-card,routing = "Headphones", "LHP", "Headphones", "RHP", From 6eaa8431b340577ddfba86cf92f4b52e52370db4 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Fri, 12 Apr 2024 17:10:52 +0100 Subject: [PATCH 598/969] ARM: imx: Assign parents for mmdc event_source devices Currently the PMU device appears directly under /sys/devices/ Only root busses should appear there, so instead assign the pmu->dev parent to be the platform device. Link: https://lore.kernel.org/linux-cxl/ZCLI9A40PJsyqAmq@kroah.com/ Cc: Shawn Guo Signed-off-by: Jonathan Cameron Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mmdc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 25893d109190..b68cb86dbe4c 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -437,6 +437,7 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, { *pmu_mmdc = (struct mmdc_pmu) { .pmu = (struct pmu) { + .parent = dev, .task_ctx_nr = perf_invalid_context, .attr_groups = attr_groups, .event_init = mmdc_pmu_event_init, From 808852fa3a5e11c8d2bf0aef3695aaf930bd4fa9 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Apr 2024 21:35:01 +0100 Subject: [PATCH 599/969] riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI Add the IRQC node to RZ/Five (R9A07G043F) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240403203503.634465-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 75 +++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index f35324b9173c..e0ddf8f602c7 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -54,6 +54,81 @@ dma-noncoherent; interrupt-parent = <&plic>; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g043f-irqc"; + reg = <0 0x110a0000 0 0x20000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <33 IRQ_TYPE_LEVEL_HIGH>, + <34 IRQ_TYPE_LEVEL_HIGH>, + <35 IRQ_TYPE_LEVEL_HIGH>, + <36 IRQ_TYPE_LEVEL_HIGH>, + <37 IRQ_TYPE_LEVEL_HIGH>, + <38 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>, + <40 IRQ_TYPE_LEVEL_HIGH>, + <476 IRQ_TYPE_LEVEL_HIGH>, + <477 IRQ_TYPE_LEVEL_HIGH>, + <478 IRQ_TYPE_LEVEL_HIGH>, + <479 IRQ_TYPE_LEVEL_HIGH>, + <480 IRQ_TYPE_LEVEL_HIGH>, + <481 IRQ_TYPE_LEVEL_HIGH>, + <482 IRQ_TYPE_LEVEL_HIGH>, + <483 IRQ_TYPE_LEVEL_HIGH>, + <484 IRQ_TYPE_LEVEL_HIGH>, + <485 IRQ_TYPE_LEVEL_HIGH>, + <486 IRQ_TYPE_LEVEL_HIGH>, + <487 IRQ_TYPE_LEVEL_HIGH>, + <488 IRQ_TYPE_LEVEL_HIGH>, + <489 IRQ_TYPE_LEVEL_HIGH>, + <490 IRQ_TYPE_LEVEL_HIGH>, + <491 IRQ_TYPE_LEVEL_HIGH>, + <492 IRQ_TYPE_LEVEL_HIGH>, + <493 IRQ_TYPE_LEVEL_HIGH>, + <494 IRQ_TYPE_LEVEL_HIGH>, + <495 IRQ_TYPE_LEVEL_HIGH>, + <496 IRQ_TYPE_LEVEL_HIGH>, + <497 IRQ_TYPE_LEVEL_HIGH>, + <498 IRQ_TYPE_LEVEL_HIGH>, + <499 IRQ_TYPE_LEVEL_HIGH>, + <500 IRQ_TYPE_LEVEL_HIGH>, + <501 IRQ_TYPE_LEVEL_HIGH>, + <502 IRQ_TYPE_LEVEL_HIGH>, + <503 IRQ_TYPE_LEVEL_HIGH>, + <504 IRQ_TYPE_LEVEL_HIGH>, + <505 IRQ_TYPE_LEVEL_HIGH>, + <506 IRQ_TYPE_LEVEL_HIGH>, + <507 IRQ_TYPE_LEVEL_HIGH>, + <57 IRQ_TYPE_LEVEL_HIGH>, + <66 IRQ_TYPE_EDGE_RISING>, + <67 IRQ_TYPE_EDGE_RISING>, + <68 IRQ_TYPE_EDGE_RISING>, + <69 IRQ_TYPE_EDGE_RISING>, + <70 IRQ_TYPE_EDGE_RISING>, + <71 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", + "ec7tiovf-1"; + clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>, + <&cpg CPG_MOD R9A07G043_IAX45_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_IAX45_RESETN>; + }; + plic: interrupt-controller@12c00000 { compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; #interrupt-cells = <2>; From 1731ab2f8b62f0be2073de581ffef6db1196ad4f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Apr 2024 21:35:02 +0100 Subject: [PATCH 600/969] arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI Now that we have added support for IRQC to both RZ/Five and RZ/G2UL SoCs we can move the interrupt-parent for pinctrl node back to the common shared r9a07g043.dtsi file. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240403203503.634465-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 8721f4c9fa0f..d2365def1059 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -598,6 +598,7 @@ gpio-ranges = <&pinctrl 0 0 152>; #interrupt-cells = <2>; interrupt-controller; + interrupt-parent = <&irqc>; clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043_GPIO_RSTN>, diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 964b0a475eee..165bfcfef3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -54,10 +54,6 @@ }; }; -&pinctrl { - interrupt-parent = <&irqc>; -}; - &soc { interrupt-parent = <&gic>; From fc5d2b222ab18612bc7bdfef7f672afd2cd7275b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 3 Apr 2024 21:35:03 +0100 Subject: [PATCH 601/969] riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes Now that we have enabled IRQC support for RZ/Five SoC switch to interrupt mode for ethernet0/1 PHYs instead of polling mode. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240403203503.634465-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index 433ab5c6a626..5e808242649e 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -6,19 +6,3 @@ */ #include - -#if (!SW_ET0_EN_N) -ð0 { - phy0: ethernet-phy@7 { - /delete-property/ interrupt-parent; - /delete-property/ interrupts; - }; -}; -#endif - -ð1 { - phy1: ethernet-phy@7 { - /delete-property/ interrupt-parent; - /delete-property/ interrupts; - }; -}; From e58d8e885b4e937145a96cd94bc890c2134ff640 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 17 Apr 2024 12:20:03 +0100 Subject: [PATCH 602/969] arm64: dts: renesas: rzg3s-smarc-som: Enable eMMC by default Enable eMMC by default on the RZ/G3S SMARC platform, as previously done on RZ/G2L boards and other Renesas platforms. The SW_CONFIG2 setting selects between the uSD0 card and eMMC. By setting SW_CONFIG2 to SW_OFF, we select eMMC by default. Signed-off-by: Lad Prabhakar Reviewed-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240417112003.428348-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 1f87150a2e0a..8a3d302f1535 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -25,7 +25,7 @@ * SW_OFF - SD2 is connected to SoC * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC */ -#define SW_CONFIG2 SW_ON +#define SW_CONFIG2 SW_OFF #define SW_CONFIG3 SW_ON / { From 6e6973948ce6911e35cb559bc53de4156b4a9675 Mon Sep 17 00:00:00 2001 From: "Jason J. Herne" Date: Mon, 15 Apr 2024 11:25:51 -0400 Subject: [PATCH 603/969] s390/ap: Externalize AP bus specific bitmap reading function Rename hex2bitmap() to ap_hex2bitmap() and export it for external use. This function will be used by the implementation of the vfio-ap ap_config sysfs attribute. Signed-off-by: "Jason J. Herne" Reviewed-by: Tony Krowiak Reviewed-by: Harald Freudenberger Link: https://lore.kernel.org/r/20240415152555.13152-2-jjherne@linux.ibm.com Signed-off-by: Alexander Gordeev --- drivers/s390/crypto/ap_bus.c | 13 +++---------- drivers/s390/crypto/ap_bus.h | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c index 09059b3a3a42..c20b45092079 100644 --- a/drivers/s390/crypto/ap_bus.c +++ b/drivers/s390/crypto/ap_bus.c @@ -1043,15 +1043,7 @@ static struct notifier_block ap_bus_nb = { .notifier_call = ap_bus_cfg_chg, }; -/* - * hex2bitmap() - parse hex mask string and set bitmap. - * Valid strings are "0x012345678" with at least one valid hex number. - * Rest of the bitmap to the right is padded with 0. No spaces allowed - * within the string, the leading 0x may be omitted. - * Returns the bitmask with exactly the bits set as given by the hex - * string (both in big endian order). - */ -static int hex2bitmap(const char *str, unsigned long *bitmap, int bits) +int ap_hex2bitmap(const char *str, unsigned long *bitmap, int bits) { int i, n, b; @@ -1078,6 +1070,7 @@ static int hex2bitmap(const char *str, unsigned long *bitmap, int bits) return -EINVAL; return 0; } +EXPORT_SYMBOL(ap_hex2bitmap); /* * modify_bitmap() - parse bitmask argument and modify an existing @@ -1143,7 +1136,7 @@ static int ap_parse_bitmap_str(const char *str, unsigned long *bitmap, int bits, rc = modify_bitmap(str, newmap, bits); } else { memset(newmap, 0, size); - rc = hex2bitmap(str, newmap, bits); + rc = ap_hex2bitmap(str, newmap, bits); } return rc; } diff --git a/drivers/s390/crypto/ap_bus.h b/drivers/s390/crypto/ap_bus.h index 59c7ed49aa02..fdbc6fdfdf57 100644 --- a/drivers/s390/crypto/ap_bus.h +++ b/drivers/s390/crypto/ap_bus.h @@ -343,6 +343,28 @@ int ap_parse_mask_str(const char *str, unsigned long *bitmap, int bits, struct mutex *lock); +/* + * ap_hex2bitmap() - Convert a string containing a hexadecimal number (str) + * into a bitmap (bitmap) with bits set that correspond to the bits represented + * by the hex string. Input and output data is in big endian order. + * + * str - Input hex string of format "0x1234abcd". The leading "0x" is optional. + * At least one digit is required. Must be large enough to hold the number of + * bits represented by the bits parameter. + * + * bitmap - Pointer to a bitmap. Upon successful completion of this function, + * this bitmap will have bits set to match the value of str. If bitmap is longer + * than str, then the rightmost bits of bitmap are padded with zeros. Must be + * large enough to hold the number of bits represented by the bits parameter. + * + * bits - Length, in bits, of the bitmap represented by str. Must be a multiple + * of 8. + * + * Returns: 0 On success + * -EINVAL If str format is invalid or bits is not a multiple of 8. + */ +int ap_hex2bitmap(const char *str, unsigned long *bitmap, int bits); + /* * Interface to wait for the AP bus to have done one initial ap bus * scan and all detected APQNs have been bound to device drivers. From e12aa0b5b2fbf324daf62245e76083e6065ec47c Mon Sep 17 00:00:00 2001 From: "Jason J. Herne" Date: Mon, 15 Apr 2024 11:25:52 -0400 Subject: [PATCH 604/969] s390/vfio-ap: Add sysfs attr, ap_config, to export mdev state Add ap_config sysfs attribute. This will provide the means for setting or displaying the adapters, domains and control domains assigned to the vfio-ap mediated device in a single operation. This sysfs attribute is comprised of three masks: One for adapters, one for domains, and one for control domains. This attribute is intended to be used by mdevctl to query a vfio-ap mediated device's state. Signed-off-by: "Jason J. Herne" Reviewed-by: Tony Krowiak Tested-by: Matthew Rosato Link: https://lore.kernel.org/r/20240415152555.13152-3-jjherne@linux.ibm.com Signed-off-by: Alexander Gordeev --- drivers/s390/crypto/vfio_ap_ops.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/s390/crypto/vfio_ap_ops.c b/drivers/s390/crypto/vfio_ap_ops.c index fc169bc61593..e01f53a3c5b7 100644 --- a/drivers/s390/crypto/vfio_ap_ops.c +++ b/drivers/s390/crypto/vfio_ap_ops.c @@ -1570,6 +1570,32 @@ static ssize_t guest_matrix_show(struct device *dev, } static DEVICE_ATTR_RO(guest_matrix); +static ssize_t write_ap_bitmap(unsigned long *bitmap, char *buf, int offset, char sep) +{ + return sysfs_emit_at(buf, offset, "0x%016lx%016lx%016lx%016lx%c", + bitmap[0], bitmap[1], bitmap[2], bitmap[3], sep); +} + +static ssize_t ap_config_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct ap_matrix_mdev *matrix_mdev = dev_get_drvdata(dev); + int idx = 0; + + idx += write_ap_bitmap(matrix_mdev->matrix.apm, buf, idx, ','); + idx += write_ap_bitmap(matrix_mdev->matrix.aqm, buf, idx, ','); + idx += write_ap_bitmap(matrix_mdev->matrix.adm, buf, idx, '\n'); + + return idx; +} + +static ssize_t ap_config_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + return count; +} +static DEVICE_ATTR_RW(ap_config); + static struct attribute *vfio_ap_mdev_attrs[] = { &dev_attr_assign_adapter.attr, &dev_attr_unassign_adapter.attr, @@ -1577,6 +1603,7 @@ static struct attribute *vfio_ap_mdev_attrs[] = { &dev_attr_unassign_domain.attr, &dev_attr_assign_control_domain.attr, &dev_attr_unassign_control_domain.attr, + &dev_attr_ap_config.attr, &dev_attr_control_domains.attr, &dev_attr_matrix.attr, &dev_attr_guest_matrix.attr, From f3e3a4008c1d06707fd57664e3071f43b417762d Mon Sep 17 00:00:00 2001 From: "Jason J. Herne" Date: Mon, 15 Apr 2024 11:25:53 -0400 Subject: [PATCH 605/969] s390/vfio-ap: Ignore duplicate link requests in vfio_ap_mdev_link_queue vfio_ap_mdev_link_queue is changed to detect if a matrix_mdev has already linked the given queue. If so, it bails out. Signed-off-by: "Jason J. Herne" Reviewed-by: Tony Krowiak Link: https://lore.kernel.org/r/20240415152555.13152-4-jjherne@linux.ibm.com Signed-off-by: Alexander Gordeev --- drivers/s390/crypto/vfio_ap_ops.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/s390/crypto/vfio_ap_ops.c b/drivers/s390/crypto/vfio_ap_ops.c index e01f53a3c5b7..1499c2181122 100644 --- a/drivers/s390/crypto/vfio_ap_ops.c +++ b/drivers/s390/crypto/vfio_ap_ops.c @@ -794,10 +794,11 @@ err_put_vdev: static void vfio_ap_mdev_link_queue(struct ap_matrix_mdev *matrix_mdev, struct vfio_ap_queue *q) { - if (q) { - q->matrix_mdev = matrix_mdev; - hash_add(matrix_mdev->qtable.queues, &q->mdev_qnode, q->apqn); - } + if (!q || vfio_ap_mdev_get_queue(matrix_mdev, q->apqn)) + return; + + q->matrix_mdev = matrix_mdev; + hash_add(matrix_mdev->qtable.queues, &q->mdev_qnode, q->apqn); } static void vfio_ap_mdev_link_apqn(struct ap_matrix_mdev *matrix_mdev, int apqn) From 8fb456bc9f9b136d5369f8fdd54597edd692d36d Mon Sep 17 00:00:00 2001 From: "Jason J. Herne" Date: Mon, 15 Apr 2024 11:25:54 -0400 Subject: [PATCH 606/969] s390/vfio-ap: Add write support to sysfs attr ap_config Allow writing a complete set of masks to ap_config. Doing so will cause the vfio-ap driver to replace the vfio-ap mediated device's matrix masks with the given set of masks. If the given state cannot be set, then no changes are made to the vfio-ap mediated device. The format of the data written to ap_config is as follows: {amask},{dmask},{cmask}\n \n is a newline character. amask, dmask, and cmask are masks identifying which adapters, domains, and control domains should be assigned to the mediated device. The format of a mask is as follows: 0xNN..NN Where NN..NN is 64 hexadecimal characters representing a 256-bit value. The leftmost (highest order) bit represents adapter/domain 0. For an example set of masks that represent your mdev's current configuration, simply cat ap_config. This attribute is intended to be used by an mdevctl callout script supporting the mdev type vfio_ap-passthrough to atomically update a vfio-ap mediated device's state. Signed-off-by: "Jason J. Herne" Reviewed-by: Tony Krowiak Tested-by: Matthew Rosato Link: https://lore.kernel.org/r/20240415152555.13152-5-jjherne@linux.ibm.com Signed-off-by: Alexander Gordeev --- drivers/s390/crypto/vfio_ap_ops.c | 190 ++++++++++++++++++++++++-- drivers/s390/crypto/vfio_ap_private.h | 6 +- 2 files changed, 180 insertions(+), 16 deletions(-) diff --git a/drivers/s390/crypto/vfio_ap_ops.c b/drivers/s390/crypto/vfio_ap_ops.c index 1499c2181122..9f76f2d7b66e 100644 --- a/drivers/s390/crypto/vfio_ap_ops.c +++ b/drivers/s390/crypto/vfio_ap_ops.c @@ -1119,20 +1119,29 @@ static void vfio_ap_mdev_unlink_adapter(struct ap_matrix_mdev *matrix_mdev, } } -static void vfio_ap_mdev_hot_unplug_adapter(struct ap_matrix_mdev *matrix_mdev, - unsigned long apid) +static void vfio_ap_mdev_hot_unplug_adapters(struct ap_matrix_mdev *matrix_mdev, + unsigned long *apids) { struct vfio_ap_queue *q, *tmpq; struct list_head qlist; + unsigned long apid; + bool apcb_update = false; INIT_LIST_HEAD(&qlist); - vfio_ap_mdev_unlink_adapter(matrix_mdev, apid, &qlist); - if (test_bit_inv(apid, matrix_mdev->shadow_apcb.apm)) { - clear_bit_inv(apid, matrix_mdev->shadow_apcb.apm); - vfio_ap_mdev_update_guest_apcb(matrix_mdev); + for_each_set_bit_inv(apid, apids, AP_DEVICES) { + vfio_ap_mdev_unlink_adapter(matrix_mdev, apid, &qlist); + + if (test_bit_inv(apid, matrix_mdev->shadow_apcb.apm)) { + clear_bit_inv(apid, matrix_mdev->shadow_apcb.apm); + apcb_update = true; + } } + /* Only update apcb if needed to avoid impacting guest */ + if (apcb_update) + vfio_ap_mdev_update_guest_apcb(matrix_mdev); + vfio_ap_mdev_reset_qlist(&qlist); list_for_each_entry_safe(q, tmpq, &qlist, reset_qnode) { @@ -1141,6 +1150,16 @@ static void vfio_ap_mdev_hot_unplug_adapter(struct ap_matrix_mdev *matrix_mdev, } } +static void vfio_ap_mdev_hot_unplug_adapter(struct ap_matrix_mdev *matrix_mdev, + unsigned long apid) +{ + DECLARE_BITMAP(apids, AP_DEVICES); + + bitmap_zero(apids, AP_DEVICES); + set_bit_inv(apid, apids); + vfio_ap_mdev_hot_unplug_adapters(matrix_mdev, apids); +} + /** * unassign_adapter_store - parses the APID from @buf and clears the * corresponding bit in the mediated matrix device's APM @@ -1301,20 +1320,29 @@ static void vfio_ap_mdev_unlink_domain(struct ap_matrix_mdev *matrix_mdev, } } -static void vfio_ap_mdev_hot_unplug_domain(struct ap_matrix_mdev *matrix_mdev, - unsigned long apqi) +static void vfio_ap_mdev_hot_unplug_domains(struct ap_matrix_mdev *matrix_mdev, + unsigned long *apqis) { struct vfio_ap_queue *q, *tmpq; struct list_head qlist; + unsigned long apqi; + bool apcb_update = false; INIT_LIST_HEAD(&qlist); - vfio_ap_mdev_unlink_domain(matrix_mdev, apqi, &qlist); - if (test_bit_inv(apqi, matrix_mdev->shadow_apcb.aqm)) { - clear_bit_inv(apqi, matrix_mdev->shadow_apcb.aqm); - vfio_ap_mdev_update_guest_apcb(matrix_mdev); + for_each_set_bit_inv(apqi, apqis, AP_DOMAINS) { + vfio_ap_mdev_unlink_domain(matrix_mdev, apqi, &qlist); + + if (test_bit_inv(apqi, matrix_mdev->shadow_apcb.aqm)) { + clear_bit_inv(apqi, matrix_mdev->shadow_apcb.aqm); + apcb_update = true; + } } + /* Only update apcb if needed to avoid impacting guest */ + if (apcb_update) + vfio_ap_mdev_update_guest_apcb(matrix_mdev); + vfio_ap_mdev_reset_qlist(&qlist); list_for_each_entry_safe(q, tmpq, &qlist, reset_qnode) { @@ -1323,6 +1351,16 @@ static void vfio_ap_mdev_hot_unplug_domain(struct ap_matrix_mdev *matrix_mdev, } } +static void vfio_ap_mdev_hot_unplug_domain(struct ap_matrix_mdev *matrix_mdev, + unsigned long apqi) +{ + DECLARE_BITMAP(apqis, AP_DOMAINS); + + bitmap_zero(apqis, AP_DEVICES); + set_bit_inv(apqi, apqis); + vfio_ap_mdev_hot_unplug_domains(matrix_mdev, apqis); +} + /** * unassign_domain_store - parses the APQI from @buf and clears the * corresponding bit in the mediated matrix device's AQM @@ -1590,10 +1628,136 @@ static ssize_t ap_config_show(struct device *dev, struct device_attribute *attr, return idx; } +/* Number of characters needed for a complete hex mask representing the bits in .. */ +#define AP_DEVICES_STRLEN (AP_DEVICES / 4 + 3) +#define AP_DOMAINS_STRLEN (AP_DOMAINS / 4 + 3) +#define AP_CONFIG_STRLEN (AP_DEVICES_STRLEN + 2 * AP_DOMAINS_STRLEN) + +static int parse_bitmap(char **strbufptr, unsigned long *bitmap, int nbits) +{ + char *curmask; + + curmask = strsep(strbufptr, ",\n"); + if (!curmask) + return -EINVAL; + + bitmap_clear(bitmap, 0, nbits); + return ap_hex2bitmap(curmask, bitmap, nbits); +} + +static int ap_matrix_overflow_check(struct ap_matrix_mdev *matrix_mdev) +{ + unsigned long bit; + + for_each_set_bit_inv(bit, matrix_mdev->matrix.apm, AP_DEVICES) { + if (bit > matrix_mdev->matrix.apm_max) + return -ENODEV; + } + + for_each_set_bit_inv(bit, matrix_mdev->matrix.aqm, AP_DOMAINS) { + if (bit > matrix_mdev->matrix.aqm_max) + return -ENODEV; + } + + for_each_set_bit_inv(bit, matrix_mdev->matrix.adm, AP_DOMAINS) { + if (bit > matrix_mdev->matrix.adm_max) + return -ENODEV; + } + + return 0; +} + +static void ap_matrix_copy(struct ap_matrix *dst, struct ap_matrix *src) +{ + /* This check works around false positive gcc -Wstringop-overread */ + if (!src) + return; + + bitmap_copy(dst->apm, src->apm, AP_DEVICES); + bitmap_copy(dst->aqm, src->aqm, AP_DOMAINS); + bitmap_copy(dst->adm, src->adm, AP_DOMAINS); +} + static ssize_t ap_config_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - return count; + struct ap_matrix_mdev *matrix_mdev = dev_get_drvdata(dev); + struct ap_matrix m_new, m_old, m_added, m_removed; + DECLARE_BITMAP(apm_filtered, AP_DEVICES); + unsigned long newbit; + char *newbuf, *rest; + int rc = count; + bool do_update; + + newbuf = kstrndup(buf, AP_CONFIG_STRLEN, GFP_KERNEL); + if (!newbuf) + return -ENOMEM; + rest = newbuf; + + mutex_lock(&ap_perms_mutex); + get_update_locks_for_mdev(matrix_mdev); + + /* Save old state */ + ap_matrix_copy(&m_old, &matrix_mdev->matrix); + if (parse_bitmap(&rest, m_new.apm, AP_DEVICES) || + parse_bitmap(&rest, m_new.aqm, AP_DOMAINS) || + parse_bitmap(&rest, m_new.adm, AP_DOMAINS)) { + rc = -EINVAL; + goto out; + } + + bitmap_andnot(m_removed.apm, m_old.apm, m_new.apm, AP_DEVICES); + bitmap_andnot(m_removed.aqm, m_old.aqm, m_new.aqm, AP_DOMAINS); + bitmap_andnot(m_added.apm, m_new.apm, m_old.apm, AP_DEVICES); + bitmap_andnot(m_added.aqm, m_new.aqm, m_old.aqm, AP_DOMAINS); + + /* Need new bitmaps in matrix_mdev for validation */ + ap_matrix_copy(&matrix_mdev->matrix, &m_new); + + /* Ensure new state is valid, else undo new state */ + rc = vfio_ap_mdev_validate_masks(matrix_mdev); + if (rc) { + ap_matrix_copy(&matrix_mdev->matrix, &m_old); + goto out; + } + rc = ap_matrix_overflow_check(matrix_mdev); + if (rc) { + ap_matrix_copy(&matrix_mdev->matrix, &m_old); + goto out; + } + rc = count; + + /* Need old bitmaps in matrix_mdev for unplug/unlink */ + ap_matrix_copy(&matrix_mdev->matrix, &m_old); + + /* Unlink removed adapters/domains */ + vfio_ap_mdev_hot_unplug_adapters(matrix_mdev, m_removed.apm); + vfio_ap_mdev_hot_unplug_domains(matrix_mdev, m_removed.aqm); + + /* Need new bitmaps in matrix_mdev for linking new adapters/domains */ + ap_matrix_copy(&matrix_mdev->matrix, &m_new); + + /* Link newly added adapters */ + for_each_set_bit_inv(newbit, m_added.apm, AP_DEVICES) + vfio_ap_mdev_link_adapter(matrix_mdev, newbit); + + for_each_set_bit_inv(newbit, m_added.aqm, AP_DOMAINS) + vfio_ap_mdev_link_domain(matrix_mdev, newbit); + + /* filter resources not bound to vfio-ap */ + do_update = vfio_ap_mdev_filter_matrix(matrix_mdev, apm_filtered); + do_update |= vfio_ap_mdev_filter_cdoms(matrix_mdev); + + /* Apply changes to shadow apbc if things changed */ + if (do_update) { + vfio_ap_mdev_update_guest_apcb(matrix_mdev); + reset_queues_for_apids(matrix_mdev, apm_filtered); + } +out: + release_update_locks_for_mdev(matrix_mdev); + mutex_unlock(&ap_perms_mutex); + kfree(newbuf); + return rc; } static DEVICE_ATTR_RW(ap_config); diff --git a/drivers/s390/crypto/vfio_ap_private.h b/drivers/s390/crypto/vfio_ap_private.h index 98d37aa27044..437a161c8659 100644 --- a/drivers/s390/crypto/vfio_ap_private.h +++ b/drivers/s390/crypto/vfio_ap_private.h @@ -75,11 +75,11 @@ extern struct ap_matrix_dev *matrix_dev; */ struct ap_matrix { unsigned long apm_max; - DECLARE_BITMAP(apm, 256); + DECLARE_BITMAP(apm, AP_DEVICES); unsigned long aqm_max; - DECLARE_BITMAP(aqm, 256); + DECLARE_BITMAP(aqm, AP_DOMAINS); unsigned long adm_max; - DECLARE_BITMAP(adm, 256); + DECLARE_BITMAP(adm, AP_DOMAINS); }; /** From 3113a29e25fe072d6eb0abccd695d7cc72ac9b6f Mon Sep 17 00:00:00 2001 From: "Jason J. Herne" Date: Mon, 15 Apr 2024 11:25:55 -0400 Subject: [PATCH 607/969] docs: Update s390 vfio-ap doc for ap_config sysfs attribute A new sysfs attribute, ap_config, for the vfio_ap driver is documented. Signed-off-by: "Jason J. Herne" Reviewed-by: Tony Krowiak Link: https://lore.kernel.org/r/20240415152555.13152-6-jjherne@linux.ibm.com Signed-off-by: Alexander Gordeev --- Documentation/arch/s390/vfio-ap.rst | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/arch/s390/vfio-ap.rst b/Documentation/arch/s390/vfio-ap.rst index cf8533f2a8b6..ea744cbc8687 100644 --- a/Documentation/arch/s390/vfio-ap.rst +++ b/Documentation/arch/s390/vfio-ap.rst @@ -380,6 +380,36 @@ matrix device. control_domains: A read-only file for displaying the control domain numbers assigned to the vfio_ap mediated device. + ap_config: + A read/write file that, when written to, allows all three of the + vfio_ap mediated device's ap matrix masks to be replaced in one shot. + Three masks are given, one for adapters, one for domains, and one for + control domains. If the given state cannot be set then no changes are + made to the vfio-ap mediated device. + + The format of the data written to ap_config is as follows: + {amask},{dmask},{cmask}\n + + \n is a newline character. + + amask, dmask, and cmask are masks identifying which adapters, domains, + and control domains should be assigned to the mediated device. + + The format of a mask is as follows: + 0xNN..NN + + Where NN..NN is 64 hexadecimal characters representing a 256-bit value. + The leftmost (highest order) bit represents adapter/domain 0. + + For an example set of masks that represent your mdev's current + configuration, simply cat ap_config. + + Setting an adapter or domain number greater than the maximum allowed for + the system will result in an error. + + This attribute is intended to be used by automation. End users would be + better served using the respective assign/unassign attributes for + adapters, domains, and control domains. * functions: From 57ce4b27a12c827a24aaa18aa444bcb8733cb053 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Mar 2024 10:16:47 +0200 Subject: [PATCH 608/969] arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node Add firmware-name property to the WiFi device tree node to specify board-specific lookup directory. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-wcn3990-firmware-path-v2-3-f89e98e71a57@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index fca341300521..bb5191422660 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -602,6 +602,7 @@ vdd-1.3-rfa-supply = <&pm4125_l10>; vdd-3.3-ch0-supply = <&pm4125_l22>; qcom,ath10k-calibration-variant = "Thundercomm_RB1"; + firmware-name = "qcm2290"; status = "okay"; }; From 673b174b5b2ca2fb99fe52bf7bad3cc348432170 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Mar 2024 10:16:48 +0200 Subject: [PATCH 609/969] arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node Add firmware-name property to the WiFi device tree node to specify board-specific lookup directory. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-wcn3990-firmware-path-v2-4-f89e98e71a57@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 696d6d43c56b..2c39bb1b97db 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -678,6 +678,7 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; qcom,ath10k-calibration-variant = "Thundercomm_RB2"; + firmware-name = "qrb4210"; status = "okay"; }; From a6e140f174366e1644c626c7feebfc5d6c48d6db Mon Sep 17 00:00:00 2001 From: Thanh Quan Date: Tue, 16 Apr 2024 17:29:59 +0200 Subject: [PATCH 610/969] arm64: dts: renesas: r8a779h0: Add MSIOF nodes Add device nodes for the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Thanh Quan Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/62d2a1424cabda06c53541d93f6a1a5110267a71.1713280753.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 96 +++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 0e97799fa55a..530219f21295 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -826,6 +826,102 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 618>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 619>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 620>; + dmas = <&dmac1 0x45>, <&dmac1 0x44>, + <&dmac2 0x45>, <&dmac2 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + dmas = <&dmac1 0x47>, <&dmac1 0x46>, + <&dmac2 0x47>, <&dmac2 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof4: spi@e6c20000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + dmas = <&dmac1 0x49>, <&dmac1 0x48>, + <&dmac2 0x49>, <&dmac2 0x48>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof5: spi@e6c28000 { + compatible = "renesas,msiof-r8a779h0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c28000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + dmas = <&dmac1 0x4b>, <&dmac1 0x4a>, + <&dmac2 0x4b>, <&dmac2 0x4a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac1: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779h0", "renesas,rcar-gen4-dmac"; From d28970ddd1b89ebd2ec7117a007de72ec94e3d4d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 16 Apr 2024 17:40:01 +0200 Subject: [PATCH 611/969] arm64: dts: renesas: r8a779h0: Add INTC-EX node Add the device node for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car V4M (R8A779H0) SoC, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/66aba473186df9a137e7f95393209b23a5916fd1.1713281889.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 530219f21295..bd3955316a88 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -404,6 +404,22 @@ #thermal-sensor-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 611>; + }; + tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; From 5bd21a0009697011ea90ccccc9ff4b90696dbca9 Mon Sep 17 00:00:00 2001 From: Thanh Le Date: Fri, 19 Apr 2024 14:10:51 +0200 Subject: [PATCH 612/969] arm64: dts: renesas: r8a779h0: Add IPMMU nodes Add device nodes for the main and cache I/O Memory Management Unit (IPMMU) instances on the R-Car V4M (R8A779H0) SoC. Add IPMMU main and cache nodes for R-Car R8A779H0 SoC. Signed-off-by: Thanh Le Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b4701548e199ee2a72434bf73990557a63e13bd9.1713526951.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 100 ++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index bd3955316a88..f4a97e72fcde 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1028,6 +1028,106 @@ status = "disabled"; }; + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_ir: iommu@eed80000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vc: iommu@eedc0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeedc0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_3dg: iommu@eee00000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@eee80000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@eeec0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeeec0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_vip0: iommu@eef00000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeef00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779H0_PD_C4>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779h0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = , + ; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From f026b6426603d25d2c8a8c517925c7b243cf223d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 19 Apr 2024 14:10:52 +0200 Subject: [PATCH 613/969] arm64: dts: renesas: r8a779h0: Link IOMMU consumers Link all IOMMU consumers to the corresponding IPMMU instances. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/d22ff0526263937ddfa214cdc3ec116a359cbb27.1713526951.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index f4a97e72fcde..6d791024cabe 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -673,6 +673,7 @@ phy-mode = "rgmii"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; + iommus = <&ipmmu_hc 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -971,6 +972,14 @@ resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac2: dma-controller@e7351000 { @@ -996,6 +1005,10 @@ resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <8>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>; }; mmc0: mmc@ee140000 { @@ -1009,6 +1022,7 @@ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; status = "disabled"; }; From 1eba0b61be72506549e79dd11a132b5d73aed094 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 11 Apr 2024 08:45:00 +0800 Subject: [PATCH 614/969] riscv: dts: sophgo: add reserved memory node for CV1800B The original dts of CV1800B has a weird memory length as it contains reserved memory for coprocessor. Make this area a separate node so it can get the real memory length. Link: https://lore.kernel.org/r/IA1PR20MB49531F274753B04A5547DB59BB052@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts | 12 +++++++++--- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 5 +++++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts index 94e64ddce8fa..cd013588adc0 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts @@ -23,9 +23,15 @@ stdout-path = "serial0:115200n8"; }; - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x3f40000>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + coprocessor_rtos: region@83f40000 { + reg = <0x83f40000 0xc0000>; + no-map; + }; }; }; diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index baf641829e72..ec9530972ae2 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -7,6 +7,11 @@ / { compatible = "sophgo,cv1800b"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; }; &plic { From ed4d5ab179b9f0a60da87c650a31f1816db9b4b4 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:09 +0000 Subject: [PATCH 615/969] soc: mediatek: cmdq: Fix typo of CMDQ_JUMP_RELATIVE For cmdq jump command, offset 0 means relative jump and offset 1 means absolute jump. cmdq_pkt_jump() is absolute jump, so fix the typo of CMDQ_JUMP_RELATIVE in cmdq_pkt_jump(). Fixes: 946f1792d3d7 ("soc: mediatek: cmdq: add jump function") Signed-off-by: Chun-Kuang Hu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240222154120.16959-2-chunkuang.hu@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index b0cd071c4719..0b2e5690dacf 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -14,7 +14,8 @@ #define CMDQ_POLL_ENABLE_MASK BIT(0) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_REG_TYPE 1 -#define CMDQ_JUMP_RELATIVE 1 +#define CMDQ_JUMP_RELATIVE 0 +#define CMDQ_JUMP_ABSOLUTE 1 struct cmdq_instruction { union { @@ -397,7 +398,7 @@ int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr) struct cmdq_instruction inst = {}; inst.op = CMDQ_CODE_JUMP; - inst.offset = CMDQ_JUMP_RELATIVE; + inst.offset = CMDQ_JUMP_ABSOLUTE; inst.value = addr >> cmdq_get_shift_pa(((struct cmdq_client *)pkt->cl)->chan); return cmdq_pkt_append_command(pkt, inst); From ade17653411284e8f7d07279097039f8b84f85d3 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:10 +0000 Subject: [PATCH 616/969] soc: mediatek: cmdq: Add parameter shift_pa to cmdq_pkt_jump() In original design, cmdq_pkt_jump() call cmdq_get_shift_pa() every time to get shift_pa. But the shift_pa is constant value for each SoC, so client driver just need to call cmdq_get_shift_pa() once and pass shift_pa to cmdq_pkt_jump() to prevent frequent function call. Signed-off-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20240222154120.16959-3-chunkuang.hu@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 5 ++--- include/linux/soc/mediatek/mtk-cmdq.h | 6 ++++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 0b2e5690dacf..3380e56dd69b 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -393,14 +393,13 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) } EXPORT_SYMBOL(cmdq_pkt_assign); -int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr) +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) { struct cmdq_instruction inst = {}; inst.op = CMDQ_CODE_JUMP; inst.offset = CMDQ_JUMP_ABSOLUTE; - inst.value = addr >> - cmdq_get_shift_pa(((struct cmdq_client *)pkt->cl)->chan); + inst.value = addr >> shift_pa; return cmdq_pkt_append_command(pkt, inst); } EXPORT_SYMBOL(cmdq_pkt_jump); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 649955d2cf5c..72adfd867cd9 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -253,10 +253,12 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value); * a physical address which should contains more instruction. * @pkt: the CMDQ packet * @addr: physical address of target instruction buffer + * @shift_pa: shift bits of physical address in CMDQ instruction. This value + * is got by cmdq_get_shift_pa(). * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr); +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa); /** * cmdq_pkt_finalize() - Append EOC and jump command to pkt. @@ -374,7 +376,7 @@ static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) return -EINVAL; } -static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr) +static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) { return -EINVAL; } From 7218be3b6fcf00d1a3a6867aa1be6b9ab91cce45 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:11 +0000 Subject: [PATCH 617/969] soc: mediatek: cmdq: Rename cmdq_pkt_jump() to cmdq_pkt_jump_abs() In order to distinguish absolute jump and relative jump, cmdq_pkt_jump() append absolute jump command, so rename it to cmdq_pkt_jump_abs(). Signed-off-by: Chun-Kuang Hu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240222154120.16959-4-chunkuang.hu@kernel.org [Angelo: Added temporary wrapper to avoid build breakage] Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 4 ++-- include/linux/soc/mediatek/mtk-cmdq.h | 22 +++++++++++++++++----- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 3380e56dd69b..38d9077725d2 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -393,7 +393,7 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) } EXPORT_SYMBOL(cmdq_pkt_assign); -int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) +int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) { struct cmdq_instruction inst = {}; @@ -402,7 +402,7 @@ int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) inst.value = addr >> shift_pa; return cmdq_pkt_append_command(pkt, inst); } -EXPORT_SYMBOL(cmdq_pkt_jump); +EXPORT_SYMBOL(cmdq_pkt_jump_abs); int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 72adfd867cd9..961f4c521067 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -248,17 +248,24 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value); /** - * cmdq_pkt_jump() - Append jump command to the CMDQ packet, ask GCE - * to execute an instruction that change current thread PC to - * a physical address which should contains more instruction. + * cmdq_pkt_jump_abs() - Append jump command to the CMDQ packet, ask GCE + * to execute an instruction that change current thread + * PC to a absolute physical address which should + * contains more instruction. * @pkt: the CMDQ packet - * @addr: physical address of target instruction buffer + * @addr: absolute physical address of target instruction buffer * @shift_pa: shift bits of physical address in CMDQ instruction. This value * is got by cmdq_get_shift_pa(). * * Return: 0 for success; else the error code is returned */ -int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa); +int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa); + +/* This wrapper has to be removed after all users migrated to jump_abs */ +static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) +{ + return cmdq_pkt_jump_abs(pkt, addr, shift_pa); +} /** * cmdq_pkt_finalize() - Append EOC and jump command to pkt. @@ -376,6 +383,11 @@ static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) return -EINVAL; } +static inline int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) +{ + return -EINVAL; +} + static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) { return -EINVAL; From 698cdcb19579f9de005698f9dfb660ab6ec65d32 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:12 +0000 Subject: [PATCH 618/969] soc: mediatek: cmdq: Add cmdq_pkt_jump_rel() helper function cmdq_pkt_jump_rel() append relative jump command to the packet. Relative jump change PC to the target address with offset from current PC. Signed-off-by: Chun-Kuang Hu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240222154120.16959-5-chunkuang.hu@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 10 ++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 38d9077725d2..678db09983d4 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -404,6 +404,16 @@ int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) } EXPORT_SYMBOL(cmdq_pkt_jump_abs); +int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa) +{ + struct cmdq_instruction inst = { {0} }; + + inst.op = CMDQ_CODE_JUMP; + inst.value = (u32)offset >> shift_pa; + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_jump_rel); + int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { struct cmdq_instruction inst = { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 961f4c521067..cadb6a157607 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -267,6 +267,20 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_ return cmdq_pkt_jump_abs(pkt, addr, shift_pa); } +/** + * cmdq_pkt_jump_rel() - Append jump command to the CMDQ packet, ask GCE + * to execute an instruction that change current thread + * PC to a physical address with relative offset. The + * target address should contains more instruction. + * @pkt: the CMDQ packet + * @offset: relative offset of target instruction buffer from current PC. + * @shift_pa: shift bits of physical address in CMDQ instruction. This value + * is got by cmdq_get_shift_pa(). + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa); + /** * cmdq_pkt_finalize() - Append EOC and jump command to pkt. * @pkt: the CMDQ packet @@ -393,6 +407,11 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_ return -EINVAL; } +static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa) +{ + return -EINVAL; +} + static inline int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { return -EINVAL; From 3d86ced95d8c09d11c172f542edd40f58a4098fa Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:13 +0000 Subject: [PATCH 619/969] soc: mediatek: cmdq: Add cmdq_pkt_eoc() helper function cmdq_pkt_eoc() append eoc command to CMDQ packet. eoc command would ask GCE to generate IRQ. It's usually appended to the end of packet to notify all command in the packet is done. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20240222154120.16959-6-chunkuang.hu@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 10 ++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 678db09983d4..766dbafaef62 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -414,6 +414,16 @@ int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa) } EXPORT_SYMBOL(cmdq_pkt_jump_rel); +int cmdq_pkt_eoc(struct cmdq_pkt *pkt) +{ + struct cmdq_instruction inst = { {0} }; + + inst.op = CMDQ_CODE_EOC; + inst.value = CMDQ_EOC_IRQ_EN; + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_eoc); + int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { struct cmdq_instruction inst = { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index cadb6a157607..921d631361d2 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -281,6 +281,20 @@ static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_ */ int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_pa); +/** + * cmdq_pkt_eoc() - Append EOC and ask GCE to generate an IRQ at end of execution + * @pkt: The CMDQ packet + * + * Appends an End Of Code (EOC) command to the CMDQ packet and asks the GCE + * to generate an interrupt at the end of the execution of all commands in + * the pipeline. + * The EOC command is usually appended to the end of the pipeline to notify + * that all commands are done. + * + * Return: 0 for success or negative error number + */ +int cmdq_pkt_eoc(struct cmdq_pkt *pkt); + /** * cmdq_pkt_finalize() - Append EOC and jump command to pkt. * @pkt: the CMDQ packet @@ -412,6 +426,11 @@ static inline int cmdq_pkt_jump_rel(struct cmdq_pkt *pkt, s32 offset, u8 shift_p return -EINVAL; } +static inline int cmdq_pkt_eoc(struct cmdq_pkt *pkt) +{ + return -EINVAL; +} + static inline int cmdq_pkt_finalize(struct cmdq_pkt *pkt) { return -EINVAL; From 9935af96a72735e8e86aaaf06b031b014109ebc1 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:14 +0000 Subject: [PATCH 620/969] soc: mediatek: cmdq: Remove cmdq_pkt_flush_async() helper function cmdq_pkt_flush_async() is not used by all client drivers (MediaTek drm driver and MediaTek mdp3 driver), so remove it. Signed-off-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20240222154120.16959-7-chunkuang.hu@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 15 --------------- include/linux/soc/mediatek/mtk-cmdq.h | 18 ------------------ 2 files changed, 33 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 766dbafaef62..bbe41302210a 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -446,19 +446,4 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt) } EXPORT_SYMBOL(cmdq_pkt_finalize); -int cmdq_pkt_flush_async(struct cmdq_pkt *pkt) -{ - int err; - struct cmdq_client *client = (struct cmdq_client *)pkt->cl; - - err = mbox_send_message(client->chan, pkt); - if (err < 0) - return err; - /* We can send next packet immediately, so just call txdone. */ - mbox_client_txdone(client->chan, 0); - - return 0; -} -EXPORT_SYMBOL(cmdq_pkt_flush_async); - MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 921d631361d2..e79dc8c4ad41 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -303,19 +303,6 @@ int cmdq_pkt_eoc(struct cmdq_pkt *pkt); */ int cmdq_pkt_finalize(struct cmdq_pkt *pkt); -/** - * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ - * packet and call back at the end of done packet - * @pkt: the CMDQ packet - * - * Return: 0 for success; else the error code is returned - * - * Trigger CMDQ to asynchronously execute the CMDQ packet and call back - * at the end of done packet. Note that this is an ASYNC function. When the - * function returned, it may or may not be finished. - */ -int cmdq_pkt_flush_async(struct cmdq_pkt *pkt); - #else /* IS_ENABLED(CONFIG_MTK_CMDQ) */ static inline int cmdq_dev_get_client_reg(struct device *dev, @@ -436,11 +423,6 @@ static inline int cmdq_pkt_finalize(struct cmdq_pkt *pkt) return -EINVAL; } -static inline int cmdq_pkt_flush_async(struct cmdq_pkt *pkt) -{ - return -EINVAL; -} - #endif /* IS_ENABLED(CONFIG_MTK_CMDQ) */ #endif /* __MTK_CMDQ_H__ */ From b81b2d5534fc72f70d808c72b19f0e3f9df32a90 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Thu, 22 Feb 2024 15:41:15 +0000 Subject: [PATCH 621/969] soc: mediatek: cmdq: Refine cmdq_pkt_create() and cmdq_pkt_destroy() cmdq_pkt_create() and cmdq_pkt_destroy() is not suitable for client drivers so each client driver has implement its own function. This refinement would pass struct cmdq_pkt pointer into cmdq_pkt_create(). In addition, client driver has the struct cmdq_client information, so it's not necessary to store this information in struct cmdq_pkt. After this refinement, client drivers could use these helper funciton instead of implementing its own version. Signed-off-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20240222154120.16959-8-chunkuang.hu@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 24 +++++++----------------- include/linux/soc/mediatek/mtk-cmdq.h | 14 ++++++++------ 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index bbe41302210a..1a1f1b260a06 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -106,22 +106,16 @@ void cmdq_mbox_destroy(struct cmdq_client *client) } EXPORT_SYMBOL(cmdq_mbox_destroy); -struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size) +int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size) { - struct cmdq_pkt *pkt; struct device *dev; dma_addr_t dma_addr; - pkt = kzalloc(sizeof(*pkt), GFP_KERNEL); - if (!pkt) - return ERR_PTR(-ENOMEM); pkt->va_base = kzalloc(size, GFP_KERNEL); - if (!pkt->va_base) { - kfree(pkt); - return ERR_PTR(-ENOMEM); - } + if (!pkt->va_base) + return -ENOMEM; + pkt->buf_size = size; - pkt->cl = (void *)client; dev = client->chan->mbox->dev; dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size, @@ -129,24 +123,20 @@ struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size) if (dma_mapping_error(dev, dma_addr)) { dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size); kfree(pkt->va_base); - kfree(pkt); - return ERR_PTR(-ENOMEM); + return -ENOMEM; } pkt->pa_base = dma_addr; - return pkt; + return 0; } EXPORT_SYMBOL(cmdq_pkt_create); -void cmdq_pkt_destroy(struct cmdq_pkt *pkt) +void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt) { - struct cmdq_client *client = (struct cmdq_client *)pkt->cl; - dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size, DMA_TO_DEVICE); kfree(pkt->va_base); - kfree(pkt); } EXPORT_SYMBOL(cmdq_pkt_destroy); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index e79dc8c4ad41..e5335fb22a3b 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -62,17 +62,19 @@ void cmdq_mbox_destroy(struct cmdq_client *client); /** * cmdq_pkt_create() - create a CMDQ packet * @client: the CMDQ mailbox client + * @pkt: the CMDQ packet * @size: required CMDQ buffer size * - * Return: CMDQ packet pointer + * Return: 0 for success; else the error code is returned */ -struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size); +int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size); /** * cmdq_pkt_destroy() - destroy the CMDQ packet + * @client: the CMDQ mailbox client * @pkt: the CMDQ packet */ -void cmdq_pkt_destroy(struct cmdq_pkt *pkt); +void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt); /** * cmdq_pkt_write() - append write command to the CMDQ packet @@ -318,12 +320,12 @@ static inline struct cmdq_client *cmdq_mbox_create(struct device *dev, int index static inline void cmdq_mbox_destroy(struct cmdq_client *client) { } -static inline struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size) +static inline int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size) { - return ERR_PTR(-EINVAL); + return -EINVAL; } -static inline void cmdq_pkt_destroy(struct cmdq_pkt *pkt) { } +static inline void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt) { } static inline int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value) { From 49ddaa495f8b60c8c4022ebe540024dd870e4dd1 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Thu, 7 Mar 2024 09:34:55 +0800 Subject: [PATCH 622/969] soc: mediatek: mtk-cmdq: Add specific purpose register definitions for GCE Add specific purpose register definitions for GCE, so CMDQ users can use them as a buffer to store data. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240307013458.23550-2-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- include/linux/soc/mediatek/mtk-cmdq.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index e5335fb22a3b..042c61f29dc1 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -14,6 +14,15 @@ #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) +/* + * Every cmdq thread has its own SPRs (Specific Purpose Registers), + * so there are 4 * N (threads) SPRs in GCE that shares the same indexes below. + */ +#define CMDQ_THR_SPR_IDX0 (0) +#define CMDQ_THR_SPR_IDX1 (1) +#define CMDQ_THR_SPR_IDX2 (2) +#define CMDQ_THR_SPR_IDX3 (3) + struct cmdq_pkt; struct cmdq_client_reg { From 263801f8e5a159cff2dfbc2a1d9cf9f1afecfa81 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Thu, 7 Mar 2024 09:34:56 +0800 Subject: [PATCH 623/969] soc: mediatek: mtk-cmdq: Add cmdq_pkt_mem_move() function Add cmdq_pkt_mem_move() function to support CMDQ user making an instruction for moving a value from a source address to a destination address. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240307013458.23550-3-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 26 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 12 ++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 1a1f1b260a06..4cd1a25866a9 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -290,6 +290,32 @@ int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, } EXPORT_SYMBOL(cmdq_pkt_write_s_mask_value); +int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr) +{ + const u16 high_addr_reg_idx = CMDQ_THR_SPR_IDX0; + const u16 value_reg_idx = CMDQ_THR_SPR_IDX1; + int ret; + + /* read the value of src_addr into high_addr_reg_idx */ + ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(src_addr)); + if (ret < 0) + return ret; + ret = cmdq_pkt_read_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(src_addr), value_reg_idx); + if (ret < 0) + return ret; + + /* write the value of value_reg_idx into dst_addr */ + ret = cmdq_pkt_assign(pkt, high_addr_reg_idx, CMDQ_ADDR_HIGH(dst_addr)); + if (ret < 0) + return ret; + ret = cmdq_pkt_write_s(pkt, high_addr_reg_idx, CMDQ_ADDR_LOW(dst_addr), value_reg_idx); + if (ret < 0) + return ret; + + return 0; +} +EXPORT_SYMBOL(cmdq_pkt_mem_move); + int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear) { struct cmdq_instruction inst = { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 042c61f29dc1..167c8fecac30 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -184,6 +184,18 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask); +/** + * cmdq_pkt_mem_move() - append memory move command to the CMDQ packet + * @pkt: the CMDQ packet + * @src_addr: source address + * @dst_addr: destination address + * + * Appends a CMDQ command to copy the value found in `src_addr` to `dst_addr`. + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_addr); + /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet * @pkt: the CMDQ packet From 400e2fa8058e7032974a892c7336b3ea20e24cfd Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Thu, 7 Mar 2024 09:34:57 +0800 Subject: [PATCH 624/969] soc: mediatek: mtk-cmdq: Add cmdq_pkt_poll_addr() function Add cmdq_pkt_poll_addr function to support CMDQ user making an instruction for polling a specific address of hardware rigster to check the value with or without mask. POLL is a legacy operation in GCE, so it does not support SPR and CMDQ_CODE_LOGIC. To support polling the register address which doesn't have the subsys id, CMDQ users need to make an instruction with GPR and CMDQ_CODE_MASK operation to move the register address to be poll into GPR. Then users can make an POLL instruction with GPR to poll the register address assigned in previous instruction. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240307013458.23550-4-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 49 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 21 +++++++++++ 2 files changed, 70 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 4cd1a25866a9..ee55992f6491 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -12,6 +12,8 @@ #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_POLL_ENABLE_MASK BIT(0) +/* dedicate the last GPR_R15 to assign the register address to be poll */ +#define CMDQ_POLL_ADDR_GPR (15) #define CMDQ_EOC_IRQ_EN BIT(0) #define CMDQ_REG_TYPE 1 #define CMDQ_JUMP_RELATIVE 0 @@ -397,6 +399,53 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, } EXPORT_SYMBOL(cmdq_pkt_poll_mask); +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask) +{ + struct cmdq_instruction inst = { {0} }; + u8 use_mask = 0; + int ret; + + /* + * Append an MASK instruction to set the mask for following POLL instruction + * which enables use_mask bit. + */ + if (mask != GENMASK(31, 0)) { + inst.op = CMDQ_CODE_MASK; + inst.mask = ~mask; + ret = cmdq_pkt_append_command(pkt, inst); + if (ret < 0) + return ret; + use_mask = CMDQ_POLL_ENABLE_MASK; + } + + /* + * POLL is an legacy operation in GCE and it does not support SPR and CMDQ_CODE_LOGIC, + * so it can not use cmdq_pkt_assign to keep polling register address to SPR. + * If user wants to poll a register address which doesn't have a subsys id, + * user needs to use GPR and CMDQ_CODE_MASK to move polling register address to GPR. + */ + inst.op = CMDQ_CODE_MASK; + inst.dst_t = CMDQ_REG_TYPE; + inst.sop = CMDQ_POLL_ADDR_GPR; + inst.value = addr; + ret = cmdq_pkt_append_command(pkt, inst); + if (ret < 0) + return ret; + + /* Append POLL instruction to poll the register address assign to GPR previously. */ + inst.op = CMDQ_CODE_POLL; + inst.dst_t = CMDQ_REG_TYPE; + inst.sop = CMDQ_POLL_ADDR_GPR; + inst.offset = use_mask; + inst.value = value; + ret = cmdq_pkt_append_command(pkt, inst); + if (ret < 0) + return ret; + + return 0; +} +EXPORT_SYMBOL(cmdq_pkt_poll_addr); + int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) { struct cmdq_instruction inst = {}; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 167c8fecac30..f59f42e46ef1 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -270,6 +270,22 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, */ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value); +/** + * cmdq_pkt_poll_addr() - Append blocking POLL command to CMDQ packet + * @pkt: the CMDQ packet + * @addr: the hardware register address + * @value: the specified target register value + * @mask: the specified target register mask + * + * Appends a polling (POLL) command to the CMDQ packet and asks the GCE + * to execute an instruction that checks for the specified `value` (with + * or without `mask`) to appear in the specified hardware register `addr`. + * All GCE threads will be blocked by this instruction. + * + * Return: 0 for success or negative error code + */ +int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask); + /** * cmdq_pkt_jump_abs() - Append jump command to the CMDQ packet, ask GCE * to execute an instruction that change current thread @@ -421,6 +437,11 @@ static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) return -EINVAL; } +static inline int cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u32 value, u32 mask) +{ + return -EINVAL; +} + static inline int cmdq_pkt_jump_abs(struct cmdq_pkt *pkt, dma_addr_t addr, u8 shift_pa) { return -EINVAL; From 69ff68332dc5005539ac37c5c85444aaaec7c914 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Thu, 7 Mar 2024 09:34:58 +0800 Subject: [PATCH 625/969] soc: mediatek: mtk-cmdq: Add cmdq_pkt_acquire_event() function Add cmdq_pkt_acquire_event() function to support CMDQ user making an instruction for acquiring event. CMDQ users can use cmdq_pkt_acquire_event() as `mutex_lock` and cmdq_pkt_clear_event() as `mutex_unlock` to protect the global resource modified instructions between them. cmdq_pkt_acquire_event() would wait for event to be cleared. After event is cleared by cmdq_pkt_clear_event() in other GCE threads, cmdq_pkt_acquire_event() would set event and keep executing next instruction. So the mutex would work like this: cmdq_pkt_acquire_event() /* mutex lock */ /* critical secton instructions that modified global resource */ cmdq_pkt_clear_event() /* mutex unlock */ Prevent the critical section instructions from being affected by other GCE threads. Signed-off-by: Jason-JH.Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240307013458.23550-5-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index ee55992f6491..d1ca4b21587e 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -334,6 +334,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear) } EXPORT_SYMBOL(cmdq_pkt_wfe); +int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event) +{ + struct cmdq_instruction inst = {}; + + if (event >= CMDQ_MAX_EVENT) + return -EINVAL; + + inst.op = CMDQ_CODE_WFE; + inst.value = CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE | CMDQ_WFE_WAIT; + inst.event = event; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_acquire_event); + int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) { struct cmdq_instruction inst = { {0} }; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index f59f42e46ef1..d4a8e34505e6 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -206,6 +206,21 @@ int cmdq_pkt_mem_move(struct cmdq_pkt *pkt, dma_addr_t src_addr, dma_addr_t dst_ */ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear); +/** + * cmdq_pkt_acquire_event() - append acquire event command to the CMDQ packet + * @pkt: the CMDQ packet + * @event: the desired event to be acquired + * + * User can use cmdq_pkt_acquire_event() as `mutex_lock` and cmdq_pkt_clear_event() + * as `mutex_unlock` to protect some `critical section` instructions between them. + * cmdq_pkt_acquire_event() would wait for event to be cleared. + * After event is cleared by cmdq_pkt_clear_event in other GCE threads, + * cmdq_pkt_acquire_event() would set event and keep executing next instruction. + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event); + /** * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet * @pkt: the CMDQ packet From 27e69538b8fe9f025ab508178498e9502c77e900 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Thu, 29 Feb 2024 14:51:08 -0500 Subject: [PATCH 626/969] soc: mediatek: cmdq: Don't log an error when gce-client-reg is not found MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Most of the callers to this function do not require CMDQ support, it is optional, so the missing property shouldn't cause an error message. However, it could result on degraded performance, so the fact that it's missing should still be alerted. Furthermore, the callers that do require CMDQ support already log at the error level when an error is returned. Change the log message in this helper to be printed at the warning level instead. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240229-gce-client-reg-log-dbg-v2-1-4975077173d0@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-cmdq-helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index d1ca4b21587e..046522664dc1 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -58,7 +58,7 @@ int cmdq_dev_get_client_reg(struct device *dev, "mediatek,gce-client-reg", 3, idx, &spec); if (err < 0) { - dev_err(dev, + dev_warn(dev, "error %d can't parse gce-client-reg property (%d)", err, idx); From 7843b6b83d7f8059824e634ffc8d53fd3d9f4041 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 14 Mar 2024 12:30:15 +0100 Subject: [PATCH 627/969] soc: mediatek: socinfo: Advertise about unknown MediaTek SoC In case we're running on a MediaTek SoC that is not declared in the socinfo_data_table, print a message stating that and, with it, also print out the read eFuse data: this allows to easily add a new SoC in the table, granted that its actual soc/segment/marketing names are already previously known. This is especially useful when booting an already known SoC that already has socinfo support, but has a different silicon version and/or revision, hence different model information in the eFuses. Link: https://lore.kernel.org/r/20240314113015.121940-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-socinfo.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-socinfo.c index 42572e8c1520..4494cca1d075 100644 --- a/drivers/soc/mediatek/mtk-socinfo.c +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -144,7 +144,14 @@ static int mtk_socinfo_get_socinfo_data(struct mtk_socinfo *mtk_socinfop) } } - return match_socinfo_index >= 0 ? match_socinfo_index : -ENOENT; + if (match_socinfo_index < 0) { + dev_warn(mtk_socinfop->dev, + "Unknown MediaTek SoC with ID 0x%08x 0x%08x\n", + cell_data[0], cell_data[1]); + return -ENOENT; + } + + return match_socinfo_index; } static int mtk_socinfo_probe(struct platform_device *pdev) From 26bb17dae6fa3c828b53d86839589edc1a523d91 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 22 Mar 2024 10:28:43 +0100 Subject: [PATCH 628/969] soc: mediatek: mtk-mutex: Add support for MT8188 VPPSYS Add MT8188 VPPSYS0 and VPPSYS1 mutex info to driver data Link: https://lore.kernel.org/r/20240322092845.381313-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 73c256d3950b..b5af1fb5847e 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -496,6 +496,39 @@ static const unsigned int mt8188_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_MERGE5] = MT8188_MUTEX_MOD_DISP1_VPP_MERGE4, }; +static const unsigned int mt8188_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { + [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, + [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, + [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, + [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, + [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, + [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, + [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, + [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, + [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, + [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, + [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, + [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, + [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, + [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, + [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, + [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, + [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, + [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, + [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, + [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, + [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, + [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, + [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, + [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, + [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, + [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, + [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, + [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, + [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, + [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, +}; + static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, @@ -735,6 +768,13 @@ static const struct mtk_mutex_data mt8188_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt8188_vpp_mutex_driver_data = { + .mutex_sof = mt8188_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, + .mutex_table_mod = mt8188_mdp_mutex_table_mod, +}; + static const struct mtk_mutex_data mt8192_mutex_driver_data = { .mutex_mod = mt8192_mutex_mod, .mutex_sof = mt8183_mutex_sof, @@ -1089,6 +1129,7 @@ static const struct of_device_id mutex_driver_dt_match[] = { { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data }, { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data }, { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data }, + { .compatible = "mediatek,mt8188-vpp-mutex", .data = &mt8188_vpp_mutex_driver_data }, { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data }, { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data }, { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data }, From bc98f77d80d7bc3a23b3fc8a745960304a8a0c75 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 4 Apr 2024 10:20:56 +0200 Subject: [PATCH 629/969] soc: mediatek: mtk-socinfo: Add entry for MT8395AV/ZA Genio 1200 Add an entry for the MT8395 SoC with commercial name Genio 1200. Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard Reviewed-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20240404082056.93454-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-socinfo.c index 4494cca1d075..6943ab29f095 100644 --- a/drivers/soc/mediatek/mtk-socinfo.c +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -56,6 +56,7 @@ static struct socinfo_data socinfo_data_table[] = { MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EHZA", "Kompanio 1200", 0x81950304, CELL_NOT_USED), MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EZA", "Kompanio 1380", 0x81950400, CELL_NOT_USED), MTK_SOCINFO_ENTRY("MT8195", "MT8195TV/EHZA", "Kompanio 1380", 0x81950404, CELL_NOT_USED), + MTK_SOCINFO_ENTRY("MT8395", "MT8395AV/ZA", "Genio 1200", 0x83950100, CELL_NOT_USED), }; static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfop) From 8a87e1d21ef84fe68913aeba9838222422eef4d7 Mon Sep 17 00:00:00 2001 From: Jason-ch Chen Date: Tue, 9 Apr 2024 11:53:55 +0800 Subject: [PATCH 630/969] soc: mediatek: mtk-socinfo: Correct the marketing name for MT8188GV Change 'Kompanio 830' to 'Kompanio 838'. Signed-off-by: Jason-ch Chen Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20240409035355.27659-1-jason-ch.chen@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-socinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-socinfo.c b/drivers/soc/mediatek/mtk-socinfo.c index 6943ab29f095..74672a9d6d13 100644 --- a/drivers/soc/mediatek/mtk-socinfo.c +++ b/drivers/soc/mediatek/mtk-socinfo.c @@ -48,8 +48,8 @@ static struct socinfo_data socinfo_data_table[] = { MTK_SOCINFO_ENTRY("MT8183", "MT8183V/AZA", "Kompanio 500", 0x00010043, 0x00000940), MTK_SOCINFO_ENTRY("MT8186", "MT8186GV/AZA", "Kompanio 520", 0x81861001, CELL_NOT_USED), MTK_SOCINFO_ENTRY("MT8186T", "MT8186TV/AZA", "Kompanio 528", 0x81862001, CELL_NOT_USED), - MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/AZA", "Kompanio 830", 0x81880000, 0x00000010), - MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/HZA", "Kompanio 830", 0x81880000, 0x00000011), + MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/AZA", "Kompanio 838", 0x81880000, 0x00000010), + MTK_SOCINFO_ENTRY("MT8188", "MT8188GV/HZA", "Kompanio 838", 0x81880000, 0x00000011), MTK_SOCINFO_ENTRY("MT8192", "MT8192V/AZA", "Kompanio 820", 0x00001100, 0x00040080), MTK_SOCINFO_ENTRY("MT8192T", "MT8192V/ATZA", "Kompanio 828", 0x00000100, 0x000400C0), MTK_SOCINFO_ENTRY("MT8195", "MT8195GV/EZA", "Kompanio 1200", 0x81950300, CELL_NOT_USED), From 046f4c69090c120a51aa4767628afa900aac8e28 Mon Sep 17 00:00:00 2001 From: Jianfeng Wang Date: Mon, 22 Apr 2024 21:55:53 -0700 Subject: [PATCH 631/969] slub: introduce count_partial_free_approx() When reading "/proc/slabinfo", the kernel needs to report the number of free objects for each kmem_cache. The current implementation uses count_partial() to get it by scanning each kmem_cache_node's partial slab list and summing free objects from every partial slab. This process must hold per-kmem_cache_node spinlock and disable IRQ, and may take a long time. Consequently, it can block slab allocations on other CPUs and cause timeouts for network devices, when the partial list is long. In production, even NMI watchdog can be triggered due to this matter: e.g., for "buffer_head", the number of partial slabs was observed to be ~1M in one kmem_cache_node. This problem was also confirmed by others [1-3]. Iterating a partial list to get the exact count of objects can cause soft lockups for a long list with or without the lock (e.g., if preemption is disabled), and may not be very useful: the object count can change after the lock is released. The approach of maintaining free-object counters requires atomic operations on the fast path [3]. So, the fix is to introduce count_partial_free_approx(). This function can be used for getting the free object count in a kmem_cache_node's partial list. It limits the number of slabs to scan and avoids scanning the whole list by giving an approximation for a long list. Suppose the limit is N. If the list's length is not greater than N, output the exact count by traversing the list; if its length is greater than N, output an approximated count by traversing a subset of the list. The proposed method is to scan N/2 slabs from the list's head and N/2 slabs from the tail. For a partial list with ~280K slabs, benchmarks show that it performs better than just counting from the list's head, after slabs get sorted by kmem_cache_shrink(). Default the limit to 10000, as it produces an approximation within 1% of the exact count for both scenarios. Then, use count_partial_free_approx() in get_slabinfo(). Benchmarks: Diff = (exact - approximated) / exact * Normal case (w/o kmem_cache_shrink()): | MAX_TO_SCAN | Diff (count from head)| Diff (count head+tail)| | 1000 | 0.43 % | 1.09 % | | 5000 | 0.06 % | 0.37 % | | 10000 | 0.02 % | 0.16 % | | 20000 | 0.009 % | -0.003 % | * Skewed case (w/ kmem_cache_shrink()): | MAX_TO_SCAN | Diff (count from head)| Diff (count head+tail)| | 1000 | 12.46 % | 6.75 % | | 5000 | 5.38 % | 1.27 % | | 10000 | 4.99 % | 0.22 % | | 20000 | 4.86 % | -0.06 % | [1] https://lore.kernel.org/linux-mm/alpine.DEB.2.21.2003031602460.1537@www.lameter.com/T/ [2] https://lore.kernel.org/lkml/alpine.DEB.2.22.394.2008071258020.55871@www.lameter.com/T/ [3] https://lore.kernel.org/lkml/1e01092b-140d-2bab-aeba-321a74a194ee@linux.com/T/ Signed-off-by: Jianfeng Wang Acked-by: David Rientjes Signed-off-by: Vlastimil Babka --- mm/slub.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/mm/slub.c b/mm/slub.c index 62a0bb2c3147..7e2a208134c3 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -3238,6 +3238,43 @@ static unsigned long count_partial(struct kmem_cache_node *n, #endif /* CONFIG_SLUB_DEBUG || SLAB_SUPPORTS_SYSFS */ #ifdef CONFIG_SLUB_DEBUG +#define MAX_PARTIAL_TO_SCAN 10000 + +static unsigned long count_partial_free_approx(struct kmem_cache_node *n) +{ + unsigned long flags; + unsigned long x = 0; + struct slab *slab; + + spin_lock_irqsave(&n->list_lock, flags); + if (n->nr_partial <= MAX_PARTIAL_TO_SCAN) { + list_for_each_entry(slab, &n->partial, slab_list) + x += slab->objects - slab->inuse; + } else { + /* + * For a long list, approximate the total count of objects in + * it to meet the limit on the number of slabs to scan. + * Scan from both the list's head and tail for better accuracy. + */ + unsigned long scanned = 0; + + list_for_each_entry(slab, &n->partial, slab_list) { + x += slab->objects - slab->inuse; + if (++scanned == MAX_PARTIAL_TO_SCAN / 2) + break; + } + list_for_each_entry_reverse(slab, &n->partial, slab_list) { + x += slab->objects - slab->inuse; + if (++scanned == MAX_PARTIAL_TO_SCAN) + break; + } + x = mult_frac(x, n->nr_partial, scanned); + x = min(x, node_nr_objs(n)); + } + spin_unlock_irqrestore(&n->list_lock, flags); + return x; +} + static noinline void slab_out_of_memory(struct kmem_cache *s, gfp_t gfpflags, int nid) { @@ -7116,7 +7153,7 @@ void get_slabinfo(struct kmem_cache *s, struct slabinfo *sinfo) for_each_kmem_cache_node(s, node, n) { nr_slabs += node_nr_slabs(n); nr_objs += node_nr_objs(n); - nr_free += count_partial(n, count_free); + nr_free += count_partial_free_approx(n); } sinfo->active_objs = nr_objs - nr_free; From b3d8a8e870144369fdbcbb1a78878ce98532265a Mon Sep 17 00:00:00 2001 From: Jianfeng Wang Date: Mon, 22 Apr 2024 21:55:54 -0700 Subject: [PATCH 632/969] slub: use count_partial_free_approx() in slab_out_of_memory() slab_out_of_memory() uses count_partial() to get the exact count of free objects for each node. As it may get called in the slab allocation path, count_partial_free_approx() can be used to avoid the risk and overhead of traversing a long partial slab list. At the same time, show_slab_objects() still uses count_partial(). Thus, slub users can still have the option to access the exact count of objects via sysfs if the overhead is acceptable to them. Signed-off-by: Jianfeng Wang Acked-by: David Rientjes Signed-off-by: Vlastimil Babka --- mm/slub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/slub.c b/mm/slub.c index 7e2a208134c3..3aa12b9b323d 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -3301,7 +3301,7 @@ slab_out_of_memory(struct kmem_cache *s, gfp_t gfpflags, int nid) unsigned long nr_objs; unsigned long nr_free; - nr_free = count_partial(n, count_free); + nr_free = count_partial_free_approx(n); nr_slabs = node_nr_slabs(n); nr_objs = node_nr_objs(n); From 873d845a357a4d89700cb1bb5b3da68890756f50 Mon Sep 17 00:00:00 2001 From: Rong Zhang Date: Tue, 13 Feb 2024 18:58:38 +0800 Subject: [PATCH 633/969] dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn) Document Samsung Galaxy S5 China (kltechn) as a klte variant based on msm8974pro. Also including "samsung,klte" in the compatible chain as kltechn works fine with the klte DTB except for LEDs and WiFi missing. Signed-off-by: Rong Zhang Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240213110137.122737-4-i@rong.moe Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bdc4a8d5388c..6279143d0619 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -188,6 +188,13 @@ properties: - const: qcom,msm8974pro - const: qcom,msm8974 + - items: + - enum: + - samsung,kltechn + - const: samsung,klte + - const: qcom,msm8974pro + - const: qcom,msm8974 + - items: - enum: - acer,a1-724 From 16dcf57734620edea32339df2ff8875da00a34c1 Mon Sep 17 00:00:00 2001 From: Rong Zhang Date: Tue, 13 Feb 2024 18:58:36 +0800 Subject: [PATCH 634/969] ARM: dts: qcom: msm8974: Split out common part of samsung-klte Samsung Galaxy S5 has many variants. Variants that support LTE use klte* as their codename. Currently, the only supported one is the one without any suffix, namely, klte. It is known that other klte* variants have only minor differences compared to klte and can mostly work with the klte DTB. Split the common part into a common DTSI so that it can be imported in the DTS of klte and other klte* variants. Signed-off-by: Rong Zhang Tested-by: Alexey Minnekhanov Reviewed-by: Krzysztof Kozlowski Tested-by: Icenowy Zheng Link: https://lore.kernel.org/r/20240213110137.122737-2-i@rong.moe Signed-off-by: Bjorn Andersson --- .../qcom-msm8974pro-samsung-klte-common.dtsi | 812 +++++++++++++++++ .../dts/qcom/qcom-msm8974pro-samsung-klte.dts | 813 +----------------- 2 files changed, 818 insertions(+), 807 deletions(-) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi new file mode 100644 index 000000000000..11e35b34ebd6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi @@ -0,0 +1,812 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro.dtsi" +#include "pma8084.dtsi" +#include +#include +#include + +/ { + chassis-type = "handset"; + + aliases { + serial0 = &blsp1_uart1; + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_3; /* SDC2 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + key-volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + key-home { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + i2c-gpio-touchkey { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_touchkey_pins>; + + touchkey@20 { + compatible = "cypress,tm2-touchkey"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_pin>; + + vcc-supply = <&max77826_ldo15>; + vdd-supply = <&pma8084_l19>; + + linux,keycodes = ; + }; + }; + + i2c_led_gpio: i2c-gpio-led { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_led_gpioex_pins>; + + i2c-gpio,delay-us = <2>; + + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + + gpio-controller; + #gpio-cells = <2>; + + vcc-supply = <&pma8084_s4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpioex_pin>; + + reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + }; + + led-controller@30 { + compatible = "panasonic,an30259a"; + reg = <0x30>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + }; + }; + }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_panel: panel-regulator { + compatible = "regulator-fixed"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_en_pin>; + + regulator-name = "panel-vddr-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&max77826_ldo13>; + vio-supply = <&pma8084_lvs2>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c6 { + status = "okay"; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_i2c6 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + }; +}; + +&blsp2_uart2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_pins_active>; + pinctrl-1 = <&blsp2_uart2_pins_sleep>; + + bluetooth { + compatible = "brcm,bcm43540-bt"; + max-speed = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_pins>; + device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&tlmm>; + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + }; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + panel: panel@0 { + reg = <0>; + compatible = "samsung,s6e3fa2"; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_te_pin &panel_rst_pin>; + + iovdd-supply = <&pma8084_lvs4>; + vddr-supply = <&vreg_panel>; + + reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; + + vddio-supply = <&pma8084_l12>; +}; + +&pma8084_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + + touchkey_pin: touchkey-int-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + touch_pin: touchscreen-int-state { + pins = "gpio8"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; + + panel_en_pin: panel-en-state { + pins = "gpio14"; + function = "normal"; + bias-pull-up; + power-source = ; + qcom,drive-strength = ; + }; + + wlan_sleep_clk_pin: wlan-sleep-clk-state { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + qcom,drive-strength = ; + }; + + panel_rst_pin: panel-rst-state { + pins = "gpio17"; + function = "normal"; + bias-disable; + power-source = ; + qcom,drive-strength = ; + }; + + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio21"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; +}; + +&remoteproc_adsp { + status = "okay"; + cx-supply = <&pma8084_s2>; +}; + +&remoteproc_mss { + status = "okay"; + cx-supply = <&pma8084_s2>; + mss-supply = <&pma8084_s6>; + mx-supply = <&pma8084_s1>; + pll-supply = <&pma8084_l12>; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pma8084-regulators"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "okay"; + max-frequency = <100000000>; + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pma8084_s4>; + non-removable; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + interrupt-parent = <&tlmm>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; + }; +}; + +&sdhc_3 { + status = "okay"; + max-frequency = <100000000>; + vmmc-supply = <&pma8084_l21>; + vqmmc-supply = <&pma8084_l13>; + + /* + * cd-gpio is intentionally disabled. If enabled, an SD card + * present during boot is not initialized correctly. Without + * cd-gpios the driver resorts to polling, so hotplug works. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; + /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ +}; + +&tlmm { + /* This seems suspicious, but somebody with this device should look into it. */ + blsp2_uart2_pins_active: blsp2-uart2-pins-active-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "blsp_uart8"; + drive-strength = <8>; + bias-disable; + }; + + blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + bt_pins: bt-pins-state { + hostwake-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <16>; + }; + + devwake-pins { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + }; + }; + + sdc1_on: sdhc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + sdc3_on: sdc3-on-state { + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + sdhc3_cd_pin: sdc3-cd-on-state { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + sdc2_on: sdhc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + i2c_touchkey_pins: i2c-touchkey-state { + pins = "gpio95", "gpio96"; + function = "gpio"; + bias-pull-up; + }; + + i2c_led_gpioex_pins: i2c-led-gpioex-state { + function = "gpio"; + bias-pull-down; + }; + + gpioex_pin: gpioex-state { + pins = "gpio145"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + wifi_pin: wifi-state { + pins = "gpio92"; + function = "gpio"; + bias-pull-down; + }; + + panel_te_pin: panel-state { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + }; +}; + +&usb { + status = "okay"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + hnp-disable; + srp-disable; + adp-disable; +}; + +&usb_hs1_phy { + status = "okay"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts index b93539e2b87e..954665f3a9dd 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte.dts @@ -1,817 +1,16 @@ // SPDX-License-Identifier: GPL-2.0 -#include "qcom-msm8974pro.dtsi" -#include "pma8084.dtsi" -#include -#include -#include +#include "qcom-msm8974pro-samsung-klte-common.dtsi" / { model = "Samsung Galaxy S5"; compatible = "samsung,klte", "qcom,msm8974pro", "qcom,msm8974"; - chassis-type = "handset"; - - aliases { - serial0 = &blsp1_uart1; - mmc0 = &sdhc_1; /* SDC1 eMMC slot */ - mmc1 = &sdhc_3; /* SDC2 SD card slot */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_pin_a>; - - key-volume-down { - label = "volume_down"; - gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - - key-home { - label = "home_key"; - gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - wakeup-source; - debounce-interval = <15>; - }; - - key-volume-up { - label = "volume_up"; - gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - debounce-interval = <15>; - }; - }; - - i2c-gpio-touchkey { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_touchkey_pins>; - - touchkey@20 { - compatible = "cypress,tm2-touchkey"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&touchkey_pin>; - - vcc-supply = <&max77826_ldo15>; - vdd-supply = <&pma8084_l19>; - - linux,keycodes = ; - }; - }; - - i2c-gpio-led { - compatible = "i2c-gpio"; - #address-cells = <1>; - #size-cells = <0>; - scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c_led_gpioex_pins>; - - i2c-gpio,delay-us = <2>; - - gpio_expander: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - - gpio-controller; - #gpio-cells = <2>; - - vcc-supply = <&pma8084_s4>; - - pinctrl-names = "default"; - pinctrl-0 = <&gpioex_pin>; - - reset-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - }; - - led-controller@30 { - compatible = "panasonic,an30259a"; - reg = <0x30>; - - #address-cells = <1>; - #size-cells = <0>; - - led@1 { - reg = <1>; - function = LED_FUNCTION_STATUS; - color = ; - }; - - led@2 { - reg = <2>; - function = LED_FUNCTION_STATUS; - color = ; - }; - - led@3 { - reg = <3>; - function = LED_FUNCTION_STATUS; - color = ; - }; - }; - }; - - vreg_wlan: wlan-regulator { - compatible = "regulator-fixed"; - - regulator-name = "wl-reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vreg_panel: panel-regulator { - compatible = "regulator-fixed"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_en_pin>; - - regulator-name = "panel-vddr-reg"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - - gpio = <&pma8084_gpios 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vreg_vph_pwr: vreg-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph-pwr"; - - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - regulator-always-on; - }; }; -&blsp1_i2c2 { - status = "okay"; - - touchscreen@20 { - compatible = "syna,rmi4-i2c"; - reg = <0x20>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - - vdd-supply = <&max77826_ldo13>; - vio-supply = <&pma8084_lvs2>; - - pinctrl-names = "default"; - pinctrl-0 = <&touch_pin>; - - syna,startup-delay-ms = <100>; - - #address-cells = <1>; - #size-cells = <0>; - - rmi4-f01@1 { - reg = <0x1>; - syna,nosleep-mode = <1>; - }; - - rmi4-f12@12 { - reg = <0x12>; - syna,sensor-type = <1>; - }; - }; +&i2c_led_gpio { + scl-gpios = <&tlmm 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; -&blsp1_i2c6 { - status = "okay"; - - pmic@60 { - reg = <0x60>; - compatible = "maxim,max77826"; - - regulators { - max77826_ldo1: LDO1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo2: LDO2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - max77826_ldo3: LDO3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - max77826_ldo4: LDO4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo5: LDO5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo6: LDO6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo7: LDO7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo8: LDO8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo9: LDO9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_ldo10: LDO10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo11: LDO11 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2950000>; - }; - - max77826_ldo12: LDO12 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo13: LDO13 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo14: LDO14 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - max77826_ldo15: LDO15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - max77826_buck: BUCK { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - max77826_buckboost: BUCKBOOST { - regulator-min-microvolt = <3400000>; - regulator-max-microvolt = <3400000>; - }; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&blsp2_i2c6 { - status = "okay"; - - fuelgauge@36 { - compatible = "maxim,max17048"; - reg = <0x36>; - - maxim,double-soc; - maxim,rcomp = /bits/ 8 <0x56>; - - interrupt-parent = <&pma8084_gpios>; - interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-names = "default"; - pinctrl-0 = <&fuelgauge_pin>; - }; -}; - -&blsp2_uart2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_pins_active>; - pinctrl-1 = <&blsp2_uart2_pins_sleep>; - - bluetooth { - compatible = "brcm,bcm43540-bt"; - max-speed = <3000000>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_pins>; - device-wakeup-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio_expander 9 GPIO_ACTIVE_HIGH>; - interrupt-parent = <&tlmm>; - interrupts = <75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wakeup"; - }; -}; - -&gpu { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - status = "okay"; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - panel: panel@0 { - reg = <0>; - compatible = "samsung,s6e3fa2"; - - pinctrl-names = "default"; - pinctrl-0 = <&panel_te_pin &panel_rst_pin>; - - iovdd-supply = <&pma8084_lvs4>; - vddr-supply = <&vreg_panel>; - - reset-gpios = <&pma8084_gpios 17 GPIO_ACTIVE_LOW>; - - port { - panel_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - }; -}; - -&mdss_dsi0_out { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; -}; - -&mdss_dsi0_phy { - status = "okay"; - - vddio-supply = <&pma8084_l12>; -}; - -&pma8084_gpios { - gpio_keys_pin_a: gpio-keys-active-state { - pins = "gpio2", "gpio3", "gpio5"; - function = "normal"; - - bias-pull-up; - power-source = ; - }; - - touchkey_pin: touchkey-int-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; - }; - - touch_pin: touchscreen-int-state { - pins = "gpio8"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; - }; - - panel_en_pin: panel-en-state { - pins = "gpio14"; - function = "normal"; - bias-pull-up; - power-source = ; - qcom,drive-strength = ; - }; - - wlan_sleep_clk_pin: wlan-sleep-clk-state { - pins = "gpio16"; - function = "func2"; - - output-high; - power-source = ; - qcom,drive-strength = ; - }; - - panel_rst_pin: panel-rst-state { - pins = "gpio17"; - function = "normal"; - bias-disable; - power-source = ; - qcom,drive-strength = ; - }; - - fuelgauge_pin: fuelgauge-int-state { - pins = "gpio21"; - function = "normal"; - bias-disable; - input-enable; - power-source = ; - }; -}; - -&remoteproc_adsp { - status = "okay"; - cx-supply = <&pma8084_s2>; -}; - -&remoteproc_mss { - status = "okay"; - cx-supply = <&pma8084_s2>; - mss-supply = <&pma8084_s6>; - mx-supply = <&pma8084_s1>; - pll-supply = <&pma8084_l12>; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pma8084-regulators"; - - pma8084_s1: s1 { - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - pma8084_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_s4: s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_s5: s5 { - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - - pma8084_s6: s6 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - pma8084_l1: l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l3: l3 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1200000>; - }; - - pma8084_l4: l4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l8: l8 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l9: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l10: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l11: l11 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pma8084_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - pma8084_l13: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pma8084_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pma8084_l15: l15 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l16: l16 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - - pma8084_l17: l17 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l18: l18 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - }; - - pma8084_l19: l19 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l20: l20 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - pma8084_l21: l21 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-system-load = <200000>; - regulator-allow-set-load; - }; - - pma8084_l22: l22 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pma8084_l23: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - pma8084_l24: l24 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pma8084_l25: l25 { - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - }; - - pma8084_l26: l26 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2050000>; - }; - - pma8084_l27: l27 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1225000>; - }; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pma8084_l20>; - vqmmc-supply = <&pma8084_s4>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; -}; - -&sdhc_2 { - status = "okay"; - max-frequency = <100000000>; - vmmc-supply = <&vreg_wlan>; - vqmmc-supply = <&pma8084_s4>; - non-removable; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; - - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - - interrupt-parent = <&tlmm>; - interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host-wake"; - - pinctrl-names = "default"; - pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; - }; -}; - -&sdhc_3 { - status = "okay"; - max-frequency = <100000000>; - vmmc-supply = <&pma8084_l21>; - vqmmc-supply = <&pma8084_l13>; - - /* - * cd-gpio is intentionally disabled. If enabled, an SD card - * present during boot is not initialized correctly. Without - * cd-gpios the driver resorts to polling, so hotplug works. - */ - pinctrl-names = "default"; - pinctrl-0 = <&sdc3_on /* &sdhc3_cd_pin */>; - /* cd-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; */ -}; - -&tlmm { - /* This seems suspicious, but somebody with this device should look into it. */ - blsp2_uart2_pins_active: blsp2-uart2-pins-active-state { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "blsp_uart8"; - drive-strength = <8>; - bias-disable; - }; - - blsp2_uart2_pins_sleep: blsp2-uart2-pins-sleep-state { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - bt_pins: bt-pins-state { - hostwake-pins { - pins = "gpio75"; - function = "gpio"; - drive-strength = <16>; - }; - - devwake-pins { - pins = "gpio91"; - function = "gpio"; - drive-strength = <2>; - }; - }; - - sdc1_on: sdhc1-on-state { - clk-pins { - pins = "sdc1_clk"; - drive-strength = <4>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <4>; - bias-pull-up; - }; - }; - - sdc3_on: sdc3-on-state { - pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "sdc3"; - drive-strength = <8>; - bias-disable; - }; - - sdhc3_cd_pin: sdc3-cd-on-state { - pins = "gpio62"; - function = "gpio"; - - drive-strength = <2>; - bias-disable; - }; - - sdc2_on: sdhc2-on-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <6>; - bias-disable; - }; - - cmd-data-pins { - pins = "sdc2_cmd", "sdc2_data"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - i2c_touchkey_pins: i2c-touchkey-state { - pins = "gpio95", "gpio96"; - function = "gpio"; - bias-pull-up; - }; - - i2c_led_gpioex_pins: i2c-led-gpioex-state { - pins = "gpio120", "gpio121"; - function = "gpio"; - bias-pull-down; - }; - - gpioex_pin: gpioex-state { - pins = "gpio145"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - - wifi_pin: wifi-state { - pins = "gpio92"; - function = "gpio"; - bias-pull-down; - }; - - panel_te_pin: panel-state { - pins = "gpio12"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - }; -}; - -&usb { - status = "okay"; - - phys = <&usb_hs1_phy>; - phy-select = <&tcsr 0xb000 0>; - - hnp-disable; - srp-disable; - adp-disable; -}; - -&usb_hs1_phy { - status = "okay"; - - v1p8-supply = <&pma8084_l6>; - v3p3-supply = <&pma8084_l24>; - - qcom,init-seq = /bits/ 8 <0x1 0x64>; +&i2c_led_gpioex_pins { + pins = "gpio120", "gpio121"; }; From a730364f16ddc65268d828acdbf17f2a762e84be Mon Sep 17 00:00:00 2001 From: Rong Zhang Date: Tue, 13 Feb 2024 18:58:37 +0800 Subject: [PATCH 635/969] ARM: dts: qcom: msm8974-klte-common: Pin WiFi board type klte* variants have little difference in the WiFi part. Without "brcm,board-type", variant-specific NVRAM file will be probed (e.g., klte probes samsung,klte). Pin it to "samsung,klte" to allow klte* to load the same NVRAM file as klte. Signed-off-by: Rong Zhang Acked-by: Konrad Dybcio Tested-by: Icenowy Zheng Link: https://lore.kernel.org/r/20240213110137.122737-3-i@rong.moe Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi index 11e35b34ebd6..b5443fd5b425 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi @@ -661,6 +661,12 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; + /* + * Allow all klte* variants to load the same NVRAM file, + * as they have little difference in the WiFi part. + */ + brcm,board-type = "samsung,klte"; + interrupt-parent = <&tlmm>; interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; From 01088e255a27f396dcbc412e10b26cd14be5ff19 Mon Sep 17 00:00:00 2001 From: Rong Zhang Date: Tue, 13 Feb 2024 18:58:39 +0800 Subject: [PATCH 636/969] ARM: dts: qcom: msm8974: Add DTS for Samsung Galaxy S5 China (kltechn) The only difference between Samsung Galaxy S5 China (kltechn) and klte is the gpio pins of i2c_led_gpio. With pins corrected, the LEDs and WiFi are able to work properly. Signed-off-by: Rong Zhang Reviewed-by: Krzysztof Kozlowski Tested-by: Icenowy Zheng Link: https://lore.kernel.org/r/20240213110137.122737-5-i@rong.moe Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcom-msm8974pro-samsung-kltechn.dts | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-kltechn.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 5d5df062b8a0..e2e922bdc9e9 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -46,6 +46,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8974pro-fairphone-fp2.dtb \ qcom-msm8974pro-oneplus-bacon.dtb \ qcom-msm8974pro-samsung-klte.dtb \ + qcom-msm8974pro-samsung-kltechn.dtb \ qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ qcom-msm8974pro-sony-xperia-shinano-leo.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-kltechn.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-kltechn.dts new file mode 100644 index 000000000000..b902e31b16c2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-kltechn.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro-samsung-klte-common.dtsi" + +/ { + model = "Samsung Galaxy S5 China"; + compatible = "samsung,kltechn", "samsung,klte", "qcom,msm8974pro", "qcom,msm8974"; +}; + +&i2c_led_gpio { + scl-gpios = <&tlmm 61 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&tlmm 60 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c_led_gpioex_pins { + pins = "gpio60", "gpio61"; +}; From d78084cdb5a959a5759efed9b3bc3182d005073c Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Thu, 18 Apr 2024 18:26:19 +0200 Subject: [PATCH 637/969] dt-bindings: arm: rockchip: Correct the descriptions for Radxa boards Correct the descriptions of a few Radxa boards, according to the up-to-date documentation from Radxa and the detailed explanation from Naoki. [1] To sum it up, the short naming, as specified by Radxa, is preferred. [1] https://lore.kernel.org/linux-rockchip/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/ Suggested-by: FUKAUMI Naoki Signed-off-by: Dragan Simic Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/1e148d6cd4486b31b5e7f3824cf6bccf536b74c0.1713457260.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4bd033adeee4..2e284ba8732d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -722,7 +722,7 @@ properties: - const: qnap,ts433 - const: rockchip,rk3568 - - description: Radxa Compute Module 3(CM3) + - description: Radxa Compute Module 3 (CM3) items: - enum: - radxa,cm3-io @@ -784,7 +784,7 @@ properties: - const: radxa,rockpis - const: rockchip,rk3308 - - description: Radxa Rock2 Square + - description: Radxa Rock 2 Square items: - const: radxa,rock2-square - const: rockchip,rk3288 @@ -794,12 +794,12 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 - - description: Radxa ROCK 5 Model A + - description: Radxa ROCK 5A items: - const: radxa,rock-5a - const: rockchip,rk3588s - - description: Radxa ROCK 5 Model B + - description: Radxa ROCK 5B items: - const: radxa,rock-5b - const: rockchip,rk3588 From 45e831033f7a00a14f64afa1e34c476a9ff0f9f0 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Thu, 18 Apr 2024 18:26:20 +0200 Subject: [PATCH 638/969] arm64: dts: rockchip: Correct the model names for Radxa ROCK 5 boards Correct the descriptions of a few Radxa boards, according to the up-to-date documentation from Radxa and the detailed explanation from Naoki. [1] To sum it up, the short naming, as specified by Radxa, is preferred. [1] https://lore.kernel.org/linux-rockchip/B26C732A4DCEA9B3+282b8775-601b-4d4a-a513-4924b7940076@radxa.com/ Suggested-by: FUKAUMI Naoki Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/6931289a252dc2d6c7bfd2388835c5e98ba0d8c9.1713457260.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index b67b6c50d0dc..b8e15b76a8a6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -7,7 +7,7 @@ #include "rk3588.dtsi" / { - model = "Radxa ROCK 5 Model B"; + model = "Radxa ROCK 5B"; compatible = "radxa,rock-5b", "rockchip,rk3588"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index b8ca3ee4c89a..641628eeebda 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -8,7 +8,7 @@ #include "rk3588s.dtsi" / { - model = "Radxa ROCK 5 Model A"; + model = "Radxa ROCK 5A"; compatible = "radxa,rock-5a", "rockchip,rk3588s"; aliases { From fac5b3381639a504cd0e8c015242622331cc7a52 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 19 Apr 2024 18:30:18 +0800 Subject: [PATCH 639/969] dt-bindings: arm: rockchip: correct the model name for Radxa ROCK 3A According to https://radxa.com/products/rock3/3a, the name of this board should be "Radxa ROCK 3A". Suggested-by: FUKAUMI Naoki Signed-off-by: Chukun Pan Reviewed-by: Dragan Simic Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240419103019.992586-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 2e284ba8732d..742c1a85de4b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -789,7 +789,7 @@ properties: - const: radxa,rock2-square - const: rockchip,rk3288 - - description: Radxa ROCK3 Model A + - description: Radxa ROCK 3A items: - const: radxa,rock3a - const: rockchip,rk3568 From 626a479873b6a680b3227c4852bde4a1f2c17fdf Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 19 Apr 2024 18:30:19 +0800 Subject: [PATCH 640/969] arm64: dts: rockchip: correct the model name for Radxa ROCK 3A According to https://radxa.com/products/rock3/3a, the name of this board should be "Radxa ROCK 3A". Suggested-by: FUKAUMI Naoki Signed-off-by: Chukun Pan Reviewed-by: Dragan Simic Link: https://lore.kernel.org/r/20240419103019.992586-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index a5e974ea659e..ccc4119ca43a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -8,7 +8,7 @@ #include "rk3568.dtsi" / { - model = "Radxa ROCK3 Model A"; + model = "Radxa ROCK 3A"; compatible = "radxa,rock3a", "rockchip,rk3568"; aliases { From 595f06c32dcb0188bd24856984e0f1adf2a7d2eb Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 18 Apr 2024 12:36:27 -0500 Subject: [PATCH 641/969] arm64: dts: rockchip: Add USB-C Support for rk3588s-indiedroid-nova Add support for the USB-C port on the Indiedroid Nova board. This port supports USB-C DP Alt mode (not implemented yet in drivers), but works as a USB XHCI/EHCI/OHCI port. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20240418173627.1368494-1-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-indiedroid-nova.dts | 71 ++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index ce8119cbb824..0acfac2313b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -316,7 +316,7 @@ pinctrl-names = "default"; vbus-supply = <&vbus5v0_typec>; - connector { + usb_con: connector { compatible = "usb-c-connector"; data-role = "dual"; label = "USB-C"; @@ -325,6 +325,32 @@ source-pdos = ; sink-pdos = ; op-sink-microwatt = <1000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; }; }; @@ -788,6 +814,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -839,6 +873,17 @@ status = "okay"; }; +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + dwc3_0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + &usb_host1_ehci { status = "okay"; }; @@ -850,3 +895,27 @@ &usb_host2_xhci { status = "okay"; }; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,dp-lane-mux = <2 3>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; From 5adbad5c464a708a87cf5ade1bfe2ca947bb2f82 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 22 Apr 2024 16:33:56 +0200 Subject: [PATCH 642/969] arm64: dts: rockchip: move uart2 pinmux to dtsi on rk3588-tiger The association of uart2 to the q7-uart pins is part of the module itself and not the baseboard used. Therefore move the pinctrl over to the tiger dtsi. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422143356.2596414-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 1 - arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index d672198c6b64..9bdd14799eff 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -231,7 +231,6 @@ }; &uart2 { - pinctrl-0 = <&uart2m2_xfer>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 72fe696b0034..4984e36a8c2d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -688,6 +688,11 @@ status = "okay"; }; +/* Routed to UART0 on the Q7 connector */ +&uart2 { + pinctrl-0 = <&uart2m2_xfer>; +}; + /* Mule-ATtiny UPDI */ &uart4 { pinctrl-0 = <&uart4m2_xfer>; From 0ec7e1096332bc2b9bc881c21cfd234058f747b3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 23 Apr 2024 09:49:56 +0200 Subject: [PATCH 643/969] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar The Jaguar SBC provides an M.2 slot connected to the pcie3 controller. In contrast to a number of other boards the pcie-refclk is gpio-controlled, so the necessary clock and is added to the list of pcie3 clocks. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240423074956.2622318-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 4076c92668ba..3756abe38984 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -72,6 +72,27 @@ }; }; + /* + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE + * clock generator. + * The clock output is gated via the OE pin on the clock generator. + * This is modeled as a fixed-clock plus a gpio-gate-clock. + */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_refclk: pcie-refclk-clock { + compatible = "gpio-gate-clock"; + clocks = <&pcie_refclk_gen>; + #clock-cells = <0>; + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m0>; + }; + pps { compatible = "pps-gpio"; gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; @@ -358,6 +379,30 @@ status = "okay"; }; +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>; + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */ + vpcie3v3-supply = <&vcc3v3_mdot2>; + status = "okay"; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -376,6 +421,20 @@ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + pcie30x4 { + pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_perstn_m0: pcie30x4-perstn-m0 { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_waken_m0: pcie30x4-waken-m0 { + rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; + }; + }; }; &saradc { From d21ca7a353d3677f0b9c730fb37f7abd373cc9ea Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sat, 20 Apr 2024 11:42:58 +0800 Subject: [PATCH 644/969] dt-bindings: vendor-prefixes: add ArmSoM Add vendor prefix for ArmSoM (https://www.armsom.org) Signed-off-by: Jianfeng Liu Acked-by: Conor Dooley Reviewed-by: Weizhao Ouyang Link: https://lore.kernel.org/r/20240420034300.176920-2-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 59c6c6760bc0..b68f115b2388 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -151,6 +151,8 @@ patternProperties: description: ARM Ltd. "^armadeus,.*": description: ARMadeus Systems SARL + "^armsom,.*": + description: ArmSoM Technology Co., Ltd. "^arrow,.*": description: Arrow Electronics "^artesyn,.*": From 90a5434fc4b4c09fc0b5e4364e8594dabeae0d8d Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sat, 20 Apr 2024 11:42:59 +0800 Subject: [PATCH 645/969] dt-bindings: arm: rockchip: Add ArmSoM Sige7 Add devicetree binding for ArmSoM Sige7 board Signed-off-by: Jianfeng Liu Acked-by: Krzysztof Kozlowski Reviewed-by: Weizhao Ouyang Link: https://lore.kernel.org/r/20240420034300.176920-3-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 742c1a85de4b..fb0b32d3d6fd 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -49,6 +49,11 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: ArmSoM Sige7 board + items: + - const: armsom,sige7 + - const: rockchip,rk3588 + - description: Asus Tinker board items: - const: asus,rk3288-tinker From 81c828a67c78bb03ea75819c417c93c7f3d637b5 Mon Sep 17 00:00:00 2001 From: Jianfeng Liu Date: Sat, 20 Apr 2024 11:43:00 +0800 Subject: [PATCH 646/969] arm64: dts: rockchip: Add ArmSom Sige7 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specification: Rockchip Rk3588 SoC 4x ARM Cortex-A76, 4x ARM Cortex-A55 8/16/32GB Memory LPDDR4/LPDDR4x Mali G610MP4 GPU 2× MIPI-CSI Connector 1× MIPI-DSI Connector 1x M.2 Key M (PCIe 3.0 4-lanes) 2x RTL8125 2.5G Ethernet Onboard AP6275P for WIFI6/BT5 32GB/64GB/128GB eMMC MicroSD card slot 1x USB2.0, 1x USB3.0 Type-A, 1x US3.0 Type-C 1x HDMI Output, 1x type-C DP Output Functions work normally: USB2.0 Host USB3.0 Type-A Host M.2 Key M (PCIe 3.0 4-lanes) 2x RTL8125 2.5G Ethernet eMMC MicroSD card More information can be obtained from the following website https://docs.armsom.org/armsom-sige7 Signed-off-by: Jianfeng Liu Reviewed-by: Weizhao Ouyang Link: https://lore.kernel.org/r/20240420034300.176920-4-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-armsom-sige7.dts | 721 ++++++++++++++++++ 2 files changed, 722 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 7da198be8787..0624c72840b8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -111,6 +111,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts new file mode 100644 index 000000000000..98c622b27647 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts @@ -0,0 +1,721 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588.dtsi" + +/ { + model = "ArmSoM Sige7"; + compatible = "armsom,sige7", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + analog-sound { + compatible = "audio-graph-card"; + dais = <&i2s0_8ch_p0>; + label = "rk3588-es8316"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g>; + + led_green: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led_red: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +/* phy1 - right ethernet port */ +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* phy2 - WiFi */ +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* phy0 - left ethernet port */ +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_g: led-rgb-g { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-rgb-r { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; From 433dafc7b4f9f9a1011d72b32e138b598faa4807 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Tue, 23 Apr 2024 02:43:43 +0200 Subject: [PATCH 647/969] dt-bindings: arm: rockchip: Correct the descriptions for Pine64 boards Correct the descriptions of a few Pine64 boards and devices, according to their official names used on the Pine64 wiki. This ensures consistency between the officially used names and the names in the source code. Cc: Marek Kraus Signed-off-by: Dragan Simic Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/ec124dab2b1a8776aa39177ecce34babca3a50e2.1713832790.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index fb0b32d3d6fd..1bbbaf81134b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -648,7 +648,7 @@ properties: - const: phytec,rk3288-phycore-som - const: rockchip,rk3288 - - description: Pine64 PinebookPro + - description: Pine64 Pinebook Pro items: - const: pine64,pinebook-pro - const: rockchip,rk3399 @@ -661,7 +661,7 @@ properties: - const: pine64,pinenote - const: rockchip,rk3566 - - description: Pine64 PinePhonePro + - description: Pine64 PinePhone Pro items: - const: pine64,pinephone-pro - const: rockchip,rk3399 @@ -699,7 +699,7 @@ properties: - const: pine64,quartzpro64 - const: rockchip,rk3588 - - description: Pine64 SoQuartz SoM + - description: Pine64 SOQuartz items: - enum: - pine64,soquartz-blade From adbc5e6b457e773f1afa11fdb9b667cd492a7f82 Mon Sep 17 00:00:00 2001 From: Dragan Simic Date: Tue, 23 Apr 2024 02:43:44 +0200 Subject: [PATCH 648/969] arm64: dts: rockchip: Correct the model names for Pine64 boards Correct the model names of a few Pine64 boards and devices, according to their official names used on the Pine64 wiki. This ensures consistency between the officially used names and the names in the source code. Cc: Marek Kraus Signed-off-by: Dragan Simic Link: https://lore.kernel.org/r/06ce014a1dedff11a785fe523056b3b8ffdf21ee.1713832790.git.dsimic@manjaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 61f3fec5a8b1..e5709c7ee06a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -16,7 +16,7 @@ #include "rk3399-opp.dtsi" / { - model = "Pine64 PinePhonePro"; + model = "Pine64 PinePhone Pro"; compatible = "pine64,pinephone-pro", "rockchip,rk3399"; chassis-type = "handset"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 59843a7a199c..0b191d8462ad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -8,7 +8,7 @@ #include "rk3566.dtsi" / { - model = "Pine64 RK3566 Quartz64-A Board"; + model = "Pine64 Quartz64 Model A"; compatible = "pine64,quartz64-a", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts index 2d92713be2a0..26322a358d91 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -8,7 +8,7 @@ #include "rk3566.dtsi" / { - model = "Pine64 RK3566 Quartz64-B Board"; + model = "Pine64 Quartz64 Model B"; compatible = "pine64,quartz64-b", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts index fdbf1c783242..fdbb4a6a19d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts @@ -10,7 +10,7 @@ #include "rk3566-soquartz.dtsi" / { - model = "PINE64 RK3566 SOQuartz on Blade carrier board"; + model = "Pine64 SOQuartz on Blade carrier board"; compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts index 6ed3fa4aee34..2b6f0df477b6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -5,7 +5,7 @@ #include "rk3566-soquartz.dtsi" / { - model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + model = "Pine64 SOQuartz on CM4-IO carrier board"; compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts index f2095dfa4eaf..9a6a63277c3d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts @@ -5,7 +5,7 @@ #include "rk3566-soquartz.dtsi" / { - model = "PINE64 RK3566 SOQuartz on Model A carrier board"; + model = "Pine64 SOQuartz on Model A carrier board"; compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index bfb7b952f4c5..dd4e9c1893c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -8,7 +8,7 @@ #include "rk3566.dtsi" / { - model = "Pine64 RK3566 SoQuartz SOM"; + model = "Pine64 SOQuartz system on module"; compatible = "pine64,soquartz", "rockchip,rk3566"; aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index 68d432c61ea5..a3bf94d0b778 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -13,7 +13,7 @@ #include "rk3588.dtsi" / { - model = "PINE64 QuartzPro64"; + model = "Pine64 QuartzPro64"; compatible = "pine64,quartzpro64", "rockchip,rk3588"; aliases { From d7f2039e5321636069baa77ef2f1e5d22cb69a88 Mon Sep 17 00:00:00 2001 From: Jing Luo Date: Sat, 20 Apr 2024 22:03:55 +0900 Subject: [PATCH 649/969] arm64: dts: rockchip: correct gpio_pwrctrl1 typos on rk3588(s) boards gpio_pwrctrl2 gets duplicated by both rk806_dvs1_null and rk806_dvs2_null gpio_pwrctrl1 is unset. This typo appears in multiple files. Let's fix them. Note: I haven't had the chance to test them all because I don't own all of these boards (obviously). Please test if it's needed. Signed-off-by: Jing Luo Link: https://lore.kernel.org/r/20240420130355.639406-1-jing@jing.rocks Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi index def4fb0c04ef..41f5be4718c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi @@ -362,7 +362,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index c0d4a15323e2..d9bf67525e86 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -182,7 +182,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 3756abe38984..31d2f8994f85 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -516,7 +516,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 4984e36a8c2d..29f8e536de1b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -401,7 +401,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index dc08da518a76..6b9206ce4a03 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -318,7 +318,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index 25a2ae7d4827..3b2ec1d0c542 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -484,7 +484,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index 0acfac2313b1..d8c50fdcca3b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -554,7 +554,7 @@ vcca-supply = <&vcc5v0_sys>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts index 25de4362af38..73700d77eed9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -336,7 +336,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 641628eeebda..8e2a07612d17 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -414,7 +414,7 @@ #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { - pins = "gpio_pwrctrl2"; + pins = "gpio_pwrctrl1"; function = "pin_fun0"; }; From 0eb2a93518fb4728bd1d55fcd3b57fce4797ef1d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 23 Apr 2024 13:46:35 +0200 Subject: [PATCH 650/969] arm64: dts: rockchip: fix pcie-refclk frequency on rk3588 tiger The clock-generator of course only produces a 100MHz clock rate, not 1GHz. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240423114635.2637310-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 29f8e536de1b..a8565720cf53 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -46,7 +46,7 @@ pcie_refclk_gen: pcie-refclk-gen-clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1000000000>; + clock-frequency = <100000000>; }; pcie_refclk: pcie-refclk-clock { From 3482efee1144262dc839792103e6a9e29defecbc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 22 Apr 2024 18:39:49 +0200 Subject: [PATCH 651/969] arm64: dts: rockchip: fix comment for upper usb3 port The comment for the host2_xhci points to the wrong port on the board. The upper usb3 port is the correct one, so fix the comment to prevent confusion. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422163951.2604273-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 9bdd14799eff..2aa43e7430e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -239,12 +239,12 @@ status = "okay"; }; -/* host0 on Q7_USB_P2, lower usb3 port */ +/* host0 on Q7_USB_P2, upper usb3 port */ &usb_host0_ehci { status = "okay"; }; -/* host0 on Q7_USB_P2, lower usb3 port */ +/* host0 on Q7_USB_P2, upper usb3 port */ &usb_host0_ohci { status = "okay"; }; @@ -259,7 +259,7 @@ status = "okay"; }; -/* host2 on Q7_USB_P2, lower usb3 port */ +/* host2 on Q7_USB_P2, upper usb3 port */ &usb_host2_xhci { status = "okay"; }; From eabb53f5dacfd643b5255f35bad30b8f914decdc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 22 Apr 2024 18:39:50 +0200 Subject: [PATCH 652/969] arm64: dts: rockchip: add usb-id extcon on rk3588 tiger The Q7 standard specifies a usb-id pin on the connector to distiuish between host and device mode. Model this via the usb-id extcon binding. While the pin is part of the Q7 standard, so part of the module, the extcon stays disabled in the som dtsi and will only be enabled in a baseboard using it. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422163951.2604273-3-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index a8565720cf53..aebe1fedd2d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -23,6 +23,14 @@ reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; }; + extcon_usb3: extcon-usb3 { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id>; + status = "disabled"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -327,6 +335,13 @@ rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb3 { + usb3_id: usb3-id { + rockchip,pins = + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &saradc { From d7b83921d098bd76623381f75f5cd2296f1315cc Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 22 Apr 2024 18:39:51 +0200 Subject: [PATCH 653/969] arm64: dts: rockchip: add dual-role usb3 hosts to rk3588 Tiger-Haikou Apart from the host-only usb3 controller (host2) the rk3588 also provides two dual-role controllers. On the Tiger-Haikou combination these are connected to the lower usb3-host port in host-only mode and the micro-usb3 port for dual-role operation. Add the necessary controllers, phys to the Tiger-Haikou board and enable the usb-id extcon. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://lore.kernel.org/r/20240422163951.2604273-4-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-tiger-haikou.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 2aa43e7430e5..e4b7a0a4444b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -113,6 +113,16 @@ vin-supply = <&dc_12v>; }; + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; + vcc5v0_usb: vcc5v0-usb-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; @@ -137,6 +147,10 @@ status = "okay"; }; +&extcon_usb3 { + status = "okay"; +}; + &gmac0 { status = "okay"; }; @@ -199,6 +213,13 @@ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb2 { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &sdmmc { @@ -214,6 +235,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -236,6 +274,13 @@ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { status = "okay"; }; @@ -249,6 +294,13 @@ status = "okay"; }; +/* host0_xhci on Q7_USB_P1, usb3-otg port */ +&usb_host0_xhci { + dr_mode = "otg"; + extcon = <&extcon_usb3>; + status = "okay"; +}; + /* host1 on Q7_USB_P3, usb2 port */ &usb_host1_ehci { status = "okay"; @@ -259,6 +311,12 @@ status = "okay"; }; +/* host1_xhci on Q7_USB_P0, lower usb3 port */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + /* host2 on Q7_USB_P2, upper usb3 port */ &usb_host2_xhci { status = "okay"; From fefda685ec0846a1f1c2b13af2cce4cea580a768 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 25 Mar 2024 15:46:52 +0200 Subject: [PATCH 654/969] arm64: defconfig: enable REGULATOR_QCOM_USB_VBUS Enable the VBUS regulator used on Qualcomm platforms (RB1, RB2, RB5) to supply VBUS voltage to the USB-C connector. Reported-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240325-arm64-config-usb-vbus-v1-1-d14601f81d08@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 254198352f37..971df4f7de00 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -773,6 +773,7 @@ CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPMH=y CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_QCOM_USB_VBUS=m CONFIG_REGULATOR_RAA215300=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y From 2c20032e1ed34edee457c64c266d2c5bb1c52fc5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:11:24 +0200 Subject: [PATCH 655/969] arm64: dts: sc9860: add missing aon-prediv unit address Nodes with "reg" property are supposed to have unit address, as reported by dtc W=1 warning: sc9860.dtsi:210.26-216.5: Warning (simple_bus_reg): /soc/aon-prediv: simple-bus unit address format error, expected "402d0000" Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401141128.98317-1-krzk@kernel.org --- arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 2b8867fad285..9f4a4c7ecb55 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -207,7 +207,7 @@ #clock-cells = <1>; }; - aon_prediv: aon-prediv { + aon_prediv: aon-prediv@402d0000 { compatible = "sprd,sc9860-aon-prediv"; reg = <0 0x402d0000 0 0x400>; clocks = <&ext_26m>, <&pll 0>, From 74be4a8d52fd49243d7c533649d2ebbfd0f34f97 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:11:25 +0200 Subject: [PATCH 656/969] arm64: dts: sc9860: move GPIO keys to board GPIO keys are properties of a board, not SoC, because SoC physically does not have any keys or buttons. This also fixes dtc W=1 build warning: sc9860.dtsi:688.13-714.5: Warning (simple_bus_reg): /soc/gpio-keys: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401141128.98317-2-krzk@kernel.org --- arch/arm64/boot/dts/sprd/sc9860.dtsi | 28 ----------------------- arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 28 +++++++++++++++++++++++ 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 9f4a4c7ecb55..48e1b64f87b2 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -684,33 +684,5 @@ }; }; }; - - gpio-keys { - compatible = "gpio-keys"; - - key-volumedown { - label = "Volume Down Key"; - linux,code = ; - gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; - debounce-interval = <2>; - wakeup-source; - }; - - key-volumeup { - label = "Volume Up Key"; - linux,code = ; - gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - - key-power { - label = "Power Key"; - linux,code = ; - gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; - debounce-interval = <2>; - wakeup-source; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts index de468189a4fb..ed8aee9e1828 100644 --- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts @@ -34,6 +34,34 @@ stdout-path = "serial1:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + key-volumedown { + label = "Volume Down Key"; + linux,code = ; + gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>; + debounce-interval = <2>; + wakeup-source; + }; + + key-volumeup { + label = "Volume Up Key"; + linux,code = ; + gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>; + debounce-interval = <2>; + wakeup-source; + }; + + key-power { + label = "Power Key"; + linux,code = ; + gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>; + debounce-interval = <2>; + wakeup-source; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; From 653f383e7c02869792810244c94df468e4e322b1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:11:26 +0200 Subject: [PATCH 657/969] arm64: dts: sc9860: move GIC to soc node All devices on MMIO bus should be within the "soc" node. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401141128.98317-3-krzk@kernel.org --- arch/arm64/boot/dts/sprd/sc9860.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 48e1b64f87b2..c5f5481db27b 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -135,18 +135,6 @@ }; }; - gic: interrupt-controller@12001000 { - compatible = "arm,gic-400"; - reg = <0 0x12001000 0 0x1000>, - <0 0x12002000 0 0x2000>, - <0 0x12004000 0 0x2000>, - <0 0x12006000 0 0x2000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; @@ -185,6 +173,18 @@ }; soc { + gic: interrupt-controller@12001000 { + compatible = "arm,gic-400"; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x2000>, + <0 0x12004000 0 0x2000>, + <0 0x12006000 0 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + pmu_gate: pmu-gate { compatible = "sprd,sc9860-pmu-gate"; sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ From 09dddc24eb359ca82b2ae526d3b51583130f4f07 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:11:27 +0200 Subject: [PATCH 658/969] arm64: dts: whale2: add missing ap-apb unit address Nodes with "reg" property are supposed to have unit address, as reported by dtc W=1 warning: whale2.dtsi:67.10-116.5: Warning (simple_bus_reg): /soc/ap-apb: simple-bus unit address format error, expected "70000000" Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401141128.98317-4-krzk@kernel.org --- arch/arm64/boot/dts/sprd/whale2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index fece49704b5c..7068bfd2f4c3 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -64,7 +64,7 @@ reg = <0 0x70b00000 0 0x40000>; }; - ap-apb { + ap-apb@70000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From e80ab9c9782b8928c8a1392eae7ae52445bd3881 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:11:28 +0200 Subject: [PATCH 659/969] arm64: dts: sharkl3: add missing unit addresses Nodes with "reg" property are supposed to have unit address, as reported by dtc W=1 warning: sharkl3.dtsi:42.23-48.6: Warning (unit_address_vs_reg): /soc/syscon@402b0000/pmu-gate: node has a reg or ranges property, but no unit name sharkl3.dtsi:59.29-63.6: Warning (unit_address_vs_reg): /soc/syscon@402e0000/aonapb-gate: node has a reg or ranges property, but no unit name sharkl3.dtsi:74.13-80.6: Warning (unit_address_vs_reg): /soc/syscon@40353000/pll: node has a reg or ranges property, but no unit name sharkl3.dtsi:91.15-95.6: Warning (unit_address_vs_reg): /soc/syscon@40359000/mpll: node has a reg or ranges property, but no unit name sharkl3.dtsi:106.15-112.6: Warning (unit_address_vs_reg): /soc/syscon@4035c000/rpll: node has a reg or ranges property, but no unit name sharkl3.dtsi:123.15-127.6: Warning (unit_address_vs_reg): /soc/syscon@40363000/dpll: node has a reg or ranges property, but no unit name sharkl3.dtsi:138.21-142.6: Warning (unit_address_vs_reg): /soc/syscon@60800000/mm-gate: node has a reg or ranges property, but no unit name sharkl3.dtsi:153.27-159.6: Warning (unit_address_vs_reg): /soc/syscon@71300000/apapb-gate: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401141128.98317-5-krzk@kernel.org --- arch/arm64/boot/dts/sprd/sharkl3.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sharkl3.dtsi b/arch/arm64/boot/dts/sprd/sharkl3.dtsi index 206a4afdab1c..9b4ee0bdd69f 100644 --- a/arch/arm64/boot/dts/sprd/sharkl3.dtsi +++ b/arch/arm64/boot/dts/sprd/sharkl3.dtsi @@ -24,7 +24,7 @@ #size-cells = <1>; ranges = <0 0 0x20e00000 0x4000>; - apahb_gate: apahb-gate { + apahb_gate: apahb-gate@0 { compatible = "sprd,sc9863a-apahb-gate"; reg = <0x0 0x1020>; #clock-cells = <1>; @@ -39,7 +39,7 @@ #size-cells = <1>; ranges = <0 0 0x402b0000 0x4000>; - pmu_gate: pmu-gate { + pmu_gate: pmu-gate@0 { compatible = "sprd,sc9863a-pmu-gate"; reg = <0 0x1200>; clocks = <&ext_26m>; @@ -56,7 +56,7 @@ #size-cells = <1>; ranges = <0 0 0x402e0000 0x4000>; - aonapb_gate: aonapb-gate { + aonapb_gate: aonapb-gate@0 { compatible = "sprd,sc9863a-aonapb-gate"; reg = <0 0x1100>; #clock-cells = <1>; @@ -71,7 +71,7 @@ #size-cells = <1>; ranges = <0 0 0x40353000 0x3000>; - pll: pll { + pll: pll@0 { compatible = "sprd,sc9863a-pll"; reg = <0 0x100>; clocks = <&ext_26m>; @@ -88,7 +88,7 @@ #size-cells = <1>; ranges = <0 0 0x40359000 0x3000>; - mpll: mpll { + mpll: mpll@0 { compatible = "sprd,sc9863a-mpll"; reg = <0 0x100>; #clock-cells = <1>; @@ -103,7 +103,7 @@ #size-cells = <1>; ranges = <0 0 0x4035c000 0x3000>; - rpll: rpll { + rpll: rpll@0 { compatible = "sprd,sc9863a-rpll"; reg = <0 0x100>; clocks = <&ext_26m>; @@ -120,7 +120,7 @@ #size-cells = <1>; ranges = <0 0 0x40363000 0x3000>; - dpll: dpll { + dpll: dpll@0 { compatible = "sprd,sc9863a-dpll"; reg = <0 0x100>; #clock-cells = <1>; @@ -135,7 +135,7 @@ #size-cells = <1>; ranges = <0 0 0x60800000 0x3000>; - mm_gate: mm-gate { + mm_gate: mm-gate@0 { compatible = "sprd,sc9863a-mm-gate"; reg = <0 0x1100>; #clock-cells = <1>; @@ -150,7 +150,7 @@ #size-cells = <1>; ranges = <0 0 0x71300000 0x4000>; - apapb_gate: apapb-gate { + apapb_gate: apapb-gate@0 { compatible = "sprd,sc9863a-apapb-gate"; reg = <0 0x1000>; clocks = <&ext_26m>; From 345531df1cf864bbdba8d5a31c0b5519296c39cc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:49 +0200 Subject: [PATCH 660/969] arm64: dts: uniphier: ld11-global: use generic node name for audio-codec Devicetree specification expects node names to be generic, representing the class of devices. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140952.97923-1-krzk@kernel.org --- arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index da44a15a8adf..2f88e81b7ee3 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -111,7 +111,7 @@ &i2c0 { status = "okay"; - tas5707a@1d { + audio-codec@1d { compatible = "ti,tas5711"; reg = <0x1d>; reset-gpios = <&gpio UNIPHIER_GPIO_PORT(23, 4) GPIO_ACTIVE_LOW>; From 2e2798377b8b086832512dc4826b1b4c6a59aa2b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:50 +0200 Subject: [PATCH 661/969] arm64: dts: uniphier: ld11-global: drop audio codec port unit address Audio codec port does not have "reg", thus it should not have unit address, as reported by dtc W=1 warning: uniphier-ld11-global.dts:127.10-132.5: Warning (unit_address_vs_reg): /soc@0/i2c@58780000/tas5707a@1d/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140952.97923-2-krzk@kernel.org --- arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index 2f88e81b7ee3..a251c4343548 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -124,7 +124,7 @@ PVDD_C-supply = <&_vcc_reg>; PVDD_D-supply = <&_vcc_reg>; - port@0 { + port { tas_speaker: endpoint { dai-format = "i2s"; remote-endpoint = <&i2s_hpcmout1>; From e505949abaa4f616b166430719767867ce26bdc6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:51 +0200 Subject: [PATCH 662/969] arm64: dts: uniphier: ld20-global: use generic node name for audio-codec Devicetree specification expects node names to be generic, representing the class of devices. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140952.97923-3-krzk@kernel.org --- arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index a01579cb3b79..a4c86137f424 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -111,7 +111,7 @@ &i2c0 { status = "okay"; - tas5707@1b { + audio-codec@1b { compatible = "ti,tas5711"; reg = <0x1b>; reset-gpios = <&gpio UNIPHIER_GPIO_PORT(0, 0) GPIO_ACTIVE_LOW>; From 63252893550f75389616d24731c0c6051bb16a77 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:52 +0200 Subject: [PATCH 663/969] arm64: dts: uniphier: ld20-global: drop audio codec port unit address Audio codec port does not have "reg", thus it should not have unit address, as reported by dtc W=1 warning: uniphier-ld20-global.dts:127.10-132.5: Warning (unit_address_vs_reg): /soc@0/i2c@58780000/tas5707@1b/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140952.97923-4-krzk@kernel.org --- arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index a4c86137f424..79f6db2455c1 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -124,7 +124,7 @@ PVDD_C-supply = <&_vcc_reg>; PVDD_D-supply = <&_vcc_reg>; - port@0 { + port { tas_speaker: endpoint { dai-format = "i2s"; remote-endpoint = <&i2s_hpcmout1>; From 9c1998bb182d7edbddf8bef66f87ea68f8b91d67 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:10 +0200 Subject: [PATCH 664/969] arm64: dts: realtek: rtd129x: add missing unit address to soc node "soc" node has "ranges" property thus add matching unit address to fix dtc W=1 warnings: rtd129x.dtsi:51.6-122.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140912.97157-1-krzk@kernel.org --- arch/arm64/boot/dts/realtek/rtd129x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi index 39aefe66a794..ba50e292bdbb 100644 --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi @@ -48,7 +48,7 @@ clock-output-names = "osc27M"; }; - soc { + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From ed719eaa59f8bb0354dde2e37ece3e05239d0b1d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:11 +0200 Subject: [PATCH 665/969] arm64: dts: realtek: rtd139x: add missing unit address to soc node "soc" node has "ranges" property thus add matching unit address to fix dtc W=1 warnings: rtd139x.dtsi:50.6-120.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140912.97157-2-krzk@kernel.org --- arch/arm64/boot/dts/realtek/rtd139x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi index a3c10ceeb586..e8af39193e75 100644 --- a/arch/arm64/boot/dts/realtek/rtd139x.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi @@ -47,7 +47,7 @@ clock-output-names = "osc27M"; }; - soc { + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From bd54eff2c5272efeb91d37efd4d1af9270601028 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:09:12 +0200 Subject: [PATCH 666/969] arm64: dts: realtek: rtc16xx: add missing unit address to soc node "soc" node has "ranges" property thus add matching unit address to fix dtc W=1 warnings: rtd16xx.dtsi:130.6-198.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240401140912.97157-3-krzk@kernel.org --- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 34802cc62983..c10c7eaf1b03 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -127,7 +127,7 @@ #clock-cells = <0>; }; - soc { + soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From d2377018b01d33265d8908db074b4cdfaaaae26b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:41:28 +0200 Subject: [PATCH 667/969] arm64: dts: cavium: move non-MMIO node out of soc Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: thunder-88xx.dtsi:374.28-379.5: Warning (simple_bus_reg): /soc/refclk50mhz: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402194129.69481-1-krzk@kernel.org --- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 8ad31dee11a3..e29e878ee120 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -365,19 +365,19 @@ interrupts = <1 7 4>; }; + refclk50mhz: refclk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "refclk50mhz"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "refclk50mhz"; - }; - gic0: interrupt-controller@8010,00000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 74f65c57ea1fbfa7de0bb39f32e85583dee20f3c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 21:41:29 +0200 Subject: [PATCH 668/969] arm64: dts: cavium: correct unit addresses Correct several nodes' unit addresses to fix dtc W=1 warnings: thunder-88xx.dtsi:381.44-398.5: Warning (simple_bus_reg): /soc/interrupt-controller@8010,00000000: simple-bus unit address format error, expected "801000000000" thunder-88xx.dtsi:400.30-406.5: Warning (simple_bus_reg): /soc/serial@87e0,24000000: simple-bus unit address format error, expected "87e024000000" thunder-88xx.dtsi:408.30-414.5: Warning (simple_bus_reg): /soc/serial@87e0,25000000: simple-bus unit address format error, expected "87e025000000" Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402194129.69481-2-krzk@kernel.org --- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index e29e878ee120..2e65ea715800 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -378,7 +378,7 @@ #size-cells = <2>; ranges; - gic0: interrupt-controller@8010,00000000 { + gic0: interrupt-controller@801000000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; @@ -397,7 +397,7 @@ }; }; - uaa0: serial@87e0,24000000 { + uaa0: serial@87e024000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x24000000 0x0 0x1000>; interrupts = <1 21 4>; @@ -405,7 +405,7 @@ clock-names = "apb_pclk"; }; - uaa1: serial@87e0,25000000 { + uaa1: serial@87e025000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x25000000 0x0 0x1000>; interrupts = <1 22 4>; From 819deee7eb48a20024c1719c37a28034a6f3fea9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:08:17 +0200 Subject: [PATCH 669/969] arm64: dts: apm: storm: move non-MMIO node out of soc Non-MMIO devices, like fixed-clocks, should not be within simple-bus. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200818.79446-1-krzk@kernel.org --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 988928c60f15..633d8418f7cc 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -112,6 +112,13 @@ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ }; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <100000000>; + clock-output-names = "refclk"; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ @@ -137,12 +144,6 @@ #address-cells = <2>; #size-cells = <2>; ranges; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; pcppll: pcppll@17000100 { compatible = "apm,xgene-pcppll-clock"; From 1ac231d8e6d096c2ce5f71e892de8226fff2f770 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:08:18 +0200 Subject: [PATCH 670/969] arm64: dts: apm: shadowcat: move non-MMIO node out of soc Non-MMIO devices, like fixed-clocks, should not be within simple-bus. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200818.79446-2-krzk@kernel.org --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 65ebac3082e2..ea5721ea02f0 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -211,6 +211,13 @@ }; }; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <100000000>; + clock-output-names = "refclk"; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <1 12 0xff04>; @@ -236,13 +243,6 @@ #size-cells = <2>; ranges; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <1>; - clock-frequency = <100000000>; - clock-output-names = "refclk"; - }; - pmdpll: pmdpll@170000f0 { compatible = "apm,xgene-pcppll-v2-clock"; #clock-cells = <1>; From 71ef9c6212ef6b545f53b72328892251c72aa53d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:07:40 +0200 Subject: [PATCH 671/969] arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses Add io-fabric unit address, because it has ranges property. This also fixes dtc W=1 warnings: alpine-v2.dtsi:153.13-229.5: Warning (simple_bus_reg): /soc/io-fabric: simple-bus unit address format error, expected "fc000000" Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200744.79349-1-krzk@kernel.org --- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index dbf2dce8d1d6..32b6ac8a5352 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -150,7 +150,7 @@ al,msi-num-spis = <160>; }; - io-fabric { + io-fabric@fc000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 915f104e558e409048a0c5137da91c4958a694b5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:07:41 +0200 Subject: [PATCH 672/969] arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc Non-MMIO devices should not be within simple-bus, as reported by dtc W=1 warning: alpine-v2.dtsi:100.9-106.5: Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property alpine-v2.dtsi:108.7-114.5: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200744.79349-2-krzk@kernel.org --- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 33 ++++++++++++----------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index 32b6ac8a5352..5b6b58dd44cb 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -39,6 +39,7 @@ / { model = "Annapurna Labs Alpine v2"; compatible = "al,alpine-v2"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -89,6 +90,22 @@ clock-frequency = <1000000>; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -97,22 +114,6 @@ interrupt-parent = <&gic>; ranges; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = , - , - , - ; - }; - gic: interrupt-controller@f0200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ From 3eea51b918d89c967752ec555f8a156e464be274 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:07:42 +0200 Subject: [PATCH 673/969] arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses Add io-fabric unit address, because it has ranges property. This also fixes dtc W=1 warnings: alpine-v2.dtsi:153.13-229.5: Warning (simple_bus_reg): /soc/io-fabric: simple-bus unit address format error, expected "fc000000" Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200744.79349-3-krzk@kernel.org --- arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 3ea178acdddf..0ab40741f697 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -361,7 +361,7 @@ interrupt-parent = <&gic>; }; - io-fabric { + io-fabric@fc000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 653208b75eb7368e26f83c962f57646199f3c182 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:07:43 +0200 Subject: [PATCH 674/969] arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses Cache device nodes within cpus do not have "reg" property, so should not have unit address, as reported by dtc W=1 warnings: alpine-v3.dtsi:247.24-254.5: Warning (unit_address_vs_reg): /cpus/cache@0: node has a unit name, but no reg or ranges property alpine-v3.dtsi:256.26-263.5: Warning (unit_address_vs_reg): /cpus/cache@100: node has a unit name, but no reg or ranges property alpine-v3.dtsi:265.26-272.5: Warning (unit_address_vs_reg): /cpus/cache@200: node has a unit name, but no reg or ranges property alpine-v3.dtsi:274.26-281.5: Warning (unit_address_vs_reg): /cpus/cache@300: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200744.79349-4-krzk@kernel.org --- arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 0ab40741f697..3099fdfa9520 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -244,7 +244,7 @@ next-level-cache = <&cluster3_l2>; }; - cluster0_l2: cache@0 { + cluster0_l2: cache-0 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -253,7 +253,7 @@ cache-unified; }; - cluster1_l2: cache@100 { + cluster1_l2: cache-100 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -262,7 +262,7 @@ cache-unified; }; - cluster2_l2: cache@200 { + cluster2_l2: cache-200 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; @@ -271,7 +271,7 @@ cache-unified; }; - cluster3_l2: cache@300 { + cluster3_l2: cache-300 { compatible = "cache"; cache-size = <0x200000>; cache-line-size = <64>; From d5ede1dcacd898df93610d87b1e86c9920626133 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 22:07:44 +0200 Subject: [PATCH 675/969] arm64: dts: amazon: alpine-v3: correct gic unit addresses Correct gic unit addresses to fix dtc W=1 warnings: alpine-v3.dtsi:321.38-331.5: Warning (simple_bus_reg): /soc/interrupt-controller@f0000000: simple-bus unit address format error, expected "f0800000" Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240402200744.79349-5-krzk@kernel.org --- arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 3099fdfa9520..8b6156b5af65 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -318,7 +318,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f0000000 { + gic: interrupt-controller@f0800000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; From de2ba5bd3607a5e5442a5fcbdea6ee2823b72fb9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 7 Apr 2024 12:28:41 +0200 Subject: [PATCH 676/969] arm64: dts: cavium: thunder2-99xx: drop redundant reg-names There is no "reg-names" property in the PCI bindings and the value does not conform to Devicetree coding style (upper-case letters, space), so assume this was copied from downstream. This fixes dtbs_check warning: thunder2-99xx.dtb: pcie@30000000: Unevaluated properties are not allowed ('reg-names' was unexpected) Link: https://lore.kernel.org/r/20240407102841.38617-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index 3419bd252696..874d4d3a4e4f 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -103,7 +103,6 @@ /* ECAM at 0x3000_0000 - 0x4000_0000 */ reg = <0x0 0x30000000 0x0 0x10000000>; - reg-names = "PCI ECAM"; /* * PCI ranges: From 5e0705a74f8075dbefcb0ad18d6bbf909c72ebf3 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Sat, 24 Feb 2024 02:37:07 -0800 Subject: [PATCH 677/969] ARM: dts: aspeed: Add vendor prefixes to lm25066 compat strings Due to the way i2c driver matching works (falling back to the driver's id_table if of_match_table fails) this didn't actually cause any misbehavior, but let's add the vendor prefixes so things actually work the way they were intended to. Signed-off-by: Zev Weiss Reviewed-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240224103712.20864-2-zev@bewilderbeest.net Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts | 4 ++-- arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts index 4554abf0c7cd..9aa2de3723b5 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts @@ -98,14 +98,14 @@ /* IPB PMIC */ lm25066@40 { - compatible = "lm25066"; + compatible = "ti,lm25066"; reg = <0x40>; shunt-resistor-micro-ohms = <1000>; }; /* 12VSB PMIC */ lm25066@41 { - compatible = "lm25066"; + compatible = "ti,lm25066"; reg = <0x41>; shunt-resistor-micro-ohms = <10000>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts index 6600f7e9bf5e..e830fec0570f 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-delta-ahe50dc.dts @@ -14,7 +14,7 @@ #define EFUSE(hexaddr, num) \ efuse@##hexaddr { \ - compatible = "lm25066"; \ + compatible = "ti,lm25066"; \ reg = <0x##hexaddr>; \ shunt-resistor-micro-ohms = <675>; \ regulators { \ From 161e83f538183897c23644f5576b10f3c03df521 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:57 +0100 Subject: [PATCH 678/969] of: property: fw_devlink: Add support for "access-controller" Allows tracking dependencies between devices and their access controller. Signed-off-by: Gatien Chevallier Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- drivers/of/property.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/of/property.c b/drivers/of/property.c index a6358ee99b74..769ae2cf5f3c 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1252,6 +1252,7 @@ DEFINE_SIMPLE_PROP(backlight, "backlight", NULL) DEFINE_SIMPLE_PROP(panel, "panel", NULL) DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells") DEFINE_SIMPLE_PROP(post_init_providers, "post-init-providers", NULL) +DEFINE_SIMPLE_PROP(access_controllers, "access-controllers", "#access-controller-cells") DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") @@ -1359,6 +1360,7 @@ static const struct supplier_bindings of_supplier_bindings[] = { { .parse_prop = parse_msi_parent, }, { .parse_prop = parse_gpio_compat, }, { .parse_prop = parse_interrupts, }, + { .parse_prop = parse_access_controllers, }, { .parse_prop = parse_regulators, }, { .parse_prop = parse_gpio, }, { .parse_prop = parse_gpios, }, From a182084572533d48818fefc6c4af1b8f8853c447 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:58 +0100 Subject: [PATCH 679/969] bus: rifsc: introduce RIFSC firewall controller driver RIFSC is a peripheral firewall controller that filter accesses based on Arm TrustZone secure state, Arm CPU privilege execution level and Compartment IDentification of the STM32 SoC subsystems. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_rifsc.c | 252 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_rifsc.c diff --git a/MAINTAINERS b/MAINTAINERS index b896bd80d361..43ec60410657 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20815,6 +20815,7 @@ ST STM32 FIREWALL M: Gatien Chevallier S: Maintained F: drivers/bus/stm32_firewall.c +F: drivers/bus/stm32_rifsc.c ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index fc0511450ec2..e50d18e1d141 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c new file mode 100644 index 000000000000..4cf1b60014b7 --- /dev/null +++ b/drivers/bus/stm32_rifsc.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* + * RIFSC offset register + */ +#define RIFSC_RISC_SECCFGR0 0x10 +#define RIFSC_RISC_PRIVCFGR0 0x30 +#define RIFSC_RISC_PER0_CIDCFGR 0x100 +#define RIFSC_RISC_PER0_SEMCR 0x104 +#define RIFSC_RISC_HWCFGR2 0xFEC + +/* + * SEMCR register + */ +#define SEMCR_MUTEX BIT(0) + +/* + * HWCFGR2 register + */ +#define HWCFGR2_CONF1_MASK GENMASK(15, 0) +#define HWCFGR2_CONF2_MASK GENMASK(23, 16) +#define HWCFGR2_CONF3_MASK GENMASK(31, 24) + +/* + * RIFSC miscellaneous + */ +#define RIFSC_RISC_CFEN_MASK BIT(0) +#define RIFSC_RISC_SEM_EN_MASK BIT(1) +#define RIFSC_RISC_SCID_MASK GENMASK(6, 4) +#define RIFSC_RISC_SEML_SHIFT 16 +#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) +#define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24) + +#define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \ + RIFSC_RISC_SEM_EN_MASK | \ + RIFSC_RISC_SCID_MASK | \ + RIFSC_RISC_SEMWL_MASK) + +#define IDS_PER_RISC_SEC_PRIV_REGS 32 + +/* RIF miscellaneous */ +/* + * CIDCFGR register fields + */ +#define CIDCFGR_CFEN BIT(0) +#define CIDCFGR_SEMEN BIT(1) +#define CIDCFGR_SEMWL(x) BIT(RIFSC_RISC_SEML_SHIFT + (x)) + +#define SEMWL_SHIFT 16 + +/* Compartiment IDs */ +#define RIF_CID0 0x0 +#define RIF_CID1 0x1 + +static bool stm32_rifsc_is_semaphore_available(void __iomem *addr) +{ + return !(readl(addr) & SEMCR_MUTEX); +} + +static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, + int id) +{ + void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; + + writel(SEMCR_MUTEX, addr); + + /* Check that CID1 has the semaphore */ + if (stm32_rifsc_is_semaphore_available(addr) || + FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1) + return -EACCES; + + return 0; +} + +static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, + int id) +{ + void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; + + if (stm32_rifsc_is_semaphore_available(addr)) + return; + + writel(SEMCR_MUTEX, addr); + + /* Ok if another compartment takes the semaphore before the check */ + WARN_ON(!stm32_rifsc_is_semaphore_available(addr) && + FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1); +} + +static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + struct stm32_firewall_controller *rifsc_controller = ctrl; + u32 reg_offset, reg_id, sec_reg_value, cid_reg_value; + int rc; + + if (firewall_id >= rifsc_controller->max_entries) { + dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* + * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for + * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register + * per peripheral + */ + reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS; + reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS; + sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); + cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id); + + /* First check conditions for semaphore mode, which doesn't take into account static CID. */ + if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) { + if (cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT)) { + /* Static CID is irrelevant if semaphore mode */ + goto skip_cid_check; + } else { + dev_dbg(rifsc_controller->dev, + "Invalid bus semaphore configuration: index %d\n", firewall_id); + return -EACCES; + } + } + + /* + * Skip CID check if CID filtering isn't enabled or filtering is enabled on CID0, which + * corresponds to whatever CID. + */ + if (!(cid_reg_value & CIDCFGR_CFEN) || + FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0) + goto skip_cid_check; + + /* Coherency check with the CID configuration */ + if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { + dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n", + firewall_id); + return -EACCES; + } + +skip_cid_check: + /* Check security configuration */ + if (sec_reg_value & BIT(reg_offset)) { + dev_dbg(rifsc_controller->dev, + "Invalid security configuration for peripheral: %d\n", firewall_id); + return -EACCES; + } + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) { + rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id); + if (rc) { + dev_err(rifsc_controller->dev, + "Couldn't acquire semaphore for peripheral: %d\n", firewall_id); + return rc; + } + } + + return 0; +} + +static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + stm32_rif_release_semaphore(ctrl, firewall_id); +} + +static int stm32_rifsc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rifsc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_risup, nb_rimu, nb_risal; + struct resource *res; + void __iomem *mmio; + int rc; + + rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL); + if (!rifsc_controller) + return -ENOMEM; + + mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + rifsc_controller->dev = &pdev->dev; + rifsc_controller->mmio = mmio; + rifsc_controller->name = dev_driver_string(rifsc_controller->dev); + rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + rifsc_controller->grant_access = stm32_rifsc_grant_access; + rifsc_controller->release_access = stm32_rifsc_release_access; + + /* Get number of RIFSC entries*/ + nb_risup = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF1_MASK; + nb_rimu = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF2_MASK; + nb_risal = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF3_MASK; + rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal; + + platform_set_drvdata(pdev, rifsc_controller); + + rc = stm32_firewall_controller_register(rifsc_controller); + if (rc) { + dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + rc = stm32_firewall_populate_bus(rifsc_controller); + if (rc) { + dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d", + rc); + return rc; + } + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_rifsc_of_match[] = { + { .compatible = "st,stm32mp25-rifsc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match); + +static struct platform_driver stm32_rifsc_driver = { + .probe = stm32_rifsc_probe, + .driver = { + .name = "stm32-rifsc", + .of_match_table = stm32_rifsc_of_match, + }, +}; +module_platform_driver(stm32_rifsc_driver); + +MODULE_AUTHOR("Gatien Chevallier "); +MODULE_DESCRIPTION("STMicroelectronics RIFSC driver"); +MODULE_LICENSE("GPL"); From ddfade88f49d49b04930ae006ab0974eb547529c Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 24 Apr 2024 14:40:43 +0300 Subject: [PATCH 680/969] firmware: arm_ffa: Fix memory corruption in ffa_msg_send2() The "msg" pointer is a struct and msg->offset is the sizeof(*msg). The pointer here math means the memcpy() will write outside the bounds. Cast "msg" to a u8 pointer to fix this. Fixes: 02c19d84c7c5 ("firmware: arm_ffa: Add support for FFA_MSG_SEND2") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/cd5fb6b5-81fa-4a6d-b2b8-284ca704bbff@moroto.mountain Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index 26968edac5b2..b29496cac2af 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -363,7 +363,7 @@ static int ffa_msg_send2(u16 src_id, u16 dst_id, void *buf, size_t sz) msg->offset = sizeof(*msg); msg->send_recv_id = src_dst_ids; msg->size = sz; - memcpy(msg + msg->offset, buf, sz); + memcpy((u8 *)msg + msg->offset, buf, sz); /* flags = 0, sender VMID = 0 works for both physical/virtual NS */ invoke_ffa_fn((ffa_value_t){ From 7b4e7a4ff1583367bca6895b18d3572baa970ba5 Mon Sep 17 00:00:00 2001 From: Jean-Michel Hautbois Date: Wed, 24 Apr 2024 18:35:41 +0300 Subject: [PATCH 681/969] ARM: dts: bcm2835: Add Unicam CSI nodes Add both MIPI CSI-2 nodes in the bcm283x tree and take care of the Raspberry Pi / BCM2711 specific in the related files. Signed-off-by: Jean-Michel Hautbois Reviewed-by: Laurent Pinchart Signed-off-by: Stefan Wahren Link: https://lore.kernel.org/r/20240424153542.32503-6-laurent.pinchart@ideasonboard.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711.dtsi | 8 +++++++ arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi | 14 ++++++++++++ arch/arm/boot/dts/broadcom/bcm283x.dtsi | 24 +++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index 22c7f1561344..1d8f9f80f935 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -1114,6 +1114,14 @@ #address-cells = <2>; }; +&csi0 { + interrupts = ; +}; + +&csi1 { + interrupts = ; +}; + &cma { /* * arm64 reserves the CMA by default somewhere in ZONE_DMA32, diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi index 6e6dc109f0c2..e9bf41b9f5c1 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi @@ -26,6 +26,20 @@ }; }; +&csi0 { + clocks = <&clocks BCM2835_CLOCK_CAM0>, + <&firmware_clocks 4>; + clock-names = "lp", "vpu"; + power-domains = <&power RPI_POWER_DOMAIN_UNICAM0>; +}; + +&csi1 { + clocks = <&clocks BCM2835_CLOCK_CAM1>, + <&firmware_clocks 4>; + clock-names = "lp", "vpu"; + power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>; +}; + &gpio { gpioout: gpioout { brcm,pins = <6>; diff --git a/arch/arm/boot/dts/broadcom/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi index 2ca8a2505a4d..69b0919f1324 100644 --- a/arch/arm/boot/dts/broadcom/bcm283x.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm283x.dtsi @@ -454,6 +454,30 @@ status = "disabled"; }; + csi0: csi@7e800000 { + compatible = "brcm,bcm2835-unicam"; + reg = <0x7e800000 0x800>, + <0x7e802000 0x4>; + reg-names = "unicam", "cmi"; + interrupts = <2 6>; + brcm,num-data-lanes = <2>; + status = "disabled"; + port { + }; + }; + + csi1: csi@7e801000 { + compatible = "brcm,bcm2835-unicam"; + reg = <0x7e801000 0x800>, + <0x7e802004 0x4>; + reg-names = "unicam", "cmi"; + interrupts = <2 7>; + brcm,num-data-lanes = <4>; + status = "disabled"; + port { + }; + }; + i2c1: i2c@7e804000 { compatible = "brcm,bcm2835-i2c"; reg = <0x7e804000 0x1000>; From 6fd2ec4283288afe966ff3f6b3cf4e19cdd77570 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 23 Apr 2024 12:50:45 +0300 Subject: [PATCH 682/969] dt-bindings: arm: bcm: add bindings for ASUS RT-AC3200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ASUS RT-AC3200 under BCM4709 based boards. Acked-by: Krzysztof Kozlowski Signed-off-by: Arınç ÜNAL Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20240423-for-soc-asus-rt-ac3200-ac5300-v3-1-23d33cfafe7a@arinc9.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 4cc4e6754681..215bef740aca 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -53,6 +53,7 @@ properties: - description: BCM4709 based boards items: - enum: + - asus,rt-ac3200 - asus,rt-ac87u - buffalo,wxr-1900dhp - linksys,ea9200 From 5b4ce81fc1cc8c3361dfd8bc8b0a04a8c2012508 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 23 Apr 2024 12:50:46 +0300 Subject: [PATCH 683/969] dt-bindings: arm: bcm: add bindings for ASUS RT-AC5300 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ASUS RT-AC5300 under BCM47094 based boards. Acked-by: Krzysztof Kozlowski Signed-off-by: Arınç ÜNAL Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20240423-for-soc-asus-rt-ac3200-ac5300-v3-2-23d33cfafe7a@arinc9.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 215bef740aca..d925e7a3b5ef 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -68,6 +68,7 @@ properties: items: - enum: - asus,rt-ac3100 + - asus,rt-ac5300 - asus,rt-ac88u - dlink,dir-885l - dlink,dir-890l From b116239094d8ff99ecf3183729c5d459487aec34 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 23 Apr 2024 12:50:47 +0300 Subject: [PATCH 684/969] ARM: dts: BCM5301X: Add DT for ASUS RT-AC3200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the device tree for ASUS RT-AC3200 which is an AC3200 router featuring 5 Ethernet ports over the integrated Broadcom switch. Hardware info: * Processor: Broadcom BCM4709A0 dual-core @ 1.0 GHz * Switch: BCM53012 in BCM4709A0 * DDR3 RAM: 256 MB * Flash: 128 MB * 2.4GHz: BCM43602 3x3 single chip 802.11b/g/n SoC * 5GHz: BCM43602 3x3 two chips 802.11a/n/ac SoC * Ports: 4 LAN Ports, 1 WAN Port Co-developed-by: Tom Brautaset Signed-off-by: Tom Brautaset Signed-off-by: Arınç ÜNAL Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20240423-for-soc-asus-rt-ac3200-ac5300-v3-3-23d33cfafe7a@arinc9.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/Makefile | 1 + .../dts/broadcom/bcm4709-asus-rt-ac3200.dts | 150 ++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile index 7099d9560033..c61fca514775 100644 --- a/arch/arm/boot/dts/broadcom/Makefile +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -64,6 +64,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47081-luxul-xap-1410.dtb \ bcm47081-luxul-xwr-1200.dtb \ bcm47081-tplink-archer-c5-v2.dtb \ + bcm4709-asus-rt-ac3200.dtb \ bcm4709-asus-rt-ac87u.dtb \ bcm4709-buffalo-wxr-1900dhp.dtb \ bcm4709-linksys-ea9200.dtb \ diff --git a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts new file mode 100644 index 000000000000..53cb0c58f6d0 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Author: Tom Brautaset + */ + +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +#include + +/ { + compatible = "asus,rt-ac3200", "brcm,bcm4709", "brcm,bcm4708"; + model = "ASUS RT-AC3200"; + + memory@0 { + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + device_type = "memory"; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x00180000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-wifi { + label = "Wi-Fi"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-red { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-wps { + color = ; + function = LED_FUNCTION_WPS; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + nvmem-cells = <&et0macaddr 2>; + nvmem-cell-names = "mac-address"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000000 0x00080000>; + label = "boot"; + read-only; + }; + + partition@80000 { + reg = <0x00080000 0x00180000>; + label = "nvram"; + }; + + partition@200000 { + compatible = "brcm,trx"; + reg = <0x00200000 0x07e00000>; + label = "firmware"; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "wan"; + }; + + port@1 { + label = "lan1"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan3"; + }; + + port@4 { + label = "lan4"; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; From 961dedc6b4e4ed1c516bc91930d79249192cb959 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 23 Apr 2024 12:50:48 +0300 Subject: [PATCH 685/969] ARM: dts: BCM5301X: Add DT for ASUS RT-AC5300 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the device tree for ASUS RT-AC5300 which is an AC5300 router featuring 5 Ethernet ports over the integrated Broadcom switch. Hardware info: * Processor: Broadcom BCM4709C0 dual-core @ 1.4 GHz * Switch: BCM53012 in BCM4709C0 * DDR3 RAM: 512 MB * Flash: 128 MB * 2.4GHz: BCM4366 4x4 single chip 802.11b/g/n SoC * 5GHz: BCM4366 4x4 two chips 802.11a/n/ac SoC * Ports: 4 LAN Ports, 1 WAN Port Co-developed-by: Tom Brautaset Signed-off-by: Tom Brautaset Signed-off-by: Arınç ÜNAL Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20240423-for-soc-asus-rt-ac3200-ac5300-v3-4-23d33cfafe7a@arinc9.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/Makefile | 1 + .../dts/broadcom/bcm47094-asus-rt-ac5300.dts | 156 ++++++++++++++++++ 2 files changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile index c61fca514775..5881bcc95eba 100644 --- a/arch/arm/boot/dts/broadcom/Makefile +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-netgear-r8000.dtb \ bcm4709-tplink-archer-c9-v1.dtb \ bcm47094-asus-rt-ac3100.dtb \ + bcm47094-asus-rt-ac5300.dtb \ bcm47094-asus-rt-ac88u.dtb \ bcm47094-dlink-dir-885l.dtb \ bcm47094-dlink-dir-890l.dtb \ diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts new file mode 100644 index 000000000000..6c666dc7ad23 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Author: Tom Brautaset + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +#include + +/ { + compatible = "asus,rt-ac5300", "brcm,bcm47094", "brcm,bcm4708"; + model = "ASUS RT-AC5300"; + + memory@0 { + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + device_type = "memory"; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x00180000>; + + et1macaddr: et1macaddr { + #nvmem-cell-cells = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-reset { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-wifi { + label = "Wi-Fi"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-lan { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + + led-power { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-red { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-wps { + color = ; + function = LED_FUNCTION_WPS; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et1macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr 1>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + nvmem-cells = <&et1macaddr 2>; + nvmem-cell-names = "mac-address"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000000 0x00080000>; + label = "boot"; + read-only; + }; + + partition@80000 { + reg = <0x00080000 0x00180000>; + label = "nvram"; + }; + + partition@200000 { + compatible = "brcm,trx"; + reg = <0x00200000 0x07e00000>; + label = "firmware"; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; From 4dd01a3721bd0fb1e855ce881c3ee93209449e5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Tue, 23 Apr 2024 12:50:49 +0300 Subject: [PATCH 686/969] ARM: dts: BCM5301X: Conform to DTS Coding Style on ASUS RT-AC3100 & AC88U MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reorder the nodes and properties to conform to the Devicetree Sources (DTS) Coding Style. Signed-off-by: Arınç ÜNAL Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20240423-for-soc-asus-rt-ac3200-ac5300-v3-5-23d33cfafe7a@arinc9.com Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcm47094-asus-rt-ac3100.dtsi | 92 +++++++++---------- .../dts/broadcom/bcm47094-asus-rt-ac88u.dts | 73 ++++++++------- 2 files changed, 82 insertions(+), 83 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi index 9c7efb1c44f1..2cfaaabc7a6a 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi @@ -10,9 +10,9 @@ / { memory@0 { - device_type = "memory"; reg = <0x00000000 0x08000000>, <0x88000000 0x18000000>; + device_type = "memory"; }; nvram@1c080000 { @@ -20,6 +20,34 @@ reg = <0x1c080000 0x00180000>; }; + gpio-keys { + compatible = "gpio-keys"; + + button-led { + label = "Backlight"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "Reset"; + linux,code = ; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-wifi { + label = "Wi-Fi"; + linux,code = ; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + + button-wps { + label = "WPS"; + linux,code = ; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + }; + leds { compatible = "gpio-leds"; @@ -66,32 +94,29 @@ gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; }; }; +}; - gpio-keys { - compatible = "gpio-keys"; +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - button-led { - label = "Backlight"; - linux,code = ; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + partition@0 { + reg = <0x00000000 0x00080000>; + label = "boot"; + read-only; }; - button-reset { - label = "Reset"; - linux,code = ; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + partition@80000 { + reg = <0x00080000 0x00180000>; + label = "nvram"; }; - button-wifi { - label = "Wi-Fi"; - linux,code = ; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - - button-wps { - label = "WPS"; - linux,code = ; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + partition@200000 { + compatible = "brcm,trx"; + reg = <0x00200000 0x07e00000>; + label = "firmware"; }; }; }; @@ -141,28 +166,3 @@ &usb3_phy { status = "okay"; }; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - partition@80000 { - label = "nvram"; - reg = <0x00080000 0x00180000>; - }; - - partition@200000 { - label = "firmware"; - reg = <0x00200000 0x07e00000>; - compatible = "brcm,trx"; - }; - }; -}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts index c78f0c7b137d..a197f447fd97 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts @@ -19,13 +19,34 @@ switch { compatible = "realtek,rtl8365mb"; - /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; realtek,disable-leds; dsa,member = <1 0>; + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; @@ -69,31 +90,23 @@ }; }; }; - - mdio { - compatible = "realtek,smi-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - reg = <1>; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - }; - - ethphy3: ethernet-phy@3 { - reg = <3>; - }; - }; }; }; +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr 0>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + nvmem-cells = <&et1macaddr 1>; + nvmem-cell-names = "mac-address"; +}; + &srab { dsa,member = <0 0>; @@ -112,17 +125,3 @@ }; }; }; - -&gmac0 { - status = "disabled"; -}; - -&gmac1 { - nvmem-cells = <&et1macaddr 0>; - nvmem-cell-names = "mac-address"; -}; - -&gmac2 { - nvmem-cells = <&et1macaddr 1>; - nvmem-cell-names = "mac-address"; -}; From 8af2d1ab78f2342f8c4c3740ca02d86f0ebfac5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= Date: Tue, 23 Apr 2024 12:34:25 +0200 Subject: [PATCH 687/969] admin-guide/hw-vuln/core-scheduling: fix return type of PR_SCHED_CORE_GET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit sched_core_share_pid() copies the cookie to userspace with put_user(id, (u64 __user *)uaddr), expecting 64 bits of space. The "unsigned long" datatype that is documented in core-scheduling.rst however is only 32 bits large on 32 bit architectures. Document "unsigned long long" as the correct data type that is always 64bits large. This matches what the selftest cs_prctl_test.c has been doing all along. Fixes: 0159bb020ca9 ("Documentation: Add usecases, design and interface for core scheduling") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/util-linux/df7a25a0-7923-4f8b-a527-5e6f0064074d@t-8ch.de/ Signed-off-by: Thomas Weißschuh Reviewed-by: Chris Hyser Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240423-core-scheduling-cookie-v1-1-5753a35f8dfc@weissschuh.net --- Documentation/admin-guide/hw-vuln/core-scheduling.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/core-scheduling.rst b/Documentation/admin-guide/hw-vuln/core-scheduling.rst index cf1eeefdfc32..a92e10ec402e 100644 --- a/Documentation/admin-guide/hw-vuln/core-scheduling.rst +++ b/Documentation/admin-guide/hw-vuln/core-scheduling.rst @@ -67,8 +67,8 @@ arg4: will be performed for all tasks in the task group of ``pid``. arg5: - userspace pointer to an unsigned long for storing the cookie returned by - ``PR_SCHED_CORE_GET`` command. Should be 0 for all other commands. + userspace pointer to an unsigned long long for storing the cookie returned + by ``PR_SCHED_CORE_GET`` command. Should be 0 for all other commands. In order for a process to push a cookie to, or pull a cookie from a process, it is required to have the ptrace access mode: `PTRACE_MODE_READ_REALCREDS` to the From b413f9cd4cf0d8efd22245b960f9c162117f2762 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ma=C3=ADra=20Canal?= Date: Mon, 22 Apr 2024 11:18:40 -0300 Subject: [PATCH 688/969] mm: Update shuffle documentation to match its current state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 839195352d82 ("mm/shuffle: remove dynamic reconfiguration") removed the dynamic reconfiguration capabilities from the shuffle page allocator. This means that, now, we don't have any perspective of an "autodetection of memory-side-cache" that triggers the enablement of the shuffle page allocator. Therefore, let the documentation reflect that the only way to enable the shuffle page allocator is by setting `page_alloc.shuffle=1`. Signed-off-by: Maíra Canal Reviewed-by: David Hildenbrand Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240422142007.1062231-1-mcanal@igalia.com --- Documentation/admin-guide/kernel-parameters.txt | 10 ++++------ mm/Kconfig | 7 +++---- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 623fce7d5fcd..e6809b85b211 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4169,13 +4169,11 @@ page_alloc.shuffle= [KNL] Boolean flag to control whether the page allocator - should randomize its free lists. The randomization may - be automatically enabled if the kernel detects it is - running on a platform with a direct-mapped memory-side - cache, and this parameter can be used to - override/disable that behavior. The state of the flag - can be read from sysfs at: + should randomize its free lists. This parameter can be + used to enable/disable page randomization. The state of + the flag can be read from sysfs at: /sys/module/page_alloc/parameters/shuffle. + This parameter is only available if CONFIG_SHUFFLE_PAGE_ALLOCATOR=y. page_owner= [KNL,EARLY] Boot-time page_owner enabling option. Storage of the information about who allocated diff --git a/mm/Kconfig b/mm/Kconfig index b1448aa81e15..f30a18a0e37d 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -333,10 +333,9 @@ config SHUFFLE_PAGE_ALLOCATOR While the randomization improves cache utilization it may negatively impact workloads on platforms without a cache. For - this reason, by default, the randomization is enabled only - after runtime detection of a direct-mapped memory-side-cache. - Otherwise, the randomization may be force enabled with the - 'page_alloc.shuffle' kernel command line parameter. + this reason, by default, the randomization is not enabled even + if SHUFFLE_PAGE_ALLOCATOR=y. The randomization may be force enabled + with the 'page_alloc.shuffle' kernel command line parameter. Say Y if unsure. From 3adde4c5f230e462211b41f1eae37077a0bbd8cd Mon Sep 17 00:00:00 2001 From: Haoyang Liu Date: Sun, 21 Apr 2024 22:20:20 +0800 Subject: [PATCH 689/969] docs/zh_CN: Add dev-tools/kcov Chinese translation Translate dev-tools/kcov into Chinese and add it in dev-tools/zh_CN/index.rst. Signed-off-by: Haoyang Liu Reviewed-by: Yanteng Si Reviewed-by: Alex Shi Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240421142021.19504-1-tttturtleruss@hust.edu.cn --- .../translations/zh_CN/dev-tools/index.rst | 2 +- .../translations/zh_CN/dev-tools/kcov.rst | 359 ++++++++++++++++++ 2 files changed, 360 insertions(+), 1 deletion(-) create mode 100644 Documentation/translations/zh_CN/dev-tools/kcov.rst diff --git a/Documentation/translations/zh_CN/dev-tools/index.rst b/Documentation/translations/zh_CN/dev-tools/index.rst index 51e5b3e724c1..fa900f5beb68 100644 --- a/Documentation/translations/zh_CN/dev-tools/index.rst +++ b/Documentation/translations/zh_CN/dev-tools/index.rst @@ -22,6 +22,7 @@ Documentation/translations/zh_CN/dev-tools/testing-overview.rst sparse gcov kasan + kcov ubsan kmemleak gdb-kernel-debugging @@ -29,7 +30,6 @@ Documentation/translations/zh_CN/dev-tools/testing-overview.rst Todolist: - coccinelle - - kcov - kcsan - kfence - kgdb diff --git a/Documentation/translations/zh_CN/dev-tools/kcov.rst b/Documentation/translations/zh_CN/dev-tools/kcov.rst new file mode 100644 index 000000000000..629154df7121 --- /dev/null +++ b/Documentation/translations/zh_CN/dev-tools/kcov.rst @@ -0,0 +1,359 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: ../disclaimer-zh_CN.rst + +:Original: Documentation/dev-tools/kcov.rst +:Translator: 刘浩阳 Haoyang Liu + +KCOV: 用于模糊测试的代码覆盖率 +============================== + +KCOV 以一种适用于覆盖率引导的模糊测试的形式收集和暴露内核代码覆盖率信息。 +一个正在运行的内核的覆盖率数据可以通过 ``kcov`` 调试文件导出。覆盖率的收集是基 +于任务启用的，因此 KCOV 可以精确捕获单个系统调用的覆盖率。 + +要注意的是 KCOV 不是为了收集尽可能多的覆盖率数据。而是为了收集相对稳定的覆盖率 +，这是系统调用输入的函数。为了完成这个目标，它不收集软硬中断的覆盖率（除非移除 +覆盖率收集被启用，见下文）以及内核中固有的不确定部分的覆盖率（如调度器，锁定） + +除了收集代码覆盖率，KCOV 还收集操作数比较的覆盖率。见 "操作数比较收集" 一节 +查看详细信息。 + +除了从系统调用处理器收集覆盖率数据，KCOV 还从后台内核或软中断任务中执行的内核 +被标注的部分收集覆盖率。见 "远程覆盖率收集" 一节查看详细信息。 + +先决条件 +-------- + +KCOV 依赖编译器插桩，要求 GCC 6.1.0 及更高版本或者内核支持的任意版本的 Clang。 + +收集操作数比较的覆盖率需要 GCC 8+ 或者 Clang。 + +为了启用 KCOV，需要使用如下参数配置内核:: + + CONFIG_KCOV=y + +为了启用操作数比较覆盖率的收集，使用如下参数:: + + CONFIG_KCOV_ENABLE_COMPARISONS=y + +覆盖率数据只会在调试文件系统被挂载后才可以获取:: + + mount -t debugfs none /sys/kernel/debug + +覆盖率收集 +---------- + +下面的程序演示了如何使用 KCOV 在一个测试程序中收集单个系统调用的覆盖率： + +.. code-block:: c + + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + #define KCOV_INIT_TRACE _IOR('c', 1, unsigned long) + #define KCOV_ENABLE _IO('c', 100) + #define KCOV_DISABLE _IO('c', 101) + #define COVER_SIZE (64<<10) + + #define KCOV_TRACE_PC 0 + #define KCOV_TRACE_CMP 1 + + int main(int argc, char **argv) + { + int fd; + unsigned long *cover, n, i; + + /* 单个文件描述符允许 + * 在单线程上收集覆盖率。 + */ + fd = open("/sys/kernel/debug/kcov", O_RDWR); + if (fd == -1) + perror("open"), exit(1); + /* 设置跟踪模式和跟踪大小。 */ + if (ioctl(fd, KCOV_INIT_TRACE, COVER_SIZE)) + perror("ioctl"), exit(1); + /* 映射内核空间和用户空间共享的缓冲区。 */ + cover = (unsigned long*)mmap(NULL, COVER_SIZE * sizeof(unsigned long), + PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if ((void*)cover == MAP_FAILED) + perror("mmap"), exit(1); + /* 在当前线程中启用覆盖率收集。 */ + if (ioctl(fd, KCOV_ENABLE, KCOV_TRACE_PC)) + perror("ioctl"), exit(1); + /* 在调用 ioctl() 之后重置覆盖率。 */ + __atomic_store_n(&cover[0], 0, __ATOMIC_RELAXED); + /* 调用目标系统调用。 */ + read(-1, NULL, 0); + /* 读取收集到的 PC 的数目。 */ + n = __atomic_load_n(&cover[0], __ATOMIC_RELAXED); + for (i = 0; i < n; i++) + printf("0x%lx\n", cover[i + 1]); + /* 在当前线程上禁用覆盖率收集。在这之后 + * 可以在其他线程上收集覆盖率 + */ + if (ioctl(fd, KCOV_DISABLE, 0)) + perror("ioctl"), exit(1); + /* 释放资源 */ + if (munmap(cover, COVER_SIZE * sizeof(unsigned long))) + perror("munmap"), exit(1); + if (close(fd)) + perror("close"), exit(1); + return 0; + } + +在使用 ``addr2line`` 传输后，程序输出应该如下所示:: + + SyS_read + fs/read_write.c:562 + __fdget_pos + fs/file.c:774 + __fget_light + fs/file.c:746 + __fget_light + fs/file.c:750 + __fget_light + fs/file.c:760 + __fdget_pos + fs/file.c:784 + SyS_read + fs/read_write.c:562 + +如果一个程序需要从多个线程收集覆盖率（独立地）。那么每个线程都需要单独打开 +``/sys/kernel/debug/kcov``。 + +接口的细粒度允许高效的创建测试进程。即，一个父进程打开了 +``/sys/kernel/debug/kcov``，启用了追踪模式，映射了覆盖率缓冲区，然后在一个循 +环中创建了子进程。这个子进程只需要启用覆盖率收集即可（当一个线程退出时将自动禁 +用覆盖率收集）。 + +操作数比较收集 +-------------- + +操作数比较收集和覆盖率收集类似： + +.. code-block:: c + + /* 包含和上文一样的头文件和宏定义。 */ + + /* 每次记录的 64 位字的数量。 */ + #define KCOV_WORDS_PER_CMP 4 + + /* + * 收集的比较种类的格式。 + * + * 0 比特表示是否是一个编译时常量。 + * 1 & 2 比特包含参数大小的 log2 值，最大 8 字节。 + */ + + #define KCOV_CMP_CONST (1 << 0) + #define KCOV_CMP_SIZE(n) ((n) << 1) + #define KCOV_CMP_MASK KCOV_CMP_SIZE(3) + + int main(int argc, char **argv) + { + int fd; + uint64_t *cover, type, arg1, arg2, is_const, size; + unsigned long n, i; + + fd = open("/sys/kernel/debug/kcov", O_RDWR); + if (fd == -1) + perror("open"), exit(1); + if (ioctl(fd, KCOV_INIT_TRACE, COVER_SIZE)) + perror("ioctl"), exit(1); + /* + * 注意缓冲区指针的类型是 uint64_t*，因为所有的 + * 比较操作数都被提升为 uint64_t 类型。 + */ + cover = (uint64_t *)mmap(NULL, COVER_SIZE * sizeof(unsigned long), + PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if ((void*)cover == MAP_FAILED) + perror("mmap"), exit(1); + /* 注意这里是 KCOV_TRACE_CMP 而不是 KCOV_TRACE_PC。 */ + if (ioctl(fd, KCOV_ENABLE, KCOV_TRACE_CMP)) + perror("ioctl"), exit(1); + __atomic_store_n(&cover[0], 0, __ATOMIC_RELAXED); + read(-1, NULL, 0); + /* 读取收集到的比较操作数的数量。 */ + n = __atomic_load_n(&cover[0], __ATOMIC_RELAXED); + for (i = 0; i < n; i++) { + uint64_t ip; + + type = cover[i * KCOV_WORDS_PER_CMP + 1]; + /* arg1 和 arg2 - 比较的两个操作数。 */ + arg1 = cover[i * KCOV_WORDS_PER_CMP + 2]; + arg2 = cover[i * KCOV_WORDS_PER_CMP + 3]; + /* ip - 调用者的地址。 */ + ip = cover[i * KCOV_WORDS_PER_CMP + 4]; + /* 操作数的大小。 */ + size = 1 << ((type & KCOV_CMP_MASK) >> 1); + /* is_const - 当操作数是一个编译时常量时为真。*/ + is_const = type & KCOV_CMP_CONST; + printf("ip: 0x%lx type: 0x%lx, arg1: 0x%lx, arg2: 0x%lx, " + "size: %lu, %s\n", + ip, type, arg1, arg2, size, + is_const ? "const" : "non-const"); + } + if (ioctl(fd, KCOV_DISABLE, 0)) + perror("ioctl"), exit(1); + /* 释放资源。 */ + if (munmap(cover, COVER_SIZE * sizeof(unsigned long))) + perror("munmap"), exit(1); + if (close(fd)) + perror("close"), exit(1); + return 0; + } + +注意 KCOV 的模式（代码覆盖率收集或操作数比较收集）是互斥的。 + +远程覆盖率收集 +-------------- + +除了从用户空间进程发布的系统调用句柄收集覆盖率数据以外，KCOV 也可以从部分在其 +他上下文中执行的内核中收集覆盖率 - 称为“远程”覆盖率。 + +使用 KCOV 收集远程覆盖率要求： + +1. 修改内核源码并使用 ``kcov_remote_start`` 和 ``kcov_remote_stop`` 来标注要收集 + 覆盖率的代码片段。 + +2. 在用户空间的收集覆盖率的进程应使用 ``KCOV_REMOTE_ENABLE`` 而不是 ``KCOV_ENABLE``。 + +``kcov_remote_start`` 和 ``kcov_remote_stop`` 的标注以及 ``KCOV_REMOTE_ENABLE`` +ioctl 都接受可以识别特定覆盖率收集片段的句柄。句柄的使用方式取决于匹配代码片段执 +行的上下文。 + +KCOV 支持在如下上下文中收集远程覆盖率： + +1. 全局内核后台任务。这些任务是内核启动时创建的数量有限的实例（如，每一个 + USB HCD 产生一个 USB ``hub_event`` 工作器）。 + +2. 局部内核后台任务。这些任务通常是由于用户空间进程与某些内核接口进行交互时产 + 生的，并且通常在进程退出时会被停止（如，vhost 工作器）。 + +3. 软中断。 + +对于 #1 和 #3，必须选择一个独特的全局句柄并将其传递给对应的 +``kcov_remote_start`` 调用。一个用户空间进程必须将该句柄存储在 +``kcov_remote_arg`` 结构体的 ``handle`` 数组字段中并将其传递给 +``KCOV_REMOTE_ENABLE``。这会将使用的 KCOV 设备附加到由此句柄引用的代码片段。多个全局 +句柄标识的不同代码片段可以一次性传递。 + +对于 #2，用户空间进程必须通过 ``kcov_remote_arg`` 结构体的 ``common_handle`` 字段 +传递一个非零句柄。这个通用句柄将会被保存在当前 ``task_struct`` 结构体的 +``kcov_handle`` 字段中并且需要通过自定义内核代码的修改来传递给新创建的本地任务 +。这些任务需要在 ``kcov_remote_start`` 和 ``kcov_remote_stop`` 标注中依次使用传递过来的 +句柄。 + +KCOV 对全局句柄和通用句柄均遵循一个预定义的格式。每一个句柄都是一个 ``u64`` 整形 +。当前，只有最高位和低四位字节被使用。第 4-7 字节是保留位并且值必须为 0。 + +对于全局句柄，最高位的字节表示该句柄属于的子系统的标识。比如，KCOV 使用 ``1`` +表示 USB 子系统类型。全局句柄的低 4 字节表示子系统中任务实例的标识。比如，每一 +个 ``hub_event`` 工作器使用 USB 总线号作为任务实例的标识。 + +对于通用句柄，使用一个保留值 ``0`` 作为子系统标识，因为这些句柄不属于一个特定 +的子系统。通用句柄的低 4 字节用于识别有用户进程生成的所有本地句柄的集合实例， +该进程将通用句柄传递给 ``KCOV_REMOTE_ENABLE``。 + +实际上，如果只从系统中的单个用户空间进程收集覆盖率，那么可以使用任意值作为通用 +句柄的实例标识。然而，如果通用句柄被多个用户空间进程使用，每个进程必须使用唯一 +的实例标识。一个选择是使用进程标识作为通用句柄实例的标识。 + +下面的程序演示了如何使用 KCOV 从一个由进程产生的本地任务和处理 USB 总线的全局 +任务 #1 收集覆盖率： + +.. code-block:: c + + /* 包含和上文一样的头文件和宏定义。 */ + + struct kcov_remote_arg { + __u32 trace_mode; + __u32 area_size; + __u32 num_handles; + __aligned_u64 common_handle; + __aligned_u64 handles[0]; + }; + + #define KCOV_INIT_TRACE _IOR('c', 1, unsigned long) + #define KCOV_DISABLE _IO('c', 101) + #define KCOV_REMOTE_ENABLE _IOW('c', 102, struct kcov_remote_arg) + + #define COVER_SIZE (64 << 10) + + #define KCOV_TRACE_PC 0 + + #define KCOV_SUBSYSTEM_COMMON (0x00ull << 56) + #define KCOV_SUBSYSTEM_USB (0x01ull << 56) + + #define KCOV_SUBSYSTEM_MASK (0xffull << 56) + #define KCOV_INSTANCE_MASK (0xffffffffull) + + static inline __u64 kcov_remote_handle(__u64 subsys, __u64 inst) + { + if (subsys & ~KCOV_SUBSYSTEM_MASK || inst & ~KCOV_INSTANCE_MASK) + return 0; + return subsys | inst; + } + + #define KCOV_COMMON_ID 0x42 + #define KCOV_USB_BUS_NUM 1 + + int main(int argc, char **argv) + { + int fd; + unsigned long *cover, n, i; + struct kcov_remote_arg *arg; + + fd = open("/sys/kernel/debug/kcov", O_RDWR); + if (fd == -1) + perror("open"), exit(1); + if (ioctl(fd, KCOV_INIT_TRACE, COVER_SIZE)) + perror("ioctl"), exit(1); + cover = (unsigned long*)mmap(NULL, COVER_SIZE * sizeof(unsigned long), + PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if ((void*)cover == MAP_FAILED) + perror("mmap"), exit(1); + + /* 通过通用句柄和 USB 总线 #1 启用代码覆盖率收集。 */ + arg = calloc(1, sizeof(*arg) + sizeof(uint64_t)); + if (!arg) + perror("calloc"), exit(1); + arg->trace_mode = KCOV_TRACE_PC; + arg->area_size = COVER_SIZE; + arg->num_handles = 1; + arg->common_handle = kcov_remote_handle(KCOV_SUBSYSTEM_COMMON, + KCOV_COMMON_ID); + arg->handles[0] = kcov_remote_handle(KCOV_SUBSYSTEM_USB, + KCOV_USB_BUS_NUM); + if (ioctl(fd, KCOV_REMOTE_ENABLE, arg)) + perror("ioctl"), free(arg), exit(1); + free(arg); + + /* + * 在这里用户需要触发执行一个内核代码段 + * 该代码段要么使用通用句柄标识 + * 要么触发了一些 USB 总线 #1 上的一些活动。 + */ + sleep(2); + + n = __atomic_load_n(&cover[0], __ATOMIC_RELAXED); + for (i = 0; i < n; i++) + printf("0x%lx\n", cover[i + 1]); + if (ioctl(fd, KCOV_DISABLE, 0)) + perror("ioctl"), exit(1); + if (munmap(cover, COVER_SIZE * sizeof(unsigned long))) + perror("munmap"), exit(1); + if (close(fd)) + perror("close"), exit(1); + return 0; + } From a3b97f341d03f7e46273c845de6c711c7f215d5c Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Wed, 17 Apr 2024 12:14:29 +0200 Subject: [PATCH 690/969] MAINTAINERS: repair file entry in DOCUMENTATION Commit 1e596d5eff3d ("docs: Detect variable fonts and suggest denylisting them") adds the new script check-variable-fonts.sh and intends to refer to it in the DOCUMENTATION section in MAINTAINERS. However, the file entry refers to scripts/check-variable-font.sh. Note the missing "s". Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Repair this new file entry in the DOCUMENTATION section. Signed-off-by: Lukas Bulwahn Reviewed-by: Akira Yokosawa Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240417101429.240495-1-lukas.bulwahn@redhat.com --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3a4768c2f712..701e02ef30d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6406,7 +6406,7 @@ S: Maintained P: Documentation/doc-guide/maintainer-profile.rst T: git git://git.lwn.net/linux.git docs-next F: Documentation/ -F: scripts/check-variable-font.sh +F: scripts/check-variable-fonts.sh F: scripts/documentation-file-ref-check F: scripts/kernel-doc F: scripts/sphinx-pre-install From 5f8e4007c10d8f7a0f28be8a7894eb7712d0b111 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 11 Apr 2024 11:32:08 +0200 Subject: [PATCH 691/969] kernel-doc: fix struct_group_tagged() parsing kernel-doc emits a warning on struct_group_tagged() if you describe your struct group member: include/net/libeth/rx.h:69: warning: Excess struct member 'fp' description in 'libeth_fq' The code: /** * struct libeth_fq - structure representing a buffer queue * @fp: hotpath part of the structure * @pp: &page_pool for buffer management [...] */ struct libeth_fq { struct_group_tagged(libeth_fq_fp, fp, struct page_pool *pp; [...] ); When a struct_group_tagged() is encountered, we need to build a `struct TAG NAME;` from it, so that it will be treated as a valid embedded struct. Decouple the regex and do the replacement there. As far as I can see, this doesn't produce any new warnings on the current mainline tree. Reported-by: Jakub Kicinski Closes: https://lore.kernel.org/netdev/20240405212513.0d189968@kernel.org Fixes: 50d7bd38c3aa ("stddef: Introduce struct_group() helper macro") Signed-off-by: Kees Cook Co-developed-by: Alexander Lobakin Signed-off-by: Alexander Lobakin Reviewed-by: Przemek Kitszel Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240411093208.2483580-1-aleksander.lobakin@intel.com --- scripts/kernel-doc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/kernel-doc b/scripts/kernel-doc index cb1be22afc65..438dfe76b989 100755 --- a/scripts/kernel-doc +++ b/scripts/kernel-doc @@ -1151,7 +1151,8 @@ sub dump_struct($$) { # - first eat non-declaration parameters and rewrite for final match # - then remove macro, outer parens, and trailing semicolon $members =~ s/\bstruct_group\s*\(([^,]*,)/STRUCT_GROUP(/gos; - $members =~ s/\bstruct_group_(attr|tagged)\s*\(([^,]*,){2}/STRUCT_GROUP(/gos; + $members =~ s/\bstruct_group_attr\s*\(([^,]*,){2}/STRUCT_GROUP(/gos; + $members =~ s/\bstruct_group_tagged\s*\(([^,]*),([^,]*),/struct $1 $2; STRUCT_GROUP(/gos; $members =~ s/\b__struct_group\s*\(([^,]*,){3}/STRUCT_GROUP(/gos; $members =~ s/\bSTRUCT_GROUP(\(((?:(?>[^)(]+)|(?1))*)\))[^;]*;/$2/gos; From 192f97fe164dd946d0da54bf6e17ff6f9ab9ba43 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Wed, 17 Apr 2024 17:48:00 +0800 Subject: [PATCH 692/969] soc: hisilicon: kunpeng_hccs: Add the check for obtaining complete port attribute The hccs_get_all_port_attr() is used to obtain the attribute of all the ports on a specified DIE from the firmware. However this interface doesn't ensure whether the firmware reports the complete attribute of all the ports or not. So this patch adds the check for this. Signed-off-by: Huisong Li Signed-off-by: Wei Xu --- drivers/soc/hisilicon/kunpeng_hccs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/hisilicon/kunpeng_hccs.c b/drivers/soc/hisilicon/kunpeng_hccs.c index 9ff70b38e5e9..e882a61636ec 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.c +++ b/drivers/soc/hisilicon/kunpeng_hccs.c @@ -556,6 +556,12 @@ static int hccs_get_all_port_attr(struct hccs_dev *hdev, start_id = rsp_head.next_id; } + if (left_buf_len != 0) { + dev_err(hdev->dev, "failed to get the expected port number(%u) attribute.\n", + size); + return -EINVAL; + } + return 0; } From 95d6333e0622dd5ca32c7832a015ae24f56d1ad2 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Wed, 17 Apr 2024 17:48:01 +0800 Subject: [PATCH 693/969] soc: hisilicon: kunpeng_hccs: replace MAILBOX dependency with PCC The kunpeng_hccs driver depends on the Platform Communication Channel Driver. If the PCC driver is not enabled, this driver will be failed to probe. And since the PCC driver depends on the MAILBOX, replace the MAILBOX dependency with the PCC. Signed-off-by: Huisong Li Signed-off-by: Wei Xu --- drivers/soc/hisilicon/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig index 0ab688af308f..4b0a099b28cc 100644 --- a/drivers/soc/hisilicon/Kconfig +++ b/drivers/soc/hisilicon/Kconfig @@ -6,7 +6,7 @@ menu "Hisilicon SoC drivers" config KUNPENG_HCCS tristate "HCCS driver on Kunpeng SoC" depends on ACPI - depends on MAILBOX + depends on PCC depends on ARM64 || COMPILE_TEST help The Huawei Cache Coherence System (HCCS) is a multi-chip From f2bd276193c92d7987b6246e6dd0a7e42ac9d56a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 11 Apr 2024 07:44:30 +0300 Subject: [PATCH 694/969] bus: ti-sysc: Move check for no-reset-on-init We are wrongly checking SYSC_QUIRK_NO_RESET_ON_INIT flag in sysc_reset(), it can be called also after init from sysc_reinit_module(). Let's move the check to the init code in preparation for adding reset control support in the future. Note that this change is not needed as a fix as there are no known issues caused by it currently. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 41d33f39efe5..a9d2aaae68b2 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -2145,8 +2145,7 @@ static int sysc_reset(struct sysc *ddata) sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; if (ddata->legacy_mode || - ddata->cap->regbits->srst_shift < 0 || - ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) + ddata->cap->regbits->srst_shift < 0) return 0; sysc_mask = BIT(ddata->cap->regbits->srst_shift); @@ -2240,12 +2239,14 @@ static int sysc_init_module(struct sysc *ddata) goto err_main_clocks; } - error = sysc_reset(ddata); - if (error) - dev_err(ddata->dev, "Reset failed with %d\n", error); + if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { + error = sysc_reset(ddata); + if (error) + dev_err(ddata->dev, "Reset failed with %d\n", error); - if (error && !ddata->legacy_mode) - sysc_disable_module(ddata->dev); + if (error && !ddata->legacy_mode) + sysc_disable_module(ddata->dev); + } err_main_clocks: if (error) From 5a85fd3c9de7083edc4d32b6cf0bda1a57b4dd3a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 11 Apr 2024 07:44:30 +0300 Subject: [PATCH 695/969] bus: ti-sysc: Add a description and copyrights The ti-sysc driver is missing coprights and description, let's add those. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index a9d2aaae68b2..1dd9d35cc0fc 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1,6 +1,17 @@ // SPDX-License-Identifier: GPL-2.0 /* * ti-sysc.c - Texas Instruments sysc interconnect target driver + * + * TI SoCs have an interconnect target wrapper IP for many devices. The wrapper + * IP manages clock gating, resets, and PM capabilities for the connected devices. + * + * Copyright (C) 2017-2024 Texas Instruments Incorporated - https://www.ti.com/ + * + * Many features are based on the earlier omap_hwmod arch code with thanks to all + * the people who developed and debugged the code over the years: + * + * Copyright (C) 2009-2011 Nokia Corporation + * Copyright (C) 2011-2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include From 5f711f03658856de21f524cd8efd154f796fd997 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 11 Apr 2024 07:44:30 +0300 Subject: [PATCH 696/969] bus: ti-sysc: Drop legacy quirk handling for uarts With the 8250_omap and omap-serial drivers no longer relying on the use of pm_runtime_irq_safe(), we can finally drop the related legacy quirk handling for uarts. Reviewed-by: Dhruva Gole Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 1dd9d35cc0fc..71428ec4fa73 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1540,19 +1540,6 @@ struct sysc_revision_quirk { } static const struct sysc_revision_quirk sysc_revision_quirks[] = { - /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ - SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, - SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), - SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, - SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), - /* Uarts on omap4 and later */ - SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, - SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), - SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, - SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), - SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, - SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), - /* Quirks that need to be set based on the module address */ SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | @@ -1610,6 +1597,17 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, + SYSC_QUIRK_SWSUP_SIDLE_ACT), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, + SYSC_QUIRK_SWSUP_SIDLE_ACT), + /* Uarts on omap4 and later */ + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, + SYSC_QUIRK_SWSUP_SIDLE_ACT), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, + SYSC_QUIRK_SWSUP_SIDLE_ACT), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, + SYSC_QUIRK_SWSUP_SIDLE_ACT), SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, From 2414277f5145eee513df389da7ee5f7a7014a326 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 11 Apr 2024 07:44:30 +0300 Subject: [PATCH 697/969] bus: ti-sysc: Drop legacy quirk handling for smartreflex With the smartreflex driver no longer relying on the use of pm_runtime_irq_safe(), we can finally drop the related legacy quirk handling. Reviewed-by: Dhruva Gole Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 71428ec4fa73..467702da0e82 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -2869,8 +2869,7 @@ static const struct sysc_capabilities sysc_34xx_sr = { .type = TI_SYSC_OMAP34XX_SR, .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, .regbits = &sysc_regbits_omap34xx_sr, - .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | - SYSC_QUIRK_LEGACY_IDLE, + .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED, }; /* @@ -2891,13 +2890,12 @@ static const struct sysc_capabilities sysc_36xx_sr = { .type = TI_SYSC_OMAP36XX_SR, .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, .regbits = &sysc_regbits_omap36xx_sr, - .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, + .mod_quirks = SYSC_QUIRK_UNCACHED, }; static const struct sysc_capabilities sysc_omap4_sr = { .type = TI_SYSC_OMAP4_SR, .regbits = &sysc_regbits_omap36xx_sr, - .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, }; /* From 4bcc2e91b9e77644ee04b290bfd2c1410d7c402e Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 11 Apr 2024 07:44:30 +0300 Subject: [PATCH 698/969] bus: ti-sysc: Drop legacy idle quirk handling There are no more users that need the legacy idle quirk so let's drop the legacy idle quirk handling. This simplifies the PM code to just sysc_pm_ops with unified handling for all the interconnect targets. Reviewed-by: Dhruva Gole Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 109 +------------------------- include/linux/platform_data/ti-sysc.h | 1 - 2 files changed, 2 insertions(+), 108 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 467702da0e82..8767e04d6c89 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1469,8 +1469,7 @@ static int __maybe_unused sysc_noirq_suspend(struct device *dev) ddata = dev_get_drvdata(dev); - if (ddata->cfg.quirks & - (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) + if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) return 0; if (!ddata->enabled) @@ -1488,8 +1487,7 @@ static int __maybe_unused sysc_noirq_resume(struct device *dev) ddata = dev_get_drvdata(dev); - if (ddata->cfg.quirks & - (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) + if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) return 0; if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { @@ -2457,89 +2455,6 @@ static int __maybe_unused sysc_child_runtime_resume(struct device *dev) return pm_generic_runtime_resume(dev); } -#ifdef CONFIG_PM_SLEEP -static int sysc_child_suspend_noirq(struct device *dev) -{ - struct sysc *ddata; - int error; - - ddata = sysc_child_to_parent(dev); - - dev_dbg(ddata->dev, "%s %s\n", __func__, - ddata->name ? ddata->name : ""); - - error = pm_generic_suspend_noirq(dev); - if (error) { - dev_err(dev, "%s error at %i: %i\n", - __func__, __LINE__, error); - - return error; - } - - if (!pm_runtime_status_suspended(dev)) { - error = pm_generic_runtime_suspend(dev); - if (error) { - dev_dbg(dev, "%s busy at %i: %i\n", - __func__, __LINE__, error); - - return 0; - } - - error = sysc_runtime_suspend(ddata->dev); - if (error) { - dev_err(dev, "%s error at %i: %i\n", - __func__, __LINE__, error); - - return error; - } - - ddata->child_needs_resume = true; - } - - return 0; -} - -static int sysc_child_resume_noirq(struct device *dev) -{ - struct sysc *ddata; - int error; - - ddata = sysc_child_to_parent(dev); - - dev_dbg(ddata->dev, "%s %s\n", __func__, - ddata->name ? ddata->name : ""); - - if (ddata->child_needs_resume) { - ddata->child_needs_resume = false; - - error = sysc_runtime_resume(ddata->dev); - if (error) - dev_err(ddata->dev, - "%s runtime resume error: %i\n", - __func__, error); - - error = pm_generic_runtime_resume(dev); - if (error) - dev_err(ddata->dev, - "%s generic runtime resume: %i\n", - __func__, error); - } - - return pm_generic_resume_noirq(dev); -} -#endif - -static struct dev_pm_domain sysc_child_pm_domain = { - .ops = { - SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, - sysc_child_runtime_resume, - NULL) - USE_PLATFORM_PM_SLEEP_OPS - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, - sysc_child_resume_noirq) - } -}; - /* Caller needs to take list_lock if ever used outside of cpu_pm */ static void sysc_reinit_modules(struct sysc_soc_info *soc) { @@ -2610,25 +2525,6 @@ out_unlock: mutex_unlock(&sysc_soc->list_lock); } -/** - * sysc_legacy_idle_quirk - handle children in omap_device compatible way - * @ddata: device driver data - * @child: child device driver - * - * Allow idle for child devices as done with _od_runtime_suspend(). - * Otherwise many child devices will not idle because of the permanent - * parent usecount set in pm_runtime_irq_safe(). - * - * Note that the long term solution is to just modify the child device - * drivers to not set pm_runtime_irq_safe() and then this can be just - * dropped. - */ -static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) -{ - if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) - dev_pm_domain_set(child, &sysc_child_pm_domain); -} - static int sysc_notifier_call(struct notifier_block *nb, unsigned long event, void *device) { @@ -2645,7 +2541,6 @@ static int sysc_notifier_call(struct notifier_block *nb, error = sysc_child_add_clocks(ddata, dev); if (error) return error; - sysc_legacy_idle_quirk(ddata, dev); break; default: break; diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index eb556f988d57..d8f15770a522 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -71,7 +71,6 @@ struct sysc_regbits { #define SYSC_QUIRK_SWSUP_SIDLE_ACT BIT(12) #define SYSC_QUIRK_SWSUP_SIDLE BIT(11) #define SYSC_QUIRK_EXT_OPT_CLOCK BIT(10) -#define SYSC_QUIRK_LEGACY_IDLE BIT(9) #define SYSC_QUIRK_RESET_STATUS BIT(8) #define SYSC_QUIRK_NO_IDLE BIT(7) #define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6) From 081a4fd9c026a8fbb1a41c89a591bed8997192b3 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 16 Apr 2024 10:47:49 -0400 Subject: [PATCH 699/969] ARM: dts: nxp: imx6sx: fix esai related warning when do dtb_check Remove undocumented compatible string 'fsl,imx6sx-esai', which never used in driver sound/soc/fsl/fsl_esai.c. Remove unused clock-names 'mem'. Driver never use clock name 'mem'. Fix below warning: arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: compatible:0: 'fsl,imx6sx-esai' is not one of ['fsl,imx35-esai', 'fsl,imx6ull-esai', 'fsl,imx8qm-esai', 'fsl,vf610-esai'] from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arm/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: compatible: ['fsl,imx6sx-esai', 'fsl,imx35-esai'] is too long from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arm/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: clocks: [[2, 239], [2, 240], [2, 152], [2, 239], [2, 196]] is too long from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: clock-names:1: 'extal' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: clock-names:2: 'fsys' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: clock-names:3: 'spba' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: esai@2024000: clock-names: ['core', 'mem', 'extal', 'fsys', 'spba'] is too long Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 6d3deba60de5..b386448486df 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -339,15 +339,14 @@ }; esai: esai@2024000 { - compatible = "fsl,imx6sx-esai", "fsl,imx35-esai"; + compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, - <&clks IMX6SX_CLK_ESAI_MEM>, <&clks IMX6SX_CLK_ESAI_EXTAL>, <&clks IMX6SX_CLK_ESAI_IPG>, <&clks IMX6SX_CLK_SPBA>; - clock-names = "core", "mem", "extal", + clock-names = "core", "extal", "fsys", "spba"; dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; From 8f610681b3487c4ce6815bb9fa10bbd82c1d3226 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 16 Apr 2024 10:47:50 -0400 Subject: [PATCH 700/969] ARM: dts: nxp: imx6qdl: fix esai clock warning when do dtb_check Remove unused clock-names 'mem'. Driver (sound/soc/fsl/fsl_esai.c.) never use clock name 'mem'. arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: esai@2024000: clocks: [[2, 208], [2, 209], [2, 118], [2, 208], [2, 156]] is too long from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: esai@2024000: clock-names:1: 'extal' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: esai@2024000: clock-names:2: 'fsys' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: esai@2024000: clock-names:3: 'spba' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: esai@2024000: clock-names: ['core', 'mem', 'extal', 'fsys', 'spba'] is too long from schema $id: http://devicetree.org/schemas/sound/fsl,esai.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 8431b8a994f4..d2200c9db25a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -397,11 +397,10 @@ reg = <0x02024000 0x4000>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, - <&clks IMX6QDL_CLK_ESAI_MEM>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, <&clks IMX6QDL_CLK_ESAI_IPG>, <&clks IMX6QDL_CLK_SPBA>; - clock-names = "core", "mem", "extal", "fsys", "spba"; + clock-names = "core", "extal", "fsys", "spba"; dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; dma-names = "rx", "tx"; status = "disabled"; From c834a7847602424157bbaf9898a5c677c3bb1f83 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 16 Apr 2024 21:06:59 +0200 Subject: [PATCH 701/969] ARM: dts: imx6ull-tarragon: Reduce SPI clock for QCA7000 Our hardware department recently informed us that, according to the specification, the QCA7000 should be operated with a maximum SPI clock frequency of 12 MHz. Even if it appears to work at a higher frequency, we should not take any risks here. A short performance test showed no measurable loss of speed. Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts index 67007ce383e3..f9bbd589b66d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-master.dts @@ -45,7 +45,7 @@ interrupts = <19 IRQ_TYPE_EDGE_RISING>; spi-cpha; spi-cpol; - spi-max-frequency = <16000000>; + spi-max-frequency = <12000000>; }; }; @@ -63,7 +63,7 @@ interrupts = <9 IRQ_TYPE_EDGE_RISING>; spi-cpha; spi-cpol; - spi-max-frequency = <16000000>; + spi-max-frequency = <12000000>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts index cee223b5f8e1..ef06619d7c86 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slave.dts @@ -23,7 +23,7 @@ interrupts = <19 IRQ_TYPE_EDGE_RISING>; spi-cpha; spi-cpol; - spi-max-frequency = <16000000>; + spi-max-frequency = <12000000>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts index 7fd53b7a4372..83db65bf630f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-slavext.dts @@ -45,7 +45,7 @@ interrupts = <19 IRQ_TYPE_EDGE_RISING>; spi-cpha; spi-cpol; - spi-max-frequency = <16000000>; + spi-max-frequency = <12000000>; }; }; From bc8a8c8c15075a8512ad25e16d3a022e81ee7985 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 17 Apr 2024 13:42:06 +0200 Subject: [PATCH 702/969] arm64: dts: imx8mp: Align both CSI2 pixel clock Configure both CSI2 clock-frequency and assigned-clock-rates the same way. There does not seem to be any reason for keeping the two CSI2 pixel clock set to different frequencies. This also reduces first CSI2 clock from overdrive mode frequency which is 500 MHz down below the regular mode frequency of 400 MHz. Reviewed-by: Alexander Stein Reviewed-by: Peng Fan Signed-off-by: Marek Vasut Reviewed-by: Ahmad Fatoum Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9f3e7c23b2ef..f3837d526fcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1657,7 +1657,7 @@ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; interrupts = ; - clock-frequency = <500000000>; + clock-frequency = <266000000>; clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, @@ -1667,7 +1667,7 @@ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_CLK_24M>; - assigned-clock-rates = <500000000>; + assigned-clock-rates = <266000000>; power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; status = "disabled"; From 880efa71293cbc819eb8c567d55580e015c3e9f7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 17 Apr 2024 11:08:29 -0400 Subject: [PATCH 703/969] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960 and sai[0,1,4,5] Add cm40_i2c, wm8960 and sai[0,1,4,5] for imx8qxp-mek (SCH-38813). Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 83d298c2bfd3..cee13e58762c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -44,6 +44,22 @@ }; }; }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; }; &dsp { @@ -188,6 +204,47 @@ }; +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_cm40_i2c>; + pinctrl-1 = <&pinctrl_cm40_i2c_gpio>; + scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + wm8960: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, + <49152000>, + <12288000>, + <12288000>; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm40_intmux { + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -218,6 +275,53 @@ status = "okay"; }; +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai4 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai4_lpcg IMX_LPCG_CLK_0>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg IMX_LPCG_CLK_0>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + &thermal_zones { pmic-thermal { polling-delay-passive = <250>; @@ -314,6 +418,21 @@ }; &iomuxc { + + pinctrl_cm40_i2c: cm40i2cgrp { + fsl,pins = < + IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c + IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c + >; + }; + + pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp { + fsl,pins = < + IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c + IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 @@ -385,6 +504,25 @@ >; }; + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060 + IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 From f1ca4e3890544d0b9acd1ce1f006d5c5255074d3 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 18 Apr 2024 15:09:25 -0500 Subject: [PATCH 704/969] arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping PCI devices should use PCI interrupt binding for their interrupts assuming they function as standard PCI interrupts. The embedded PCI devices in the LS1028a are mapping the interrupts directly to the host interrupt controller. While that works here, it is unusual. Based on the reference manual, there is not any INTC or INTD to map, so only INTA and INTB are mapped. Signed-off-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ae534c23b970..8f8179924851 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1099,6 +1099,10 @@ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 /* BAR4 (PF5) - non-prefetchable memory */ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; enetc_port0: ethernet@0,0 { compatible = "fsl,enetc"; @@ -1143,7 +1147,7 @@ mscc_felix: ethernet-switch@0,5 { reg = <0x000500 0 0 0 0>; /* IEP INT_B */ - interrupts = ; + interrupts = <2>; status = "disabled"; mscc_felix_ports: ports { @@ -1216,7 +1220,7 @@ rcec@1f,0 { reg = <0x00f800 0 0 0 0>; /* IEP INT_A */ - interrupts = ; + interrupts = <1>; }; }; From fe3726223cc41e6a51be907eaadf767fc695182b Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 18 Apr 2024 15:09:26 -0500 Subject: [PATCH 705/969] arm64: dts: freescale: ls1028a: Add standard PCI device compatible strings to ENETC PCI devices should have a compatible string based on the vendor and device IDs. Add these to the Freescale ENETC devices. Putting the PCI compatible string first as vendor and device ID is more specific than a compatible without any device specific information. Signed-off-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 8f8179924851..70b8731029c4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1105,19 +1105,19 @@ <0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; enetc_port0: ethernet@0,0 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000000 0 0 0 0>; status = "disabled"; }; enetc_port1: ethernet@0,1 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000100 0 0 0 0>; status = "disabled"; }; enetc_port2: ethernet@0,2 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000200 0 0 0 0>; phy-mode = "internal"; status = "disabled"; @@ -1130,14 +1130,14 @@ }; enetc_mdio_pf3: mdio@0,3 { - compatible = "fsl,enetc-mdio"; + compatible = "pci1957,ee01", "fsl,enetc-mdio"; reg = <0x000300 0 0 0 0>; #address-cells = <1>; #size-cells = <0>; }; ethernet@0,4 { - compatible = "fsl,enetc-ptp"; + compatible = "pci1957,ee02", "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; little-endian; @@ -1205,7 +1205,7 @@ }; enetc_port3: ethernet@0,6 { - compatible = "fsl,enetc"; + compatible = "pci1957,e100", "fsl,enetc"; reg = <0x000600 0 0 0 0>; phy-mode = "internal"; status = "disabled"; From 76c54d53aaa0c349442764c0f639450a05089707 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:36:56 +0800 Subject: [PATCH 706/969] arm64: dts: imx93: use FSL_EDMA_RX for rx channel Use FSL_EDMA_RX for dma rx channel bitmask, which is intuitive. Signed-off-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 25 ++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 95128932abda..7131d3455aac 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -375,7 +376,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART1_GATE>; clock-names = "ipg"; - dmas = <&edma1 17 0 1>, <&edma1 16 0 0>; + dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -386,7 +387,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART2_GATE>; clock-names = "ipg"; - dmas = <&edma1 19 0 1>, <&edma1 18 0 0>; + dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -414,7 +415,7 @@ <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -751,7 +752,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; - dmas = <&edma2 18 0 1>, <&edma2 17 0 0>; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -762,7 +763,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; - dmas = <&edma2 20 0 1>, <&edma2 19 0 0>; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -773,7 +774,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; - dmas = <&edma2 22 0 1>, <&edma2 21 0 0>; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -784,7 +785,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; - dmas = <&edma2 24 0 1>, <&edma2 23 0 0>; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -827,7 +828,7 @@ <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 59 0 1>, <&edma2 58 0 0>; + dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -840,7 +841,7 @@ <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -859,7 +860,7 @@ <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUD_XCVR_GATE>; clock-names = "ipg", "phy", "spba", "pll_ipg"; - dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -870,7 +871,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART7_GATE>; clock-names = "ipg"; - dmas = <&edma2 88 0 1>, <&edma2 87 0 0>; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -881,7 +882,7 @@ interrupts = ; clocks = <&clk IMX93_CLK_LPUART8_GATE>; clock-names = "ipg"; - dmas = <&edma2 90 0 1>, <&edma2 89 0 0>; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; From 7eb9efd28f117b3f14d1c14794e4131075a4dc29 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:36:57 +0800 Subject: [PATCH 707/969] arm64: dts: imx93: add dma support for lpi2c[1..8] Add dma support for lpi2c[1..8]. Signed-off-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 7131d3455aac..520902a0bd00 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -331,6 +331,8 @@ clocks = <&clk IMX93_CLK_LPI2C1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -343,6 +345,8 @@ clocks = <&clk IMX93_CLK_LPI2C2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -707,6 +711,8 @@ clocks = <&clk IMX93_CLK_LPI2C3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -719,6 +725,8 @@ clocks = <&clk IMX93_CLK_LPI2C4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -896,6 +904,8 @@ clocks = <&clk IMX93_CLK_LPI2C5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -908,6 +918,8 @@ clocks = <&clk IMX93_CLK_LPI2C6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -920,6 +932,8 @@ clocks = <&clk IMX93_CLK_LPI2C7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -932,6 +946,8 @@ clocks = <&clk IMX93_CLK_LPI2C8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; From cd6cb1fff35aa519b3cb2d53477b01fc0f1cf088 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:36:58 +0800 Subject: [PATCH 708/969] arm64: dts: imx93: add dma support for lpspi[1..8] Add dma support for lpspi[1..8] Signed-off-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 520902a0bd00..b6cd73d9105e 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -359,6 +359,8 @@ clocks = <&clk IMX93_CLK_LPSPI1_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -371,6 +373,8 @@ clocks = <&clk IMX93_CLK_LPSPI2_GATE>, <&clk IMX93_CLK_BUS_AON>; clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -739,6 +743,8 @@ clocks = <&clk IMX93_CLK_LPSPI3_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -751,6 +757,8 @@ clocks = <&clk IMX93_CLK_LPSPI4_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -960,6 +968,8 @@ clocks = <&clk IMX93_CLK_LPSPI5_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -972,6 +982,8 @@ clocks = <&clk IMX93_CLK_LPSPI6_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -984,6 +996,8 @@ clocks = <&clk IMX93_CLK_LPSPI7_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -996,6 +1010,8 @@ clocks = <&clk IMX93_CLK_LPSPI8_GATE>, <&clk IMX93_CLK_BUS_WAKEUP>; clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; From 45bf3c0eee25f6202c638a654f7379eb3a96cb90 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 19 Apr 2024 11:36:59 +0800 Subject: [PATCH 709/969] arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz 1. Config SDHC1 clock 400MHz to support eMMC HS400ES mode 2. The original usdhc2 and usdhc3 root clock is 200MHz. Then WIFI on usdhc3 at SDR104 mode can work under 200MHz. But if imx93 work under Low Drive mode, the usdhc3 pad signal is not good under 200MHz, SDR104 mode can't work stable. Need to downgrade to 133MHz to let WIFI work stable. To cover all the cases, for Norminal Drive mode, keep usdhc root at 400MHz, then card(SD/wifi) can work at SDR104 mode under 200MHz to get the best performance. For Low Drive mode, bootloader need override usdhc root clock to 266MHz, and the card(SD/wifi) work at SDR104 mode under 133MHz, can work stable. Reviewed-by: Sherry Sun Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index b6cd73d9105e..330b9518a76f 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1032,6 +1032,9 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1046,6 +1049,9 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; @@ -1109,6 +1115,9 @@ <&clk IMX93_CLK_WAKEUP_AXI>, <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; From b2ab0edaf484d578e8d0c06093af0003586def72 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:37:00 +0800 Subject: [PATCH 710/969] arm64: dts: imx93: add nvmem property for fec1 Add nvmem property for fec1 to get mac address. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 330b9518a76f..47396e7457e1 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1082,6 +1082,8 @@ fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -1191,6 +1193,11 @@ reg = <0x47510000 0x10000>; #address-cells = <1>; #size-cells = <1>; + + eth_mac1: mac-address@4ec { + reg = <0x4ec 0x6>; + }; + }; s4muap: mailbox@47520000 { From 0d4fbaffbdcaec3fce29445b00324f470ee403c4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:37:01 +0800 Subject: [PATCH 711/969] arm64: dts: imx93: add nvmem property for eqos Add nvmem properties for eqos to get mac address. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 47396e7457e1..4a3f42355cb8 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1106,6 +1106,8 @@ assigned-clock-rates = <100000000>, <250000000>; intf_mode = <&wakeupmix_gpr 0x28>; snps,clk-csr = <0>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -1198,6 +1200,10 @@ reg = <0x4ec 0x6>; }; + eth_mac2: mac-address@4f2 { + reg = <0x4f2 0x6>; + }; + }; s4muap: mailbox@47520000 { From 2333cdb54eff89b641f1caaf48c4d0f2fad55dd3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:37:02 +0800 Subject: [PATCH 712/969] arm64: dts: imx93-11x11-evk: update resource table address Update the resource table to avoid conflict because iMX93 ROM use last 4KB TCM aream. Also correct vdev1vring node name to align with reg. Fixes: e1da729459e6 ("arm64: dts: imx93: enable CM33 for 11x11 EVK") Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 2211922c1826..29425ca2d7d6 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -39,7 +39,7 @@ no-map; }; - vdev1vring0: vdev1vring0@a4000000 { + vdev1vring0: vdev1vring0@a4010000 { reg = <0 0xa4010000 0 0x8000>; no-map; }; @@ -49,8 +49,8 @@ no-map; }; - rsc_table: rsc-table@2021f000 { - reg = <0 0x2021f000 0 0x1000>; + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; no-map; }; From 3fa24052a1047a009d8d3b4de75325debe4cdaca Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:37:03 +0800 Subject: [PATCH 713/969] arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec Add sleep pinctrl settings for EQoS and FEC to save power when suspend. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 44 ++++++++++++++++++- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 29425ca2d7d6..3b1ab204bbbf 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -181,8 +181,9 @@ }; &eqos { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; phy-mode = "rgmii-id"; phy-handle = <ðphy1>; status = "okay"; @@ -201,8 +202,9 @@ }; &fec { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; phy-mode = "rgmii-id"; phy-handle = <ðphy2>; fsl,magic-packet; @@ -413,6 +415,25 @@ >; }; + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e @@ -439,6 +460,25 @@ >; }; + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e From a4a60f8101bec856a505bd593e0007a0f250b8a8 Mon Sep 17 00:00:00 2001 From: Luke Wang Date: Fri, 19 Apr 2024 11:37:04 +0800 Subject: [PATCH 714/969] arm64: dts: imx93-11x11-evk: add different usdhc pinctrl for different timing usage imx93-11x11-evk dts use the strongest driver strength for default(high-speed), 100MHz(SDR50/DDR50/DDR52) and 200MHz(SDR104/HS200/HS400) timing. To make usdhc working appropriately for each timing, add X1 drive strength to default timing and X3 drive strength to 100MHz timing. Reviewed-by: Haibo Chen Signed-off-by: Luke Wang Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 68 +++++++++++++++++-- 1 file changed, 64 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 3b1ab204bbbf..5785ffc9297b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -273,8 +273,8 @@ &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; @@ -283,8 +283,8 @@ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; @@ -510,6 +510,40 @@ /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe @@ -539,6 +573,32 @@ /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe From 4fb2337cb9a68db5ae757fff3b4818c9f4a24e2a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 19 Apr 2024 11:37:05 +0800 Subject: [PATCH 715/969] arm64: dts: imx93-11x11-evk: add sleep pinctrl for sdhc2 Add sleep pinctrl for SDHC2 for suspend usage. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 5785ffc9297b..82dcd709da93 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -281,10 +281,11 @@ }; &usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; bus-width = <4>; @@ -571,6 +572,12 @@ >; }; + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < @@ -609,4 +616,17 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + }; From 63e3cc2b87c24532a497a3da6d55951e97a8be91 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Fri, 19 Apr 2024 11:37:06 +0800 Subject: [PATCH 716/969] arm64: dts: imx93-11x11-evk: add reset gpios for ethernet PHYs Both the PHYs of the EQOS interface and the FEC interface are supported to be reset by I2C GPIO Expender. So add the support to reset PHYs. Signed-off-by: Wei Fang Reviewed-by: Clark Wang Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 82dcd709da93..83e586a62013 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -197,6 +197,9 @@ ethphy1: ethernet-phy@1 { reg = <1>; eee-broken-1000t; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; }; }; }; @@ -218,6 +221,9 @@ ethphy2: ethernet-phy@2 { reg = <2>; eee-broken-1000t; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; }; }; }; From dbf76c0d3da8d18a46f75130bdfae7b3b54407c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 23 Apr 2024 15:31:03 +0100 Subject: [PATCH 717/969] dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt-schema documentation and clock IDs for the high speed interface 0 HSI0 clock management unit. This is used (amongst others) for USB. While the usual (sed) script has been used to derive the linux clock IDs from the data sheet, one manual tweak was applied to fix a typo which we don't want to carry: HSI0_USPDPDBG_USER -> HSI0_USBDPDBG_USER (note USB vs USP). Signed-off-by: André Draszik Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240423-hsi0-gs101-v1-1-2c3ddb50c720@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 29 +++++++++- include/dt-bindings/clock/google,gs101.h | 54 +++++++++++++++++++ 2 files changed, 81 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 1d2bcea41c85..94dcc4f84c85 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -30,16 +30,17 @@ properties: - google,gs101-cmu-top - google,gs101-cmu-apm - google,gs101-cmu-misc + - google,gs101-cmu-hsi0 - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 clocks: minItems: 1 - maxItems: 3 + maxItems: 5 clock-names: minItems: 1 - maxItems: 3 + maxItems: 5 "#clock-cells": const: 1 @@ -72,6 +73,30 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: HSI0 bus clock (from CMU_TOP) + - description: DPGTC (from CMU_TOP) + - description: USB DRD controller clock (from CMU_TOP) + - description: USB Display Port debug clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: dpgtc + - const: usb31drd + - const: usbdpdbg + - if: properties: compatible: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 3dac3577788a..7a2006f0edf1 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -313,6 +313,60 @@ #define CLK_APM_PLL_DIV4_APM 70 #define CLK_APM_PLL_DIV16_APM 71 +/* CMU_HSI0 */ +#define CLK_FOUT_USB_PLL 1 +#define CLK_MOUT_PLL_USB 2 +#define CLK_MOUT_HSI0_ALT_USER 3 +#define CLK_MOUT_HSI0_BUS_USER 4 +#define CLK_MOUT_HSI0_DPGTC_USER 5 +#define CLK_MOUT_HSI0_TCXO_USER 6 +#define CLK_MOUT_HSI0_USB20_USER 7 +#define CLK_MOUT_HSI0_USB31DRD_USER 8 +#define CLK_MOUT_HSI0_USBDPDBG_USER 9 +#define CLK_MOUT_HSI0_BUS 10 +#define CLK_MOUT_HSI0_USB20_REF 11 +#define CLK_MOUT_HSI0_USB31DRD 12 +#define CLK_DOUT_HSI0_USB31DRD 13 +#define CLK_GOUT_HSI0_PCLK 14 +#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26 15 +#define CLK_GOUT_HSI0_CLK_HSI0_ALT 16 +#define CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK 17 +#define CLK_GOUT_HSI0_DP_LINK_I_PCLK 18 +#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 19 +#define CLK_GOUT_HSI0_ETR_MIU_I_ACLK 20 +#define CLK_GOUT_HSI0_ETR_MIU_I_PCLK 21 +#define CLK_GOUT_HSI0_GPC_HSI0_PCLK 22 +#define CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK 23 +#define CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK 24 +#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK 25 +#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK 26 +#define CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK 27 +#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK 28 +#define CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK 29 +#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK 30 +#define CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK 31 +#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 32 +#define CLK_GOUT_HSI0_SSMT_USB_ACLK 33 +#define CLK_GOUT_HSI0_SSMT_USB_PCLK 34 +#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 35 +#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 36 +#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK 37 +#define CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK 38 +#define CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK 39 +#define CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK 40 +#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 41 +#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 42 +#define CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26 43 +#define CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40 44 +#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL 45 +#define CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK 46 +#define CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK 47 +#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK 48 +#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK 49 +#define CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK 50 +#define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51 +#define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52 + /* CMU_MISC */ #define CLK_MOUT_MISC_BUS_USER 1 #define CLK_MOUT_MISC_SSS_USER 2 From 8005c3e17db0d93c3f91dd23c45a1a463a2b0ebc Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Thu, 25 Apr 2024 09:35:07 +0800 Subject: [PATCH 718/969] arm64: dts: imx93-11x11-evk: add RTC PCF2131 support Support RTC PCF2131 on imx93-11x11-evk. Signed-off-by: Joy Zou Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 83e586a62013..d400d85f42a9 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -402,6 +402,20 @@ }; }; +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -509,6 +523,13 @@ >; }; + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + pinctrl_pcal6524: pcal6524grp { fsl,pins = < MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e From 3a3e2b83e8059679e92be4273c601ea21e105a89 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 24 Apr 2024 14:16:40 +0100 Subject: [PATCH 719/969] firmware: arm_ffa: Avoid queuing work when running on the worker queue Currently notif_pcpu_irq_work_fn() may get queued from the work that is already running on the 'notif_pcpu_wq' workqueue. This may add unnecessary delays and could be avoided if the work is called directly instead. This change removes queuing of the work when already running on the 'notif_pcpu_wq' workqueue thereby removing any possible delays in that path. Link: https://lore.kernel.org/r/20240424131640.706870-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_ffa/driver.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c index b29496cac2af..78abde20ab01 100644 --- a/drivers/firmware/arm_ffa/driver.c +++ b/drivers/firmware/arm_ffa/driver.c @@ -1146,7 +1146,7 @@ static void handle_notif_callbacks(u64 bitmap, enum notify_type type) } } -static void notif_pcpu_irq_work_fn(struct work_struct *work) +static void notif_get_and_handle(void *unused) { int rc; struct ffa_notify_bitmaps bitmaps; @@ -1169,10 +1169,17 @@ ffa_self_notif_handle(u16 vcpu, bool is_per_vcpu, void *cb_data) struct ffa_drv_info *info = cb_data; if (!is_per_vcpu) - notif_pcpu_irq_work_fn(&info->notif_pcpu_work); + notif_get_and_handle(info); else - queue_work_on(vcpu, info->notif_pcpu_wq, - &info->notif_pcpu_work); + smp_call_function_single(vcpu, notif_get_and_handle, info, 0); +} + +static void notif_pcpu_irq_work_fn(struct work_struct *work) +{ + struct ffa_drv_info *info = container_of(work, struct ffa_drv_info, + notif_pcpu_work); + + ffa_self_notif_handle(smp_processor_id(), true, info); } static const struct ffa_info_ops ffa_drv_info_ops = { @@ -1345,8 +1352,10 @@ static irqreturn_t ffa_sched_recv_irq_handler(int irq, void *irq_data) static irqreturn_t notif_pend_irq_handler(int irq, void *irq_data) { struct ffa_pcpu_irq *pcpu = irq_data; + struct ffa_drv_info *info = pcpu->info; - ffa_self_notif_handle(smp_processor_id(), true, pcpu->info); + queue_work_on(smp_processor_id(), info->notif_pcpu_wq, + &info->notif_pcpu_work); return IRQ_HANDLED; } From 956dbce43d14c380545c5b70394ccffa2bd036c2 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:56:26 -0500 Subject: [PATCH 720/969] arm64: dts: ti: k3-am65: Add full compatible to SerDes control nodes This matches the binding for this register region which fixes a couple DTS check warnings. While here trim the leading 0s from the "reg" definition. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185627.29852-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 670557c89f75..5bc3ec080474 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -482,13 +482,13 @@ ranges = <0x0 0x0 0x00100000 0x1c000>; serdes0_clk: clock@4080 { - compatible = "syscon"; - reg = <0x00004080 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4080 0x4>; }; serdes1_clk: clock@4090 { - compatible = "syscon"; - reg = <0x00004090 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4090 0x4>; }; serdes_mux: mux-controller { From da795dc4f2a058acceb4f4d47f8353015eb6ba6d Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 13:56:27 -0500 Subject: [PATCH 721/969] arm64: dts: ti: k3-am65: Move SerDes mux nodes under the control node These SerDes lane select muxes use bits from the same register as the SerDes clock select mux. Make the lane select mux a child of the SerDes control node. This removes one more requirement on scm-conf being a syscon node which will later be converted to fix a couple DTS check warnings. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326185627.29852-2-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 5bc3ec080474..de5b1b20a617 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -66,7 +66,7 @@ assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; ti,serdes-clk = <&serdes0_clk>; #clock-cells = <1>; - mux-controls = <&serdes_mux 0>; + mux-controls = <&serdes0_mux 0>; }; serdes1: serdes@910000 { @@ -81,7 +81,7 @@ assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; ti,serdes-clk = <&serdes1_clk>; #clock-cells = <1>; - mux-controls = <&serdes_mux 1>; + mux-controls = <&serdes1_mux 0>; }; main_uart0: serial@2800000 { @@ -484,18 +484,23 @@ serdes0_clk: clock@4080 { compatible = "ti,am654-serdes-ctrl", "syscon"; reg = <0x4080 0x4>; + + serdes0_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>; /* lane select */ + }; }; serdes1_clk: clock@4090 { compatible = "ti,am654-serdes-ctrl", "syscon"; reg = <0x4090 0x4>; - }; - serdes_mux: mux-controller { - compatible = "mmio-mux"; - #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ - <0x4090 0x3>; /* SERDES1 lane select */ + serdes1_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>; /* lane select */ + }; }; dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { From 8ec19dbe9217edbb564b16a5f68465b8cd42a167 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 15:59:17 -0500 Subject: [PATCH 722/969] arm64: dts: ti: k3-am65: Use exact ranges for FSS node The FSS bus contains several register ranges. Using an empty ranges property works but causes a DT warning when we give this node an address. Fix this by explicitly defining the memory ranges in use. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326205920.40147-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 4f808e508975..8feab9317644 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -285,7 +285,11 @@ compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; From 98b939a9b3204120bd3a96015d74cbe818a3a2e9 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 15:59:18 -0500 Subject: [PATCH 723/969] arm64: dts: ti: k3-j7200: Use exact ranges for FSS node The FSS bus contains several register ranges. Using an empty ranges property works but causes a DT warning when we give this node an address. Fix this by explicitly defining the memory ranges in use. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326205920.40147-2-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index c547bc8fb608..fccaabfb1348 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -518,10 +518,12 @@ fss: bus@47000000 { compatible = "simple-bus"; - reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; From 74904fc1f1f1c802eaed10edc3744f0997c154ff Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 15:59:19 -0500 Subject: [PATCH 724/969] arm64: dts: ti: k3-j721e: Use exact ranges for FSS node The FSS bus contains several register ranges. Using an empty ranges property works but causes a DT warning when we give this node an address. Fix this by explicitly defining the memory ranges in use. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326205920.40147-3-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 8fc768d84b75..9349ae07c046 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -344,10 +344,14 @@ fss: bus@47000000 { compatible = "simple-bus"; - reg = <0x0 0x47000000 0x0 0x100>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47034000 0x0 0x47034000 0x0 0x100>, /* HBMC Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* HBMC/OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ hbmc_mux: mux-controller@47000004 { compatible = "reg-mux"; From b3f629482cade3a6ada44d2e83dd65f0f1ed1293 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 26 Mar 2024 15:59:20 -0500 Subject: [PATCH 725/969] arm64: dts: ti: k3-j784s4: Use exact ranges for FSS node The FSS bus contains several register ranges. Using an empty ranges property works but causes a DT warning when we give this node an address. Fix this by explicitly defining the memory ranges in use. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20240326205920.40147-4-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index b47338e0f481..2e18d91ae92f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -672,10 +672,13 @@ fss: bus@47000000 { compatible = "simple-bus"; - reg = <0x00 0x47000000 0x00 0x100>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ + <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ + <0x0 0x47050000 0x0 0x47050000 0x0 0x100>, /* OSPI1 Control */ + <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>, /* OSPI0 Memory */ + <0x7 0x00000000 0x7 0x00000000 0x1 0x0000000>; /* OSPI1 Memory */ ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; From 2eeb74c449e910851fa48f4868ec0edadaa28f08 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:04:00 +0100 Subject: [PATCH 726/969] bus: etzpc: introduce ETZPC firewall controller driver ETZPC is a peripheral and memory firewall controller that filter accesses based on Arm TrustZone secure state and Arm CPU privilege execution level. It handles MCU isolation as well. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_etzpc.c | 141 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_etzpc.c diff --git a/MAINTAINERS b/MAINTAINERS index 43ec60410657..fcbf46a399cb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20814,6 +20814,7 @@ F: drivers/media/i2c/st-mipid02.c ST STM32 FIREWALL M: Gatien Chevallier S: Maintained +F: drivers/bus/stm32_etzpc.c F: drivers/bus/stm32_firewall.c F: drivers/bus/stm32_rifsc.c diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index e50d18e1d141..cddd4984d6af 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o stm32_etzpc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_etzpc.c b/drivers/bus/stm32_etzpc.c new file mode 100644 index 000000000000..7fc0f16960be --- /dev/null +++ b/drivers/bus/stm32_etzpc.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* + * ETZPC registers + */ +#define ETZPC_DECPROT 0x10 +#define ETZPC_HWCFGR 0x3F0 + +/* + * HWCFGR register + */ +#define ETZPC_HWCFGR_NUM_TZMA GENMASK(7, 0) +#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8) +#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16) +#define ETZPC_HWCFGR_CHUNKS1N4 GENMASK(31, 24) + +/* + * ETZPC miscellaneous + */ +#define ETZPC_PROT_MASK GENMASK(1, 0) +#define ETZPC_PROT_A7NS 0x3 +#define ETZPC_DECPROT_SHIFT 1 + +#define IDS_PER_DECPROT_REGS 16 + +static int stm32_etzpc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + u32 offset, reg_offset, sec_val; + + if (firewall_id >= ctrl->max_entries) { + dev_err(ctrl->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* Check access configuration, 16 peripherals per register */ + reg_offset = ETZPC_DECPROT + 0x4 * (firewall_id / IDS_PER_DECPROT_REGS); + offset = (firewall_id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT; + + /* Verify peripheral is non-secure and attributed to cortex A7 */ + sec_val = (readl(ctrl->mmio + reg_offset) >> offset) & ETZPC_PROT_MASK; + if (sec_val != ETZPC_PROT_A7NS) { + dev_dbg(ctrl->dev, "Invalid bus configuration: reg_offset %#x, value %d\n", + reg_offset, sec_val); + return -EACCES; + } + + return 0; +} + +static void stm32_etzpc_release_access(struct stm32_firewall_controller *ctrl __maybe_unused, + u32 firewall_id __maybe_unused) +{ +} + +static int stm32_etzpc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *etzpc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_per, nb_master; + struct resource *res; + void __iomem *mmio; + int rc; + + etzpc_controller = devm_kzalloc(&pdev->dev, sizeof(*etzpc_controller), GFP_KERNEL); + if (!etzpc_controller) + return -ENOMEM; + + mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + etzpc_controller->dev = &pdev->dev; + etzpc_controller->mmio = mmio; + etzpc_controller->name = dev_driver_string(etzpc_controller->dev); + etzpc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + etzpc_controller->grant_access = stm32_etzpc_grant_access; + etzpc_controller->release_access = stm32_etzpc_release_access; + + /* Get number of etzpc entries*/ + nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + etzpc_controller->max_entries = nb_per + nb_master; + + platform_set_drvdata(pdev, etzpc_controller); + + rc = stm32_firewall_controller_register(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + rc = stm32_firewall_populate_bus(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't populate ETZPC bus: %d", + rc); + return rc; + } + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_etzpc_of_match[] = { + { .compatible = "st,stm32-etzpc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_etzpc_of_match); + +static struct platform_driver stm32_etzpc_driver = { + .probe = stm32_etzpc_probe, + .driver = { + .name = "stm32-etzpc", + .of_match_table = stm32_etzpc_of_match, + }, +}; +module_platform_driver(stm32_etzpc_driver); + +MODULE_AUTHOR("Gatien Chevallier "); +MODULE_DESCRIPTION("STMicroelectronics ETZPC driver"); +MODULE_LICENSE("GPL"); From e4500d7525f9223a0a46431caa6d0f2d165f05ce Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 12 Apr 2024 11:25:37 +0300 Subject: [PATCH 727/969] bus: stm32_firewall: fix off by one in stm32_firewall_get_firewall() The "nb_firewall" variable is the number of elements in the firewall[] array, which is allocated in stm32_firewall_populate_bus(). So change this > comparison to >= to prevent an out of bound access. Fixes: 5c9668cfc6d7 ("firewall: introduce stm32_firewall framework") Signed-off-by: Dan Carpenter Reviewed-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- drivers/bus/stm32_firewall.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c index decb79449047..2fc9761dadec 100644 --- a/drivers/bus/stm32_firewall.c +++ b/drivers/bus/stm32_firewall.c @@ -53,7 +53,7 @@ int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *f return err; } - if (j > nb_firewall) { + if (j >= nb_firewall) { pr_err("Too many firewall controllers"); of_node_put(provider); return -EINVAL; From 7666e9ec9b58f64e4a1a462620ae3d0015ee39bf Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:03:59 +0100 Subject: [PATCH 728/969] arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards RIFSC is a firewall controller. Add "st,stm32mp25-rifsc" compatible and reference RIFSC as an access-control-provider. Keep "simple-bus" compatible backward compatibility. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 ++++-- arch/arm64/boot/dts/st/stm32mp255.dtsi | 33 +++++++++++++------------- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5dd4f3580a60..af1444bf9442 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -123,11 +123,12 @@ interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; usart2: serial@400e0000 { @@ -135,6 +136,7 @@ reg = <0x400e0000 0x400>; interrupts = ; clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; status = "disabled"; }; @@ -148,6 +150,7 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + access-controllers = <&rifsc 76>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 17f197c5b22b..570c5dd0b2c3 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,22 +5,21 @@ */ #include "stm32mp253.dtsi" -/ { - soc@0 { - rifsc: rifsc-bus@42080000 { - vdec: vdec@480d0000 { - compatible = "st,stm32mp25-vdec"; - reg = <0x480d0000 0x3c8>; - interrupts = ; - clocks = <&ck_icn_p_vdec>; - }; +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&ck_icn_p_vdec>; + access-controllers = <&rifsc 89>; - venc: venc@480e0000 { - compatible = "st,stm32mp25-venc"; - reg = <0x480e0000 0x800>; - interrupts = ; - clocks = <&ck_icn_ls_mcu>; - }; - }; }; -}; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = ; + clocks = <&ck_icn_ls_mcu>; + access-controllers = <&rifsc 90>; + }; +}; \ No newline at end of file From f9b497f7fb8c322ee27808154122553ceafc17c3 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:04:01 +0100 Subject: [PATCH 729/969] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for backward compatibility. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151.dtsi | 2662 +++++++++++++------------ arch/arm/boot/dts/st/stm32mp153.dtsi | 50 +- arch/arm/boot/dts/st/stm32mp15xc.dtsi | 18 +- 3 files changed, 1368 insertions(+), 1362 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index fa4cbd312e5a..b508423936bf 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -122,1042 +122,6 @@ interrupt-parent = <&intc>; ranges; - timers2: timer@40000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40000000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM2_K>; - clock-names = "int"; - dmas = <&dmamux1 18 0x400 0x1>, - <&dmamux1 19 0x400 0x1>, - <&dmamux1 20 0x400 0x1>, - <&dmamux1 21 0x400 0x1>, - <&dmamux1 22 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@1 { - compatible = "st,stm32h7-timer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers3: timer@40001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40001000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM3_K>; - clock-names = "int"; - dmas = <&dmamux1 23 0x400 0x1>, - <&dmamux1 24 0x400 0x1>, - <&dmamux1 25 0x400 0x1>, - <&dmamux1 26 0x400 0x1>, - <&dmamux1 27 0x400 0x1>, - <&dmamux1 28 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@2 { - compatible = "st,stm32h7-timer-trigger"; - reg = <2>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers4: timer@40002000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40002000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM4_K>; - clock-names = "int"; - dmas = <&dmamux1 29 0x400 0x1>, - <&dmamux1 30 0x400 0x1>, - <&dmamux1 31 0x400 0x1>, - <&dmamux1 32 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@3 { - compatible = "st,stm32h7-timer-trigger"; - reg = <3>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers5: timer@40003000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40003000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM5_K>; - clock-names = "int"; - dmas = <&dmamux1 55 0x400 0x1>, - <&dmamux1 56 0x400 0x1>, - <&dmamux1 57 0x400 0x1>, - <&dmamux1 58 0x400 0x1>, - <&dmamux1 59 0x400 0x1>, - <&dmamux1 60 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@4 { - compatible = "st,stm32h7-timer-trigger"; - reg = <4>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers6: timer@40004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40004000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM6_K>; - clock-names = "int"; - dmas = <&dmamux1 69 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@5 { - compatible = "st,stm32h7-timer-trigger"; - reg = <5>; - status = "disabled"; - }; - }; - - timers7: timer@40005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40005000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM7_K>; - clock-names = "int"; - dmas = <&dmamux1 70 0x400 0x1>; - dma-names = "up"; - status = "disabled"; - - timer@6 { - compatible = "st,stm32h7-timer-trigger"; - reg = <6>; - status = "disabled"; - }; - }; - - timers12: timer@40006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40006000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@40007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@40008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x40008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - lptimer1: timer@40009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x40009000 0x400>; - interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM1_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@0 { - compatible = "st,stm32-lptimer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - spi2: spi@4000b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000b000 0x400>; - interrupts = ; - clocks = <&rcc SPI2_K>; - resets = <&rcc SPI2_R>; - dmas = <&dmamux1 39 0x400 0x05>, - <&dmamux1 40 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s2: audio-controller@4000b000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000b000 0x400>; - interrupts = ; - dmas = <&dmamux1 39 0x400 0x01>, - <&dmamux1 40 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi3: spi@4000c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x4000c000 0x400>; - interrupts = ; - clocks = <&rcc SPI3_K>; - resets = <&rcc SPI3_R>; - dmas = <&dmamux1 61 0x400 0x05>, - <&dmamux1 62 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s3: audio-controller@4000c000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x4000c000 0x400>; - interrupts = ; - dmas = <&dmamux1 61 0x400 0x01>, - <&dmamux1 62 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spdifrx: audio-controller@4000d000 { - compatible = "st,stm32h7-spdifrx"; - #sound-dai-cells = <0>; - reg = <0x4000d000 0x400>; - clocks = <&rcc SPDIF_K>; - clock-names = "kclk"; - interrupts = ; - dmas = <&dmamux1 93 0x400 0x01>, - <&dmamux1 94 0x400 0x01>; - dma-names = "rx", "rx-ctrl"; - status = "disabled"; - }; - - usart2: serial@4000e000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000e000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x15>, - <&dmamux1 44 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart3: serial@4000f000 { - compatible = "st,stm32h7-uart"; - reg = <0x4000f000 0x400>; - interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART3_K>; - wakeup-source; - dmas = <&dmamux1 45 0x400 0x15>, - <&dmamux1 46 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart4: serial@40010000 { - compatible = "st,stm32h7-uart"; - reg = <0x40010000 0x400>; - interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART4_K>; - wakeup-source; - dmas = <&dmamux1 63 0x400 0x15>, - <&dmamux1 64 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart5: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART5_K>; - wakeup-source; - dmas = <&dmamux1 65 0x400 0x15>, - <&dmamux1 66 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c1: i2c@40012000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40012000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C1_K>; - resets = <&rcc I2C1_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x1>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c2: i2c@40013000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40013000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C2_K>; - resets = <&rcc I2C2_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x2>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c3: i2c@40014000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40014000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@40015000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x40015000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - - cec: cec@40016000 { - compatible = "st,stm32-cec"; - reg = <0x40016000 0x400>; - interrupts = ; - clocks = <&rcc CEC_K>, <&rcc CEC>; - clock-names = "cec", "hdmi-cec"; - status = "disabled"; - }; - - dac: dac@40017000 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40017000 0x400>; - clocks = <&rcc DAC12>; - clock-names = "pclk"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <1>; - status = "disabled"; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channel-cells = <1>; - reg = <2>; - status = "disabled"; - }; - }; - - uart7: serial@40018000 { - compatible = "st,stm32h7-uart"; - reg = <0x40018000 0x400>; - interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART7_K>; - wakeup-source; - dmas = <&dmamux1 79 0x400 0x15>, - <&dmamux1 80 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart8: serial@40019000 { - compatible = "st,stm32h7-uart"; - reg = <0x40019000 0x400>; - interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc UART8_K>; - wakeup-source; - dmas = <&dmamux1 81 0x400 0x15>, - <&dmamux1 82 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers1: timer@44000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44000000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM1_K>; - clock-names = "int"; - dmas = <&dmamux1 11 0x400 0x1>, - <&dmamux1 12 0x400 0x1>, - <&dmamux1 13 0x400 0x1>, - <&dmamux1 14 0x400 0x1>, - <&dmamux1 15 0x400 0x1>, - <&dmamux1 16 0x400 0x1>, - <&dmamux1 17 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@0 { - compatible = "st,stm32h7-timer-trigger"; - reg = <0>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - timers8: timer@44001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44001000 0x400>; - interrupts = , - , - , - ; - interrupt-names = "brk", "up", "trg-com", "cc"; - clocks = <&rcc TIM8_K>; - clock-names = "int"; - dmas = <&dmamux1 47 0x400 0x1>, - <&dmamux1 48 0x400 0x1>, - <&dmamux1 49 0x400 0x1>, - <&dmamux1 50 0x400 0x1>, - <&dmamux1 51 0x400 0x1>, - <&dmamux1 52 0x400 0x1>, - <&dmamux1 53 0x400 0x1>; - dma-names = "ch1", "ch2", "ch3", "ch4", - "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@7 { - compatible = "st,stm32h7-timer-trigger"; - reg = <7>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-timer-counter"; - status = "disabled"; - }; - }; - - usart6: serial@44003000 { - compatible = "st,stm32h7-uart"; - reg = <0x44003000 0x400>; - interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART6_K>; - wakeup-source; - dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi1: spi@44004000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44004000 0x400>; - interrupts = ; - clocks = <&rcc SPI1_K>; - resets = <&rcc SPI1_R>; - dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s1: audio-controller@44004000 { - compatible = "st,stm32h7-i2s"; - #sound-dai-cells = <0>; - reg = <0x44004000 0x400>; - interrupts = ; - dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@44005000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44005000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - timers15: timer@44006000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44006000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@44007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@44008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x44008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - - spi5: spi@44009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x44009000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - sai1: sai@4400a000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400a000 0x400>; - reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; - interrupts = ; - resets = <&rcc SAI1_R>; - status = "disabled"; - - sai1a: audio-controller@4400a004 { - #sound-dai-cells = <0>; - - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 87 0x400 0x01>; - status = "disabled"; - }; - - sai1b: audio-controller@4400a024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI1_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 88 0x400 0x01>; - status = "disabled"; - }; - }; - - sai2: sai@4400b000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400b000 0x400>; - reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; - interrupts = ; - resets = <&rcc SAI2_R>; - status = "disabled"; - - sai2a: audio-controller@4400b004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x4 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 89 0x400 0x01>; - status = "disabled"; - }; - - sai2b: audio-controller@4400b024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 90 0x400 0x01>; - status = "disabled"; - }; - }; - - sai3: sai@4400c000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x4400c000 0x400>; - reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; - interrupts = ; - resets = <&rcc SAI3_R>; - status = "disabled"; - - sai3a: audio-controller@4400c004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 113 0x400 0x01>; - status = "disabled"; - }; - - sai3b: audio-controller@4400c024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI3_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 114 0x400 0x01>; - status = "disabled"; - }; - }; - - dfsdm: dfsdm@4400d000 { - compatible = "st,stm32mp1-dfsdm"; - reg = <0x4400d000 0x800>; - clocks = <&rcc DFSDM_K>; - clock-names = "dfsdm"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - dfsdm0: filter@0 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <0>; - interrupts = ; - dmas = <&dmamux1 101 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm1: filter@1 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <1>; - interrupts = ; - dmas = <&dmamux1 102 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm2: filter@2 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <2>; - interrupts = ; - dmas = <&dmamux1 103 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm3: filter@3 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <3>; - interrupts = ; - dmas = <&dmamux1 104 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm4: filter@4 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <4>; - interrupts = ; - dmas = <&dmamux1 91 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - dfsdm5: filter@5 { - compatible = "st,stm32-dfsdm-adc"; - #io-channel-cells = <1>; - reg = <5>; - interrupts = ; - dmas = <&dmamux1 92 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - }; - - dma1: dma-controller@48000000 { - compatible = "st,stm32-dma"; - reg = <0x48000000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA1>; - resets = <&rcc DMA1_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dma2: dma-controller@48001000 { - compatible = "st,stm32-dma"; - reg = <0x48001000 0x400>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&rcc DMA2>; - resets = <&rcc DMA2_R>; - #dma-cells = <4>; - st,mem2mem; - dma-requests = <8>; - }; - - dmamux1: dma-router@48002000 { - compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x40>; - #dma-cells = <3>; - dma-requests = <128>; - dma-masters = <&dma1 &dma2>; - dma-channels = <16>; - clocks = <&rcc DMAMUX>; - resets = <&rcc DMAMUX_R>; - }; - - adc: adc@48003000 { - compatible = "st,stm32mp1-adc-core"; - reg = <0x48003000 0x400>; - interrupts = , - ; - clocks = <&rcc ADC12>, <&rcc ADC12_K>; - clock-names = "bus", "adc"; - interrupt-controller; - st,syscfg = <&syscfg>; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc1: adc@0 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x01>; - dma-names = "rx"; - status = "disabled"; - }; - - adc2: adc@100 { - compatible = "st,stm32mp1-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100>; - interrupt-parent = <&adc>; - interrupts = <1>; - dmas = <&dmamux1 10 0x400 0x01>; - dma-names = "rx"; - nvmem-cells = <&vrefint>; - nvmem-cell-names = "vrefint"; - status = "disabled"; - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - }; - }; - - sdmmc3: mmc@48004000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; - reg = <0x48004000 0x400>; - interrupts = ; - clocks = <&rcc SDMMC3_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC3_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <120000000>; - status = "disabled"; - }; - - usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>, <&usbphyc>; - clock-names = "otg", "utmi"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&usb33>; - status = "disabled"; - }; - ipcc: mailbox@4c001000 { compatible = "st,stm32mp1-ipcc"; #mbox-cells = <1>; @@ -1172,18 +136,6 @@ status = "disabled"; }; - dcmi: dcmi@4c006000 { - compatible = "st,stm32-dcmi"; - reg = <0x4c006000 0x400>; - interrupts = ; - resets = <&rcc CAMITF_R>; - clocks = <&rcc DCMI>; - clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x01>; - dma-names = "tx"; - status = "disabled"; - }; - rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -1232,131 +184,6 @@ clocks = <&rcc SYSCFG>; }; - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - }; - - lptimer4: timer@50023000 { - compatible = "st,stm32-lptimer"; - reg = <0x50023000 0x400>; - interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM4_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - lptimer5: timer@50024000 { - compatible = "st,stm32-lptimer"; - reg = <0x50024000 0x400>; - interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM5_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - }; - - vrefbuf: vrefbuf@50025000 { - compatible = "st,stm32-vrefbuf"; - reg = <0x50025000 0x8>; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2500000>; - clocks = <&rcc VREF>; - status = "disabled"; - }; - - sai4: sai@50027000 { - compatible = "st,stm32h7-sai"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x50027000 0x400>; - reg = <0x50027000 0x4>, <0x500273f0 0x10>; - interrupts = ; - resets = <&rcc SAI4_R>; - status = "disabled"; - - sai4a: audio-controller@50027004 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-a"; - reg = <0x04 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 99 0x400 0x01>; - status = "disabled"; - }; - - sai4b: audio-controller@50027024 { - #sound-dai-cells = <0>; - compatible = "st,stm32-sai-sub-b"; - reg = <0x24 0x20>; - clocks = <&rcc SAI4_K>; - clock-names = "sai_ck"; - dmas = <&dmamux1 100 0x400 0x01>; - status = "disabled"; - }; - }; - dts: thermal@50028000 { compatible = "st,stm32-thermal"; reg = <0x50028000 0x100>; @@ -1367,26 +194,6 @@ status = "disabled"; }; - hash1: hash@54002000 { - compatible = "st,stm32f756-hash"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; - dma-names = "in"; - dma-maxburst = <2>; - status = "disabled"; - }; - - rng1: rng@54003000 { - compatible = "st,stm32-rng"; - reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -1398,55 +205,6 @@ dma-requests = <48>; }; - fmc: memory-controller@58002000 { - #address-cells = <2>; - #size-cells = <1>; - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - - nand-controller@4,0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - interrupts = ; - dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, - <&mdma1 20 0x2 0x12000a08 0x0 0x0>, - <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = ; - dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, - <&mdma1 22 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; @@ -1482,39 +240,6 @@ status = "disabled"; }; - ethernet0: ethernet@5800a000 { - compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; - reg = <0x5800a000 0x2000>; - reg-names = "stmmaceth"; - interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "eth-ck", - "ptp_ref", - "ethstp"; - clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHCK_K>, - <&rcc ETHPTP_K>, - <&rcc ETHSTP>; - st,syscon = <&syscfg 0x4>; - snps,mixed-burst; - snps,pbl = <2>; - snps,en-tx-lpi-clockgating; - snps,axi-config = <&stmmac_axi_config_0>; - snps,tso; - status = "disabled"; - - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - }; - usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; @@ -1580,45 +305,6 @@ }; }; - usart1: serial@5c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x5c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - wakeup-source; - status = "disabled"; - }; - - spi6: spi@5c001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32h7-spi"; - reg = <0x5c001000 0x400>; - interrupts = ; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; - dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, - <&mdma1 35 0x0 0x40002 0x0 0x0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c4: i2c@5c002000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c002000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; - }; - rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -1647,20 +333,1342 @@ }; }; - i2c6: i2c@5c009000 { - compatible = "st,stm32mp15-i2c"; - reg = <0x5c009000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; + etzpc: bus@5c007000 { + compatible = "simple-bus"; + reg = <0x5c007000 0x400>; #address-cells = <1>; - #size-cells = <0>; - st,syscfg-fmp = <&syscfg 0x4 0x20>; - wakeup-source; - i2c-analog-filter; - status = "disabled"; + #size-cells = <1>; + ranges; + + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + timers12: timer@40006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40006000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@40007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@40008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000b000 0x400>; + interrupts = ; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi2: spi@4000b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = ; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x4000c000 0x400>; + interrupts = ; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = ; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + + usart2: serial@4000e000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000e000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART4_K>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c1: i2c@40012000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c3: i2c@40014000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40014000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@40015000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x40015000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + cec: cec@40016000 { + compatible = "st,stm32-cec"; + reg = <0x40016000 0x400>; + interrupts = ; + clocks = <&rcc CEC_K>, <&rcc CEC>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + status = "disabled"; + }; + + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + status = "disabled"; + }; + }; + + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + #sound-dai-cells = <0>; + reg = <0x44004000 0x400>; + interrupts = ; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@44004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = ; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@44005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44005000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@44007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x44009000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400a000 0x400>; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = ; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + #sound-dai-cells = <0>; + + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400b000 0x400>; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = ; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + sai3: sai@4400c000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x4400c000 0x400>; + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = ; + resets = <&rcc SAI3_R>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 113 0x400 0x01>; + status = "disabled"; + }; + + sai3b: audio-controller@4400c024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI3_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 114 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <0>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm2: filter@2 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <2>; + interrupts = ; + dmas = <&dmamux1 103 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm3: filter@3 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <3>; + interrupts = ; + dmas = <&dmamux1 104 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm4: filter@4 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <4>; + interrupts = ; + dmas = <&dmamux1 91 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm5: filter@5 { + compatible = "st,stm32-dfsdm-adc"; + #io-channel-cells = <1>; + reg = <5>; + interrupts = ; + dmas = <&dmamux1 92 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; + }; + + adc: adc@48003000 { + compatible = "st,stm32mp1-adc-core"; + reg = <0x48003000 0x400>; + interrupts = , + ; + clocks = <&rcc ADC12>, <&rcc ADC12_K>; + clock-names = "bus", "adc"; + interrupt-controller; + st,syscfg = <&syscfg>; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32mp1-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x100>; + interrupt-parent = <&adc>; + interrupts = <1>; + dmas = <&dmamux1 10 0x400 0x01>; + dma-names = "rx"; + nvmem-cells = <&vrefint>; + nvmem-cell-names = "vrefint"; + status = "disabled"; + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + }; + }; + + sdmmc3: mmc@48004000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00253180>; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC3_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + status = "disabled"; + }; + + usbotg_hs: usb-otg@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x10000>; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + dcmi: dcmi@4c006000 { + compatible = "st,stm32-dcmi"; + reg = <0x4c006000 0x400>; + interrupts = ; + resets = <&rcc CAMITF_R>; + clocks = <&rcc DCMI>; + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x01>; + dma-names = "tx"; + status = "disabled"; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + status = "disabled"; + }; + + sai4: sai@50027000 { + compatible = "st,stm32h7-sai"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x50027000 0x400>; + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = ; + resets = <&rcc SAI4_R>; + status = "disabled"; + + sai4a: audio-controller@50027004 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-a"; + reg = <0x04 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 99 0x400 0x01>; + status = "disabled"; + }; + + sai4b: audio-controller@50027024 { + #sound-dai-cells = <0>; + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + clocks = <&rcc SAI4_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 100 0x400 0x01>; + status = "disabled"; + }; + }; + + hash1: hash@54002000 { + compatible = "st,stm32f756-hash"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; + status = "disabled"; + }; + + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4>; + snps,mixed-burst; + snps,pbl = <2>; + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; + + usart1: serial@5c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x5c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + wakeup-source; + status = "disabled"; + }; + + spi6: spi@5c001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x5c001000 0x400>; + interrupts = ; + clocks = <&rcc SPI6_K>; + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@5c002000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c002000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; + + i2c6: i2c@5c009000 { + compatible = "st,stm32mp15-i2c"; + reg = <0x5c009000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C6_K>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; + i2c-analog-filter; + status = "disabled"; + }; }; tamp: tamp@5c00a000 { diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 486084e0b80b..36e17ea0b179 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -28,32 +28,32 @@ , ; }; +}; - soc { - m_can1: can@4400e000 { - compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x1400>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; - status = "disabled"; - }; +&etzpc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; - m_can2: can@4400f000 { - compatible = "bosch,m_can"; - reg = <0x4400f000 0x400>, <0x44011000 0x2800>; - reg-names = "m_can", "message_ram"; - interrupts = , - ; - interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; - status = "disabled"; - }; + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi index b06a55a2fa18..d36c3457451a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -4,15 +4,13 @@ * Author: Alexandre Torgue for STMicroelectronics. */ -/ { - soc { - cryp1: cryp@54001000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54001000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; }; }; From ad4263523f5175e9cff7be72c9fb4b4a56a8b451 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:04:02 +0100 Subject: [PATCH 730/969] ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP15 reference manual Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151.dtsi | 66 ++++++++++++++++++++++++++- arch/arm/boot/dts/st/stm32mp153.dtsi | 2 + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 + 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b508423936bf..16bd6eee32b4 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -334,10 +334,11 @@ }; etzpc: bus@5c007000 { - compatible = "simple-bus"; + compatible = "st,stm32-etzpc", "simple-bus"; reg = <0x5c007000 0x400>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; timers2: timer@40000000 { @@ -355,6 +356,7 @@ <&dmamux1 21 0x400 0x1>, <&dmamux1 22 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + access-controllers = <&etzpc 16>; status = "disabled"; pwm { @@ -391,6 +393,7 @@ <&dmamux1 27 0x400 0x1>, <&dmamux1 28 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc 17>; status = "disabled"; pwm { @@ -425,6 +428,7 @@ <&dmamux1 31 0x400 0x1>, <&dmamux1 32 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4"; + access-controllers = <&etzpc 18>; status = "disabled"; pwm { @@ -461,6 +465,7 @@ <&dmamux1 59 0x400 0x1>, <&dmamux1 60 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc 19>; status = "disabled"; pwm { @@ -492,6 +497,7 @@ clock-names = "int"; dmas = <&dmamux1 69 0x400 0x1>; dma-names = "up"; + access-controllers = <&etzpc 20>; status = "disabled"; timer@5 { @@ -512,6 +518,7 @@ clock-names = "int"; dmas = <&dmamux1 70 0x400 0x1>; dma-names = "up"; + access-controllers = <&etzpc 21>; status = "disabled"; timer@6 { @@ -530,6 +537,7 @@ interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; + access-controllers = <&etzpc 22>; status = "disabled"; pwm { @@ -554,6 +562,7 @@ interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; + access-controllers = <&etzpc 23>; status = "disabled"; pwm { @@ -578,6 +587,7 @@ interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; + access-controllers = <&etzpc 24>; status = "disabled"; pwm { @@ -602,6 +612,7 @@ clocks = <&rcc LPTIM1_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 25>; status = "disabled"; pwm { @@ -630,6 +641,7 @@ dmas = <&dmamux1 39 0x400 0x01>, <&dmamux1 40 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 27>; status = "disabled"; }; @@ -644,6 +656,7 @@ dmas = <&dmamux1 39 0x400 0x05>, <&dmamux1 40 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 27>; status = "disabled"; }; @@ -655,6 +668,7 @@ dmas = <&dmamux1 61 0x400 0x01>, <&dmamux1 62 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 28>; status = "disabled"; }; @@ -669,6 +683,7 @@ dmas = <&dmamux1 61 0x400 0x05>, <&dmamux1 62 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 28>; status = "disabled"; }; @@ -682,6 +697,7 @@ dmas = <&dmamux1 93 0x400 0x01>, <&dmamux1 94 0x400 0x01>; dma-names = "rx", "rx-ctrl"; + access-controllers = <&etzpc 29>; status = "disabled"; }; @@ -694,6 +710,7 @@ dmas = <&dmamux1 43 0x400 0x15>, <&dmamux1 44 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 30>; status = "disabled"; }; @@ -706,6 +723,7 @@ dmas = <&dmamux1 45 0x400 0x15>, <&dmamux1 46 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 31>; status = "disabled"; }; @@ -718,6 +736,7 @@ dmas = <&dmamux1 63 0x400 0x15>, <&dmamux1 64 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 32>; status = "disabled"; }; @@ -730,6 +749,7 @@ dmas = <&dmamux1 65 0x400 0x15>, <&dmamux1 66 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 33>; status = "disabled"; }; @@ -746,6 +766,7 @@ st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 34>; status = "disabled"; }; @@ -762,6 +783,7 @@ st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 35>; status = "disabled"; }; @@ -778,6 +800,7 @@ st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 36>; status = "disabled"; }; @@ -794,6 +817,7 @@ st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 37>; status = "disabled"; }; @@ -803,6 +827,7 @@ interrupts = ; clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; + access-controllers = <&etzpc 38>; status = "disabled"; }; @@ -813,6 +838,7 @@ clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 39>; status = "disabled"; dac1: dac@1 { @@ -839,6 +865,7 @@ dmas = <&dmamux1 79 0x400 0x15>, <&dmamux1 80 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 40>; status = "disabled"; }; @@ -851,6 +878,7 @@ dmas = <&dmamux1 81 0x400 0x15>, <&dmamux1 82 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 41>; status = "disabled"; }; @@ -875,6 +903,7 @@ <&dmamux1 17 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; + access-controllers = <&etzpc 48>; status = "disabled"; pwm { @@ -916,6 +945,7 @@ <&dmamux1 53 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; + access-controllers = <&etzpc 49>; status = "disabled"; pwm { @@ -945,6 +975,7 @@ dmas = <&dmamux1 71 0x400 0x15>, <&dmamux1 72 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 51>; status = "disabled"; }; @@ -956,6 +987,7 @@ dmas = <&dmamux1 37 0x400 0x01>, <&dmamux1 38 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 52>; status = "disabled"; }; @@ -970,6 +1002,7 @@ dmas = <&dmamux1 37 0x400 0x05>, <&dmamux1 38 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 52>; status = "disabled"; }; @@ -984,6 +1017,7 @@ dmas = <&dmamux1 83 0x400 0x05>, <&dmamux1 84 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 53>; status = "disabled"; }; @@ -1001,6 +1035,7 @@ <&dmamux1 107 0x400 0x1>, <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; + access-controllers = <&etzpc 54>; status = "disabled"; pwm { @@ -1028,6 +1063,7 @@ dmas = <&dmamux1 109 0x400 0x1>, <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 55>; status = "disabled"; pwm { @@ -1054,6 +1090,7 @@ dmas = <&dmamux1 111 0x400 0x1>, <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 56>; status = "disabled"; pwm { @@ -1080,6 +1117,7 @@ dmas = <&dmamux1 85 0x400 0x05>, <&dmamux1 86 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 57>; status = "disabled"; }; @@ -1091,6 +1129,7 @@ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; interrupts = ; resets = <&rcc SAI1_R>; + access-controllers = <&etzpc 58>; status = "disabled"; sai1a: audio-controller@4400a004 { @@ -1123,6 +1162,7 @@ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; interrupts = ; resets = <&rcc SAI2_R>; + access-controllers = <&etzpc 59>; status = "disabled"; sai2a: audio-controller@4400b004 { @@ -1154,6 +1194,7 @@ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; interrupts = ; resets = <&rcc SAI3_R>; + access-controllers = <&etzpc 60>; status = "disabled"; sai3a: audio-controller@4400c004 { @@ -1184,6 +1225,7 @@ clock-names = "dfsdm"; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 61>; status = "disabled"; dfsdm0: filter@0 { @@ -1263,6 +1305,7 @@ #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + access-controllers = <&etzpc 88>; }; dma2: dma-controller@48001000 { @@ -1281,6 +1324,7 @@ #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + access-controllers = <&etzpc 89>; }; dmamux1: dma-router@48002000 { @@ -1292,6 +1336,7 @@ dma-channels = <16>; clocks = <&rcc DMAMUX>; resets = <&rcc DMAMUX_R>; + access-controllers = <&etzpc 90>; }; adc: adc@48003000 { @@ -1306,6 +1351,7 @@ #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 72>; status = "disabled"; adc1: adc@0 { @@ -1356,6 +1402,7 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + access-controllers = <&etzpc 86>; status = "disabled"; }; @@ -1373,6 +1420,7 @@ dr_mode = "otg"; otg-rev = <0x200>; usb33d-supply = <&usb33>; + access-controllers = <&etzpc 85>; status = "disabled"; }; @@ -1385,6 +1433,7 @@ clock-names = "mclk"; dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; + access-controllers = <&etzpc 70>; status = "disabled"; }; @@ -1397,6 +1446,7 @@ clocks = <&rcc LPTIM2_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 64>; status = "disabled"; pwm { @@ -1426,6 +1476,7 @@ clocks = <&rcc LPTIM3_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 65>; status = "disabled"; pwm { @@ -1448,6 +1499,7 @@ clocks = <&rcc LPTIM4_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 66>; status = "disabled"; pwm { @@ -1464,6 +1516,7 @@ clocks = <&rcc LPTIM5_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 67>; status = "disabled"; pwm { @@ -1479,6 +1532,7 @@ regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2500000>; clocks = <&rcc VREF>; + access-controllers = <&etzpc 69>; status = "disabled"; }; @@ -1490,6 +1544,7 @@ reg = <0x50027000 0x4>, <0x500273f0 0x10>; interrupts = ; resets = <&rcc SAI4_R>; + access-controllers = <&etzpc 68>; status = "disabled"; sai4a: audio-controller@50027004 { @@ -1522,6 +1577,7 @@ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; + access-controllers = <&etzpc 8>; status = "disabled"; }; @@ -1530,6 +1586,7 @@ reg = <0x54003000 0x400>; clocks = <&rcc RNG1_K>; resets = <&rcc RNG1_R>; + access-controllers = <&etzpc 7>; status = "disabled"; }; @@ -1540,6 +1597,7 @@ reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; + access-controllers = <&etzpc 91>; status = "disabled"; ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ @@ -1579,6 +1637,7 @@ resets = <&rcc QSPI_R>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 92>; status = "disabled"; }; @@ -1606,6 +1665,7 @@ snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; + access-controllers = <&etzpc 94>; status = "disabled"; stmmac_axi_config_0: stmmac-axi-config { @@ -1621,6 +1681,7 @@ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART1_K>; wakeup-source; + access-controllers = <&etzpc 3>; status = "disabled"; }; @@ -1634,6 +1695,7 @@ resets = <&rcc SPI6_R>; dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, <&mdma1 35 0x0 0x40002 0x0 0x0>; + access-controllers = <&etzpc 4>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -1651,6 +1713,7 @@ st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 5>; status = "disabled"; }; @@ -1667,6 +1730,7 @@ st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 12>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 36e17ea0b179..4640dafb1598 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -41,6 +41,7 @@ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + access-controllers = <&etzpc 62>; status = "disabled"; }; @@ -54,6 +55,7 @@ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + access-controllers = <&etzpc 62>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi index d36c3457451a..97465717f932 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -11,6 +11,7 @@ interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 9>; status = "disabled"; }; }; From a06b9560eb6c5cc50f9604179b1c72f52b904eb9 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Fri, 5 Jan 2024 14:04:03 +0100 Subject: [PATCH 731/969] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for backward compatibility. Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 1038 +++++++++++++------------ arch/arm/boot/dts/st/stm32mp133.dtsi | 50 +- arch/arm/boot/dts/st/stm32mp13xc.dtsi | 18 +- arch/arm/boot/dts/st/stm32mp13xf.dtsi | 18 +- 4 files changed, 565 insertions(+), 559 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 3900f32da797..9a401da8b5cc 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -745,340 +745,6 @@ dma-channels = <16>; }; - adc_2: adc@48004000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48004000 0x400>; - interrupts = ; - clocks = <&rcc ADC2>, <&rcc ADC2_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc2: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_2>; - interrupts = <0>; - dmas = <&dmamux1 10 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - channel@16 { - reg = <16>; - label = "vddcpu"; - }; - channel@17 { - reg = <17>; - label = "vddq_ddr"; - }; - }; - }; - - usbotg_hs: usb@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x40000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&scmi_usb33>; - status = "disabled"; - }; - - usart1: serial@4c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - resets = <&rcc USART1_R>; - wakeup-source; - dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart2: serial@4c001000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c001000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - resets = <&rcc USART2_R>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s4: audio-controller@4c002000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4c002000 0x400>; - #sound-dai-cells = <0>; - interrupts = ; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@4c002000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c002000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi5: spi@4c003000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c003000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 85 0x400 0x01>, - <&dmamux1 86 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c3: i2c@4c004000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c004000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 73 0x400 0x1>, - <&dmamux1 74 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c4: i2c@4c005000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c005000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 75 0x400 0x1>, - <&dmamux1 76 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@4c006000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c006000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 115 0x400 0x1>, - <&dmamux1 116 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - i2c-analog-filter; - status = "disabled"; - }; - - timers12: timer@4c007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@4c008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@4c009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c009000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - timers15: timer@4c00a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00a000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@4c00b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00b000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@4c00c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00c000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -1105,69 +771,6 @@ clocks = <&rcc SYSCFG>; }; - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; @@ -1210,25 +813,6 @@ }; }; - hash: hash@54003000 { - compatible = "st,stm32mp13-hash"; - reg = <0x54003000 0x400>; - interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; - dma-names = "in"; - status = "disabled"; - }; - - rng: rng@54004000 { - compatible = "st,stm32mp13-rng"; - reg = <0x54004000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -1239,82 +823,6 @@ dma-requests = <48>; }; - fmc: memory-controller@58002000 { - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - #address-cells = <2>; - #size-cells = <1>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - nand-controller@4,0 { - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, - <&mdma 24 0x2 0x12000a08 0x0 0x0>, - <&mdma 25 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, - <&mdma 26 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - crc1: crc@58009000 { compatible = "st,stm32f7-crc"; reg = <0x58009000 0x400>; @@ -1349,29 +857,6 @@ status = "disabled"; }; - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <&scmi_reg11>; - vdda1v8-supply = <&scmi_reg18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -1400,6 +885,529 @@ }; }; + etzpc: bus@5c007000 { + compatible = "simple-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&scmi_usb33>; + status = "disabled"; + }; + + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + hash: hash@54003000 { + compatible = "st,stm32mp13-hash"; + reg = <0x54003000 0x400>; + interrupts = ; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; + dma-names = "in"; + status = "disabled"; + }; + + rng: rng@54004000 { + compatible = "st,stm32mp13-rng"; + reg = <0x54004000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + + fmc: memory-controller@58002000 { + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + nand-controller@4,0 { + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, + <&mdma 24 0x2 0x12000a08 0x0 0x0>, + <&mdma 25 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index df451c3c2a26..c4d3a520c14b 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -33,35 +33,37 @@ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + }; +}; - adc_1: adc@48003000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48003000 0x400>; - interrupts = ; - clocks = <&rcc ADC1>, <&rcc ADC1_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; +&etzpc { + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = ; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; #address-cells = <1>; #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; status = "disabled"; - adc1: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_1>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@18 { - reg = <18>; - label = "vrefint"; - }; + channel@18 { + reg = <18>; + label = "vrefint"; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi index 4d00e7592882..b9fb071a1471 100644 --- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi @@ -4,15 +4,13 @@ * Author: Alexandre Torgue for STMicroelectronics. */ -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi index 4d00e7592882..b9fb071a1471 100644 --- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi @@ -4,15 +4,13 @@ * Author: Alexandre Torgue for STMicroelectronics. */ -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; }; }; From c83509527529c1fcd9c1bf341d101a2372649484 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 5 Apr 2024 13:45:24 +0200 Subject: [PATCH 732/969] ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP13 reference manual Signed-off-by: Gatien Chevallier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 28 ++++++++++++++++++++++++++- arch/arm/boot/dts/st/stm32mp133.dtsi | 1 + arch/arm/boot/dts/st/stm32mp13xc.dtsi | 1 + arch/arm/boot/dts/st/stm32mp13xf.dtsi | 1 + 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 9a401da8b5cc..fa32f15dbdd2 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -886,10 +886,11 @@ }; etzpc: bus@5c007000 { - compatible = "simple-bus"; + compatible = "st,stm32-etzpc", "simple-bus"; reg = <0x5c007000 0x400>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; adc_2: adc@48004000 { @@ -902,6 +903,7 @@ #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 33>; status = "disabled"; adc2: adc@0 { @@ -949,6 +951,7 @@ dr_mode = "otg"; otg-rev = <0x200>; usb33d-supply = <&scmi_usb33>; + access-controllers = <&etzpc 34>; status = "disabled"; }; @@ -962,6 +965,7 @@ dmas = <&dmamux1 41 0x400 0x5>, <&dmamux1 42 0x400 0x1>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 16>; status = "disabled"; }; @@ -975,6 +979,7 @@ dmas = <&dmamux1 43 0x400 0x5>, <&dmamux1 44 0x400 0x1>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 17>; status = "disabled"; }; @@ -986,6 +991,7 @@ dmas = <&dmamux1 83 0x400 0x01>, <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 13>; status = "disabled"; }; @@ -1000,6 +1006,7 @@ dmas = <&dmamux1 83 0x400 0x01>, <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 18>; status = "disabled"; }; @@ -1014,6 +1021,7 @@ dmas = <&dmamux1 85 0x400 0x01>, <&dmamux1 86 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 19>; status = "disabled"; }; @@ -1032,6 +1040,7 @@ dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x4>; i2c-analog-filter; + access-controllers = <&etzpc 20>; status = "disabled"; }; @@ -1050,6 +1059,7 @@ dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x8>; i2c-analog-filter; + access-controllers = <&etzpc 21>; status = "disabled"; }; @@ -1068,6 +1078,7 @@ dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x10>; i2c-analog-filter; + access-controllers = <&etzpc 22>; status = "disabled"; }; @@ -1080,6 +1091,7 @@ interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; + access-controllers = <&etzpc 23>; status = "disabled"; pwm { @@ -1104,6 +1116,7 @@ interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; + access-controllers = <&etzpc 24>; status = "disabled"; pwm { @@ -1128,6 +1141,7 @@ interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; + access-controllers = <&etzpc 25>; status = "disabled"; pwm { @@ -1157,6 +1171,7 @@ <&dmamux1 107 0x400 0x1>, <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; + access-controllers = <&etzpc 26>; status = "disabled"; pwm { @@ -1184,6 +1199,7 @@ dmas = <&dmamux1 109 0x400 0x1>, <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 27>; status = "disabled"; pwm { @@ -1211,6 +1227,7 @@ dmas = <&dmamux1 111 0x400 0x1>, <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 28>; status = "disabled"; pwm { @@ -1235,6 +1252,7 @@ clocks = <&rcc LPTIM2_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 1>; status = "disabled"; pwm { @@ -1269,6 +1287,7 @@ clocks = <&rcc LPTIM3_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 2>; status = "disabled"; pwm { @@ -1297,6 +1316,7 @@ resets = <&rcc HASH1_R>; dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; dma-names = "in"; + access-controllers = <&etzpc 41>; status = "disabled"; }; @@ -1305,6 +1325,7 @@ reg = <0x54004000 0x400>; clocks = <&rcc RNG1_K>; resets = <&rcc RNG1_R>; + access-controllers = <&etzpc 40>; status = "disabled"; }; @@ -1320,6 +1341,7 @@ #size-cells = <1>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; + access-controllers = <&etzpc 54>; status = "disabled"; nand-controller@4,0 { @@ -1353,6 +1375,7 @@ dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; + access-controllers = <&etzpc 55>; status = "disabled"; }; @@ -1367,6 +1390,7 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; + access-controllers = <&etzpc 50>; status = "disabled"; }; @@ -1381,6 +1405,7 @@ cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; + access-controllers = <&etzpc 51>; status = "disabled"; }; @@ -1394,6 +1419,7 @@ resets = <&rcc USBPHY_R>; vdda1v1-supply = <&scmi_reg11>; vdda1v8-supply = <&scmi_reg18>; + access-controllers = <&etzpc 5>; status = "disabled"; usbphyc_port0: usb-phy@0 { diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index c4d3a520c14b..3e394c8e58b9 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -47,6 +47,7 @@ #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 32>; status = "disabled"; adc1: adc@0 { diff --git a/arch/arm/boot/dts/st/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi index b9fb071a1471..a8bd5fe6536c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi @@ -11,6 +11,7 @@ interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 42>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi index b9fb071a1471..a8bd5fe6536c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi @@ -11,6 +11,7 @@ interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 42>; status = "disabled"; }; }; From 96a9e2b2a279778204e5baf384ef264720884a35 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Mon, 25 Mar 2024 08:56:28 +0100 Subject: [PATCH 733/969] ARM: dts: stm32: move can3 node from stm32f746 to stm32f769 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to documents [1], [2] and [3], we have 2 CAN devices on the stm32f746 platform and 3 on the stm32f769 platform. So let's move the can3 node from stm32f746.dtsi to stm32f769.dtsi. [1] https://www.st.com/en/microcontrollers-microprocessors/stm32f7-series.html [2] RM0385: STM32F75xxx and STM32F74xxx advanced Arm®-based 32-bit MCUs [3] RM0410: STM32F76xxx and STM32F77xxx advanced Arm®-based 32-bit MCUs Fixes: df362914eead ("ARM: dts: stm32: re-add CAN support on stm32f746") Signed-off-by: Dario Binacchi Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f746.dtsi | 17 ----------------- arch/arm/boot/dts/st/stm32f769.dtsi | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index 65c72b6fcc83..2537b3d47e6f 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -257,23 +257,6 @@ status = "disabled"; }; - can3: can@40003400 { - compatible = "st,stm32f4-bxcan"; - reg = <0x40003400 0x200>; - interrupts = <104>, <105>, <106>, <107>; - interrupt-names = "tx", "rx0", "rx1", "sce"; - resets = <&rcc STM32F7_APB1_RESET(CAN3)>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; - st,gcan = <&gcan3>; - status = "disabled"; - }; - - gcan3: gcan@40003600 { - compatible = "st,stm32f4-gcan", "syscon"; - reg = <0x40003600 0x200>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; - }; - spi2: spi@40003800 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32f769.dtsi b/arch/arm/boot/dts/st/stm32f769.dtsi index 4e7d9032149c..e8cbb99e81a6 100644 --- a/arch/arm/boot/dts/st/stm32f769.dtsi +++ b/arch/arm/boot/dts/st/stm32f769.dtsi @@ -7,6 +7,23 @@ / { soc { + can3: can@40003400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40003400 0x200>; + interrupts = <104>, <105>, <106>, <107>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN3)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + st,gcan = <&gcan3>; + status = "disabled"; + }; + + gcan3: gcan@40003600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40003600 0x200>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + }; + dsi: dsi@40016c00 { compatible = "st,stm32-dsi"; reg = <0x40016c00 0x800>; From 9af77157d3e50829cfda5d017f1c0098b10aca22 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 26 Mar 2024 08:54:38 +0100 Subject: [PATCH 734/969] ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1 Add heartbeat led for stm32mp157c-ed1. Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index 66ed5f9921ba..9cf5ed111b52 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -10,6 +10,7 @@ #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include +#include #include / { @@ -71,6 +72,17 @@ }; }; + led { + compatible = "gpio-leds"; + led-blue { + gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + function = LED_FUNCTION_HEARTBEAT; + color = ; + }; + }; + sd_switch: regulator-sd_switch { compatible = "regulator-gpio"; regulator-name = "sd_switch"; From 13f2bdd7af142c94e2078e1b9db8408d9c1393ed Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Wed, 10 Apr 2024 16:42:22 +0200 Subject: [PATCH 735/969] media: dt-bindings: add access-controllers to STM32MP25 video codecs access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Signed-off-by: Hugues Fruchet Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/media/st,stm32mp25-video-codec.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml index b8611bc8756c..73726c65cfb9 100644 --- a/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-video-codec.yaml @@ -30,6 +30,10 @@ properties: clocks: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg From 162e813a27437c9ba45e3052c09beb7283f520ea Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 19 Mar 2024 05:05:06 +0100 Subject: [PATCH 736/969] ARM: dts: stm32: add PWR regulators support on stm32mp131 This patch adds STM32 PWR regulators DT support on stm32mp131. This requires TFA to clear RCC_SECCFGR, is disabled by default and can only be enabled on board DT level. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index fa32f15dbdd2..ecfa120827ba 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -758,6 +758,30 @@ <&scmi_clk CK_SCMI_LSI>; }; + pwr_regulators: pwr@50001000 { + compatible = "st,stm32mp1,pwr-reg"; + reg = <0x50001000 0x10>; + status = "disabled"; + + reg11: reg11 { + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp13-exti", "syscon"; interrupt-controller; From ce90d0c87f895ffbdb6c3da5d9e07ac3549e5edb Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 23 Feb 2024 13:36:51 +0100 Subject: [PATCH 737/969] dt-bindings: display: simple: allow panel-common properties This device inherits properties from panel-common. Those should be allowed to use, instead of specifying properties to true for each specific use. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- .../bindings/display/panel/panel-simple.yaml | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index a95445f40870..397e810008bd 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -348,15 +348,6 @@ properties: # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel - yes-optoelectronics,ytc700tlag-05-201c - backlight: true - ddc-i2c-bus: true - enable-gpios: true - port: true - power-supply: true - no-hpd: true - hpd-gpios: true - data-mapping: true - if: not: properties: @@ -367,7 +358,7 @@ then: properties: data-mapping: false -additionalProperties: false +unevaluatedProperties: false required: - compatible From dcb12b83ad69c0f12aa07a3e0203085dcef8765e Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 23 Feb 2024 13:36:48 +0100 Subject: [PATCH 738/969] ARM: dts: stm32: add LTDC support for STM32MP13x SoC family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal display - Thin film transistor) Display Controller. It provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD-TFT panels. Main features * 2 input layers blended together to compose the display * Cropping of layers from any input size and location * Multiple input pixel formats: – Predefined ARGB, with 7 formats: ARGB8888, ABGR8888, RGBA8888, BGRA8888, RGB565, BGR565, RGB888packed. – Flexible ARGB, allowing any width and location for A,R,G,B components. – Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV, Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L (FourCC: Yxx, full planar) with some flexibility on the sequence of the component. * Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer * Color transparency keying * Composition with flexible window position and size versus output display * Blending with flexible layer order and alpha value (per pixel or constant) * Background underlying color * Gamma with non-linear configurable table * Dithering for output with less bits per component (pseudo-random on 2 bits) * Polarity inversion for HSync, VSync, and DataEnable outputs * Output as RGB888 24 bpp or YUV422 16 bpp * Secure layer (using Layer2) capability, with grouped regs and additional interrupt set * Interrupts based on 7 different events * AXI master interface with long efficient bursts (64 or 128 bytes) Signed-off-by: Raphael Gallais-Pou Signed-off-by: Yannick Fertre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135.dtsi b/arch/arm/boot/dts/st/stm32mp135.dtsi index 68d32f9f5314..834a4d545fe4 100644 --- a/arch/arm/boot/dts/st/stm32mp135.dtsi +++ b/arch/arm/boot/dts/st/stm32mp135.dtsi @@ -19,5 +19,16 @@ port { }; }; + + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&scmi_reset RST_SCMI_LTDC>; + status = "disabled"; + }; }; }; From 9547d383102bcfa38556ab236e3a27797bfd424b Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 23 Feb 2024 13:36:49 +0100 Subject: [PATCH 739/969] ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family Adds LTDC pinctrl support and assigns dedicated GPIO pins. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 57 +++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 27e0c3826789..32c5d8a1e06a 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -47,6 +47,63 @@ }; }; + ltdc_pins_a: ltdc-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + mcp23017_pins_a: mcp23017-0 { pins { pinmux = ; From da5216c68b5814ee5a473c306f1bc5564985cf2e Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 23 Feb 2024 13:36:50 +0100 Subject: [PATCH 740/969] ARM: dts: stm32: enable display support on stm32mp135f-dk board Link panel and display controller. Enable panel, backlight and display controller. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 52171214a308..567e53ad285f 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -66,6 +66,46 @@ default-state = "off"; }; }; + + panel_backlight: panel-backlight { + compatible = "gpio-backlight"; + gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + + panel_rgb: panel-rgb { + compatible = "rocktech,rk043fn48h"; + enable-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + backlight = <&panel_backlight>; + power-supply = <&scmi_v3v3_sw>; + status = "okay"; + + width-mm = <105>; + height-mm = <67>; + + panel-timing { + clock-frequency = <10000000>; + hactive = <480>; + hback-porch = <43>; + hfront-porch = <10>; + hsync-len = <1>; + hsync-active = <0>; + vactive = <272>; + vback-porch = <26>; + vfront-porch = <4>; + vsync-len = <10>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; }; &adc_1 { @@ -168,6 +208,19 @@ status = "okay"; }; +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_a>; + pinctrl-1 = <<dc_sleep_pins_a>; + status = "okay"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + &rtc { status = "okay"; }; From 948a4db95dc8c86e70357c20fe2aede7fab69219 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Thu, 11 Apr 2024 11:24:53 +0200 Subject: [PATCH 741/969] arm64: dts: st: add rcc support for STM32MP25 Add RCC support to manage clocks and resets on the STM32MP25. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 144 ++++++++++++++++++------- arch/arm64/boot/dts/st/stm32mp255.dtsi | 4 +- 2 files changed, 110 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index af1444bf9442..193808919e83 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -3,7 +3,9 @@ * Copyright (C) STMicroelectronics 2023 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ +#include #include +#include / { #address-cells = <2>; @@ -35,34 +37,16 @@ }; clocks { - ck_flexgen_08: ck-flexgen-08 { + clk_dsi_txbyte: txbyteclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <100000000>; + clock-frequency = <0>; }; - ck_flexgen_51: ck-flexgen-51 { + clk_rcbsec: clk-rcbsec { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_ls_mcu: ck-icn-ls-mcu { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_p_vdec: ck-icn-p-vdec { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - - ck_icn_p_venc: ck-icn-p-venc { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; + clock-frequency = <64000000>; }; }; @@ -135,7 +119,7 @@ compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; interrupts = ; - clocks = <&ck_flexgen_08>; + clocks = <&rcc CK_KER_USART2>; access-controllers = <&rifsc 32>; status = "disabled"; }; @@ -145,8 +129,9 @@ arm,primecell-periphid = <0x00353180>; reg = <0x48220000 0x400>, <0x44230400 0x8>; interrupts = ; - clocks = <&ck_flexgen_51>; + clocks = <&rcc CK_KER_SDMMC1 >; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; @@ -171,6 +156,93 @@ }; }; + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; @@ -189,7 +261,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; st,bank-name = "GPIOA"; status = "disabled"; }; @@ -200,7 +272,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x10000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; st,bank-name = "GPIOB"; status = "disabled"; }; @@ -211,7 +283,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x20000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; st,bank-name = "GPIOC"; status = "disabled"; }; @@ -222,7 +294,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x30000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; st,bank-name = "GPIOD"; status = "disabled"; }; @@ -233,7 +305,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x40000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; st,bank-name = "GPIOE"; status = "disabled"; }; @@ -244,7 +316,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x50000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; st,bank-name = "GPIOF"; status = "disabled"; }; @@ -255,7 +327,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x60000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; st,bank-name = "GPIOG"; status = "disabled"; }; @@ -266,7 +338,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x70000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; st,bank-name = "GPIOH"; status = "disabled"; }; @@ -277,7 +349,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x80000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; st,bank-name = "GPIOI"; status = "disabled"; }; @@ -288,7 +360,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x90000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; st,bank-name = "GPIOJ"; status = "disabled"; }; @@ -299,7 +371,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0xa0000 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; st,bank-name = "GPIOK"; status = "disabled"; }; @@ -318,7 +390,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&ck_icn_ls_mcu>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 570c5dd0b2c3..f689b47c5010 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -10,7 +10,7 @@ compatible = "st,stm32mp25-vdec"; reg = <0x480d0000 0x3c8>; interrupts = ; - clocks = <&ck_icn_p_vdec>; + clocks = <&rcc CK_BUS_VDEC>; access-controllers = <&rifsc 89>; }; @@ -19,7 +19,7 @@ compatible = "st,stm32mp25-venc"; reg = <0x480e0000 0x800>; interrupts = ; - clocks = <&ck_icn_ls_mcu>; + clocks = <&rcc CK_BUS_VENC>; access-controllers = <&rifsc 90>; }; }; \ No newline at end of file From 9fd205d487989a58028ea1089c16bba589b17cfb Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 15 Dec 2023 18:06:11 +0100 Subject: [PATCH 742/969] arm64: dts: st: add all 8 i2c nodes on stm32mp251 Add the 8 nodes for all i2c instances available on the stm32mp251. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 104 +++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 193808919e83..b55839bc2bfc 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -124,6 +124,110 @@ status = "disabled"; }; + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c3: i2c@40140000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40140000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C3>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 43>; + status = "disabled"; + }; + + i2c4: i2c@40150000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40150000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C4>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 44>; + status = "disabled"; + }; + + i2c5: i2c@40160000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40160000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C5>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 45>; + status = "disabled"; + }; + + i2c6: i2c@40170000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40170000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C6>; + resets = <&rcc I2C6_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 46>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 48>; + status = "disabled"; + }; + sdmmc1: mmc@48220000 { compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00353180>; From a3d208bf04c45ea64b1fd72fd643bb83745d7883 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 15 Dec 2023 18:06:12 +0100 Subject: [PATCH 743/969] arm64: dts: st: add i2c2/i2c8 pins for stm32mp25 Add the i2c2 and i2c8 pins used on STM32MP257F-EV1 board. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 66791a974f8f..4194807606ce 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,23 @@ #include &pinctrl { + i2c2_pins_a: i2c2-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_a: i2c2-sleep-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -90,3 +107,22 @@ }; }; }; + +&pinctrl_z { + i2c8_pins_a: i2c8-0 { + pins { + pinmux = , /* I2C8_SCL */ + ; /* I2C8_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c8_sleep_pins_a: i2c8-sleep-0 { + pins { + pinmux = , /* I2C8_SCL */ + ; /* I2C8_SDA */ + }; + }; +}; From 004434bccfcb29e218044d96d8fe6ce8e9077796 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 15 Dec 2023 18:06:13 +0100 Subject: [PATCH 744/969] arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1 Add properties for i2c2 and i2c8 available on the stm32mp257f-ev1. i2c2 is enabled since several devices are attached to it while i2c8 is kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index b2d3afb15758..0ea8e69bfb3d 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -55,6 +55,26 @@ status = "okay"; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <13>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <57>; + i2c-scl-falling-time-ns = <7>; + clock-frequency = <400000>; + status = "disabled"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; From f08b42c11955653c48cfcc7886a15166bea8be46 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 25 Apr 2024 10:10:50 +0200 Subject: [PATCH 745/969] arm64: dts: st: add all 8 spi nodes on stm32mp251 Add the 8 nodes for all spi instances available on the stm32mp251. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 96 ++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index b55839bc2bfc..64240f94d05d 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -115,6 +115,30 @@ #access-controller-cells = <1>; ranges; + spi2: spi@400b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + usart2: serial@400e0000 { compatible = "st,stm32h7-uart"; reg = <0x400e0000 0x400>; @@ -215,6 +239,78 @@ status = "disabled"; }; + spi1: spi@40230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + spi6: spi@40350000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40350000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI6>; + resets = <&rcc SPI6_R>; + access-controllers = <&rifsc 27>; + status = "disabled"; + }; + + spi7: spi@40360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x40360000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI7>; + resets = <&rcc SPI7_R>; + access-controllers = <&rifsc 28>; + status = "disabled"; + }; + + spi8: spi@46020000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + i2c8: i2c@46040000 { compatible = "st,stm32mp25-i2c"; reg = <0x46040000 0x400>; From 1d1d4072138d193b3923f9e4c9181650a60c87ac Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 18 Dec 2023 16:57:17 +0100 Subject: [PATCH 746/969] arm64: dts: st: add spi3/spi8 pins for stm32mp25 Add the spi3 and spi8 pins used on STM32MP257F-EV1 board. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 4194807606ce..7a82896dcbf6 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -77,6 +77,28 @@ }; }; + spi3_pins_a: spi3-0 { + pins1 { + pinmux = , /* SPI3_SCK */ + ; /* SPI3_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins1 { + pinmux = , /* SPI3_SCK */ + , /* SPI3_MOSI */ + ; /* SPI3_MISO */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = ; /* USART2_TX */ @@ -126,3 +148,27 @@ }; }; }; + +&pinctrl_z { + spi8_pins_a: spi8-0 { + pins1 { + pinmux = , /* SPI8_SCK */ + ; /* SPI8_MOSI */ + drive-push-pull; + bias-disable; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI8_MISO */ + bias-disable; + }; + }; + + spi8_sleep_pins_a: spi8-sleep-0 { + pins1 { + pinmux = , /* SPI8_SCK */ + , /* SPI8_MOSI */ + ; /* SPI8_MISO */ + }; + }; +}; From bc99659688ba39def8fd43758e9ea88a3c3c9817 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 18 Dec 2023 16:57:18 +0100 Subject: [PATCH 747/969] arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1 Add properties for spi3 and spi8 available on the stm32mp257f-ev1. Both are kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 0ea8e69bfb3d..27b7360e5dba 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -88,6 +88,20 @@ status = "okay"; }; +&spi3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + status = "disabled"; +}; + +&spi8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi8_pins_a>; + pinctrl-1 = <&spi8_sleep_pins_a>; + status = "disabled"; +}; + &usart2 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart2_pins_a>; From 36cf0d86d760f30b59bc61ffc72c58503c353a17 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 24 Apr 2024 18:53:44 +0200 Subject: [PATCH 748/969] arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25 Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP251 is a single core Cortex A35, STM32MP253 is a dual core CA35. Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++---- arch/arm64/boot/dts/st/stm32mp253.dtsi | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 64240f94d05d..4b48e4ed2d28 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -93,10 +93,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&intc>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; always-on; }; diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index af48e82efe8a..029f88981961 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -20,4 +20,11 @@ ; interrupt-affinity = <&cpu0>, <&cpu1>; }; + + timer { + interrupts = , + , + , + ; + }; }; From 5bc23521d617b4ac8f66d1614e7c8eb79da9cd5a Mon Sep 17 00:00:00 2001 From: "Bilbao, Carlos" Date: Wed, 24 Apr 2024 14:59:19 -0500 Subject: [PATCH 749/969] docs/MAINTAINERS: Update my email address In the near future, I will not have access to the email address I used as maintainer of a number of things, mostly in the documentation. Update that address to my personal email address (see Link) so I can continue contributing and update .mailmap. Link: https://lore.kernel.org/all/BL1PR12MB58749FF2BFEDB817DE1FE6CBF82A2@BL1PR12MB5874.namprd12.prod.outlook.com/ Signed-off-by: Carlos Bilbao Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/139b8cab-009c-4688-be41-c4c526532ea1@amd.com --- .mailmap | 1 + Documentation/security/snp-tdx-threat-model.rst | 2 +- Documentation/translations/sp_SP/index.rst | 2 +- Documentation/translations/sp_SP/memory-barriers.txt | 4 ++-- .../translations/sp_SP/process/code-of-conduct.rst | 2 +- Documentation/translations/sp_SP/process/coding-style.rst | 2 +- .../translations/sp_SP/process/email-clients.rst | 2 +- Documentation/translations/sp_SP/process/howto.rst | 2 +- Documentation/translations/sp_SP/process/kernel-docs.rst | 2 +- .../sp_SP/process/kernel-enforcement-statement.rst | 2 +- Documentation/translations/sp_SP/process/magic-number.rst | 2 +- .../translations/sp_SP/process/programming-language.rst | 2 +- .../translations/sp_SP/process/submitting-patches.rst | 2 +- MAINTAINERS | 8 ++++---- 14 files changed, 18 insertions(+), 17 deletions(-) diff --git a/.mailmap b/.mailmap index 2216b5d5c84e..7e2dd6060544 100644 --- a/.mailmap +++ b/.mailmap @@ -113,6 +113,7 @@ Brian Silverman Cai Huoqing Can Guo Carl Huang +Carlos Bilbao Changbin Du Changbin Du Chao Yu diff --git a/Documentation/security/snp-tdx-threat-model.rst b/Documentation/security/snp-tdx-threat-model.rst index ec66f2ed80c9..3a2d41d2e645 100644 --- a/Documentation/security/snp-tdx-threat-model.rst +++ b/Documentation/security/snp-tdx-threat-model.rst @@ -4,7 +4,7 @@ Confidential Computing in Linux for x86 virtualization .. contents:: :local: -By: Elena Reshetova and Carlos Bilbao +By: Elena Reshetova and Carlos Bilbao Motivation ========== diff --git a/Documentation/translations/sp_SP/index.rst b/Documentation/translations/sp_SP/index.rst index c543b495c042..274ef4ad96b9 100644 --- a/Documentation/translations/sp_SP/index.rst +++ b/Documentation/translations/sp_SP/index.rst @@ -7,7 +7,7 @@ Traducción al español \kerneldocCJKoff -:maintainer: Carlos Bilbao +:maintainer: Carlos Bilbao .. _sp_disclaimer: diff --git a/Documentation/translations/sp_SP/memory-barriers.txt b/Documentation/translations/sp_SP/memory-barriers.txt index 27097a808c88..153e57130775 100644 --- a/Documentation/translations/sp_SP/memory-barriers.txt +++ b/Documentation/translations/sp_SP/memory-barriers.txt @@ -1,6 +1,6 @@ NOTE: This is a version of Documentation/memory-barriers.txt translated into -Spanish by Carlos Bilbao . If you find any +Spanish by Carlos Bilbao . If you find any difference between this document and the original file or a problem with the translation, please contact the maintainer of this file. Please also note that the purpose of this file is to be easier to read for non English @@ -18,7 +18,7 @@ Documento original: David Howells Will Deacon Peter Zijlstra -Traducido por: Carlos Bilbao +Traducido por: Carlos Bilbao Nota: Si tiene alguna duda sobre la exactitud del contenido de esta traducción, la única referencia válida es la documentación oficial en inglés. diff --git a/Documentation/translations/sp_SP/process/code-of-conduct.rst b/Documentation/translations/sp_SP/process/code-of-conduct.rst index adc6c770cc37..a6c08613aefc 100644 --- a/Documentation/translations/sp_SP/process/code-of-conduct.rst +++ b/Documentation/translations/sp_SP/process/code-of-conduct.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/code-of-conduct.rst ` -:Translator: Contributor Covenant and Carlos Bilbao +:Translator: Contributor Covenant and Carlos Bilbao .. _sp_code_of_conduct: diff --git a/Documentation/translations/sp_SP/process/coding-style.rst b/Documentation/translations/sp_SP/process/coding-style.rst index a37274764371..b5a84df44cea 100644 --- a/Documentation/translations/sp_SP/process/coding-style.rst +++ b/Documentation/translations/sp_SP/process/coding-style.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/coding-style.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_codingstyle: diff --git a/Documentation/translations/sp_SP/process/email-clients.rst b/Documentation/translations/sp_SP/process/email-clients.rst index fdf1e51b84e4..55d5803daf41 100644 --- a/Documentation/translations/sp_SP/process/email-clients.rst +++ b/Documentation/translations/sp_SP/process/email-clients.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/email-clients.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_email_clients: diff --git a/Documentation/translations/sp_SP/process/howto.rst b/Documentation/translations/sp_SP/process/howto.rst index dd793c0f8574..72ea855ac9dc 100644 --- a/Documentation/translations/sp_SP/process/howto.rst +++ b/Documentation/translations/sp_SP/process/howto.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/howto.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_process_howto: diff --git a/Documentation/translations/sp_SP/process/kernel-docs.rst b/Documentation/translations/sp_SP/process/kernel-docs.rst index 2f9b3df8f8fa..a62c6854f59b 100644 --- a/Documentation/translations/sp_SP/process/kernel-docs.rst +++ b/Documentation/translations/sp_SP/process/kernel-docs.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/kernel-docs.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_kernel_docs: diff --git a/Documentation/translations/sp_SP/process/kernel-enforcement-statement.rst b/Documentation/translations/sp_SP/process/kernel-enforcement-statement.rst index d66902694089..d47a1c154610 100644 --- a/Documentation/translations/sp_SP/process/kernel-enforcement-statement.rst +++ b/Documentation/translations/sp_SP/process/kernel-enforcement-statement.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/kernel-enforcement-statement.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_process_statement_kernel: diff --git a/Documentation/translations/sp_SP/process/magic-number.rst b/Documentation/translations/sp_SP/process/magic-number.rst index 7c7dfb4ba80b..32a99aac2f6c 100644 --- a/Documentation/translations/sp_SP/process/magic-number.rst +++ b/Documentation/translations/sp_SP/process/magic-number.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/magic-number.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_magicnumbers: diff --git a/Documentation/translations/sp_SP/process/programming-language.rst b/Documentation/translations/sp_SP/process/programming-language.rst index 301f525372d8..ba2164057f45 100644 --- a/Documentation/translations/sp_SP/process/programming-language.rst +++ b/Documentation/translations/sp_SP/process/programming-language.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/programming-language.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_programming_language: diff --git a/Documentation/translations/sp_SP/process/submitting-patches.rst b/Documentation/translations/sp_SP/process/submitting-patches.rst index 3b35566db736..328ec80bd61d 100644 --- a/Documentation/translations/sp_SP/process/submitting-patches.rst +++ b/Documentation/translations/sp_SP/process/submitting-patches.rst @@ -1,7 +1,7 @@ .. include:: ../disclaimer-sp.rst :Original: :ref:`Documentation/process/submitting-patches.rst ` -:Translator: Carlos Bilbao +:Translator: Carlos Bilbao .. _sp_submittingpatches: diff --git a/MAINTAINERS b/MAINTAINERS index 701e02ef30d4..c51453144ee8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -993,7 +993,7 @@ F: drivers/video/fbdev/geode/ AMD HSMP DRIVER M: Naveen Krishna Chatradhi -R: Carlos Bilbao +R: Carlos Bilbao L: platform-driver-x86@vger.kernel.org S: Maintained F: Documentation/arch/x86/amd_hsmp.rst @@ -5355,7 +5355,7 @@ F: drivers/usb/atm/cxacru.c CONFIDENTIAL COMPUTING THREAT MODEL FOR X86 VIRTUALIZATION (SNP/TDX) M: Elena Reshetova -M: Carlos Bilbao +M: Carlos Bilbao S: Maintained F: Documentation/security/snp-tdx-threat-model.rst @@ -10607,7 +10607,7 @@ S: Orphan F: drivers/video/fbdev/imsttfb.c INDEX OF FURTHER KERNEL DOCUMENTATION -M: Carlos Bilbao +M: Carlos Bilbao S: Maintained F: Documentation/process/kernel-docs.rst @@ -20660,7 +20660,7 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/dvb-frontends/sp2* SPANISH DOCUMENTATION -M: Carlos Bilbao +M: Carlos Bilbao R: Avadhut Naik S: Maintained F: Documentation/translations/sp_SP/ From e171c7cef29409411b708c5752c16512266f48b4 Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Mon, 22 Apr 2024 12:11:00 +0800 Subject: [PATCH 750/969] docs/zh_CN: add process/cve Chinese translation Translate process/cve.rst into Chinese and add it to Documentation/translations/zh_CN directory. Signed-off-by: Dongliang Mu Reviewed-by: Alex Shi Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240422041115.2439166-1-dzm91@hust.edu.cn --- .../translations/zh_CN/process/cve.rst | 89 +++++++++++++++++++ .../translations/zh_CN/process/index.rst | 1 + 2 files changed, 90 insertions(+) create mode 100644 Documentation/translations/zh_CN/process/cve.rst diff --git a/Documentation/translations/zh_CN/process/cve.rst b/Documentation/translations/zh_CN/process/cve.rst new file mode 100644 index 000000000000..e39b796efcec --- /dev/null +++ b/Documentation/translations/zh_CN/process/cve.rst @@ -0,0 +1,89 @@ +.. include:: ../disclaimer-zh_CN.rst + +:Original: Documentation/process/cve.rst +:Translator: Dongliang Mu + +==== +CVEs +==== + +Common Vulnerabilities and Exposure (CVE®) 编号是一种明确的方式来 +识别、定义和登记公开披露的安全漏洞。随着时间的推移，它们在内核项目中的实用性 +已经下降，CVE编号经常以不适当的方式和不适当的原因被分配。因此，内核开发社区 +倾向于避免使用它们。然而，分配CVE与其他形式的安全标识符的持续压力，以及内核 +社区之外的个人和公司的持续滥用，已经清楚地表明内核社区应该控制这些CVE分配。 + +Linux内核开发团队确实有能力为潜在的Linux内核安全问题分配CVE。CVE的分配 +独立于 :doc:`安全漏洞报送流程`。 + +所有分配给Linux内核的CVE列表都可以在linux-cve邮件列表的存档中找到，如 +https://lore.kernel.org/linux-cve-announce/ 所示。如果想获得已分配 +CVE的通知，请“订阅”该邮件列表。要获得分配的CVE通知，请订阅该邮件列表： +`订阅 `_。 + +过程 +======= + +作为正常稳定发布过程的一部分，可能存在安全问题的内核更改由负责CVE编号分配 +的开发人员识别，并自动为其分配CVE编号。这些CVE分配会作为经常性的通告经常 +发布在linux-cve-announce邮件列表上。 + +注意，由于Linux内核在系统中的特殊地位，几乎任何漏洞都可能被利用来危害内核 +的安全性，但是当漏洞被修复后，利用的可能性通常不明显。因此，CVE分配团队过于 +谨慎，并将CVE编号分配给他们识别的任何漏洞修复。这就解释了为什么Linux内核 +团队会发布大量的CVE。 + +如果CVE分配团队错过了任何用户认为应该分配CVE的特定修复，请发送电子邮件到 +，那里的团队将与您一起工作。请注意，任何潜在的安全问题 +不应被发送到此邮箱，它仅用于为已发布的内核树中的漏洞修复分配CVE。如果你觉得 +自己发现了一个未修复的安全问题，请按照 :doc:`安全漏洞报送流程 +` 发送到Linux内核社区。 + +Linux内核不会给未修复的安全问题自动分配CVE；只有在安全修复可用且应用于 +稳定内核树后，CVE分配才会自动发生，并且它将通过安全修复的Git提交编号进行 +跟踪。如果有人希望在提交安全修复之前分配CVE，请联系内核CVE分配团队，从 +他们的一批保留编号中获得相应的CVE编号。 + +对于目前没有得到稳定与长期维护内核团队积极支持的内核版本中发现的任何问题， +都不会分配CVEs。当前支持的内核分支列表可以在 https://kernel.org/releases.html +上找到。 + +被分配CVE的争论 +========================= + +对于为特定内核修改分配的CVE，其争论或修改的权限仅属于受影响子系统的维护者。 +这一原则确保了漏洞报告的高度准确性和可问责性。只有那些具有深厚专业知识和 +对子系统深入了解的维护人员，才能有效评估内核漏洞的有效性和范围，并确定其适当的 +CVE指定策略。在此指定权限之外，任何争论或修改CVE的尝试都可能导致混乱、 +不准确的报告，并最终危及系统。 + +无效的CVE +============ + +如果发现的安全问题存在于仅由某Linux发行版支持的Linux内核中，即安全问题是 +由于Linux发行版所做的更改导致，或者Linux的发行版内核版本不再是Linux内核 +社区支持的内核版本，那么Linux内核CVE团队将不能分配CVE，必须从Linux +发行版本身请求。 + +内核CVE分配团队以外的任何团队对Linux内核支持版本分配的CVE都不应被 +视为有效CVE。请通知内核CVE分配团队，以便他们可以通过CNA修复措施使 +这些条目失效。 + +特定CVE的适用性 +============================== + +由于Linux内核可以以许多不同方式使用，外部用户可以通过许多不同方式访问它，或者 +根本没有访问，因此任何特定CVE的适用性取决于Linux用户，而不是内核CVE分配团队。 +请不要与我们联系来尝试确定任何特定CVE的适用性。 + +此外，由于源代码树非常大，而任何一个系统都只使用源代码树的一小部分，因此任何 +Linux用户都应该意识到，大量分配的CVEs与他们的系统无关。 + +简而言之，我们不知道您的用例，也不知道您使用的是内核的哪个部分，因此我们无法 +确定特定的CVE是否与您的系统相关。 + +与往常一样，最好采用所有发布的内核更改，因为它们是由许多社区成员在一个统一的 +整体中一起进行测试的，而不是作为个别的精选更改。还要注意，对于许多安全问题来 +说，整体问题的解决方案并不是在单个更改中找到的，而是在彼此之上的许多修复的总 +和。理想情况下，CVE将被分配给所有问题的所有修复，但有时我们将无法注意到一些 +修复，因此某些修复可能在没有CVE的情况下被采取。 diff --git a/Documentation/translations/zh_CN/process/index.rst b/Documentation/translations/zh_CN/process/index.rst index 3ca02d281be0..5c6c8ccdd50d 100644 --- a/Documentation/translations/zh_CN/process/index.rst +++ b/Documentation/translations/zh_CN/process/index.rst @@ -48,6 +48,7 @@ TODOLIST: :maxdepth: 1 embargoed-hardware-issues + cve TODOLIST: From 3394cc0e38cb9be7367a8ebb4448dda5aa9d8250 Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Thu, 22 Feb 2024 21:21:42 +0100 Subject: [PATCH 751/969] ARM: tegra: paz00: Add emc-tables for ram-code 1 The same table as ram-code 0 operates correctly on ram-code 1 v2: rebase on current kernel Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra20-paz00.dts | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts index afb922bd79a7..1408e1e00759 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts @@ -533,6 +533,49 @@ 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; + + emc-tables@1 { + nvidia,ram-code = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000016 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000a 0x000000c8 + 0x00000003 0x00000006 0x00000004 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe03b0323 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; }; usb@c5000000 { From 4d4d3fe6b3cc2a0b2a334a08bb9c64ba1dcbbea4 Mon Sep 17 00:00:00 2001 From: Akhil R Date: Wed, 3 Apr 2024 15:30:38 +0530 Subject: [PATCH 752/969] arm64: defconfig: Enable Tegra Security Engine Enable Tegra Security Engine which can accelerate various AES and HASH algorithms on supported hardware. Signed-off-by: Akhil R Signed-off-by: Thierry Reding --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..af6f247c497c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1647,6 +1647,7 @@ CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m CONFIG_CRYPTO_DEV_QCE=m CONFIG_CRYPTO_DEV_QCOM_RNG=m +CONFIG_CRYPTO_DEV_TEGRA=m CONFIG_CRYPTO_DEV_CCREE=m CONFIG_CRYPTO_DEV_HISI_SEC2=m CONFIG_CRYPTO_DEV_HISI_ZIP=m From de024f63cea3ec833bc8a55be2753879e2750db9 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 3 Apr 2024 12:42:08 +0100 Subject: [PATCH 753/969] soc/tegra: pmc: Add EQOS wake event for Tegra194 and Tegra234 Add the wake event for the EQOS ethernet controller on Tegra194 and Tegra234 devices, so that system can be woken up by an event from this ethernet controller. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index d6bfcea5ee65..91d0ad6ddefc 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4074,6 +4074,7 @@ static const char * const tegra194_reset_sources[] = { }; static const struct tegra_wake_event tegra194_wake_events[] = { + TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)), TEGRA_WAKE_IRQ("pmu", 24, 209), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)), TEGRA_WAKE_IRQ("rtc", 73, 10), @@ -4210,6 +4211,7 @@ static const char * const tegra234_reset_sources[] = { static const struct tegra_wake_event tegra234_wake_events[] = { TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)), + TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)), TEGRA_WAKE_IRQ("pmu", 24, 209), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), From 22b92b28fcf4f7748279c4071c63e53fecfacc2d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 20 Apr 2023 14:12:33 +0200 Subject: [PATCH 754/969] dt-bindings: display: tegra: Allow dma-coherent on Tegra194 and later Tegra194 and later chips have a coherency fabric, so some devices can be marked as DMA coherent to avoid unnecessary cache maintenance. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 94c5242c03b2..3563378a01af 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -177,6 +177,15 @@ allOf: required: - reg-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-host1x + then: + properties: + dma-coherent: true - if: properties: compatible: @@ -226,6 +235,8 @@ allOf: use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to usable stream IDs. + dma-coherent: true + required: - reg-names From ff4d7e172100e2c35c92ce96881c3777ac566528 Mon Sep 17 00:00:00 2001 From: Mohammad Shehar Yaar Tausif Date: Tue, 23 Apr 2024 17:36:29 +0530 Subject: [PATCH 755/969] ARM: tegra: tegra20-ac97: Replace deprecated "gpio" suffix Replace "gpio" suffix with "gpios" for tegra20-ac97 DTS as the "gpio" suffix is deprecated. Signed-off-by: Mohammad Shehar Yaar Tausif Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi index 8c1d5c9fa483..2ff7be8f1382 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi @@ -445,9 +445,9 @@ tegra_ac97: ac97@70002000 { status = "okay"; - nvidia,codec-reset-gpio = + nvidia,codec-reset-gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - nvidia,codec-sync-gpio = + nvidia,codec-sync-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; }; From fd46e5e136a83f61c1746d5a08686c0c4f4c0706 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 18 Apr 2024 13:16:15 -0500 Subject: [PATCH 756/969] arm64: dts: allwinner: h616: Add NMI device node Add device node for the H616 Non Maskable Interrupt (NMI) controller. This controller is present on all H616 boards and derivatives such as the T507 and H700. Note that on the H616 no NMI pad is exposed. Reviewed-by: Andre Przywara Signed-off-by: Chris Morgan Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240418181615.1370179-3-macroalpha82@gmail.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index a061b69c07c2..f8ecd7db4868 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -775,6 +775,15 @@ #reset-cells = <1>; }; + nmi_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun50i-h616-nmi", + "allwinner,sun9i-a80-nmi"; + reg = <0x07010320 0xc>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h616-r-pinctrl"; reg = <0x07022000 0x400>; From 2633c58e1354d7de2c8e7be8bdb6f68a0a01bad7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 16:08:54 +0200 Subject: [PATCH 757/969] arm64: tegra: Correct Tegra132 I2C alias There is no such device as "as3722@40", because its name is "pmic". Use phandles for aliases to fix relying on full node path. This corrects aliases for RTC devices and also fixes dtc W=1 warning: tegra132-norrin.dts:12.3-36: Warning (alias_paths): /aliases:rtc0: aliases property is not a valid node (/i2c@7000d000/as3722@40) Fixes: 0f279ebdf3ce ("arm64: tegra: Add NVIDIA Tegra132 Norrin support") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 4 ++-- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 14d58859bb55..683ac124523b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -9,8 +9,8 @@ compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@7000d000/as3722@40"; - rtc1 = "/rtc@7000e000"; + rtc0 = &as3722; + rtc1 = &tegra_rtc; serial0 = &uarta; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 7e24a212c7e4..5bcccfef3f7f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -572,7 +572,7 @@ status = "disabled"; }; - rtc@7000e000 { + tegra_rtc: rtc@7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; interrupts = ; From 0d23cacb2ae0fc9d8d40f36cb37ad272b3249ffe Mon Sep 17 00:00:00 2001 From: Akhil R Date: Wed, 3 Apr 2024 15:30:39 +0530 Subject: [PATCH 758/969] arm64: tegra: Add Tegra Security Engine DT nodes Add device tree nodes for Tegra AES and HASH engines. Signed-off-by: Akhil R Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 78cbfdd98dd1..f2e2d8d6845b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4406,6 +4406,22 @@ */ status = "disabled"; }; + + crypto@15820000 { + compatible = "nvidia,tegra234-se-aes"; + reg = <0x00 0x15820000 0x00 0x10000>; + clocks = <&bpmp TEGRA234_CLK_SE>; + iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>; + dma-coherent; + }; + + crypto@15840000 { + compatible = "nvidia,tegra234-se-hash"; + reg = <0x00 0x15840000 0x00 0x10000>; + clocks = <&bpmp TEGRA234_CLK_SE>; + iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>; + dma-coherent; + }; }; pcie@140a0000 { From a3592fae4d6674bf88834ad7fbba20678f20bdac Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 23 Apr 2024 12:14:55 -0700 Subject: [PATCH 759/969] arm: dts: bcm2711: Describe Ethernet LEDs Describe the Ethernet LEDs for the Raspberry Pi 4 model B board as well as the Raspberry Pi 4 CM board. The Raspberry Pi 400 board does not include RJ45 connector LEDs so the 'leds' node is deleted accordingly. The Ethernet PHY LEDs are numbered in the PHY package/pin list from LED1 through LED4, however their address within the LED registers function selector is 0-indexed. Link: https://lore.kernel.org/r/20240423191500.1443636-1-florian.fainelli@broadcom.com Signed-off-by: Florian Fainelli Reviewed-by: Stefan Wahren --- .../arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 22 +++++++++++++++++ .../arm/boot/dts/broadcom/bcm2711-rpi-400.dts | 1 + .../boot/dts/broadcom/bcm2711-rpi-cm4-io.dts | 24 +++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts index cfc8cb5e10ba..353bb50ce542 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -5,6 +5,7 @@ #include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-peripheral.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" +#include / { compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; @@ -204,6 +205,27 @@ phy1: ethernet-phy@1 { /* No PHY interrupt */ reg = <0x1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* LED1 */ + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* LED2 */ + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts index 5a2869a18bd5..ca9be91b4f36 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts @@ -30,6 +30,7 @@ &genet_mdio { clock-frequency = <1950000>; + /delete-node/ leds; }; &led_pwr { diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts index 7c6a5bdf48aa..6bc77dd48c0d 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4-io.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include #include "bcm2711-rpi-cm4.dtsi" #include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -110,6 +111,29 @@ }; }; +&phy1 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* LED2 */ + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* LED3 */ + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; +}; + &led_act { gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; }; From 6bc6bf8a940a686c4c11ce3a49427e62e355010c Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Sat, 27 Apr 2024 23:02:24 +1200 Subject: [PATCH 760/969] dt-bindings: arm: sunxi: document Anbernic RG35XX handheld gaming device variants RG35XX 2024: Base version with Allwinner H700 RG35XX Plus: Adds Wifi/BT RG35XX H: Adds second USB port and analog sticks to -Plus in horizontal form factor Use three separate device descriptions rather than enum as per existing sunxi binding style. Signed-off-by: Ryan Walklin Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240427110225.727472-4-ryan@testtoast.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index f465f3a59c80..c6d0d8d81ed4 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -56,6 +56,21 @@ properties: - const: anbernic,rg-nano - const: allwinner,sun8i-v3s + - description: Anbernic RG35XX (2024) + - items: + - const: anbernic,rg35xx-2024 + - const: allwinner,sun50i-h700 + + - description: Anbernic RG35XX Plus + - items: + - const: anbernic,rg35xx-plus + - const: allwinner,sun50i-h700 + + - description: Anbernic RG35XX H + - items: + - const: anbernic,rg35xx-h + - const: allwinner,sun50i-h700 + - description: Amarula A64 Relic items: - const: amarula,a64-relic From 0923a6c604fc68300d9b9f8e1205d9abd3025cf6 Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Sat, 27 Apr 2024 23:02:26 +1200 Subject: [PATCH 761/969] arm64: dts: allwinner: h700: Add RG35XX 2024 DTS The base model RG35XX (2024) is a handheld gaming device based on an Allwinner H700 chip. The H700 is a H616 variant (4x ARM Cortex-A53 cores @ 1.5Ghz with Mali G31 GPU) which exposes RGB LCD and NMI pins. Device features: - Allwinner H700 @ 1.5GHz - 1GB LPDDR4 DRAM - X-Powers AXP717 PMIC - 3.5" 640x480 RGB LCD - Two microSD slots - Mini-HDMI out - GPIO keypad - 3.5mm headphone jack - USB-C charging port Enabled in this DTS: - AXP717 PMIC with RSB serial interface, regulators and NMI interrupt controller - Power LED (charge LED on device controlled directly by PMIC) - Serial UART (accessible from headers on the board) - First SD slot (SD2 appears to have a GPIO-switched regulator for 1.8v low-voltage signalling, this is not yet modeled. Enablement with a switched regulator will be confirmed and posted in a follow-up patch). Signed-off-by: Ryan Walklin Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20240427110225.727472-6-ryan@testtoast.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h700-anbernic-rg35xx-2024.dts | 327 ++++++++++++++++++ 2 files changed, 328 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index c571971f2fac..4da4749f01d2 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -48,3 +48,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts new file mode 100644 index 000000000000..ee30584b6ad7 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin . + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include +#include +#include +#include + +/ { + model = "Anbernic RG35XX 2024"; + chassis-type = "handset"; + compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys_gamepad: gpio-keys-gamepad { + compatible = "gpio-keys"; + + button-a { + label = "Action-Pad A"; + gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ + linux,input-type = ; + linux,code = ; + }; + + button-b { + label = "Action-Pad B"; + gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ + linux,input-type = ; + linux,code = ; + }; + + button-down { + label = "D-Pad Down"; + gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */ + linux,input-type = ; + linux,code = ; + }; + + button-l1 { + label = "Key L1"; + gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */ + linux,input-type = ; + linux,code = ; + }; + + button-l2 { + label = "Key L2"; + gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ + linux,input-type = ; + linux,code = ; + }; + + button-left { + label = "D-Pad left"; + gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + linux,input-type = ; + linux,code = ; + }; + + button-menu { + label = "Key Menu"; + gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ + linux,input-type = ; + linux,code = ; + }; + + button-r1 { + label = "Key R1"; + gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ + linux,input-type = ; + linux,code = ; + }; + + button-r2 { + label = "Key R2"; + gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */ + linux,input-type = ; + linux,code = ; + }; + + button-right { + label = "D-Pad Right"; + gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + linux,input-type = ; + linux,code = ; + }; + + button-select { + label = "Key Select"; + gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ + linux,input-type = ; + linux,code = ; + }; + button-start { + label = "Key Start"; + gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + linux,input-type = ; + linux,code = ; + }; + + button-up { + label = "D-Pad Up"; + gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ + linux,input-type = ; + linux,code = ; + }; + + button-x { + label = "Action-Pad X"; + gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ + linux,input-type = ; + linux,code = ; + }; + + button-y { + label = "Action Pad Y"; + gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */ + linux,input-type = ; + linux,code = ; + }; + }; + + gpio-keys-volume { + compatible = "gpio-keys"; + autorepeat; + + button-vol-up { + label = "Key Volume Up"; + gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */ + linux,input-type = ; + linux,code = ; + }; + + button-vol-down { + label = "Key Volume Down"; + gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */ + linux,input-type = ; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + default-state = "on"; + }; + }; + + reg_vcc5v: regulator-vcc5v { /* USB-C power input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc1>; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + disable-wp; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pa-supply = <®_cldo3>; + vcc-pc-supply = <®_cldo3>; + vcc-pe-supply = <®_cldo3>; + vcc-pf-supply = <®_cldo3>; + vcc-pg-supply = <®_aldo4>; + vcc-ph-supply = <®_cldo3>; + vcc-pi-supply = <®_cldo3>; +}; + +&r_rsb { + status = "okay"; + + axp717: pmic@3a3 { + compatible = "x-powers,axp717"; + reg = <0x3a3>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + + regulators { + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <940000>; + regulator-max-microvolt = <940000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + + reg_aldo1: aldo1 { + /* 1.8v - unused */ + }; + + reg_aldo2: aldo2 { + /* 1.8v - unused */ + }; + + reg_aldo3: aldo3 { + /* 1.8v - unused */ + }; + + reg_aldo4: aldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg"; + }; + + reg_bldo1: bldo1 { + /* 1.8v - unused */ + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll"; + }; + + reg_bldo3: bldo3 { + /* 2.8v - unused */ + }; + + reg_bldo4: bldo4 { + /* 1.2v - unused */ + }; + + reg_cldo1: cldo1 { + /* 3.3v - audio codec - not yet implemented */ + }; + + reg_cldo2: cldo2 { + /* 3.3v - unused */ + }; + + reg_cldo3: cldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_boost: boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5200000>; + regulator-name = "boost"; + }; + + reg_cpusldo: cpusldo { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */ +&usbotg { + dr_mode = "peripheral"; /* USB type-C receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From 398e5fdf60ed2482115732f12c88f199d27afb75 Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Sat, 27 Apr 2024 23:02:27 +1200 Subject: [PATCH 762/969] arm64: dts: allwinner: h700: Add RG35XX-Plus DTS The RG35XX-Plus adds a RTL8221CS SDIO Wifi/BT chip to the RG35XX (2024). Enabled in this DTS: - WiFi - Bluetooth - Supporting power sequence and GPIOs Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240427110225.727472-7-ryan@testtoast.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h700-anbernic-rg35xx-plus.dts | 53 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 4da4749f01d2..2d6b7e6f0b29 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -49,3 +49,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts new file mode 100644 index 000000000000..60a8e4922103 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-plus.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin . + */ + +#include "sun50i-h700-anbernic-rg35xx-2024.dts" + +/ { + model = "Anbernic RG35XX Plus"; + compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700"; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; +}; + +/* SDIO WiFi RTL8821CS */ +&mmc1 { + vmmc-supply = <®_cldo4>; + vqmmc-supply = <®_aldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */ + interrupt-names = "host-wake"; + }; +}; + +/* Bluetooth RTL8821CS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; + device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ + enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */ + host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */ + }; +}; From 0d185df6c9ff841be2460d2f4610de22f326d5dc Mon Sep 17 00:00:00 2001 From: Ryan Walklin Date: Sat, 27 Apr 2024 23:02:28 +1200 Subject: [PATCH 763/969] arm64: dts: allwinner: h700: Add RG35XX-H DTS The RG35XX-H adds thumbsticks, a stereo speaker, and a second USB port to the RG35XX-Plus, and has a horizontal form factor. Enabled in this DTS: - Thumbsticks - Second USB port Signed-off-by: Ryan Walklin Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20240427110225.727472-8-ryan@testtoast.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h700-anbernic-rg35xx-h.dts | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 2d6b7e6f0b29..0db7b60b49a1 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -50,3 +50,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts new file mode 100644 index 000000000000..63036256917f --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin . + * Copyright (C) 2024 Chris Morgan . + */ + +#include "sun50i-h700-anbernic-rg35xx-plus.dts" + +/ { + model = "Anbernic RG35XX H"; + compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; +}; + +&gpio_keys_gamepad { + button-thumbl { + label = "GPIO Thumb Left"; + gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ + linux,input-type = ; + linux,code = ; + }; + + button-thumbr { + label = "GPIO Thumb Right"; + gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */ + linux,input-type = ; + linux,code = ; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; From 4e2511d7f323ad60253e92c80fc87c858fe52567 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:48 +0200 Subject: [PATCH 764/969] ARM: dts: imx51-ts4800: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx51-ts4800.dtb: pwm@73fb4000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index f7408722d68a..2bd0761c7e90 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -45,7 +45,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 78770>; + pwms = <&pwm1 0 78770 0>; brightness-levels = <0 150 200 255>; default-brightness-level = <1>; power-supply = <&backlight_reg>; @@ -113,7 +113,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_backlight>; status = "okay"; From 44f46de2872f70010d9e1831bd0919efeae2ace1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:49 +0200 Subject: [PATCH 765/969] ARM: dts: imx53-m53evk: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx53-m53evk.dtb: pwm@53fb4000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts index c323b4dbe9f0..1353d985969c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts @@ -41,7 +41,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 3000>; + pwms = <&pwm1 0 3000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; power-supply = <®_backlight>; @@ -313,7 +313,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From e10432d3dae57d543feabfb9f2a61b71a8155af7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:50 +0200 Subject: [PATCH 766/969] ARM: dts: imx53-ppd: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx53-ppd.dtb: pwm@53fb4000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx53-ppd.dtb: pwm@53fb8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-ppd.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts index 70c4a4852256..e939acc1c88b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -167,7 +167,7 @@ pwm_bl: backlight { compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; + pwms = <&pwm2 0 50000 0>; brightness-levels = <0 2 5 7 10 12 15 17 20 22 25 28 30 33 35 38 40 43 45 48 51 53 56 58 61 63 66 68 71 73 76 79 81 84 86 89 91 94 96 99 102 104 @@ -187,7 +187,7 @@ led-1 { label = "alarm-brightness"; - pwms = <&pwm1 0 100000>; + pwms = <&pwm1 0 100000 0>; max-brightness = <255>; }; }; @@ -628,14 +628,12 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; From 03438afeaaeb9a3a7350e1f308a2ea4d92a7dbbc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:51 +0200 Subject: [PATCH 767/969] ARM: dts: imx53-kp: Drop redundant settings in pwm nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit imx53-kp.dtsi includes imx53-tqma53.dtsi which already sets #pwm-cells to 2. So the two nodes can be dropped without resulting in any changes in the compiled device tree blobs. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi index 4508f34139a0..8b25416a5303 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi @@ -162,14 +162,6 @@ >; }; -&pwm1 { - #pwm-cells = <2>; -}; - -&pwm2 { - #pwm-cells = <2>; -}; - &uart1 { status = "okay"; }; From ca9692885359c28ff3aeb6402fb83b1c82ae142b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:52 +0200 Subject: [PATCH 768/969] ARM: dts: imx53-tqma: Use #pwm-cells = <3> for imx27-pwm devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dtb: pwm@53fb4000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dtb: pwm@53fb8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dtb: pwm@53fb4000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx53-kp-hsc.dtb: pwm@53fb8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx53-mba53.dtb: pwm@53fb4000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx53-mba53.dtb: pwm@53fb8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx53-mba53.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi | 8 -------- 4 files changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts b/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts index 0e7f071fd10e..f6f116366643 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp-ddc.dts @@ -13,7 +13,7 @@ backlight_lcd: backlight { compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; + pwms = <&pwm2 0 50000 0>; power-supply = <®_backlight>; brightness-levels = <0 24 28 32 36 40 44 48 52 56 diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi index 8b25416a5303..ae5f87b8612d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi @@ -13,7 +13,7 @@ compatible = "pwm-beeper"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_buzzer>; - pwms = <&pwm1 0 500000>; + pwms = <&pwm1 0 500000 0>; }; gpio-buttons { diff --git a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts index 6a37616cef1c..2117de872703 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts @@ -17,7 +17,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; + pwms = <&pwm2 0 50000 0>; brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>; default-brightness-level = <10>; enable-gpios = <&gpio7 7 0>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi index 294811bfc8d2..b2d7271d1d24 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi @@ -202,14 +202,6 @@ }; }; -&pwm1 { - #pwm-cells = <2>; -}; - -&pwm2 { - #pwm-cells = <2>; -}; - &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From 5e1553bacf0ea2336bebfff152d1cf2841ca6b5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:53 +0200 Subject: [PATCH 769/969] ARM: dts: imx6dl-aristainetos_4: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts index cc861a43eb58..a5ac79346854 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts @@ -14,7 +14,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; @@ -79,6 +79,5 @@ }; &pwm1 { - #pwm-cells = <2>; status = "okay"; }; From 28d28f52930635adeda7ae2fa72d7d504b5c6d73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:54 +0200 Subject: [PATCH 770/969] ARM: dts: imx6dl-aristainetos_7: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts index b6cb78870cd5..5a25bdbbeb68 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts @@ -49,7 +49,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 3000>; + pwms = <&pwm3 0 3000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; pinctrl-names = "default"; @@ -69,6 +69,5 @@ }; &pwm3 { - #pwm-cells = <2>; status = "okay"; }; From 60946195eecb73a3968bfeacce3fda7013b33849 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:55 +0200 Subject: [PATCH 771/969] ARM: dts: imx6dl-mamoj: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts index 028951955bde..72ee236d2f5e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-mamoj.dts @@ -21,7 +21,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ + pwms = <&pwm3 0 25000 0>; /* 25000ns -> 40kHz */ brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; default-brightness-level = <7>; }; @@ -303,7 +303,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; From 6adfbf06b18b2273e3d3266b78693b38c4147637 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:56 +0200 Subject: [PATCH 772/969] ARM: dts: imx6q-ba16: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi index f266f1b7e0cf..09d9ca0cb332 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi @@ -55,7 +55,7 @@ compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_display>; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 @@ -349,7 +349,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From fa86e5450c94e67c4050aadccd4c29c6ed9c90a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:57 +0200 Subject: [PATCH 773/969] ARM: dts: imx6q-bosch-acc: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts index 02648806c275..d3f14b4d3b51 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts @@ -36,7 +36,7 @@ backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm1 0 200000>; + pwms = <&pwm1 0 200000 0>; brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; num-interpolated-steps = <10>; default-brightness-level = <60>; @@ -117,14 +117,14 @@ color = ; max-brightness = <248>; default-state = "off"; - pwms = <&pwm2 0 500000>; + pwms = <&pwm2 0 500000 0>; }; led_white: led-1 { color = ; max-brightness = <248>; default-state = "off"; - pwms = <&pwm3 0 500000>; + pwms = <&pwm3 0 500000 0>; linux,default-trigger = "heartbeat"; }; }; @@ -484,28 +484,24 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From ae04d96e49769684d3bfaad5cbbd0682c6ab1be3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:58 +0200 Subject: [PATCH 774/969] ARM: dts: imx6qdl-apf6dev: Use #pwm-cells = <3> for imx27-pwm devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-apf6dev.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-apf6dev.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi index 338d292553ad..3a46ade3b6bd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi @@ -13,7 +13,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 191000>; + pwms = <&pwm3 0 191000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <0>; power-supply = <®_5v>; @@ -212,7 +212,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; From b2d823160a07dd7b8d090477e92cbc3a997d660a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:41:59 +0200 Subject: [PATCH 775/969] ARM: dts: imx6qdl-aristainetos2: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi index db1bc511e71f..758eaf9d93d2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi @@ -46,7 +46,7 @@ / { backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; @@ -346,7 +346,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From a49aee94f6d923d779a9bf33966f2f12022bff45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:00 +0200 Subject: [PATCH 776/969] ARM: dts: imx6qdl-cubox-i: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-emmc-som-v15.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-cubox-i-som-v15.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-emmc-som-v15.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-cubox-i-som-v15.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi index 1e530d892b76..761566ae3cf5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi @@ -64,7 +64,7 @@ active-low; label = "imx6:red:front"; max-brightness = <248>; - pwms = <&pwm1 0 50000>; + pwms = <&pwm1 0 50000 0>; }; }; @@ -233,7 +233,6 @@ }; &pwm1 { - #pwm-cells = <2>; status = "okay"; }; From 795df6eed5b05b47d8de710c38059832142c542f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:01 +0200 Subject: [PATCH 777/969] ARM: dts: imx6qdl-emcon: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi index 42b2ba23aefc..a308a3584b62 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi @@ -66,7 +66,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lvds_bl>; enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; - pwms = <&pwm1 0 50000>; + pwms = <&pwm1 0 50000 0>; brightness-levels = < 0 4 8 16 32 64 80 96 112 128 144 160 176 250 @@ -78,7 +78,7 @@ pwm_fan: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; - pwms = <&pwm4 0 50000>; + pwms = <&pwm4 0 50000 0>; cooling-levels = <0 64 127 191 255>; status = "disabled"; }; @@ -145,7 +145,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgb_bl>; enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; brightness-levels = < 250 176 160 144 128 112 96 80 64 48 32 16 8 1 @@ -736,17 +736,14 @@ }; &pwm1 { - #pwm-cells = <2>; status = "okay"; }; &pwm3 { - #pwm-cells = <2>; status = "okay"; }; &pwm4 { - #pwm-cells = <2>; status = "okay"; }; From 810f7f291feceba9eee460bcb74be7e8b81f9e0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:02 +0200 Subject: [PATCH 778/969] ARM: dts: imx6qdl-gw52xx: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index 535679c27d6f..48ffb3ee01bd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -25,7 +25,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; }; @@ -520,7 +520,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From 03dded49b317b6911d951ec490e07ba13a246166 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:03 +0200 Subject: [PATCH 779/969] ARM: dts: imx6qdl-gw53xx: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index 3e1c572af582..1eae438fbdae 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -25,7 +25,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; }; @@ -517,7 +517,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From db04708c47e641e4da96329b7fff834fe5cc25b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:04 +0200 Subject: [PATCH 780/969] ARM: dts: imx6qdl-gw54xx: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index 0ffa0357a6fa..c2ec8572c8a5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -26,7 +26,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; }; @@ -570,7 +570,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default", "state_dio"; pinctrl-0 = <&pinctrl_pwm4_backlight>; pinctrl-1 = <&pinctrl_pwm4_dio>; From da10a1e80e086a5d9a44c99ba0671d7740e9ed34 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:05 +0200 Subject: [PATCH 781/969] ARM: dts: imx6qdl-gw560x: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw560x.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-gw560x.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi index 46cf4080fec3..7cee983da669 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -66,7 +66,7 @@ backlight-display { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 @@ -619,7 +619,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From e5d394803ea20173718d83e2cc0461deb9c5ba76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:06 +0200 Subject: [PATCH 782/969] ARM: dts: imx6qdl-gw5903: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw5903.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-gw5903.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi index a74cde050158..fbc704c064b6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -56,7 +56,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 @@ -502,7 +502,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From 05d294db0800e905b3cfcdd59f9803269d339103 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:07 +0200 Subject: [PATCH 783/969] ARM: dts: imx6qdl-gw5904: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw5904.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-gw5904.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 1e723807ab4c..070506279186 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -70,7 +70,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; }; @@ -586,7 +586,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From 18b027ae253f0e90f01a43d2a0df7e4014ef0add Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:08 +0200 Subject: [PATCH 784/969] ARM: dts: imx6qdl-icore: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-icore.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-icore-mipi.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-icore.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-icore-mipi.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap10.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-icore-ofcap12.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi index efe11524b885..9975b6ee433d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi @@ -20,7 +20,7 @@ backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm3 0 100000>; + pwms = <&pwm3 0 100000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; }; @@ -245,7 +245,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; From 2e040442c6a98c83540b818561a019aac1fe7934 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:09 +0200 Subject: [PATCH 785/969] ARM: dts: imx6qdl-nit6xlite: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-nit6xlite.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi index f2542d725ce7..a30cf0d06206 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -108,7 +108,7 @@ backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -117,7 +117,7 @@ backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -499,7 +499,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -512,7 +511,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From 98046c4ee4c2ff8133e87c596778a923975d7ae8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:10 +0200 Subject: [PATCH 786/969] ARM: dts: imx6qdl-nitrogen6_max: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_max.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index 32a110a35b02..33174febf410 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -183,7 +183,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -192,7 +192,7 @@ backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -201,7 +201,7 @@ backlight_lvds1: backlight-lvds1 { compatible = "pwm-backlight"; - pwms = <&pwm2 0 5000000>; + pwms = <&pwm2 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -735,14 +735,12 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; @@ -755,7 +753,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From ea9950d81eab9d4de87e12462d1ba533533f5b44 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:11 +0200 Subject: [PATCH 787/969] ARM: dts: imx6qdl-nitrogen6_som2: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_som2.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-nitrogen6_som2.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 414196b75991..8e64314fa8b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -17,7 +17,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -26,7 +26,7 @@ backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -641,7 +641,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -654,7 +653,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From 1d3b165fd4b87289cd20eefad00853823e7376ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:12 +0200 Subject: [PATCH 788/969] ARM: dts: imx6qdl-nitrogen6x: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-nitrogen6x.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6x.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi index f278b14911ce..121177273dd0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -134,7 +134,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -143,7 +143,7 @@ backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -596,7 +596,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; @@ -609,7 +608,6 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From 890a27b1107e8cf042fe11328ae1472586097192 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:13 +0200 Subject: [PATCH 789/969] ARM: dts: imx6qdl-phytec-mira: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-emmc.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-phytec-mira-rdk-nand.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-phytec-mira-rdk-nand.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi index 1ca4d219609f..0b4c09b09c03 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi @@ -15,7 +15,7 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_backlight>; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; status = "okay"; }; @@ -224,7 +224,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From f8039b9dd5e895c4a6e319af06c4bd808797b370 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:14 +0200 Subject: [PATCH 790/969] ARM: dts: imx6qdl-sabreauto: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-sabreauto.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabreauto.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index 51517e27418c..6656e2e762a1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -153,7 +153,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; @@ -802,7 +802,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; From 2a08654ee2a9de9c45ee270575992332edd93ea3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:15 +0200 Subject: [PATCH 791/969] ARM: dts: imx6qdl-sabrelite: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-sabrelite.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabrelite.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi index 84c8a9531e18..9c502bf77d0b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi @@ -99,7 +99,7 @@ #clock-cells = <0>; clock-frequency = <22000000>; clock-output-names = "mipi_pwm3"; - pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */ + pwms = <&pwm3 0 45 0>; /* 1 / 45 ns = 22 MHz */ status = "okay"; }; @@ -162,7 +162,7 @@ backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -171,7 +171,7 @@ backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_3p3v>; @@ -654,21 +654,18 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; From 7ab26773788b6450cfc315c04ae20db60447ce98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:16 +0200 Subject: [PATCH 792/969] ARM: dts: imx6qdl-sabresd: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-sabresd.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-sabresd.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6qp-sabresd.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index 4fe58764b929..8f4f5fba68cc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -119,7 +119,7 @@ backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; status = "okay"; @@ -755,7 +755,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From 06db84c57fa11cde247a8d8a16ffc7ede5a88a1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:17 +0200 Subject: [PATCH 793/969] ARM: dts: imx6qdl-savageboard: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-savageboard.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-savageboard.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi index 02e6d36e85fa..6823a639ed2f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi @@ -83,7 +83,7 @@ brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <4>; power-supply = <®_3p3v>; - pwms = <&pwm1 0 10000>; + pwms = <&pwm1 0 10000 0>; }; reg_3p3v: regulator-3p3v { @@ -140,7 +140,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From 0d68bb973201469793f2fe327d6324236250b01a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:18 +0200 Subject: [PATCH 794/969] ARM: dts: imx6qdl-skov-cpu: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt2.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6dl-skov-revc-lt6.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt2.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-skov-revc-lt6.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-skov-reve-mi1010ait-1cp1.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi index d59d5d0e1d19..6ab71a729fd8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -282,7 +282,6 @@ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <2>; status = "okay"; }; From 4d1e5aded39f8deb9e829e435f8c418da1f8aeb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:19 +0200 Subject: [PATCH 795/969] ARM: dts: imx6q-kp: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6q-kp-tpc.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi index 091903f53a56..c425d427663d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi @@ -15,7 +15,7 @@ / { backlight_lcd: backlight-lcd { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 255>; num-interpolated-steps = <255>; default-brightness-level = <250>; @@ -23,7 +23,7 @@ beeper { compatible = "pwm-beeper"; - pwms = <&pwm2 0 500000>; + pwms = <&pwm2 0 500000 0>; }; lcd_display: display { @@ -378,14 +378,12 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; }; &pwm2 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; From 825bfb1085ea261c5fac24a02f48608ccfc547a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:20 +0200 Subject: [PATCH 796/969] ARM: dts: imx6q-novena: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-novena.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-novena.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts index a7d5a68110fc..d392b5bd2eea 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -67,7 +67,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 10000000>; + pwms = <&pwm1 0 10000000 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight_novena>; power-supply = <®_lvds_lcd>; @@ -465,7 +465,6 @@ }; &pwm1 { - #pwm-cells = <2>; status = "okay"; }; From b2c7bf48720ddbdf32ba43e3b318562244785ffc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:21 +0200 Subject: [PATCH 797/969] ARM: dts: imx6q-pistachio: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts index 46c6b96d8073..56b77cc0af2b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts @@ -124,7 +124,7 @@ backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm1 0 50000>; + pwms = <&pwm1 0 50000 0>; brightness-levels = < 0 /*1 2 3 4 5 6*/ 7 8 9 10 11 12 13 14 15 16 17 18 19 @@ -571,7 +571,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From 600c98d0ead431494abdb93c2e759b303e9dcd35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:22 +0200 Subject: [PATCH 798/969] ARM: dts: imx6q-prti6q: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts index 3508a2cd928a..a7d5693c5ab7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts @@ -22,7 +22,7 @@ compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; default-brightness-level = <1>; @@ -292,7 +292,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From 27d698c73dc29699a6540598ac85a4b581ffc326 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:23 +0200 Subject: [PATCH 799/969] ARM: dts: imx6q-var-dt6customboard: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts index 2290c1237634..0225a621ec7a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts @@ -18,7 +18,7 @@ backlight_lvds: backlight { compatible = "pwm-backlight"; - pwms = <&pwm2 0 50000>; + pwms = <&pwm2 0 50000 0>; brightness-levels = <0 4 8 16 32 64 128 248>; default-brightness-level = <7>; status = "okay"; @@ -203,7 +203,6 @@ }; &pwm2 { - #pwm-cells = <2>; status = "okay"; }; From c027e8fc1a088151659c99e8054e5bf729c3d41e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:24 +0200 Subject: [PATCH 800/969] ARM: dts: imx6sl-evk: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6sl-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable these devices. Drop this property, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts index 239bc6dfc584..31eee0419af7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts @@ -23,7 +23,7 @@ backlight_display: backlight_display { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; @@ -584,10 +584,8 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; }; ®_vdd1p1 { From 50c0557cab9e1da019ab5491855239a041141229 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:25 +0200 Subject: [PATCH 801/969] ARM: dts: imx6sll-evk: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6sll-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable this device. Drop this property, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts index e3e9b0ec4f73..febc2dd9967d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts @@ -26,7 +26,7 @@ backlight_display: backlight-display { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; @@ -314,10 +314,8 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; }; &snvs_poweroff { From 01c7523fc30aeaa6db49b62c24c23c8f5475f1df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:26 +0200 Subject: [PATCH 802/969] ARM: dts: imx6sx-nitrogen6sx: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: pwm@208c000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable this device. Drop this property, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts index b82d91a7d76d..1c1515a854c8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts @@ -18,7 +18,7 @@ backlight-lvds { compatible = "pwm-backlight"; - pwms = <&pwm4 0 5000000>; + pwms = <&pwm4 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; power-supply = <®_3p3v>; @@ -229,10 +229,8 @@ }; &pwm4 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; }; &ssi1 { From 340bef9852edd63e2bb356b0f52db8c7c17f59fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:27 +0200 Subject: [PATCH 803/969] ARM: dts: imx6sx-sdb: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6sx-sdb-reva.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb-sai.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-sdb-mqs.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm node as the soc dtsi doesn't disable this device. Drop this property, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index 67872c16372a..7d4170c27732 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -23,7 +23,7 @@ backlight_display: backlight-display { compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; @@ -295,10 +295,8 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; }; &snvs_poweroff { From e80729dbfbdc673914416e8e0aa926284278cecf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:28 +0200 Subject: [PATCH 804/969] ARM: dts: imx6sx-softing-vining-2000: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dtb: pwm@2084000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dtb: pwm@22a8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# There is no need for an explicit status = "okay" in the pwm nodes as the soc dtsi doesn't disable these devices. Drop these properties, too. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- .../boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts index bfcd8f7d86dd..f999eb244373 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-softing-vining-2000.dts @@ -46,19 +46,19 @@ led-1 { label = "red"; max-brightness = <255>; - pwms = <&pwm6 0 50000>; + pwms = <&pwm6 0 50000 0>; }; led-2 { label = "green"; max-brightness = <255>; - pwms = <&pwm2 0 50000>; + pwms = <&pwm2 0 50000 0>; }; led-3 { label = "blue"; max-brightness = <255>; - pwms = <&pwm1 0 50000>; + pwms = <&pwm1 0 50000 0>; }; }; }; @@ -505,24 +505,18 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; }; &pwm2 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; }; &pwm6 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm6>; - status = "okay"; }; ®_arm { From 099c500fb05ed77aa5b246f0ec6ff0d934c2ac23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:29 +0200 Subject: [PATCH 805/969] ARM: dts: imx6ul-14x14-evk: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ull-14x14-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ulz-14x14-evk.dtb: pwm@2080000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index f10f0525490b..9cfb99ac9e9d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -16,7 +16,7 @@ backlight_display: backlight-display { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; @@ -277,7 +277,6 @@ }; &pwm1 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; status = "okay"; From 71bc44caaa547a2268b374508934c6209216966e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:30 +0200 Subject: [PATCH 806/969] ARM: dts: imx6ul-ccimx6ulsbcpro: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dtb: pwm@20f0000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts index 1762bc47e18d..ed61ae8524fa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts @@ -18,7 +18,7 @@ lcd_backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm5 0 50000>; + pwms = <&pwm5 0 50000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; @@ -168,7 +168,6 @@ }; &pwm5 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; status = "okay"; From 0af28e0d6a963ff8618344311f4bef713515c1ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:31 +0200 Subject: [PATCH 807/969] ARM: dts: imx6ul-geam: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6ul-geam.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts index 2ca18f3dad0a..cdbb8c435cd6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts @@ -21,7 +21,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm8 0 100000>; + pwms = <&pwm8 0 100000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 @@ -194,7 +194,6 @@ }; &pwm8 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; status = "okay"; From 6400c2ed8c4f298fcdde6e97247b2147421f2e04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:32 +0200 Subject: [PATCH 808/969] ARM: dts: imx6ul-imx6ull-opos6uldev: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-opos6uldev.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ull-opos6uldev.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi index af337f18a266..be3cacb4fa7a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-opos6uldev.dtsi @@ -9,7 +9,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 191000>; + pwms = <&pwm3 0 191000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <7>; power-supply = <®_5v>; @@ -143,7 +143,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; From 1b5ee99effc2ba114712f9c8e388a924534b84ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:33 +0200 Subject: [PATCH 809/969] ARM: dts: imx6ul-isiot: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-isiot-emmc.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi index 14fc4828ba4e..ee86c36205f9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi @@ -20,7 +20,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm8 0 100000>; + pwms = <&pwm8 0 100000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 @@ -187,7 +187,6 @@ }; &pwm8 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; status = "okay"; From ce88af1a8ecbc659ff44177386f677a2ea8d6bfb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:34 +0200 Subject: [PATCH 810/969] ARM: dts: imx6ul-kontron-bl-43: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warning: arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dtb: pwm@20f8000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts index 0c643706a158..4e8191a65211 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dts @@ -14,7 +14,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm7 0 5000000>; + pwms = <&pwm7 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; @@ -41,7 +41,6 @@ }; &pwm7 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm7>; status = "okay"; From f98cf09e1c086a8a27bc696add94f1b790794e62 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:35 +0200 Subject: [PATCH 811/969] ARM: dts: imx6ul-kontron-bl-common: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-43.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ull-kontron-bl.dtb: pwm@20fc000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi index 33d5f27285a4..d8f7877349c9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi @@ -35,7 +35,7 @@ pwm-beeper { compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; + pwms = <&pwm8 0 5000 0>; }; reg_3v3: regulator-3v3 { @@ -152,7 +152,6 @@ }; &pwm8 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm8>; status = "okay"; From 68313ee6961ca59a77c164a55cc352cc8bbfa6ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 5 Apr 2024 23:42:36 +0200 Subject: [PATCH 812/969] ARM: dts: imx6ul-pico: Use #pwm-cells = <3> for imx27-pwm device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding dictates using 3 pwm-cells. Adhere to that. This fixes the following dtbs_check warnings: arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dtb: pwm@2088000: #pwm-cells:0:0: 3 was expected from schema : http://devicetree.org/schemas/pwm/imx-pwm.yaml# Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi index 07dcecbe485d..fe307f49b9e5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi @@ -22,7 +22,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; status = "okay"; @@ -177,7 +177,6 @@ }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "okay"; From 8b40a46966d294bc64bad0feb13d3304fde738f2 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 17 Apr 2024 15:38:47 -0500 Subject: [PATCH 813/969] arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Jisheng Zhang Acked-by: Sudeep Holla Acked-by: Dinh Nguyen Acked-by: Heiko Stuebner Acked-by: Bjorn Andersson Acked-by: Florian Fainelli Acked-by: Alim Akhtar Acked-by: Thierry Reding Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 2 +- arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 +- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 2 +- arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 5 ----- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- arch/arm64/boot/dts/sprd/sc9860.dtsi | 2 +- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 2 +- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 +- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 31 files changed, 43 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index 22c7f1561344..926f87b86590 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -432,8 +432,8 @@ }; }; - arm-pmu { - compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; + pmu { + compatible = "arm,cortex-a72-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 072fe20cfca0..cbbc53c47921 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -79,7 +79,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 170 4>, <0 171 4>, <0 172 4>, diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index dbf2dce8d1d6..dbe21d88a29e 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -106,7 +106,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 988928c60f15..ee3f838b4904 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -122,7 +122,7 @@ }; pmu { - compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; + compatible = "apm,potenza-pmu"; interrupts = <1 12 0xff04>; }; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 8db4243a4947..9115c99d0dc0 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -102,7 +102,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = , ; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 896d1f33b5b6..cfd9fd23a1c2 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -102,7 +102,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index d8516ec0dae7..857fa427e195 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -142,7 +142,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 8ad31dee11a3..4c9f1f808427 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -361,7 +361,7 @@ }; pmu { - compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; + compatible = "cavium,thunder-pmu"; interrupts = <1 7 4>; }; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index 3419bd252696..68cb3d01187a 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -83,7 +83,7 @@ }; pmu { - compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; + compatible = "brcm,vulcan-pmu"; interrupts = ; /* PMU overflow */ }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index fe9093b3c02e..a0f7bbd691a0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -81,7 +81,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d333b773bc45..8ee6d8c0ef61 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -276,7 +276,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <0 106 0x4>, <0 107 0x4>, <0 95 0x4>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1aa38ed09aa4..8352197cea6f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -12,6 +12,13 @@ #include #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a57-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 8581ea55d254..245bbd615c81 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -12,6 +12,13 @@ #include #include "fsl-ls208xa.dtsi" +/ { + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ + }; +}; + &cpu { cpu0: cpu@0 { device_type = "cpu"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 0b7292835906..ccba0a135b24 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -247,11 +247,6 @@ <1 10 4>; /* Hypervisor PPI, active-low */ }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ - }; - psci { compatible = "arm,psci-0.2"; method = "smc"; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a0674c5c5576..b8abd98bdc43 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -104,7 +104,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi index 781761d2942b..ae00e9e54e82 100644 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -70,7 +70,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 76aafa172eb0..2a5eeb21da47 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -80,7 +80,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 5591939e057b..75377c292bcb 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -68,7 +68,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 1cc3fa1c354d..9603223dd761 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -68,7 +68,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 9cbd6dd8f671..d0b03dc4d3f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -165,7 +165,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a35-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 47f8268e46bf..882b1d1f4ada 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -2004,7 +2004,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 89beac833d43..d3cd68190a17 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -165,7 +165,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 832f472c4b7a..f2a5e2e40461 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -177,7 +177,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7dbdf8ca6de6..b74cf4baedd6 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -224,7 +224,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = ; }; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 34802cc62983..e57317a17aa9 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -109,7 +109,7 @@ }; arm_pmu: pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 62af0cb94839..734f87db4d11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -141,7 +141,7 @@ }; arm-pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index e27eb3ed1d47..6bfdbdb0e1cd 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -165,7 +165,7 @@ }; pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index 22d81ace740a..53e5b77d70b5 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -134,7 +134,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a55-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index 53d616c3cfed..71e4bfcc9e81 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -88,7 +88,7 @@ }; pmu { - compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 047a83cee603..690b4ed9c29b 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -304,7 +304,7 @@ }; arm-pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a72-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 25d20d803230..34d0e0be3fe6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -169,7 +169,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupt-parent = <&gic>; interrupts = , , From a2269a66eec37916e2bcc148b7f7ed398b66263f Mon Sep 17 00:00:00 2001 From: Alexander Egorenkov Date: Tue, 23 Apr 2024 11:42:05 +0200 Subject: [PATCH 814/969] s390/os_info: Initialize old os_info in standalone dump kernel The commit be42660d0c13 ("s390/crash: use old os_info to create PT_LOAD headers") introduced use of the old os_info into standalone dump kernel. Before this change os_info_old_init() expected to be called only from a regular kdump kernel although the function itself is able to work in standalone dump kernels as well (because copy_oldmem_kernel() is able to handle both use cases). Therefore, fix the expectation of os_info_old_init() and enable it to be called from a standalone dump kernel. Fixes: f4cac27dc0d6 ("s390/crash: Use old os_info to create PT_LOAD headers") Acked-by: Alexander Gordeev Signed-off-by: Alexander Egorenkov Signed-off-by: Alexander Gordeev --- arch/s390/kernel/os_info.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c index 3f4dc045a894..cb73860c048d 100644 --- a/arch/s390/kernel/os_info.c +++ b/arch/s390/kernel/os_info.c @@ -18,6 +18,7 @@ #include #include #include +#include /* * OS info structure has to be page aligned @@ -146,7 +147,7 @@ static void os_info_old_init(void) if (os_info_init) return; - if (!oldmem_data.start) + if (!oldmem_data.start && !is_ipl_type_dump()) goto fail; if (copy_oldmem_kernel(&addr, __LC_OS_INFO, sizeof(addr))) goto fail; From fe742c08f3d930d62647412f602d2b4a211a0a39 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Fri, 26 Apr 2024 08:02:06 +0200 Subject: [PATCH 815/969] s390/os_info: Fix array size in struct os_info gcc's -Warray-bounds warned about an out-of-bounds access to the entry array contained in struct os_info. This doesn't trigger a bug right now because there's a large reserved space after the array. Nevertheless fix this, and also add a BUILD_BUG_ON to make sure struct os_info is always exactly on page in size. Fixes: f4cac27dc0d6 ("s390/crash: Use old os_info to create PT_LOAD headers") Reviewed-by: Alexander Gordeev Signed-off-by: Sven Schnelle Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/os_info.h | 5 +++-- arch/s390/kernel/os_info.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/os_info.h b/arch/s390/include/asm/os_info.h index dea2b37b635e..3ee9e8f5ceae 100644 --- a/arch/s390/include/asm/os_info.h +++ b/arch/s390/include/asm/os_info.h @@ -27,6 +27,7 @@ #define OS_INFO_IMAGE_START 10 #define OS_INFO_IMAGE_END 11 #define OS_INFO_IMAGE_PHYS 12 +#define OS_INFO_MAX 13 #define OS_INFO_FLAG_REIPL_CLEAR (1UL << 0) @@ -46,8 +47,8 @@ struct os_info { u16 version_minor; u64 crashkernel_addr; u64 crashkernel_size; - struct os_info_entry entry[10]; - u8 reserved[3864]; + struct os_info_entry entry[OS_INFO_MAX]; + u8 reserved[3804]; } __packed; void os_info_init(void); diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c index cb73860c048d..b695f980bbde 100644 --- a/arch/s390/kernel/os_info.c +++ b/arch/s390/kernel/os_info.c @@ -73,6 +73,7 @@ void __init os_info_init(void) { struct lowcore *abs_lc; + BUILD_BUG_ON(sizeof(struct os_info) != PAGE_SIZE); os_info.version_major = OS_INFO_VERSION_MAJOR; os_info.version_minor = OS_INFO_VERSION_MINOR; os_info.magic = OS_INFO_MAGIC; From 9679fec2cad447d70f32142c194f2d1c8544717c Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Tue, 23 Apr 2024 16:27:24 +0200 Subject: [PATCH 816/969] s390/pci: Drop unneeded reference to CONFIG_DMI The S/390 architecture doesn't support SMBIOS, so CONFIG_DMI will never be defined there. So we can simply omit these preprocessing directives and speed up the build a bit. Signed-off-by: Jean Delvare Cc: Niklas Schnelle Cc: Gerald Schaefer Acked-by: Niklas Schnelle Link: https://lore.kernel.org/r/20240423162724.3966265a@endymion.delvare Signed-off-by: Alexander Gordeev --- arch/s390/pci/pci_sysfs.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/s390/pci/pci_sysfs.c b/arch/s390/pci/pci_sysfs.c index a0b872b74fe3..0f4f1e8fc480 100644 --- a/arch/s390/pci/pci_sysfs.c +++ b/arch/s390/pci/pci_sysfs.c @@ -172,7 +172,6 @@ static ssize_t uid_is_unique_show(struct device *dev, } static DEVICE_ATTR_RO(uid_is_unique); -#ifndef CONFIG_DMI /* analogous to smbios index */ static ssize_t index_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -202,7 +201,6 @@ static struct attribute_group zpci_ident_attr_group = { .attrs = zpci_ident_attrs, .is_visible = zpci_index_is_visible, }; -#endif static struct bin_attribute *zpci_bin_attrs[] = { &bin_attr_util_string, @@ -245,8 +243,6 @@ static struct attribute_group pfip_attr_group = { const struct attribute_group *zpci_attr_groups[] = { &zpci_attr_group, &pfip_attr_group, -#ifndef CONFIG_DMI &zpci_ident_attr_group, -#endif NULL, }; From cae74ba8c295bc41bda749ef27a8f2b3ee957a41 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Fri, 26 Apr 2024 12:02:15 +0200 Subject: [PATCH 817/969] s390/ftrace: Use unwinder instead of __builtin_return_address() Using __builtin_return_address(n) might return undefined values when used with values of n outside of the stack. This was noticed when __builtin_return_address() was called in ftrace on top level functions like the interrupt handlers. As this behaviour cannot be fixed, use the s390 stack unwinder and remove the ftrace compilation flags for unwind_bc.c and stacktrace.c to prevent the unwinding function polluting function traces. Another advantage is that this also works with clang. Reviewed-by: Heiko Carstens Signed-off-by: Sven Schnelle Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/ftrace.h | 8 ++------ arch/s390/kernel/Makefile | 2 ++ arch/s390/kernel/stacktrace.c | 19 +++++++++++++++++++ 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h index 621f23d5ae30..77e479d44f1e 100644 --- a/arch/s390/include/asm/ftrace.h +++ b/arch/s390/include/asm/ftrace.h @@ -8,12 +8,8 @@ #ifndef __ASSEMBLY__ -#ifdef CONFIG_CC_IS_CLANG -/* https://llvm.org/pr41424 */ -#define ftrace_return_address(n) 0UL -#else -#define ftrace_return_address(n) __builtin_return_address(n) -#endif +unsigned long return_address(unsigned int n); +#define ftrace_return_address(n) return_address(n) void ftrace_caller(void); diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile index fa029d0dc28f..db2d9ba5a86d 100644 --- a/arch/s390/kernel/Makefile +++ b/arch/s390/kernel/Makefile @@ -11,6 +11,8 @@ CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE) # Do not trace early setup code CFLAGS_REMOVE_early.o = $(CC_FLAGS_FTRACE) CFLAGS_REMOVE_rethook.o = $(CC_FLAGS_FTRACE) +CFLAGS_REMOVE_stacktrace.o = $(CC_FLAGS_FTRACE) +CFLAGS_REMOVE_unwind_bc.o = $(CC_FLAGS_FTRACE) endif diff --git a/arch/s390/kernel/stacktrace.c b/arch/s390/kernel/stacktrace.c index 94f440e38303..7c294da45bf5 100644 --- a/arch/s390/kernel/stacktrace.c +++ b/arch/s390/kernel/stacktrace.c @@ -101,3 +101,22 @@ void arch_stack_walk_user(stack_trace_consume_fn consume_entry, void *cookie, } pagefault_enable(); } + +unsigned long return_address(unsigned int n) +{ + struct unwind_state state; + unsigned long addr; + + /* Increment to skip current stack entry */ + n++; + + unwind_for_each_frame(&state, NULL, NULL, 0) { + addr = unwind_get_return_address(&state); + if (!addr) + break; + if (!n--) + return addr; + } + return 0; +} +EXPORT_SYMBOL_GPL(return_address); From 5f90003f09042b504d90ee38618cfd380ce16f4a Mon Sep 17 00:00:00 2001 From: Sumanth Korikkar Date: Thu, 25 Apr 2024 16:59:30 +0200 Subject: [PATCH 818/969] s390: vmlinux.lds.S: Drop .hash and .gnu.hash for !CONFIG_PIE_BUILD Sections .hash and .gnu.hash are only created when CONFIG_PIE_BUILD option is enabled. Drop these for the case CONFIG_PIE_BUILD is disabled. [ agordeev: Reworded the commit message ] Fixes: 778666df60f0 ("s390: compile relocatable kernel without -fPIE") Suggested-by: Alexander Gordeev Signed-off-by: Sumanth Korikkar Reviewed-by: Alexander Gordeev Signed-off-by: Alexander Gordeev --- arch/s390/kernel/vmlinux.lds.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index 023fade1da3b..163d64f300c1 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -209,13 +209,13 @@ SECTIONS .dynstr ALIGN(8) : { *(.dynstr) } -#endif .hash ALIGN(8) : { *(.hash) } .gnu.hash ALIGN(8) : { *(.gnu.hash) } +#endif . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ From 00cda11d3b2ea07295490b7d67942014f1cbc5c1 Mon Sep 17 00:00:00 2001 From: Sumanth Korikkar Date: Thu, 25 Apr 2024 16:59:31 +0200 Subject: [PATCH 819/969] s390: Compile kernel with -fPIC and link with -no-pie When the kernel is built with CONFIG_PIE_BUILD option enabled it uses dynamic symbols, for which the linker does not allow more than 64K number of entries. This can break features like kpatch. Hence, whenever possible the kernel is built with CONFIG_PIE_BUILD option disabled. For that support of unaligned symbols generated by linker scripts in the compiler is necessary. However, older compilers might lack such support. In that case the build process resorts to CONFIG_PIE_BUILD option-enabled build. Compile object files with -fPIC option and then link the kernel binary with -no-pie linker option. As result, the dynamic symbols are not generated and not only kpatch feature succeeds, but also the whole CONFIG_PIE_BUILD option-enabled code could be dropped. [ agordeev: Reworded the commit message ] Suggested-by: Ulrich Weigand Signed-off-by: Sumanth Korikkar Reviewed-by: Alexander Gordeev Signed-off-by: Alexander Gordeev --- arch/s390/Kconfig | 12 ---------- arch/s390/Makefile | 9 ++------ arch/s390/boot/Makefile | 7 +----- arch/s390/boot/boot.h | 6 ----- arch/s390/boot/startup.c | 42 ---------------------------------- arch/s390/boot/vmlinux.lds.S | 2 -- arch/s390/kernel/vmlinux.lds.S | 33 -------------------------- 7 files changed, 3 insertions(+), 108 deletions(-) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index a077ded1b9e6..7e7fe89c9b25 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -593,18 +593,6 @@ config RELOCATABLE Note: this option exists only for documentation purposes, please do not remove it. -config PIE_BUILD - def_bool CC_IS_CLANG && !$(cc-option,-munaligned-symbols) - help - If the compiler is unable to generate code that can manage unaligned - symbols, the kernel is linked as a position-independent executable - (PIE) and includes dynamic relocations that are processed early - during bootup. - - For kpatch functionality, it is recommended to build the kernel - without the PIE_BUILD option. PIE_BUILD is only enabled when the - compiler lacks proper support for handling unaligned symbols. - config RANDOMIZE_BASE bool "Randomize the address of the kernel image (KASLR)" default y diff --git a/arch/s390/Makefile b/arch/s390/Makefile index 64821f54f1e0..f2b21c7a70ef 100644 --- a/arch/s390/Makefile +++ b/arch/s390/Makefile @@ -14,14 +14,9 @@ KBUILD_AFLAGS_MODULE += -fPIC KBUILD_CFLAGS_MODULE += -fPIC KBUILD_AFLAGS += -m64 KBUILD_CFLAGS += -m64 -ifdef CONFIG_PIE_BUILD -KBUILD_CFLAGS += -fPIE -LDFLAGS_vmlinux := -pie -z notext -else -KBUILD_CFLAGS += $(call cc-option,-munaligned-symbols,) -LDFLAGS_vmlinux := --emit-relocs --discard-none +KBUILD_CFLAGS += -fPIC +LDFLAGS_vmlinux := -no-pie --emit-relocs --discard-none extra_tools := relocs -endif aflags_dwarf := -Wa,-gdwarf-2 KBUILD_AFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -D__ASSEMBLY__ ifndef CONFIG_AS_IS_LLVM diff --git a/arch/s390/boot/Makefile b/arch/s390/boot/Makefile index bd5d4d37a961..070c9b2e905f 100644 --- a/arch/s390/boot/Makefile +++ b/arch/s390/boot/Makefile @@ -37,8 +37,7 @@ CFLAGS_sclp_early_core.o += -I$(srctree)/drivers/s390/char obj-y := head.o als.o startup.o physmem_info.o ipl_parm.o ipl_report.o vmem.o obj-y += string.o ebcdic.o sclp_early_core.o mem.o ipl_vmparm.o cmdline.o -obj-y += version.o pgm_check_info.o ctype.o ipl_data.o -obj-y += $(if $(CONFIG_PIE_BUILD),machine_kexec_reloc.o,relocs.o) +obj-y += version.o pgm_check_info.o ctype.o ipl_data.o relocs.o obj-$(findstring y, $(CONFIG_PROTECTED_VIRTUALIZATION_GUEST) $(CONFIG_PGSTE)) += uv.o obj-$(CONFIG_RANDOMIZE_BASE) += kaslr.o obj-y += $(if $(CONFIG_KERNEL_UNCOMPRESSED),,decompressor.o) info.o @@ -49,9 +48,7 @@ targets := bzImage section_cmp.boot.data section_cmp.boot.preserved.data $(obj-y targets += vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 targets += vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.lz4 targets += vmlinux.bin.zst info.bin syms.bin vmlinux.syms $(obj-all) -ifndef CONFIG_PIE_BUILD targets += relocs.S -endif OBJECTS := $(addprefix $(obj)/,$(obj-y)) OBJECTS_ALL := $(addprefix $(obj)/,$(obj-all)) @@ -110,13 +107,11 @@ OBJCOPYFLAGS_vmlinux.bin := -O binary --remove-section=.comment --remove-section $(obj)/vmlinux.bin: vmlinux FORCE $(call if_changed,objcopy) -ifndef CONFIG_PIE_BUILD CMD_RELOCS=arch/s390/tools/relocs quiet_cmd_relocs = RELOCS $@ cmd_relocs = $(CMD_RELOCS) $< > $@ $(obj)/relocs.S: vmlinux FORCE $(call if_changed,relocs) -endif suffix-$(CONFIG_KERNEL_GZIP) := .gz suffix-$(CONFIG_KERNEL_BZIP2) := .bz2 diff --git a/arch/s390/boot/boot.h b/arch/s390/boot/boot.h index 85da1c6cef4f..18027fdc92b0 100644 --- a/arch/s390/boot/boot.h +++ b/arch/s390/boot/boot.h @@ -24,14 +24,8 @@ struct vmlinux_info { unsigned long bootdata_size; unsigned long bootdata_preserved_off; unsigned long bootdata_preserved_size; -#ifdef CONFIG_PIE_BUILD - unsigned long dynsym_start; - unsigned long rela_dyn_start; - unsigned long rela_dyn_end; -#else unsigned long got_start; unsigned long got_end; -#endif unsigned long amode31_size; unsigned long init_mm_off; unsigned long swapper_pg_dir_off; diff --git a/arch/s390/boot/startup.c b/arch/s390/boot/startup.c index 246d54499c20..467283b112cd 100644 --- a/arch/s390/boot/startup.c +++ b/arch/s390/boot/startup.c @@ -151,41 +151,6 @@ static void copy_bootdata(void) memcpy((void *)vmlinux.bootdata_preserved_off, __boot_data_preserved_start, vmlinux.bootdata_preserved_size); } -#ifdef CONFIG_PIE_BUILD -static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, - unsigned long offset, unsigned long phys_offset) -{ - Elf64_Rela *rela_start, *rela_end, *rela; - int r_type, r_sym, rc; - Elf64_Addr loc, val; - Elf64_Sym *dynsym; - - rela_start = (Elf64_Rela *) vmlinux.rela_dyn_start; - rela_end = (Elf64_Rela *) vmlinux.rela_dyn_end; - dynsym = (Elf64_Sym *) vmlinux.dynsym_start; - for (rela = rela_start; rela < rela_end; rela++) { - loc = rela->r_offset + phys_offset - __START_KERNEL; - val = rela->r_addend; - r_sym = ELF64_R_SYM(rela->r_info); - if (r_sym) { - if (dynsym[r_sym].st_shndx != SHN_UNDEF) - val += dynsym[r_sym].st_value + offset - __START_KERNEL; - } else { - /* - * 0 == undefined symbol table index (SHN_UNDEF), - * used for R_390_RELATIVE, only add KASLR offset - */ - val += offset - __START_KERNEL; - } - r_type = ELF64_R_TYPE(rela->r_info); - rc = arch_kexec_do_relocs(r_type, (void *) loc, val, 0); - if (rc) - error("Unknown relocation type"); - } -} - -static void kaslr_adjust_got(unsigned long offset) {} -#else static void kaslr_adjust_relocs(unsigned long min_addr, unsigned long max_addr, unsigned long offset, unsigned long phys_offset) { @@ -212,7 +177,6 @@ static void kaslr_adjust_got(unsigned long offset) for (entry = (u64 *)vmlinux.got_start; entry < (u64 *)vmlinux.got_end; entry++) *entry += offset - __START_KERNEL; } -#endif /* * Merge information from several sources into a single ident_map_size value. @@ -398,14 +362,8 @@ static void kaslr_adjust_vmlinux_info(long offset) { vmlinux.bootdata_off += offset; vmlinux.bootdata_preserved_off += offset; -#ifdef CONFIG_PIE_BUILD - vmlinux.rela_dyn_start += offset; - vmlinux.rela_dyn_end += offset; - vmlinux.dynsym_start += offset; -#else vmlinux.got_start += offset; vmlinux.got_end += offset; -#endif vmlinux.init_mm_off += offset; vmlinux.swapper_pg_dir_off += offset; vmlinux.invalid_pg_dir_off += offset; diff --git a/arch/s390/boot/vmlinux.lds.S b/arch/s390/boot/vmlinux.lds.S index d6454ec01e22..1fe5a1d3ff60 100644 --- a/arch/s390/boot/vmlinux.lds.S +++ b/arch/s390/boot/vmlinux.lds.S @@ -99,14 +99,12 @@ SECTIONS _decompressor_end = .; -#ifndef CONFIG_PIE_BUILD . = ALIGN(4); .vmlinux.relocs : { __vmlinux_relocs_64_start = .; *(.vmlinux.relocs_64) __vmlinux_relocs_64_end = .; } -#endif #ifdef CONFIG_KERNEL_UNCOMPRESSED . = ALIGN(PAGE_SIZE); diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index 163d64f300c1..a1ce3925ec71 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -192,31 +192,6 @@ SECTIONS PERCPU_SECTION(0x100) -#ifdef CONFIG_PIE_BUILD - .dynsym ALIGN(8) : { - __dynsym_start = .; - *(.dynsym) - __dynsym_end = .; - } - .rela.dyn ALIGN(8) : { - __rela_dyn_start = .; - *(.rela*) - __rela_dyn_end = .; - } - .dynamic ALIGN(8) : { - *(.dynamic) - } - .dynstr ALIGN(8) : { - *(.dynstr) - } - .hash ALIGN(8) : { - *(.hash) - } - .gnu.hash ALIGN(8) : { - *(.gnu.hash) - } -#endif - . = ALIGN(PAGE_SIZE); __init_end = .; /* freed after init ends here */ @@ -238,14 +213,8 @@ SECTIONS QUAD(__boot_data_preserved_start) /* bootdata_preserved_off */ QUAD(__boot_data_preserved_end - __boot_data_preserved_start) /* bootdata_preserved_size */ -#ifdef CONFIG_PIE_BUILD - QUAD(__dynsym_start) /* dynsym_start */ - QUAD(__rela_dyn_start) /* rela_dyn_start */ - QUAD(__rela_dyn_end) /* rela_dyn_end */ -#else QUAD(__got_start) /* got_start */ QUAD(__got_end) /* got_end */ -#endif QUAD(_eamode31 - _samode31) /* amode31_size */ QUAD(init_mm) QUAD(swapper_pg_dir) @@ -281,12 +250,10 @@ SECTIONS *(.plt) *(.plt.*) *(.iplt) *(.igot .igot.plt) } ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!") -#ifndef CONFIG_PIE_BUILD .rela.dyn : { *(.rela.*) *(.rela_*) } ASSERT(SIZEOF(.rela.dyn) == 0, "Unexpected run-time relocations (.rela) detected!") -#endif /* Sections to be discarded */ DISCARDS From 01aea123b11c7ebbdd64b2df3a4a5a7ad86a460d Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 14:02:17 +0100 Subject: [PATCH 820/969] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt schema documentation and clock IDs for the High Speed Interface 2 (HSI2) clock management unit. This CMU feeds high speed interfaces such as PCIe and UFS. [AD: * keep CMUs in google,gs101.h sorted alphabetically * resolve minor merge conflicts in google,gs101-clock.yaml * s/ufs_embd/ufs s/mmc_card/mmc Signed-off-by: Peter Griffin Reviewed-by: Rob Herring (Arm) Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-1-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 26 ++++++++ include/dt-bindings/clock/google,gs101.h | 62 +++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 94dcc4f84c85..caf442ead24b 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -31,6 +31,7 @@ properties: - google,gs101-cmu-apm - google,gs101-cmu-misc - google,gs101-cmu-hsi0 + - google,gs101-cmu-hsi2 - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 @@ -97,6 +98,31 @@ allOf: - const: usb31drd - const: usbdpdbg + - if: + properties: + compatible: + contains: + enum: + - google,gs101-cmu-hsi2 + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: High Speed Interface bus clock (from CMU_TOP) + - description: High Speed Interface pcie clock (from CMU_TOP) + - description: High Speed Interface ufs clock (from CMU_TOP) + - description: High Speed Interface mmc clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - const: pcie + - const: ufs + - const: mmc + - if: properties: compatible: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 7a2006f0edf1..442f9e9037dc 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -367,6 +367,68 @@ #define CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK 51 #define CLK_GOUT_HSI0_XIU_P_HSI0_ACLK 52 +/* CMU_HSI2 */ +#define CLK_MOUT_HSI2_BUS_USER 1 +#define CLK_MOUT_HSI2_MMC_CARD_USER 2 +#define CLK_MOUT_HSI2_PCIE_USER 3 +#define CLK_MOUT_HSI2_UFS_EMBD_USER 4 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN 5 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN 6 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK 7 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK 8 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK 9 +#define CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK 10 +#define CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK 11 +#define CLK_GOUT_HSI2_GPC_HSI2_PCLK 12 +#define CLK_GOUT_HSI2_GPIO_HSI2_PCLK 13 +#define CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK 14 +#define CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK 15 +#define CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK 16 +#define CLK_GOUT_HSI2_MMC_CARD_I_ACLK 17 +#define CLK_GOUT_HSI2_MMC_CARD_SDCLKIN 18 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG 19 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG 20 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG 21 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK 22 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG 23 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG 24 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG 25 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK 26 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK 27 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK 28 +#define CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK 29 +#define CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK 30 +#define CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK 31 +#define CLK_GOUT_HSI2_PPMU_HSI2_ACLK 32 +#define CLK_GOUT_HSI2_PPMU_HSI2_PCLK 33 +#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK 34 +#define CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK 35 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK 36 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK 37 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK 38 +#define CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK 39 +#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK 40 +#define CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK 41 +#define CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK 42 +#define CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK 43 +#define CLK_GOUT_HSI2_SSMT_HSI2_ACLK 44 +#define CLK_GOUT_HSI2_SSMT_HSI2_PCLK 45 +#define CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2 46 +#define CLK_GOUT_HSI2_SYSREG_HSI2_PCLK 47 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK 48 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK 49 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK 50 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK 51 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK 52 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK 53 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK 54 +#define CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK 55 +#define CLK_GOUT_HSI2_UFS_EMBD_I_ACLK 56 +#define CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO 57 +#define CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK 58 +#define CLK_GOUT_HSI2_XIU_D_HSI2_ACLK 59 +#define CLK_GOUT_HSI2_XIU_P_HSI2_ACLK 60 + /* CMU_MISC */ #define CLK_MOUT_MISC_BUS_USER 1 #define CLK_MOUT_MISC_SSS_USER 2 From 4982a4a2092ee9f7334d8f119a6a15d8165f7a04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Fri, 26 Apr 2024 11:03:05 +0100 Subject: [PATCH 821/969] arm64: dts: exynos: gs101: enable cmu-hsi0 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu-hsi0 clock controller. It feeds USB. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240426-hsi0-gs101-v2-2-2157da8b63e3@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index eddb6b326fde..9755a0bb70a1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1247,6 +1247,20 @@ }; }; + cmu_hsi0: clock-controller@11000000 { + compatible = "google,gs101-cmu-hsi0"; + reg = <0x11000000 0x4000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI0_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>, + <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; + clock-names = "oscclk", "bus", "dpgtc", "usb31drd", + "usbdpdbg"; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; From 86124c76683e31033180f1d31e7543863ce6d850 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 14:02:18 +0100 Subject: [PATCH 822/969] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu_hsi2 clock management unit. It feeds some of the high speed interfaces such as PCIe and UFS. Signed-off-by: Peter Griffin Reviewed-by: Tudor Ambarus Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-2-f233be0a2455@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9755a0bb70a1..a0305555c4fd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1267,6 +1267,18 @@ interrupts = ; }; + cmu_hsi2: clock-controller@14400000 { + compatible = "google,gs101-cmu-hsi2"; + reg = <0x14400000 0x4000>; + #clock-cells = <1>; + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_HSI2_BUS>, + <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>, + <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; From 14d15fcbe0f1fac5979a0b01160f3651340e38b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Mon, 29 Apr 2024 11:35:49 +0100 Subject: [PATCH 823/969] arm64: dts: exynos: gs101: add USB & USB-phy nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for Google Tensor GS101. The USB 3.1 DRD controller has the following features: * compliant with both USB device 3.1 and USB device 2.0 standards * compliant with USB host 3.1 and USB host 2.0 standards * supports USB device 3.1 and USB device 2.0 interfaces * supports USB host 3.1 and USB host 2.0 interfaces * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface * single USB port which can be used for USB 3.1 or USB 2.0 * on-chip USB PHY transceiver * DWC3 compatible * supports up to 16 bi-directional endpoints * compliant with xHCI 1.1 specification Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-1-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index a0305555c4fd..e3b068c1a2c1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1261,6 +1261,47 @@ "usbdpdbg"; }; + usbdrd31_phy: phy@11100000 { + compatible = "google,gs101-usb31drd-phy"; + reg = <0x11100000 0x0100>, + <0x110f0000 0x0800>, + <0x110e0000 0x2800>; + reg-names = "phy", "pcs", "pma"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK>; + clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbdrd31: usb@11110000 { + compatible = "google,gs101-dwusb3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; + clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x11110000 0x10000>; + status = "disabled"; + + usbdrd31_dwc3: usb@0 { + compatible = "snps,dwc3"; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40>; + clock-names = "ref"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + }; + pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; From b93b3140e82a0e48442087c38346eabfb92c63af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Mon, 29 Apr 2024 11:35:50 +0100 Subject: [PATCH 824/969] arm64: dts: exynos: gs101-oriole: enable USB on this board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pixel 6 (Oriole) has a USB-C connector that can act as host or device. The USB role is detected dynamically using a MAX77759 TCPCI controller, but since there is no driver for the MAX77759, the role is defaulted to peripheral, without any endpoints / ports. This allows Oriole to be configured as a gadget, e.g. using configfs. As PMIC regulators are not implemented yet, we rely on USB LDOs being enabled by the bootloader. A placeholder regulator is used for now. Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20240429-usb-dts-gs101-v2-2-7c1797c9db80@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/google/gs101-oriole.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 6be15e990b65..03b2a6fdfdc4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -53,6 +53,12 @@ wakeup-source; }; }; + + /* TODO: Remove this once PMIC is implemented */ + reg_placeholder: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "placeholder_reg"; + }; }; &ext_24_5m { @@ -106,6 +112,24 @@ status = "okay"; }; +&usbdrd31 { + status = "okay"; + vdd10-supply = <®_placeholder>; + vdd33-supply = <®_placeholder>; +}; + +&usbdrd31_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + maximum-speed = "super-speed-plus"; + status = "okay"; +}; + +&usbdrd31_phy { + status = "okay"; +}; + &usi_uart { samsung,clkreq-on; /* needed for UART mode */ status = "okay"; From 6d1434a7d95939d21cf300f73040e3e6a02e84f8 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 29 Apr 2024 12:15:34 +0100 Subject: [PATCH 825/969] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update dt schema to include the gs101 hsi2 sysreg compatible. Signed-off-by: Peter Griffin Reviewed-by: André Draszik Acked-by: Rob Herring Link: https://lore.kernel.org/r/20240429111537.2369227-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index c0c6ce8fc786..3ca220582897 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - google,gs101-apm-sysreg + - google,gs101-hsi2-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos3-sysreg @@ -72,6 +73,7 @@ allOf: compatible: contains: enum: + - google,gs101-hsi2-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg - samsung,exynos850-cmgp-sysreg From 0d80ac75cba26fde5cae55323b7617f0fec5322b Mon Sep 17 00:00:00 2001 From: Connor Abbott Date: Fri, 26 Apr 2024 19:33:59 +0100 Subject: [PATCH 826/969] arm64: dts: qcom: sm8650: Fix GPU cx_mem size This is doubled compared to previous GPUs. We can't access the new SW_FUSE_VALUE register without this. Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") Signed-off-by: Connor Abbott Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240426-a750-raytracing-v2-1-562ac9866d63@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 434ad2f12332..745d40adb7fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2614,7 +2614,7 @@ gpu: gpu@3d00000 { compatible = "qcom,adreno-43051401", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d9e000 0x0 0x2000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", From 28c0cf16b3083566cd96b60d3cedbe69b79a8e5b Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Thu, 4 Apr 2024 11:42:50 -0700 Subject: [PATCH 827/969] arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add Audio Codec The Audio Codec runs over the MCASP (Multichannel Audio Serial Port). Add pinmux for the Audio Reference Clock and MCASP2. Add DT nodes for Audio Codec, MCASP2, VCC 1v8 and VCC 3v3 regulators. Additionally, create a sound node that connects our sound card and the MCASP2. Signed-off-by: Garrett Giordano Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240404184250.3772829-1-ggiordano@phytec.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-am625-phyboard-lyra-rdk.dts | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index e225d76d02c8..d7b8aa607c8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -66,6 +66,35 @@ }; }; + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "phyBOARD-Lyra"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "External Speaker", "SPOP", + "External Speaker", "SPOM"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp2>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&audio_refclk1>; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -82,6 +111,15 @@ }; }; + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_3v3_mmc: regulator-vcc-3v3-mmc { compatible = "regulator-fixed"; regulator-name = "VCC_3V3_MMC"; @@ -90,9 +128,24 @@ regulator-always-on; regulator-boot-on; }; + + vcc_3v3_sw: regulator-vcc-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; }; &main_pmx0 { + audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ @@ -150,6 +203,15 @@ >; }; + main_mcasp2_pins_default: main-mcasp2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x070, PIN_INPUT, 3) /* (T24) GPMC0_AD13.MCASP2_ACLKX */ + AM62X_IOPAD(0x06c, PIN_INPUT, 3) /* (T22) GPMC0_AD12.MCASP2_AFSX */ + AM62X_IOPAD(0x064, PIN_OUTPUT, 3) /* (T25) GPMC0_AD10.MCASP2_AXR2 */ + AM62X_IOPAD(0x068, PIN_INPUT, 3) /* (R21) GPMC0_AD11.MCASP2_AXR3 */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ @@ -254,6 +316,21 @@ clock-frequency = <100000>; status = "okay"; + audio_codec: audio-codec@18 { + pinctrl-names = "default"; + pinctrl-0 = <&audio_ext_refclk1_pins_default>; + + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + ai3x-micbias-vg = <2>; + + AVDD-supply = <&vcc_3v3_sw>; + IOVDD-supply = <&vcc_3v3_sw>; + DRVDD-supply = <&vcc_3v3_sw>; + DVDD-supply = <&vcc_1v8>; + }; + gpio_exp: gpio-expander@21 { pinctrl-names = "default"; pinctrl-0 = <&gpio_exp_int_pins_default>; @@ -329,6 +406,28 @@ status = "okay"; }; +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp2_pins_default>; + + /* MCASP_IIS_MODE */ + op-mode = <0>; + tdm-slots = <2>; + + /* 0: INACTIVE, 1: TX, 2: RX */ + serial-dir = < + 0 0 1 2 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; +}; + &sdhci1 { vmmc-supply = <&vcc_3v3_mmc>; vqmmc-supply = <&vddshv5_sdio>; From cc91d709f030b931a71e7571b2d9f9850be57a1d Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Tue, 9 Apr 2024 17:43:14 +0100 Subject: [PATCH 828/969] arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG1 devices Add the required nodes to enable ICSSG SR1.0 based prueth networking. Signed-off-by: Jan Kiszka Signed-off-by: Diogo Ivo Link: https://lore.kernel.org/r/20240409164314.157602-1-diogo.ivo@siemens.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-am65-iot2050-common-pg1.dtsi | 32 ++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi index c50a585dd638..ef7897763ef8 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi @@ -43,9 +43,33 @@ }; &icssg0_eth { - status = "disabled"; -}; + compatible = "ti,am654-sr1-icssg-prueth"; -&icssg0_mdio { - status = "disabled"; + ti,prus = <&pru0_0>, <&rtu0_0>, <&pru0_1>, <&rtu0_1>; + firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf", + "ti-pruss/am65x-rtu0-prueth-fw.elf", + "ti-pruss/am65x-pru1-prueth-fw.elf", + "ti-pruss/am65x-rtu1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, /* MII mode */ + <2>; + + dmas = <&main_udmap 0xc100>, /* egress slice 0 */ + <&main_udmap 0xc101>, /* egress slice 0 */ + <&main_udmap 0xc102>, /* egress slice 0 */ + <&main_udmap 0xc103>, /* egress slice 0 */ + <&main_udmap 0xc104>, /* egress slice 1 */ + <&main_udmap 0xc105>, /* egress slice 1 */ + <&main_udmap 0xc106>, /* egress slice 1 */ + <&main_udmap 0xc107>, /* egress slice 1 */ + <&main_udmap 0x4100>, /* ingress slice 0 */ + <&main_udmap 0x4101>, /* ingress slice 1 */ + <&main_udmap 0x4102>, /* mgmnt rsp slice 0 */ + <&main_udmap 0x4103>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; }; From 556e0504b05994a0c4265202f4d43e9b034a772d Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 12 Apr 2024 14:52:14 +0300 Subject: [PATCH 829/969] arm64: dts: ti: k3-am62*: Add PHY2 region to USB wrapper node Add PHY2 register space to USB wrapper node. This is required to deal with Errata i2409. Signed-off-by: Roger Quadros Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240412-for-v6-9-am62-usb-errata-dt-v1-1-ef0d79920f75@kernel.org Closes: https://lore.kernel.org/all/20240408095200.GA14655@francesco-nb/ Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++-- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index e9cffca073ef..e0ec28b14a07 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -619,7 +619,8 @@ usbss0: dwc3-usb@f900000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; clocks = <&k3_clks 161 3>; clock-names = "ref"; ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; @@ -644,7 +645,8 @@ usbss1: dwc3-usb@f910000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index aa1e057082f0..93494e30305b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -603,7 +603,8 @@ usbss0: dwc3-usb@f900000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f900000 0x00 0x800>; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; clocks = <&k3_clks 161 3>; clock-names = "ref"; ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; @@ -626,7 +627,8 @@ usbss1: dwc3-usb@f910000 { compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; From ef80ebe421afcd184552b7b81eb038a9bb7a3262 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 12 Apr 2024 15:01:58 +0300 Subject: [PATCH 830/969] arm64: dts: ti: k3-am62/a: use sub-node for USB_PHY_CTRL registers Exposing the entire CTRL_MMR space to syscon is not a good idea. Add sub-nodes for USB0_PHY_CTRL and USB1_PHY_CTRL and use them in the USB0/USB1 nodes. Signed-off-by: Roger Quadros Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-1-93b827adf97e@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 ++++++++++ arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++-- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 10 ++++++++++ 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index e0ec28b14a07..448a59dc53a7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -623,7 +623,7 @@ <0x00 0x0f908000 0x00 0x400>; clocks = <&k3_clks 161 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; @@ -649,7 +649,7 @@ <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 23ce1bfda8d6..66ddf2dc51af 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -21,6 +21,16 @@ compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; }; target-module@2b300050 { diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 93494e30305b..31fc59b02f21 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -607,7 +607,7 @@ <0x00 0x0f908000 0x00 0x400>; clocks = <&k3_clks 161 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; @@ -631,7 +631,7 @@ <0x00 0x0f918000 0x00 0x400>; clocks = <&k3_clks 162 3>; clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; #address-cells = <2>; #size-cells = <2>; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index f7bec484705a..98043e9aa316 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -17,6 +17,16 @@ compatible = "ti,am654-chipid"; reg = <0x14 0x4>; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; }; wkup_uart0: serial@2b300000 { From c1453d3c3e9baf538b5f978c9e7cc24e47cc877e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 12 Apr 2024 15:01:59 +0300 Subject: [PATCH 831/969] arm64: dts: ti: k3-am62p: add the USB sub-system There are two USB instances available on the am62p5 starter kit. Include and enable them for use on the board. USB LPM feature is kept disabled as it is not supported. Signed-off-by: Vignesh Raghavendra Signed-off-by: Roger Quadros Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-2-93b827adf97e@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 52 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 10 +++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 67 +++++++++++++++++++++ 3 files changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 88bc64111234..900d1f9530a2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -635,6 +635,58 @@ status = "disabled"; }; + usbss0: usb@f900000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks = <&k3_clks 161 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb0: usb@31000000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31000000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + usbss1: usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + fss: bus@fc00000 { compatible = "simple-bus"; reg = <0x00 0x0fc00000 0x00 0x70000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi index a84756c336d0..c71d9624ea27 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -18,6 +18,16 @@ reg = <0x14 0x4>; bootph-all; }; + + usb0_phy_ctrl: syscon@4008 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4008 0x4>; + }; + + usb1_phy_ctrl: syscon@4018 { + compatible = "ti,am62-usb-phy-ctrl", "syscon"; + reg = <0x4018 0x4>; + }; }; wkup_uart0: serial@2b300000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 6a9c99c5fb2a..6e7234659111 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -27,6 +27,8 @@ spi0 = &ospi0; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; }; chosen { @@ -297,6 +299,12 @@ bootph-all; }; + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + main_wlirq_pins_default: main-wlirq-default-pins { pinctrl-single,pins = < AM62PX_IOPAD(0x0128, PIN_INPUT, 7) /* (K25) MMC2_SDWP.GPIO0_72 */ @@ -340,6 +348,36 @@ }; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; @@ -466,6 +504,35 @@ }; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + &mcasp1 { status = "okay"; #sound-dai-cells = <0>; From 35fd7af5f7b394749ad1030f72df345ae880318b Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Fri, 12 Apr 2024 15:02:00 +0300 Subject: [PATCH 832/969] arm64: dts: ti: k3-am62a: Disable USB LPM As per AM62A TRM [1] USB Link Power Management (LPM) feature is not supported. Disable it else it may cause enumeration failure on some devices. > 4.9.2.1 USB2SS Unsupported Features > The following features are not supported on this family of devices: > ... > - USB 2.0 ECN: Link Power Management (LPM) > ... [1] - https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Roger Quadros Reviewed-by: Ravi Gunasekaran Link: https://lore.kernel.org/r/20240412-for-v6-10-am62-usb-typec-dt-v7-3-93b827adf97e@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 31fc59b02f21..3fd59283eafe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -622,6 +622,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; @@ -646,6 +648,8 @@ interrupt-names = "host", "peripheral"; maximum-speed = "high-speed"; dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; }; }; From 2870e137ac66f03091e57358174acbb7f0df4506 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Mon, 15 Apr 2024 15:26:04 +0530 Subject: [PATCH 833/969] arm64: dts: ti: k3-j784s4-evm: Fix UART pin type and macro type Along fixing wkup UART TX pin as OUTPUT instead of INPUT, updating J784S4 macro for pin mux instead of J721S2. Fixes: 5dfbd1debc8c ("arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eeprom") Fixes: 6fa5d37a2f34 ("arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts") Signed-off-by: Udit Kumar Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240415095605.3547933-2-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 81fd7afac8c5..d511b25d62e3 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -343,16 +343,16 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; From de63748f0919cd3b04cad8556eddbb0c9dfc2c51 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Mon, 15 Apr 2024 15:26:05 +0530 Subject: [PATCH 834/969] arm64: dts: ti: k3-am69-sk: Fix UART pin type and macro type Along fixing wkup UART RTS and TX pins as OUTPUT instead of INPUT updating J784S4 macro for pin mux instead of J721S2. Fixes: 45299dd1991b ("arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uarts") Fixes: 08ae12b63750 ("arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eeprom") Signed-off-by: Udit Kumar Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240415095605.3547933-3-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 50de2a448a3a..d88651c297a2 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -517,18 +517,18 @@ wkup_uart0_pins_default: wkup-uart0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { bootph-all; pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ - J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; From 04c6dd3466d7c19315c20b349e543d41c4420817 Mon Sep 17 00:00:00 2001 From: Brandon Brnich Date: Mon, 15 Apr 2024 15:46:59 -0500 Subject: [PATCH 835/969] arm64: dts: ti: k3-am62a-main: Add Wave5 Video Encoder/Decoder Node This patch adds support for the Wave521cl on the AM62A-SK. Signed-off-by: Brandon Brnich Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20240415204659.798548-1-b-brnich@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 3fd59283eafe..e746a20b9a5d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1057,4 +1057,11 @@ #size-cells = <0>; }; }; + + vpu: video-codec@30210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x30210000 0x00 0x10000>; + clocks = <&k3_clks 204 2>; + power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; + }; }; From 954b585eace0bcb6070444fdbc8ee8c5148e3ee9 Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Fri, 19 Apr 2024 12:31:14 -0700 Subject: [PATCH 836/969] arm64: dts: ti: am64-phyboard-electra: Add overlay to enable a GPIO fan The phyBOARD-Electra has a GPIO fan header. This overlay enables the fan header and sets the fan to turn on at 65C. Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240419193114.3090084-1-nmorrisson@phytec.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 ++ .../k3-am642-phyboard-electra-gpio-fan.dtso | 50 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 9a722c2473fb..fd91cf40af6d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-pcie.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-hummingboard-t-usb3.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -131,6 +132,8 @@ k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo +k3-am642-phyboard-electra-gpio-fan-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-gpio-fan.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ @@ -174,6 +177,7 @@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am62p5-sk += -@ DTC_FLAGS_k3-am642-evm += -@ +DTC_FLAGS_k3-am642-phyboard-electra-rdk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-am68-sk-base-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso new file mode 100644 index 000000000000..5057658061b4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-gpio-fan.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2024 PHYTEC America LLC + * Author: Nathan Morrisson + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + fan: gpio-fan { + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 8600 1>; + gpios = <&main_gpio0 28 GPIO_ACTIVE_LOW>; + #cooling-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_fan_pins_default>; + }; +}; + +&main_pmx0 { + gpio_fan_pins_default: gpio-fan-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x070, PIN_OUTPUT, 7) /* (V18) GPMC0_AD13.GPIO0_28 */ + >; + }; +}; + +&thermal_zones { + main0_thermal: main0-thermal { + trips { + main0_thermal_trip0: main0-thermal-trip { + temperature = <65000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&main0_thermal_trip0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; From 01b4bd7bb36e253384792e842245153293f1404b Mon Sep 17 00:00:00 2001 From: Nathan Morrisson Date: Fri, 19 Apr 2024 12:35:52 -0700 Subject: [PATCH 837/969] arm64: dts: ti: Enable overlays for the am625-phyboard-lyra Add symbols when building the am625-phyboard-lyra-rdk DTB so overlays can be applied. Fixes: d8280f30a9cd ("arm64: dts: ti: am62-phyboard-lyra: Add overlay to enable a GPIO fan") Signed-off-by: Nathan Morrisson Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240419193552.3090343-1-nmorrisson@phytec.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index fd91cf40af6d..8fa0ae5b138a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -172,6 +172,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ +DTC_FLAGS_k3-am625-phyboard-lyra-rdk += -@ DTC_FLAGS_k3-am625-sk += -@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ From 8ffe9cb889f2b831a9d5bbb1f7ad42d30e31170f Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 23 Apr 2024 10:17:28 -0500 Subject: [PATCH 838/969] arm64: dts: ti: k3-am65-main: Fix sdhci node properties Update otap-del-sel properties as per datasheet [0]. Add missing clkbuf-sel and itap-del-sel values also as per datasheet [0]. Move clkbuf-sel and ti,trm-icp above the otap-del-sel properties so the sdhci nodes could be more uniform across platforms. [0] https://www.ti.com/lit/ds/symlink/am6548.pdf Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez Link: https://lore.kernel.org/r/20240423151732.3541894-2-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index de5b1b20a617..7f26e5bd72a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -435,6 +435,8 @@ interrupts = ; mmc-ddr-1_8v; mmc-hs200-1_8v; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; @@ -445,8 +447,7 @@ ti,otap-del-sel-ddr50 = <0x5>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; - ti,otap-del-sel-hs400 = <0x0>; - ti,trm-icp = <0x8>; + ti,itap-del-sel-ddr52 = <0x0>; dma-coherent; status = "disabled"; }; @@ -458,18 +459,22 @@ clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; clock-names = "clk_ahb", "clk_xin"; interrupts = ; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0x8>; ti,otap-del-sel-sdr104 = <0x7>; ti,otap-del-sel-ddr50 = <0x4>; ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; - ti,clkbuf-sel = <0x7>; - ti,trm-icp = <0x8>; + ti,itap-del-sel-legacy = <0xa>; + ti,itap-del-sel-sd-hs = <0x1>; + ti,itap-del-sel-sdr12 = <0xa>; + ti,itap-del-sel-sdr25 = <0x1>; dma-coherent; status = "disabled"; }; From 735ddec7a1ea836cdb69cd46c8334f2654dfc1fb Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Tue, 23 Apr 2024 10:17:29 -0500 Subject: [PATCH 839/969] arm64: dts: ti: k3-am65-main: Remove unused properties in sdhci nodes On AM65x platform, sdhci0 is for eMMC and sdhci1 is for SD. Remove the properties that are not applicable for each device. Fixes: eac99d38f861 ("arm64: dts: ti: k3-am654-main: Update otap-del-sel values") Fixes: d7600d070fb0 ("arm64: dts: ti: k3-am65-main: Add support for sdhci1") Signed-off-by: Judith Mendez Link: https://lore.kernel.org/r/20240423151732.3541894-3-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 7f26e5bd72a9..ed71561c5bd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -439,12 +439,6 @@ ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; ti,otap-del-sel-mmc-hs = <0x0>; - ti,otap-del-sel-sd-hs = <0x0>; - ti,otap-del-sel-sdr12 = <0x0>; - ti,otap-del-sel-sdr25 = <0x0>; - ti,otap-del-sel-sdr50 = <0x8>; - ti,otap-del-sel-sdr104 = <0x7>; - ti,otap-del-sel-ddr50 = <0x5>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; ti,itap-del-sel-ddr52 = <0x0>; @@ -462,15 +456,12 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0x8>; ti,otap-del-sel-sdr104 = <0x7>; ti,otap-del-sel-ddr50 = <0x4>; - ti,otap-del-sel-ddr52 = <0x4>; - ti,otap-del-sel-hs200 = <0x7>; ti,itap-del-sel-legacy = <0xa>; ti,itap-del-sel-sd-hs = <0x1>; ti,itap-del-sel-sdr12 = <0xa>; From 8f023012eb4aa9100ecb1457ab96ddcc54c5d373 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Tue, 23 Apr 2024 10:17:30 -0500 Subject: [PATCH 840/969] arm64: dts: ti: k3-am62a: Enable UHS mode support for SD cards Hook up required IO voltage regulators and drop no-1-8-v to support UHS modes on SD cards. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra Signed-off-by: Judith Mendez Link: https://lore.kernel.org/r/20240423151732.3541894-4-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index e746a20b9a5d..bf9c2d9c6439 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -573,7 +573,6 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - no-1-8-v; status = "disabled"; }; @@ -597,7 +596,6 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; - no-1-8-v; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index f241637a5642..fa43cd0b631e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -113,6 +113,20 @@ regulator-boot-on; }; + vddshv_sdio: regulator-5 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -342,6 +356,12 @@ AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ >; }; + + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; }; &mcu_pmx0 { @@ -580,6 +600,7 @@ /* SD/MMC */ status = "okay"; vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; From 31c40d25f5fc7c683b6dacbc86f106690e890b28 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 23 Apr 2024 10:17:31 -0500 Subject: [PATCH 841/969] arm64: dts: ti: k3-j721s2-main: Enable support for SDR104 speed mode According to TRM for J721S2, SDR104 speed mode is supported by the SoC but its capabilities were masked in device tree. Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card in J721S2 SoC. [+] Refer to : section 12.3.6.1.1 MMCSD Features, in J721S2 TRM - https://www.ti.com/lit/zip/spruj28 Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20240423151732.3541894-5-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 3cb06a7e4117..9ed6949b40e9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -768,8 +768,6 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; - /* Masking support for SDR104 capability */ - sdhci-caps-mask = <0x00000003 0x00000000>; status = "disabled"; }; From c28d88b2c298d74a2b47aaa10b5a1562992ed6dc Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Tue, 23 Apr 2024 10:17:32 -0500 Subject: [PATCH 842/969] arm64: dts: ti: k3-j784s4-main: Enable support for UHS mode Remove sdhci-caps-mask to enable support for SDR104 speed mode for SD card and remove no-1-8-v property so that SD card can work in any UHS-1 high speed mode it can support. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Bhavya Kapoor Signed-off-by: Dasnavis Sabiya Signed-off-by: Vignesh Raghavendra Signed-off-by: Judith Mendez Link: https://lore.kernel.org/r/20240423151732.3541894-6-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index d42f25cacf23..6a4554c6c9c1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -904,8 +904,6 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; - sdhci-caps-mask = <0x00000003 0x00000000>; - no-1-8-v; status = "disabled"; }; From 5ae1471df6b79b2ec26c973639961523147c7b66 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Mon, 22 Apr 2024 18:48:40 +0530 Subject: [PATCH 843/969] arm64: dts: ti: k3-j722s-evm: Enable UHS support for MMCSD Enable the UHS modes for MMCSD in J722S by removing the no-1-8-v property. Signed-off-by: Bhavya Kapoor Reviewed-by: Judith Mendez Link: https://lore.kernel.org/r/20240422131840.34642-1-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 78032caeb5fc..bf3c246d13d1 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -381,7 +381,6 @@ pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; status = "okay"; bootph-all; }; From 566bbb018e415fe5d7f960b8003915bf8d8d1414 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Fri, 1 Mar 2024 09:49:00 +0100 Subject: [PATCH 844/969] arm64: dts: ti: k3-am62-verdin: replace sleep-moci hog with regulator The Verdin family has a signal called sleep-moci which can be used to turn off peripherals on the carrier board when the SoM goes into suspend. So far we have hogged this signal, which means the peripherals are always on and it is not possible to add peripherals that depend on the sleep-moci to be on. With this change, we replace the hog with a regulator so that peripherals can add their own regulators that use the same gpio. Carrier boards that allow peripherals to be powered off in suspend can disable this regulator and implement their own regulator to control the sleep-moci. Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240301084901.16656-2-eichest@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 24 ++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index ff7cab0ff76c..2038c5e04639 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -138,6 +138,22 @@ vin-supply = <®_1v8>; }; + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + /* Verdin SD_1 Power Supply */ reg_sdhc1_vmmc: regulator-sdhci1 { compatible = "regulator-fixed"; @@ -985,14 +1001,6 @@ "", "", ""; - - verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { - gpio-hog; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <31 GPIO_ACTIVE_HIGH>; - line-name = "CTRL_SLEEP_MOCI#"; - output-high; - }; }; &main_gpio1 { From 3935fbc87ddebea5439f3ab6a78b1e83e976bf88 Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Fri, 1 Mar 2024 09:49:01 +0100 Subject: [PATCH 845/969] arm64: dts: ti: k3-am62-verdin-dahlia: support sleep-moci Previously, we had the sleep-moci pin set to always on. However, the Dahlia carrier board supports disabling the sleep-moci when the system is suspended to power down peripherals that support it. This reduces overall power consumption. This commit adds support for this feature by disabling the reg_force_sleep_moci regulator and adding a new regulator for the USB hub that can be turned off when the system is suspended. Signed-off-by: Stefan Eichenberger Reviewed-by: Francesco Dolcini Link: https://lore.kernel.org/r/20240301084901.16656-3-eichest@gmail.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 9202181fbd65..e8f4d136e5df 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -43,6 +43,15 @@ sound-dai = <&mcasp0>; }; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpio = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; }; /* Verdin ETHs */ @@ -184,6 +193,11 @@ status = "okay"; }; +/* Do not force CTRL_SLEEP_MOCI# always enabled */ +®_force_sleep_moci { + status = "disabled"; +}; + /* Verdin SD_1 */ &sdhci1 { status = "okay"; @@ -204,7 +218,15 @@ }; &usb1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + usb-hub@1 { + compatible = "usb424,2744"; + reg = <1>; + vdd-supply = <®_usb_hub>; + }; }; /* Verdin CTRL_WAKE1_MICO# */ From 62d514ff78488f1b86a537bdc6c31ab7e56906b6 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Wed, 24 Apr 2024 13:24:22 +0530 Subject: [PATCH 846/969] arm64: dts: ti: k3-j721s2: Add main esm address range Main ESM address change was missing for J721S2 SOC, So adding main ESM address mapping. Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20240424075423.1229127-2-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index be4502fe1c9d..568e6a04619d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -117,6 +117,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ From 1142985a62f1abd7a6e0b44df42f629c4da5c8f7 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Wed, 24 Apr 2024 13:24:23 +0530 Subject: [PATCH 847/969] arm64: dts: ti: k3-j784s4: Add main esm address range Main ESM address change was missing for J784S4 SOC, So adding main ESM address mapping. Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20240424075423.1229127-3-u-kumar1@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 6e2e92ffe745..da7368ed6b52 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -234,6 +234,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ From 8e558642d9ff3341be75426152e4eccc0f277b53 Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Thu, 25 Apr 2024 08:25:58 -0700 Subject: [PATCH 848/969] arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add USB-C The USB-C PD manages plug orientation, power delivery, and our endpoint for the USB interface. Add this node and include its endpoint. Configure USB0 for role-switching and wire it to our USB-C PD endpoint. Signed-off-by: Garrett Giordano Reviewed-by: Wadim Egorov Link: https://lore.kernel.org/r/20240425152558.485763-1-ggiordano@phytec.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-am625-phyboard-lyra-rdk.dts | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index d7b8aa607c8c..50d2573c840e 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -348,6 +348,24 @@ "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; }; + usb-pd@22 { + compatible = "ti,tps6598x"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + sii9022: bridge-hdmi@39 { compatible = "sil,sii9022"; reg = <0x39>; @@ -449,7 +467,13 @@ }; &usb0 { - dr_mode = "peripheral"; + usb-role-switch; + + port { + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; }; &usb1 { From 0b1133ee36ecbf3b02f69cc4e8a169f1b6019e40 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 5 Mar 2024 15:15:32 +0200 Subject: [PATCH 849/969] arm64: dts: ti: k3-am625-beagleplay: Fix Ethernet PHY RESET GPIOs The RESET GPIO pinmux should be part of MDIO bus node so that they can be in the right state before the PHY can be probed via MDIO bus scan. The GPIO pin should be setup with PIN_INPUT so that input circuitry is enabled in case software wants to check pin status. Without this, incorrect status is shown in /sys/kernel/debug/gpio. Add GPIO reset for the Gigabit Ethernet PHY. As per RTL8211F datasheet, reset assert width is 10ms and PHY registers can be access accessed after 50ms of reset deassert. Fixes: f5a731f0787f ("arm64: dts: ti: Add k3-am625-beagleplay") Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20240305-b4-for-v6-9-am65-beagleplay-ethernet-reset-v2-1-2bf463a7bf13@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 84977c1cc85d..18e3070a8683 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -289,6 +289,8 @@ pinctrl-single,pins = < AM62X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x015c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ + AM62X_IOPAD(0x018c, PIN_INPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ >; }; @@ -380,7 +382,6 @@ AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ - AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ >; @@ -594,6 +595,9 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&main_gpio0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; }; cpsw3g_phy1: ethernet-phy@1 { @@ -612,7 +616,7 @@ "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ "EEPROM_WP", /* 10 */ "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ - "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ + "CC1352P7_BOOT", "CC1352P7_RSTN", "GBE_RSTN", "", "", /* 13-17 */ "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ From b052c7fe3cb787282ab7e1fa088c794a1eb7fdb0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 24 Apr 2024 04:19:27 +0300 Subject: [PATCH 850/969] arm64: defconfig: select INTERCONNECT_QCOM_SM6115 as built-in Enable CONFIG_INTERCONNECT_QCOM_SM6115 as built-in to enable the interconnect driver for the SoC used on Qualcomm Robotics RB2 board. Building as built-in is required as on this platform interconnects are required to bring up the console. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240424-enable-sm6115-icc-v3-1-21c83be48f0e@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 971df4f7de00..1f95949d745e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1592,6 +1592,7 @@ CONFIG_INTERCONNECT_QCOM_SC8180X=y CONFIG_INTERCONNECT_QCOM_SC8280XP=y CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_INTERCONNECT_QCOM_SDX75=y +CONFIG_INTERCONNECT_QCOM_SM6115=y CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=y CONFIG_INTERCONNECT_QCOM_SM8350=m From b5f5fe4b317c0fbda725a44d9c92d97930ad68e9 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:43 +0100 Subject: [PATCH 851/969] arm64: dts: exynos: gs101: Add the hsi2 sysreg node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This has some configuration bits such as sharability that are required by UFS. Signed-off-by: Peter Griffin Reviewed-by: André Draszik Link: https://lore.kernel.org/r/20240430141445.2688499-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index e3b068c1a2c1..9f7635a7928e 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1320,6 +1320,12 @@ clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; From 4c65d7054b4ce8ceb30ba2b8aed90ceff6158d73 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:44 +0100 Subject: [PATCH 852/969] arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the ufs controller node and phy node for gs101. Signed-off-by: Peter Griffin Acked-by: André Draszik Link: https://lore.kernel.org/r/20240430141445.2688499-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9f7635a7928e..16e1c474e8dd 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1332,6 +1332,42 @@ interrupts = ; }; + ufs_0: ufs@14700000 { + compatible = "google,gs101-ufs"; + reg = <0x14700000 0x200>, + <0x14701100 0x200>, + <0x14780000 0xa000>, + <0x14600000 0x100>; + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>, + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>, + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + clock-names = "core_clk", "sclk_unipro_main", "fmp", + "aclk", "pclk", "sysreg"; + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + pinctrl-names = "default"; + phys = <&ufs_0_phy>; + phy-names = "ufs-phy"; + samsung,sysreg = <&sysreg_hsi2 0x710>; + status = "disabled"; + }; + + ufs_0_phy: phy@14704000 { + compatible = "google,gs101-ufs-phy"; + reg = <0x14704000 0x3000>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&ext_24_5m>; + clock-names = "ref_clk"; + status = "disabled"; + }; + cmu_apm: clock-controller@17400000 { compatible = "google,gs101-cmu-apm"; reg = <0x17400000 0x8000>; From aaafb21e8190cd2bc8cadf3e0f017bc5c11bb109 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 30 Apr 2024 15:14:45 +0100 Subject: [PATCH 853/969] arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs regulator Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node. ufs regulator is a stub until full s2mpg11 slave pmic support is added. The gpio defined is for the BOOTLD0 (gs101) signal connected to UFS_EN(s2mpg11) gpio enabled voltage rail for UFS. Signed-off-by: Peter Griffin Link: https://lore.kernel.org/r/20240430141445.2688499-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 03b2a6fdfdc4..5e8ffe065081 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -59,6 +59,15 @@ compatible = "regulator-fixed"; regulator-name = "placeholder_reg"; }; + + /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ + ufs_0_fixed_vcc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; }; &ext_24_5m { @@ -112,6 +121,15 @@ status = "okay"; }; +&ufs_0 { + status = "okay"; + vcc-supply = <&ufs_0_fixed_vcc_reg>; +}; + +&ufs_0_phy { + status = "okay"; +}; + &usbdrd31 { status = "okay"; vdd10-supply = <®_placeholder>; From 9ecaa2e94e602a3cbcbfe182535f6297f7630b98 Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Tue, 30 Apr 2024 17:58:51 +0200 Subject: [PATCH 854/969] s390: Relocate vmlinux ELF data to virtual address space Currently kernel image relocation tables and other ELF data are set to base zero. Since kernel virtual and physical address spaces are uncoupled the kernel is mapped at the top of the virtual address space, hence making the information contained in vmlinux ELF tables inconsistent. That does not pose any issue with regard to the kernel booting and operation, but makes it difficult to use a generated vmlinux with some debugging tools (e.g. gdb). Relocate vmlinux image base address from zero to a base address in the virtual address space. It is the address that kernel is mapped to in cases KASLR is disabled. The vmlinux ELF header before and after this change looks like this: Elf file type is EXEC (Executable file) Entry point 0x100000 There are 3 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000001000 0x0000000000100000 0x0000000000100000 0x0000000001323378 0x0000000001323378 R E 0x1000 LOAD 0x0000000001325000 0x0000000001424000 0x0000000001424000 0x00000000003a4200 0x000000000048fdb8 RWE 0x1000 NOTE 0x00000000012a33b0 0x00000000013a23b0 0x00000000013a23b0 0x0000000000000054 0x0000000000000054 0x4 Elf file type is EXEC (Executable file) Entry point 0x3ffe0000000 There are 3 program headers, starting at offset 64 Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align LOAD 0x0000000000001000 0x000003ffe0000000 0x000003ffe0000000 0x0000000001323378 0x0000000001323378 R E 0x1000 LOAD 0x0000000001325000 0x000003ffe1324000 0x000003ffe1324000 0x00000000003a4200 0x000000000048fdb8 RWE 0x1000 NOTE 0x00000000012a33b0 0x000003ffe12a23b0 0x000003ffe12a23b0 0x0000000000000054 0x0000000000000054 0x4 Suggested-by: Vasily Gorbik Acked-by: Heiko Carstens Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/page.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 224ff9d433ea..7880b7b3173e 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -276,8 +276,8 @@ static inline unsigned long virt_to_pfn(const void *kaddr) #define AMODE31_SIZE (3 * PAGE_SIZE) #define KERNEL_IMAGE_SIZE (512 * 1024 * 1024) -#define __START_KERNEL 0x100000 -#define __NO_KASLR_START_KERNEL CONFIG_KERNEL_IMAGE_BASE +#define __START_KERNEL CONFIG_KERNEL_IMAGE_BASE +#define __NO_KASLR_START_KERNEL __START_KERNEL #define __NO_KASLR_END_KERNEL (__NO_KASLR_START_KERNEL + KERNEL_IMAGE_SIZE) #endif /* _S390_PAGE_H */ From cc4edb92f55aea6eb26930087c8075bdf9967b1b Mon Sep 17 00:00:00 2001 From: Nina Schoetterl-Glausch Date: Mon, 29 Apr 2024 19:15:12 +0200 Subject: [PATCH 855/969] KVM: s390: vsie: Use virt_to_phys for crypto control block The address of the crypto control block in the (shadow) SIE block is absolute/physical. Convert from virtual to physical when shadowing the guest's control block during VSIE. Signed-off-by: Nina Schoetterl-Glausch Reviewed-by: Christian Borntraeger Acked-by: Alexander Gordeev Link: https://lore.kernel.org/r/20240429171512.879215-1-nsg@linux.ibm.com Signed-off-by: Alexander Gordeev --- arch/s390/kvm/vsie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/kvm/vsie.c b/arch/s390/kvm/vsie.c index d8527a046cf7..c9ecae830634 100644 --- a/arch/s390/kvm/vsie.c +++ b/arch/s390/kvm/vsie.c @@ -362,7 +362,7 @@ end: case -EACCES: return set_validity_icpt(scb_s, 0x003CU); } - scb_s->crycbd = ((__u32)(__u64) &vsie_page->crycb) | CRYCB_FORMAT2; + scb_s->crycbd = (u32)virt_to_phys(&vsie_page->crycb) | CRYCB_FORMAT2; return 0; } From f329598c27332ff9e85e5551bed3cab280971678 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 25 Apr 2024 16:00:59 +0530 Subject: [PATCH 856/969] arm64: dts: ti: Fix csi2-dual-imx219 dtb names Fix the output filenames of the combined device tree blobs generated by applying *-csi2-dual-imx219-* overlays on the base dtbs during compile test. Fixes: f767eb918096 ("arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219") Signed-off-by: Jai Luthra Reviewed-by: Aradhya Bhatia Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/104fbdbc-a3f6-091a-72f4-17d4fa24ad92@ti.com/ Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 8fa0ae5b138a..2c327cc320cf 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -164,10 +164,10 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ - k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ - k3-am69-sk-csi2-dual-imx219-dtbs \ + k3-am68-sk-base-board-csi2-dual-imx219.dtb \ + k3-am69-sk-csi2-dual-imx219.dtb \ k3-j721e-evm-pcie0-ep.dtb \ - k3-j721e-sk-csi2-dual-imx219-dtbs \ + k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb # Enable support for device-tree overlays From 3170a2c906c61407d725e9022b6225c5ff062d9f Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Mon, 29 Apr 2024 21:50:47 +0530 Subject: [PATCH 857/969] arm64: dts: qcom: sc8280xp: Add USB DWC3 Multiport controller Add USB and DWC3 node for tertiary port of SC8280 along with Multiport interrupts and PHYs. Signed-off-by: Krishna Kurapati Reviewed-by: Johan Hovold Tested-by: Johan Hovold Link: https://lore.kernel.org/r/20240429162048.2133512-2-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0403811264d8..9a00863b3d41 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3423,6 +3423,88 @@ interrupts = ; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 127 IRQ_TYPE_EDGE_BOTH>, + <&pdc 126 IRQ_TYPE_EDGE_BOTH>, + <&pdc 129 IRQ_TYPE_EDGE_BOTH>, + <&pdc 128 IRQ_TYPE_EDGE_BOTH>, + <&pdc 131 IRQ_TYPE_EDGE_BOTH>, + <&pdc 130 IRQ_TYPE_EDGE_BOTH>, + <&pdc 133 IRQ_TYPE_EDGE_BOTH>, + <&pdc 132 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "pwr_event_1", "pwr_event_2", + "pwr_event_3", "pwr_event_4", + "hs_phy_1", "hs_phy_2", + "hs_phy_3", "hs_phy_4", + "dp_hs_phy_1", "dm_hs_phy_1", + "dp_hs_phy_2", "dm_hs_phy_2", + "dp_hs_phy_3", "dm_hs_phy_3", + "dp_hs_phy_4", "dm_hs_phy_4", + "ss_phy_1", "ss_phy_2"; + + power-domains = <&gcc USB30_MP_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-0", "usb3-0", + "usb2-1", "usb3-1", + "usb2-2", + "usb2-3"; + dr_mode = "host"; + }; + }; + usb_0: usb@a6f8800 { compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; From eb24bd3c593fad7bd88cb7e7db683014c125e23b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 1 May 2024 08:56:41 +0200 Subject: [PATCH 858/969] arm64: dts: qcom: sc8280xp-x13s: enable USB MP and fingerprint reader Enable the multiport USB controller to which the fingerprint reader in the X13s power button is connected. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20240501065641.965-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index f325066e24d8..e937732abede 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -416,6 +416,13 @@ regulator-always-on; }; + vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + vreg_l3b: ldo3 { regulator-name = "vreg_l3b"; regulator-min-microvolt = <1200000>; @@ -466,6 +473,13 @@ regulator-initial-mode = ; }; + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + vreg_l12c: ldo12 { regulator-name = "vreg_l12c"; regulator-min-microvolt = <1800000>; @@ -499,6 +513,13 @@ vdd-l6-l9-l10-supply = <&vreg_s12b>; vdd-l8-supply = <&vreg_s12b>; + vreg_l2d: ldo2 { + regulator-name = "vreg_l2d"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + vreg_l3d: ldo3 { regulator-name = "vreg_l3d"; regulator-min-microvolt = <1200000>; @@ -527,12 +548,26 @@ regulator-initial-mode = ; }; + vreg_l8d: ldo8 { + regulator-name = "vreg_l8d"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + vreg_l9d: ldo9 { regulator-name = "vreg_l9d"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; + + vreg_l10d: ldo10 { + regulator-name = "vreg_l10d"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; }; }; @@ -1162,6 +1197,56 @@ remote-endpoint = <&pmic_glink_con1_hs>; }; +&usb_2 { + status = "okay"; +}; + +&usb_2_hsphy0 { + vdda-pll-supply = <&vreg_l1b>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l7d>; + + status = "okay"; +}; + +&usb_2_hsphy1 { + vdda-pll-supply = <&vreg_l8d>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l7d>; + + status = "okay"; +}; + +&usb_2_hsphy2 { + vdda-pll-supply = <&vreg_l10d>; + vdda18-supply = <&vreg_l8c>; + vdda33-supply = <&vreg_l2d>; + + status = "okay"; +}; + +&usb_2_hsphy3 { + vdda-pll-supply = <&vreg_l10d>; + vdda18-supply = <&vreg_l8c>; + vdda33-supply = <&vreg_l2d>; + + status = "okay"; +}; + +&usb_2_qmpphy0 { + vdda-phy-supply = <&vreg_l1b>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&usb_2_qmpphy1 { + vdda-phy-supply = <&vreg_l8d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + &vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; From dff55f66aaba931c71ba5f20906f0a75c4df1da8 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 1 May 2024 09:50:05 +0200 Subject: [PATCH 859/969] dt-bindings: soc: qcom,wcnss: fix bluetooth address example The 'local-bd-address' property is used to pass a unique Bluetooth device address from the boot firmware to the kernel and should otherwise be left unset. Update the example to reduce the risk that a non-zero address will be used by default in some devicetree. Signed-off-by: Johan Hovold Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240501075005.4588-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml index 74bb92e31554..fd6db0ca98eb 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml @@ -116,8 +116,8 @@ examples: bluetooth { compatible = "qcom,wcnss-bt"; - /* BD address 00:11:22:33:44:55 */ - local-bd-address = [ 55 44 33 22 11 00 ]; + /* Updated by boot firmware (little-endian order) */ + local-bd-address = [ 00 00 00 00 00 00 ]; }; wifi { From f5f390a77f18eaeb2c93211a1b7c5e66b5acd423 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 1 May 2024 09:52:01 +0200 Subject: [PATCH 860/969] arm64: dts: qcom: qcs404: fix bluetooth device address The 'local-bd-address' property is used to pass a unique Bluetooth device address from the boot firmware to the kernel and should otherwise be left unset so that the OS can prevent the controller from being used until a valid address has been provided through some other means (e.g. using btmgmt). Fixes: 60f77ae7d1c1 ("arm64: dts: qcom: qcs404-evb: Enable uart3 and add Bluetooth") Cc: stable@vger.kernel.org # 5.10 Signed-off-by: Johan Hovold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20240501075201.4732-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 10655401528e..a22b4501ce1e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -62,7 +62,7 @@ vddrf-supply = <&vreg_l1_1p3>; vddch0-supply = <&vdd_ch0_3p3>; - local-bd-address = [ 02 00 00 00 5a ad ]; + local-bd-address = [ 00 00 00 00 00 00 ]; max-speed = <3200000>; }; From 9329933699b32d467a99befa20415c4b2172389a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 Apr 2024 20:38:57 -0700 Subject: [PATCH 861/969] soc: qcom: pmic_glink: Make client-lock non-sleeping The recently introduced commit '635ce0db8956 ("soc: qcom: pmic_glink: don't traverse clients list without a lock")' ensured that the clients list is not modified while traversed. But the callback is made from the GLINK IRQ handler and as such this mutual exclusion can not be provided by a (sleepable) mutex. Replace the mutex with a spinlock. Fixes: 635ce0db8956 ("soc: qcom: pmic_glink: don't traverse clients list without a lock") Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240430-pmic-glink-sleep-while-atomic-v1-1-88fb493e8545@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index e85a12ec2aab..823fd108fa03 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -11,6 +11,7 @@ #include #include #include +#include enum { PMIC_GLINK_CLIENT_BATT = 0, @@ -36,7 +37,7 @@ struct pmic_glink { unsigned int pdr_state; /* serializing clients list updates */ - struct mutex client_lock; + spinlock_t client_lock; struct list_head clients; }; @@ -58,10 +59,11 @@ static void _devm_pmic_glink_release_client(struct device *dev, void *res) { struct pmic_glink_client *client = (struct pmic_glink_client *)res; struct pmic_glink *pg = client->pg; + unsigned long flags; - mutex_lock(&pg->client_lock); + spin_lock_irqsave(&pg->client_lock, flags); list_del(&client->node); - mutex_unlock(&pg->client_lock); + spin_unlock_irqrestore(&pg->client_lock, flags); } struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, @@ -72,6 +74,7 @@ struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, { struct pmic_glink_client *client; struct pmic_glink *pg = dev_get_drvdata(dev->parent); + unsigned long flags; client = devres_alloc(_devm_pmic_glink_release_client, sizeof(*client), GFP_KERNEL); if (!client) @@ -84,12 +87,12 @@ struct pmic_glink_client *devm_pmic_glink_register_client(struct device *dev, client->priv = priv; mutex_lock(&pg->state_lock); - mutex_lock(&pg->client_lock); + spin_lock_irqsave(&pg->client_lock, flags); list_add(&client->node, &pg->clients); client->pdr_notify(client->priv, pg->client_state); - mutex_unlock(&pg->client_lock); + spin_unlock_irqrestore(&pg->client_lock, flags); mutex_unlock(&pg->state_lock); devres_add(dev, client); @@ -112,6 +115,7 @@ static int pmic_glink_rpmsg_callback(struct rpmsg_device *rpdev, void *data, struct pmic_glink_client *client; struct pmic_glink_hdr *hdr; struct pmic_glink *pg = dev_get_drvdata(&rpdev->dev); + unsigned long flags; if (len < sizeof(*hdr)) { dev_warn(pg->dev, "ignoring truncated message\n"); @@ -120,12 +124,12 @@ static int pmic_glink_rpmsg_callback(struct rpmsg_device *rpdev, void *data, hdr = data; - mutex_lock(&pg->client_lock); + spin_lock_irqsave(&pg->client_lock, flags); list_for_each_entry(client, &pg->clients, node) { if (client->id == le32_to_cpu(hdr->owner)) client->cb(data, len, client->priv); } - mutex_unlock(&pg->client_lock); + spin_unlock_irqrestore(&pg->client_lock, flags); return 0; } @@ -165,6 +169,7 @@ static void pmic_glink_state_notify_clients(struct pmic_glink *pg) { struct pmic_glink_client *client; unsigned int new_state = pg->client_state; + unsigned long flags; if (pg->client_state != SERVREG_SERVICE_STATE_UP) { if (pg->pdr_state == SERVREG_SERVICE_STATE_UP && pg->ept) @@ -175,10 +180,10 @@ static void pmic_glink_state_notify_clients(struct pmic_glink *pg) } if (new_state != pg->client_state) { - mutex_lock(&pg->client_lock); + spin_lock_irqsave(&pg->client_lock, flags); list_for_each_entry(client, &pg->clients, node) client->pdr_notify(client->priv, new_state); - mutex_unlock(&pg->client_lock); + spin_unlock_irqrestore(&pg->client_lock, flags); pg->client_state = new_state; } } @@ -265,7 +270,7 @@ static int pmic_glink_probe(struct platform_device *pdev) pg->dev = &pdev->dev; INIT_LIST_HEAD(&pg->clients); - mutex_init(&pg->client_lock); + spin_lock_init(&pg->client_lock); mutex_init(&pg->state_lock); match_data = (unsigned long *)of_device_get_match_data(&pdev->dev); From 4b34d4c25da289712d9a5bd5bac5888f099cbc5c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 Apr 2024 19:33:12 -0700 Subject: [PATCH 862/969] firmware: qcom: uefisecapp: Allow on sc8180x Primus and Flex 5G Testing indicates that qseecom and uefisecapp are working on both the SC8180X Primus and Lenovo Flex 5G, providing EFI variable access. Add the two to the allow list. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240430-uefisecapp-allowlist-sc8180x-v1-1-1a626ea9c5f1@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 5ff62f57aa55..9cb02cd94c04 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1671,7 +1671,9 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_send); + any potential issues with this, only allow validated machines for now. */ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { + { .compatible = "lenovo,flex-5g" }, { .compatible = "lenovo,thinkpad-x13s", }, + { .compatible = "qcom,sc8180x-primus" }, { } }; From 844776cb65a77ef27bfba2220e285940b714ae4e Mon Sep 17 00:00:00 2001 From: linke li Date: Sat, 27 Apr 2024 16:51:54 +0800 Subject: [PATCH 863/969] mm/slub: mark racy access on slab->freelist In deactivate_slab(), slab->freelist can be changed concurrently. Mark data race on slab->freelist as benign using READ_ONCE. This patch is aimed at reducing the number of benign races reported by KCSAN in order to focus future debugging effort on harmful races. Signed-off-by: linke li Signed-off-by: Vlastimil Babka --- mm/slub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/slub.c b/mm/slub.c index 3aa12b9b323d..88d3dcdfa45d 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -2806,7 +2806,7 @@ static void deactivate_slab(struct kmem_cache *s, struct slab *slab, struct slab new; struct slab old; - if (slab->freelist) { + if (READ_ONCE(slab->freelist)) { stat(s, DEACTIVATE_REMOTE_FREES); tail = DEACTIVATE_TO_TAIL; } From 5c04a5b065e97dd331dba67da9896897fced3bee Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 30 Apr 2024 14:18:54 -0500 Subject: [PATCH 864/969] arm64: dts: Add/fix /memory node unit-addresses '/memory' nodes always have a 'reg' property, and therefore should have a unit-address with just plain hex (i.e. no commas). Fix all the arm64 '/memory' nodes. It's possible that some bootloader depends on /memory (arm32 ATAG to DT code does for example). If so, the memory node should be commented with that requirement. Signed-off-by: Rob Herring (Arm) Reviewed-by: Florian Fainelli Reviewed-by: Heiko Stuebner Reviewed-by: Bryan O'Donoghue Reviewed-by: Chanho Min Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240430191856.874600-2-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/actions/s700-cubieboard7.dts | 2 +- arch/arm64/boot/dts/apm/apm-merlin.dts | 2 +- arch/arm64/boot/dts/apm/apm-mustang.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts | 2 +- arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 2 +- arch/arm64/boot/dts/lg/lg1312-ref.dts | 2 +- arch/arm64/boot/dts/lg/lg1313-ref.dts | 2 +- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 2 +- arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3368-r88.dts | 2 +- arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts index 63e375cd9eb4..bd54b5165129 100644 --- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts +++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts @@ -24,7 +24,7 @@ reg = <0x0 0x0 0x0 0x80000000>; }; - memory@1,e0000000 { + memory@1e0000000 { device_type = "memory"; reg = <0x1 0xe0000000 0x0 0x0>; }; diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index 2e8069002ec1..6e05cf1a3df6 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -15,7 +15,7 @@ chosen { }; - memory { + memory@100000000 { device_type = "memory"; reg = < 0x1 0x00000000 0x0 0x80000000 >; }; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index 033e10e12b18..e7644cddf06f 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -15,7 +15,7 @@ chosen { }; - memory { + memory@100000000 { device_type = "memory"; reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index dec5a110f1e8..f43cfe66b6af 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -50,7 +50,7 @@ bootargs = "earlycon=uart8250,mmio32,0x66130000"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index 1d314f17bbdd..c50df1d02797 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -47,7 +47,7 @@ bootargs = "earlycon=uart8250,mmio32,0x66130000"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000001 0x00000000>; }; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts index d005e1e79c3d..89fc4107a0c4 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts @@ -14,7 +14,7 @@ model = "Cavium ThunderX2 CN99XX"; compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ diff --git a/arch/arm64/boot/dts/lg/lg1312-ref.dts b/arch/arm64/boot/dts/lg/lg1312-ref.dts index 260a2c5b19e5..cdd10f138098 100644 --- a/arch/arm64/boot/dts/lg/lg1312-ref.dts +++ b/arch/arm64/boot/dts/lg/lg1312-ref.dts @@ -22,7 +22,7 @@ serial2 = &uart2; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/lg/lg1313-ref.dts b/arch/arm64/boot/dts/lg/lg1313-ref.dts index e89ae853788a..6ace977ff4cf 100644 --- a/arch/arm64/boot/dts/lg/lg1313-ref.dts +++ b/arch/arm64/boot/dts/lg/lg1313-ref.dts @@ -22,7 +22,7 @@ serial2 = &uart2; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index a5ab2bc0f835..eeceb5b292a8 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -16,7 +16,7 @@ stdout-path = &serial0; }; - memory { + memory@0 { reg = <0x0 0x0 0x0 0x40000000>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 9ebb7369256e..2e5b6b2c1f56 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -25,7 +25,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0xc0000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 1b8379ba87f9..34e2f80514a3 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -16,7 +16,7 @@ stdout-path = "serial0"; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi index b48b98c13705..e5c0dbf794ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi @@ -17,7 +17,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts index dcee2e28916f..23ae2d9de382 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts @@ -21,7 +21,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts index b16b7ca02379..7f14206d53c3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts @@ -21,7 +21,7 @@ stdout-path = "serial2:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts index ed8aee9e1828..1ce3cbbd9668 100644 --- a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts @@ -24,7 +24,7 @@ spi0 = &adi_bus; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x60000000>, <0x1 0x80000000 0 0x60000000>; From 306c4ac9896b07b8872293eb224058ff83f81fac Mon Sep 17 00:00:00 2001 From: Hyunmin Lee Date: Wed, 24 Apr 2024 23:04:21 +0900 Subject: [PATCH 865/969] mm/slub: create kmalloc 96 and 192 caches regardless cache size order For SLAB the kmalloc caches needed to be created in ascending sizes in order. However, the constraint is not necessary anymore because SLAB has been removed and SLUB doesn't need to comply with the constraint. Thus, kmalloc 96 and 192 caches can be created after the other size kmalloc caches are created instead of checking every time to find their order to be created. Also, this change could prevent engineers from being confused by the removed constraint. Signed-off-by: Hyunmin Lee Co-developed-by: Jeungwoo Yoo Signed-off-by: Jeungwoo Yoo Co-developed-by: Sangyun Kim Signed-off-by: Sangyun Kim Cc: Hyeonggon Yoo <42.hyeyoo@gmail.com> Cc: Gwan-gyeong Mun Reviewed-by: Christoph Lameter Acked-by: David Rientjes Signed-off-by: Vlastimil Babka --- mm/slab_common.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/mm/slab_common.c b/mm/slab_common.c index 67c03d6bd26c..7cfdcc8cbf5f 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -916,21 +916,16 @@ void __init create_kmalloc_caches(void) * Including KMALLOC_CGROUP if CONFIG_MEMCG_KMEM defined */ for (type = KMALLOC_NORMAL; type < NR_KMALLOC_TYPES; type++) { + /* Caches that are NOT of the two-to-the-power-of size. */ + if (KMALLOC_MIN_SIZE <= 32 && !kmalloc_caches[type][1]) + new_kmalloc_cache(1, type); + if (KMALLOC_MIN_SIZE <= 64 && !kmalloc_caches[type][2]) + new_kmalloc_cache(2, type); + + /* Caches that are of the two-to-the-power-of size. */ for (i = KMALLOC_SHIFT_LOW; i <= KMALLOC_SHIFT_HIGH; i++) { if (!kmalloc_caches[type][i]) new_kmalloc_cache(i, type); - - /* - * Caches that are not of the two-to-the-power-of size. - * These have to be created immediately after the - * earlier power of two caches - */ - if (KMALLOC_MIN_SIZE <= 32 && i == 6 && - !kmalloc_caches[type][1]) - new_kmalloc_cache(1, type); - if (KMALLOC_MIN_SIZE <= 64 && i == 7 && - !kmalloc_caches[type][2]) - new_kmalloc_cache(2, type); } } #ifdef CONFIG_RANDOM_KMALLOC_CACHES From 7338999ca3468404f547b1540211114cbdb26d06 Mon Sep 17 00:00:00 2001 From: Hyunmin Lee Date: Wed, 24 Apr 2024 23:04:22 +0900 Subject: [PATCH 866/969] mm/slub: remove the check for NULL kmalloc_caches If the same size kmalloc cache already exists, it should not be created again. So there is the check for NULL kmalloc_caches before calling the kmalloc creation function. However, new_kmalloc_cache() itself checks NULL kmalloc_cahces before cache creation. Therefore, the NULL check is not necessary in this function. Signed-off-by: Hyunmin Lee Co-developed-by: Jeungwoo Yoo Signed-off-by: Jeungwoo Yoo Co-developed-by: Sangyun Kim Signed-off-by: Sangyun Kim Cc: Hyeonggon Yoo <42.hyeyoo@gmail.com> Cc: Gwan-gyeong Mun Reviewed-by: Christoph Lameter Acked-by: David Rientjes Signed-off-by: Vlastimil Babka --- mm/slab_common.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/mm/slab_common.c b/mm/slab_common.c index 7cfdcc8cbf5f..c37f8c41ffb0 100644 --- a/mm/slab_common.c +++ b/mm/slab_common.c @@ -917,16 +917,14 @@ void __init create_kmalloc_caches(void) */ for (type = KMALLOC_NORMAL; type < NR_KMALLOC_TYPES; type++) { /* Caches that are NOT of the two-to-the-power-of size. */ - if (KMALLOC_MIN_SIZE <= 32 && !kmalloc_caches[type][1]) + if (KMALLOC_MIN_SIZE <= 32) new_kmalloc_cache(1, type); - if (KMALLOC_MIN_SIZE <= 64 && !kmalloc_caches[type][2]) + if (KMALLOC_MIN_SIZE <= 64) new_kmalloc_cache(2, type); /* Caches that are of the two-to-the-power-of size. */ - for (i = KMALLOC_SHIFT_LOW; i <= KMALLOC_SHIFT_HIGH; i++) { - if (!kmalloc_caches[type][i]) - new_kmalloc_cache(i, type); - } + for (i = KMALLOC_SHIFT_LOW; i <= KMALLOC_SHIFT_HIGH; i++) + new_kmalloc_cache(i, type); } #ifdef CONFIG_RANDOM_KMALLOC_CACHES random_kmalloc_seed = get_random_u64(); From dfce05c82fb1a16c389e8fb2445dcd0dea7c1a72 Mon Sep 17 00:00:00 2001 From: Federico Vaga Date: Sat, 16 Mar 2024 23:54:00 +0100 Subject: [PATCH 867/969] doc:it_IT: align Italian documentation Translation for the following patches commit 6e55b1cbf05d ("docs: try to encourage (netdev?) reviewers") commit e49ad8530de9 ("CREDITS, MAINTAINERS, docs/process/howto: Update man-pages' maintainer") commit 44ac5abac86b ("Documentation/security-bugs: move from admin-guide/ to process/") commit 5a602de99797 ("Add .editorconfig file for basic formatting") commit 129027b78c49 ("docs: deprecated.rst: Update an example") commit efc0a7cfe9ec ("Docs/process/changes: Consolidate NFS-utils update links") commit 383f30882197 ("Docs/process/changes: Replace http:// with https://") commit 80fe9e51510b ("rust: upgrade to Rust 1.74.1") commit c584476d477e ("doc: Add tar requirement to changes.rst") commit b230235b3865 ("docs: Set minimal gtags / GNU GLOBAL version to 6.6.5") commit 3e893e16af55 ("docs: Raise the minimum Sphinx requirement to 2.4.4") commit 08ab786556ff ("rust: bindgen: upgrade to 0.65.1") commit 185ea7676ef3 ("Documentation: coding-style: Update syntax highlighting for code-blocks") commit 932be49b71e7 ("Documentation: coding-style: Fix indentation in code-blocks") commit 5c7944ca7b13 ("coding-style: Add guidance to prefer dev_dbg") commit c15ec3d1a287 ("Documentation: doc-guide: use '%' constant indicator in Return: examples") commit 329ac9af902e ("docs: submitting-patches: Discuss interleaved replies") commit 5382774515d4 ("(docs-next) A reworked process/index.rst") Signed-off-by: Federico Vaga Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240316225400.22590-1-federico.vaga@vaga.pv.it --- .../it_IT/doc-guide/kernel-doc.rst | 10 +-- .../translations/it_IT/process/2.Process.rst | 9 ++- .../translations/it_IT/process/4.Coding.rst | 4 ++ .../it_IT/process/7.AdvancedTopics.rst | 19 ++++++ .../translations/it_IT/process/changes.rst | 36 ++++++---- .../it_IT/process/coding-style.rst | 12 +++- .../translations/it_IT/process/deprecated.rst | 2 +- .../translations/it_IT/process/howto.rst | 6 +- .../translations/it_IT/process/index.rst | 68 ++++++++++++++++--- .../security-bugs.rst | 0 .../it_IT/process/stable-kernel-rules.rst | 2 +- .../it_IT/process/submitting-patches.rst | 27 ++++++++ 12 files changed, 156 insertions(+), 39 deletions(-) rename Documentation/translations/it_IT/{admin-guide => process}/security-bugs.rst (100%) diff --git a/Documentation/translations/it_IT/doc-guide/kernel-doc.rst b/Documentation/translations/it_IT/doc-guide/kernel-doc.rst index 5cece223b46b..74057d203539 100644 --- a/Documentation/translations/it_IT/doc-guide/kernel-doc.rst +++ b/Documentation/translations/it_IT/doc-guide/kernel-doc.rst @@ -180,9 +180,9 @@ Il valore di ritorno, se c'è, viene descritto in una sezione dedicata di nome se provate a formattare bene il vostro testo come nel seguente esempio:: * Return: - * 0 - OK - * -EINVAL - invalid argument - * -ENOMEM - out of memory + * %0 - OK + * %-EINVAL - invalid argument + * %-ENOMEM - out of memory le righe verranno unite e il risultato sarà:: @@ -192,8 +192,8 @@ Il valore di ritorno, se c'è, viene descritto in una sezione dedicata di nome utilizzare una lista ReST, ad esempio:: * Return: - * * 0 - OK to runtime suspend the device - * * -EBUSY - Device should not be runtime suspended + * * %0 - OK to runtime suspend the device + * * %-EBUSY - Device should not be runtime suspended #) Se il vostro testo ha delle righe che iniziano con una frase seguita dai due punti, allora ognuna di queste frasi verrà considerata come il nome diff --git a/Documentation/translations/it_IT/process/2.Process.rst b/Documentation/translations/it_IT/process/2.Process.rst index 25cd00351c03..0a62c0f33faf 100644 --- a/Documentation/translations/it_IT/process/2.Process.rst +++ b/Documentation/translations/it_IT/process/2.Process.rst @@ -462,9 +462,12 @@ linux-kernel: di far domande. Molti sviluppatori possono divenire impazienti con le persone che chiaramente non hanno svolto i propri compiti a casa. -- Evitate il *top-posting* (cioè la pratica di mettere la vostra risposta sopra - alla frase alla quale state rispondendo). Ciò renderebbe la vostra risposta - difficile da leggere e genera scarsa impressione. +- Rispondete sotto alla porzione di righe citate, così da dare un contesto alle + vostre risposte, e quindi renderle più leggibili (in altre parole, evitate di + rispondere in cima, ovvero prima del testo citato). Per maggiori dettagli + leggete :ref:`Documentation/translations/it_IT/process/submitting-patches.rst + `. + - Chiedete nella lista di discussione corretta. Linux-kernel può essere un punto di incontro generale, ma non è il miglior posto dove trovare diff --git a/Documentation/translations/it_IT/process/4.Coding.rst b/Documentation/translations/it_IT/process/4.Coding.rst index 54fd255b77d0..ec874a8dfb9d 100644 --- a/Documentation/translations/it_IT/process/4.Coding.rst +++ b/Documentation/translations/it_IT/process/4.Coding.rst @@ -72,6 +72,10 @@ compiti del genere. Consultate il file :ref:`Documentation/translations/it_IT/process/clang-format.rst ` per maggiori dettagli +Se utilizzate un programma compatibile con EditorConfig, allora alcune +configurazioni basilari come l'indentazione e la fine delle righe verranno +applicate automaticamente. Per maggiori informazioni consultate la pagina: +https://editorconfig.org/ Livelli di astrazione ********************* diff --git a/Documentation/translations/it_IT/process/7.AdvancedTopics.rst b/Documentation/translations/it_IT/process/7.AdvancedTopics.rst index dffd813a0910..a83fcfe18024 100644 --- a/Documentation/translations/it_IT/process/7.AdvancedTopics.rst +++ b/Documentation/translations/it_IT/process/7.AdvancedTopics.rst @@ -160,6 +160,8 @@ preparerà una richiesta nel modo in cui gli altri sviluppatori se l'aspettano, e verificherà che vi siate ricordati di pubblicare quelle patch su un server pubblico. +.. _development_advancedtopics_reviews_it: + Revisionare le patch -------------------- @@ -180,6 +182,13 @@ i commenti come domande e non come critiche. Chiedere "Come viene rilasciato il *lock* in questo percorso?" funziona sempre molto meglio che "qui la sincronizzazione è sbagliata". +In caso di disaccordi, può essere utile chiedere una terza opinione. Se dopo +pochi scambi la discussione raggiunge un punto morto, allora chiedete ai +manutentori o altri revisori di partecipare esprimendo la loro opinione. Spesso +vige un silenzio assenso per cui gli altri revisori non intervengono se non gli +viene richiesto esplicitamente. L'opinione di più persone avrà sicuramente un +peso maggiore. + Diversi sviluppatori revisioneranno il codice con diversi punti di vista. Alcuni potrebbero concentrarsi principalmente sullo stile del codice e se alcune linee hanno degli spazio bianchi di troppo. Altri si chiederanno @@ -189,3 +198,13 @@ l'uso eccessivo di *stack*, problemi di sicurezza, duplicazione del codice in altri contesti, documentazione, effetti negativi sulle prestazioni, cambi all'ABI dello spazio utente, eccetera. Qualunque tipo di revisione è ben accetta e di valore, se porta ad avere un codice migliore nel kernel. + +Non esistono requisiti particolarmente stringenti per l'uso di etichette come +``Reviewd-by``. Tuttavia, perché la revisione sia efficace ci si aspetta un +qualche tipo di messaggio che dica "ho verificato A, B e C nel codice che è +appena stato inviato e mi sembra tutto in ordine". Inoltre, questo permette ai +manutentori di prendere conoscenza circa una revisione avvenuta per davvero. + +Per finire, la revisione delle patch può diventare un processo negativo, troppo +focalizzato sulla ricerca dei problemi. Provate a fare qualche complimento di +tanto in tanto, specialmente con i nuovi arrivati. diff --git a/Documentation/translations/it_IT/process/changes.rst b/Documentation/translations/it_IT/process/changes.rst index f37c53f8b524..ade695a7de19 100644 --- a/Documentation/translations/it_IT/process/changes.rst +++ b/Documentation/translations/it_IT/process/changes.rst @@ -34,13 +34,15 @@ PC Card, per esempio, probabilmente non dovreste preoccuparvi di pcmciautils. ====================== ================= ======================================== GNU C 5.1 gcc --version Clang/LLVM (optional) 11.0.0 clang --version +Rust (opzionale) 1.74.1 rustc --version +bindgen (opzionale) 0.65.1 bindgen --version GNU make 3.81 make --version bash 4.2 bash --version binutils 2.25 ld -v flex 2.5.35 flex --version bison 2.0 bison --version pahole 1.16 pahole --version -util-linux 2.10o fdformat --version +util-linux 2.10o mount --version kmod 13 depmod -V e2fsprogs 1.41.4 e2fsck -V jfsutils 1.1.3 fsck.jfs -V @@ -59,8 +61,10 @@ mcelog 0.6 mcelog --version iptables 1.4.2 iptables -V openssl & libcrypto 1.0.0 openssl version bc 1.06.95 bc --version -Sphinx\ [#f1]_ 1.7 sphinx-build --version +Sphinx\ [#f1]_ 2.4.4 sphinx-build --version cpio any cpio --version +GNU tar 1.28 tar --version +gtags (opzionale) 6.6.5 gtags --version ====================== ================= ======================================== .. [#f1] Sphinx è necessario solo per produrre la documentazione del Kernel @@ -151,6 +155,18 @@ Se la firma dei moduli è abilitata, allora vi servirà openssl per compilare il kernel 3.7 e successivi. Vi serviranno anche i pacchetti di sviluppo di openssl per compilare il kernel 4.3 o successivi. +Tar +--- + +GNU Tar è necessario per accedere ai file d'intestazione del kernel usando sysfs +(CONFIG_IKHEADERS) + +gtags / GNU GLOBAL (opzionale) +------------------------------ + +Il programma GNU GLOBAL versione 6.6.5, o successiva, è necessario quando si +vuole eseguire ``make gtags`` e generare i relativi indici. Internamente si fa +uso del parametro gtags ``-C (--directory)`` che compare in questa versione. Strumenti di sistema ******************** @@ -434,7 +450,7 @@ E2fsprogs JFSutils -------- -- +- Reiserfsprogs ------------- @@ -455,7 +471,7 @@ Pcmciautils Quota-tools ----------- -- +- Microcodice Intel P6 @@ -476,7 +492,7 @@ FUSE mcelog ------ -- +- cpio ---- @@ -497,7 +513,8 @@ PPP NFS-utils --------- -- +- +- Iptables -------- @@ -512,12 +529,7 @@ Ip-route2 OProfile -------- -- - -NFS-Utils ---------- - -- +- Documentazione del kernel ************************* diff --git a/Documentation/translations/it_IT/process/coding-style.rst b/Documentation/translations/it_IT/process/coding-style.rst index 284a75ac19f8..a4b9f44081da 100644 --- a/Documentation/translations/it_IT/process/coding-style.rst +++ b/Documentation/translations/it_IT/process/coding-style.rst @@ -214,7 +214,7 @@ Non usate inutilmente le graffe dove una singola espressione è sufficiente. e -.. code-block:: none +.. code-block:: c if (condition) do_this(); @@ -652,7 +652,7 @@ Quindi, potete sbarazzarvi di GNU emacs, o riconfigurarlo con valori più sensati. Per fare quest'ultima cosa, potete appiccicare il codice che segue nel vostro file .emacs: -.. code-block:: none +.. code-block:: elisp (defun c-lineup-arglist-tabs-only (ignored) "Line up argument lists by tabs, not spaces" @@ -728,6 +728,10 @@ il testo e altre cose simili. Per maggiori dettagli, consultate il file :ref:`Documentation/translations/it_IT/process/clang-format.rst `. +Se utilizzate un programma compatibile con EditorConfig, allora alcune +configurazioni basilari come l'indentazione e la fine delle righe verranno +applicate automaticamente. Per maggiori informazioni consultate la pagina: +https://editorconfig.org/ 10) File di configurazione Kconfig ---------------------------------- @@ -898,7 +902,9 @@ usare per assicurarvi che i messaggi vengano associati correttamente ai dispositivi e ai driver, e che siano etichettati correttamente: dev_err(), dev_warn(), dev_info(), e così via. Per messaggi che non sono associati ad alcun dispositivo, definisce pr_info(), pr_warn(), pr_err(), -eccetera. +eccetera. Quando tutto funziona correttamente, non dovrebbero esserci stampe, +per cui preferite dev_dbg/pr_debug a meno che non sia qualcosa di sbagliato +da segnalare. Tirar fuori un buon messaggio di debug può essere una vera sfida; e quando l'avete può essere d'enorme aiuto per risolvere problemi da remoto. diff --git a/Documentation/translations/it_IT/process/deprecated.rst b/Documentation/translations/it_IT/process/deprecated.rst index ba0ed7dc154c..d4ab76e9be49 100644 --- a/Documentation/translations/it_IT/process/deprecated.rst +++ b/Documentation/translations/it_IT/process/deprecated.rst @@ -86,7 +86,7 @@ da kcalloc(). Se questo tipo di allocatore non è disponibile, allora dovrebbero essere usate le funzioni del tipo *saturate-on-overflow*:: - bar = vmalloc(array_size(count, size)); + bar = dma_alloc_coherent(dev, array_size(count, size), &dma, GFP_KERNEL); Un altro tipico caso da evitare è quello di calcolare la dimensione di una struttura seguita da un vettore di altre strutture, come nel seguente caso:: diff --git a/Documentation/translations/it_IT/process/howto.rst b/Documentation/translations/it_IT/process/howto.rst index 052f1b3610cb..090941a0a898 100644 --- a/Documentation/translations/it_IT/process/howto.rst +++ b/Documentation/translations/it_IT/process/howto.rst @@ -85,8 +85,8 @@ relativi file di documentatione che spiegano come usarele. Quando un cambiamento del kernel genera anche un cambiamento nell'interfaccia con lo spazio utente, è raccomandabile che inviate una notifica o una correzione alle pagine *man* spiegando tale modifica agli amministratori di -queste pagine all'indirizzo mtk.manpages@gmail.com, aggiungendo -in CC la lista linux-api@vger.kernel.org. +queste pagine all'indirizzo alx@kernel.org, aggiungendo in CC la +lista linux-api@vger.kernel.org. Di seguito una lista di file che sono presenti nei sorgente del kernel e che è richiesto che voi leggiate: @@ -144,7 +144,7 @@ Di seguito una lista di file che sono presenti nei sorgente del kernel e che dello sviluppo di Linux ed è molto importante per le persone che arrivano da esperienze con altri Sistemi Operativi. - :ref:`Documentation/translations/it_IT/admin-guide/security-bugs.rst ` + :ref:`Documentation/translations/it_IT/process/security-bugs.rst ` Se ritenete di aver trovato un problema di sicurezza nel kernel Linux, seguite i passaggi scritti in questo documento per notificarlo agli sviluppatori del kernel, ed aiutare la risoluzione del problema. diff --git a/Documentation/translations/it_IT/process/index.rst b/Documentation/translations/it_IT/process/index.rst index cd7977905fb8..73c643dcc541 100644 --- a/Documentation/translations/it_IT/process/index.rst +++ b/Documentation/translations/it_IT/process/index.rst @@ -21,19 +21,75 @@ l'accettazione delle vostre modifiche con il minimo sforzo. Di seguito le guide che ogni sviluppatore dovrebbe leggere. +Introduzione al funzionamento dello sviluppo del kernel +------------------------------------------------------- + +Innanzitutto, leggete questi documenti che vi aiuteranno ad entrare nella +comunità del kernel. + .. toctree:: :maxdepth: 1 howto - code-of-conduct development-process submitting-patches + submit-checklist + +Strumenti e guide tecniche per gli sviluppatori del kernel +---------------------------------------------------------- + +Quella che segue è una raccolta di documenti che uno sviluppatore del kernel +Linux dovrebbe conoscere. + +.. toctree:: + :maxdepth: 1 + + changes programming-language coding-style maintainer-pgp-guide email-clients + applying-patches + adding-syscalls + volatile-considered-harmful + botching-up-ioctls + +Politiche e dichiarazioni degli sviluppatori +-------------------------------------------- + +Quelle che seguono rappresentano le regole che cerchiamo di seguire all'interno +della comunità del kernel (e oltre). + +.. toctree:: + :maxdepth: 1 + + code-of-conduct kernel-enforcement-statement kernel-driver-statement + stable-api-nonsense + stable-kernel-rules + management-style + +Gestire i bachi +--------------- + +I bachi sono parte della nostra vita; dunque è importante che vengano trattati +con riguardo. I documenti che seguono descrivono le nostre politiche riguardo al +trattamento di alcune classi particolari di bachi: le regressioni e i problemi +di sicurezza. + +Informazioni per i manutentori +------------------------------ + +Come trovare le persone che accetteranno le vostre modifiche. + +.. toctree:: + :maxdepth: 1 + + maintainers + +Altri documenti +--------------- Poi ci sono altre guide sulla comunità che sono di interesse per molti degli sviluppatori: @@ -41,13 +97,7 @@ degli sviluppatori: .. toctree:: :maxdepth: 1 - changes - stable-api-nonsense - management-style - stable-kernel-rules - submit-checklist kernel-docs - maintainers Ed infine, qui ci sono alcune guide più tecniche che son state messe qua solo perché non si è trovato un posto migliore. @@ -55,11 +105,7 @@ perché non si è trovato un posto migliore. .. toctree:: :maxdepth: 1 - applying-patches - adding-syscalls magic-number - volatile-considered-harmful - botching-up-ioctls clang-format ../riscv/patch-acceptance diff --git a/Documentation/translations/it_IT/admin-guide/security-bugs.rst b/Documentation/translations/it_IT/process/security-bugs.rst similarity index 100% rename from Documentation/translations/it_IT/admin-guide/security-bugs.rst rename to Documentation/translations/it_IT/process/security-bugs.rst diff --git a/Documentation/translations/it_IT/process/stable-kernel-rules.rst b/Documentation/translations/it_IT/process/stable-kernel-rules.rst index 248bf1e4b171..a2577a806a18 100644 --- a/Documentation/translations/it_IT/process/stable-kernel-rules.rst +++ b/Documentation/translations/it_IT/process/stable-kernel-rules.rst @@ -44,7 +44,7 @@ Procedura per sottomettere patch per i sorgenti -stable .. note:: Una patch di sicurezza non dovrebbe essere gestita (solamente) dal processo di revisione -stable, ma dovrebbe seguire le procedure descritte in - :ref:`Documentation/translations/it_IT/admin-guide/security-bugs.rst `. + :ref:`Documentation/translations/it_IT/process/security-bugs.rst `. Per tutte le altre sottomissioni, scegliere una delle seguenti procedure ------------------------------------------------------------------------ diff --git a/Documentation/translations/it_IT/process/submitting-patches.rst b/Documentation/translations/it_IT/process/submitting-patches.rst index f91c8092844f..4c6a276bdc08 100644 --- a/Documentation/translations/it_IT/process/submitting-patches.rst +++ b/Documentation/translations/it_IT/process/submitting-patches.rst @@ -349,6 +349,33 @@ Leggete Documentation/translations/it_IT/process/email-clients.rst per le raccomandazioni sui programmi di posta elettronica e l'etichetta da usare sulle liste di discussione. +.. _it_interleaved_replies: + +Rispondere alle email in riga e riducendo la citazioni +------------------------------------------------------ + +Nelle discussioni riguardo allo sviluppo del kernel viene fortemente scoraggiato +l'uso di risposte in cima ai messaggi di posta elettronica. Rispondere in riga +rende le conversazioni molto più scorrevoli. Maggiori dettagli possono essere +trovati qui: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style + +Come spesso citato nelle liste di discussione:: + + R: http://en.wikipedia.org/wiki/Top_post + D: Dove posso trovare informazioni riguardo alle "risposte in cima"? + R: Perché incasina il normale ordine con cui si legge un testo. + D: Perché è così terribile rispondere in cima? + R: Risposte in cima. + Q: Qual è la cosa più fastidiosa nei messaggi di posta elettronica? + +Allo stesso modo, per favore eliminate tutte le citazioni non necessarie per la +vostra risposta. Questo permette di trovare più facilmente le risposte, e +permette di risparmiare tempo e spazio. Per maggiori dettagli: +http://daringfireball.net/2007/07/on_top :: + + R: No. + D: Dovrei includere un blocco di citazione dopo la mia risposta? + .. _it_resend_reminders: Non scoraggiatevi - o impazientitevi From 02e97ef1094ae1b81afd50b7ea399e75c431ce4e Mon Sep 17 00:00:00 2001 From: Akira Yokosawa Date: Thu, 2 May 2024 17:56:10 +0900 Subject: [PATCH 868/969] docs: ja_JP/howto: Catch up update in v6.8 Catch up the update made in commit e49ad8530de9 ("CREDITS, MAINTAINERS, docs/process/howto: Update man-pages' maintainer"). Signed-off-by: Akira Yokosawa Cc: Tsugikazu Shibata Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240502085610.111739-1-akiyks@gmail.com --- Documentation/translations/ja_JP/process/howto.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/translations/ja_JP/process/howto.rst b/Documentation/translations/ja_JP/process/howto.rst index 8d856ebe873c..872876c67896 100644 --- a/Documentation/translations/ja_JP/process/howto.rst +++ b/Documentation/translations/ja_JP/process/howto.rst @@ -110,7 +110,7 @@ Linux カーネルソースツリーは幅広い範囲のドキュメントを 新しいドキュメントファイルも追加することを勧めます。 カーネルの変更が、カーネルがユーザ空間に公開しているインターフェイスの 変更を引き起こす場合、その変更を説明するマニュアルページのパッチや情報 -をマニュアルページのメンテナ mtk.manpages@gmail.com に送り、CC を +をマニュアルページのメンテナ alx@kernel.org に送り、CC を linux-api@vger.kernel.org に送ることを勧めます。 以下はカーネルソースツリーに含まれている読んでおくべきファイルの一覧で From d43ddd5c91802a46354fa4c4381416ef760676e2 Mon Sep 17 00:00:00 2001 From: Akira Yokosawa Date: Wed, 1 May 2024 12:16:11 +0900 Subject: [PATCH 869/969] docs: kernel_include.py: Cope with docutils 0.21 Running "make htmldocs" on a newly installed Sphinx 7.3.7 ends up in a build error: Sphinx parallel build error: AttributeError: module 'docutils.nodes' has no attribute 'reprunicode' docutils 0.21 has removed nodes.reprunicode, quote from release note [1]: * Removed objects: docutils.nodes.reprunicode, docutils.nodes.ensure_str() Python 2 compatibility hacks Sphinx 7.3.0 supports docutils 0.21 [2]: kernel_include.py, whose origin is misc.py of docutils, uses reprunicode. Upstream docutils removed the offending line from the corresponding file (docutils/docutils/parsers/rst/directives/misc.py) in January 2022. Quoting the changelog [3]: Deprecate `nodes.reprunicode` and `nodes.ensure_str()`. Drop uses of the deprecated constructs (not required with Python 3). Do the same for kernel_include.py. Tested against: - Sphinx 2.4.5 (docutils 0.17.1) - Sphinx 3.4.3 (docutils 0.17.1) - Sphinx 5.3.0 (docutils 0.18.1) - Sphinx 6.2.1 (docutils 0.19) - Sphinx 7.2.6 (docutils 0.20.1) - Sphinx 7.3.7 (docutils 0.21.2) Link: http://www.docutils.org/RELEASE-NOTES.html#release-0-21-2024-04-09 [1] Link: https://www.sphinx-doc.org/en/master/changes.html#release-7-3-0-released-apr-16-2024 [2] Link: https://github.com/docutils/docutils/commit/c8471ce47a24 [3] Signed-off-by: Akira Yokosawa Cc: stable@vger.kernel.org Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/faf5fa45-2a9d-4573-9d2e-3930bdc1ed65@gmail.com --- Documentation/sphinx/kernel_include.py | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/sphinx/kernel_include.py b/Documentation/sphinx/kernel_include.py index abe768088377..638762442336 100755 --- a/Documentation/sphinx/kernel_include.py +++ b/Documentation/sphinx/kernel_include.py @@ -97,7 +97,6 @@ class KernelInclude(Include): # HINT: this is the only line I had to change / commented out: #path = utils.relative_path(None, path) - path = nodes.reprunicode(path) encoding = self.options.get( 'encoding', self.state.document.settings.input_encoding) e_handler=self.state.document.settings.input_encoding_error_handler From da51bbcdbace8f43adf6066934c3926b656376e5 Mon Sep 17 00:00:00 2001 From: Remington Brasga Date: Mon, 29 Apr 2024 22:55:27 +0000 Subject: [PATCH 870/969] Docs: typos/spelling Fix spelling and grammar in Docs descriptions Signed-off-by: Remington Brasga Reviewed-by: Randy Dunlap Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240429225527.2329-1-rbrasga@uci.edu --- Documentation/admin-guide/hw-vuln/srso.rst | 2 +- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/admin-guide/mm/ksm.rst | 2 +- Documentation/arch/m68k/buddha-driver.rst | 2 +- Documentation/arch/sparc/oradax/dax-hv-api.txt | 2 +- Documentation/arch/x86/xstate.rst | 2 +- Documentation/core-api/entry.rst | 2 +- Documentation/driver-api/mtd/nand_ecc.rst | 2 +- Documentation/driver-api/scsi.rst | 2 +- Documentation/driver-api/usb/usb.rst | 2 +- Documentation/driver-api/wbrf.rst | 2 +- Documentation/filesystems/directory-locking.rst | 4 ++-- Documentation/filesystems/porting.rst | 4 ++-- Documentation/mm/slub.rst | 2 +- Documentation/security/SCTP.rst | 2 +- Documentation/translations/zh_TW/process/submit-checklist.rst | 2 +- 16 files changed, 18 insertions(+), 18 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/srso.rst b/Documentation/admin-guide/hw-vuln/srso.rst index e715bfc09879..4bd3ce3ba171 100644 --- a/Documentation/admin-guide/hw-vuln/srso.rst +++ b/Documentation/admin-guide/hw-vuln/srso.rst @@ -135,7 +135,7 @@ and does not want to suffer the performance impact, one can always disable the mitigation with spec_rstack_overflow=off. Similarly, 'Mitigation: IBPB' is another full mitigation type employing -an indrect branch prediction barrier after having applied the required +an indirect branch prediction barrier after having applied the required microcode patch for one's system. This mitigation comes also at a performance cost. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index e6809b85b211..4ea02ed8d8a6 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -7308,7 +7308,7 @@ This can be changed after boot by writing to the matching /sys/module/workqueue/parameters file. All workqueues with the "default" affinity scope will be - updated accordignly. + updated accordingly. workqueue.debug_force_rr_cpu Workqueue used to implicitly guarantee that work diff --git a/Documentation/admin-guide/mm/ksm.rst b/Documentation/admin-guide/mm/ksm.rst index a639cac12477..ad8e7a41f3b5 100644 --- a/Documentation/admin-guide/mm/ksm.rst +++ b/Documentation/admin-guide/mm/ksm.rst @@ -308,7 +308,7 @@ limited by the ``advisor_max_cpu`` parameter. In addition there is also the ``advisor_target_scan_time`` parameter. This parameter sets the target time to scan all the KSM candidate pages. The parameter ``advisor_target_scan_time`` decides how aggressive the scan time advisor scans candidate pages. Lower -values make the scan time advisor to scan more aggresively. This is the most +values make the scan time advisor to scan more aggressively. This is the most important parameter for the configuration of the scan time advisor. The initial value and the maximum value can be changed with diff --git a/Documentation/arch/m68k/buddha-driver.rst b/Documentation/arch/m68k/buddha-driver.rst index 20e401413991..5d1bc824978b 100644 --- a/Documentation/arch/m68k/buddha-driver.rst +++ b/Documentation/arch/m68k/buddha-driver.rst @@ -173,7 +173,7 @@ When accessing IDE registers with A6=1 (for example $84x), the timing will always be mode 0 8-bit compatible, no matter what you have selected in the speed register: -781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive. +781ns select, IOR/IOW after 4 clock cycles (=314ns) active. All the timings with a very short select-signal (the 355ns fast accesses) depend on the accelerator card used in the diff --git a/Documentation/arch/sparc/oradax/dax-hv-api.txt b/Documentation/arch/sparc/oradax/dax-hv-api.txt index 7ecd0bf4957b..ef1a4c2bf08b 100644 --- a/Documentation/arch/sparc/oradax/dax-hv-api.txt +++ b/Documentation/arch/sparc/oradax/dax-hv-api.txt @@ -41,7 +41,7 @@ Chapter 36. Coprocessor services submissions until they succeed; waiting for an outstanding CCB to complete is not necessary, and would not be a guarantee that a future submission would succeed. - The availablility of DAX coprocessor command service is indicated by the presence of the DAX virtual + The availability of DAX coprocessor command service is indicated by the presence of the DAX virtual device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device node”). diff --git a/Documentation/arch/x86/xstate.rst b/Documentation/arch/x86/xstate.rst index ae5c69e48b11..cec05ac464c1 100644 --- a/Documentation/arch/x86/xstate.rst +++ b/Documentation/arch/x86/xstate.rst @@ -138,7 +138,7 @@ Note this example does not include the sigaltstack preparation. Dynamic features in signal frames --------------------------------- -Dynamcally enabled features are not written to the signal frame upon signal +Dynamically enabled features are not written to the signal frame upon signal entry if the feature is in its initial configuration. This differs from non-dynamic features which are always written regardless of their configuration. Signal handlers can examine the XSAVE buffer's XSTATE_BV diff --git a/Documentation/core-api/entry.rst b/Documentation/core-api/entry.rst index e12f22ab33c7..a15f9b1767a2 100644 --- a/Documentation/core-api/entry.rst +++ b/Documentation/core-api/entry.rst @@ -18,7 +18,7 @@ exceptions`_, `NMI and NMI-like exceptions`_. Non-instrumentable code - noinstr --------------------------------- -Most instrumentation facilities depend on RCU, so intrumentation is prohibited +Most instrumentation facilities depend on RCU, so instrumentation is prohibited for entry code before RCU starts watching and exit code after RCU stops watching. In addition, many architectures must save and restore register state, which means that (for example) a breakpoint in the breakpoint entry code would diff --git a/Documentation/driver-api/mtd/nand_ecc.rst b/Documentation/driver-api/mtd/nand_ecc.rst index 74347c14a70b..a0d681f26a2e 100644 --- a/Documentation/driver-api/mtd/nand_ecc.rst +++ b/Documentation/driver-api/mtd/nand_ecc.rst @@ -462,7 +462,7 @@ statements is reduced. This is also reflected in the assembly code. Analysis 3 ========== -Very weird. Guess it has to do with caching or instruction parallellism +Very weird. Guess it has to do with caching or instruction parallelism or so. I also tried on an eeePC (Celeron, clocked at 900 Mhz). Interesting observation was that this one is only 30% slower (according to time) executing the code as my 3Ghz D920 processor. diff --git a/Documentation/driver-api/scsi.rst b/Documentation/driver-api/scsi.rst index 64b231d125e0..ec92ea2c82cd 100644 --- a/Documentation/driver-api/scsi.rst +++ b/Documentation/driver-api/scsi.rst @@ -259,7 +259,7 @@ attributes for Serial Attached SCSI, a variant of SATA aimed at large high-end systems. The SAS transport class contains common code to deal with SAS HBAs, an -aproximated representation of SAS topologies in the driver model, and +approximated representation of SAS topologies in the driver model, and various sysfs attributes to expose these topologies and management interfaces to userspace. diff --git a/Documentation/driver-api/usb/usb.rst b/Documentation/driver-api/usb/usb.rst index fb41768696ec..89f9c37bb979 100644 --- a/Documentation/driver-api/usb/usb.rst +++ b/Documentation/driver-api/usb/usb.rst @@ -422,7 +422,7 @@ USBDEVFS_CONNECTINFO USBDEVFS_GET_SPEED Returns the speed of the device. The speed is returned as a - nummerical value in accordance with enum usb_device_speed + numerical value in accordance with enum usb_device_speed File modification time is not updated by this request. diff --git a/Documentation/driver-api/wbrf.rst b/Documentation/driver-api/wbrf.rst index f48bfa029813..6b18833e2e69 100644 --- a/Documentation/driver-api/wbrf.rst +++ b/Documentation/driver-api/wbrf.rst @@ -68,7 +68,7 @@ The expected flow for the consumers: can be enabled for the device. 2. Call `amd_wbrf_register_notifier` to register for notification of frequency band change(add or remove) from other producers. -3. Call the `amd_wbrf_retrieve_freq_band` initally to retrieve +3. Call the `amd_wbrf_retrieve_freq_band` initially to retrieve current active frequency bands considering some producers may broadcast such information before the consumer is up. 4. On receiving a notification for frequency band change, run diff --git a/Documentation/filesystems/directory-locking.rst b/Documentation/filesystems/directory-locking.rst index 05ea387bc9fb..6fdf0b02df43 100644 --- a/Documentation/filesystems/directory-locking.rst +++ b/Documentation/filesystems/directory-locking.rst @@ -44,7 +44,7 @@ For our purposes all operations fall in 6 classes: * decide which of the source and target need to be locked. The source needs to be locked if it's a non-directory, target - if it's a non-directory or about to be removed. - * take the locks that need to be taken (exlusive), in inode pointer order + * take the locks that need to be taken (exclusive), in inode pointer order if need to take both (that can happen only when both source and target are non-directories - the source because it wouldn't need to be locked otherwise and the target because mixing directory and non-directory is @@ -234,7 +234,7 @@ among the children, in some order. But that is also impossible, since neither of the children is a descendent of another. That concludes the proof, since the set of operations with the -properties requiered for a minimal deadlock can not exist. +properties required for a minimal deadlock can not exist. Note that the check for having a common ancestor in cross-directory rename is crucial - without it a deadlock would be possible. Indeed, diff --git a/Documentation/filesystems/porting.rst b/Documentation/filesystems/porting.rst index 1be76ef117b3..f2b44c2400c6 100644 --- a/Documentation/filesystems/porting.rst +++ b/Documentation/filesystems/porting.rst @@ -858,7 +858,7 @@ be misspelled d_alloc_anon(). **mandatory** -[should've been added in 2016] stale comment in finish_open() nonwithstanding, +[should've been added in 2016] stale comment in finish_open() notwithstanding, failure exits in ->atomic_open() instances should *NOT* fput() the file, no matter what. Everything is handled by the caller. @@ -989,7 +989,7 @@ This mechanism would only work for a single device so the block layer couldn't find the owning superblock of any additional devices. In the old mechanism reusing or creating a superblock for a racing mount(2) and -umount(2) relied on the file_system_type as the holder. This was severly +umount(2) relied on the file_system_type as the holder. This was severely underdocumented however: (1) Any concurrent mounter that managed to grab an active reference on an diff --git a/Documentation/mm/slub.rst b/Documentation/mm/slub.rst index b517ee28a955..60d350d08362 100644 --- a/Documentation/mm/slub.rst +++ b/Documentation/mm/slub.rst @@ -80,7 +80,7 @@ to the dentry cache with:: Debugging options may require the minimum possible slab order to increase as a result of storing the metadata (for example, caches with PAGE_SIZE object -sizes). This has a higher liklihood of resulting in slab allocation errors +sizes). This has a higher likelihood of resulting in slab allocation errors in low memory situations or if there's high fragmentation of memory. To switch off debugging for such caches by default, use:: diff --git a/Documentation/security/SCTP.rst b/Documentation/security/SCTP.rst index b73eb764a001..6d80d464ab6e 100644 --- a/Documentation/security/SCTP.rst +++ b/Documentation/security/SCTP.rst @@ -81,7 +81,7 @@ A summary of the ``@optname`` entries is as follows:: destination addresses. SCTP_SENDMSG_CONNECT - Initiate a connection that is generated by a - sendmsg(2) or sctp_sendmsg(3) on a new asociation. + sendmsg(2) or sctp_sendmsg(3) on a new association. SCTP_PRIMARY_ADDR - Set local primary address. diff --git a/Documentation/translations/zh_TW/process/submit-checklist.rst b/Documentation/translations/zh_TW/process/submit-checklist.rst index 43f2e3c5b514..0ecb187753e4 100644 --- a/Documentation/translations/zh_TW/process/submit-checklist.rst +++ b/Documentation/translations/zh_TW/process/submit-checklist.rst @@ -31,7 +31,7 @@ Linux內核補丁提交檢查單 c) 使用 ``O=builddir`` 時可以成功編譯 - d) 任何 Doucmentation/ 下的變更都能成功構建且不引入新警告/錯誤。 + d) 任何 Documentation/ 下的變更都能成功構建且不引入新警告/錯誤。 用 ``make htmldocs`` 或 ``make pdfdocs`` 檢驗構建情況並修復問題。 3) 通過使用本地交叉編譯工具或其他一些構建設施在多個CPU體系結構上構建。 From 125db341e2e25db32e494aed865e5415a40fc07b Mon Sep 17 00:00:00 2001 From: Ivan Orlov Date: Mon, 29 Apr 2024 16:57:34 +0100 Subject: [PATCH 871/969] docs, kprobes: Add riscv as supported architecture Support of kprobes and kretprobes for riscv was introduced 3 years ago by the following change: commit c22b0bcb1dd0 ("riscv: Add kprobes supported") Add riscv to the list of supported architectures. Signed-off-by: Ivan Orlov Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240429155735.68781-1-ivan.orlov@codethink.co.uk --- Documentation/trace/kprobes.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/trace/kprobes.rst b/Documentation/trace/kprobes.rst index e1636e579c9c..5e606730cec6 100644 --- a/Documentation/trace/kprobes.rst +++ b/Documentation/trace/kprobes.rst @@ -322,6 +322,7 @@ architectures: - s390 - parisc - loongarch +- riscv Configuring Kprobes =================== From db483303b58f175cf7508ccfb1d5514f2488f11e Mon Sep 17 00:00:00 2001 From: Thorsten Leemhuis Date: Mon, 29 Apr 2024 09:18:26 +0200 Subject: [PATCH 872/969] docs: stable-kernel-rules: reduce redundancy Explain the general concept once in the intro to keep things somewhat shorter in the individual points. Reviewed-by: Greg Kroah-Hartman Signed-off-by: Thorsten Leemhuis Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/106e21789e2bf02d174e1715b49cd4d30886d51f.1714367921.git.linux@leemhuis.info --- Documentation/process/stable-kernel-rules.rst | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index 1704f1c686d0..0da9c57287c1 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -79,10 +79,9 @@ stable tree without anything else needing to be done by the author or subsystem maintainer. To sent additional instructions to the stable team, use a shell-style inline -comment: +comment to pass arbitrary or predefined notes: - * To specify any additional patch prerequisites for cherry picking use the - following format in the sign-off area: + * Specify any additional patch prerequisites for cherry picking: .. code-block:: none @@ -114,8 +113,7 @@ comment: prerequisite of patch2 if you have already marked patch1 for stable inclusion. - * For patches that may have kernel version prerequisites specify them using - the following format in the sign-off area: + * Point out kernel version prerequisites: .. code-block:: none @@ -132,14 +130,13 @@ comment: Note, such tagging is unnecessary if the stable team can derive the appropriate versions from Fixes: tags. - * To delay pick up of patches, use the following format: + * Delay pick up of patches: .. code-block:: none Cc: # after 4 weeks in mainline - * For any other requests, just add a note to the stable tag. This for example - can be used to point out known problems: + * Point out known problems: .. code-block:: none From 2263c40e65255202f6f6d9dfa31d23906995ff7c Mon Sep 17 00:00:00 2001 From: Thorsten Leemhuis Date: Mon, 29 Apr 2024 09:18:27 +0200 Subject: [PATCH 873/969] docs: stable-kernel-rules: call mainline by its name and change example Fine-tuning: * s/Linus' tree/Linux mainline/, as mainline is the term used elsewhere in the document. * Provide a better example for the 'delayed backporting' case that uses a fixed rather than a relative reference point, which makes it easier to handle for the stable team. Signed-off-by: Thorsten Leemhuis Reviewed-by: Greg Kroah-Hartman Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/0a120573ea827aee12d45e7bd802ba85c09884da.1714367921.git.linux@leemhuis.info --- Documentation/process/stable-kernel-rules.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index 0da9c57287c1..d28072b570f8 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -6,7 +6,7 @@ Everything you ever wanted to know about Linux -stable releases Rules on what kind of patches are accepted, and which ones are not, into the "-stable" tree: - - It or an equivalent fix must already exist in Linus' tree (upstream). + - It or an equivalent fix must already exist in Linux mainline (upstream). - It must be obviously correct and tested. - It cannot be bigger than 100 lines, with context. - It must follow the @@ -134,7 +134,7 @@ comment to pass arbitrary or predefined notes: .. code-block:: none - Cc: # after 4 weeks in mainline + Cc: # after -rc3 * Point out known problems: From 5db34f5bfd78230148df83472af5a85c91d04058 Mon Sep 17 00:00:00 2001 From: Thorsten Leemhuis Date: Mon, 29 Apr 2024 09:18:28 +0200 Subject: [PATCH 874/969] docs: stable-kernel-rules: remove code-labels tags and a indention level Remove the 'code-block:: none' labels and switch to the shorter '::' to reduce noise. Remove a unneeded level of indentation, as that reduces the chance that readers have to scroll sideways in some of the code blocks. No text changes. Rendered html output looks like before, except for the different level of indentation. CC: Jonathan Corbet Signed-off-by: Thorsten Leemhuis Reviewed-by: Greg Kroah-Hartman Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/755afbeafc8e1457154cb4b30ff4397f34326679.1714367921.git.linux@leemhuis.info --- Documentation/process/stable-kernel-rules.rst | 223 ++++++++---------- 1 file changed, 101 insertions(+), 122 deletions(-) diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index d28072b570f8..b4af627154f1 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -6,29 +6,29 @@ Everything you ever wanted to know about Linux -stable releases Rules on what kind of patches are accepted, and which ones are not, into the "-stable" tree: - - It or an equivalent fix must already exist in Linux mainline (upstream). - - It must be obviously correct and tested. - - It cannot be bigger than 100 lines, with context. - - It must follow the - :ref:`Documentation/process/submitting-patches.rst ` - rules. - - It must either fix a real bug that bothers people or just add a device ID. - To elaborate on the former: +- It or an equivalent fix must already exist in Linux mainline (upstream). +- It must be obviously correct and tested. +- It cannot be bigger than 100 lines, with context. +- It must follow the + :ref:`Documentation/process/submitting-patches.rst ` + rules. +- It must either fix a real bug that bothers people or just add a device ID. + To elaborate on the former: - - It fixes a problem like an oops, a hang, data corruption, a real security - issue, a hardware quirk, a build error (but not for things marked - CONFIG_BROKEN), or some "oh, that's not good" issue. - - Serious issues as reported by a user of a distribution kernel may also - be considered if they fix a notable performance or interactivity issue. - As these fixes are not as obvious and have a higher risk of a subtle - regression they should only be submitted by a distribution kernel - maintainer and include an addendum linking to a bugzilla entry if it - exists and additional information on the user-visible impact. - - No "This could be a problem..." type of things like a "theoretical race - condition", unless an explanation of how the bug can be exploited is also - provided. - - No "trivial" fixes without benefit for users (spelling changes, whitespace - cleanups, etc). + - It fixes a problem like an oops, a hang, data corruption, a real security + issue, a hardware quirk, a build error (but not for things marked + CONFIG_BROKEN), or some "oh, that's not good" issue. + - Serious issues as reported by a user of a distribution kernel may also + be considered if they fix a notable performance or interactivity issue. + As these fixes are not as obvious and have a higher risk of a subtle + regression they should only be submitted by a distribution kernel + maintainer and include an addendum linking to a bugzilla entry if it + exists and additional information on the user-visible impact. + - No "This could be a problem..." type of things like a "theoretical race + condition", unless an explanation of how the bug can be exploited is also + provided. + - No "trivial" fixes without benefit for users (spelling changes, whitespace + cleanups, etc). Procedure for submitting patches to the -stable tree @@ -42,11 +42,11 @@ Procedure for submitting patches to the -stable tree There are three options to submit a change to -stable trees: - 1. Add a 'stable tag' to the description of a patch you then submit for - mainline inclusion. - 2. Ask the stable team to pick up a patch already mainlined. - 3. Submit a patch to the stable team that is equivalent to a change already - mainlined. +1. Add a 'stable tag' to the description of a patch you then submit for + mainline inclusion. +2. Ask the stable team to pick up a patch already mainlined. +3. Submit a patch to the stable team that is equivalent to a change already + mainlined. The sections below describe each of the options in more detail. @@ -68,79 +68,62 @@ Option 1 ******** To have a patch you submit for mainline inclusion later automatically picked up -for stable trees, add the tag +for stable trees, add this tag in the sign-off area:: -.. code-block:: none + Cc: stable@vger.kernel.org - Cc: stable@vger.kernel.org - -in the sign-off area. Once the patch is mainlined it will be applied to the -stable tree without anything else needing to be done by the author or -subsystem maintainer. +Once the patch is mainlined it will be applied to the stable tree without +anything else needing to be done by the author or subsystem maintainer. To sent additional instructions to the stable team, use a shell-style inline comment to pass arbitrary or predefined notes: - * Specify any additional patch prerequisites for cherry picking: +* Specify any additional patch prerequisites for cherry picking:: - .. code-block:: none + Cc: # 3.3.x: a1f84a3: sched: Check for idle + Cc: # 3.3.x: 1b9508f: sched: Rate-limit newidle + Cc: # 3.3.x: fd21073: sched: Fix affinity logic + Cc: # 3.3.x + Signed-off-by: Ingo Molnar - Cc: # 3.3.x: a1f84a3: sched: Check for idle - Cc: # 3.3.x: 1b9508f: sched: Rate-limit newidle - Cc: # 3.3.x: fd21073: sched: Fix affinity logic - Cc: # 3.3.x - Signed-off-by: Ingo Molnar + The tag sequence has the meaning of:: - The tag sequence has the meaning of: + git cherry-pick a1f84a3 + git cherry-pick 1b9508f + git cherry-pick fd21073 + git cherry-pick - .. code-block:: none + Note that for a patch series, you do not have to list as prerequisites the + patches present in the series itself. For example, if you have the following + patch series:: - git cherry-pick a1f84a3 - git cherry-pick 1b9508f - git cherry-pick fd21073 - git cherry-pick + patch1 + patch2 - Note that for a patch series, you do not have to list as prerequisites the - patches present in the series itself. For example, if you have the following - patch series: + where patch2 depends on patch1, you do not have to list patch1 as + prerequisite of patch2 if you have already marked patch1 for stable + inclusion. - .. code-block:: none +* Point out kernel version prerequisites:: - patch1 - patch2 + Cc: # 3.3.x - where patch2 depends on patch1, you do not have to list patch1 as - prerequisite of patch2 if you have already marked patch1 for stable - inclusion. + The tag has the meaning of:: - * Point out kernel version prerequisites: + git cherry-pick - .. code-block:: none + For each "-stable" tree starting with the specified version. - Cc: # 3.3.x + Note, such tagging is unnecessary if the stable team can derive the + appropriate versions from Fixes: tags. - The tag has the meaning of: +* Delay pick up of patches:: - .. code-block:: none + Cc: # after -rc3 - git cherry-pick +* Point out known problems:: - For each "-stable" tree starting with the specified version. - - Note, such tagging is unnecessary if the stable team can derive the - appropriate versions from Fixes: tags. - - * Delay pick up of patches: - - .. code-block:: none - - Cc: # after -rc3 - - * Point out known problems: - - .. code-block:: none - - Cc: # see patch description, needs adjustments for <= 6.3 + Cc: # see patch description, needs adjustments for <= 6.3 .. _option_2: @@ -160,17 +143,13 @@ Option 3 Send the patch, after verifying that it follows the above rules, to stable@vger.kernel.org and mention the kernel versions you wish it to be applied to. When doing so, you must note the upstream commit ID in the changelog of your -submission with a separate line above the commit text, like this: +submission with a separate line above the commit text, like this:: -.. code-block:: none + commit upstream. - commit upstream. +Or alternatively:: -or alternatively: - -.. code-block:: none - - [ Upstream commit ] + [ Upstream commit ] If the submitted patch deviates from the original upstream patch (for example because it had to be adjusted for the older API), this must be very clearly @@ -191,55 +170,55 @@ developers and by the relevant subsystem maintainer. Review cycle ------------ - - When the -stable maintainers decide for a review cycle, the patches will be - sent to the review committee, and the maintainer of the affected area of - the patch (unless the submitter is the maintainer of the area) and CC: to - the linux-kernel mailing list. - - The review committee has 48 hours in which to ACK or NAK the patch. - - If the patch is rejected by a member of the committee, or linux-kernel - members object to the patch, bringing up issues that the maintainers and - members did not realize, the patch will be dropped from the queue. - - The ACKed patches will be posted again as part of release candidate (-rc) - to be tested by developers and testers. - - Usually only one -rc release is made, however if there are any outstanding - issues, some patches may be modified or dropped or additional patches may - be queued. Additional -rc releases are then released and tested until no - issues are found. - - Responding to the -rc releases can be done on the mailing list by sending - a "Tested-by:" email with any testing information desired. The "Tested-by:" - tags will be collected and added to the release commit. - - At the end of the review cycle, the new -stable release will be released - containing all the queued and tested patches. - - Security patches will be accepted into the -stable tree directly from the - security kernel team, and not go through the normal review cycle. - Contact the kernel security team for more details on this procedure. +- When the -stable maintainers decide for a review cycle, the patches will be + sent to the review committee, and the maintainer of the affected area of + the patch (unless the submitter is the maintainer of the area) and CC: to + the linux-kernel mailing list. +- The review committee has 48 hours in which to ACK or NAK the patch. +- If the patch is rejected by a member of the committee, or linux-kernel + members object to the patch, bringing up issues that the maintainers and + members did not realize, the patch will be dropped from the queue. +- The ACKed patches will be posted again as part of release candidate (-rc) + to be tested by developers and testers. +- Usually only one -rc release is made, however if there are any outstanding + issues, some patches may be modified or dropped or additional patches may + be queued. Additional -rc releases are then released and tested until no + issues are found. +- Responding to the -rc releases can be done on the mailing list by sending + a "Tested-by:" email with any testing information desired. The "Tested-by:" + tags will be collected and added to the release commit. +- At the end of the review cycle, the new -stable release will be released + containing all the queued and tested patches. +- Security patches will be accepted into the -stable tree directly from the + security kernel team, and not go through the normal review cycle. + Contact the kernel security team for more details on this procedure. Trees ----- - - The queues of patches, for both completed versions and in progress - versions can be found at: +- The queues of patches, for both completed versions and in progress + versions can be found at: - https://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git + https://git.kernel.org/pub/scm/linux/kernel/git/stable/stable-queue.git - - The finalized and tagged releases of all stable kernels can be found - in separate branches per version at: +- The finalized and tagged releases of all stable kernels can be found + in separate branches per version at: - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git - - The release candidate of all stable kernel versions can be found at: +- The release candidate of all stable kernel versions can be found at: - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git/ + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git/ - .. warning:: - The -stable-rc tree is a snapshot in time of the stable-queue tree and - will change frequently, hence will be rebased often. It should only be - used for testing purposes (e.g. to be consumed by CI systems). + .. warning:: + The -stable-rc tree is a snapshot in time of the stable-queue tree and + will change frequently, hence will be rebased often. It should only be + used for testing purposes (e.g. to be consumed by CI systems). Review committee ---------------- - - This is made up of a number of kernel developers who have volunteered for - this task, and a few that haven't. +- This is made up of a number of kernel developers who have volunteered for + this task, and a few that haven't. From bb12799503d75f29ddc5a6b2905f960ababe308c Mon Sep 17 00:00:00 2001 From: Thorsten Leemhuis Date: Mon, 29 Apr 2024 09:18:29 +0200 Subject: [PATCH 875/969] docs: stable-kernel-rules: explain use of stable@kernel.org (w/o @vger.) Document when to use of stable@kernel.org instead of stable@vger.kernel.org, as the two are easily mixed up and their difference not explained anywhere[1]. Link: https://lore.kernel.org/all/20240422231550.3cf5f723@sal.lan/ [1] Signed-off-by: Thorsten Leemhuis Reviewed-by: Greg Kroah-Hartman Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/6783b71da48aac5290756343f58591dc42da87bc.1714367921.git.linux@leemhuis.info --- Documentation/process/stable-kernel-rules.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index b4af627154f1..ebf4152659f2 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -72,6 +72,10 @@ for stable trees, add this tag in the sign-off area:: Cc: stable@vger.kernel.org +Use ``Cc: stable@kernel.org`` instead when fixing unpublished vulnerabilities: +it reduces the chance of accidentally exposing the fix to the public by way of +'git send-email', as mails sent to that address are not delivered anywhere. + Once the patch is mainlined it will be applied to the stable tree without anything else needing to be done by the author or subsystem maintainer. From af3e4a5ab9a017da9cf624791629e2df710a171c Mon Sep 17 00:00:00 2001 From: Thorsten Leemhuis Date: Mon, 29 Apr 2024 09:18:30 +0200 Subject: [PATCH 876/969] docs: stable-kernel-rules: create special tag to flag 'no backporting' Document a new variant of the stable tag developers can use to make the stable team's tools ignore a change[1]. That way developers can use 'Fixes:' tags without fearing the changes might be backported in semi-automatic fashion. Such concerns are the reason why some developers deliberately omit the 'Fixes:' tag in changes[2] -- which somewhat undermines the reason for the existence of that tag and might be unwise in the long term[3]. Link: https://lore.kernel.org/all/b452fd54-fdc6-47e4-8c26-6627f6b7eff3@leemhuis.info/ [1] Link: https://lore.kernel.org/all/cover.1712226175.git.antony.antony@secunet.com/ [2] Link: https://lore.kernel.org/all/dfd87673-c581-4b4b-b37a-1cf5c817240d@leemhuis.info/ [3] Signed-off-by: Thorsten Leemhuis Reviewed-by: Greg Kroah-Hartman Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/35989d3b2f3f8cf23828b0c84fde9b17a74be97c.1714367921.git.linux@leemhuis.info --- Documentation/process/stable-kernel-rules.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index ebf4152659f2..9ca8083b41c7 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -129,6 +129,12 @@ comment to pass arbitrary or predefined notes: Cc: # see patch description, needs adjustments for <= 6.3 +There furthermore is a variant of the stable tag you can use to make the stable +team's backporting tools (e.g AUTOSEL or scripts that look for commits +containing a 'Fixes:' tag) ignore a change:: + + Cc: # reason goes here, and must be present + .. _option_2: Option 2 From 5384258f4ef0c27cc9d5255ce4992f13656e215d Mon Sep 17 00:00:00 2001 From: Akira Yokosawa Date: Sat, 27 Apr 2024 17:24:11 +0900 Subject: [PATCH 877/969] docs: scripts/check-variable-fonts.sh: Improve commands for detection As mentioned in "Assumption:", current grep expression can't catch font files whose names are changed from upstream "Noto CJK fonts". To avoid false negatives, use command of the form: fc-list : file family variable , where ":" works as a wildcard pattern. Variable fonts can be detected by filtering the output with "variable=True" and "Noto CJK" font-family variants. Signed-off-by: Akira Yokosawa Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/c62ba2e6-c124-4e91-8011-cb1da408a3c5@gmail.com --- scripts/check-variable-fonts.sh | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/scripts/check-variable-fonts.sh b/scripts/check-variable-fonts.sh index 12765e54e4f3..ce63f0acea5f 100755 --- a/scripts/check-variable-fonts.sh +++ b/scripts/check-variable-fonts.sh @@ -20,10 +20,6 @@ # suggestions if variable-font files of "Noto CJK" fonts are in the list of # fonts accessible from XeTeX. # -# Assumption: -# File names are not modified from those of upstream Noto CJK fonts: -# https://github.com/notofonts/noto-cjk/ -# # References: # [1]: https://lore.kernel.org/r/8734tqsrt7.fsf@meer.lwn.net/ # [2]: https://lore.kernel.org/r/1708585803.600323099@f111.i.mail.ru/ @@ -96,13 +92,15 @@ export XDG_CONFIG_HOME=${FONTS_CONF_DENY_VF} -vffonts=`fc-list -b | grep -iE 'file: .*noto.*cjk.*-vf' | \ - sed -e 's/\tfile:/ file:/' -e 's/(s)$//' | sort | uniq` +notocjkvffonts=`fc-list : file family variable | \ + grep 'variable=True' | \ + grep -E -e 'Noto (Sans|Sans Mono|Serif) CJK' | \ + sed -e 's/^/ /' -e 's/: Noto S.*$//' | sort | uniq` -if [ "x$vffonts" != "x" ] ; then +if [ "x$notocjkvffonts" != "x" ] ; then echo '=============================================================================' echo 'XeTeX is confused by "variable font" files listed below:' - echo "$vffonts" + echo "$notocjkvffonts" echo echo 'For CJK pages in PDF, they need to be hidden from XeTeX by denylisting.' echo 'Or, CJK pages can be skipped by uninstalling texlive-xecjk.' From 7f20ac18cdaa63a1e8fcb9f7a9dc9e160e16c106 Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Sat, 27 Apr 2024 13:37:02 +0800 Subject: [PATCH 878/969] docs/zh_CN: remove two inconsistent spaces The spaces on the left and right of texts should be consistent. Remove these redundent spaces. Signed-off-by: Dongliang Mu Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240427053703.2339727-1-dzm91@hust.edu.cn --- Documentation/translations/zh_CN/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/translations/zh_CN/index.rst b/Documentation/translations/zh_CN/index.rst index 6ccec9657cc6..20b9d4270d1f 100644 --- a/Documentation/translations/zh_CN/index.rst +++ b/Documentation/translations/zh_CN/index.rst @@ -24,8 +24,8 @@ 上的linux-doc邮件列表。 顺便说下，中文文档也需要遵守内核编码风格，风格中中文和英文的主要不同就是中文 -的字符标点占用两个英文字符宽度， 所以，当英文要求不要超过每行100个字符时， -中文就不要超过50个字符。另外，也要注意'-'，'=' 等符号与相关标题的对齐。在将 +的字符标点占用两个英文字符宽度，所以，当英文要求不要超过每行100个字符时， +中文就不要超过50个字符。另外，也要注意'-'，'='等符号与相关标题的对齐。在将 补丁提交到社区之前，一定要进行必要的 ``checkpatch.pl`` 检查和编译测试。 与Linux 内核社区一起工作 From 10466b17af6567448c2ade4265c90760539fb787 Mon Sep 17 00:00:00 2001 From: "Bird, Tim" Date: Fri, 26 Apr 2024 23:18:14 +0000 Subject: [PATCH 879/969] docs: stable-kernel-rules: fix typo sent->send Change 'sent' to 'send' Signed-off-by: Tim Bird Link: https://lore.kernel.org/r/SA3PR13MB63726A746C847D7C0919C25BFD162@SA3PR13MB6372.namprd13.prod.outlook.com Reviewed-by: Greg Kroah-Hartman Signed-off-by: Jonathan Corbet --- Documentation/process/stable-kernel-rules.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/process/stable-kernel-rules.rst b/Documentation/process/stable-kernel-rules.rst index 9ca8083b41c7..edf90bbe30f4 100644 --- a/Documentation/process/stable-kernel-rules.rst +++ b/Documentation/process/stable-kernel-rules.rst @@ -79,7 +79,7 @@ it reduces the chance of accidentally exposing the fix to the public by way of Once the patch is mainlined it will be applied to the stable tree without anything else needing to be done by the author or subsystem maintainer. -To sent additional instructions to the stable team, use a shell-style inline +To send additional instructions to the stable team, use a shell-style inline comment to pass arbitrary or predefined notes: * Specify any additional patch prerequisites for cherry picking:: From f7771eba325dd2c75f0f2469342b96002e31710f Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Fri, 26 Apr 2024 14:59:48 +0800 Subject: [PATCH 880/969] docs/zh_CN/rust: Update the translation of arch-support to 6.9-rc4 Update to commit 81889e8523e6 ("RISC-V: enable building 64-bit kernels with rust support") commit 01848eee20c6 ("docs: rust: fix improper rendering in Arch Supportpage") commit 724a75ac9542 ("arm64: rust: Enable Rust support for AArch64") commit 90868ff9cade ("LoongArch: Enable initial Rust support") commit e5e86572e3f2 ("rust: sort uml documentation arch support table") commit 04df97e150c8 ("Documentation: rust: Fix arch support table") commit 0438aadfa69a ("rust: arch/um: Add support for CONFIG_RUST under x86_64 UML") Signed-off-by: Yanteng Si Reviewed-by: Dongliang Mu Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/e61eee747275c4e258416e079315b8e23fe3fde5.1714113680.git.siyanteng@loongson.cn --- .../translations/zh_CN/rust/arch-support.rst | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/Documentation/translations/zh_CN/rust/arch-support.rst b/Documentation/translations/zh_CN/rust/arch-support.rst index afbd02afec45..abd708d48f82 100644 --- a/Documentation/translations/zh_CN/rust/arch-support.rst +++ b/Documentation/translations/zh_CN/rust/arch-support.rst @@ -16,8 +16,12 @@ 下面是目前可以工作的架构的一般总结。支持程度与 ``MAINTAINERS`` 文件中的``S`` 值相对应: -============ ================ ============================================== -架构 支持水平 限制因素 -============ ================ ============================================== -``x86`` Maintained 只有 ``x86_64`` -============ ================ ============================================== +============= ================ ============================================== +架构 支持水平 限制因素 +============= ================ ============================================== +``arm64`` Maintained 只有小端序 +``loongarch`` Maintained \- +``riscv`` Maintained 只有 ``riscv64`` +``um`` Maintained 只有 ``x86_64`` +``x86`` Maintained 只有 ``x86_64`` +============= ================ ============================================== From 88bfcfa43ab67601d38917d9344723e344b257d8 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Fri, 26 Apr 2024 14:59:49 +0800 Subject: [PATCH 881/969] docs/zh_CN/rust: Update the translation of coding-guidelines to 6.9-rc4 Update to commit bc2e7d5c298a ("rust: support `srctree`-relative links") Signed-off-by: Yanteng Si Reviewed-by: Dongliang Mu Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/e83b5dd929371d42889b19750e5e0385544e170f.1714113680.git.siyanteng@loongson.cn --- .../translations/zh_CN/rust/coding-guidelines.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/translations/zh_CN/rust/coding-guidelines.rst b/Documentation/translations/zh_CN/rust/coding-guidelines.rst index 6c0bdbbc5a2a..419143b938ed 100644 --- a/Documentation/translations/zh_CN/rust/coding-guidelines.rst +++ b/Documentation/translations/zh_CN/rust/coding-guidelines.rst @@ -157,6 +157,18 @@ https://commonmark.org/help/ https://doc.rust-lang.org/rustdoc/how-to-write-documentation.html +此外，内核支持通过在链接目标前添加 ``srctree/`` 来创建相对于源代码树的链接。例如: + +.. code-block:: rust + + //! C header: [`include/linux/printk.h`](srctree/include/linux/printk.h) + +或者: + +.. code-block:: rust + + /// [`struct mutex`]: srctree/include/linux/mutex.h + 命名 ---- From 914819526febff081b1ea96df7cbd3eb06817d61 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Fri, 26 Apr 2024 15:02:12 +0800 Subject: [PATCH 882/969] docs/zh_CN/rust: Update the translation of general-information to 6.9-rc4 Update to commit ba4abeb13d5e ("docs: rust: Move testing to a separate page") commit be412baf7240 ("docs: rust: Add rusttest info") commit bd9e54a42ce2 ("docs: rust: update Rust docs output path") Signed-off-by: Yanteng Si Reviewed-by: Dongliang Mu Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/09fc6c2e0553fb5fae9c91146e1bceb149b6cf71.1714113680.git.siyanteng@loongson.cn --- Documentation/translations/zh_CN/rust/general-information.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/translations/zh_CN/rust/general-information.rst b/Documentation/translations/zh_CN/rust/general-information.rst index 6b91dfe1834a..251f6ee2bb44 100644 --- a/Documentation/translations/zh_CN/rust/general-information.rst +++ b/Documentation/translations/zh_CN/rust/general-information.rst @@ -32,7 +32,7 @@ Rust内核代码使用其内置的文档生成器 ``rustdoc`` 进行记录。 要在你的网络浏览器中本地阅读该文档，请运行如:: - xdg-open rust/doc/kernel/index.html + xdg-open Documentation/output/rust/rustdoc/kernel/index.html 要了解如何编写文档，请看 coding-guidelines.rst 。 From 55b8d0a33227bea08c327ee9f6c31491e8627818 Mon Sep 17 00:00:00 2001 From: Yanteng Si Date: Fri, 26 Apr 2024 15:02:35 +0800 Subject: [PATCH 883/969] docs/zh_CN/rust: Update the translation of quick-start to 6.9-rc4 Update to commit 711cbfc71765 ("docs: rust: Clarify that 'rustup override' applies to build directory") commit 7583ce66ddf7 ("docs: rust: remove `CC=clang` mentions") commit 2285eb2f2429 ("docs: rust: clarify what 'rustup override' does") commit 8cb40124cf92 ("docs: rust: update instructions for obtaining 'core' source") commit b603c6cc405a ("docs: rust: add command line to rust-analyzer section") commit 08ab786556ff ("rust: bindgen: upgrade to 0.65.1") commit eae90172c5b8 ("docs: rust: add paragraph about finding a suitable `libclang`") commit 6883b29c6cae ("docs: rust: point directly to the standalone installers") Signed-off-by: Yanteng Si Reviewed-by: Dongliang Mu Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/aff560c262f255e873c07cc66891cf8140ad433d.1714113680.git.siyanteng@loongson.cn --- .../translations/zh_CN/rust/quick-start.rst | 50 +++++++++++++------ 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/Documentation/translations/zh_CN/rust/quick-start.rst b/Documentation/translations/zh_CN/rust/quick-start.rst index a4b8e8a50a89..8616556ae4d7 100644 --- a/Documentation/translations/zh_CN/rust/quick-start.rst +++ b/Documentation/translations/zh_CN/rust/quick-start.rst @@ -37,13 +37,18 @@ rustc 需要一个特定版本的Rust编译器。较新的版本可能会也可能不会工作，因为就目前而言，内核依赖 于一些不稳定的Rust特性。 -如果使用的是 ``rustup`` ，请进入检出的源代码目录并运行:: +如果使用的是 ``rustup`` ，请进入内核编译目录（或者用 ``--path=`` 参数 +来 ``设置`` sub-command)并运行:: rustup override set $(scripts/min-tool-version.sh rustc) -或者从以下网址获取一个独立的安装程序或安装 ``rustup`` ： ++这将配置你的工作目录使用正确版本的 ``rustc``，而不影响你的默认工具链。 - https://www.rust-lang.org +请注意覆盖应用当前的工作目录（和它的子目录）。 + +如果你使用 ``rustup``， 可以从下面的链接拉取一个单独的安装程序: + + https://forge.rust-lang.org/infra/other-installation-methods.html#standalone Rust标准库源代码 @@ -57,21 +62,23 @@ Rust标准库的源代码是必需的，因为构建系统会交叉编译 ``core 这些组件是按工具链安装的，因此以后升级Rust编译器版本需要重新添加组件。 -否则，如果使用独立的安装程序，可以将Rust仓库克隆到工具链的安装文件夹中:: +否则，如果使用独立的安装程序，可以将Rust源码树下载到安装工具链的文件夹中:: - git clone --recurse-submodules \ - --branch $(scripts/min-tool-version.sh rustc) \ - https://github.com/rust-lang/rust \ - $(rustc --print sysroot)/lib/rustlib/src/rust + curl -L "https://static.rust-lang.org/dist/rust-src-$(scripts/min-tool-version.sh rustc).tar.gz" | + tar -xzf - -C "$(rustc --print sysroot)/lib" \ + "rust-src-$(scripts/min-tool-version.sh rustc)/rust-src/lib/" \ + --strip-components=3 -在这种情况下，以后升级Rust编译器版本需要手动更新这个克隆的仓库。 +在这种情况下，以后升级Rust编译器版本需要手动更新这个源代码树（这可以通过移除 +``$(rustc --print sysroot)/lib/rustlib/src/rust`` ，然后重新执行上 +面的命令做到）。 libclang ******** ``bindgen`` 使用 ``libclang`` （LLVM的一部分）来理解内核中的C代码，这意味着需要安 -装LLVM；同在开启 ``CC=clang`` 或 ``LLVM=1`` 时编译内核一样。 +装LLVM；同在开启``LLVM=1`` 时编译内核一样。 Linux发行版中可能会有合适的包，所以最好先检查一下。 @@ -94,7 +101,20 @@ bindgen 通过以下方式安装它（注意，这将从源码下载并构建该工具）:: - cargo install --locked --version $(scripts/min-tool-version.sh bindgen) bindgen + cargo install --locked --version $(scripts/min-tool-version.sh bindgen) bindgen-cli + +``bindgen`` 需要找到合适的 ``libclang`` 才能工作。如果没有找到（或者找到的 +``libclang`` 与应该使用的 ``libclang`` 不同），则可以使用 ``clang-sys`` +理解的环境变量（Rust绑定创建的 ``bindgen`` 用来访问 ``libclang``）: + + +* ``LLVM_CONFIG_PATH`` 可以指向一个 ``llvm-config`` 可执行文件。 + +* 或者 ``LIBCLANG_PATH`` 可以指向 ``libclang`` 共享库或包含它的目录。 + +* 或者 ``CLANG_PATH`` 可以指向 ``clang`` 可执行文件。 + +详情请参阅 ``clang-sys`` 的文档: 开发依赖 @@ -163,7 +183,9 @@ rust-analyzer 一起使用，以实现语法高亮、补全、转到定义和其他功能。 ``rust-analyzer`` 需要一个配置文件， ``rust-project.json``, 它可以由 ``rust-analyzer`` -Make 目标生成。 +Make 目标生成:: + + make LLVM=1 rust-analyzer 配置 @@ -189,10 +211,6 @@ Rust支持（CONFIG_RUST）需要在 ``General setup`` 菜单中启用。在其 make LLVM=1 -对于不支持完整LLVM工具链的架构，使用:: - - make CC=clang - 使用GCC对某些配置也是可行的，但目前它是非常试验性的。 From fb73c312a939cfcf9bae0d88fdb382516b424e50 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 22 Apr 2024 19:18:25 +0200 Subject: [PATCH 884/969] arm64: defconfig: enable Khadas TS050 panel as module Enable the Khadas TS050 panel driver as module since it's required to use the TS050 panel on the Khadas VIM3 and VIM3L boards. Link: https://lore.kernel.org/r/20240422-amlogic-v6-9-upstream-deconfig-dsi-v1-1-01511908477c@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2c30d617e180..76c687ae8b89 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -865,6 +865,7 @@ CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m +CONFIG_DRM_PANEL_KHADAS_TS050=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m From 1665b303a00c1acb2fe126486c6256c755f0b7c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:46 +0100 Subject: [PATCH 885/969] arm64: dts: exynos: gs101: specify bus clock for pinctrl (far) alive MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-1-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 16e1c474e8dd..09f6b33cf5b4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1390,6 +1390,8 @@ pinctrl_gpio_alive: pinctrl@174d0000 { compatible = "google,gs101-pinctrl"; reg = <0x174d0000 0x00001000>; + clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; + clock-names = "pclk"; wakeup-interrupt-controller { compatible = "google,gs101-wakeup-eint", @@ -1401,6 +1403,8 @@ pinctrl_far_alive: pinctrl@174e0000 { compatible = "google,gs101-pinctrl"; reg = <0x174e0000 0x00001000>; + clocks = <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK>; + clock-names = "pclk"; wakeup-interrupt-controller { compatible = "google,gs101-wakeup-eint", From 42e3f188b238b7fb1c42dee8b4dc4107cbb321e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:47 +0100 Subject: [PATCH 886/969] arm64: dts: exynos: gs101: specify bus clock for pinctrl_peric[01] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-2-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 09f6b33cf5b4..878e05a865a0 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -370,6 +370,8 @@ pinctrl_peric0: pinctrl@10840000 { compatible = "google,gs101-pinctrl"; reg = <0x10840000 0x00001000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK>; + clock-names = "pclk"; interrupts = ; }; @@ -914,6 +916,8 @@ pinctrl_peric1: pinctrl@10c40000 { compatible = "google,gs101-pinctrl"; reg = <0x10c40000 0x00001000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK>; + clock-names = "pclk"; interrupts = ; }; From 8120dc4656aedf86c24e1b5776f84fdd9f8ece80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:48 +0100 Subject: [PATCH 887/969] arm64: dts: exynos: gs101: specify bus clock for pinctrl_hsi2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bus clock is needed for pinctrl register access to work. Add it. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 878e05a865a0..9edda5b94abc 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1333,6 +1333,8 @@ pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_GPIO_HSI2_PCLK>; + clock-names = "pclk"; interrupts = ; }; From 4db286b0a29aa3576a401b637ac5910dac22117f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Draszik?= Date: Tue, 30 Apr 2024 10:49:49 +0100 Subject: [PATCH 888/969] arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinctrl instances hsi1, gsactrl, and gsacore need a clock for register access to work. Since we haven't implemented the relevant CMUs for the clocks required by these instances just add empty clocks for now so as to make the DT pass the validation checks. Once the clocks are implmented in the gs101 clock driver, these should be updated then. Signed-off-by: André Draszik Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9edda5b94abc..a66e996666b8 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1309,6 +1309,9 @@ pinctrl_hsi1: pinctrl@11840000 { compatible = "google,gs101-pinctrl"; reg = <0x11840000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; interrupts = ; }; @@ -1422,11 +1425,17 @@ pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; }; pinctrl_gsacore: pinctrl@17a80000 { compatible = "google,gs101-pinctrl"; reg = <0x17a80000 0x00001000>; + /* TODO: update once support for this CMU exists */ + clocks = <0>; + clock-names = "pclk"; }; cmu_top: clock-controller@1e080000 { From c0c153e341d2a82241bf0a0b78117ceeb29be3eb Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 28 Apr 2024 20:36:17 +0800 Subject: [PATCH 889/969] dt-bindings: arm: rockchip: add Radxa ROCK 3C The Radxa ROCK 3C is a similar board to the Radxa ROCK 3A with the Rockchip RK3566 SoC. Add devicetree binding documentation for it. Signed-off-by: Chukun Pan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240428123618.72170-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 1bbbaf81134b..e04c213a0dee 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -799,6 +799,11 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 + - description: Radxa ROCK 3C + items: + - const: radxa,rock-3c + - const: rockchip,rk3566 + - description: Radxa ROCK 5A items: - const: radxa,rock-5a From ee219017ddb50be14c60d3cbe3e51ac0b2008d40 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 28 Apr 2024 20:36:18 +0800 Subject: [PATCH 890/969] arm64: dts: rockchip: Add Radxa ROCK 3C The Radxa ROCK 3C is a development board with the Rockchip RK3566 SoC. It has the following features: - 1/2/4GB LPDDR4 - 1x HDMI Type A - 1x PCIE 2.0 slot - 1x FAN connector - 3.5mm jack with mic - 1GbE RTL8211F Ethernet - 1x USB 3.0, 3x USB 2.0 - 40-pin expansion header - MicroSD card/eMMC socket - 16MB SPI NOR (gd25lq128d) - AP6256 or AIC8800 WiFi/BT Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240428123618.72170-3-amadeus@jmu.edu.cn [dropped rk809-sound and not specified pmic sound properties] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-rock-3c.dts | 726 ++++++++++++++++++ 2 files changed, 727 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 0624c72840b8..f42fa62b4064 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rock-3c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts new file mode 100644 index 000000000000..b242409d378c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Radxa ROCK 3C"; + compatible = "radxa,rock-3c", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v_dcin>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en>; + regulator-name = "vcc5v0_usb30_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_cam: vcc-cam-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam_en>; + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: vcc-mipi-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_mipi_en>; + regulator-name = "vcc_mipi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_h: bt-host-wake-h { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam { + vcc_cam_en: vcc_cam_en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + display { + vcc_mipi_en: vcc_mipi_en { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led2: user-led2 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb30_host_en: vcc5v0-usb30-host-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_h: wifi-host-wake-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <120000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 3cd1ed57ce70dd64bd1dfb69cbb3173bf4fe0582 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 2 May 2024 09:42:37 +0000 Subject: [PATCH 891/969] arm64: dts: rockchip: Support poweroff on Edgeble Neural Compute Module On Edgeble Neural Compute Module add system-power-controller property to RK806 pmic so that these chips can power off the device. Cc: Jagan Teki Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20240502094246.4695-1-anand@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi index d9bf67525e86..709d348cf06b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -162,6 +162,8 @@ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>; vcc3-supply = <&vcc5v0_sys>; From 7676e12650055f4eff5f2cccdf9903981619553e Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Thu, 2 May 2024 09:42:38 +0000 Subject: [PATCH 892/969] arm64: dts: rockchip: Add USB3 on Edgeble NCM6A-IO board Add the proper nodes to activate the USB 3.0 ports on the Edgeble NCM6A-IO board. Cc: Jagan Teki Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20240502094246.4695-2-anand@edgeble.ai Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 963e880ccc12..7b1317898358 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -68,6 +68,10 @@ status = "okay"; }; +&combphy2_psu { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -230,3 +234,7 @@ &usb_host1_ohci { status = "okay"; }; + +&usb_host2_xhci { + status = "okay"; +}; From 4aae6cdd61aa0daa2f01d1660be8f22b88b61929 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Wed, 1 May 2024 17:22:41 +0300 Subject: [PATCH 893/969] arm64: dts: rockchip: enable GPU on khadas-edge2 Enable the Mali GPU node on Khadas Edge 2. Signed-off-by: Muhammed Efe Cetin Link: https://lore.kernel.org/r/20240501142241.98554-1-efectn@6tel.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index ea085abb98ec..dbddfc3bb464 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -176,6 +176,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; From 8beafb228f2be5de03e73178ac1081847d0d411f Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Thu, 25 Apr 2024 17:29:13 -0500 Subject: [PATCH 894/969] arm64: dts: rockchip: Enable GPU on Orange Pi 5 Enable the Mali GPU in the Orange Pi 5 Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20240425222913.1760-1-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts index 73700d77eed9..3770a607e4fc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -146,6 +146,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; From c57d1a970275aabfbfab4c56001394ada3456d8e Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Wed, 17 Apr 2024 22:52:33 -0500 Subject: [PATCH 895/969] arm64: dts: rockchip: add USB-C support to rk3588s-orangepi-5 Add support for using the Orange Pi 5 USB-C port for USB in OHCI, EHCI or XHCI mode. Displayport AltMode is not yet supported. Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20240418035232.35344-2-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts index 3770a607e4fc..feea6b20a6bf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -6,6 +6,7 @@ #include #include #include +#include #include "rk3588s.dtsi" / { @@ -217,6 +218,56 @@ pinctrl-0 = <&i2c6m3_xfer>; status = "okay"; + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "source"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; @@ -630,6 +681,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -651,6 +710,29 @@ status = "okay"; }; +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + &usb_host0_ehci { status = "okay"; }; @@ -659,6 +741,18 @@ status = "okay"; }; +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + &usb_host1_ehci { status = "okay"; }; From 6c7676a2d3cde81f02e2cb7ac40ca5a99c107dec Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 9 Apr 2024 20:00:03 +0800 Subject: [PATCH 896/969] arm64: dts: rockchip: enable onboard spi flash for rock-3a There is a mx25u12835f spi flash on this board, enable it. [ 2.525805] spi-nor spi4.0: mx25u12835f (16384 Kbytes) Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20240409120003.309358-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index ccc4119ca43a..ebdedea15ad1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -757,6 +757,20 @@ status = "okay"; }; +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <0>; From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 2 May 2024 16:02:32 +0200 Subject: [PATCH 897/969] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs The mmu600_pcie is connected with the five PCIe controllers. The mmu600_php is connected with the USB3 controller, the GMAC controllers, and the SATA controllers. See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual). The IOMMUs are disabled by default, as further patches are needed to program the SID/SSIDs in to the IOMMUs. iommu: Default domain type: Translated iommu: DMA domain TLB invalidation policy: strict mode arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf) arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs Additionally, the IOMMU correctly triggers an IOMMU fault when a PCIe device performs a write (since the device hasn't been assigned a SID/SSID): arm-smmu-v3 fc900000.iommu: event 0x02 received: arm-smmu-v3 fc900000.iommu: 0x0000010000000002 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 arm-smmu-v3 fc900000.iommu: 0x0000000000000000 While this doesn't provide much value as is, having the devices as disabled in the device tree will allow developers to see that the rk3588 actually has IOMMUs on the SoC. Signed-off-by: Niklas Cassel Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index b0a59ec5183b..6ac5ac8b48ab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -579,6 +579,30 @@ status = "disabled"; }; + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + pmu1grf: syscon@fd58a000 { compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfd58a000 0x0 0x10000>; From 5d7531517427429e31d7bb84c00b0c7bec30e280 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Tue, 30 Jan 2024 14:25:43 -0500 Subject: [PATCH 898/969] alpha: sort scr_mem{cpy,move}w() out Take scr_memmove() out of line, make both it and scr_memcpyw() conditional upon VGA_CONSOLE or MDA_CONSOLE (if neither is selected, we are certain to be working with the kernel-allocated buffer rather than VRAM and defaults will work just fine). That allows to clean vt_buffer.h, but that's a separate story Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/include/asm/vga.h | 2 ++ arch/alpha/kernel/io.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/alpha/include/asm/vga.h b/arch/alpha/include/asm/vga.h index 4c347a8454c7..919931cb5b63 100644 --- a/arch/alpha/include/asm/vga.h +++ b/arch/alpha/include/asm/vga.h @@ -13,6 +13,7 @@ #define VT_BUF_HAVE_RW #define VT_BUF_HAVE_MEMSETW #define VT_BUF_HAVE_MEMCPYW +#define VT_BUF_HAVE_MEMMOVEW static inline void scr_writew(u16 val, volatile u16 *addr) { @@ -40,6 +41,7 @@ static inline void scr_memsetw(u16 *s, u16 c, unsigned int count) /* Do not trust that the usage will be correct; analyze the arguments. */ extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count); +extern void scr_memmovew(u16 *d, const u16 *s, unsigned int count); /* ??? These are currently only used for downloading character sets. As such, they don't need memory barriers. Is this all they are intended diff --git a/arch/alpha/kernel/io.c b/arch/alpha/kernel/io.c index eda09778268f..c28035d6d1e6 100644 --- a/arch/alpha/kernel/io.c +++ b/arch/alpha/kernel/io.c @@ -647,6 +647,10 @@ void _memset_c_io(volatile void __iomem *to, unsigned long c, long count) EXPORT_SYMBOL(_memset_c_io); +#if IS_ENABLED(CONFIG_VGA_CONSOLE) || IS_ENABLED(CONFIG_MDA_CONSOLE) + +#include + /* A version of memcpy used by the vga console routines to move data around arbitrarily between screen and main memory. */ @@ -681,6 +685,21 @@ scr_memcpyw(u16 *d, const u16 *s, unsigned int count) EXPORT_SYMBOL(scr_memcpyw); +void scr_memmovew(u16 *d, const u16 *s, unsigned int count) +{ + if (d < s) + scr_memcpyw(d, s, count); + else { + count /= 2; + d += count; + s += count; + while (count--) + scr_writew(scr_readw(--s), --d); + } +} +EXPORT_SYMBOL(scr_memmovew); +#endif + void __iomem *ioport_map(unsigned long port, unsigned int size) { return IO_CONCAT(__IO_PREFIX,ioportmap) (port); From 397c66c2c989ff98a5016c69cb1547676d596fd1 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 18 Dec 2023 22:59:26 -0500 Subject: [PATCH 899/969] alpha: fix modversions for strcpy() et.al. On alpha str{n,}{cpy,cat}() implementations are playing fun games with shared chunks of code. The problem is, they are using direct branches and need to be next to each other. Currently it's done by building them in separate object files, then using ld -r to link those together. Unfortunately, genksyms machinery has no idea what to do with that - we have generated in arch/alpha/lib/.strcat.S.cmd, but there's nothing to propagate that into .stycpy.S.cmd, so modpost doesn't find anything for those symbols, resulting in WARNING: modpost: EXPORT symbol "strcpy" [vmlinux] version generation failed, symbol will not be versioned. Is "strcpy" prototyped in ? WARNING: modpost: EXPORT symbol "strcat" [vmlinux] version generation failed, symbol will not be versioned. Is "strcat" prototyped in ? WARNING: modpost: EXPORT symbol "strncpy" [vmlinux] version generation failed, symbol will not be versioned. Is "strncpy" prototyped in ? WARNING: modpost: EXPORT symbol "strncat" [vmlinux] version generation failed, symbol will not be versioned. Is "strncat" prototyped in ? spew on modversion-enabled builds (all 4 functions in question are in fact prototyped in asm-prototypes.h) Fixing doesn't require messing with kbuild, thankfully - just build one object (i.e. have sty{n,}cpy.S with includes of relevant *.S instead of playing with ld -r) and that's it. Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/lib/Makefile | 14 -------------- arch/alpha/lib/stycpy.S | 11 +++++++++++ arch/alpha/lib/styncpy.S | 11 +++++++++++ 3 files changed, 22 insertions(+), 14 deletions(-) create mode 100644 arch/alpha/lib/stycpy.S create mode 100644 arch/alpha/lib/styncpy.S diff --git a/arch/alpha/lib/Makefile b/arch/alpha/lib/Makefile index 6a779b9018fd..84046e730e6d 100644 --- a/arch/alpha/lib/Makefile +++ b/arch/alpha/lib/Makefile @@ -44,17 +44,3 @@ AFLAGS___remlu.o = -DREM -DINTSIZE $(addprefix $(obj)/,__divqu.o __remqu.o __divlu.o __remlu.o): \ $(src)/$(ev6-y)divide.S FORCE $(call if_changed_rule,as_o_S) - -# There are direct branches between {str*cpy,str*cat} and stx*cpy. -# Ensure the branches are within range by merging these objects. - -LDFLAGS_stycpy.o := -r -LDFLAGS_styncpy.o := -r - -$(obj)/stycpy.o: $(obj)/strcpy.o $(obj)/$(ev67-y)strcat.o \ - $(obj)/$(ev6-y)stxcpy.o FORCE - $(call if_changed,ld) - -$(obj)/styncpy.o: $(obj)/strncpy.o $(obj)/$(ev67-y)strncat.o \ - $(obj)/$(ev6-y)stxncpy.o FORCE - $(call if_changed,ld) diff --git a/arch/alpha/lib/stycpy.S b/arch/alpha/lib/stycpy.S new file mode 100644 index 000000000000..32ecd9c5f90d --- /dev/null +++ b/arch/alpha/lib/stycpy.S @@ -0,0 +1,11 @@ +#include "strcpy.S" +#ifdef CONFIG_ALPHA_EV67 +#include "ev67-strcat.S" +#else +#include "strcat.S" +#endif +#ifdef CONFIG_ALPHA_EV6 +#include "ev6-stxcpy.S" +#else +#include "stxcpy.S" +#endif diff --git a/arch/alpha/lib/styncpy.S b/arch/alpha/lib/styncpy.S new file mode 100644 index 000000000000..72fc2754eb57 --- /dev/null +++ b/arch/alpha/lib/styncpy.S @@ -0,0 +1,11 @@ +#include "strncpy.S" +#ifdef CONFIG_ALPHA_EV67 +#include "ev67-strncat.S" +#else +#include "strncat.S" +#endif +#ifdef CONFIG_ALPHA_EV6 +#include "ev6-stxncpy.S" +#else +#include "stxncpy.S" +#endif From b973afe9d805d04230f55743bda1e34ce5ff8940 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Wed, 24 Jan 2024 10:57:02 -0500 Subject: [PATCH 900/969] alpha: add clone3() support Since clone3() needs the full register state saved for copying into the child, it needs the same kind of wrapper as fork(), vfork() and clone(). Exact same wrapper works, actually... Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/entry.S | 1 + arch/alpha/kernel/syscalls/syscall.tbl | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S index eb51f93a70c8..dd26062d75b3 100644 --- a/arch/alpha/kernel/entry.S +++ b/arch/alpha/kernel/entry.S @@ -811,6 +811,7 @@ alpha_\name: fork_like fork fork_like vfork fork_like clone +fork_like clone3 .macro sigreturn_like name .align 4 diff --git a/arch/alpha/kernel/syscalls/syscall.tbl b/arch/alpha/kernel/syscalls/syscall.tbl index 8ff110826ce2..26cce7e7f70b 100644 --- a/arch/alpha/kernel/syscalls/syscall.tbl +++ b/arch/alpha/kernel/syscalls/syscall.tbl @@ -474,7 +474,7 @@ 542 common fsmount sys_fsmount 543 common fspick sys_fspick 544 common pidfd_open sys_pidfd_open -# 545 reserved for clone3 +545 common clone3 alpha_clone3 546 common close_range sys_close_range 547 common openat2 sys_openat2 548 common pidfd_getfd sys_pidfd_getfd From 5759b57f03ca07b465dc394112d8f383ef671a82 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Wed, 24 Jan 2024 11:01:00 -0500 Subject: [PATCH 901/969] alpha: don't make functions public without a reason if it's really used only inside the same source file, make it static... Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/core_cia.c | 6 +++--- arch/alpha/kernel/core_marvel.c | 2 +- arch/alpha/kernel/core_wildfire.c | 8 ++++---- arch/alpha/kernel/perf_event.c | 2 +- arch/alpha/kernel/smc37c669.c | 4 +++- arch/alpha/kernel/sys_nautilus.c | 6 +++--- arch/alpha/kernel/sys_sio.c | 2 +- drivers/char/agp/alpha-agp.c | 2 +- 8 files changed, 17 insertions(+), 15 deletions(-) diff --git a/arch/alpha/kernel/core_cia.c b/arch/alpha/kernel/core_cia.c index 12926e9538b8..ca3d9c732b61 100644 --- a/arch/alpha/kernel/core_cia.c +++ b/arch/alpha/kernel/core_cia.c @@ -280,7 +280,7 @@ cia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) #define CIA_BROKEN_TBIA_SIZE 1024 /* Always called with interrupts disabled */ -void +static void cia_pci_tbi_try2(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) { @@ -576,7 +576,7 @@ struct } window[4]; } saved_config __attribute((common)); -void +static void cia_save_srm_settings(int is_pyxis) { int i; @@ -602,7 +602,7 @@ cia_save_srm_settings(int is_pyxis) mb(); } -void +static void cia_restore_srm_settings(void) { int i; diff --git a/arch/alpha/kernel/core_marvel.c b/arch/alpha/kernel/core_marvel.c index e9348aec4649..b22248044bf0 100644 --- a/arch/alpha/kernel/core_marvel.c +++ b/arch/alpha/kernel/core_marvel.c @@ -355,7 +355,7 @@ marvel_init_io7(struct io7 *io7) } } -void __init +static void __init marvel_io7_present(gct6_node *node) { int pe; diff --git a/arch/alpha/kernel/core_wildfire.c b/arch/alpha/kernel/core_wildfire.c index 3a804b67f9da..8dd08c5e4270 100644 --- a/arch/alpha/kernel/core_wildfire.c +++ b/arch/alpha/kernel/core_wildfire.c @@ -59,7 +59,7 @@ unsigned long wildfire_pca_mask; unsigned long wildfire_cpu_mask; unsigned long wildfire_mem_mask; -void __init +static void __init wildfire_init_hose(int qbbno, int hoseno) { struct pci_controller *hose; @@ -137,7 +137,7 @@ wildfire_init_hose(int qbbno, int hoseno) wildfire_pci_tbi(hose, 0, 0); /* Flush TLB at the end. */ } -void __init +static void __init wildfire_init_pca(int qbbno, int pcano) { @@ -154,7 +154,7 @@ wildfire_init_pca(int qbbno, int pcano) wildfire_init_hose(qbbno, (pcano << 1) + 1); } -void __init +static void __init wildfire_init_qbb(int qbbno) { int pcano; @@ -176,7 +176,7 @@ wildfire_init_qbb(int qbbno) } } -void __init +static void __init wildfire_hardware_probe(void) { unsigned long temp; diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index ccdb508c1516..1f0eb4f25c0f 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -870,7 +870,7 @@ static void alpha_perf_event_irq_handler(unsigned long la_ptr, /* * Init call to initialise performance events at kernel startup. */ -int __init init_hw_perf_events(void) +static int __init init_hw_perf_events(void) { pr_info("Performance events: "); diff --git a/arch/alpha/kernel/smc37c669.c b/arch/alpha/kernel/smc37c669.c index bbbd34586de0..cb8726b667da 100644 --- a/arch/alpha/kernel/smc37c669.c +++ b/arch/alpha/kernel/smc37c669.c @@ -2430,13 +2430,15 @@ int __init smcc669_write( struct FILE *fp, int size, int number, unsigned char * } #endif -void __init +#if SMC_DEBUG +static void __init SMC37c669_dump_registers(void) { int i; for (i = 0; i <= 0x29; i++) printk("-- CR%02x : %02x\n", i, SMC37c669_read_config(i)); } +#endif /*+ * ============================================================================ * = SMC_init - SMC37c669 Super I/O controller initialization = diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c index 96fd6ff3fe81..4dcee81606a5 100644 --- a/arch/alpha/kernel/sys_nautilus.c +++ b/arch/alpha/kernel/sys_nautilus.c @@ -78,7 +78,7 @@ nautilus_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -void +static void nautilus_kill_arch(int mode) { struct pci_bus *bus = pci_isa_hose->bus; @@ -127,7 +127,7 @@ naut_sys_machine_check(unsigned long vector, unsigned long la_ptr, /* Machine checks can come from two sources - those on the CPU and those in the system. They are analysed separately but all starts here. */ -void +static void nautilus_machine_check(unsigned long vector, unsigned long la_ptr) { char *mchk_class; @@ -197,7 +197,7 @@ static struct resource busn_resource = { .flags = IORESOURCE_BUS, }; -void __init +static void __init nautilus_init_pci(void) { struct pci_controller *hose = hose_head; diff --git a/arch/alpha/kernel/sys_sio.c b/arch/alpha/kernel/sys_sio.c index 086488ed83a7..0bf38f868665 100644 --- a/arch/alpha/kernel/sys_sio.c +++ b/arch/alpha/kernel/sys_sio.c @@ -310,7 +310,7 @@ alphabook1_init_pci(void) outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */ } -void +static void sio_kill_arch(int mode) { #if defined(ALPHA_RESTORE_SRM_SETUP) diff --git a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c index c9bf2c219841..f0d0c044731c 100644 --- a/drivers/char/agp/alpha-agp.c +++ b/drivers/char/agp/alpha-agp.c @@ -149,7 +149,7 @@ struct agp_bridge_driver alpha_core_agp_driver = { struct agp_bridge_data *alpha_bridge; -int __init +static int __init alpha_core_agp_setup(void) { alpha_agp_info *agp = alpha_mv.agp_info(); From 0ec60e28711fc23afd3a64e9a402d08fb83188c3 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Thu, 25 Jan 2024 09:09:08 -0500 Subject: [PATCH 902/969] alpha: sys_sio: fix misspelled ifdefs definitions of avanti_mv and noname_mv (and associated ALIAS_MV) are conditional upon the wrong thing - it should be CONFIG_ALPHA_{AVANTI,NONAME}_CH, not CONFIG_ALPHA_{AVANTI,NONAME}. The former is a system type; the latter is for the bits shared by AVANTI with XL and NONAME with ALPHA_BOOK1 resp. We want all those machine vectors defined (but not aliased - see ALIAS_MV() definition for details) for GENERIC build; for system-specfic builds we want only one mv, so avanti_mv should *not* be there for XL; it certainly should not be have alpha_mv aliased to it on such config - xl_mv will be there and alpha_mv can't be aliased to both of those. The same goes for Noname vs. Alphabook1. Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/sys_sio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/alpha/kernel/sys_sio.c b/arch/alpha/kernel/sys_sio.c index 0bf38f868665..c28a6ae1d989 100644 --- a/arch/alpha/kernel/sys_sio.c +++ b/arch/alpha/kernel/sys_sio.c @@ -360,7 +360,7 @@ struct alpha_machine_vector alphabook1_mv __initmv = { ALIAS_MV(alphabook1) #endif -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI) +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI_CH) struct alpha_machine_vector avanti_mv __initmv = { .vector_name = "Avanti", DO_EV4_MMU, @@ -389,7 +389,7 @@ struct alpha_machine_vector avanti_mv __initmv = { ALIAS_MV(avanti) #endif -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME) +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME_CH) struct alpha_machine_vector noname_mv __initmv = { .vector_name = "Noname", DO_EV4_MMU, From 6e8d0237857c6d434de9475aed8cee842b204bd7 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Thu, 25 Jan 2024 09:22:01 -0500 Subject: [PATCH 903/969] alpha: missing includes ... and missing externs in proto.h Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/bugs.c | 1 + arch/alpha/kernel/console.c | 1 + arch/alpha/kernel/core_irongate.c | 1 - arch/alpha/kernel/irq.c | 1 + arch/alpha/kernel/pci-noop.c | 1 + arch/alpha/kernel/proto.h | 31 +++++++++++++++++++++++++++---- arch/alpha/kernel/smc37c669.c | 2 ++ arch/alpha/kernel/smc37c93x.c | 2 ++ arch/alpha/kernel/smp.c | 1 + arch/alpha/kernel/srmcons.c | 2 ++ arch/alpha/kernel/sys_nautilus.c | 2 -- arch/alpha/lib/checksum.c | 1 + arch/alpha/lib/fpreg.c | 1 + arch/alpha/lib/memcpy.c | 3 +++ arch/alpha/math-emu/math.c | 7 +------ arch/alpha/mm/init.c | 2 +- 16 files changed, 45 insertions(+), 14 deletions(-) diff --git a/arch/alpha/kernel/bugs.c b/arch/alpha/kernel/bugs.c index 08cc10d7fa17..e8c51089325f 100644 --- a/arch/alpha/kernel/bugs.c +++ b/arch/alpha/kernel/bugs.c @@ -1,6 +1,7 @@ #include #include +#include #ifdef CONFIG_SYSFS diff --git a/arch/alpha/kernel/console.c b/arch/alpha/kernel/console.c index 5476279329a6..4193f76e9633 100644 --- a/arch/alpha/kernel/console.c +++ b/arch/alpha/kernel/console.c @@ -15,6 +15,7 @@ #include #include "pci_impl.h" +#include "proto.h" #ifdef CONFIG_VGA_HOSE diff --git a/arch/alpha/kernel/core_irongate.c b/arch/alpha/kernel/core_irongate.c index 6b8ed12936b6..05dc4c1b9074 100644 --- a/arch/alpha/kernel/core_irongate.c +++ b/arch/alpha/kernel/core_irongate.c @@ -226,7 +226,6 @@ albacore_init_arch(void) if (memtop > pci_mem) { #ifdef CONFIG_BLK_DEV_INITRD extern unsigned long initrd_start, initrd_end; - extern void *move_initrd(unsigned long); /* Move the initrd out of the way. */ if (initrd_end && __pa(initrd_end) > pci_mem) { diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index 15f2effd6baf..c67047c5d830 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c @@ -28,6 +28,7 @@ #include #include +#include "irq_impl.h" volatile unsigned long irq_err_count; DEFINE_PER_CPU(unsigned long, irq_pmi_count); diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c index ae82061edae9..32ca59a5a704 100644 --- a/arch/alpha/kernel/pci-noop.c +++ b/arch/alpha/kernel/pci-noop.c @@ -17,6 +17,7 @@ #include #include +#include "pci_impl.h" #include "proto.h" diff --git a/arch/alpha/kernel/proto.h b/arch/alpha/kernel/proto.h index 2c89c1c55712..5b1d0d71d479 100644 --- a/arch/alpha/kernel/proto.h +++ b/arch/alpha/kernel/proto.h @@ -15,6 +15,7 @@ struct pt_regs; struct task_struct; struct pci_dev; struct pci_controller; +struct pci_bus; /* core_apecs.c */ extern struct pci_ops apecs_pci_ops; @@ -114,6 +115,9 @@ extern int boot_cpuid; #ifdef CONFIG_VERBOSE_MCHECK extern unsigned long alpha_verbose_mcheck; #endif +#ifdef CONFIG_BLK_DEV_INITRD +extern void * __init move_initrd(unsigned long); +#endif extern struct screen_info vgacon_screen_info; /* srmcons.c */ @@ -128,6 +132,7 @@ extern void unregister_srm_console(void); /* smp.c */ extern void setup_smp(void); extern void handle_ipi(struct pt_regs *); +extern void __init smp_callin(void); /* bios32.c */ /* extern void reset_for_srm(void); */ @@ -139,13 +144,13 @@ extern void common_init_rtc(void); extern unsigned long est_cycle_freq; /* smc37c93x.c */ -extern void SMC93x_Init(void); +extern int __init SMC93x_Init(void); /* smc37c669.c */ -extern void SMC669_Init(int); +extern void __init SMC669_Init(int); /* es1888.c */ -extern void es1888_init(void); +extern void __init es1888_init(void); /* ../lib/fpreg.c */ extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); @@ -166,19 +171,37 @@ extern void entSys(void); extern void entUna(void); extern void entDbg(void); +/* pci.c */ +extern void pcibios_claim_one_bus(struct pci_bus *); + /* ptrace.c */ extern int ptrace_set_bpt (struct task_struct *child); extern int ptrace_cancel_bpt (struct task_struct *child); +extern void syscall_trace_leave(void); +extern unsigned long syscall_trace_enter(void); + +/* signal.c */ +struct sigcontext; +extern void do_sigreturn(struct sigcontext __user *); +struct rt_sigframe; +extern void do_rt_sigreturn(struct rt_sigframe __user *); +extern void do_work_pending(struct pt_regs *, unsigned long, unsigned long, unsigned long); /* traps.c */ extern void dik_show_regs(struct pt_regs *regs, unsigned long *r9_15); extern void die_if_kernel(char *, struct pt_regs *, long, unsigned long *); +extern void do_entInt(unsigned long, unsigned long, unsigned long, struct pt_regs *); +extern void do_entArith(unsigned long, unsigned long, struct pt_regs *); +extern void do_entIF(unsigned long, struct pt_regs *); +extern void do_entDbg(struct pt_regs *); +struct allregs; +extern void do_entUna(void *, unsigned long, unsigned long, struct allregs *); +extern void do_entUnaUser(void __user *, unsigned long, unsigned long, struct pt_regs *); /* sys_titan.c */ extern void titan_dispatch_irqs(u64); /* ../mm/init.c */ -extern void switch_to_system_map(void); extern void srm_paging_stop(void); static inline int diff --git a/arch/alpha/kernel/smc37c669.c b/arch/alpha/kernel/smc37c669.c index cb8726b667da..a5a6ed97a6ce 100644 --- a/arch/alpha/kernel/smc37c669.c +++ b/arch/alpha/kernel/smc37c669.c @@ -11,6 +11,8 @@ #include #include +#include "proto.h" + #if 0 # define DBG_DEVS(args) printk args #else diff --git a/arch/alpha/kernel/smc37c93x.c b/arch/alpha/kernel/smc37c93x.c index 71cd7aca38ce..8028273f0d16 100644 --- a/arch/alpha/kernel/smc37c93x.c +++ b/arch/alpha/kernel/smc37c93x.c @@ -12,6 +12,8 @@ #include #include +#include "proto.h" + #define SMC_DEBUG 0 #if SMC_DEBUG diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c index 8e9dd63b220c..ed06367ece57 100644 --- a/arch/alpha/kernel/smp.c +++ b/arch/alpha/kernel/smp.c @@ -38,6 +38,7 @@ #include #include #include +#include #include "proto.h" #include "irq_impl.h" diff --git a/arch/alpha/kernel/srmcons.c b/arch/alpha/kernel/srmcons.c index feaf89f6936b..3e61073f4b30 100644 --- a/arch/alpha/kernel/srmcons.c +++ b/arch/alpha/kernel/srmcons.c @@ -21,6 +21,8 @@ #include #include +#include "proto.h" + static DEFINE_SPINLOCK(srmcons_callback_lock); static int srm_is_registered_console = 0; diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c index 4dcee81606a5..13b79960b4b9 100644 --- a/arch/alpha/kernel/sys_nautilus.c +++ b/arch/alpha/kernel/sys_nautilus.c @@ -184,8 +184,6 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr) mb(); } -extern void pcibios_claim_one_bus(struct pci_bus *); - static struct resource irongate_mem = { .name = "Irongate PCI MEM", .flags = IORESOURCE_MEM, diff --git a/arch/alpha/lib/checksum.c b/arch/alpha/lib/checksum.c index 3f35c3ed6948..17fa230baeef 100644 --- a/arch/alpha/lib/checksum.c +++ b/arch/alpha/lib/checksum.c @@ -12,6 +12,7 @@ #include #include +#include #include diff --git a/arch/alpha/lib/fpreg.c b/arch/alpha/lib/fpreg.c index 7c08b225261c..eee11fb4c7f1 100644 --- a/arch/alpha/lib/fpreg.c +++ b/arch/alpha/lib/fpreg.c @@ -9,6 +9,7 @@ #include #include #include +#include #if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67) #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); diff --git a/arch/alpha/lib/memcpy.c b/arch/alpha/lib/memcpy.c index cbac3dc6d963..78b6850a9d53 100644 --- a/arch/alpha/lib/memcpy.c +++ b/arch/alpha/lib/memcpy.c @@ -18,6 +18,7 @@ #include #include +#include /* * This should be done in one go with ldq_u*2/mask/stq_u. Do it @@ -150,6 +151,8 @@ static inline void __memcpy_aligned_dn (unsigned long d, unsigned long s, DO_REST_ALIGNED_DN(d,s,n); } +#undef memcpy + void * memcpy(void * dest, const void *src, size_t n) { if (!(((unsigned long) dest ^ (unsigned long) src) & 7)) { diff --git a/arch/alpha/math-emu/math.c b/arch/alpha/math-emu/math.c index 4212258f3cfd..68d420bfd3c0 100644 --- a/arch/alpha/math-emu/math.c +++ b/arch/alpha/math-emu/math.c @@ -4,6 +4,7 @@ #include #include #include +#include #include @@ -45,12 +46,6 @@ #define MISC_TRAPB 0x0000 #define MISC_EXCB 0x0400 -extern unsigned long alpha_read_fp_reg (unsigned long reg); -extern void alpha_write_fp_reg (unsigned long reg, unsigned long val); -extern unsigned long alpha_read_fp_reg_s (unsigned long reg); -extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val); - - #ifdef MODULE MODULE_DESCRIPTION("FP Software completion module"); diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c index a155180d7a83..4fe618446e4c 100644 --- a/arch/alpha/mm/init.c +++ b/arch/alpha/mm/init.c @@ -33,7 +33,7 @@ #include #include -extern void die_if_kernel(char *,struct pt_regs *,long); +#include "../kernel/proto.h" static struct pcb_struct original_pcb; From d92f1456a198a78788b03ff0f40db187dab63e65 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Thu, 25 Jan 2024 09:23:08 -0500 Subject: [PATCH 904/969] alpha: core_lca: take the unused functions out the only user had been drivers/char/h8.c, and that got taken out and shot back in 2004... Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/core_lca.c | 44 ------------------------------------ 1 file changed, 44 deletions(-) diff --git a/arch/alpha/kernel/core_lca.c b/arch/alpha/kernel/core_lca.c index 57e0750419f2..4616b11643d5 100644 --- a/arch/alpha/kernel/core_lca.c +++ b/arch/alpha/kernel/core_lca.c @@ -471,47 +471,3 @@ lca_machine_check(unsigned long vector, unsigned long la_ptr) } #endif /* CONFIG_VERBOSE_MCHECK */ } - -/* - * The following routines are needed to support the SPEED changing - * necessary to successfully manage the thermal problem on the AlphaBook1. - */ - -void -lca_clock_print(void) -{ - long pmr_reg; - - pmr_reg = LCA_READ_PMR; - - printk("Status of clock control:\n"); - printk("\tPrimary clock divisor\t0x%lx\n", LCA_GET_PRIMARY(pmr_reg)); - printk("\tOverride clock divisor\t0x%lx\n", LCA_GET_OVERRIDE(pmr_reg)); - printk("\tInterrupt override is %s\n", - (pmr_reg & LCA_PMR_INTO) ? "on" : "off"); - printk("\tDMA override is %s\n", - (pmr_reg & LCA_PMR_DMAO) ? "on" : "off"); - -} - -int -lca_get_clock(void) -{ - long pmr_reg; - - pmr_reg = LCA_READ_PMR; - return(LCA_GET_PRIMARY(pmr_reg)); - -} - -void -lca_clock_fiddle(int divisor) -{ - long pmr_reg; - - pmr_reg = LCA_READ_PMR; - LCA_SET_PRIMARY_CLOCK(pmr_reg, divisor); - /* lca_norm_clock = divisor; */ - LCA_WRITE_PMR(pmr_reg); - mb(); -} From 20e84a6f3350931859e766e2c8033db48f140c4c Mon Sep 17 00:00:00 2001 From: Al Viro Date: Thu, 25 Jan 2024 09:23:57 -0500 Subject: [PATCH 905/969] alpha: jensen, t2 - make __EXTERN_INLINE same as for the rest We want io.h primitives (readb(), etc.) to be extern inline. However, that requires the backing out-of-line implementation somewhere, preferably kept in sync with the inline ones. The way it's done is __EXTERN_INLINE macro that defaults to extern inline, but can be overridden in compilation unit where the out-of-line instance will be. That works, but it's brittle - we *must* make sure that asm/io.h is the very first include in such compilation units. There'd been a bunch of bugs of that sort in the past. Another issue is the choice of overriding definition for __EXTERN_INLINE; it must be either 'inline' or empty. Either will do for compilation purposes - inline void foo(...) {...} (without extern or static) is going to generate out-of-line instance. The difference is that 'definition without a prototype' heuristics trigger on void foo(void) { ... } but not on inline void foo(void) { ... } Most of the overrides go for 'inline'; in two cases (sys_jensen and core_t2) __EXTERN_INLINE is defined as empty. Without -Wmissing-prototypes it didn't matter, but now that we have that thing always on... Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/core_t2.c | 2 +- arch/alpha/kernel/sys_jensen.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/alpha/kernel/core_t2.c b/arch/alpha/kernel/core_t2.c index 98d5b6ff8a76..3d72d90624f1 100644 --- a/arch/alpha/kernel/core_t2.c +++ b/arch/alpha/kernel/core_t2.c @@ -10,7 +10,7 @@ * Code common to all T2 core logic chips. */ -#define __EXTERN_INLINE +#define __EXTERN_INLINE inline #include #include #undef __EXTERN_INLINE diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c index 5c9c88428124..a1bb1c4a7e93 100644 --- a/arch/alpha/kernel/sys_jensen.c +++ b/arch/alpha/kernel/sys_jensen.c @@ -7,7 +7,7 @@ * * Code supporting the Jensen. */ -#define __EXTERN_INLINE +#define __EXTERN_INLINE inline #include #include #undef __EXTERN_INLINE From 82c525bfafb48bc637100348274d824fda494c70 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Fri, 26 Jan 2024 08:28:19 -0500 Subject: [PATCH 906/969] alpha: trim the unused stuff from asm-offsets.c Out of 21 constants, only 6 are used... Signed-off-by: Al Viro Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/kernel/asm-offsets.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/arch/alpha/kernel/asm-offsets.c b/arch/alpha/kernel/asm-offsets.c index bf1eedd27cf7..4cfeae42c79a 100644 --- a/arch/alpha/kernel/asm-offsets.c +++ b/arch/alpha/kernel/asm-offsets.c @@ -10,35 +10,16 @@ #include #include #include -#include +#include static void __used foo(void) { - DEFINE(TI_TASK, offsetof(struct thread_info, task)); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); - DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); DEFINE(TI_FP, offsetof(struct thread_info, fp)); DEFINE(TI_STATUS, offsetof(struct thread_info, status)); BLANK(); - DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked)); - DEFINE(TASK_CRED, offsetof(struct task_struct, cred)); - DEFINE(TASK_REAL_PARENT, offsetof(struct task_struct, real_parent)); - DEFINE(TASK_GROUP_LEADER, offsetof(struct task_struct, group_leader)); - DEFINE(TASK_TGID, offsetof(struct task_struct, tgid)); - BLANK(); - - DEFINE(CRED_UID, offsetof(struct cred, uid)); - DEFINE(CRED_EUID, offsetof(struct cred, euid)); - DEFINE(CRED_GID, offsetof(struct cred, gid)); - DEFINE(CRED_EGID, offsetof(struct cred, egid)); - BLANK(); - DEFINE(SIZEOF_PT_REGS, sizeof(struct pt_regs)); - DEFINE(PT_PTRACED, PT_PTRACED); - DEFINE(CLONE_VM, CLONE_VM); - DEFINE(CLONE_UNTRACED, CLONE_UNTRACED); - DEFINE(SIGCHLD, SIGCHLD); BLANK(); DEFINE(HAE_CACHE, offsetof(struct alpha_machine_vector, hae_cache)); From f81f335a56a8e90d5cac38b79661e6fbf35249f1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 13 Dec 2023 15:46:35 +0100 Subject: [PATCH 907/969] alpha: remove DECpc AXP150 (Jensen) support This is one of the hackiest Alpha machines, and the only one without PCI support. Removing this allows cleaning up code in eise and tty drivers in addition to the architecture code. Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- Documentation/driver-api/eisa.rst | 4 +- arch/alpha/Kconfig | 18 +- arch/alpha/include/asm/dma-mapping.h | 4 - arch/alpha/include/asm/io.h | 20 +- arch/alpha/include/asm/jensen.h | 363 --------------------------- arch/alpha/kernel/Makefile | 3 +- arch/alpha/kernel/pci-noop.c | 114 --------- arch/alpha/kernel/setup.c | 19 +- arch/alpha/kernel/sys_jensen.c | 237 ----------------- drivers/eisa/Kconfig | 9 +- drivers/eisa/virtual_root.c | 2 +- drivers/input/serio/i8042-io.h | 5 +- drivers/tty/serial/8250/8250.h | 3 - drivers/tty/serial/8250/8250_alpha.c | 21 -- drivers/tty/serial/8250/8250_core.c | 4 - drivers/tty/serial/8250/Makefile | 2 - 16 files changed, 16 insertions(+), 812 deletions(-) delete mode 100644 arch/alpha/include/asm/jensen.h delete mode 100644 arch/alpha/kernel/pci-noop.c delete mode 100644 arch/alpha/kernel/sys_jensen.c delete mode 100644 drivers/tty/serial/8250/8250_alpha.c diff --git a/Documentation/driver-api/eisa.rst b/Documentation/driver-api/eisa.rst index 3eac11b7eb01..b33ebe1ec9ed 100644 --- a/Documentation/driver-api/eisa.rst +++ b/Documentation/driver-api/eisa.rst @@ -196,8 +196,8 @@ eisa_bus.disable_dev virtual_root.force_probe Force the probing code to probe EISA slots even when it cannot find an EISA compliant mainboard (nothing appears on slot 0). Defaults to 0 - (don't force), and set to 1 (force probing) when either - CONFIG_ALPHA_JENSEN or CONFIG_EISA_VLB_PRIMING are set. + (don't force), and set to 1 (force probing) when + CONFIG_EISA_VLB_PRIMING is set. Random notes ============ diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 3afd042150f8..9b8d3ce40c28 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -10,7 +10,7 @@ config ALPHA select ARCH_NO_SG_CHAIN select ARCH_USE_CMPXCHG_LOCKREF select DMA_OPS if PCI - select FORCE_PCI if !ALPHA_JENSEN + select FORCE_PCI select PCI_DOMAINS if PCI select PCI_SYSCALL if PCI select HAVE_ASM_MODVERSIONS @@ -99,7 +99,6 @@ choice EB64+ EB64+ 21064 evaluation board EB66 EB66 21066 evaluation board EB66+ EB66+ 21066 evaluation board - Jensen DECpc 150, DEC 2000 models 300, 500 LX164 AlphaPC164-LX Lynx AS 2100A Miata Personal Workstation 433/500/600 a/au @@ -198,17 +197,6 @@ config ALPHA_EIGER Apparently an obscure OEM single-board computer based on the Typhoon/Tsunami chipset family. Information on it is scanty. -config ALPHA_JENSEN - bool "Jensen" - select HAVE_EISA - help - DEC PC 150 AXP (aka Jensen): This is a very old Digital system - one - of the first-generation Alpha systems. A number of these systems - seem to be available on the second- hand market. The Jensen is a - floor-standing tower system which originally used a 150MHz 21064 It - used programmable logic to interface a 486 EISA I/O bridge to the - CPU. - config ALPHA_LX164 bool "LX164" help @@ -337,7 +325,7 @@ config ALPHA_NONAME config ALPHA_EV4 bool - depends on ALPHA_JENSEN || (ALPHA_SABLE && !ALPHA_GAMMA) || ALPHA_LYNX || ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K + depends on (ALPHA_SABLE && !ALPHA_GAMMA) || ALPHA_LYNX || ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K default y if !ALPHA_LYNX default y if !ALPHA_EV5 @@ -483,7 +471,7 @@ config ALPHA_QEMU config ALPHA_SRM bool "Use SRM as bootloader" if ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS || ALPHA_NONAME depends on TTY - default y if ALPHA_JENSEN || ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL + default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL help There are two different types of booting firmware on Alphas: SRM, which is command line driven, and ARC, which uses menus and arrow diff --git a/arch/alpha/include/asm/dma-mapping.h b/arch/alpha/include/asm/dma-mapping.h index 6ce7e2041685..ad5a59b035cb 100644 --- a/arch/alpha/include/asm/dma-mapping.h +++ b/arch/alpha/include/asm/dma-mapping.h @@ -6,11 +6,7 @@ extern const struct dma_map_ops alpha_pci_ops; static inline const struct dma_map_ops *get_arch_dma_ops(void) { -#ifdef CONFIG_ALPHA_JENSEN - return NULL; -#else return &alpha_pci_ops; -#endif } #endif /* _ALPHA_DMA_MAPPING_H */ diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index 4f47a5003fe8..0c54ddb5b33e 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -209,8 +209,6 @@ static inline int generic_is_mmio(const volatile void __iomem *a) # include #elif defined(CONFIG_ALPHA_IRONGATE) # include -#elif defined(CONFIG_ALPHA_JENSEN) -# include #elif defined(CONFIG_ALPHA_LCA) # include #elif defined(CONFIG_ALPHA_MARVEL) @@ -631,23 +629,7 @@ extern void outsl (unsigned long port, const void *src, unsigned long count); #define outsw outsw #define outsl outsl -/* - * The Alpha Jensen hardware for some rather strange reason puts - * the RTC clock at 0x170 instead of 0x70. Probably due to some - * misguided idea about using 0x70 for NMI stuff. - * - * These defines will override the defaults when doing RTC queries - */ - -#ifdef CONFIG_ALPHA_GENERIC -# define RTC_PORT(x) ((x) + alpha_mv.rtc_port) -#else -# ifdef CONFIG_ALPHA_JENSEN -# define RTC_PORT(x) (0x170+(x)) -# else -# define RTC_PORT(x) (0x70 + (x)) -# endif -#endif +#define RTC_PORT(x) (0x70 + (x)) #define RTC_ALWAYS_BCD 0 /* diff --git a/arch/alpha/include/asm/jensen.h b/arch/alpha/include/asm/jensen.h deleted file mode 100644 index 66eb049eb421..000000000000 --- a/arch/alpha/include/asm/jensen.h +++ /dev/null @@ -1,363 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ALPHA_JENSEN_H -#define __ALPHA_JENSEN_H - -#include - -/* - * Defines for the AlphaPC EISA IO and memory address space. - */ - -/* - * NOTE! The memory operations do not set any memory barriers, as it's - * not needed for cases like a frame buffer that is essentially memory-like. - * You need to do them by hand if the operations depend on ordering. - * - * Similarly, the port IO operations do a "mb" only after a write operation: - * if an mb is needed before (as in the case of doing memory mapped IO - * first, and then a port IO operation to the same device), it needs to be - * done by hand. - * - * After the above has bitten me 100 times, I'll give up and just do the - * mb all the time, but right now I'm hoping this will work out. Avoiding - * mb's may potentially be a noticeable speed improvement, but I can't - * honestly say I've tested it. - * - * Handling interrupts that need to do mb's to synchronize to non-interrupts - * is another fun race area. Don't do it (because if you do, I'll have to - * do *everything* with interrupts disabled, ugh). - */ - -/* - * EISA Interrupt Acknowledge address - */ -#define EISA_INTA (IDENT_ADDR + 0x100000000UL) - -/* - * FEPROM addresses - */ -#define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL) -#define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL) - -/* - * VL82C106 base address - */ -#define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL) - -/* - * EISA "Host Address Extension" address (bits 25-31 of the EISA address) - */ -#define EISA_HAE (IDENT_ADDR + 0x1D0000000UL) - -/* - * "SYSCTL" register address - */ -#define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL) - -/* - * "spare" register address - */ -#define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL) - -/* - * EISA memory address offset - */ -#define EISA_MEM (IDENT_ADDR + 0x200000000UL) - -/* - * EISA IO address offset - */ -#define EISA_IO (IDENT_ADDR + 0x300000000UL) - - -#ifdef __KERNEL__ - -#ifndef __EXTERN_INLINE -#define __EXTERN_INLINE extern inline -#define __IO_EXTERN_INLINE -#endif - -/* - * Handle the "host address register". This needs to be set - * to the high 7 bits of the EISA address. This is also needed - * for EISA IO addresses, which are only 16 bits wide (the - * hae needs to be set to 0). - * - * HAE isn't needed for the local IO operations, though. - */ - -#define JENSEN_HAE_ADDRESS EISA_HAE -#define JENSEN_HAE_MASK 0x1ffffff - -__EXTERN_INLINE void jensen_set_hae(unsigned long addr) -{ - /* hae on the Jensen is bits 31:25 shifted right */ - addr >>= 25; - if (addr != alpha_mv.hae_cache) - set_hae(addr); -} - -#define vuip volatile unsigned int * -#define vulp volatile unsigned long * - -/* - * IO functions - * - * The "local" functions are those that don't go out to the EISA bus, - * but instead act on the VL82C106 chip directly.. This is mainly the - * keyboard, RTC, printer and first two serial lines.. - * - * The local stuff makes for some complications, but it seems to be - * gone in the PCI version. I hope I can get DEC suckered^H^H^H^H^H^H^H^H - * convinced that I need one of the newer machines. - */ - -__EXTERN_INLINE unsigned int jensen_local_inb(unsigned long addr) -{ - return 0xff & *(vuip)((addr << 9) + EISA_VL82C106); -} - -__EXTERN_INLINE void jensen_local_outb(u8 b, unsigned long addr) -{ - *(vuip)((addr << 9) + EISA_VL82C106) = b; - mb(); -} - -__EXTERN_INLINE unsigned int jensen_bus_inb(unsigned long addr) -{ - long result; - - jensen_set_hae(0); - result = *(volatile int *)((addr << 7) + EISA_IO + 0x00); - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE void jensen_bus_outb(u8 b, unsigned long addr) -{ - jensen_set_hae(0); - *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101; - mb(); -} - -/* - * It seems gcc is not very good at optimizing away logical - * operations that result in operations across inline functions. - * Which is why this is a macro. - */ - -#define jensen_is_local(addr) ( \ -/* keyboard */ (addr == 0x60 || addr == 0x64) || \ -/* RTC */ (addr == 0x170 || addr == 0x171) || \ -/* mb COM2 */ (addr >= 0x2f8 && addr <= 0x2ff) || \ -/* mb LPT1 */ (addr >= 0x3bc && addr <= 0x3be) || \ -/* mb COM2 */ (addr >= 0x3f8 && addr <= 0x3ff)) - -__EXTERN_INLINE u8 jensen_inb(unsigned long addr) -{ - if (jensen_is_local(addr)) - return jensen_local_inb(addr); - else - return jensen_bus_inb(addr); -} - -__EXTERN_INLINE void jensen_outb(u8 b, unsigned long addr) -{ - if (jensen_is_local(addr)) - jensen_local_outb(b, addr); - else - jensen_bus_outb(b, addr); -} - -__EXTERN_INLINE u16 jensen_inw(unsigned long addr) -{ - long result; - - jensen_set_hae(0); - result = *(volatile int *) ((addr << 7) + EISA_IO + 0x20); - result >>= (addr & 3) * 8; - return 0xffffUL & result; -} - -__EXTERN_INLINE u32 jensen_inl(unsigned long addr) -{ - jensen_set_hae(0); - return *(vuip) ((addr << 7) + EISA_IO + 0x60); -} - -__EXTERN_INLINE u64 jensen_inq(unsigned long addr) -{ - jensen_set_hae(0); - return *(vulp) ((addr << 7) + EISA_IO + 0x60); -} - -__EXTERN_INLINE void jensen_outw(u16 b, unsigned long addr) -{ - jensen_set_hae(0); - *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001; - mb(); -} - -__EXTERN_INLINE void jensen_outl(u32 b, unsigned long addr) -{ - jensen_set_hae(0); - *(vuip) ((addr << 7) + EISA_IO + 0x60) = b; - mb(); -} - -__EXTERN_INLINE void jensen_outq(u64 b, unsigned long addr) -{ - jensen_set_hae(0); - *(vulp) ((addr << 7) + EISA_IO + 0x60) = b; - mb(); -} - -/* - * Memory functions. - */ - -__EXTERN_INLINE u8 jensen_readb(const volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - long result; - - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - result = *(volatile int *) ((addr << 7) + EISA_MEM + 0x00); - result >>= (addr & 3) * 8; - return 0xffUL & result; -} - -__EXTERN_INLINE u16 jensen_readw(const volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - long result; - - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - result = *(volatile int *) ((addr << 7) + EISA_MEM + 0x20); - result >>= (addr & 3) * 8; - return 0xffffUL & result; -} - -__EXTERN_INLINE u32 jensen_readl(const volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - return *(vuip) ((addr << 7) + EISA_MEM + 0x60); -} - -__EXTERN_INLINE u64 jensen_readq(const volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long r0, r1; - - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - addr = (addr << 7) + EISA_MEM + 0x60; - r0 = *(vuip) (addr); - r1 = *(vuip) (addr + (4 << 7)); - return r1 << 32 | r0; -} - -__EXTERN_INLINE void jensen_writeb(u8 b, volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - *(vuip) ((addr << 7) + EISA_MEM + 0x00) = b * 0x01010101; -} - -__EXTERN_INLINE void jensen_writew(u16 b, volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - *(vuip) ((addr << 7) + EISA_MEM + 0x20) = b * 0x00010001; -} - -__EXTERN_INLINE void jensen_writel(u32 b, volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - *(vuip) ((addr << 7) + EISA_MEM + 0x60) = b; -} - -__EXTERN_INLINE void jensen_writeq(u64 b, volatile void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - jensen_set_hae(addr); - addr &= JENSEN_HAE_MASK; - addr = (addr << 7) + EISA_MEM + 0x60; - *(vuip) (addr) = b; - *(vuip) (addr + (4 << 7)) = b >> 32; -} - -__EXTERN_INLINE void __iomem *jensen_ioportmap(unsigned long addr) -{ - return (void __iomem *)addr; -} - -__EXTERN_INLINE void __iomem *jensen_ioremap(unsigned long addr, - unsigned long size) -{ - return (void __iomem *)(addr + 0x100000000ul); -} - -__EXTERN_INLINE int jensen_is_ioaddr(unsigned long addr) -{ - return (long)addr >= 0; -} - -__EXTERN_INLINE int jensen_is_mmio(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= 0x100000000ul; -} - -/* New-style ioread interface. All the routines are so ugly for Jensen - that it doesn't make sense to merge them. */ - -#define IOPORT(OS, NS) \ -__EXTERN_INLINE u##NS jensen_ioread##NS(const void __iomem *xaddr) \ -{ \ - if (jensen_is_mmio(xaddr)) \ - return jensen_read##OS(xaddr - 0x100000000ul); \ - else \ - return jensen_in##OS((unsigned long)xaddr); \ -} \ -__EXTERN_INLINE void jensen_iowrite##NS(u##NS b, void __iomem *xaddr) \ -{ \ - if (jensen_is_mmio(xaddr)) \ - jensen_write##OS(b, xaddr - 0x100000000ul); \ - else \ - jensen_out##OS(b, (unsigned long)xaddr); \ -} - -IOPORT(b, 8) -IOPORT(w, 16) -IOPORT(l, 32) -IOPORT(q, 64) - -#undef IOPORT - -#undef vuip -#undef vulp - -#undef __IO_PREFIX -#define __IO_PREFIX jensen -#define jensen_trivial_rw_bw 0 -#define jensen_trivial_rw_lq 0 -#define jensen_trivial_io_bw 0 -#define jensen_trivial_io_lq 0 -#define jensen_trivial_iounmap 1 -#include - -#ifdef __IO_EXTERN_INLINE -#undef __EXTERN_INLINE -#undef __IO_EXTERN_INLINE -#endif - -#endif /* __KERNEL__ */ - -#endif /* __ALPHA_JENSEN_H */ diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index fb4efec7cbc7..4b31060e1711 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -27,7 +27,7 @@ obj-y += core_apecs.o core_cia.o core_irongate.o core_lca.o \ core_tsunami.o obj-y += sys_alcor.o sys_cabriolet.o sys_dp264.o sys_eb64p.o sys_eiger.o \ - sys_jensen.o sys_miata.o sys_mikasa.o sys_nautilus.o \ + sys_miata.o sys_mikasa.o sys_nautilus.o \ sys_noritake.o sys_rawhide.o sys_ruffian.o sys_rx164.o \ sys_sable.o sys_sio.o sys_sx164.o sys_takara.o @@ -78,7 +78,6 @@ obj-$(CONFIG_ALPHA_TITAN) += sys_titan.o irq_i8259.o smc37c669.o obj-$(CONFIG_ALPHA_EB64P) += sys_eb64p.o irq_i8259.o obj-$(CONFIG_ALPHA_EB66) += sys_eb64p.o irq_i8259.o obj-$(CONFIG_ALPHA_EIGER) += sys_eiger.o irq_i8259.o -obj-$(CONFIG_ALPHA_JENSEN) += sys_jensen.o pci-noop.o irq_i8259.o obj-$(CONFIG_ALPHA_MARVEL) += sys_marvel.o obj-$(CONFIG_ALPHA_MIATA) += sys_miata.o irq_pyxis.o irq_i8259.o \ es1888.o smc37c669.o diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c deleted file mode 100644 index 32ca59a5a704..000000000000 --- a/arch/alpha/kernel/pci-noop.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/alpha/kernel/pci-noop.c - * - * Stub PCI interfaces for Jensen-specific kernels. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pci_impl.h" -#include "proto.h" - - -/* - * The PCI controller list. - */ - -struct pci_controller *hose_head, **hose_tail = &hose_head; -struct pci_controller *pci_isa_hose; - - -struct pci_controller * __init -alloc_pci_controller(void) -{ - struct pci_controller *hose; - - hose = memblock_alloc(sizeof(*hose), SMP_CACHE_BYTES); - if (!hose) - panic("%s: Failed to allocate %zu bytes\n", __func__, - sizeof(*hose)); - - *hose_tail = hose; - hose_tail = &hose->next; - - return hose; -} - -struct resource * __init -alloc_resource(void) -{ - void *ptr = memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES); - - if (!ptr) - panic("%s: Failed to allocate %zu bytes\n", __func__, - sizeof(struct resource)); - - return ptr; -} - -SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus, - unsigned long, dfn) -{ - struct pci_controller *hose; - - /* from hose or from bus.devfn */ - if (which & IOBASE_FROM_HOSE) { - for (hose = hose_head; hose; hose = hose->next) - if (hose->index == bus) - break; - if (!hose) - return -ENODEV; - } else { - /* Special hook for ISA access. */ - if (bus == 0 && dfn == 0) - hose = pci_isa_hose; - else - return -ENODEV; - } - - switch (which & ~IOBASE_FROM_HOSE) { - case IOBASE_HOSE: - return hose->index; - case IOBASE_SPARSE_MEM: - return hose->sparse_mem_base; - case IOBASE_DENSE_MEM: - return hose->dense_mem_base; - case IOBASE_SPARSE_IO: - return hose->sparse_io_base; - case IOBASE_DENSE_IO: - return hose->dense_io_base; - case IOBASE_ROOT_BUS: - return hose->bus->number; - } - - return -EOPNOTSUPP; -} - -SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn, - unsigned long, off, unsigned long, len, void __user *, buf) -{ - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - else - return -ENODEV; -} - -SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn, - unsigned long, off, unsigned long, len, void __user *, buf) -{ - if (!capable(CAP_SYS_ADMIN)) - return -EPERM; - else - return -ENODEV; -} diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 0738f9396f95..6e6c842ef07c 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -181,7 +181,6 @@ WEAK(eb64p_mv); WEAK(eb66_mv); WEAK(eb66p_mv); WEAK(eiger_mv); -WEAK(jensen_mv); WEAK(lx164_mv); WEAK(lynx_mv); WEAK(marvel_ev7_mv); @@ -224,7 +223,7 @@ static void __init reserve_std_resources(void) { static struct resource standard_io_resources[] = { - { .name = "rtc", .start = -1, .end = -1 }, + { .name = "rtc", .start = 0x70, .end = 0x7f}, { .name = "dma1", .start = 0x00, .end = 0x1f }, { .name = "pic1", .start = 0x20, .end = 0x3f }, { .name = "timer", .start = 0x40, .end = 0x5f }, @@ -246,10 +245,6 @@ reserve_std_resources(void) } } - /* Fix up for the Jensen's queer RTC placement. */ - standard_io_resources[0].start = RTC_PORT(0); - standard_io_resources[0].end = RTC_PORT(0) + 0x0f; - for (i = 0; i < ARRAY_SIZE(standard_io_resources); ++i) request_resource(io, standard_io_resources+i); } @@ -486,14 +481,7 @@ setup_arch(char **cmdline_p) /* * Locate the command line. */ - /* Hack for Jensen... since we're restricted to 8 or 16 chars for - boot flags depending on the boot mode, we need some shorthand. - This should do for installation. */ - if (strcmp(COMMAND_LINE, "INSTALL") == 0) { - strscpy(command_line, "root=/dev/fd0 load_ramdisk=1", sizeof(command_line)); - } else { - strscpy(command_line, COMMAND_LINE, sizeof(command_line)); - } + strscpy(command_line, COMMAND_LINE, sizeof(command_line)); strcpy(boot_command_line, command_line); *cmdline_p = command_line; @@ -745,7 +733,7 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) NULL, /* Ruby */ NULL, /* Flamingo */ NULL, /* Mannequin */ - &jensen_mv, + NULL, /* Jensens */ NULL, /* Pelican */ NULL, /* Morgan */ NULL, /* Sable -- see below. */ @@ -943,7 +931,6 @@ get_sysvec_byname(const char *name) &eb66_mv, &eb66p_mv, &eiger_mv, - &jensen_mv, &lx164_mv, &lynx_mv, &miata_mv, diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c deleted file mode 100644 index a1bb1c4a7e93..000000000000 --- a/arch/alpha/kernel/sys_jensen.c +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/alpha/kernel/sys_jensen.c - * - * Copyright (C) 1995 Linus Torvalds - * Copyright (C) 1998, 1999 Richard Henderson - * - * Code supporting the Jensen. - */ -#define __EXTERN_INLINE inline -#include -#include -#undef __EXTERN_INLINE - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include "proto.h" -#include "irq_impl.h" -#include "pci_impl.h" -#include "machvec_impl.h" - - -/* - * Jensen is special: the vector is 0x8X0 for EISA interrupt X, and - * 0x9X0 for the local motherboard interrupts. - * - * Note especially that those local interrupts CANNOT be masked, - * which causes much of the pain below... - * - * 0x660 - NMI - * - * 0x800 - IRQ0 interval timer (not used, as we use the RTC timer) - * 0x810 - IRQ1 line printer (duh..) - * 0x860 - IRQ6 floppy disk - * - * 0x900 - COM1 - * 0x920 - COM2 - * 0x980 - keyboard - * 0x990 - mouse - * - * PCI-based systems are more sane: they don't have the local - * interrupts at all, and have only normal PCI interrupts from - * devices. Happily it's easy enough to do a sane mapping from the - * Jensen. - * - * Note that this means that we may have to do a hardware - * "local_op" to a different interrupt than we report to the rest of the - * world. - */ - -static void -jensen_local_enable(struct irq_data *d) -{ - /* the parport is really hw IRQ 1, silly Jensen. */ - if (d->irq == 7) - i8259a_enable_irq(d); -} - -static void -jensen_local_disable(struct irq_data *d) -{ - /* the parport is really hw IRQ 1, silly Jensen. */ - if (d->irq == 7) - i8259a_disable_irq(d); -} - -static void -jensen_local_mask_ack(struct irq_data *d) -{ - /* the parport is really hw IRQ 1, silly Jensen. */ - if (d->irq == 7) - i8259a_mask_and_ack_irq(d); -} - -static struct irq_chip jensen_local_irq_type = { - .name = "LOCAL", - .irq_unmask = jensen_local_enable, - .irq_mask = jensen_local_disable, - .irq_mask_ack = jensen_local_mask_ack, -}; - -static void -jensen_device_interrupt(unsigned long vector) -{ - int irq; - - switch (vector) { - case 0x660: - printk("Whee.. NMI received. Probable hardware error\n"); - printk("61=%02x, 461=%02x\n", inb(0x61), inb(0x461)); - return; - - /* local device interrupts: */ - case 0x900: irq = 4; break; /* com1 -> irq 4 */ - case 0x920: irq = 3; break; /* com2 -> irq 3 */ - case 0x980: irq = 1; break; /* kbd -> irq 1 */ - case 0x990: irq = 9; break; /* mouse -> irq 9 */ - - default: - if (vector > 0x900) { - printk("Unknown local interrupt %lx\n", vector); - return; - } - - irq = (vector - 0x800) >> 4; - if (irq == 1) - irq = 7; - break; - } - - /* If there is no handler yet... */ - if (!irq_has_action(irq)) { - /* If it is a local interrupt that cannot be masked... */ - if (vector >= 0x900) - { - /* Clear keyboard/mouse state */ - inb(0x64); - inb(0x60); - /* Reset serial ports */ - inb(0x3fa); - inb(0x2fa); - outb(0x0c, 0x3fc); - outb(0x0c, 0x2fc); - /* Clear NMI */ - outb(0,0x61); - outb(0,0x461); - } - } - -#if 0 - /* A useful bit of code to find out if an interrupt is going wild. */ - { - static unsigned int last_msg = 0, last_cc = 0; - static int last_irq = -1, count = 0; - unsigned int cc; - - __asm __volatile("rpcc %0" : "=r"(cc)); - ++count; -#define JENSEN_CYCLES_PER_SEC (150000000) - if (cc - last_msg > ((JENSEN_CYCLES_PER_SEC) * 3) || - irq != last_irq) { - printk(KERN_CRIT " irq %d count %d cc %u @ %lx\n", - irq, count, cc-last_cc, get_irq_regs()->pc); - count = 0; - last_msg = cc; - last_irq = irq; - } - last_cc = cc; - } -#endif - - handle_irq(irq); -} - -static void __init -jensen_init_irq(void) -{ - init_i8259a_irqs(); - - irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); - irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); - irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); - irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); - irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); - - common_init_isa_dma(); -} - -static void __init -jensen_init_arch(void) -{ - struct pci_controller *hose; -#ifdef CONFIG_PCI - static struct pci_dev fake_isa_bridge = { .dma_mask = 0xffffffffUL, }; - - isa_bridge = &fake_isa_bridge; -#endif - - /* Create a hose so that we can report i/o base addresses to - userland. */ - - pci_isa_hose = hose = alloc_pci_controller(); - hose->io_space = &ioport_resource; - hose->mem_space = &iomem_resource; - hose->index = 0; - - hose->sparse_mem_base = EISA_MEM - IDENT_ADDR; - hose->dense_mem_base = 0; - hose->sparse_io_base = EISA_IO - IDENT_ADDR; - hose->dense_io_base = 0; - - hose->sg_isa = hose->sg_pci = NULL; - __direct_map_base = 0; - __direct_map_size = 0xffffffff; -} - -static void -jensen_machine_check(unsigned long vector, unsigned long la) -{ - printk(KERN_CRIT "Machine check\n"); -} - -/* - * The System Vector - */ - -struct alpha_machine_vector jensen_mv __initmv = { - .vector_name = "Jensen", - DO_EV4_MMU, - IO_LITE(JENSEN,jensen), - .machine_check = jensen_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .rtc_port = 0x170, - - .nr_irqs = 16, - .device_interrupt = jensen_device_interrupt, - - .init_arch = jensen_init_arch, - .init_irq = jensen_init_irq, - .init_rtc = common_init_rtc, - .init_pci = NULL, - .kill_arch = NULL, -}; -ALIAS_MV(jensen) diff --git a/drivers/eisa/Kconfig b/drivers/eisa/Kconfig index c8bbf90209f5..a66b3be502a9 100644 --- a/drivers/eisa/Kconfig +++ b/drivers/eisa/Kconfig @@ -44,17 +44,16 @@ config EISA_PCI_EISA When in doubt, say Y. -# Using EISA_VIRTUAL_ROOT on something other than an Alpha or -# an X86 may lead to crashes... +# Using EISA_VIRTUAL_ROOT on something other than an X86 may lead +# to crashes... config EISA_VIRTUAL_ROOT bool "EISA virtual root device" - depends on EISA && (ALPHA || X86) + depends on EISA && X86 default y help Activate this option if your system only have EISA bus - (no PCI slots). The Alpha Jensen is an example of such - a system. + (no PCI slots). When in doubt, say Y. diff --git a/drivers/eisa/virtual_root.c b/drivers/eisa/virtual_root.c index 37e6dd219c37..cd9515d9d8f0 100644 --- a/drivers/eisa/virtual_root.c +++ b/drivers/eisa/virtual_root.c @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_ALPHA_JENSEN) || defined(CONFIG_EISA_VLB_PRIMING) +#if defined(CONFIG_EISA_VLB_PRIMING) #define EISA_FORCE_PROBE_DEFAULT 1 #else #define EISA_FORCE_PROBE_DEFAULT 0 diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h index 64590b86eb37..a8f4b2d70e59 100644 --- a/drivers/input/serio/i8042-io.h +++ b/drivers/input/serio/i8042-io.h @@ -15,10 +15,7 @@ * IRQs. */ -#ifdef __alpha__ -# define I8042_KBD_IRQ 1 -# define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special */ -#elif defined(__arm__) +#if defined(__arm__) /* defined in include/asm-arm/arch-xxx/irqs.h */ #include #elif defined(CONFIG_PPC) diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index 1aa3e55c8b47..6a7b286f6f5a 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -293,9 +293,6 @@ static inline int serial8250_in_MCR(struct uart_8250_port *up) return mctrl; } -bool alpha_jensen(void); -void alpha_jensen_set_mctrl(struct uart_port *port, unsigned int mctrl); - #ifdef CONFIG_SERIAL_8250_PNP int serial8250_pnp_init(void); void serial8250_pnp_exit(void); diff --git a/drivers/tty/serial/8250/8250_alpha.c b/drivers/tty/serial/8250/8250_alpha.c deleted file mode 100644 index 58e70328aa4d..000000000000 --- a/drivers/tty/serial/8250/8250_alpha.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include -#include "8250.h" - -bool alpha_jensen(void) -{ - return !strcmp(alpha_mv.vector_name, "Jensen"); -} - -void alpha_jensen_set_mctrl(struct uart_port *port, unsigned int mctrl) -{ - /* - * Digital did something really horribly wrong with the OUT1 and OUT2 - * lines on Alpha Jensen. The failure mode is that if either is - * cleared, the machine locks up with endless interrupts. - */ - mctrl |= TIOCM_OUT1 | TIOCM_OUT2; - - serial8250_do_set_mctrl(port, mctrl); -} diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index b62ad9006780..2504e0455875 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c @@ -508,10 +508,6 @@ static struct uart_8250_port *serial8250_setup_port(int index) up->ops = &univ8250_driver_ops; - if (IS_ENABLED(CONFIG_ALPHA_JENSEN) || - (IS_ENABLED(CONFIG_ALPHA_GENERIC) && alpha_jensen())) - up->port.set_mctrl = alpha_jensen_set_mctrl; - serial8250_set_defaults(up); return up; diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index ea2e81f58eac..69ac00270547 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -5,8 +5,6 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250-y := 8250_core.o -8250-$(CONFIG_ALPHA_GENERIC) += 8250_alpha.o -8250-$(CONFIG_ALPHA_JENSEN) += 8250_alpha.o 8250-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o 8250_base-y := 8250_port.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o From d2b1e353dacc1bd0e28be9ec9687e3b408e733c6 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 13 Dec 2023 17:53:59 +0100 Subject: [PATCH 908/969] alpha: sable: remove early machine support The sable family (Alphaserver 2000 and 2100) comes in variants for EV4, EV45, EV5 and EV56. Drop support for the earlier ones that lack support for the BWX extension but keep the later 'gamma' variant around since that works with EV56 CPUs. Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/Kconfig | 29 +-- arch/alpha/include/asm/core_t2.h | 8 - arch/alpha/include/asm/irq.h | 1 - arch/alpha/kernel/Makefile | 1 - arch/alpha/kernel/setup.c | 11 +- arch/alpha/kernel/sys_sable.c | 294 +------------------------------ 6 files changed, 11 insertions(+), 333 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 9b8d3ce40c28..951a9c712361 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -100,7 +100,6 @@ choice EB66 EB66 21066 evaluation board EB66+ EB66+ 21066 evaluation board LX164 AlphaPC164-LX - Lynx AS 2100A Miata Personal Workstation 433/500/600 a/au Marvel AlphaServer ES47 / ES80 / GS1280 Mikasa AS 1000 @@ -203,12 +202,6 @@ config ALPHA_LX164 A technical overview of this board is available at . -config ALPHA_LYNX - bool "Lynx" - select HAVE_EISA - help - AlphaServer 2100A-based systems. - config ALPHA_MARVEL bool "Marvel" help @@ -325,9 +318,8 @@ config ALPHA_NONAME config ALPHA_EV4 bool - depends on (ALPHA_SABLE && !ALPHA_GAMMA) || ALPHA_LYNX || ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K - default y if !ALPHA_LYNX - default y if !ALPHA_EV5 + depends on ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K + default y config ALPHA_LCA bool @@ -352,8 +344,8 @@ config ALPHA_EB64P Runs from standard PC power supply. config ALPHA_EV5 - bool "EV5 CPU(s) (model 5/xxx)?" if ALPHA_LYNX - default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE && ALPHA_GAMMA || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR + bool + default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR config ALPHA_CIA bool @@ -378,16 +370,9 @@ config ALPHA_PRIMO help Say Y if you have an AS 1000 5/xxx or an AS 1000A 5/xxx. -config ALPHA_GAMMA - bool "EV5 CPU(s) (model 5/xxx)?" if ALPHA_SABLE - depends on ALPHA_SABLE || ALPHA_LYNX - default ALPHA_LYNX - help - Say Y if you have an AS 2000 5/xxx or an AS 2100 5/xxx. - config ALPHA_T2 bool - depends on ALPHA_SABLE || ALPHA_LYNX + depends on ALPHA_SABLE default y config ALPHA_PYXIS @@ -471,7 +456,7 @@ config ALPHA_QEMU config ALPHA_SRM bool "Use SRM as bootloader" if ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS || ALPHA_NONAME depends on TTY - default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL + default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL help There are two different types of booting firmware on Alphas: SRM, which is command line driven, and ARC, which uses menus and arrow @@ -497,7 +482,7 @@ config ARCH_MAY_HAVE_PC_FDC config SMP bool "Symmetric multi-processing support" - depends on ALPHA_SABLE || ALPHA_LYNX || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL + depends on ALPHA_SABLE || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL help This enables support for systems with more than one CPU. If you have a system with only one CPU, say N. If you have a system with more diff --git a/arch/alpha/include/asm/core_t2.h b/arch/alpha/include/asm/core_t2.h index ab956b1625b5..ca9b091d9c5f 100644 --- a/arch/alpha/include/asm/core_t2.h +++ b/arch/alpha/include/asm/core_t2.h @@ -25,16 +25,8 @@ #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */ /* GAMMA-SABLE is a SABLE with EV5-based CPUs */ -/* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ #define _GAMMA_BIAS 0x8000000000UL - -#if defined(CONFIG_ALPHA_GENERIC) -#define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias -#elif defined(CONFIG_ALPHA_GAMMA) #define GAMMA_BIAS _GAMMA_BIAS -#else -#define GAMMA_BIAS 0 -#endif /* * Memory spaces: diff --git a/arch/alpha/include/asm/irq.h b/arch/alpha/include/asm/irq.h index 432402c8e47f..442097c56934 100644 --- a/arch/alpha/include/asm/irq.h +++ b/arch/alpha/include/asm/irq.h @@ -55,7 +55,6 @@ # define NR_IRQS 40 #elif defined(CONFIG_ALPHA_DP264) || \ - defined(CONFIG_ALPHA_LYNX) || \ defined(CONFIG_ALPHA_SHARK) # define NR_IRQS 64 diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index 4b31060e1711..706ce8625e35 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -88,7 +88,6 @@ obj-$(CONFIG_ALPHA_RAWHIDE) += sys_rawhide.o irq_i8259.o obj-$(CONFIG_ALPHA_RUFFIAN) += sys_ruffian.o irq_pyxis.o irq_i8259.o obj-$(CONFIG_ALPHA_RX164) += sys_rx164.o irq_i8259.o obj-$(CONFIG_ALPHA_SABLE) += sys_sable.o -obj-$(CONFIG_ALPHA_LYNX) += sys_sable.o obj-$(CONFIG_ALPHA_BOOK1) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o obj-$(CONFIG_ALPHA_AVANTI) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o obj-$(CONFIG_ALPHA_NONAME) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 6e6c842ef07c..3b833bd97817 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -182,7 +182,6 @@ WEAK(eb66_mv); WEAK(eb66p_mv); WEAK(eiger_mv); WEAK(lx164_mv); -WEAK(lynx_mv); WEAK(marvel_ev7_mv); WEAK(miata_mv); WEAK(mikasa_mv); @@ -198,7 +197,6 @@ WEAK(privateer_mv); WEAK(rawhide_mv); WEAK(ruffian_mv); WEAK(rx164_mv); -WEAK(sable_mv); WEAK(sable_gamma_mv); WEAK(shark_mv); WEAK(sx164_mv); @@ -751,7 +749,7 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) &alphabook1_mv, &rawhide_mv, NULL, /* K2 */ - &lynx_mv, /* Lynx */ + NULL, /* Lynx */ &xl_mv, NULL, /* EB164 -- see variation. */ NULL, /* Noritake -- see below. */ @@ -905,10 +903,7 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) vec = &noritake_mv; break; case ST_DEC_2100_A500: - if (cpu == EV5_CPU || cpu == EV56_CPU) - vec = &sable_gamma_mv; - else - vec = &sable_mv; + vec = &sable_gamma_mv; break; } } @@ -932,7 +927,6 @@ get_sysvec_byname(const char *name) &eb66p_mv, &eiger_mv, &lx164_mv, - &lynx_mv, &miata_mv, &mikasa_mv, &mikasa_primo_mv, @@ -947,7 +941,6 @@ get_sysvec_byname(const char *name) &rawhide_mv, &ruffian_mv, &rx164_mv, - &sable_mv, &sable_gamma_mv, &shark_mv, &sx164_mv, diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c index 930005b2f630..49f5c75134ec 100644 --- a/arch/alpha/kernel/sys_sable.c +++ b/arch/alpha/kernel/sys_sable.c @@ -212,232 +212,6 @@ sable_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */ -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) - -/***********************************************************************/ -/* LYNX hardware specifics - */ -/* - * For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC. - * - * Bit Meaning Kernel IRQ - *------------------------------------------ - * 0 - * 1 - * 2 - * 3 mouse 12 - * 4 - * 5 - * 6 keyboard 1 - * 7 floppy 6 - * 8 COM2 3 - * 9 parallel port 7 - *10 EISA irq 3 - - *11 EISA irq 4 - - *12 EISA irq 5 5 - *13 EISA irq 6 - - *14 EISA irq 7 - - *15 COM1 4 - *16 EISA irq 9 9 - *17 EISA irq 10 10 - *18 EISA irq 11 11 - *19 EISA irq 12 - - *20 - *21 EISA irq 14 14 - *22 EISA irq 15 15 - *23 IIC - - *24 VGA (builtin) - - *25 - *26 - *27 - *28 NCR810 (builtin) 28 - *29 - *30 - *31 - *32 PCI 0 slot 4 A primary bus 32 - *33 PCI 0 slot 4 B primary bus 33 - *34 PCI 0 slot 4 C primary bus 34 - *35 PCI 0 slot 4 D primary bus - *36 PCI 0 slot 5 A primary bus - *37 PCI 0 slot 5 B primary bus - *38 PCI 0 slot 5 C primary bus - *39 PCI 0 slot 5 D primary bus - *40 PCI 0 slot 6 A primary bus - *41 PCI 0 slot 6 B primary bus - *42 PCI 0 slot 6 C primary bus - *43 PCI 0 slot 6 D primary bus - *44 PCI 0 slot 7 A primary bus - *45 PCI 0 slot 7 B primary bus - *46 PCI 0 slot 7 C primary bus - *47 PCI 0 slot 7 D primary bus - *48 PCI 0 slot 0 A secondary bus - *49 PCI 0 slot 0 B secondary bus - *50 PCI 0 slot 0 C secondary bus - *51 PCI 0 slot 0 D secondary bus - *52 PCI 0 slot 1 A secondary bus - *53 PCI 0 slot 1 B secondary bus - *54 PCI 0 slot 1 C secondary bus - *55 PCI 0 slot 1 D secondary bus - *56 PCI 0 slot 2 A secondary bus - *57 PCI 0 slot 2 B secondary bus - *58 PCI 0 slot 2 C secondary bus - *59 PCI 0 slot 2 D secondary bus - *60 PCI 0 slot 3 A secondary bus - *61 PCI 0 slot 3 B secondary bus - *62 PCI 0 slot 3 C secondary bus - *63 PCI 0 slot 3 D secondary bus - */ - -static void -lynx_update_irq_hw(unsigned long bit, unsigned long mask) -{ - /* - * Write the AIR register on the T3/T4 with the - * address of the IC mask register (offset 0x40) - */ - *(vulp)T2_AIR = 0x40; - mb(); - *(vulp)T2_AIR; /* re-read to force write */ - mb(); - *(vulp)T2_DIR = mask; - mb(); - mb(); -} - -static void -lynx_ack_irq_hw(unsigned long bit) -{ - *(vulp)T2_VAR = (u_long) bit; - mb(); - mb(); -} - -static irq_swizzle_t lynx_irq_swizzle = { - { /* irq_to_mask */ - -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */ - -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */ - -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo */ - -1, -1, -1, -1, 28, -1, -1, -1, /* pseudo */ - 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */ - 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */ - 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */ - 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */ - }, - { /* mask_to_irq */ - -1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */ - 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */ - 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */ - -1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */ - 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */ - 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */ - 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */ - 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */ - }, - -1, - lynx_update_irq_hw, - lynx_ack_irq_hw -}; - -static void __init -lynx_init_irq(void) -{ - sable_lynx_irq_swizzle = &lynx_irq_swizzle; - sable_lynx_init_irq(64); -} - -/* - * PCI Fixup configuration for ALPHA LYNX (2100A) - * - * The device to slot mapping looks like: - * - * Slot Device - * 0 none - * 1 none - * 2 PCI-EISA bridge - * 3 PCI-PCI bridge - * 4 NCR 810 (Demi-Lynx only) - * 5 none - * 6 PCI on board slot 4 - * 7 PCI on board slot 5 - * 8 PCI on board slot 6 - * 9 PCI on board slot 7 - * - * And behind the PPB we have: - * - * 11 PCI on board slot 0 - * 12 PCI on board slot 1 - * 13 PCI on board slot 2 - * 14 PCI on board slot 3 - */ -/* - * NOTE: the IRQ assignments below are arbitrary, but need to be consistent - * with the values in the irq swizzling tables above. - */ - -static int -lynx_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static char irq_tab[19][5] = { - /*INT INTA INTB INTC INTD */ - { -1, -1, -1, -1, -1}, /* IdSel 13, PCEB */ - { -1, -1, -1, -1, -1}, /* IdSel 14, PPB */ - { 28, 28, 28, 28, 28}, /* IdSel 15, NCR demi */ - { -1, -1, -1, -1, -1}, /* IdSel 16, none */ - { 32, 32, 33, 34, 35}, /* IdSel 17, slot 4 */ - { 36, 36, 37, 38, 39}, /* IdSel 18, slot 5 */ - { 40, 40, 41, 42, 43}, /* IdSel 19, slot 6 */ - { 44, 44, 45, 46, 47}, /* IdSel 20, slot 7 */ - { -1, -1, -1, -1, -1}, /* IdSel 22, none */ - /* The following are actually behind the PPB. */ - { -1, -1, -1, -1, -1}, /* IdSel 16 none */ - { 28, 28, 28, 28, 28}, /* IdSel 17 NCR lynx */ - { -1, -1, -1, -1, -1}, /* IdSel 18 none */ - { -1, -1, -1, -1, -1}, /* IdSel 19 none */ - { -1, -1, -1, -1, -1}, /* IdSel 20 none */ - { -1, -1, -1, -1, -1}, /* IdSel 21 none */ - { 48, 48, 49, 50, 51}, /* IdSel 22 slot 0 */ - { 52, 52, 53, 54, 55}, /* IdSel 23 slot 1 */ - { 56, 56, 57, 58, 59}, /* IdSel 24 slot 2 */ - { 60, 60, 61, 62, 63} /* IdSel 25 slot 3 */ - }; - const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5; - return COMMON_TABLE_LOOKUP; -} - -static u8 -lynx_swizzle(struct pci_dev *dev, u8 *pinp) -{ - int slot, pin = *pinp; - - if (dev->bus->number == 0) { - slot = PCI_SLOT(dev->devfn); - } - /* Check for the built-in bridge */ - else if (PCI_SLOT(dev->bus->self->devfn) == 3) { - slot = PCI_SLOT(dev->devfn) + 11; - } - else - { - /* Must be a card-based bridge. */ - do { - if (PCI_SLOT(dev->bus->self->devfn) == 3) { - slot = PCI_SLOT(dev->devfn) + 11; - break; - } - pin = pci_swizzle_interrupt_pin(dev, pin); - - /* Move up the chain of bridges. */ - dev = dev->bus->self; - /* Slot of the next bridge. */ - slot = PCI_SLOT(dev->devfn); - } while (dev->bus->self); - } - *pinp = pin; - return slot; -} - -#endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */ - /***********************************************************************/ /* GENERIC irq routines */ @@ -539,40 +313,7 @@ sable_lynx_init_pci(void) * these games with GAMMA_BIAS. */ -#if defined(CONFIG_ALPHA_GENERIC) || \ - (defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA)) -#undef GAMMA_BIAS -#define GAMMA_BIAS 0 -struct alpha_machine_vector sable_mv __initmv = { - .vector_name = "Sable", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_T2_IO, - .machine_check = t2_machine_check, - .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS, - .min_io_address = EISA_DEFAULT_IO_BASE, - .min_mem_address = T2_DEFAULT_MEM_BASE, - - .nr_irqs = 40, - .device_interrupt = sable_lynx_srm_device_interrupt, - - .init_arch = t2_init_arch, - .init_irq = sable_init_irq, - .init_rtc = common_init_rtc, - .init_pci = sable_lynx_init_pci, - .kill_arch = t2_kill_arch, - .pci_map_irq = sable_map_irq, - .pci_swizzle = common_swizzle, - - .sys = { .t2 = { - .gamma_bias = 0 - } } -}; -ALIAS_MV(sable) -#endif /* GENERIC || (SABLE && !GAMMA) */ - -#if defined(CONFIG_ALPHA_GENERIC) || \ - (defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA)) +#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) #undef GAMMA_BIAS #define GAMMA_BIAS _GAMMA_BIAS struct alpha_machine_vector sable_gamma_mv __initmv = { @@ -601,35 +342,4 @@ struct alpha_machine_vector sable_gamma_mv __initmv = { } } }; ALIAS_MV(sable_gamma) -#endif /* GENERIC || (SABLE && GAMMA) */ - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) -#undef GAMMA_BIAS -#define GAMMA_BIAS _GAMMA_BIAS -struct alpha_machine_vector lynx_mv __initmv = { - .vector_name = "Lynx", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_T2_IO, - .machine_check = t2_machine_check, - .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS, - .min_io_address = EISA_DEFAULT_IO_BASE, - .min_mem_address = T2_DEFAULT_MEM_BASE, - - .nr_irqs = 64, - .device_interrupt = sable_lynx_srm_device_interrupt, - - .init_arch = t2_init_arch, - .init_irq = lynx_init_irq, - .init_rtc = common_init_rtc, - .init_pci = sable_lynx_init_pci, - .kill_arch = t2_kill_arch, - .pci_map_irq = lynx_map_irq, - .pci_swizzle = lynx_swizzle, - - .sys = { .t2 = { - .gamma_bias = _GAMMA_BIAS - } } -}; -ALIAS_MV(lynx) -#endif /* GENERIC || LYNX */ +#endif /* GENERIC || SABLE */ From 430ad3f0ddd7bb0f6ed8c4c45bbce67e2c7ed396 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 13 Dec 2023 18:08:20 +0100 Subject: [PATCH 909/969] alpha: remove LCA and APECS based machines APECS is the DECchip 21071x chipset for the EV4 and EV45 generation, while LCA is the integrated I/O support on the corresponding low-cost alpha machines of that generation. All of these CPUs lack the BWX extension for byte and word access, so drop the chipset support and all associated machines. Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/Kconfig | 114 +----- arch/alpha/include/asm/core_apecs.h | 534 ---------------------------- arch/alpha/include/asm/core_lca.h | 378 -------------------- arch/alpha/include/asm/dma.h | 9 +- arch/alpha/include/asm/io.h | 6 +- arch/alpha/include/asm/irq.h | 8 +- arch/alpha/kernel/Makefile | 19 +- arch/alpha/kernel/core_apecs.c | 420 ---------------------- arch/alpha/kernel/core_lca.c | 473 ------------------------ arch/alpha/kernel/irq_i8259.c | 4 - arch/alpha/kernel/pci_impl.h | 4 +- arch/alpha/kernel/proto.h | 13 - arch/alpha/kernel/setup.c | 79 +--- arch/alpha/kernel/sys_cabriolet.c | 59 --- arch/alpha/kernel/sys_eb64p.c | 238 ------------- arch/alpha/kernel/sys_mikasa.c | 57 --- arch/alpha/kernel/sys_noritake.c | 60 ---- arch/alpha/kernel/sys_sio.c | 486 ------------------------- 18 files changed, 21 insertions(+), 2940 deletions(-) delete mode 100644 arch/alpha/include/asm/core_apecs.h delete mode 100644 arch/alpha/include/asm/core_lca.h delete mode 100644 arch/alpha/kernel/core_apecs.c delete mode 100644 arch/alpha/kernel/core_lca.c delete mode 100644 arch/alpha/kernel/sys_eb64p.c delete mode 100644 arch/alpha/kernel/sys_sio.c diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 951a9c712361..ee209e895505 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -90,20 +90,12 @@ choice . In summary: Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366 - Alpha-XL XL-233, XL-266 - AlphaBook1 Alpha laptop - Avanti AS 200, AS 205, AS 250, AS 255, AS 300, AS 400 - Cabriolet AlphaPC64, AlphaPCI64 DP264 DP264 / DS20 / ES40 / DS10 / DS10L EB164 EB164 21164 evaluation board - EB64+ EB64+ 21064 evaluation board - EB66 EB66 21066 evaluation board - EB66+ EB66+ 21066 evaluation board LX164 AlphaPC164-LX Miata Personal Workstation 433/500/600 a/au Marvel AlphaServer ES47 / ES80 / GS1280 Mikasa AS 1000 - Noname AXPpci33, UDB (Multia) Noritake AS 1000A, AS 600A, AS 800 PC164 AlphaPC164 Rawhide AS 1200, AS 4000, AS 4100 @@ -135,27 +127,6 @@ config ALPHA_ALCOR all the work required to support an external Bcache and to maintain memory coherence when a PCI device DMAs into (or out of) memory. -config ALPHA_XL - bool "Alpha-XL" - help - XL-233 and XL-266-based Alpha systems. - -config ALPHA_BOOK1 - bool "AlphaBook1" - help - Dec AlphaBook1/Burns Alpha-based laptops. - -config ALPHA_AVANTI_CH - bool "Avanti" - -config ALPHA_CABRIOLET - bool "Cabriolet" - help - Cabriolet AlphaPC64, AlphaPCI64 systems. Derived from EB64+ but now - baby-AT with Flash boot ROM, no on-board SCSI or Ethernet. 3 ISA - slots, 4 PCI slots (one pair are on a shared slot), uses plug-in - Bcache SIMMs. Requires power supply with 3.3V output. - config ALPHA_DP264 bool "DP264" help @@ -173,23 +144,6 @@ config ALPHA_EB164 MOUSE (PS2 style), RTC/NVRAM. Boot ROM is Flash. PC-AT-sized motherboard. Requires power supply with 3.3V output. -config ALPHA_EB64P_CH - bool "EB64+" - -config ALPHA_EB66 - bool "EB66" - help - A Digital DS group board. Uses 21066 or 21066A. I/O sub-system is - identical to EB64+. Baby PC-AT size. Runs from standard PC power - supply. The EB66 schematic was published as a marketing poster - advertising the 21066 as "the first microprocessor in the world with - embedded PCI". - -config ALPHA_EB66P - bool "EB66+" - help - Later variant of the EB66 board. - config ALPHA_EIGER bool "Eiger" help @@ -224,9 +178,6 @@ config ALPHA_NAUTILUS help Alpha systems based on the AMD 751 & ALI 1543C chipsets. -config ALPHA_NONAME_CH - bool "Noname" - config ALPHA_NORITAKE bool "Noritake" select HAVE_EISA @@ -237,9 +188,6 @@ config ALPHA_NORITAKE config ALPHA_PC164 bool "PC164" -config ALPHA_P2K - bool "Platform2000" - config ALPHA_RAWHIDE bool "Rawhide" select HAVE_EISA @@ -303,53 +251,16 @@ config ISA_DMA_API bool default y -config ALPHA_NONAME - bool - depends on ALPHA_BOOK1 || ALPHA_NONAME_CH - default y - help - The AXPpci33 (aka NoName), is based on the EB66 (includes the Multia - UDB). This design was produced by Digital's Technical OEM (TOEM) - group. It uses the 21066 processor running at 166MHz or 233MHz. It - is a baby-AT size, and runs from a standard PC power supply. It has - 5 ISA slots and 3 PCI slots (one pair are a shared slot). There are - 2 versions, with either PS/2 or large DIN connectors for the - keyboard. - config ALPHA_EV4 bool - depends on ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K - default y - -config ALPHA_LCA - bool - depends on ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K - default y - -config ALPHA_APECS - bool - depends on !ALPHA_PRIMO && (ALPHA_NORITAKE || ALPHA_MIKASA) || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL - default y - -config ALPHA_EB64P - bool - depends on ALPHA_CABRIOLET || ALPHA_EB64P_CH - default y - help - Uses 21064 or 21064A and APECs. Has ISA and PCI expansion (3 ISA, - 2 PCI, one pair are on a shared slot). Supports 36-bit DRAM SIMs. - ISA bus generated by Intel SaturnI/O PCI-ISA bridge. On-board SCSI - (NCR 810 on PCI) Ethernet (Digital 21040), KBD, MOUSE (PS2 style), - SuperI/O (2S, 1P, FD), RTC/NVRAM. Boot ROM is EPROM. PC-AT size. - Runs from standard PC power supply. config ALPHA_EV5 bool - default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR + default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR config ALPHA_CIA bool - depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR + depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR default y config ALPHA_EV56 @@ -358,18 +269,12 @@ config ALPHA_EV56 config ALPHA_EV56 prompt "EV56 CPU (speed >= 333MHz)?" - depends on ALPHA_NORITAKE || ALPHA_PRIMO + depends on ALPHA_NORITAKE || ALPHA_MIKASA config ALPHA_EV56 prompt "EV56 CPU (speed >= 400MHz)?" depends on ALPHA_RAWHIDE -config ALPHA_PRIMO - bool "EV5 CPU daughtercard (model 5/xxx)?" - depends on ALPHA_NORITAKE || ALPHA_MIKASA - help - Say Y if you have an AS 1000 5/xxx or an AS 1000A 5/xxx. - config ALPHA_T2 bool depends on ALPHA_SABLE @@ -416,15 +321,6 @@ config GENERIC_HWEIGHT bool default y if !ALPHA_EV67 -config ALPHA_AVANTI - bool - depends on ALPHA_XL || ALPHA_AVANTI_CH - default y - help - Avanti AS 200, AS 205, AS 250, AS 255, AS 300, and AS 400-based - Alphas. Info at - . - config ALPHA_BROKEN_IRQ_MASK bool depends on ALPHA_GENERIC || ALPHA_PC164 @@ -454,7 +350,7 @@ config ALPHA_QEMU config ALPHA_SRM - bool "Use SRM as bootloader" if ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS || ALPHA_NONAME + bool "Use SRM as bootloader" if ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS depends on TTY default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL help @@ -518,7 +414,7 @@ config ARCH_SPARSEMEM_ENABLE config ALPHA_WTINT bool "Use WTINT" if ALPHA_SRM || ALPHA_GENERIC default y if ALPHA_QEMU - default n if ALPHA_EV5 || ALPHA_EV56 || (ALPHA_EV4 && !ALPHA_LCA) + default n if ALPHA_EV5 || ALPHA_EV56 default n if !ALPHA_SRM && !ALPHA_GENERIC default y if SMP help diff --git a/arch/alpha/include/asm/core_apecs.h b/arch/alpha/include/asm/core_apecs.h deleted file mode 100644 index 69a2fc62c9c3..000000000000 --- a/arch/alpha/include/asm/core_apecs.h +++ /dev/null @@ -1,534 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ALPHA_APECS__H__ -#define __ALPHA_APECS__H__ - -#include -#include - -/* - * APECS is the internal name for the 2107x chipset which provides - * memory controller and PCI access for the 21064 chip based systems. - * - * This file is based on: - * - * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets - * Data Sheet - * - * EC-N0648-72 - * - * - * david.rusling@reo.mts.dec.com Initial Version. - * - */ - -/* - An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address - that get passed through the PCI<->ISA bridge chip. So we've gotta use - both windows to max out the physical memory we can DMA to. Sigh... - - If we try a window at 0 for 1GB as a work-around, we run into conflicts - with ISA/PCI bus memory which can't be relocated, like VGA aperture and - BIOS ROMs. So we must put the windows high enough to avoid these areas. - - We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1, - and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1. - Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually - be used for that range (via virt_to_bus()). - - Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb, - to keep virt_to_bus() from returning an address in the first window, for - a data area that goes beyond the 64Mb first DMA window. Sigh... - The fudge factor MUST match with MAX_DMA_ADDRESS, but - we can't just use that here, because of header file looping... :-( - - Window 1 will be used for all DMA from the ISA bus; yes, that does - limit what memory an ISA floppy or sound card or Ethernet can touch, but - it's also a known limitation on other platforms as well. We use the - same technique that is used on INTEL platforms with similar limitation: - set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init(). - We trust that any ISA bus device drivers will *always* ask for DMAable - memory explicitly via kmalloc()/get_free_pages() flags arguments. - - Note that most PCI bus devices' drivers do *not* explicitly ask for - DMAable memory; they count on being able to DMA to any memory they - get from kmalloc()/get_free_pages(). They will also use window 1 for - any physical memory accesses below 64Mb; the rest will be handled by - window 2, maxing out at 1Gb of memory. I trust this is enough... :-) - - We hope that the area before the first window is large enough so that - there will be no overlap at the top end (64Mb). We *must* locate the - PCI cards' memory just below window 1, so that there's still the - possibility of being able to access it via SPARSE space. This is - important for cards such as the Matrox Millennium, whose Xserver - wants to access memory-mapped registers in byte and short lengths. - - Note that the XL is treated differently from the AVANTI, even though - for most other things they are identical. It didn't seem reasonable to - make the AVANTI support pay for the limitations of the XL. It is true, - however, that an XL kernel will run on an AVANTI without problems. - - %%% All of this should be obviated by the ability to route - everything through the iommu. -*/ - -/* - * 21071-DA Control and Status registers. - * These are used for PCI memory access. - */ -#define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL) -#define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL) -#define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL) -#define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL) -#define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL) -#define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL) - -#define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL) -#define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL) - -#define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL) -#define APECS_IOC_PB2R (IDENT_ADDR + 0x1A0000120UL) - -#define APECS_IOC_PM1R (IDENT_ADDR + 0x1A0000140UL) -#define APECS_IOC_PM2R (IDENT_ADDR + 0x1A0000160UL) - -#define APECS_IOC_HAXR0 (IDENT_ADDR + 0x1A0000180UL) -#define APECS_IOC_HAXR1 (IDENT_ADDR + 0x1A00001A0UL) -#define APECS_IOC_HAXR2 (IDENT_ADDR + 0x1A00001C0UL) - -#define APECS_IOC_PMLT (IDENT_ADDR + 0x1A00001E0UL) - -#define APECS_IOC_TLBTAG0 (IDENT_ADDR + 0x1A0000200UL) -#define APECS_IOC_TLBTAG1 (IDENT_ADDR + 0x1A0000220UL) -#define APECS_IOC_TLBTAG2 (IDENT_ADDR + 0x1A0000240UL) -#define APECS_IOC_TLBTAG3 (IDENT_ADDR + 0x1A0000260UL) -#define APECS_IOC_TLBTAG4 (IDENT_ADDR + 0x1A0000280UL) -#define APECS_IOC_TLBTAG5 (IDENT_ADDR + 0x1A00002A0UL) -#define APECS_IOC_TLBTAG6 (IDENT_ADDR + 0x1A00002C0UL) -#define APECS_IOC_TLBTAG7 (IDENT_ADDR + 0x1A00002E0UL) - -#define APECS_IOC_TLBDATA0 (IDENT_ADDR + 0x1A0000300UL) -#define APECS_IOC_TLBDATA1 (IDENT_ADDR + 0x1A0000320UL) -#define APECS_IOC_TLBDATA2 (IDENT_ADDR + 0x1A0000340UL) -#define APECS_IOC_TLBDATA3 (IDENT_ADDR + 0x1A0000360UL) -#define APECS_IOC_TLBDATA4 (IDENT_ADDR + 0x1A0000380UL) -#define APECS_IOC_TLBDATA5 (IDENT_ADDR + 0x1A00003A0UL) -#define APECS_IOC_TLBDATA6 (IDENT_ADDR + 0x1A00003C0UL) -#define APECS_IOC_TLBDATA7 (IDENT_ADDR + 0x1A00003E0UL) - -#define APECS_IOC_TBIA (IDENT_ADDR + 0x1A0000400UL) - - -/* - * 21071-CA Control and Status registers. - * These are used to program memory timing, - * configure memory and initialise the B-Cache. - */ -#define APECS_MEM_GCR (IDENT_ADDR + 0x180000000UL) -#define APECS_MEM_EDSR (IDENT_ADDR + 0x180000040UL) -#define APECS_MEM_TAR (IDENT_ADDR + 0x180000060UL) -#define APECS_MEM_ELAR (IDENT_ADDR + 0x180000080UL) -#define APECS_MEM_EHAR (IDENT_ADDR + 0x1800000a0UL) -#define APECS_MEM_SFT_RST (IDENT_ADDR + 0x1800000c0UL) -#define APECS_MEM_LDxLAR (IDENT_ADDR + 0x1800000e0UL) -#define APECS_MEM_LDxHAR (IDENT_ADDR + 0x180000100UL) -#define APECS_MEM_GTR (IDENT_ADDR + 0x180000200UL) -#define APECS_MEM_RTR (IDENT_ADDR + 0x180000220UL) -#define APECS_MEM_VFPR (IDENT_ADDR + 0x180000240UL) -#define APECS_MEM_PDLDR (IDENT_ADDR + 0x180000260UL) -#define APECS_MEM_PDhDR (IDENT_ADDR + 0x180000280UL) - -/* Bank x Base Address Register */ -#define APECS_MEM_B0BAR (IDENT_ADDR + 0x180000800UL) -#define APECS_MEM_B1BAR (IDENT_ADDR + 0x180000820UL) -#define APECS_MEM_B2BAR (IDENT_ADDR + 0x180000840UL) -#define APECS_MEM_B3BAR (IDENT_ADDR + 0x180000860UL) -#define APECS_MEM_B4BAR (IDENT_ADDR + 0x180000880UL) -#define APECS_MEM_B5BAR (IDENT_ADDR + 0x1800008A0UL) -#define APECS_MEM_B6BAR (IDENT_ADDR + 0x1800008C0UL) -#define APECS_MEM_B7BAR (IDENT_ADDR + 0x1800008E0UL) -#define APECS_MEM_B8BAR (IDENT_ADDR + 0x180000900UL) - -/* Bank x Configuration Register */ -#define APECS_MEM_B0BCR (IDENT_ADDR + 0x180000A00UL) -#define APECS_MEM_B1BCR (IDENT_ADDR + 0x180000A20UL) -#define APECS_MEM_B2BCR (IDENT_ADDR + 0x180000A40UL) -#define APECS_MEM_B3BCR (IDENT_ADDR + 0x180000A60UL) -#define APECS_MEM_B4BCR (IDENT_ADDR + 0x180000A80UL) -#define APECS_MEM_B5BCR (IDENT_ADDR + 0x180000AA0UL) -#define APECS_MEM_B6BCR (IDENT_ADDR + 0x180000AC0UL) -#define APECS_MEM_B7BCR (IDENT_ADDR + 0x180000AE0UL) -#define APECS_MEM_B8BCR (IDENT_ADDR + 0x180000B00UL) - -/* Bank x Timing Register A */ -#define APECS_MEM_B0TRA (IDENT_ADDR + 0x180000C00UL) -#define APECS_MEM_B1TRA (IDENT_ADDR + 0x180000C20UL) -#define APECS_MEM_B2TRA (IDENT_ADDR + 0x180000C40UL) -#define APECS_MEM_B3TRA (IDENT_ADDR + 0x180000C60UL) -#define APECS_MEM_B4TRA (IDENT_ADDR + 0x180000C80UL) -#define APECS_MEM_B5TRA (IDENT_ADDR + 0x180000CA0UL) -#define APECS_MEM_B6TRA (IDENT_ADDR + 0x180000CC0UL) -#define APECS_MEM_B7TRA (IDENT_ADDR + 0x180000CE0UL) -#define APECS_MEM_B8TRA (IDENT_ADDR + 0x180000D00UL) - -/* Bank x Timing Register B */ -#define APECS_MEM_B0TRB (IDENT_ADDR + 0x180000E00UL) -#define APECS_MEM_B1TRB (IDENT_ADDR + 0x180000E20UL) -#define APECS_MEM_B2TRB (IDENT_ADDR + 0x180000E40UL) -#define APECS_MEM_B3TRB (IDENT_ADDR + 0x180000E60UL) -#define APECS_MEM_B4TRB (IDENT_ADDR + 0x180000E80UL) -#define APECS_MEM_B5TRB (IDENT_ADDR + 0x180000EA0UL) -#define APECS_MEM_B6TRB (IDENT_ADDR + 0x180000EC0UL) -#define APECS_MEM_B7TRB (IDENT_ADDR + 0x180000EE0UL) -#define APECS_MEM_B8TRB (IDENT_ADDR + 0x180000F00UL) - - -/* - * Memory spaces: - */ -#define APECS_IACK_SC (IDENT_ADDR + 0x1b0000000UL) -#define APECS_CONF (IDENT_ADDR + 0x1e0000000UL) -#define APECS_IO (IDENT_ADDR + 0x1c0000000UL) -#define APECS_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) -#define APECS_DENSE_MEM (IDENT_ADDR + 0x300000000UL) - - -/* - * Bit definitions for I/O Controller status register 0: - */ -#define APECS_IOC_STAT0_CMD 0xf -#define APECS_IOC_STAT0_ERR (1<<4) -#define APECS_IOC_STAT0_LOST (1<<5) -#define APECS_IOC_STAT0_THIT (1<<6) -#define APECS_IOC_STAT0_TREF (1<<7) -#define APECS_IOC_STAT0_CODE_SHIFT 8 -#define APECS_IOC_STAT0_CODE_MASK 0x7 -#define APECS_IOC_STAT0_P_NBR_SHIFT 13 -#define APECS_IOC_STAT0_P_NBR_MASK 0x7ffff - -#define APECS_HAE_ADDRESS APECS_IOC_HAXR1 - - -/* - * Data structure for handling APECS machine checks: - */ - -struct el_apecs_mikasa_sysdata_mcheck -{ - unsigned long coma_gcr; - unsigned long coma_edsr; - unsigned long coma_ter; - unsigned long coma_elar; - unsigned long coma_ehar; - unsigned long coma_ldlr; - unsigned long coma_ldhr; - unsigned long coma_base0; - unsigned long coma_base1; - unsigned long coma_base2; - unsigned long coma_base3; - unsigned long coma_cnfg0; - unsigned long coma_cnfg1; - unsigned long coma_cnfg2; - unsigned long coma_cnfg3; - unsigned long epic_dcsr; - unsigned long epic_pear; - unsigned long epic_sear; - unsigned long epic_tbr1; - unsigned long epic_tbr2; - unsigned long epic_pbr1; - unsigned long epic_pbr2; - unsigned long epic_pmr1; - unsigned long epic_pmr2; - unsigned long epic_harx1; - unsigned long epic_harx2; - unsigned long epic_pmlt; - unsigned long epic_tag0; - unsigned long epic_tag1; - unsigned long epic_tag2; - unsigned long epic_tag3; - unsigned long epic_tag4; - unsigned long epic_tag5; - unsigned long epic_tag6; - unsigned long epic_tag7; - unsigned long epic_data0; - unsigned long epic_data1; - unsigned long epic_data2; - unsigned long epic_data3; - unsigned long epic_data4; - unsigned long epic_data5; - unsigned long epic_data6; - unsigned long epic_data7; - - unsigned long pceb_vid; - unsigned long pceb_did; - unsigned long pceb_revision; - unsigned long pceb_command; - unsigned long pceb_status; - unsigned long pceb_latency; - unsigned long pceb_control; - unsigned long pceb_arbcon; - unsigned long pceb_arbpri; - - unsigned long esc_id; - unsigned long esc_revision; - unsigned long esc_int0; - unsigned long esc_int1; - unsigned long esc_elcr0; - unsigned long esc_elcr1; - unsigned long esc_last_eisa; - unsigned long esc_nmi_stat; - - unsigned long pci_ir; - unsigned long pci_imr; - unsigned long svr_mgr; -}; - -/* This for the normal APECS machines. */ -struct el_apecs_sysdata_mcheck -{ - unsigned long coma_gcr; - unsigned long coma_edsr; - unsigned long coma_ter; - unsigned long coma_elar; - unsigned long coma_ehar; - unsigned long coma_ldlr; - unsigned long coma_ldhr; - unsigned long coma_base0; - unsigned long coma_base1; - unsigned long coma_base2; - unsigned long coma_cnfg0; - unsigned long coma_cnfg1; - unsigned long coma_cnfg2; - unsigned long epic_dcsr; - unsigned long epic_pear; - unsigned long epic_sear; - unsigned long epic_tbr1; - unsigned long epic_tbr2; - unsigned long epic_pbr1; - unsigned long epic_pbr2; - unsigned long epic_pmr1; - unsigned long epic_pmr2; - unsigned long epic_harx1; - unsigned long epic_harx2; - unsigned long epic_pmlt; - unsigned long epic_tag0; - unsigned long epic_tag1; - unsigned long epic_tag2; - unsigned long epic_tag3; - unsigned long epic_tag4; - unsigned long epic_tag5; - unsigned long epic_tag6; - unsigned long epic_tag7; - unsigned long epic_data0; - unsigned long epic_data1; - unsigned long epic_data2; - unsigned long epic_data3; - unsigned long epic_data4; - unsigned long epic_data5; - unsigned long epic_data6; - unsigned long epic_data7; -}; - -struct el_apecs_procdata -{ - unsigned long paltemp[32]; /* PAL TEMP REGS. */ - /* EV4-specific fields */ - unsigned long exc_addr; /* Address of excepting instruction. */ - unsigned long exc_sum; /* Summary of arithmetic traps. */ - unsigned long exc_mask; /* Exception mask (from exc_sum). */ - unsigned long iccsr; /* IBox hardware enables. */ - unsigned long pal_base; /* Base address for PALcode. */ - unsigned long hier; /* Hardware Interrupt Enable. */ - unsigned long hirr; /* Hardware Interrupt Request. */ - unsigned long csr; /* D-stream fault info. */ - unsigned long dc_stat; /* D-cache status (ECC/Parity Err). */ - unsigned long dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ - unsigned long abox_ctl; /* ABox Control Register. */ - unsigned long biu_stat; /* BIU Status. */ - unsigned long biu_addr; /* BUI Address. */ - unsigned long biu_ctl; /* BIU Control. */ - unsigned long fill_syndrome;/* For correcting ECC errors. */ - unsigned long fill_addr; /* Cache block which was being read */ - unsigned long va; /* Effective VA of fault or miss. */ - unsigned long bc_tag; /* Backup Cache Tag Probe Results.*/ -}; - - -#ifdef __KERNEL__ - -#ifndef __EXTERN_INLINE -#define __EXTERN_INLINE extern inline -#define __IO_EXTERN_INLINE -#endif - -/* - * I/O functions: - * - * Unlike Jensen, the APECS machines have no concept of local - * I/O---everything goes over the PCI bus. - * - * There is plenty room for optimization here. In particular, - * the Alpha's insb/insw/extb/extw should be useful in moving - * data to/from the right byte-lanes. - */ - -#define vip volatile int __force * -#define vuip volatile unsigned int __force * -#define vulp volatile unsigned long __force * - -#define APECS_SET_HAE \ - do { \ - if (addr >= (1UL << 24)) { \ - unsigned long msb = addr & 0xf8000000; \ - addr -= msb; \ - set_hae(msb); \ - } \ - } while (0) - -__EXTERN_INLINE u8 apecs_ioread8(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long result, base_and_type; - - if (addr >= APECS_DENSE_MEM) { - addr -= APECS_DENSE_MEM; - APECS_SET_HAE; - base_and_type = APECS_SPARSE_MEM + 0x00; - } else { - addr -= APECS_IO; - base_and_type = APECS_IO + 0x00; - } - - result = *(vip) ((addr << 5) + base_and_type); - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long w, base_and_type; - - if (addr >= APECS_DENSE_MEM) { - addr -= APECS_DENSE_MEM; - APECS_SET_HAE; - base_and_type = APECS_SPARSE_MEM + 0x00; - } else { - addr -= APECS_IO; - base_and_type = APECS_IO + 0x00; - } - - w = __kernel_insbl(b, addr & 3); - *(vuip) ((addr << 5) + base_and_type) = w; -} - -__EXTERN_INLINE u16 apecs_ioread16(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long result, base_and_type; - - if (addr >= APECS_DENSE_MEM) { - addr -= APECS_DENSE_MEM; - APECS_SET_HAE; - base_and_type = APECS_SPARSE_MEM + 0x08; - } else { - addr -= APECS_IO; - base_and_type = APECS_IO + 0x08; - } - - result = *(vip) ((addr << 5) + base_and_type); - return __kernel_extwl(result, addr & 3); -} - -__EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long w, base_and_type; - - if (addr >= APECS_DENSE_MEM) { - addr -= APECS_DENSE_MEM; - APECS_SET_HAE; - base_and_type = APECS_SPARSE_MEM + 0x08; - } else { - addr -= APECS_IO; - base_and_type = APECS_IO + 0x08; - } - - w = __kernel_inswl(b, addr & 3); - *(vuip) ((addr << 5) + base_and_type) = w; -} - -__EXTERN_INLINE u32 apecs_ioread32(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < APECS_DENSE_MEM) - addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18; - return *(vuip)addr; -} - -__EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < APECS_DENSE_MEM) - addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18; - *(vuip)addr = b; -} - -__EXTERN_INLINE u64 apecs_ioread64(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < APECS_DENSE_MEM) - addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18; - return *(vulp)addr; -} - -__EXTERN_INLINE void apecs_iowrite64(u64 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < APECS_DENSE_MEM) - addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18; - *(vulp)addr = b; -} - -__EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr) -{ - return (void __iomem *)(addr + APECS_IO); -} - -__EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr, - unsigned long size) -{ - return (void __iomem *)(addr + APECS_DENSE_MEM); -} - -__EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr) -{ - return addr >= IDENT_ADDR + 0x180000000UL; -} - -__EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= APECS_DENSE_MEM; -} - -#undef APECS_SET_HAE - -#undef vip -#undef vuip -#undef vulp - -#undef __IO_PREFIX -#define __IO_PREFIX apecs -#define apecs_trivial_io_bw 0 -#define apecs_trivial_io_lq 0 -#define apecs_trivial_rw_bw 2 -#define apecs_trivial_rw_lq 1 -#define apecs_trivial_iounmap 1 -#include - -#ifdef __IO_EXTERN_INLINE -#undef __EXTERN_INLINE -#undef __IO_EXTERN_INLINE -#endif - -#endif /* __KERNEL__ */ - -#endif /* __ALPHA_APECS__H__ */ diff --git a/arch/alpha/include/asm/core_lca.h b/arch/alpha/include/asm/core_lca.h deleted file mode 100644 index d8c3e72ef8f6..000000000000 --- a/arch/alpha/include/asm/core_lca.h +++ /dev/null @@ -1,378 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ALPHA_LCA__H__ -#define __ALPHA_LCA__H__ - -#include -#include - -/* - * Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068, - * for example). - * - * This file is based on: - * - * DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors - * Hardware Reference Manual; Digital Equipment Corp.; May 1994; - * Maynard, MA; Order Number: EC-N2681-71. - */ - -/* - * NOTE: The LCA uses a Host Address Extension (HAE) register to access - * PCI addresses that are beyond the first 27 bits of address - * space. Updating the HAE requires an external cycle (and - * a memory barrier), which tends to be slow. Instead of updating - * it on each sparse memory access, we keep the current HAE value - * cached in variable cache_hae. Only if the cached HAE differs - * from the desired HAE value do we actually updated HAE register. - * The HAE register is preserved by the interrupt handler entry/exit - * code, so this scheme works even in the presence of interrupts. - * - * Dense memory space doesn't require the HAE, but is restricted to - * aligned 32 and 64 bit accesses. Special Cycle and Interrupt - * Acknowledge cycles may also require the use of the HAE. The LCA - * limits I/O address space to the bottom 24 bits of address space, - * but this easily covers the 16 bit ISA I/O address space. - */ - -/* - * NOTE 2! The memory operations do not set any memory barriers, as - * it's not needed for cases like a frame buffer that is essentially - * memory-like. You need to do them by hand if the operations depend - * on ordering. - * - * Similarly, the port I/O operations do a "mb" only after a write - * operation: if an mb is needed before (as in the case of doing - * memory mapped I/O first, and then a port I/O operation to the same - * device), it needs to be done by hand. - * - * After the above has bitten me 100 times, I'll give up and just do - * the mb all the time, but right now I'm hoping this will work out. - * Avoiding mb's may potentially be a noticeable speed improvement, - * but I can't honestly say I've tested it. - * - * Handling interrupts that need to do mb's to synchronize to - * non-interrupts is another fun race area. Don't do it (because if - * you do, I'll have to do *everything* with interrupts disabled, - * ugh). - */ - -/* - * Memory Controller registers: - */ -#define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL) -#define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL) -#define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL) -#define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL) -#define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL) -#define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL) -#define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL) -#define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL) -#define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL) -#define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL) -#define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL) -#define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL) -#define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL) -#define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL) -#define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL) -#define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL) -#define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL) -#define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL) -#define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL) - -/* - * I/O Controller registers: - */ -#define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL) -#define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL) -#define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL) -#define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL) -#define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL) -#define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL) -#define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL) -#define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL) -#define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL) -#define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL) -#define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL) -#define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL) -#define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL) -#define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL) -#define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL) -#define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL) -#define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL) -#define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL) -#define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL) -#define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL) -#define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL) -#define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL) - -/* - * Memory spaces: - */ -#define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL) -#define LCA_CONF (IDENT_ADDR + 0x1e0000000UL) -#define LCA_IO (IDENT_ADDR + 0x1c0000000UL) -#define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL) -#define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL) - -/* - * Bit definitions for I/O Controller status register 0: - */ -#define LCA_IOC_STAT0_CMD 0xf -#define LCA_IOC_STAT0_ERR (1<<4) -#define LCA_IOC_STAT0_LOST (1<<5) -#define LCA_IOC_STAT0_THIT (1<<6) -#define LCA_IOC_STAT0_TREF (1<<7) -#define LCA_IOC_STAT0_CODE_SHIFT 8 -#define LCA_IOC_STAT0_CODE_MASK 0x7 -#define LCA_IOC_STAT0_P_NBR_SHIFT 13 -#define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff - -#define LCA_HAE_ADDRESS LCA_IOC_HAE - -/* LCA PMR Power Management register defines */ -#define LCA_PMR_ADDR (IDENT_ADDR + 0x120000098UL) -#define LCA_PMR_PDIV 0x7 /* Primary clock divisor */ -#define LCA_PMR_ODIV 0x38 /* Override clock divisor */ -#define LCA_PMR_INTO 0x40 /* Interrupt override */ -#define LCA_PMR_DMAO 0x80 /* DMA override */ -#define LCA_PMR_OCCEB 0xffff0000L /* Override cycle counter - even bits */ -#define LCA_PMR_OCCOB 0xffff000000000000L /* Override cycle counter - even bits */ -#define LCA_PMR_PRIMARY_MASK 0xfffffffffffffff8L - -/* LCA PMR Macros */ - -#define LCA_READ_PMR (*(volatile unsigned long *)LCA_PMR_ADDR) -#define LCA_WRITE_PMR(d) (*((volatile unsigned long *)LCA_PMR_ADDR) = (d)) - -#define LCA_GET_PRIMARY(r) ((r) & LCA_PMR_PDIV) -#define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV) -#define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c))) - -/* LCA PMR Divisor values */ -#define LCA_PMR_DIV_1 0x0 -#define LCA_PMR_DIV_1_5 0x1 -#define LCA_PMR_DIV_2 0x2 -#define LCA_PMR_DIV_4 0x3 -#define LCA_PMR_DIV_8 0x4 -#define LCA_PMR_DIV_16 0x5 -#define LCA_PMR_DIV_MIN DIV_1 -#define LCA_PMR_DIV_MAX DIV_16 - - -/* - * Data structure for handling LCA machine checks. Correctable errors - * result in a short logout frame, uncorrectable ones in a long one. - */ -struct el_lca_mcheck_short { - struct el_common h; /* common logout header */ - unsigned long esr; /* error-status register */ - unsigned long ear; /* error-address register */ - unsigned long dc_stat; /* dcache status register */ - unsigned long ioc_stat0; /* I/O controller status register 0 */ - unsigned long ioc_stat1; /* I/O controller status register 1 */ -}; - -struct el_lca_mcheck_long { - struct el_common h; /* common logout header */ - unsigned long pt[31]; /* PAL temps */ - unsigned long exc_addr; /* exception address */ - unsigned long pad1[3]; - unsigned long pal_base; /* PALcode base address */ - unsigned long hier; /* hw interrupt enable */ - unsigned long hirr; /* hw interrupt request */ - unsigned long mm_csr; /* MMU control & status */ - unsigned long dc_stat; /* data cache status */ - unsigned long dc_addr; /* data cache addr register */ - unsigned long abox_ctl; /* address box control register */ - unsigned long esr; /* error status register */ - unsigned long ear; /* error address register */ - unsigned long car; /* cache control register */ - unsigned long ioc_stat0; /* I/O controller status register 0 */ - unsigned long ioc_stat1; /* I/O controller status register 1 */ - unsigned long va; /* virtual address register */ -}; - -union el_lca { - struct el_common * c; - struct el_lca_mcheck_long * l; - struct el_lca_mcheck_short * s; -}; - -#ifdef __KERNEL__ - -#ifndef __EXTERN_INLINE -#define __EXTERN_INLINE extern inline -#define __IO_EXTERN_INLINE -#endif - -/* - * I/O functions: - * - * Unlike Jensen, the Noname machines have no concept of local - * I/O---everything goes over the PCI bus. - * - * There is plenty room for optimization here. In particular, - * the Alpha's insb/insw/extb/extw should be useful in moving - * data to/from the right byte-lanes. - */ - -#define vip volatile int __force * -#define vuip volatile unsigned int __force * -#define vulp volatile unsigned long __force * - -#define LCA_SET_HAE \ - do { \ - if (addr >= (1UL << 24)) { \ - unsigned long msb = addr & 0xf8000000; \ - addr -= msb; \ - set_hae(msb); \ - } \ - } while (0) - - -__EXTERN_INLINE u8 lca_ioread8(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long result, base_and_type; - - if (addr >= LCA_DENSE_MEM) { - addr -= LCA_DENSE_MEM; - LCA_SET_HAE; - base_and_type = LCA_SPARSE_MEM + 0x00; - } else { - addr -= LCA_IO; - base_and_type = LCA_IO + 0x00; - } - - result = *(vip) ((addr << 5) + base_and_type); - return __kernel_extbl(result, addr & 3); -} - -__EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long w, base_and_type; - - if (addr >= LCA_DENSE_MEM) { - addr -= LCA_DENSE_MEM; - LCA_SET_HAE; - base_and_type = LCA_SPARSE_MEM + 0x00; - } else { - addr -= LCA_IO; - base_and_type = LCA_IO + 0x00; - } - - w = __kernel_insbl(b, addr & 3); - *(vuip) ((addr << 5) + base_and_type) = w; -} - -__EXTERN_INLINE u16 lca_ioread16(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long result, base_and_type; - - if (addr >= LCA_DENSE_MEM) { - addr -= LCA_DENSE_MEM; - LCA_SET_HAE; - base_and_type = LCA_SPARSE_MEM + 0x08; - } else { - addr -= LCA_IO; - base_and_type = LCA_IO + 0x08; - } - - result = *(vip) ((addr << 5) + base_and_type); - return __kernel_extwl(result, addr & 3); -} - -__EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - unsigned long w, base_and_type; - - if (addr >= LCA_DENSE_MEM) { - addr -= LCA_DENSE_MEM; - LCA_SET_HAE; - base_and_type = LCA_SPARSE_MEM + 0x08; - } else { - addr -= LCA_IO; - base_and_type = LCA_IO + 0x08; - } - - w = __kernel_inswl(b, addr & 3); - *(vuip) ((addr << 5) + base_and_type) = w; -} - -__EXTERN_INLINE u32 lca_ioread32(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < LCA_DENSE_MEM) - addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; - return *(vuip)addr; -} - -__EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < LCA_DENSE_MEM) - addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; - *(vuip)addr = b; -} - -__EXTERN_INLINE u64 lca_ioread64(const void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < LCA_DENSE_MEM) - addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; - return *(vulp)addr; -} - -__EXTERN_INLINE void lca_iowrite64(u64 b, void __iomem *xaddr) -{ - unsigned long addr = (unsigned long) xaddr; - if (addr < LCA_DENSE_MEM) - addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18; - *(vulp)addr = b; -} - -__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr) -{ - return (void __iomem *)(addr + LCA_IO); -} - -__EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr, - unsigned long size) -{ - return (void __iomem *)(addr + LCA_DENSE_MEM); -} - -__EXTERN_INLINE int lca_is_ioaddr(unsigned long addr) -{ - return addr >= IDENT_ADDR + 0x120000000UL; -} - -__EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr) -{ - return (unsigned long)addr >= LCA_DENSE_MEM; -} - -#undef vip -#undef vuip -#undef vulp - -#undef __IO_PREFIX -#define __IO_PREFIX lca -#define lca_trivial_rw_bw 2 -#define lca_trivial_rw_lq 1 -#define lca_trivial_io_bw 0 -#define lca_trivial_io_lq 0 -#define lca_trivial_iounmap 1 -#include - -#ifdef __IO_EXTERN_INLINE -#undef __EXTERN_INLINE -#undef __IO_EXTERN_INLINE -#endif - -#endif /* __KERNEL__ */ - -#endif /* __ALPHA_LCA__H__ */ diff --git a/arch/alpha/include/asm/dma.h b/arch/alpha/include/asm/dma.h index a04d76b96089..3a88812b7165 100644 --- a/arch/alpha/include/asm/dma.h +++ b/arch/alpha/include/asm/dma.h @@ -82,11 +82,6 @@ just a wiring limit. */ -/* The maximum address for ISA DMA transfer on Alpha XL, due to an - hardware SIO limitation, is 64MB. -*/ -#define ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL - /* The maximum address for ISA DMA transfer on RUFFIAN, due to an hardware SIO limitation, is 16MB. */ @@ -107,9 +102,7 @@ #ifdef CONFIG_ALPHA_GENERIC # define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address) #else -# if defined(CONFIG_ALPHA_XL) -# define MAX_ISA_DMA_ADDRESS ALPHA_XL_MAX_ISA_DMA_ADDRESS -# elif defined(CONFIG_ALPHA_RUFFIAN) +# if defined(CONFIG_ALPHA_RUFFIAN) # define MAX_ISA_DMA_ADDRESS ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS # elif defined(CONFIG_ALPHA_SABLE) # define MAX_ISA_DMA_ADDRESS ALPHA_SABLE_MAX_ISA_DMA_ADDRESS diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h index 0c54ddb5b33e..2bb8cbeedf91 100644 --- a/arch/alpha/include/asm/io.h +++ b/arch/alpha/include/asm/io.h @@ -203,14 +203,10 @@ static inline int generic_is_mmio(const volatile void __iomem *a) #else -#if defined(CONFIG_ALPHA_APECS) -# include -#elif defined(CONFIG_ALPHA_CIA) +#if defined(CONFIG_ALPHA_CIA) # include #elif defined(CONFIG_ALPHA_IRONGATE) # include -#elif defined(CONFIG_ALPHA_LCA) -# include #elif defined(CONFIG_ALPHA_MARVEL) # include #elif defined(CONFIG_ALPHA_MCPCIA) diff --git a/arch/alpha/include/asm/irq.h b/arch/alpha/include/asm/irq.h index 442097c56934..e7d22357a5a6 100644 --- a/arch/alpha/include/asm/irq.h +++ b/arch/alpha/include/asm/irq.h @@ -31,16 +31,12 @@ # define NR_IRQS (32768 + 16) /* marvel - 32 pids */ # endif -#elif defined(CONFIG_ALPHA_CABRIOLET) || \ - defined(CONFIG_ALPHA_EB66P) || \ - defined(CONFIG_ALPHA_EB164) || \ +#elif defined(CONFIG_ALPHA_EB164) || \ defined(CONFIG_ALPHA_PC164) || \ defined(CONFIG_ALPHA_LX164) # define NR_IRQS 35 -#elif defined(CONFIG_ALPHA_EB66) || \ - defined(CONFIG_ALPHA_EB64P) || \ - defined(CONFIG_ALPHA_MIKASA) +#elif defined(CONFIG_ALPHA_MIKASA) # define NR_IRQS 32 #elif defined(CONFIG_ALPHA_ALCOR) || \ diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index 706ce8625e35..bd5d62fa4a9a 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -22,14 +22,14 @@ obj-$(CONFIG_AUDIT) += audit.o ifdef CONFIG_ALPHA_GENERIC -obj-y += core_apecs.o core_cia.o core_irongate.o core_lca.o \ +obj-y += core_cia.o core_irongate.o \ core_mcpcia.o core_polaris.o core_t2.o \ core_tsunami.o -obj-y += sys_alcor.o sys_cabriolet.o sys_dp264.o sys_eb64p.o sys_eiger.o \ +obj-y += sys_alcor.o sys_cabriolet.o sys_dp264.o sys_eiger.o \ sys_miata.o sys_mikasa.o sys_nautilus.o \ sys_noritake.o sys_rawhide.o sys_ruffian.o sys_rx164.o \ - sys_sable.o sys_sio.o sys_sx164.o sys_takara.o + sys_sable.o sys_sx164.o sys_takara.o ifndef CONFIG_ALPHA_LEGACY_START_ADDRESS obj-y += core_marvel.o core_titan.o core_wildfire.o @@ -48,10 +48,8 @@ else obj-$(CONFIG_ALPHA_SRM) += srmcons.o # Core logic support -obj-$(CONFIG_ALPHA_APECS) += core_apecs.o obj-$(CONFIG_ALPHA_CIA) += core_cia.o obj-$(CONFIG_ALPHA_IRONGATE) += core_irongate.o -obj-$(CONFIG_ALPHA_LCA) += core_lca.o obj-$(CONFIG_ALPHA_MARVEL) += core_marvel.o gct.o obj-$(CONFIG_ALPHA_MCPCIA) += core_mcpcia.o obj-$(CONFIG_ALPHA_POLARIS) += core_polaris.o @@ -62,12 +60,8 @@ obj-$(CONFIG_ALPHA_WILDFIRE) += core_wildfire.o # Board support obj-$(CONFIG_ALPHA_ALCOR) += sys_alcor.o irq_i8259.o irq_srm.o -obj-$(CONFIG_ALPHA_CABRIOLET) += sys_cabriolet.o irq_i8259.o irq_srm.o \ - pc873xx.o obj-$(CONFIG_ALPHA_EB164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ pc873xx.o -obj-$(CONFIG_ALPHA_EB66P) += sys_cabriolet.o irq_i8259.o irq_srm.o \ - pc873xx.o obj-$(CONFIG_ALPHA_LX164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ smc37c93x.o obj-$(CONFIG_ALPHA_PC164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ @@ -75,8 +69,6 @@ obj-$(CONFIG_ALPHA_PC164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ obj-$(CONFIG_ALPHA_DP264) += sys_dp264.o irq_i8259.o es1888.o smc37c669.o obj-$(CONFIG_ALPHA_SHARK) += sys_dp264.o irq_i8259.o es1888.o smc37c669.o obj-$(CONFIG_ALPHA_TITAN) += sys_titan.o irq_i8259.o smc37c669.o -obj-$(CONFIG_ALPHA_EB64P) += sys_eb64p.o irq_i8259.o -obj-$(CONFIG_ALPHA_EB66) += sys_eb64p.o irq_i8259.o obj-$(CONFIG_ALPHA_EIGER) += sys_eiger.o irq_i8259.o obj-$(CONFIG_ALPHA_MARVEL) += sys_marvel.o obj-$(CONFIG_ALPHA_MIATA) += sys_miata.o irq_pyxis.o irq_i8259.o \ @@ -88,11 +80,6 @@ obj-$(CONFIG_ALPHA_RAWHIDE) += sys_rawhide.o irq_i8259.o obj-$(CONFIG_ALPHA_RUFFIAN) += sys_ruffian.o irq_pyxis.o irq_i8259.o obj-$(CONFIG_ALPHA_RX164) += sys_rx164.o irq_i8259.o obj-$(CONFIG_ALPHA_SABLE) += sys_sable.o -obj-$(CONFIG_ALPHA_BOOK1) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o -obj-$(CONFIG_ALPHA_AVANTI) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o -obj-$(CONFIG_ALPHA_NONAME) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o -obj-$(CONFIG_ALPHA_P2K) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o -obj-$(CONFIG_ALPHA_XL) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o obj-$(CONFIG_ALPHA_SX164) += sys_sx164.o irq_pyxis.o irq_i8259.o \ irq_srm.o smc37c669.o obj-$(CONFIG_ALPHA_TAKARA) += sys_takara.o irq_i8259.o pc873xx.o diff --git a/arch/alpha/kernel/core_apecs.c b/arch/alpha/kernel/core_apecs.c deleted file mode 100644 index 6df765ff2b10..000000000000 --- a/arch/alpha/kernel/core_apecs.c +++ /dev/null @@ -1,420 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/alpha/kernel/core_apecs.c - * - * Rewritten for Apecs from the lca.c from: - * - * Written by David Mosberger (davidm@cs.arizona.edu) with some code - * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit - * bios code. - * - * Code common to all APECS core logic chips. - */ - -#define __EXTERN_INLINE inline -#include -#include -#undef __EXTERN_INLINE - -#include -#include -#include - -#include -#include -#include - -#include "proto.h" -#include "pci_impl.h" - -/* - * NOTE: Herein lie back-to-back mb instructions. They are magic. - * One plausible explanation is that the i/o controller does not properly - * handle the system transaction. Another involves timing. Ho hum. - */ - -/* - * BIOS32-style PCI interface: - */ - -#define DEBUG_CONFIG 0 - -#if DEBUG_CONFIG -# define DBGC(args) printk args -#else -# define DBGC(args) -#endif - -#define vuip volatile unsigned int * - -/* - * Given a bus, device, and function number, compute resulting - * configuration space address and setup the APECS_HAXR2 register - * accordingly. It is therefore not safe to have concurrent - * invocations to configuration space access routines, but there - * really shouldn't be any need for this. - * - * Type 0: - * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * 31:11 Device select bit. - * 10:8 Function number - * 7:2 Register number - * - * Type 1: - * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * 31:24 reserved - * 23:16 bus number (8 bits = 128 possible buses) - * 15:11 Device number (5 bits) - * 10:8 function number - * 7:2 register number - * - * Notes: - * The function number selects which function of a multi-function device - * (e.g., SCSI and Ethernet). - * - * The register selects a DWORD (32 bit) register offset. Hence it - * doesn't get shifted by 2 bits as we want to "drop" the bottom two - * bits. - */ - -static int -mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, - unsigned long *pci_addr, unsigned char *type1) -{ - unsigned long addr; - u8 bus = pbus->number; - - DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x," - " pci_addr=0x%p, type1=0x%p)\n", - bus, device_fn, where, pci_addr, type1)); - - if (bus == 0) { - int device = device_fn >> 3; - - /* type 0 configuration cycle: */ - - if (device > 20) { - DBGC(("mk_conf_addr: device (%d) > 20, returning -1\n", - device)); - return -1; - } - - *type1 = 0; - addr = (device_fn << 8) | (where); - } else { - /* type 1 configuration cycle: */ - *type1 = 1; - addr = (bus << 16) | (device_fn << 8) | (where); - } - *pci_addr = addr; - DBGC(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); - return 0; -} - -static unsigned int -conf_read(unsigned long addr, unsigned char type1) -{ - unsigned long flags; - unsigned int stat0, value; - unsigned int haxr2 = 0; - - local_irq_save(flags); /* avoid getting hit by machine check */ - - DBGC(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1)); - - /* Reset status register to avoid losing errors. */ - stat0 = *(vuip)APECS_IOC_DCSR; - *(vuip)APECS_IOC_DCSR = stat0; - mb(); - DBGC(("conf_read: APECS DCSR was 0x%x\n", stat0)); - - /* If Type1 access, must set HAE #2. */ - if (type1) { - haxr2 = *(vuip)APECS_IOC_HAXR2; - mb(); - *(vuip)APECS_IOC_HAXR2 = haxr2 | 1; - DBGC(("conf_read: TYPE1 access\n")); - } - - draina(); - mcheck_expected(0) = 1; - mcheck_taken(0) = 0; - mb(); - - /* Access configuration space. */ - - /* Some SRMs step on these registers during a machine check. */ - asm volatile("ldl %0,%1; mb; mb" : "=r"(value) : "m"(*(vuip)addr) - : "$9", "$10", "$11", "$12", "$13", "$14", "memory"); - - if (mcheck_taken(0)) { - mcheck_taken(0) = 0; - value = 0xffffffffU; - mb(); - } - mcheck_expected(0) = 0; - mb(); - -#if 1 - /* - * david.rusling@reo.mts.dec.com. This code is needed for the - * EB64+ as it does not generate a machine check (why I don't - * know). When we build kernels for one particular platform - * then we can make this conditional on the type. - */ - draina(); - - /* Now look for any errors. */ - stat0 = *(vuip)APECS_IOC_DCSR; - DBGC(("conf_read: APECS DCSR after read 0x%x\n", stat0)); - - /* Is any error bit set? */ - if (stat0 & 0xffe0U) { - /* If not NDEV, print status. */ - if (!(stat0 & 0x0800)) { - printk("apecs.c:conf_read: got stat0=%x\n", stat0); - } - - /* Reset error status. */ - *(vuip)APECS_IOC_DCSR = stat0; - mb(); - wrmces(0x7); /* reset machine check */ - value = 0xffffffff; - } -#endif - - /* If Type1 access, must reset HAE #2 so normal IO space ops work. */ - if (type1) { - *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1; - mb(); - } - local_irq_restore(flags); - - return value; -} - -static void -conf_write(unsigned long addr, unsigned int value, unsigned char type1) -{ - unsigned long flags; - unsigned int stat0; - unsigned int haxr2 = 0; - - local_irq_save(flags); /* avoid getting hit by machine check */ - - /* Reset status register to avoid losing errors. */ - stat0 = *(vuip)APECS_IOC_DCSR; - *(vuip)APECS_IOC_DCSR = stat0; - mb(); - - /* If Type1 access, must set HAE #2. */ - if (type1) { - haxr2 = *(vuip)APECS_IOC_HAXR2; - mb(); - *(vuip)APECS_IOC_HAXR2 = haxr2 | 1; - } - - draina(); - mcheck_expected(0) = 1; - mb(); - - /* Access configuration space. */ - *(vuip)addr = value; - mb(); - mb(); /* magic */ - mcheck_expected(0) = 0; - mb(); - -#if 1 - /* - * david.rusling@reo.mts.dec.com. This code is needed for the - * EB64+ as it does not generate a machine check (why I don't - * know). When we build kernels for one particular platform - * then we can make this conditional on the type. - */ - draina(); - - /* Now look for any errors. */ - stat0 = *(vuip)APECS_IOC_DCSR; - - /* Is any error bit set? */ - if (stat0 & 0xffe0U) { - /* If not NDEV, print status. */ - if (!(stat0 & 0x0800)) { - printk("apecs.c:conf_write: got stat0=%x\n", stat0); - } - - /* Reset error status. */ - *(vuip)APECS_IOC_DCSR = stat0; - mb(); - wrmces(0x7); /* reset machine check */ - } -#endif - - /* If Type1 access, must reset HAE #2 so normal IO space ops work. */ - if (type1) { - *(vuip)APECS_IOC_HAXR2 = haxr2 & ~1; - mb(); - } - local_irq_restore(flags); -} - -static int -apecs_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr, pci_addr; - unsigned char type1; - long mask; - int shift; - - if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1)) - return PCIBIOS_DEVICE_NOT_FOUND; - - mask = (size - 1) * 8; - shift = (where & 3) * 8; - addr = (pci_addr << 5) + mask + APECS_CONF; - *value = conf_read(addr, type1) >> (shift); - return PCIBIOS_SUCCESSFUL; -} - -static int -apecs_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr, pci_addr; - unsigned char type1; - long mask; - - if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1)) - return PCIBIOS_DEVICE_NOT_FOUND; - - mask = (size - 1) * 8; - addr = (pci_addr << 5) + mask + APECS_CONF; - conf_write(addr, value << ((where & 3) * 8), type1); - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops apecs_pci_ops = -{ - .read = apecs_read_config, - .write = apecs_write_config, -}; - -void -apecs_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) -{ - wmb(); - *(vip)APECS_IOC_TBIA = 0; - mb(); -} - -void __init -apecs_init_arch(void) -{ - struct pci_controller *hose; - - /* - * Create our single hose. - */ - - pci_isa_hose = hose = alloc_pci_controller(); - hose->io_space = &ioport_resource; - hose->mem_space = &iomem_resource; - hose->index = 0; - - hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR; - hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR; - hose->sparse_io_base = APECS_IO - IDENT_ADDR; - hose->dense_io_base = 0; - - /* - * Set up the PCI to main memory translation windows. - * - * Window 1 is direct access 1GB at 1GB - * Window 2 is scatter-gather 8MB at 8MB (for isa) - */ - hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, - SMP_CACHE_BYTES); - hose->sg_pci = NULL; - __direct_map_base = 0x40000000; - __direct_map_size = 0x40000000; - - *(vuip)APECS_IOC_PB1R = __direct_map_base | 0x00080000; - *(vuip)APECS_IOC_PM1R = (__direct_map_size - 1) & 0xfff00000U; - *(vuip)APECS_IOC_TB1R = 0; - - *(vuip)APECS_IOC_PB2R = hose->sg_isa->dma_base | 0x000c0000; - *(vuip)APECS_IOC_PM2R = (hose->sg_isa->size - 1) & 0xfff00000; - *(vuip)APECS_IOC_TB2R = virt_to_phys(hose->sg_isa->ptes) >> 1; - - apecs_pci_tbi(hose, 0, -1); - - /* - * Finally, clear the HAXR2 register, which gets used - * for PCI Config Space accesses. That is the way - * we want to use it, and we do not want to depend on - * what ARC or SRM might have left behind... - */ - *(vuip)APECS_IOC_HAXR2 = 0; - mb(); -} - -void -apecs_pci_clr_err(void) -{ - unsigned int jd; - - jd = *(vuip)APECS_IOC_DCSR; - if (jd & 0xffe0L) { - *(vuip)APECS_IOC_SEAR; - *(vuip)APECS_IOC_DCSR = jd | 0xffe1L; - mb(); - *(vuip)APECS_IOC_DCSR; - } - *(vuip)APECS_IOC_TBIA = (unsigned int)APECS_IOC_TBIA; - mb(); - *(vuip)APECS_IOC_TBIA; -} - -void -apecs_machine_check(unsigned long vector, unsigned long la_ptr) -{ - struct el_common *mchk_header; - struct el_apecs_procdata *mchk_procdata; - struct el_apecs_sysdata_mcheck *mchk_sysdata; - - mchk_header = (struct el_common *)la_ptr; - - mchk_procdata = (struct el_apecs_procdata *) - (la_ptr + mchk_header->proc_offset - - sizeof(mchk_procdata->paltemp)); - - mchk_sysdata = (struct el_apecs_sysdata_mcheck *) - (la_ptr + mchk_header->sys_offset); - - - /* Clear the error before any reporting. */ - mb(); - mb(); /* magic */ - draina(); - apecs_pci_clr_err(); - wrmces(0x7); /* reset machine check pending flag */ - mb(); - - process_mcheck_info(vector, la_ptr, "APECS", - (mcheck_expected(0) - && (mchk_sysdata->epic_dcsr & 0x0c00UL))); -} diff --git a/arch/alpha/kernel/core_lca.c b/arch/alpha/kernel/core_lca.c deleted file mode 100644 index 4616b11643d5..000000000000 --- a/arch/alpha/kernel/core_lca.c +++ /dev/null @@ -1,473 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/alpha/kernel/core_lca.c - * - * Written by David Mosberger (davidm@cs.arizona.edu) with some code - * taken from Dave Rusling's (david.rusling@reo.mts.dec.com) 32-bit - * bios code. - * - * Code common to all LCA core logic chips. - */ - -#define __EXTERN_INLINE inline -#include -#include -#undef __EXTERN_INLINE - -#include -#include -#include -#include - -#include -#include -#include - -#include "proto.h" -#include "pci_impl.h" - - -/* - * BIOS32-style PCI interface: - */ - -/* - * Machine check reasons. Defined according to PALcode sources - * (osf.h and platform.h). - */ -#define MCHK_K_TPERR 0x0080 -#define MCHK_K_TCPERR 0x0082 -#define MCHK_K_HERR 0x0084 -#define MCHK_K_ECC_C 0x0086 -#define MCHK_K_ECC_NC 0x0088 -#define MCHK_K_UNKNOWN 0x008A -#define MCHK_K_CACKSOFT 0x008C -#define MCHK_K_BUGCHECK 0x008E -#define MCHK_K_OS_BUGCHECK 0x0090 -#define MCHK_K_DCPERR 0x0092 -#define MCHK_K_ICPERR 0x0094 - - -/* - * Platform-specific machine-check reasons: - */ -#define MCHK_K_SIO_SERR 0x204 /* all platforms so far */ -#define MCHK_K_SIO_IOCHK 0x206 /* all platforms so far */ -#define MCHK_K_DCSR 0x208 /* all but Noname */ - - -/* - * Given a bus, device, and function number, compute resulting - * configuration space address and setup the LCA_IOC_CONF register - * accordingly. It is therefore not safe to have concurrent - * invocations to configuration space access routines, but there - * really shouldn't be any need for this. - * - * Type 0: - * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | | | | | | | | | | | | | | | | | | |F|F|F|R|R|R|R|R|R|0|0| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * 31:11 Device select bit. - * 10:8 Function number - * 7:2 Register number - * - * Type 1: - * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 - * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| - * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ - * - * 31:24 reserved - * 23:16 bus number (8 bits = 128 possible buses) - * 15:11 Device number (5 bits) - * 10:8 function number - * 7:2 register number - * - * Notes: - * The function number selects which function of a multi-function device - * (e.g., SCSI and Ethernet). - * - * The register selects a DWORD (32 bit) register offset. Hence it - * doesn't get shifted by 2 bits as we want to "drop" the bottom two - * bits. - */ - -static int -mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, - unsigned long *pci_addr) -{ - unsigned long addr; - u8 bus = pbus->number; - - if (bus == 0) { - int device = device_fn >> 3; - int func = device_fn & 0x7; - - /* Type 0 configuration cycle. */ - - if (device > 12) { - return -1; - } - - *(vulp)LCA_IOC_CONF = 0; - addr = (1 << (11 + device)) | (func << 8) | where; - } else { - /* Type 1 configuration cycle. */ - *(vulp)LCA_IOC_CONF = 1; - addr = (bus << 16) | (device_fn << 8) | where; - } - *pci_addr = addr; - return 0; -} - -static unsigned int -conf_read(unsigned long addr) -{ - unsigned long flags, code, stat0; - unsigned int value; - - local_irq_save(flags); - - /* Reset status register to avoid losing errors. */ - stat0 = *(vulp)LCA_IOC_STAT0; - *(vulp)LCA_IOC_STAT0 = stat0; - mb(); - - /* Access configuration space. */ - value = *(vuip)addr; - draina(); - - stat0 = *(vulp)LCA_IOC_STAT0; - if (stat0 & LCA_IOC_STAT0_ERR) { - code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT) - & LCA_IOC_STAT0_CODE_MASK); - if (code != 1) { - printk("lca.c:conf_read: got stat0=%lx\n", stat0); - } - - /* Reset error status. */ - *(vulp)LCA_IOC_STAT0 = stat0; - mb(); - - /* Reset machine check. */ - wrmces(0x7); - - value = 0xffffffff; - } - local_irq_restore(flags); - return value; -} - -static void -conf_write(unsigned long addr, unsigned int value) -{ - unsigned long flags, code, stat0; - - local_irq_save(flags); /* avoid getting hit by machine check */ - - /* Reset status register to avoid losing errors. */ - stat0 = *(vulp)LCA_IOC_STAT0; - *(vulp)LCA_IOC_STAT0 = stat0; - mb(); - - /* Access configuration space. */ - *(vuip)addr = value; - draina(); - - stat0 = *(vulp)LCA_IOC_STAT0; - if (stat0 & LCA_IOC_STAT0_ERR) { - code = ((stat0 >> LCA_IOC_STAT0_CODE_SHIFT) - & LCA_IOC_STAT0_CODE_MASK); - if (code != 1) { - printk("lca.c:conf_write: got stat0=%lx\n", stat0); - } - - /* Reset error status. */ - *(vulp)LCA_IOC_STAT0 = stat0; - mb(); - - /* Reset machine check. */ - wrmces(0x7); - } - local_irq_restore(flags); -} - -static int -lca_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr, pci_addr; - long mask; - int shift; - - if (mk_conf_addr(bus, devfn, where, &pci_addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - shift = (where & 3) * 8; - mask = (size - 1) * 8; - addr = (pci_addr << 5) + mask + LCA_CONF; - *value = conf_read(addr) >> (shift); - return PCIBIOS_SUCCESSFUL; -} - -static int -lca_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, - u32 value) -{ - unsigned long addr, pci_addr; - long mask; - - if (mk_conf_addr(bus, devfn, where, &pci_addr)) - return PCIBIOS_DEVICE_NOT_FOUND; - - mask = (size - 1) * 8; - addr = (pci_addr << 5) + mask + LCA_CONF; - conf_write(addr, value << ((where & 3) * 8)); - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops lca_pci_ops = -{ - .read = lca_read_config, - .write = lca_write_config, -}; - -void -lca_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) -{ - wmb(); - *(vulp)LCA_IOC_TBIA = 0; - mb(); -} - -void __init -lca_init_arch(void) -{ - struct pci_controller *hose; - - /* - * Create our single hose. - */ - - pci_isa_hose = hose = alloc_pci_controller(); - hose->io_space = &ioport_resource; - hose->mem_space = &iomem_resource; - hose->index = 0; - - hose->sparse_mem_base = LCA_SPARSE_MEM - IDENT_ADDR; - hose->dense_mem_base = LCA_DENSE_MEM - IDENT_ADDR; - hose->sparse_io_base = LCA_IO - IDENT_ADDR; - hose->dense_io_base = 0; - - /* - * Set up the PCI to main memory translation windows. - * - * Mimic the SRM settings for the direct-map window. - * Window 0 is scatter-gather 8MB at 8MB (for isa). - * Window 1 is direct access 1GB at 1GB. - * - * Note that we do not try to save any of the DMA window CSRs - * before setting them, since we cannot read those CSRs on LCA. - */ - hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, - SMP_CACHE_BYTES); - hose->sg_pci = NULL; - __direct_map_base = 0x40000000; - __direct_map_size = 0x40000000; - - *(vulp)LCA_IOC_W_BASE0 = hose->sg_isa->dma_base | (3UL << 32); - *(vulp)LCA_IOC_W_MASK0 = (hose->sg_isa->size - 1) & 0xfff00000; - *(vulp)LCA_IOC_T_BASE0 = virt_to_phys(hose->sg_isa->ptes); - - *(vulp)LCA_IOC_W_BASE1 = __direct_map_base | (2UL << 32); - *(vulp)LCA_IOC_W_MASK1 = (__direct_map_size - 1) & 0xfff00000; - *(vulp)LCA_IOC_T_BASE1 = 0; - - *(vulp)LCA_IOC_TB_ENA = 0x80; - - lca_pci_tbi(hose, 0, -1); - - /* - * Disable PCI parity for now. The NCR53c810 chip has - * troubles meeting the PCI spec which results in - * data parity errors. - */ - *(vulp)LCA_IOC_PAR_DIS = 1UL<<5; - - /* - * Finally, set up for restoring the correct HAE if using SRM. - * Again, since we cannot read many of the CSRs on the LCA, - * one of which happens to be the HAE, we save the value that - * the SRM will expect... - */ - if (alpha_using_srm) - srm_hae = 0x80000000UL; -} - -/* - * Constants used during machine-check handling. I suppose these - * could be moved into lca.h but I don't see much reason why anybody - * else would want to use them. - */ - -#define ESR_EAV (1UL<< 0) /* error address valid */ -#define ESR_CEE (1UL<< 1) /* correctable error */ -#define ESR_UEE (1UL<< 2) /* uncorrectable error */ -#define ESR_WRE (1UL<< 3) /* write-error */ -#define ESR_SOR (1UL<< 4) /* error source */ -#define ESR_CTE (1UL<< 7) /* cache-tag error */ -#define ESR_MSE (1UL<< 9) /* multiple soft errors */ -#define ESR_MHE (1UL<<10) /* multiple hard errors */ -#define ESR_NXM (1UL<<12) /* non-existent memory */ - -#define IOC_ERR ( 1<<4) /* ioc logs an error */ -#define IOC_CMD_SHIFT 0 -#define IOC_CMD (0xf<> IOC_CODE_SHIFT; - unsigned cmd = (stat0 & IOC_CMD) >> IOC_CMD_SHIFT; - - printk(" %s initiated PCI %s cycle to address %x" - " failed due to %s.\n", - code > 3 ? "PCI" : "CPU", pci_cmd[cmd], stat1, err_name[code]); - - if (code == 5 || code == 6) { - printk(" (Error occurred at PCI memory address %x.)\n", - (stat0 & ~IOC_P_NBR)); - } - if (stat0 & IOC_LOST) { - printk(" Other PCI errors occurred simultaneously.\n"); - } -} - -void -lca_machine_check(unsigned long vector, unsigned long la_ptr) -{ - const char * reason; - union el_lca el; - - el.c = (struct el_common *) la_ptr; - - wrmces(rdmces()); /* reset machine check pending flag */ - - printk(KERN_CRIT "LCA machine check: vector=%#lx pc=%#lx code=%#x\n", - vector, get_irq_regs()->pc, (unsigned int) el.c->code); - - /* - * The first quadword after the common header always seems to - * be the machine check reason---don't know why this isn't - * part of the common header instead. In the case of a long - * logout frame, the upper 32 bits is the machine check - * revision level, which we ignore for now. - */ - switch ((unsigned int) el.c->code) { - case MCHK_K_TPERR: reason = "tag parity error"; break; - case MCHK_K_TCPERR: reason = "tag control parity error"; break; - case MCHK_K_HERR: reason = "access to non-existent memory"; break; - case MCHK_K_ECC_C: reason = "correctable ECC error"; break; - case MCHK_K_ECC_NC: reason = "non-correctable ECC error"; break; - case MCHK_K_CACKSOFT: reason = "MCHK_K_CACKSOFT"; break; - case MCHK_K_BUGCHECK: reason = "illegal exception in PAL mode"; break; - case MCHK_K_OS_BUGCHECK: reason = "callsys in kernel mode"; break; - case MCHK_K_DCPERR: reason = "d-cache parity error"; break; - case MCHK_K_ICPERR: reason = "i-cache parity error"; break; - case MCHK_K_SIO_SERR: reason = "SIO SERR occurred on PCI bus"; break; - case MCHK_K_SIO_IOCHK: reason = "SIO IOCHK occurred on ISA bus"; break; - case MCHK_K_DCSR: reason = "MCHK_K_DCSR"; break; - case MCHK_K_UNKNOWN: - default: reason = "unknown"; break; - } - - switch (el.c->size) { - case sizeof(struct el_lca_mcheck_short): - printk(KERN_CRIT - " Reason: %s (short frame%s, dc_stat=%#lx):\n", - reason, el.c->retry ? ", retryable" : "", - el.s->dc_stat); - if (el.s->esr & ESR_EAV) { - mem_error(el.s->esr, el.s->ear); - } - if (el.s->ioc_stat0 & IOC_ERR) { - ioc_error(el.s->ioc_stat0, el.s->ioc_stat1); - } - break; - - case sizeof(struct el_lca_mcheck_long): - printk(KERN_CRIT " Reason: %s (long frame%s):\n", - reason, el.c->retry ? ", retryable" : ""); - printk(KERN_CRIT - " reason: %#lx exc_addr: %#lx dc_stat: %#lx\n", - el.l->pt[0], el.l->exc_addr, el.l->dc_stat); - printk(KERN_CRIT " car: %#lx\n", el.l->car); - if (el.l->esr & ESR_EAV) { - mem_error(el.l->esr, el.l->ear); - } - if (el.l->ioc_stat0 & IOC_ERR) { - ioc_error(el.l->ioc_stat0, el.l->ioc_stat1); - } - break; - - default: - printk(KERN_CRIT " Unknown errorlog size %d\n", el.c->size); - } - - /* Dump the logout area to give all info. */ -#ifdef CONFIG_VERBOSE_MCHECK - if (alpha_verbose_mcheck > 1) { - unsigned long * ptr = (unsigned long *) la_ptr; - long i; - for (i = 0; i < el.c->size / sizeof(long); i += 2) { - printk(KERN_CRIT " +%8lx %016lx %016lx\n", - i*sizeof(long), ptr[i], ptr[i+1]); - } - } -#endif /* CONFIG_VERBOSE_MCHECK */ -} diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index 1dcf0d9038fd..29c6c477ac35 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c @@ -98,10 +98,6 @@ init_i8259a_irqs(void) #if defined(CONFIG_ALPHA_GENERIC) # define IACK_SC alpha_mv.iack_sc -#elif defined(CONFIG_ALPHA_APECS) -# define IACK_SC APECS_IACK_SC -#elif defined(CONFIG_ALPHA_LCA) -# define IACK_SC LCA_IACK_SC #elif defined(CONFIG_ALPHA_CIA) # define IACK_SC CIA_IACK_SC #elif defined(CONFIG_ALPHA_PYXIS) diff --git a/arch/alpha/kernel/pci_impl.h b/arch/alpha/kernel/pci_impl.h index 18043af45e2b..a16325ce21c4 100644 --- a/arch/alpha/kernel/pci_impl.h +++ b/arch/alpha/kernel/pci_impl.h @@ -143,9 +143,7 @@ struct pci_iommu_arena unsigned int align_entry; }; -#if defined(CONFIG_ALPHA_SRM) && \ - (defined(CONFIG_ALPHA_CIA) || defined(CONFIG_ALPHA_LCA) || \ - defined(CONFIG_ALPHA_AVANTI)) +#if defined(CONFIG_ALPHA_SRM) && defined(CONFIG_ALPHA_CIA) # define NEED_SRM_SAVE_RESTORE #else # undef NEED_SRM_SAVE_RESTORE diff --git a/arch/alpha/kernel/proto.h b/arch/alpha/kernel/proto.h index 5b1d0d71d479..a8bc3ead776b 100644 --- a/arch/alpha/kernel/proto.h +++ b/arch/alpha/kernel/proto.h @@ -17,13 +17,6 @@ struct pci_dev; struct pci_controller; struct pci_bus; -/* core_apecs.c */ -extern struct pci_ops apecs_pci_ops; -extern void apecs_init_arch(void); -extern void apecs_pci_clr_err(void); -extern void apecs_machine_check(unsigned long vector, unsigned long la_ptr); -extern void apecs_pci_tbi(struct pci_controller *, dma_addr_t, dma_addr_t); - /* core_cia.c */ extern struct pci_ops cia_pci_ops; extern void cia_init_pci(void); @@ -39,12 +32,6 @@ extern int irongate_pci_clr_err(void); extern void irongate_init_arch(void); #define irongate_pci_tbi ((void *)0) -/* core_lca.c */ -extern struct pci_ops lca_pci_ops; -extern void lca_init_arch(void); -extern void lca_machine_check(unsigned long vector, unsigned long la_ptr); -extern void lca_pci_tbi(struct pci_controller *, dma_addr_t, dma_addr_t); - /* core_marvel.c */ extern struct pci_ops marvel_pci_ops; extern void marvel_init_arch(void); diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 3b833bd97817..bebdffafaee8 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -171,27 +171,17 @@ EXPORT_SYMBOL(__direct_map_size); asm(".weak "#X) WEAK(alcor_mv); -WEAK(alphabook1_mv); -WEAK(avanti_mv); -WEAK(cabriolet_mv); WEAK(clipper_mv); WEAK(dp264_mv); WEAK(eb164_mv); -WEAK(eb64p_mv); -WEAK(eb66_mv); -WEAK(eb66p_mv); WEAK(eiger_mv); WEAK(lx164_mv); WEAK(marvel_ev7_mv); WEAK(miata_mv); -WEAK(mikasa_mv); WEAK(mikasa_primo_mv); WEAK(monet_mv); WEAK(nautilus_mv); -WEAK(noname_mv); -WEAK(noritake_mv); WEAK(noritake_primo_mv); -WEAK(p2k_mv); WEAK(pc164_mv); WEAK(privateer_mv); WEAK(rawhide_mv); @@ -204,7 +194,6 @@ WEAK(takara_mv); WEAK(titan_mv); WEAK(webbrick_mv); WEAK(wildfire_mv); -WEAK(xl_mv); WEAK(xlt_mv); #undef WEAK @@ -692,12 +681,6 @@ static int eb164_indices[] = {0,0,0,1,1,1,1,1,2,2,2,2,3,3,3,3,4}; static char alcor_names[][16] = {"Alcor", "Maverick", "Bret"}; static int alcor_indices[] = {0,0,0,1,1,1,0,0,0,0,0,0,2,2,2,2,2,2}; -static char eb64p_names[][16] = {"EB64+", "Cabriolet", "AlphaPCI64"}; -static int eb64p_indices[] = {0,0,1,2}; - -static char eb66_names[][8] = {"EB66", "EB66+"}; -static int eb66_indices[] = {0,0,1}; - static char marvel_names[][16] = { "Marvel/EV7" }; @@ -736,21 +719,21 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) NULL, /* Morgan */ NULL, /* Sable -- see below. */ NULL, /* Medulla */ - &noname_mv, + NULL, /* Noname */ NULL, /* Turbolaser */ - &avanti_mv, + NULL, /* Avanti */ NULL, /* Mustang */ NULL, /* Alcor, Bret, Maverick. HWRPB inaccurate? */ NULL, /* Tradewind */ NULL, /* Mikasa -- see below. */ NULL, /* EB64 */ - NULL, /* EB66 -- see variation. */ - NULL, /* EB64+ -- see variation. */ - &alphabook1_mv, + NULL, /* EB66 */ + NULL, /* EB64+ */ + NULL, /* Alphabook1 */ &rawhide_mv, NULL, /* K2 */ NULL, /* Lynx */ - &xl_mv, + NULL, /* XL */ NULL, /* EB164 -- see variation. */ NULL, /* Noritake -- see below. */ NULL, /* Cortex */ @@ -789,19 +772,6 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) &eb164_mv, &pc164_mv, &lx164_mv, &sx164_mv, &rx164_mv }; - static struct alpha_machine_vector *eb64p_vecs[] __initdata = - { - &eb64p_mv, - &cabriolet_mv, - &cabriolet_mv /* AlphaPCI64 */ - }; - - static struct alpha_machine_vector *eb66_vecs[] __initdata = - { - &eb66_mv, - &eb66p_mv - }; - static struct alpha_machine_vector *marvel_vecs[] __initdata = { &marvel_ev7_mv, @@ -869,14 +839,6 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) if (vec == &eb164_mv && cpu == EV56_CPU) vec = &pc164_mv; break; - case ST_DEC_EB64P: - if (member < ARRAY_SIZE(eb64p_indices)) - vec = eb64p_vecs[eb64p_indices[member]]; - break; - case ST_DEC_EB66: - if (member < ARRAY_SIZE(eb66_indices)) - vec = eb66_vecs[eb66_indices[member]]; - break; case ST_DEC_MARVEL: if (member < ARRAY_SIZE(marvel_indices)) vec = marvel_vecs[marvel_indices[member]]; @@ -891,16 +853,10 @@ get_sysvec(unsigned long type, unsigned long variation, unsigned long cpu) vec = tsunami_vecs[tsunami_indices[member]]; break; case ST_DEC_1000: - if (cpu == EV5_CPU || cpu == EV56_CPU) - vec = &mikasa_primo_mv; - else - vec = &mikasa_mv; + vec = &mikasa_primo_mv; break; case ST_DEC_NORITAKE: - if (cpu == EV5_CPU || cpu == EV56_CPU) - vec = &noritake_primo_mv; - else - vec = &noritake_mv; + vec = &noritake_primo_mv; break; case ST_DEC_2100_A500: vec = &sable_gamma_mv; @@ -916,26 +872,16 @@ get_sysvec_byname(const char *name) static struct alpha_machine_vector *all_vecs[] __initdata = { &alcor_mv, - &alphabook1_mv, - &avanti_mv, - &cabriolet_mv, &clipper_mv, &dp264_mv, &eb164_mv, - &eb64p_mv, - &eb66_mv, - &eb66p_mv, &eiger_mv, &lx164_mv, &miata_mv, - &mikasa_mv, &mikasa_primo_mv, &monet_mv, &nautilus_mv, - &noname_mv, - &noritake_mv, &noritake_primo_mv, - &p2k_mv, &pc164_mv, &privateer_mv, &rawhide_mv, @@ -947,7 +893,6 @@ get_sysvec_byname(const char *name) &takara_mv, &webbrick_mv, &wildfire_mv, - &xl_mv, &xlt_mv }; @@ -1009,14 +954,6 @@ get_sysnames(unsigned long type, unsigned long variation, unsigned long cpu, if (member < ARRAY_SIZE(alcor_indices)) *variation_name = alcor_names[alcor_indices[member]]; break; - case ST_DEC_EB64P: - if (member < ARRAY_SIZE(eb64p_indices)) - *variation_name = eb64p_names[eb64p_indices[member]]; - break; - case ST_DEC_EB66: - if (member < ARRAY_SIZE(eb66_indices)) - *variation_name = eb66_names[eb66_indices[member]]; - break; case ST_DEC_MARVEL: if (member < ARRAY_SIZE(marvel_indices)) *variation_name = marvel_names[marvel_indices[member]]; diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 47459b73cdb7..06a950072f82 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c @@ -23,9 +23,7 @@ #include #include #include -#include #include -#include #include #include "proto.h" @@ -232,13 +230,6 @@ cabriolet_enable_ide(void) } } -static inline void __init -cabriolet_init_pci(void) -{ - common_init_pci(); - cabriolet_enable_ide(); -} - static inline void __init cia_cab_init_pci(void) { @@ -317,32 +308,6 @@ alphapc164_init_pci(void) * The System Vector */ -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) -struct alpha_machine_vector cabriolet_mv __initmv = { - .vector_name = "Cabriolet", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_APECS_IO, - .machine_check = apecs_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 35, - .device_interrupt = cabriolet_device_interrupt, - - .init_arch = apecs_init_arch, - .init_irq = cabriolet_init_irq, - .init_rtc = common_init_rtc, - .init_pci = cabriolet_init_pci, - .pci_map_irq = cabriolet_map_irq, - .pci_swizzle = common_swizzle, -}; -#ifndef CONFIG_ALPHA_EB64P -ALIAS_MV(cabriolet) -#endif -#endif - #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164) struct alpha_machine_vector eb164_mv __initmv = { .vector_name = "EB164", @@ -368,30 +333,6 @@ struct alpha_machine_vector eb164_mv __initmv = { ALIAS_MV(eb164) #endif -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P) -struct alpha_machine_vector eb66p_mv __initmv = { - .vector_name = "EB66+", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_LCA_IO, - .machine_check = lca_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 35, - .device_interrupt = cabriolet_device_interrupt, - - .init_arch = lca_init_arch, - .init_irq = cabriolet_init_irq, - .init_rtc = common_init_rtc, - .init_pci = cabriolet_init_pci, - .pci_map_irq = eb66p_map_irq, - .pci_swizzle = common_swizzle, -}; -ALIAS_MV(eb66p) -#endif - #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164) struct alpha_machine_vector lx164_mv __initmv = { .vector_name = "LX164", diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c deleted file mode 100644 index 3c43fd347526..000000000000 --- a/arch/alpha/kernel/sys_eb64p.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/alpha/kernel/sys_eb64p.c - * - * Copyright (C) 1995 David A Rusling - * Copyright (C) 1996 Jay A Estabrook - * Copyright (C) 1998, 1999 Richard Henderson - * - * Code supporting the EB64+ and EB66. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "proto.h" -#include "irq_impl.h" -#include "pci_impl.h" -#include "machvec_impl.h" - - -/* Note mask bit is true for DISABLED irqs. */ -static unsigned int cached_irq_mask = -1; - -static inline void -eb64p_update_irq_hw(unsigned int irq, unsigned long mask) -{ - outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26)); -} - -static inline void -eb64p_enable_irq(struct irq_data *d) -{ - eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq)); -} - -static void -eb64p_disable_irq(struct irq_data *d) -{ - eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq); -} - -static struct irq_chip eb64p_irq_type = { - .name = "EB64P", - .irq_unmask = eb64p_enable_irq, - .irq_mask = eb64p_disable_irq, - .irq_mask_ack = eb64p_disable_irq, -}; - -static void -eb64p_device_interrupt(unsigned long vector) -{ - unsigned long pld; - unsigned int i; - - /* Read the interrupt summary registers */ - pld = inb(0x26) | (inb(0x27) << 8); - - /* - * Now, for every possible bit set, work through - * them and call the appropriate interrupt handler. - */ - while (pld) { - i = ffz(~pld); - pld &= pld - 1; /* clear least bit set */ - - if (i == 5) { - isa_device_interrupt(vector); - } else { - handle_irq(16 + i); - } - } -} - -static void __init -eb64p_init_irq(void) -{ - long i; - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) - /* - * CABRIO SRM may not set variation correctly, so here we test - * the high word of the interrupt summary register for the RAZ - * bits, and hope that a true EB64+ would read all ones... - */ - if (inw(0x806) != 0xffff) { - extern struct alpha_machine_vector cabriolet_mv; - - printk("Detected Cabriolet: correcting HWRPB.\n"); - - hwrpb->sys_variation |= 2L << 10; - hwrpb_update_checksum(hwrpb); - - alpha_mv = cabriolet_mv; - alpha_mv.init_irq(); - return; - } -#endif /* GENERIC */ - - outb(0xff, 0x26); - outb(0xff, 0x27); - - init_i8259a_irqs(); - - for (i = 16; i < 32; ++i) { - irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); - irq_set_status_flags(i, IRQ_LEVEL); - } - - common_init_isa_dma(); - if (request_irq(16 + 5, no_action, 0, "isa-cascade", NULL)) - pr_err("Failed to register isa-cascade interrupt\n"); -} - -/* - * PCI Fixup configuration. - * - * There are two 8 bit external summary registers as follows: - * - * Summary @ 0x26: - * Bit Meaning - * 0 Interrupt Line A from slot 0 - * 1 Interrupt Line A from slot 1 - * 2 Interrupt Line B from slot 0 - * 3 Interrupt Line B from slot 1 - * 4 Interrupt Line C from slot 0 - * 5 Interrupt line from the two ISA PICs - * 6 Tulip - * 7 NCR SCSI - * - * Summary @ 0x27 - * Bit Meaning - * 0 Interrupt Line C from slot 1 - * 1 Interrupt Line D from slot 0 - * 2 Interrupt Line D from slot 1 - * 3 RAZ - * 4 RAZ - * 5 RAZ - * 6 RAZ - * 7 RAZ - * - * The device to slot mapping looks like: - * - * Slot Device - * 5 NCR SCSI controller - * 6 PCI on board slot 0 - * 7 PCI on board slot 1 - * 8 Intel SIO PCI-ISA bridge chip - * 9 Tulip - DECchip 21040 Ethernet controller - * - * - * This two layered interrupt approach means that we allocate IRQ 16 and - * above for PCI interrupts. The IRQ relates to which bit the interrupt - * comes in on. This makes interrupt processing much easier. - */ - -static int -eb64p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static char irq_tab[5][5] = { - /*INT INTA INTB INTC INTD */ - {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */ - {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */ - {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */ - { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ - {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */ - }; - const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5; - return COMMON_TABLE_LOOKUP; -} - - -/* - * The System Vector - */ - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P) -struct alpha_machine_vector eb64p_mv __initmv = { - .vector_name = "EB64+", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_APECS_IO, - .machine_check = apecs_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 32, - .device_interrupt = eb64p_device_interrupt, - - .init_arch = apecs_init_arch, - .init_irq = eb64p_init_irq, - .init_rtc = common_init_rtc, - .init_pci = common_init_pci, - .kill_arch = NULL, - .pci_map_irq = eb64p_map_irq, - .pci_swizzle = common_swizzle, -}; -ALIAS_MV(eb64p) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66) -struct alpha_machine_vector eb66_mv __initmv = { - .vector_name = "EB66", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_LCA_IO, - .machine_check = lca_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 32, - .device_interrupt = eb64p_device_interrupt, - - .init_arch = lca_init_arch, - .init_irq = eb64p_init_irq, - .init_rtc = common_init_rtc, - .init_pci = common_init_pci, - .pci_map_irq = eb64p_map_irq, - .pci_swizzle = common_swizzle, -}; -ALIAS_MV(eb66) -#endif diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c index 7690dfd57cb6..557802398231 100644 --- a/arch/alpha/kernel/sys_mikasa.c +++ b/arch/alpha/kernel/sys_mikasa.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -164,64 +163,9 @@ mikasa_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) } -#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) -static void -mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr) -{ -#define MCHK_NO_DEVSEL 0x205U -#define MCHK_NO_TABT 0x204U - - struct el_common *mchk_header; - unsigned int code; - - mchk_header = (struct el_common *)la_ptr; - - /* Clear the error before any reporting. */ - mb(); - mb(); /* magic */ - draina(); - apecs_pci_clr_err(); - wrmces(0x7); - mb(); - - code = mchk_header->code; - process_mcheck_info(vector, la_ptr, "MIKASA APECS", - (mcheck_expected(0) - && (code == MCHK_NO_DEVSEL - || code == MCHK_NO_TABT))); -} -#endif - - /* * The System Vector */ - -#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) -struct alpha_machine_vector mikasa_mv __initmv = { - .vector_name = "Mikasa", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_APECS_IO, - .machine_check = mikasa_apecs_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 32, - .device_interrupt = mikasa_device_interrupt, - - .init_arch = apecs_init_arch, - .init_irq = mikasa_init_irq, - .init_rtc = common_init_rtc, - .init_pci = common_init_pci, - .pci_map_irq = mikasa_map_irq, - .pci_swizzle = common_swizzle, -}; -ALIAS_MV(mikasa) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO) struct alpha_machine_vector mikasa_primo_mv __initmv = { .vector_name = "Mikasa-Primo", DO_EV5_MMU, @@ -244,4 +188,3 @@ struct alpha_machine_vector mikasa_primo_mv __initmv = { .pci_swizzle = common_swizzle, }; ALIAS_MV(mikasa_primo) -#endif diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c index 47f3ce4f719a..eed3f16561c0 100644 --- a/arch/alpha/kernel/sys_noritake.c +++ b/arch/alpha/kernel/sys_noritake.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include @@ -253,64 +252,6 @@ noritake_swizzle(struct pci_dev *dev, u8 *pinp) return slot; } -#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) -static void -noritake_apecs_machine_check(unsigned long vector, unsigned long la_ptr) -{ -#define MCHK_NO_DEVSEL 0x205U -#define MCHK_NO_TABT 0x204U - - struct el_common *mchk_header; - unsigned int code; - - mchk_header = (struct el_common *)la_ptr; - - /* Clear the error before any reporting. */ - mb(); - mb(); /* magic */ - draina(); - apecs_pci_clr_err(); - wrmces(0x7); - mb(); - - code = mchk_header->code; - process_mcheck_info(vector, la_ptr, "NORITAKE APECS", - (mcheck_expected(0) - && (code == MCHK_NO_DEVSEL - || code == MCHK_NO_TABT))); -} -#endif - - -/* - * The System Vectors - */ - -#if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO) -struct alpha_machine_vector noritake_mv __initmv = { - .vector_name = "Noritake", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_APECS_IO, - .machine_check = noritake_apecs_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = EISA_DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 48, - .device_interrupt = noritake_device_interrupt, - - .init_arch = apecs_init_arch, - .init_irq = noritake_init_irq, - .init_rtc = common_init_rtc, - .init_pci = common_init_pci, - .pci_map_irq = noritake_map_irq, - .pci_swizzle = noritake_swizzle, -}; -ALIAS_MV(noritake) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO) struct alpha_machine_vector noritake_primo_mv __initmv = { .vector_name = "Noritake-Primo", DO_EV5_MMU, @@ -333,4 +274,3 @@ struct alpha_machine_vector noritake_primo_mv __initmv = { .pci_swizzle = noritake_swizzle, }; ALIAS_MV(noritake_primo) -#endif diff --git a/arch/alpha/kernel/sys_sio.c b/arch/alpha/kernel/sys_sio.c deleted file mode 100644 index c28a6ae1d989..000000000000 --- a/arch/alpha/kernel/sys_sio.c +++ /dev/null @@ -1,486 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/alpha/kernel/sys_sio.c - * - * Copyright (C) 1995 David A Rusling - * Copyright (C) 1996 Jay A Estabrook - * Copyright (C) 1998, 1999 Richard Henderson - * - * Code for all boards that route the PCI interrupts through the SIO - * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB), - * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "proto.h" -#include "irq_impl.h" -#include "pci_impl.h" -#include "machvec_impl.h" -#include "pc873xx.h" - -#if defined(ALPHA_RESTORE_SRM_SETUP) -/* Save LCA configuration data as the console had it set up. */ -struct -{ - unsigned int orig_route_tab; /* for SAVE/RESTORE */ -} saved_config __attribute((common)); -#endif - - -static void __init -sio_init_irq(void) -{ - if (alpha_using_srm) - alpha_mv.device_interrupt = srm_device_interrupt; - - init_i8259a_irqs(); - common_init_isa_dma(); -} - -static inline void __init -alphabook1_init_arch(void) -{ -#ifdef CONFIG_VGA_CONSOLE - /* The AlphaBook1 has LCD video fixed at 800x600, - 37 rows and 100 cols. */ - vgacon_screen_info.orig_y = 37; - vgacon_screen_info.orig_video_cols = 100; - vgacon_screen_info.orig_video_lines = 37; -#endif - - lca_init_arch(); -} - - -/* - * sio_route_tab selects irq routing in PCI/ISA bridge so that: - * PIRQ0 -> irq 15 - * PIRQ1 -> irq 9 - * PIRQ2 -> irq 10 - * PIRQ3 -> irq 11 - * - * This probably ought to be configurable via MILO. For - * example, sound boards seem to like using IRQ 9. - * - * This is NOT how we should do it. PIRQ0-X should have - * their own IRQs, the way intel uses the IO-APIC IRQs. - */ - -static void __init -sio_pci_route(void) -{ - unsigned int orig_route_tab; - - /* First, ALWAYS read and print the original setting. */ - pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60, - &orig_route_tab); - printk("%s: PIRQ original 0x%x new 0x%x\n", __func__, - orig_route_tab, alpha_mv.sys.sio.route_tab); - -#if defined(ALPHA_RESTORE_SRM_SETUP) - saved_config.orig_route_tab = orig_route_tab; -#endif - - /* Now override with desired setting. */ - pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60, - alpha_mv.sys.sio.route_tab); -} - -static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev) -{ - if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) && - (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA)) - return false; - - return true; -} - -static unsigned int __init -sio_collect_irq_levels(void) -{ - unsigned int level_bits = 0; - struct pci_dev *dev = NULL; - - /* Iterate through the devices, collecting IRQ levels. */ - for_each_pci_dev(dev) { - if (!sio_pci_dev_irq_needs_level(dev)) - continue; - - if (dev->irq) - level_bits |= (1 << dev->irq); - } - return level_bits; -} - -static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset) -{ - unsigned int old_level_bits; - - /* - * Now, make all PCI interrupts level sensitive. Notice: - * these registers must be accessed byte-wise. inw()/outw() - * don't work. - * - * Make sure to turn off any level bits set for IRQs 9,10,11,15, - * so that the only bits getting set are for devices actually found. - * Note that we do preserve the remainder of the bits, which we hope - * will be set correctly by ARC/SRM. - * - * Note: we at least preserve any level-set bits on AlphaBook1 - */ - old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8); - - if (reset) - old_level_bits &= 0x71ff; - - level_bits |= old_level_bits; - - outb((level_bits >> 0) & 0xff, 0x4d0); - outb((level_bits >> 8) & 0xff, 0x4d1); -} - -static inline void -sio_fixup_irq_levels(unsigned int level_bits) -{ - __sio_fixup_irq_levels(level_bits, true); -} - -static inline int -noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - /* - * The Noname board has 5 PCI slots with each of the 4 - * interrupt pins routed to different pins on the PCI/ISA - * bridge (PIRQ0-PIRQ3). The table below is based on - * information available at: - * - * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt - * - * I have no information on the Avanti interrupt routing, but - * the routing seems to be identical to the Noname except - * that the Avanti has an additional slot whose routing I'm - * unsure of. - * - * pirq_tab[0] is a fake entry to deal with old PCI boards - * that have the interrupt pin number hardwired to 0 (meaning - * that they use the default INTA line, if they are interrupt - * driven at all). - */ - static char irq_tab[][5] = { - /*INT A B C D */ - { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */ - {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */ - { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */ - {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */ - {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */ - { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */ - { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */ - { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */ - { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */ - }; - const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5; - int irq = COMMON_TABLE_LOOKUP, tmp; - tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq); - - irq = irq >= 0 ? tmp : -1; - - /* Fixup IRQ level if an actual IRQ mapping is detected */ - if (sio_pci_dev_irq_needs_level(dev) && irq >= 0) - __sio_fixup_irq_levels(1 << irq, false); - - return irq; -} - -static inline int -p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static char irq_tab[][5] = { - /*INT A B C D */ - { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */ - {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */ - { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */ - { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */ - {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */ - {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */ - { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */ - }; - const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5; - int irq = COMMON_TABLE_LOOKUP, tmp; - tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq); - return irq >= 0 ? tmp : -1; -} - -static inline void __init -noname_init_pci(void) -{ - common_init_pci(); - sio_pci_route(); - sio_fixup_irq_levels(sio_collect_irq_levels()); - - if (pc873xx_probe() == -1) { - printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n"); - } else { - printk(KERN_INFO "Found %s Super IO chip at 0x%x\n", - pc873xx_get_model(), pc873xx_get_base()); - - /* Enabling things in the Super IO chip doesn't actually - * configure and enable things, the legacy drivers still - * need to do the actual configuration and enabling. - * This only unblocks them. - */ - -#if !defined(CONFIG_ALPHA_AVANTI) - /* Don't bother on the Avanti family. - * None of them had on-board IDE. - */ - pc873xx_enable_ide(); -#endif - pc873xx_enable_epp19(); - } -} - -static inline void __init -alphabook1_init_pci(void) -{ - struct pci_dev *dev; - unsigned char orig, config; - - common_init_pci(); - sio_pci_route(); - - /* - * On the AlphaBook1, the PCMCIA chip (Cirrus 6729) - * is sensitive to PCI bus bursts, so we must DISABLE - * burst mode for the NCR 8xx SCSI... :-( - * - * Note that the NCR810 SCSI driver must preserve the - * setting of the bit in order for this to work. At the - * moment (2.0.29), ncr53c8xx.c does NOT do this, but - * 53c7,8xx.c DOES. - */ - - dev = NULL; - while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) { - if (dev->device == PCI_DEVICE_ID_NCR_53C810 - || dev->device == PCI_DEVICE_ID_NCR_53C815 - || dev->device == PCI_DEVICE_ID_NCR_53C820 - || dev->device == PCI_DEVICE_ID_NCR_53C825) { - unsigned long io_port; - unsigned char ctest4; - - io_port = dev->resource[0].start; - ctest4 = inb(io_port+0x21); - if (!(ctest4 & 0x80)) { - printk("AlphaBook1 NCR init: setting" - " burst disable\n"); - outb(ctest4 | 0x80, io_port+0x21); - } - } - } - - /* Do not set *ANY* level triggers for AlphaBook1. */ - sio_fixup_irq_levels(0); - - /* Make sure that register PR1 indicates 1Mb mem */ - outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */ - outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */ - outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */ - if ((config & 0xc0) != 0xc0) { - printk("AlphaBook1 VGA init: setting 1Mb memory\n"); - config |= 0xc0; - outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */ - } - outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */ -} - -static void -sio_kill_arch(int mode) -{ -#if defined(ALPHA_RESTORE_SRM_SETUP) - /* Since we cannot read the PCI DMA Window CSRs, we - * cannot restore them here. - * - * However, we CAN read the PIRQ route register, so restore it - * now... - */ - pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60, - saved_config.orig_route_tab); -#endif -} - - -/* - * The System Vectors - */ - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1) -struct alpha_machine_vector alphabook1_mv __initmv = { - .vector_name = "AlphaBook1", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_LCA_IO, - .machine_check = lca_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 16, - .device_interrupt = isa_device_interrupt, - - .init_arch = alphabook1_init_arch, - .init_irq = sio_init_irq, - .init_rtc = common_init_rtc, - .init_pci = alphabook1_init_pci, - .kill_arch = sio_kill_arch, - .pci_map_irq = noname_map_irq, - .pci_swizzle = common_swizzle, - - .sys = { .sio = { - /* NCR810 SCSI is 14, PCMCIA controller is 15. */ - .route_tab = 0x0e0f0a0a, - }} -}; -ALIAS_MV(alphabook1) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI_CH) -struct alpha_machine_vector avanti_mv __initmv = { - .vector_name = "Avanti", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_APECS_IO, - .machine_check = apecs_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 16, - .device_interrupt = isa_device_interrupt, - - .init_arch = apecs_init_arch, - .init_irq = sio_init_irq, - .init_rtc = common_init_rtc, - .init_pci = noname_init_pci, - .kill_arch = sio_kill_arch, - .pci_map_irq = noname_map_irq, - .pci_swizzle = common_swizzle, - - .sys = { .sio = { - .route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */ - }} -}; -ALIAS_MV(avanti) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME_CH) -struct alpha_machine_vector noname_mv __initmv = { - .vector_name = "Noname", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_LCA_IO, - .machine_check = lca_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 16, - .device_interrupt = srm_device_interrupt, - - .init_arch = lca_init_arch, - .init_irq = sio_init_irq, - .init_rtc = common_init_rtc, - .init_pci = noname_init_pci, - .kill_arch = sio_kill_arch, - .pci_map_irq = noname_map_irq, - .pci_swizzle = common_swizzle, - - .sys = { .sio = { - /* For UDB, the only available PCI slot must not map to IRQ 9, - since that's the builtin MSS sound chip. That PCI slot - will map to PIRQ1 (for INTA at least), so we give it IRQ 15 - instead. - - Unfortunately we have to do this for NONAME as well, since - they are co-indicated when the platform type "Noname" is - selected... :-( */ - - .route_tab = 0x0b0a0f0d, - }} -}; -ALIAS_MV(noname) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K) -struct alpha_machine_vector p2k_mv __initmv = { - .vector_name = "Platform2000", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_LCA_IO, - .machine_check = lca_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, - - .nr_irqs = 16, - .device_interrupt = srm_device_interrupt, - - .init_arch = lca_init_arch, - .init_irq = sio_init_irq, - .init_rtc = common_init_rtc, - .init_pci = noname_init_pci, - .kill_arch = sio_kill_arch, - .pci_map_irq = p2k_map_irq, - .pci_swizzle = common_swizzle, - - .sys = { .sio = { - .route_tab = 0x0b0a090f, - }} -}; -ALIAS_MV(p2k) -#endif - -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL) -struct alpha_machine_vector xl_mv __initmv = { - .vector_name = "XL", - DO_EV4_MMU, - DO_DEFAULT_RTC, - DO_APECS_IO, - .machine_check = apecs_machine_check, - .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = XL_DEFAULT_MEM_BASE, - - .nr_irqs = 16, - .device_interrupt = isa_device_interrupt, - - .init_arch = apecs_init_arch, - .init_irq = sio_init_irq, - .init_rtc = common_init_rtc, - .init_pci = noname_init_pci, - .kill_arch = sio_kill_arch, - .pci_map_irq = noname_map_irq, - .pci_swizzle = common_swizzle, - - .sys = { .sio = { - .route_tab = 0x0b0a090f, - }} -}; -ALIAS_MV(xl) -#endif From 4bf859076b16f1b7b096ac1f98039a362cee999e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 2 May 2024 23:09:25 +0200 Subject: [PATCH 910/969] alpha: cabriolet: remove EV5 CPU support The sys_cabriolet.c file includes support for multiple evaluation boards. pc164 and lx164 are for ev56 CPUs, while the eb164 is now the last supported machine that only supports ev5 but not ev56. Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/Kconfig | 15 ++------------- arch/alpha/include/asm/irq.h | 3 +-- arch/alpha/kernel/Makefile | 2 -- arch/alpha/kernel/sys_cabriolet.c | 28 +--------------------------- 4 files changed, 4 insertions(+), 44 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index ee209e895505..7987bb548652 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -91,7 +91,6 @@ choice Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366 DP264 DP264 / DS20 / ES40 / DS10 / DS10L - EB164 EB164 21164 evaluation board LX164 AlphaPC164-LX Miata Personal Workstation 433/500/600 a/au Marvel AlphaServer ES47 / ES80 / GS1280 @@ -134,16 +133,6 @@ config ALPHA_DP264 API Networks: 264DP, UP2000(+), CS20; Compaq: DS10(E,L), XP900, XP1000, DS20(E), ES40. -config ALPHA_EB164 - bool "EB164" - help - EB164 21164 evaluation board from DEC. Uses 21164 and ALCOR. Has - ISA and PCI expansion (3 ISA slots, 2 64-bit PCI slots (one is - shared with an ISA slot) and 2 32-bit PCI slots. Uses plus-in - Bcache SIMMs. I/O sub-system provides SuperI/O (2S, 1P, FD), KBD, - MOUSE (PS2 style), RTC/NVRAM. Boot ROM is Flash. PC-AT-sized - motherboard. Requires power supply with 3.3V output. - config ALPHA_EIGER bool "Eiger" help @@ -260,7 +249,7 @@ config ALPHA_EV5 config ALPHA_CIA bool - depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR + depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_ALCOR default y config ALPHA_EV56 @@ -350,7 +339,7 @@ config ALPHA_QEMU config ALPHA_SRM - bool "Use SRM as bootloader" if ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS + bool "Use SRM as bootloader" if ALPHA_PC164 || ALPHA_TAKARA || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS depends on TTY default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL help diff --git a/arch/alpha/include/asm/irq.h b/arch/alpha/include/asm/irq.h index e7d22357a5a6..d83b26b6660f 100644 --- a/arch/alpha/include/asm/irq.h +++ b/arch/alpha/include/asm/irq.h @@ -31,8 +31,7 @@ # define NR_IRQS (32768 + 16) /* marvel - 32 pids */ # endif -#elif defined(CONFIG_ALPHA_EB164) || \ - defined(CONFIG_ALPHA_PC164) || \ +#elif defined(CONFIG_ALPHA_PC164) || \ defined(CONFIG_ALPHA_LX164) # define NR_IRQS 35 diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile index bd5d62fa4a9a..b6c862dff1f6 100644 --- a/arch/alpha/kernel/Makefile +++ b/arch/alpha/kernel/Makefile @@ -60,8 +60,6 @@ obj-$(CONFIG_ALPHA_WILDFIRE) += core_wildfire.o # Board support obj-$(CONFIG_ALPHA_ALCOR) += sys_alcor.o irq_i8259.o irq_srm.o -obj-$(CONFIG_ALPHA_EB164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ - pc873xx.o obj-$(CONFIG_ALPHA_LX164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ smc37c93x.o obj-$(CONFIG_ALPHA_PC164) += sys_cabriolet.o irq_i8259.o irq_srm.o \ diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 06a950072f82..54e75d4fdbe3 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c @@ -6,8 +6,7 @@ * Copyright (C) 1996 Jay A Estabrook * Copyright (C) 1998, 1999, 2000 Richard Henderson * - * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164, - * PC164 and LX164. + * Code supporting the PC164 and LX164. */ #include @@ -308,31 +307,6 @@ alphapc164_init_pci(void) * The System Vector */ -#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164) -struct alpha_machine_vector eb164_mv __initmv = { - .vector_name = "EB164", - DO_EV5_MMU, - DO_DEFAULT_RTC, - DO_CIA_IO, - .machine_check = cia_machine_check, - .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, - .min_io_address = DEFAULT_IO_BASE, - .min_mem_address = CIA_DEFAULT_MEM_BASE, - - .nr_irqs = 35, - .device_interrupt = cabriolet_device_interrupt, - - .init_arch = cia_init_arch, - .init_irq = cabriolet_init_irq, - .init_rtc = common_init_rtc, - .init_pci = cia_cab_init_pci, - .kill_arch = cia_kill_arch, - .pci_map_irq = cabriolet_map_irq, - .pci_swizzle = common_swizzle, -}; -ALIAS_MV(eb164) -#endif - #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164) struct alpha_machine_vector lx164_mv __initmv = { .vector_name = "LX164", From 0ea3e1d6f31d8aea72d0d0b53919c585a12a593b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Mar 2024 10:13:11 +0100 Subject: [PATCH 911/969] arm64: dts: qcom: pm6150: correct USB VBUS regulator compatible The first part of the compatible of USB VBUS node misses ending quote, thus we have one long compatible consisting of two compatible strings leading to dtbs_check warnings: sc7180-idp.dtb: usb-vbus-regulator@1100: compatible:0: 'qcom,pm6150-vbus-reg,\n qcom,pm8150b-vbus-reg' does not match '^[a-zA-Z0-9][a-zA-Z0-9,+\\-._/]+$' sc7180-idp.dtb: /soc@0/spmi@c440000/pmic@0/usb-vbus-regulator@1100: failed to match any schema with compatible: ['qcom,pm6150-vbus-reg,\n qcom,pm8150b-vbus-reg'] Reported-by: Rob Herring Fixes: f81c2f01cad6 ("arm64: dts: qcom: pm6150: define USB-C related blocks") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240330091311.6224-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index b20a639cddf3..6de6ed562d97 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -64,8 +64,8 @@ }; pm6150_vbus: usb-vbus-regulator@1100 { - compatible = "qcom,pm6150-vbus-reg, - qcom,pm8150b-vbus-reg"; + compatible = "qcom,pm6150-vbus-reg", + "qcom,pm8150b-vbus-reg"; reg = <0x1100>; status = "disabled"; }; From 1812dc9c334f98227c65bc9c475f16fb6840a94b Mon Sep 17 00:00:00 2001 From: Alexander Gordeev Date: Sun, 5 May 2024 12:47:10 +0200 Subject: [PATCH 912/969] Revert "s390: Relocate vmlinux ELF data to virtual address space" This reverts commit 9ecaa2e94e602a3cbcbfe182535f6297f7630b98. In case CONFIG_MODULES kernel option is not defined the build fails with the following linker error: block/partitions/ibm.o: in function `ibm_partition': ibm.c:(.text+0x8bc): relocation truncated to fit: R_390_PLT32DBL against undefined symbol `dasd_biodasdinfo' Signed-off-by: Alexander Gordeev --- arch/s390/include/asm/page.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 7880b7b3173e..224ff9d433ea 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h @@ -276,8 +276,8 @@ static inline unsigned long virt_to_pfn(const void *kaddr) #define AMODE31_SIZE (3 * PAGE_SIZE) #define KERNEL_IMAGE_SIZE (512 * 1024 * 1024) -#define __START_KERNEL CONFIG_KERNEL_IMAGE_BASE -#define __NO_KASLR_START_KERNEL __START_KERNEL +#define __START_KERNEL 0x100000 +#define __NO_KASLR_START_KERNEL CONFIG_KERNEL_IMAGE_BASE #define __NO_KASLR_END_KERNEL (__NO_KASLR_START_KERNEL + KERNEL_IMAGE_SIZE) #endif /* _S390_PAGE_H */ From 04483d168d73b807aeef663660614a8919b32595 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 20:32:38 +0200 Subject: [PATCH 913/969] arm64: dts: marvell: eDPU: drop redundant address/size-cells The ethernet-switch node does not have children with unit addresses, so address/size-cells are not really correct, as reported by dtc W=1 warning: armada-3720-eDPU.dts:26.19-60.4: Warning (avoid_unnecessary_addr_size): /soc/internal-regs@d0000000/mdio@32004/switch@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property This probably also fixes dtbs_check warning, but I could not find it, so not sure about that. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts index d6d37a1f6f38..91c2f8b4edfa 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts @@ -25,8 +25,6 @@ /* Actual device is MV88E6361 */ switch: switch@0 { compatible = "marvell,mv88e6190"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; status = "disabled"; From 34f5746a8c1b308ea9a80dd80166c051220c2023 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 20:32:39 +0200 Subject: [PATCH 914/969] arm64: dts: marvell: turris-mox: drop unneeded flash address/size-cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: armada-3720-turris-mox.dts:218.10-255.4: Warning (avoid_unnecessary_addr_size): /soc/internal-regs@d0000000/spi@10600/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Andrew Lunn Reviewed-by: Marek Behún Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index f1a9f2234359..54453b0a91f9 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -216,8 +216,6 @@ assigned-clock-rates = <20000000>; flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; From 4289937de5ca3d82e4ee70f30e30f9f0cdcda6a2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Apr 2024 20:32:40 +0200 Subject: [PATCH 915/969] arm64: dts: marvell: espressobin-ultra: fix Ethernet Switch unit address The Espressobin Ultra DTS includes Espressobin DTSI which defines ethernet-switch@1 node. The Ultra DTS overrides "reg" to 3, but that leaves still old unit address which conflicts with the new phy@1 node (W=1 dtc warning): armada-3720-espressobin.dtsi:148.29-203.4: Warning (unique_unit_address_if_enabled): /soc/internal-regs@d0000000/mdio@32004/ethernet-switch@1: duplicate unit-address (also used in node /soc/internal-regs@d0000000/mdio@32004/ethernet-phy@1) Fix this by deleting ethernet-switch@1 node and merging original node with code from Ultra DTS into new ethernet-switch@3. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- .../marvell/armada-3720-espressobin-ultra.dts | 104 +++++++++++------- 1 file changed, 67 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 870bb380a40a..b3cc2b7b5d19 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -114,54 +114,84 @@ }; &mdio { + /* Switch is @3, not @1 */ + /delete-node/ ethernet-switch@1; extphy: ethernet-phy@1 { reg = <1>; reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; }; -}; -&switch0 { - reg = <3>; + switch0: ethernet-switch@3 { + compatible = "marvell,mv88e6085"; + reg = <3>; - reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + dsa,member = <0 0>; - ethernet-ports { - switch0port1: ethernet-port@1 { - reg = <1>; - label = "lan0"; - phy-handle = <&switch0phy0>; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + switch0port0: ethernet-port@0 { + reg = <0>; + label = "cpu"; + ethernet = <ð0>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch0port1: ethernet-port@1 { + reg = <1>; + label = "lan0"; + phy-handle = <&switch0phy0>; + }; + + switch0port2: ethernet-port@2 { + reg = <2>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; + + switch0port3: ethernet-port@3 { + reg = <3>; + label = "lan2"; + phy-handle = <&switch0phy2>; + }; + + switch0port4: ethernet-port@4 { + reg = <4>; + label = "lan3"; + phy-handle = <&switch0phy3>; + }; + + switch0port5: ethernet-port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&extphy>; + phy-mode = "sgmii"; + }; }; - switch0port2: ethernet-port@2 { - reg = <2>; - label = "lan1"; - phy-handle = <&switch0phy1>; - }; + mdio { + #address-cells = <1>; + #size-cells = <0>; - switch0port3: ethernet-port@3 { - reg = <3>; - label = "lan2"; - phy-handle = <&switch0phy2>; - }; - - switch0port4: ethernet-port@4 { - reg = <4>; - label = "lan3"; - phy-handle = <&switch0phy3>; - }; - - switch0port5: ethernet-port@5 { - reg = <5>; - label = "wan"; - phy-handle = <&extphy>; - phy-mode = "sgmii"; - }; - }; - - mdio { - switch0phy3: ethernet-phy@14 { - reg = <0x14>; + switch0phy0: ethernet-phy@11 { + reg = <0x11>; + }; + switch0phy1: ethernet-phy@12 { + reg = <0x12>; + }; + switch0phy2: ethernet-phy@13 { + reg = <0x13>; + }; + switch0phy3: ethernet-phy@14 { + reg = <0x14>; + }; }; }; }; From 79f46f6841619475c5d1c6bf5fdb8b71af981656 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Apr 2024 15:53:57 +0200 Subject: [PATCH 916/969] ARM: orion5x: Convert D2Net board to GPIO descriptors for LEDs This makes the LEDs on the D2Net Orion5x board use GPIO descriptors instead of hardcoded GPIOs from the global numberspace. Signed-off-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/board-d2net.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c index 0297e302d7bc..09bf366d05ff 100644 --- a/arch/arm/mach-orion5x/board-d2net.c +++ b/arch/arm/mach-orion5x/board-d2net.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -55,12 +56,9 @@ static struct gpio_led d2net_leds[] = { { .name = "d2net:blue:sata", .default_trigger = "default-on", - .gpio = D2NET_GPIO_BLUE_LED_OFF, - .active_low = 1, }, { .name = "d2net:red:fail", - .gpio = D2NET_GPIO_RED_LED, }, }; @@ -77,6 +75,17 @@ static struct platform_device d2net_gpio_leds = { }, }; +static struct gpiod_lookup_table d2net_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", D2NET_GPIO_BLUE_LED_OFF, NULL, + 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", D2NET_GPIO_RED_LED, NULL, + 1, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static void __init d2net_gpio_leds_init(void) { int err; @@ -91,6 +100,7 @@ static void __init d2net_gpio_leds_init(void) if (err) pr_err("d2net: failed to configure blue LED blink GPIO\n"); + gpiod_add_lookup_table(&d2net_leds_gpio_table); platform_device_register(&d2net_gpio_leds); } From ef48d0866a469324cfab0f92e007fa6747675671 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Apr 2024 15:53:58 +0200 Subject: [PATCH 917/969] ARM: orion5x: Convert DNS323 board to GPIO descriptors for LEDs This makes the LEDs on the D-Link DNS323 Orion5x board use GPIO descriptors instead of hardcoded GPIOs from the global numberspace. Signed-off-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/dns323-setup.c | 63 +++++++++++++++++++++------- 1 file changed, 48 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index d69259b6b60d..062109efa0ec 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -14,6 +14,7 @@ * */ #include +#include #include #include #include @@ -254,37 +255,64 @@ error_fail: static struct gpio_led dns323ab_leds[] = { { .name = "power:blue", - .gpio = DNS323_GPIO_LED_POWER2, .default_trigger = "default-on", }, { .name = "right:amber", - .gpio = DNS323_GPIO_LED_RIGHT_AMBER, - .active_low = 1, }, { .name = "left:amber", - .gpio = DNS323_GPIO_LED_LEFT_AMBER, - .active_low = 1, }, }; +static struct gpiod_lookup_table dns323a1_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_POWER2, NULL, + 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_RIGHT_AMBER, NULL, + 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_LEFT_AMBER, NULL, + 2, GPIO_ACTIVE_LOW), + { }, + }, +}; + +/* B1 is the same but power LED is active high */ +static struct gpiod_lookup_table dns323b1_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_POWER2, NULL, + 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_RIGHT_AMBER, NULL, + 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", DNS323_GPIO_LED_LEFT_AMBER, NULL, + 2, GPIO_ACTIVE_LOW), + { }, + }, +}; static struct gpio_led dns323c_leds[] = { { .name = "power:blue", - .gpio = DNS323C_GPIO_LED_POWER, .default_trigger = "timer", - .active_low = 1, }, { .name = "right:amber", - .gpio = DNS323C_GPIO_LED_RIGHT_AMBER, - .active_low = 1, }, { .name = "left:amber", - .gpio = DNS323C_GPIO_LED_LEFT_AMBER, - .active_low = 1, }, }; +static struct gpiod_lookup_table dns323c_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_POWER, NULL, + 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_RIGHT_AMBER, NULL, + 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", DNS323C_GPIO_LED_LEFT_AMBER, NULL, + 2, GPIO_ACTIVE_LOW), + { }, + }, +}; static struct gpio_led_platform_data dns323ab_led_data = { .num_leds = ARRAY_SIZE(dns323ab_leds), @@ -621,16 +649,21 @@ static void __init dns323_init(void) /* The 5181 power LED is active low and requires * DNS323_GPIO_LED_POWER1 to also be low. */ - dns323ab_leds[0].active_low = 1; - gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); - gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); - fallthrough; + gpiod_add_lookup_table(&dns323a1_leds_gpio_table); + gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable"); + gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); + i2c_register_board_info(0, dns323ab_i2c_devices, + ARRAY_SIZE(dns323ab_i2c_devices)); + + break; case DNS323_REV_B1: + gpiod_add_lookup_table(&dns323b1_leds_gpio_table); i2c_register_board_info(0, dns323ab_i2c_devices, ARRAY_SIZE(dns323ab_i2c_devices)); break; case DNS323_REV_C1: /* Hookup LEDs & Buttons */ + gpiod_add_lookup_table(&dns323c_leds_gpio_table); dns323_gpio_leds.dev.platform_data = &dns323c_led_data; dns323_button_device.dev.platform_data = &dns323c_button_data; From 948d1a99ac111beba0e27dba376c3e0fae98a779 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Apr 2024 15:53:59 +0200 Subject: [PATCH 918/969] ARM: orion5x: Convert MV2120 board to GPIO descriptors for LEDs This makes the LEDs on the MV2120 Orion5x board use GPIO descriptors instead of hardcoded GPIOs from the global numberspace. Signed-off-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/mv2120-setup.c | 29 ++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c index 2bf8ec75e908..b7327a612835 100644 --- a/arch/arm/mach-orion5x/mv2120-setup.c +++ b/arch/arm/mach-orion5x/mv2120-setup.c @@ -8,6 +8,7 @@ * License, or (at your option) any later version. */ #include +#include #include #include #include @@ -139,34 +140,45 @@ static struct i2c_board_info __initdata mv2120_i2c_rtc = { static struct gpio_led mv2120_led_pins[] = { { .name = "mv2120:blue:health", - .gpio = 0, }, { .name = "mv2120:red:health", - .gpio = 1, }, { .name = "mv2120:led:bright", - .gpio = 4, .default_trigger = "default-on", }, { .name = "mv2120:led:dimmed", - .gpio = 5, }, { .name = "mv2120:red:sata0", - .gpio = 8, - .active_low = 1, }, { .name = "mv2120:red:sata1", - .gpio = 9, - .active_low = 1, }, }; +static struct gpiod_lookup_table mv2120_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", 0, NULL, + 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", 1, NULL, + 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", 4, NULL, + 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", 5, NULL, + 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", 8, NULL, + 4, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", 9, NULL, + 5, GPIO_ACTIVE_LOW), + { }, + }, +}; + static struct gpio_led_platform_data mv2120_led_data = { .leds = mv2120_led_pins, .num_leds = ARRAY_SIZE(mv2120_led_pins), @@ -219,6 +231,7 @@ static void __init mv2120_init(void) gpio_free(MV2120_GPIO_RTC_IRQ); } i2c_register_board_info(0, &mv2120_i2c_rtc, 1); + gpiod_add_lookup_table(&mv2120_leds_gpio_table); platform_device_register(&mv2120_leds); /* register mv2120 specific power-off method */ From 73acd2ed594e6065cc3808dc7d921c10c7bb0909 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Apr 2024 15:54:00 +0200 Subject: [PATCH 919/969] ARM: orion5x: Convert Net2big board to GPIO descriptors for LEDs This makes the LEDs on the Net2big Orion5x board use GPIO descriptors instead of hardcoded GPIOs from the global numberspace. Signed-off-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/net2big-setup.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c index 695cc683cd83..6ad9740b426b 100644 --- a/arch/arm/mach-orion5x/net2big-setup.c +++ b/arch/arm/mach-orion5x/net2big-setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -214,19 +215,30 @@ err_free_1: static struct gpio_led net2big_leds[] = { { .name = "net2big:red:power", - .gpio = NET2BIG_GPIO_PWR_RED_LED, }, { .name = "net2big:blue:power", - .gpio = NET2BIG_GPIO_PWR_BLUE_LED, }, { .name = "net2big:red:sata0", - .gpio = NET2BIG_GPIO_SATA0_RED_LED, }, { .name = "net2big:red:sata1", - .gpio = NET2BIG_GPIO_SATA1_RED_LED, + }, +}; + +static struct gpiod_lookup_table net2big_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_PWR_RED_LED, NULL, + 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_PWR_BLUE_LED, NULL, + 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_SATA0_RED_LED, NULL, + 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("orion_gpio0", NET2BIG_GPIO_SATA1_RED_LED, NULL, + 3, GPIO_ACTIVE_HIGH), + { }, }, }; @@ -282,6 +294,7 @@ static void __init net2big_gpio_leds_init(void) if (err) pr_err("net2big: failed to setup SATA1 blue LED GPIO\n"); + gpiod_add_lookup_table(&net2big_leds_gpio_table); platform_device_register(&net2big_gpio_leds); } From 3153eb8e047339e5217338d2f3b25e58c8683d7f Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 23 Apr 2024 15:54:01 +0200 Subject: [PATCH 920/969] ARM: orion5x: Convert TS409 board to GPIO descriptors for LEDs This makes the LEDs on the TS409 Orion5x board use GPIO descriptors instead of hardcoded GPIOs from the global numberspace. Signed-off-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/mach-orion5x/ts409-setup.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c index 6f60dc1dfa22..8131982c10d9 100644 --- a/arch/arm/mach-orion5x/ts409-setup.c +++ b/arch/arm/mach-orion5x/ts409-setup.c @@ -8,6 +8,7 @@ * Copyright (C) 2008 Martin Michlmayr */ #include +#include #include #include #include @@ -168,20 +169,27 @@ static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = { static struct gpio_led ts409_led_pins[] = { { .name = "ts409:red:sata1", - .gpio = 4, - .active_low = 1, }, { .name = "ts409:red:sata2", - .gpio = 5, - .active_low = 1, }, { .name = "ts409:red:sata3", - .gpio = 6, - .active_low = 1, }, { .name = "ts409:red:sata4", - .gpio = 7, - .active_low = 1, + }, +}; + +static struct gpiod_lookup_table ts409_leds_gpio_table = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX("orion_gpio0", 4, NULL, + 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", 5, NULL, + 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", 6, NULL, + 2, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("orion_gpio0", 7, NULL, + 3, GPIO_ACTIVE_LOW), + { }, }, }; @@ -300,6 +308,7 @@ static void __init qnap_ts409_init(void) if (qnap_ts409_i2c_rtc.irq == 0) pr_warn("qnap_ts409_init: failed to get RTC IRQ\n"); i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1); + gpiod_add_lookup_table(&ts409_leds_gpio_table); platform_device_register(&ts409_leds); /* register tsx09 specific power-off method */ From a4184174be36369c3af8d937e165f28a43ef1e02 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 13 Dec 2023 18:00:54 +0100 Subject: [PATCH 921/969] alpha: drop pre-EV56 support All EV4 machines are already gone, and the remaining EV5 based machines all support the slightly more modern EV56 generation as well. Debian only supports EV56 and later. Drop both of these and build kernels optimized for EV56 and higher when the "generic" options is selected, tuning for an out-of-order EV6 pipeline, same as Debian userspace. Since this was the only supported architecture without 8-bit and 16-bit stores, common kernel code no longer has to worry about aligning struct members, and existing workarounds from the block and tty layers can be removed. The alpha memory management code no longer needs an abstraction for the differences between EV4 and EV5+. Link: https://lists.debian.org/debian-alpha/2023/05/msg00009.html Acked-by: Paul E. McKenney Acked-by: Matt Turner Signed-off-by: Arnd Bergmann --- arch/alpha/Kconfig | 21 +------ arch/alpha/Makefile | 8 +-- arch/alpha/include/asm/elf.h | 4 +- arch/alpha/include/asm/machvec.h | 9 --- arch/alpha/include/asm/mmu_context.h | 45 +-------------- arch/alpha/include/asm/special_insns.h | 5 +- arch/alpha/include/asm/tlbflush.h | 37 +----------- arch/alpha/include/asm/uaccess.h | 80 -------------------------- arch/alpha/include/uapi/asm/compiler.h | 18 ------ arch/alpha/kernel/machvec_impl.h | 25 +------- arch/alpha/kernel/traps.c | 64 --------------------- include/linux/blk_types.h | 6 -- include/linux/tty.h | 14 ++--- 13 files changed, 19 insertions(+), 317 deletions(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 7987bb548652..50ff06d5b799 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -240,29 +240,14 @@ config ISA_DMA_API bool default y -config ALPHA_EV4 - bool - -config ALPHA_EV5 - bool - default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR - config ALPHA_CIA bool depends on ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_ALCOR default y config ALPHA_EV56 - bool "EV56 CPU (speed >= 366MHz)?" if ALPHA_ALCOR - default y if ALPHA_RX164 || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_PC164 || ALPHA_TAKARA - -config ALPHA_EV56 - prompt "EV56 CPU (speed >= 333MHz)?" - depends on ALPHA_NORITAKE || ALPHA_MIKASA - -config ALPHA_EV56 - prompt "EV56 CPU (speed >= 400MHz)?" - depends on ALPHA_RAWHIDE + bool + default y if ALPHA_ALCOR || ALPHA_RX164 || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_NORITAKE || ALPHA_MIKASA || ALPHA_RAWHIDE || ALPHA_SABLE config ALPHA_T2 bool @@ -403,7 +388,7 @@ config ARCH_SPARSEMEM_ENABLE config ALPHA_WTINT bool "Use WTINT" if ALPHA_SRM || ALPHA_GENERIC default y if ALPHA_QEMU - default n if ALPHA_EV5 || ALPHA_EV56 + default n if ALPHA_EV56 default n if !ALPHA_SRM && !ALPHA_GENERIC default y if SMP help diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile index 45158024085e..35445ff2e489 100644 --- a/arch/alpha/Makefile +++ b/arch/alpha/Makefile @@ -15,18 +15,14 @@ CHECKFLAGS += -D__alpha__ cflags-y := -pipe -mno-fp-regs -ffixed-8 cflags-y += $(call cc-option, -fno-jump-tables) -cpuflags-$(CONFIG_ALPHA_EV4) := -mcpu=ev4 -cpuflags-$(CONFIG_ALPHA_EV5) := -mcpu=ev5 cpuflags-$(CONFIG_ALPHA_EV56) := -mcpu=ev56 cpuflags-$(CONFIG_ALPHA_POLARIS) := -mcpu=pca56 cpuflags-$(CONFIG_ALPHA_SX164) := -mcpu=pca56 cpuflags-$(CONFIG_ALPHA_EV6) := -mcpu=ev6 cpuflags-$(CONFIG_ALPHA_EV67) := -mcpu=ev67 # If GENERIC, make sure to turn off any instruction set extensions that -# the host compiler might have on by default. Given that EV4 and EV5 -# have the same instruction set, prefer EV5 because an EV5 schedule is -# more likely to keep an EV4 processor busy than vice-versa. -cpuflags-$(CONFIG_ALPHA_GENERIC) := -mcpu=ev5 +# the host compiler might have on by default. +cpuflags-$(CONFIG_ALPHA_GENERIC) := -mcpu=ev56 -mtune=ev6 cflags-y += $(cpuflags-y) diff --git a/arch/alpha/include/asm/elf.h b/arch/alpha/include/asm/elf.h index e6da23f1da83..4d7c46f50382 100644 --- a/arch/alpha/include/asm/elf.h +++ b/arch/alpha/include/asm/elf.h @@ -133,9 +133,7 @@ extern int dump_elf_task(elf_greg_t *dest, struct task_struct *task); #define ELF_PLATFORM \ ({ \ enum implver_enum i_ = implver(); \ - ( i_ == IMPLVER_EV4 ? "ev4" \ - : i_ == IMPLVER_EV5 \ - ? (amask(AMASK_BWX) ? "ev5" : "ev56") \ + ( i_ == IMPLVER_EV5 ? "ev56" \ : amask (AMASK_CIX) ? "ev6" : "ev67"); \ }) diff --git a/arch/alpha/include/asm/machvec.h b/arch/alpha/include/asm/machvec.h index 8623f995d34c..490fc880bb3f 100644 --- a/arch/alpha/include/asm/machvec.h +++ b/arch/alpha/include/asm/machvec.h @@ -72,15 +72,6 @@ struct alpha_machine_vector int (*mv_is_ioaddr)(unsigned long); int (*mv_is_mmio)(const volatile void __iomem *); - void (*mv_switch_mm)(struct mm_struct *, struct mm_struct *, - struct task_struct *); - void (*mv_activate_mm)(struct mm_struct *, struct mm_struct *); - - void (*mv_flush_tlb_current)(struct mm_struct *); - void (*mv_flush_tlb_current_page)(struct mm_struct * mm, - struct vm_area_struct *vma, - unsigned long addr); - void (*update_irq_hw)(unsigned long, unsigned long, int); void (*ack_irq)(unsigned long); void (*device_interrupt)(unsigned long vector); diff --git a/arch/alpha/include/asm/mmu_context.h b/arch/alpha/include/asm/mmu_context.h index 29a3e3a1f02b..eee8fe836a59 100644 --- a/arch/alpha/include/asm/mmu_context.h +++ b/arch/alpha/include/asm/mmu_context.h @@ -71,9 +71,7 @@ __reload_thread(struct pcb_struct *pcb) #ifdef CONFIG_ALPHA_GENERIC # define MAX_ASN (alpha_mv.max_asn) #else -# ifdef CONFIG_ALPHA_EV4 -# define MAX_ASN EV4_MAX_ASN -# elif defined(CONFIG_ALPHA_EV5) +# if defined(CONFIG_ALPHA_EV56) # define MAX_ASN EV5_MAX_ASN # else # define MAX_ASN EV6_MAX_ASN @@ -162,26 +160,6 @@ ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, task_thread_info(next)->pcb.asn = mmc & HARDWARE_ASN_MASK; } -__EXTERN_INLINE void -ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, - struct task_struct *next) -{ - /* As described, ASN's are broken for TLB usage. But we can - optimize for switching between threads -- if the mm is - unchanged from current we needn't flush. */ - /* ??? May not be needed because EV4 PALcode recognizes that - ASN's are broken and does a tbiap itself on swpctx, under - the "Must set ASN or flush" rule. At least this is true - for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com). - I'm going to leave this here anyway, just to Be Sure. -- r~ */ - if (prev_mm != next_mm) - tbiap(); - - /* Do continue to allocate ASNs, because we can still use them - to avoid flushing the icache. */ - ev5_switch_mm(prev_mm, next_mm, next); -} - extern void __load_new_mm_context(struct mm_struct *); asmlinkage void do_page_fault(unsigned long address, unsigned long mmcsr, long cause, struct pt_regs *regs); @@ -209,25 +187,8 @@ ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) __load_new_mm_context(next_mm); } -__EXTERN_INLINE void -ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm) -{ - __load_new_mm_context(next_mm); - tbiap(); -} - -#ifdef CONFIG_ALPHA_GENERIC -# define switch_mm(a,b,c) alpha_mv.mv_switch_mm((a),(b),(c)) -# define activate_mm(x,y) alpha_mv.mv_activate_mm((x),(y)) -#else -# ifdef CONFIG_ALPHA_EV4 -# define switch_mm(a,b,c) ev4_switch_mm((a),(b),(c)) -# define activate_mm(x,y) ev4_activate_mm((x),(y)) -# else -# define switch_mm(a,b,c) ev5_switch_mm((a),(b),(c)) -# define activate_mm(x,y) ev5_activate_mm((x),(y)) -# endif -#endif +#define switch_mm(a,b,c) ev5_switch_mm((a),(b),(c)) +#define activate_mm(x,y) ev5_activate_mm((x),(y)) #define init_new_context init_new_context static inline int diff --git a/arch/alpha/include/asm/special_insns.h b/arch/alpha/include/asm/special_insns.h index ca2c5c30b22e..798d0bdb11f9 100644 --- a/arch/alpha/include/asm/special_insns.h +++ b/arch/alpha/include/asm/special_insns.h @@ -15,10 +15,7 @@ enum implver_enum { (enum implver_enum) __implver; }) #else /* Try to eliminate some dead code. */ -#ifdef CONFIG_ALPHA_EV4 -#define implver() IMPLVER_EV4 -#endif -#ifdef CONFIG_ALPHA_EV5 +#ifdef CONFIG_ALPHA_EV56 #define implver() IMPLVER_EV5 #endif #if defined(CONFIG_ALPHA_EV6) diff --git a/arch/alpha/include/asm/tlbflush.h b/arch/alpha/include/asm/tlbflush.h index 94dc37cf873a..ba4b359d6c39 100644 --- a/arch/alpha/include/asm/tlbflush.h +++ b/arch/alpha/include/asm/tlbflush.h @@ -14,16 +14,6 @@ extern void __load_new_mm_context(struct mm_struct *); -/* Use a few helper functions to hide the ugly broken ASN - numbers on early Alphas (ev4 and ev45). */ - -__EXTERN_INLINE void -ev4_flush_tlb_current(struct mm_struct *mm) -{ - __load_new_mm_context(mm); - tbiap(); -} - __EXTERN_INLINE void ev5_flush_tlb_current(struct mm_struct *mm) { @@ -34,19 +24,6 @@ ev5_flush_tlb_current(struct mm_struct *mm) careful about the icache here, there is no way to invalidate a specific icache page. */ -__EXTERN_INLINE void -ev4_flush_tlb_current_page(struct mm_struct * mm, - struct vm_area_struct *vma, - unsigned long addr) -{ - int tbi_flag = 2; - if (vma->vm_flags & VM_EXEC) { - __load_new_mm_context(mm); - tbi_flag = 3; - } - tbi(tbi_flag, addr); -} - __EXTERN_INLINE void ev5_flush_tlb_current_page(struct mm_struct * mm, struct vm_area_struct *vma, @@ -59,18 +36,8 @@ ev5_flush_tlb_current_page(struct mm_struct * mm, } -#ifdef CONFIG_ALPHA_GENERIC -# define flush_tlb_current alpha_mv.mv_flush_tlb_current -# define flush_tlb_current_page alpha_mv.mv_flush_tlb_current_page -#else -# ifdef CONFIG_ALPHA_EV4 -# define flush_tlb_current ev4_flush_tlb_current -# define flush_tlb_current_page ev4_flush_tlb_current_page -# else -# define flush_tlb_current ev5_flush_tlb_current -# define flush_tlb_current_page ev5_flush_tlb_current_page -# endif -#endif +#define flush_tlb_current ev5_flush_tlb_current +#define flush_tlb_current_page ev5_flush_tlb_current_page #ifdef __MMU_EXTERN_INLINE #undef __EXTERN_INLINE diff --git a/arch/alpha/include/asm/uaccess.h b/arch/alpha/include/asm/uaccess.h index c32c2584c0b7..ef295cbb797c 100644 --- a/arch/alpha/include/asm/uaccess.h +++ b/arch/alpha/include/asm/uaccess.h @@ -96,9 +96,6 @@ struct __large_struct { unsigned long buf[100]; }; : "=r"(__gu_val), "=r"(__gu_err) \ : "m"(__m(addr)), "1"(__gu_err)) -#ifdef __alpha_bwx__ -/* Those lucky bastards with ev56 and later CPUs can do byte/word moves. */ - #define __get_user_16(addr) \ __asm__("1: ldwu %0,%2\n" \ "2:\n" \ @@ -112,33 +109,6 @@ struct __large_struct { unsigned long buf[100]; }; EXC(1b,2b,%0,%1) \ : "=r"(__gu_val), "=r"(__gu_err) \ : "m"(__m(addr)), "1"(__gu_err)) -#else -/* Unfortunately, we can't get an unaligned access trap for the sub-word - load, so we have to do a general unaligned operation. */ - -#define __get_user_16(addr) \ -{ \ - long __gu_tmp; \ - __asm__("1: ldq_u %0,0(%3)\n" \ - "2: ldq_u %1,1(%3)\n" \ - " extwl %0,%3,%0\n" \ - " extwh %1,%3,%1\n" \ - " or %0,%1,%0\n" \ - "3:\n" \ - EXC(1b,3b,%0,%2) \ - EXC(2b,3b,%0,%2) \ - : "=&r"(__gu_val), "=&r"(__gu_tmp), "=r"(__gu_err) \ - : "r"(addr), "2"(__gu_err)); \ -} - -#define __get_user_8(addr) \ - __asm__("1: ldq_u %0,0(%2)\n" \ - " extbl %0,%2,%0\n" \ - "2:\n" \ - EXC(1b,2b,%0,%1) \ - : "=&r"(__gu_val), "=r"(__gu_err) \ - : "r"(addr), "1"(__gu_err)) -#endif extern void __put_user_unknown(void); @@ -192,9 +162,6 @@ __asm__ __volatile__("1: stl %r2,%1\n" \ : "=r"(__pu_err) \ : "m"(__m(addr)), "rJ"(x), "0"(__pu_err)) -#ifdef __alpha_bwx__ -/* Those lucky bastards with ev56 and later CPUs can do byte/word moves. */ - #define __put_user_16(x, addr) \ __asm__ __volatile__("1: stw %r2,%1\n" \ "2:\n" \ @@ -208,53 +175,6 @@ __asm__ __volatile__("1: stb %r2,%1\n" \ EXC(1b,2b,$31,%0) \ : "=r"(__pu_err) \ : "m"(__m(addr)), "rJ"(x), "0"(__pu_err)) -#else -/* Unfortunately, we can't get an unaligned access trap for the sub-word - write, so we have to do a general unaligned operation. */ - -#define __put_user_16(x, addr) \ -{ \ - long __pu_tmp1, __pu_tmp2, __pu_tmp3, __pu_tmp4; \ - __asm__ __volatile__( \ - "1: ldq_u %2,1(%5)\n" \ - "2: ldq_u %1,0(%5)\n" \ - " inswh %6,%5,%4\n" \ - " inswl %6,%5,%3\n" \ - " mskwh %2,%5,%2\n" \ - " mskwl %1,%5,%1\n" \ - " or %2,%4,%2\n" \ - " or %1,%3,%1\n" \ - "3: stq_u %2,1(%5)\n" \ - "4: stq_u %1,0(%5)\n" \ - "5:\n" \ - EXC(1b,5b,$31,%0) \ - EXC(2b,5b,$31,%0) \ - EXC(3b,5b,$31,%0) \ - EXC(4b,5b,$31,%0) \ - : "=r"(__pu_err), "=&r"(__pu_tmp1), \ - "=&r"(__pu_tmp2), "=&r"(__pu_tmp3), \ - "=&r"(__pu_tmp4) \ - : "r"(addr), "r"((unsigned long)(x)), "0"(__pu_err)); \ -} - -#define __put_user_8(x, addr) \ -{ \ - long __pu_tmp1, __pu_tmp2; \ - __asm__ __volatile__( \ - "1: ldq_u %1,0(%4)\n" \ - " insbl %3,%4,%2\n" \ - " mskbl %1,%4,%1\n" \ - " or %1,%2,%1\n" \ - "2: stq_u %1,0(%4)\n" \ - "3:\n" \ - EXC(1b,3b,$31,%0) \ - EXC(2b,3b,$31,%0) \ - : "=r"(__pu_err), \ - "=&r"(__pu_tmp1), "=&r"(__pu_tmp2) \ - : "r"((unsigned long)(x)), "r"(addr), "0"(__pu_err)); \ -} -#endif - /* * Complex access routines diff --git a/arch/alpha/include/uapi/asm/compiler.h b/arch/alpha/include/uapi/asm/compiler.h index 0e00c0e13374..8c03740966b4 100644 --- a/arch/alpha/include/uapi/asm/compiler.h +++ b/arch/alpha/include/uapi/asm/compiler.h @@ -95,24 +95,6 @@ #define __kernel_ldwu(mem) (mem) #define __kernel_stb(val,mem) ((mem) = (val)) #define __kernel_stw(val,mem) ((mem) = (val)) -#else -#define __kernel_ldbu(mem) \ - ({ unsigned char __kir; \ - __asm__(".arch ev56; \ - ldbu %0,%1" : "=r"(__kir) : "m"(mem)); \ - __kir; }) -#define __kernel_ldwu(mem) \ - ({ unsigned short __kir; \ - __asm__(".arch ev56; \ - ldwu %0,%1" : "=r"(__kir) : "m"(mem)); \ - __kir; }) -#define __kernel_stb(val,mem) \ - __asm__(".arch ev56; \ - stb %1,%0" : "=m"(mem) : "r"(val)) -#define __kernel_stw(val,mem) \ - __asm__(".arch ev56; \ - stw %1,%0" : "=m"(mem) : "r"(val)) #endif - #endif /* _UAPI__ALPHA_COMPILER_H */ diff --git a/arch/alpha/kernel/machvec_impl.h b/arch/alpha/kernel/machvec_impl.h index c2ebcb39e589..129ae36b8e6d 100644 --- a/arch/alpha/kernel/machvec_impl.h +++ b/arch/alpha/kernel/machvec_impl.h @@ -44,33 +44,14 @@ #define DO_DEFAULT_RTC .rtc_port = 0x70 -#define DO_EV4_MMU \ - .max_asn = EV4_MAX_ASN, \ - .mv_switch_mm = ev4_switch_mm, \ - .mv_activate_mm = ev4_activate_mm, \ - .mv_flush_tlb_current = ev4_flush_tlb_current, \ - .mv_flush_tlb_current_page = ev4_flush_tlb_current_page - #define DO_EV5_MMU \ - .max_asn = EV5_MAX_ASN, \ - .mv_switch_mm = ev5_switch_mm, \ - .mv_activate_mm = ev5_activate_mm, \ - .mv_flush_tlb_current = ev5_flush_tlb_current, \ - .mv_flush_tlb_current_page = ev5_flush_tlb_current_page + .max_asn = EV5_MAX_ASN \ #define DO_EV6_MMU \ - .max_asn = EV6_MAX_ASN, \ - .mv_switch_mm = ev5_switch_mm, \ - .mv_activate_mm = ev5_activate_mm, \ - .mv_flush_tlb_current = ev5_flush_tlb_current, \ - .mv_flush_tlb_current_page = ev5_flush_tlb_current_page + .max_asn = EV6_MAX_ASN \ #define DO_EV7_MMU \ - .max_asn = EV6_MAX_ASN, \ - .mv_switch_mm = ev5_switch_mm, \ - .mv_activate_mm = ev5_activate_mm, \ - .mv_flush_tlb_current = ev5_flush_tlb_current, \ - .mv_flush_tlb_current_page = ev5_flush_tlb_current_page + .max_asn = EV6_MAX_ASN \ #define IO_LITE(UP,low) \ .hae_register = (unsigned long *) CAT(UP,_HAE_ADDRESS), \ diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 7fc72aeb7398..6afae65e9a8b 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -30,39 +30,6 @@ #include "proto.h" -/* Work-around for some SRMs which mishandle opDEC faults. */ - -static int opDEC_fix; - -static void -opDEC_check(void) -{ - __asm__ __volatile__ ( - /* Load the address of... */ - " br $16, 1f\n" - /* A stub instruction fault handler. Just add 4 to the - pc and continue. */ - " ldq $16, 8($sp)\n" - " addq $16, 4, $16\n" - " stq $16, 8($sp)\n" - " call_pal %[rti]\n" - /* Install the instruction fault handler. */ - "1: lda $17, 3\n" - " call_pal %[wrent]\n" - /* With that in place, the fault from the round-to-minf fp - insn will arrive either at the "lda 4" insn (bad) or one - past that (good). This places the correct fixup in %0. */ - " lda %[fix], 0\n" - " cvttq/svm $f31,$f31\n" - " lda %[fix], 4" - : [fix] "=r" (opDEC_fix) - : [rti] "n" (PAL_rti), [wrent] "n" (PAL_wrent) - : "$0", "$1", "$16", "$17", "$22", "$23", "$24", "$25"); - - if (opDEC_fix) - printk("opDEC fixup enabled.\n"); -} - void dik_show_regs(struct pt_regs *regs, unsigned long *r9_15) { @@ -353,32 +320,6 @@ do_entIF(unsigned long type, struct pt_regs *regs) return; case 4: /* opDEC */ - if (implver() == IMPLVER_EV4) { - long si_code; - - /* The some versions of SRM do not handle - the opDEC properly - they return the PC of the - opDEC fault, not the instruction after as the - Alpha architecture requires. Here we fix it up. - We do this by intentionally causing an opDEC - fault during the boot sequence and testing if - we get the correct PC. If not, we set a flag - to correct it every time through. */ - regs->pc += opDEC_fix; - - /* EV4 does not implement anything except normal - rounding. Everything else will come here as - an illegal instruction. Emulate them. */ - si_code = alpha_fp_emul(regs->pc - 4); - if (si_code == 0) - return; - if (si_code > 0) { - send_sig_fault_trapno(SIGFPE, si_code, - (void __user *) regs->pc, - 0, current); - return; - } - } break; case 5: /* illoc */ @@ -979,11 +920,6 @@ trap_init(void) register unsigned long gptr __asm__("$29"); wrkgp(gptr); - /* Hack for Multia (UDB) and JENSEN: some of their SRMs have - a bug in the handling of the opDEC fault. Fix it up if so. */ - if (implver() == IMPLVER_EV4) - opDEC_check(); - wrent(entArith, 1); wrent(entMM, 2); wrent(entIF, 3); diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index cb1526ec44b5..c3e098b21c16 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -88,15 +88,9 @@ struct block_device { /* * Block error status values. See block/blk-core:blk_errors for the details. - * Alpha cannot write a byte atomically, so we need to use 32-bit value. */ -#if defined(CONFIG_ALPHA) && !defined(__alpha_bwx__) -typedef u32 __bitwise blk_status_t; -typedef u32 blk_short_t; -#else typedef u8 __bitwise blk_status_t; typedef u16 blk_short_t; -#endif #define BLK_STS_OK 0 #define BLK_STS_NOTSUPP ((__force blk_status_t)1) #define BLK_STS_TIMEOUT ((__force blk_status_t)2) diff --git a/include/linux/tty.h b/include/linux/tty.h index 2b2e6f0a54d6..2372f9357240 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -145,15 +145,12 @@ struct tty_operations; * @count: count of open processes, reaching zero cancels all the work for * this tty and drops a @kref too (but does not free this tty) * @winsize: size of the terminal "window" (cf. @winsize_mutex) - * @flow: flow settings grouped together, see also @flow.unused + * @flow: flow settings grouped together * @flow.lock: lock for @flow members * @flow.stopped: tty stopped/started by stop_tty()/start_tty() * @flow.tco_stopped: tty stopped/started by %TCOOFF/%TCOON ioctls (it has * precedence over @flow.stopped) - * @flow.unused: alignment for Alpha, so that no members other than @flow.* are - * modified by the same 64b word store. The @flow's __aligned is - * there for the very same reason. - * @ctrl: control settings grouped together, see also @ctrl.unused + * @ctrl: control settings grouped together * @ctrl.lock: lock for @ctrl members * @ctrl.pgrp: process group of this tty (setpgrp(2)) * @ctrl.session: session of this tty (setsid(2)). Writes are protected by both @@ -161,7 +158,6 @@ struct tty_operations; * them. * @ctrl.pktstatus: packet mode status (bitwise OR of %TIOCPKT_ constants) * @ctrl.packet: packet mode enabled - * @ctrl.unused: alignment for Alpha, see @flow.unused for explanation * @hw_stopped: not controlled by the tty layer, under @driver's control for CTS * handling * @receive_room: bytes permitted to feed to @ldisc without any being lost @@ -216,8 +212,7 @@ struct tty_struct { spinlock_t lock; bool stopped; bool tco_stopped; - unsigned long unused[0]; - } __aligned(sizeof(unsigned long)) flow; + } flow; struct { struct pid *pgrp; @@ -225,8 +220,7 @@ struct tty_struct { spinlock_t lock; unsigned char pktstatus; bool packet; - unsigned long unused[0]; - } __aligned(sizeof(unsigned long)) ctrl; + } ctrl; bool hw_stopped; bool closing; From d2c470c491719130e9af2e80c1bd7223ac61ee93 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 1 Feb 2024 10:51:28 -0800 Subject: [PATCH 922/969] Documentation/litmus-tests: Add locking tests to README This commit documents the litmus tests in the "locking" directory. [ paulmck: Apply formatting feedback from Andrea Parri. ] Signed-off-by: Paul E. McKenney Cc: Alan Stern Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Nicholas Piggin Cc: David Howells Cc: Jade Alglave Cc: Luc Maranget Cc: "Paul E. McKenney" Cc: Akira Yokosawa Cc: Daniel Lustig Cc: Joel Fernandes Cc: Mark Rutland Cc: Jonathan Corbet Cc: Cc: Acked-by: Andrea Parri --- Documentation/litmus-tests/README | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/litmus-tests/README b/Documentation/litmus-tests/README index 658d37860d39..26ca56df0212 100644 --- a/Documentation/litmus-tests/README +++ b/Documentation/litmus-tests/README @@ -22,6 +22,35 @@ Atomic-RMW-ops-are-atomic-WRT-atomic_set.litmus NOTE: Require herd7 7.56 or later which supports "(void)expr". +locking (/locking directory) +---------------------------- + +DCL-broken.litmus + Demonstrates that double-checked locking needs more than just + the obvious lock acquisitions and releases. + +DCL-fixed.litmus + Demonstrates corrected double-checked locking that uses + smp_store_release() and smp_load_acquire() in addition to the + obvious lock acquisitions and releases. + +RM-broken.litmus + Demonstrates problems with "roach motel" locking, where code is + freely moved into lock-based critical sections. This example also + shows how to use the "filter" clause to discard executions that + would be excluded by other code not modeled in the litmus test. + Note also that this "roach motel" optimization is emulated by + physically moving P1()'s two reads from x under the lock. + + What is a roach motel? This is from an old advertisement for + a cockroach trap, much later featured in one of the "Men in + Black" movies. "The roaches check in. They don't check out." + +RM-fixed.litmus + The counterpart to RM-broken.litmus, showing P0()'s two loads from + x safely outside of the critical section. + + RCU (/rcu directory) -------------------- From 293f5bc2717b2178978c0d9ce9584da552279c3b Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Thu, 1 Feb 2024 11:17:54 -0800 Subject: [PATCH 923/969] Documentation/litmus-tests: Demonstrate unordered failing cmpxchg This commit adds four litmus tests showing that a failing cmpxchg() operation is unordered unless followed by an smp_mb__after_atomic() operation. Suggested-by: Frederic Weisbecker Signed-off-by: Paul E. McKenney Cc: Alan Stern Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Nicholas Piggin Cc: David Howells Cc: Jade Alglave Cc: Luc Maranget Cc: "Paul E. McKenney" Cc: Akira Yokosawa Cc: Daniel Lustig Cc: Joel Fernandes Cc: Mark Rutland Cc: Jonathan Corbet Cc: Cc: Acked-by: Andrea Parri --- Documentation/litmus-tests/README | 16 +++++++++ .../atomic/cmpxchg-fail-ordered-1.litmus | 34 +++++++++++++++++++ .../atomic/cmpxchg-fail-ordered-2.litmus | 30 ++++++++++++++++ .../atomic/cmpxchg-fail-unordered-1.litmus | 33 ++++++++++++++++++ .../atomic/cmpxchg-fail-unordered-2.litmus | 30 ++++++++++++++++ 5 files changed, 143 insertions(+) create mode 100644 Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus create mode 100644 Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus create mode 100644 Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus create mode 100644 Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus diff --git a/Documentation/litmus-tests/README b/Documentation/litmus-tests/README index 26ca56df0212..6c666f3422ea 100644 --- a/Documentation/litmus-tests/README +++ b/Documentation/litmus-tests/README @@ -21,6 +21,22 @@ Atomic-RMW-ops-are-atomic-WRT-atomic_set.litmus Test that atomic_set() cannot break the atomicity of atomic RMWs. NOTE: Require herd7 7.56 or later which supports "(void)expr". +cmpxchg-fail-ordered-1.litmus + Demonstrate that a failing cmpxchg() operation acts as a full barrier + when followed by smp_mb__after_atomic(). + +cmpxchg-fail-ordered-2.litmus + Demonstrate that a failing cmpxchg() operation acts as an acquire + operation when followed by smp_mb__after_atomic(). + +cmpxchg-fail-unordered-1.litmus + Demonstrate that a failing cmpxchg() operation does not act as a + full barrier. + +cmpxchg-fail-unordered-2.litmus + Demonstrate that a failing cmpxchg() operation does not act as an + acquire operation. + locking (/locking directory) ---------------------------- diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus new file mode 100644 index 000000000000..3df1d140b189 --- /dev/null +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus @@ -0,0 +1,34 @@ +C cmpxchg-fail-ordered-1 + +(* + * Result: Never + * + * Demonstrate that a failing cmpxchg() operation will act as a full + * barrier when followed by smp_mb__after_atomic(). + *) + +{} + +P0(int *x, int *y, int *z) +{ + int r0; + int r1; + + WRITE_ONCE(*x, 1); + r1 = cmpxchg(z, 1, 0); + smp_mb__after_atomic(); + r0 = READ_ONCE(*y); +} + +P1(int *x, int *y, int *z) +{ + int r0; + + WRITE_ONCE(*y, 1); + r1 = cmpxchg(z, 1, 0); + smp_mb__after_atomic(); + r0 = READ_ONCE(*x); +} + +locations[0:r1;1:r1] +exists (0:r0=0 /\ 1:r0=0) diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus new file mode 100644 index 000000000000..54146044a16f --- /dev/null +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus @@ -0,0 +1,30 @@ +C cmpxchg-fail-ordered-2 + +(* + * Result: Never + * + * Demonstrate use of smp_mb__after_atomic() to make a failing cmpxchg + * operation have acquire ordering. + *) + +{} + +P0(int *x, int *y) +{ + int r0; + int r1; + + WRITE_ONCE(*x, 1); + r1 = cmpxchg(y, 0, 1); +} + +P1(int *x, int *y) +{ + int r0; + + r1 = cmpxchg(y, 0, 1); + smp_mb__after_atomic(); + r2 = READ_ONCE(*x); +} + +exists (0:r1=0 /\ 1:r1=1 /\ 1:r2=0) diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus new file mode 100644 index 000000000000..a727ce23b1a6 --- /dev/null +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus @@ -0,0 +1,33 @@ +C cmpxchg-fail-unordered-1 + +(* + * Result: Sometimes + * + * Demonstrate that a failing cmpxchg() operation does not act as a + * full barrier. (In contrast, a successful cmpxchg() does act as a + * full barrier.) + *) + +{} + +P0(int *x, int *y, int *z) +{ + int r0; + int r1; + + WRITE_ONCE(*x, 1); + r1 = cmpxchg(z, 1, 0); + r0 = READ_ONCE(*y); +} + +P1(int *x, int *y, int *z) +{ + int r0; + + WRITE_ONCE(*y, 1); + r1 = cmpxchg(z, 1, 0); + r0 = READ_ONCE(*x); +} + +locations[0:r1;1:r1] +exists (0:r0=0 /\ 1:r0=0) diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus new file mode 100644 index 000000000000..a245bac55b57 --- /dev/null +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus @@ -0,0 +1,30 @@ +C cmpxchg-fail-unordered-2 + +(* + * Result: Sometimes + * + * Demonstrate that a failing cmpxchg() operation does not act as either + * an acquire release operation. (In contrast, a successful cmpxchg() + * does act as both an acquire and a release operation.) + *) + +{} + +P0(int *x, int *y) +{ + int r0; + int r1; + + WRITE_ONCE(*x, 1); + r1 = cmpxchg(y, 0, 1); +} + +P1(int *x, int *y) +{ + int r0; + + r1 = cmpxchg(y, 0, 1); + r2 = READ_ONCE(*x); +} + +exists (0:r1=0 /\ 1:r1=1 /\ 1:r2=0) From d372e20433cbc0b0e3e59c89ccb6618501fcf6af Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Tue, 30 Jan 2024 06:08:32 -0800 Subject: [PATCH 924/969] Documentation/atomic_t: Emphasize that failed atomic operations give no ordering The ORDERING section of Documentation/atomic_t.txt can easily be read as saying that conditional atomic RMW operations that fail are ordered when those operations have the _acquire() or _release() suffixes. This is not the case, therefore update this section to make it clear that failed conditional atomic RMW operations provide no ordering. Reported-by: Anna-Maria Behnsen Signed-off-by: Paul E. McKenney Cc: Alan Stern Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Nicholas Piggin Cc: David Howells Cc: Jade Alglave Cc: Luc Maranget Cc: "Paul E. McKenney" Cc: Akira Yokosawa Cc: Daniel Lustig Cc: Joel Fernandes Cc: Mark Rutland Cc: Jonathan Corbet Cc: Cc: Acked-by: Andrea Parri Acked-by: Mark Rutland --- Documentation/atomic_t.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/atomic_t.txt b/Documentation/atomic_t.txt index d7adc6d543db..bee3b1bca9a7 100644 --- a/Documentation/atomic_t.txt +++ b/Documentation/atomic_t.txt @@ -171,14 +171,14 @@ The rule of thumb: - RMW operations that are conditional are unordered on FAILURE, otherwise the above rules apply. -Except of course when an operation has an explicit ordering like: +Except of course when a successful operation has an explicit ordering like: {}_relaxed: unordered {}_acquire: the R of the RMW (or atomic_read) is an ACQUIRE {}_release: the W of the RMW (or atomic_set) is a RELEASE Where 'unordered' is against other memory locations. Address dependencies are -not defeated. +not defeated. Conditional operations are still unordered on FAILURE. Fully ordered primitives are ordered against everything prior and everything subsequent. Therefore a fully ordered primitive is like having an smp_mb() From 2ba5b4130e3d5d05c95981e1d2e660d57e613fda Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 8 Apr 2024 13:41:22 -0700 Subject: [PATCH 925/969] Documentation/litmus-tests: Make cmpxchg() tests safe for klitmus The four litmus tests in Documentation/litmus-tests/atomic do not declare all of their local variables. Although this is just fine for LKMM analysis by herd7, it causes build failures when run in-kernel by klitmus. This commit therefore adjusts these tests to declare all local variables. Reported-by: Andrea Parri Signed-off-by: Paul E. McKenney Acked-by: Andrea Parri --- .../litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus | 1 + .../litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus | 4 ++-- .../litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus | 1 + .../litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus | 4 ++-- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus index 3df1d140b189..c0f93dc07105 100644 --- a/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-1.litmus @@ -23,6 +23,7 @@ P0(int *x, int *y, int *z) P1(int *x, int *y, int *z) { int r0; + int r1; WRITE_ONCE(*y, 1); r1 = cmpxchg(z, 1, 0); diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus index 54146044a16f..5c06054f4694 100644 --- a/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-ordered-2.litmus @@ -11,7 +11,6 @@ C cmpxchg-fail-ordered-2 P0(int *x, int *y) { - int r0; int r1; WRITE_ONCE(*x, 1); @@ -20,7 +19,8 @@ P0(int *x, int *y) P1(int *x, int *y) { - int r0; + int r1; + int r2; r1 = cmpxchg(y, 0, 1); smp_mb__after_atomic(); diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus index a727ce23b1a6..39ea1f56a28d 100644 --- a/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-1.litmus @@ -23,6 +23,7 @@ P0(int *x, int *y, int *z) P1(int *x, int *y, int *z) { int r0; + int r1; WRITE_ONCE(*y, 1); r1 = cmpxchg(z, 1, 0); diff --git a/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus index a245bac55b57..61aab24a4a64 100644 --- a/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus +++ b/Documentation/litmus-tests/atomic/cmpxchg-fail-unordered-2.litmus @@ -12,7 +12,6 @@ C cmpxchg-fail-unordered-2 P0(int *x, int *y) { - int r0; int r1; WRITE_ONCE(*x, 1); @@ -21,7 +20,8 @@ P0(int *x, int *y) P1(int *x, int *y) { - int r0; + int r1; + int r2; r1 = cmpxchg(y, 0, 1); r2 = READ_ONCE(*x); From dd29dfe78bb051c5e2540f1120450a276dfb4057 Mon Sep 17 00:00:00 2001 From: Saurav Shah Date: Thu, 2 May 2024 05:06:59 +0530 Subject: [PATCH 926/969] Documentation: tracing: Fix spelling mistakes Fix spelling mistakes in the documentation. Signed-off-by: Saurav Shah Link: https://lore.kernel.org/r/20240501233659.25441-1-sauravshah.31@gmail.com Signed-off-by: Jonathan Corbet --- Documentation/trace/fprobetrace.rst | 4 ++-- Documentation/trace/ftrace.rst | 2 +- Documentation/trace/kprobetrace.rst | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/trace/fprobetrace.rst b/Documentation/trace/fprobetrace.rst index 0f187e3796e4..b4c2ca3d02c1 100644 --- a/Documentation/trace/fprobetrace.rst +++ b/Documentation/trace/fprobetrace.rst @@ -74,7 +74,7 @@ Function arguments at exit -------------------------- Function arguments can be accessed at exit probe using $arg fetcharg. This is useful to record the function parameter and return value at once, and -trace the difference of structure fields (for debuging a function whether it +trace the difference of structure fields (for debugging a function whether it correctly updates the given data structure or not) See the :ref:`sample` below for how it works. @@ -248,4 +248,4 @@ mode. You can trace that changes with return probe. cat-143 [007] ...1. 1945.720616: vfs_open__entry: (vfs_open+0x4/0x40) mode=0x1 inode=0x0 cat-143 [007] ...1. 1945.728263: vfs_open__exit: (do_open+0x274/0x3d0 <- vfs_open) mode=0xa800d inode=0xffff888004ada8d8 -You can see the `file::f_mode` and `file::f_inode` are upated in `vfs_open()`. +You can see the `file::f_mode` and `file::f_inode` are updated in `vfs_open()`. diff --git a/Documentation/trace/ftrace.rst b/Documentation/trace/ftrace.rst index 7e7b8ec17934..5aba74872ba7 100644 --- a/Documentation/trace/ftrace.rst +++ b/Documentation/trace/ftrace.rst @@ -1968,7 +1968,7 @@ wakeup One common case that people are interested in tracing is the time it takes for a task that is woken to actually wake up. Now for non Real-Time tasks, this can be arbitrary. But tracing -it none the less can be interesting. +it nonetheless can be interesting. Without function tracing:: diff --git a/Documentation/trace/kprobetrace.rst b/Documentation/trace/kprobetrace.rst index a49662ccd53c..69cb7776ae99 100644 --- a/Documentation/trace/kprobetrace.rst +++ b/Documentation/trace/kprobetrace.rst @@ -74,7 +74,7 @@ Function arguments at kretprobe ------------------------------- Function arguments can be accessed at kretprobe using $arg fetcharg. This is useful to record the function parameter and return value at once, and -trace the difference of structure fields (for debuging a function whether it +trace the difference of structure fields (for debugging a function whether it correctly updates the given data structure or not). See the :ref:`sample` in fprobe event for how it works. From fd37a0f2a3ab22e45dae8546aedafb60bb368ab6 Mon Sep 17 00:00:00 2001 From: Dennis Lam Date: Thu, 2 May 2024 17:25:22 -0400 Subject: [PATCH 927/969] docs:core-api: fixed typos and grammar in printk-index page Signed-off-by: Dennis Lam Signed-off-by: Jonathan Corbet Link: https://lore.kernel.org/r/20240502212522.4263-1-dennis.lamerice@gmail.com --- Documentation/core-api/printk-index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/core-api/printk-index.rst b/Documentation/core-api/printk-index.rst index 3062f37d119b..1979c5dd32fe 100644 --- a/Documentation/core-api/printk-index.rst +++ b/Documentation/core-api/printk-index.rst @@ -4,7 +4,7 @@ Printk Index ============ -There are many ways how to monitor the state of the system. One important +There are many ways to monitor the state of the system. One important source of information is the system log. It provides a lot of information, including more or less important warnings and error messages. @@ -101,7 +101,7 @@ their own wrappers adding __printk_index_emit(). Only few subsystem specific wrappers have been updated so far, for example, dev_printk(). As a result, the printk formats from -some subsystes can be missing in the printk index. +some subsystems can be missing in the printk index. Subsystem specific prefix From d3dedad43a999810e3bc7fc7db552e2cb9a218fa Mon Sep 17 00:00:00 2001 From: Utkarsh Tripathi Date: Fri, 3 May 2024 23:56:50 +0530 Subject: [PATCH 928/969] kernel-doc: Added "*" in $type_constants2 to fix 'make htmldocs' warning. Fixed: WARNING: Inline literal start-string without end-string in Documentation/core-api/workqueue.rst Added "*" in $type_constants2 in kernel-doc script to include "*" in the conversion to hightlights. Previously: %WQ_* --> ``WQ_``* After Changes: %WQ_* --> ``WQ_*`` Need for the fix: ``* is not recognized as a valid end-string for inline literal. Link: https://lore.kernel.org/linux-doc/640114d2-5780-48c3-a294-c0eba230f984@gmail.com Signed-off-by: Utkarsh Tripathi Suggested-by: Akira Yokosawa Reviewed-by: Akira Yokosawa Link: https://lore.kernel.org/r/20240503182650.7761-1-utripathi2002@gmail.com Signed-off-by: Jonathan Corbet --- scripts/kernel-doc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/kernel-doc b/scripts/kernel-doc index 438dfe76b989..7962d0daa638 100755 --- a/scripts/kernel-doc +++ b/scripts/kernel-doc @@ -62,7 +62,7 @@ my $anon_struct_union = 0; # match expressions used to find embedded type information my $type_constant = '\b``([^\`]+)``\b'; -my $type_constant2 = '\%([-_\w]+)'; +my $type_constant2 = '\%([-_*\w]+)'; my $type_func = '(\w+)\(\)'; my $type_param = '\@(\w*((\.\w+)|(->\w+))*(\.\.\.)?)'; my $type_param_ref = '([\!~\*]?)\@(\w*((\.\w+)|(->\w+))*(\.\.\.)?)'; From 31f605a308e627f06e4e6ab77254473f1c90f0bf Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Thu, 2 May 2024 16:12:17 +0200 Subject: [PATCH 929/969] kcsan, compiler_types: Introduce __data_racy type qualifier Based on the discussion at [1], it would be helpful to mark certain variables as explicitly "data racy", which would result in KCSAN not reporting data races involving any accesses on such variables. To do that, introduce the __data_racy type qualifier: struct foo { ... int __data_racy bar; ... }; In KCSAN-kernels, __data_racy turns into volatile, which KCSAN already treats specially by considering them "marked". In non-KCSAN kernels the type qualifier turns into no-op. The generated code between KCSAN-instrumented kernels and non-KCSAN kernels is already huge (inserted calls into runtime for every memory access), so the extra generated code (if any) due to volatile for few such __data_racy variables are unlikely to have measurable impact on performance. Link: https://lore.kernel.org/all/CAHk-=wi3iondeh_9V2g3Qz5oHTRjLsOpoy83hb58MVh=nRZe0A@mail.gmail.com/ [1] Suggested-by: Linus Torvalds Signed-off-by: Marco Elver Cc: Paul E. McKenney Cc: Tetsuo Handa Signed-off-by: Paul E. McKenney --- Documentation/dev-tools/kcsan.rst | 10 ++++++++++ include/linux/compiler_types.h | 7 +++++++ kernel/kcsan/kcsan_test.c | 17 +++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/Documentation/dev-tools/kcsan.rst b/Documentation/dev-tools/kcsan.rst index 94b6802ab0ab..02143f060b22 100644 --- a/Documentation/dev-tools/kcsan.rst +++ b/Documentation/dev-tools/kcsan.rst @@ -91,6 +91,16 @@ the below options are available: behaviour when encountering a data race is deemed safe. Please see `"Marking Shared-Memory Accesses" in the LKMM`_ for more information. +* Similar to ``data_race(...)``, the type qualifier ``__data_racy`` can be used + to document that all data races due to accesses to a variable are intended + and should be ignored by KCSAN:: + + struct foo { + ... + int __data_racy stats_counter; + ... + }; + * Disabling data race detection for entire functions can be accomplished by using the function attribute ``__no_kcsan``:: diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index 2abaa3a825a9..a38162a8590d 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -273,9 +273,16 @@ struct ftrace_likely_data { * disable all instrumentation. See Kconfig.kcsan where this is mandatory. */ # define __no_kcsan __no_sanitize_thread __disable_sanitizer_instrumentation +/* + * Type qualifier to mark variables where all data-racy accesses should be + * ignored by KCSAN. Note, the implementation simply marks these variables as + * volatile, since KCSAN will treat such accesses as "marked". + */ +# define __data_racy volatile # define __no_sanitize_or_inline __no_kcsan notrace __maybe_unused #else # define __no_kcsan +# define __data_racy #endif #ifndef __no_sanitize_or_inline diff --git a/kernel/kcsan/kcsan_test.c b/kernel/kcsan/kcsan_test.c index 015586217875..0c17b4c83e1c 100644 --- a/kernel/kcsan/kcsan_test.c +++ b/kernel/kcsan/kcsan_test.c @@ -304,6 +304,7 @@ static long test_array[3 * PAGE_SIZE / sizeof(long)]; static struct { long val[8]; } test_struct; +static long __data_racy test_data_racy; static DEFINE_SEQLOCK(test_seqlock); static DEFINE_SPINLOCK(test_spinlock); static DEFINE_MUTEX(test_mutex); @@ -358,6 +359,8 @@ static noinline void test_kernel_write_uninstrumented(void) { test_var++; } static noinline void test_kernel_data_race(void) { data_race(test_var++); } +static noinline void test_kernel_data_racy_qualifier(void) { test_data_racy++; } + static noinline void test_kernel_assert_writer(void) { ASSERT_EXCLUSIVE_WRITER(test_var); @@ -1009,6 +1012,19 @@ static void test_data_race(struct kunit *test) KUNIT_EXPECT_FALSE(test, match_never); } +/* Test the __data_racy type qualifier. */ +__no_kcsan +static void test_data_racy_qualifier(struct kunit *test) +{ + bool match_never = false; + + begin_test_checks(test_kernel_data_racy_qualifier, test_kernel_data_racy_qualifier); + do { + match_never = report_available(); + } while (!end_test_checks(match_never)); + KUNIT_EXPECT_FALSE(test, match_never); +} + __no_kcsan static void test_assert_exclusive_writer(struct kunit *test) { @@ -1424,6 +1440,7 @@ static struct kunit_case kcsan_test_cases[] = { KCSAN_KUNIT_CASE(test_read_plain_atomic_rmw), KCSAN_KUNIT_CASE(test_zero_size_access), KCSAN_KUNIT_CASE(test_data_race), + KCSAN_KUNIT_CASE(test_data_racy_qualifier), KCSAN_KUNIT_CASE(test_assert_exclusive_writer), KCSAN_KUNIT_CASE(test_assert_exclusive_access), KCSAN_KUNIT_CASE(test_assert_exclusive_access_writer), From 9578e327b2b4935a25d49e3891b8fcca9b6c10c6 Mon Sep 17 00:00:00 2001 From: Luis Henriques Date: Tue, 30 Jan 2024 10:13:44 +0000 Subject: [PATCH 930/969] keys: update key quotas in key_put() Delaying key quotas update when key's refcount reaches 0 in key_put() has been causing some issues in fscrypt testing, specifically in fstest generic/581. This commit fixes this test flakiness by dealing with the quotas immediately, and leaving all the other clean-ups to the key garbage collector. This is done by moving the updates to the qnkeys and qnbytes fields in struct key_user from key_gc_unused_keys() into key_put(). Unfortunately, this also means that we need to switch to the irq-version of the spinlock that protects these fields and use spin_lock_{irqsave,irqrestore} in all the code that touches these fields. Signed-off-by: Luis Henriques Reviewed-by: Jarkko Sakkinen Acked-by: David Howells Signed-off-by: Jarkko Sakkinen --- security/keys/gc.c | 8 -------- security/keys/key.c | 32 ++++++++++++++++++++++---------- security/keys/keyctl.c | 11 ++++++----- 3 files changed, 28 insertions(+), 23 deletions(-) diff --git a/security/keys/gc.c b/security/keys/gc.c index eaddaceda14e..7d687b0962b1 100644 --- a/security/keys/gc.c +++ b/security/keys/gc.c @@ -155,14 +155,6 @@ static noinline void key_gc_unused_keys(struct list_head *keys) security_key_free(key); - /* deal with the user's key tracking and quota */ - if (test_bit(KEY_FLAG_IN_QUOTA, &key->flags)) { - spin_lock(&key->user->lock); - key->user->qnkeys--; - key->user->qnbytes -= key->quotalen; - spin_unlock(&key->user->lock); - } - atomic_dec(&key->user->nkeys); if (state != KEY_IS_UNINSTANTIATED) atomic_dec(&key->user->nikeys); diff --git a/security/keys/key.c b/security/keys/key.c index 560790038329..2a9a769e795e 100644 --- a/security/keys/key.c +++ b/security/keys/key.c @@ -230,6 +230,7 @@ struct key *key_alloc(struct key_type *type, const char *desc, struct key *key; size_t desclen, quotalen; int ret; + unsigned long irqflags; key = ERR_PTR(-EINVAL); if (!desc || !*desc) @@ -259,7 +260,7 @@ struct key *key_alloc(struct key_type *type, const char *desc, unsigned maxbytes = uid_eq(uid, GLOBAL_ROOT_UID) ? key_quota_root_maxbytes : key_quota_maxbytes; - spin_lock(&user->lock); + spin_lock_irqsave(&user->lock, irqflags); if (!(flags & KEY_ALLOC_QUOTA_OVERRUN)) { if (user->qnkeys + 1 > maxkeys || user->qnbytes + quotalen > maxbytes || @@ -269,7 +270,7 @@ struct key *key_alloc(struct key_type *type, const char *desc, user->qnkeys++; user->qnbytes += quotalen; - spin_unlock(&user->lock); + spin_unlock_irqrestore(&user->lock, irqflags); } /* allocate and initialise the key and its description */ @@ -327,10 +328,10 @@ security_error: kfree(key->description); kmem_cache_free(key_jar, key); if (!(flags & KEY_ALLOC_NOT_IN_QUOTA)) { - spin_lock(&user->lock); + spin_lock_irqsave(&user->lock, irqflags); user->qnkeys--; user->qnbytes -= quotalen; - spin_unlock(&user->lock); + spin_unlock_irqrestore(&user->lock, irqflags); } key_user_put(user); key = ERR_PTR(ret); @@ -340,10 +341,10 @@ no_memory_3: kmem_cache_free(key_jar, key); no_memory_2: if (!(flags & KEY_ALLOC_NOT_IN_QUOTA)) { - spin_lock(&user->lock); + spin_lock_irqsave(&user->lock, irqflags); user->qnkeys--; user->qnbytes -= quotalen; - spin_unlock(&user->lock); + spin_unlock_irqrestore(&user->lock, irqflags); } key_user_put(user); no_memory_1: @@ -351,7 +352,7 @@ no_memory_1: goto error; no_quota: - spin_unlock(&user->lock); + spin_unlock_irqrestore(&user->lock, irqflags); key_user_put(user); key = ERR_PTR(-EDQUOT); goto error; @@ -380,8 +381,9 @@ int key_payload_reserve(struct key *key, size_t datalen) if (delta != 0 && test_bit(KEY_FLAG_IN_QUOTA, &key->flags)) { unsigned maxbytes = uid_eq(key->user->uid, GLOBAL_ROOT_UID) ? key_quota_root_maxbytes : key_quota_maxbytes; + unsigned long flags; - spin_lock(&key->user->lock); + spin_lock_irqsave(&key->user->lock, flags); if (delta > 0 && (key->user->qnbytes + delta > maxbytes || @@ -392,7 +394,7 @@ int key_payload_reserve(struct key *key, size_t datalen) key->user->qnbytes += delta; key->quotalen += delta; } - spin_unlock(&key->user->lock); + spin_unlock_irqrestore(&key->user->lock, flags); } /* change the recorded data length if that didn't generate an error */ @@ -645,8 +647,18 @@ void key_put(struct key *key) if (key) { key_check(key); - if (refcount_dec_and_test(&key->usage)) + if (refcount_dec_and_test(&key->usage)) { + unsigned long flags; + + /* deal with the user's key tracking and quota */ + if (test_bit(KEY_FLAG_IN_QUOTA, &key->flags)) { + spin_lock_irqsave(&key->user->lock, flags); + key->user->qnkeys--; + key->user->qnbytes -= key->quotalen; + spin_unlock_irqrestore(&key->user->lock, flags); + } schedule_work(&key_gc_work); + } } } EXPORT_SYMBOL(key_put); diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c index 10ba439968f7..4bc3e9398ee3 100644 --- a/security/keys/keyctl.c +++ b/security/keys/keyctl.c @@ -954,6 +954,7 @@ long keyctl_chown_key(key_serial_t id, uid_t user, gid_t group) long ret; kuid_t uid; kgid_t gid; + unsigned long flags; uid = make_kuid(current_user_ns(), user); gid = make_kgid(current_user_ns(), group); @@ -1010,7 +1011,7 @@ long keyctl_chown_key(key_serial_t id, uid_t user, gid_t group) unsigned maxbytes = uid_eq(uid, GLOBAL_ROOT_UID) ? key_quota_root_maxbytes : key_quota_maxbytes; - spin_lock(&newowner->lock); + spin_lock_irqsave(&newowner->lock, flags); if (newowner->qnkeys + 1 > maxkeys || newowner->qnbytes + key->quotalen > maxbytes || newowner->qnbytes + key->quotalen < @@ -1019,12 +1020,12 @@ long keyctl_chown_key(key_serial_t id, uid_t user, gid_t group) newowner->qnkeys++; newowner->qnbytes += key->quotalen; - spin_unlock(&newowner->lock); + spin_unlock_irqrestore(&newowner->lock, flags); - spin_lock(&key->user->lock); + spin_lock_irqsave(&key->user->lock, flags); key->user->qnkeys--; key->user->qnbytes -= key->quotalen; - spin_unlock(&key->user->lock); + spin_unlock_irqrestore(&key->user->lock, flags); } atomic_dec(&key->user->nkeys); @@ -1056,7 +1057,7 @@ error: return ret; quota_overrun: - spin_unlock(&newowner->lock); + spin_unlock_irqrestore(&newowner->lock, flags); zapowner = newowner; ret = -EDQUOT; goto error_put; From 9da27fb65a14c18efd4473e2e82b76b53ba60252 Mon Sep 17 00:00:00 2001 From: Silvio Gissi Date: Fri, 15 Mar 2024 15:05:39 -0400 Subject: [PATCH 931/969] keys: Fix overwrite of key expiration on instantiation The expiry time of a key is unconditionally overwritten during instantiation, defaulting to turn it permanent. This causes a problem for DNS resolution as the expiration set by user-space is overwritten to TIME64_MAX, disabling further DNS updates. Fix this by restoring the condition that key_set_expiry is only called when the pre-parser sets a specific expiry. Fixes: 39299bdd2546 ("keys, dns: Allow key types (eg. DNS) to be reclaimed immediately on expiry") Signed-off-by: Silvio Gissi cc: David Howells cc: Hazem Mohamed Abuelfotoh cc: linux-afs@lists.infradead.org cc: linux-cifs@vger.kernel.org cc: keyrings@vger.kernel.org cc: netdev@vger.kernel.org cc: stable@vger.kernel.org Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- security/keys/key.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/security/keys/key.c b/security/keys/key.c index 2a9a769e795e..3d7d185019d3 100644 --- a/security/keys/key.c +++ b/security/keys/key.c @@ -465,7 +465,8 @@ static int __key_instantiate_and_link(struct key *key, if (authkey) key_invalidate(authkey); - key_set_expiry(key, prep->expiry); + if (prep->expiry != TIME64_MAX) + key_set_expiry(key, prep->expiry); } } From 3d16af0b4cfac4b2c3b238e2ec37b38c2f316978 Mon Sep 17 00:00:00 2001 From: David Gstir Date: Wed, 3 Apr 2024 09:21:17 +0200 Subject: [PATCH 932/969] crypto: mxs-dcp: Add support for hardware-bound keys DCP (Data Co-Processor) is able to derive private keys for a fused random seed, which can be referenced by handle but not accessed by the CPU. Similarly, DCP is able to store arbitrary keys in four dedicated key slots located in its secure memory area (internal SRAM). These keys can be used to perform AES encryption. Expose these derived keys and key slots through the crypto API via their handle. The main purpose is to add DCP-backed trusted keys. Other use cases are possible too (see similar existing paes implementations), but these should carefully be evaluated as e.g. enabling AF_ALG will give userspace full access to use keys. In scenarios with untrustworthy userspace, this will enable en-/decryption oracles. Co-developed-by: Richard Weinberger Signed-off-by: Richard Weinberger Co-developed-by: David Oberhollenzer Signed-off-by: David Oberhollenzer Signed-off-by: David Gstir Acked-by: Herbert Xu Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/crypto/mxs-dcp.c | 104 ++++++++++++++++++++++++++++++++++----- include/soc/fsl/dcp.h | 20 ++++++++ 2 files changed, 113 insertions(+), 11 deletions(-) create mode 100644 include/soc/fsl/dcp.h diff --git a/drivers/crypto/mxs-dcp.c b/drivers/crypto/mxs-dcp.c index 2b3ebe0db3a6..057d73c370b7 100644 --- a/drivers/crypto/mxs-dcp.c +++ b/drivers/crypto/mxs-dcp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -101,6 +102,7 @@ struct dcp_async_ctx { struct crypto_skcipher *fallback; unsigned int key_len; uint8_t key[AES_KEYSIZE_128]; + bool key_referenced; }; struct dcp_aes_req_ctx { @@ -155,6 +157,7 @@ static struct dcp *global_sdcp; #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13) #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12) #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11) +#define MXS_DCP_CONTROL0_OTP_KEY (1 << 10) #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8) #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9) #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6) @@ -168,6 +171,8 @@ static struct dcp *global_sdcp; #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4) #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0) +#define MXS_DCP_CONTROL1_KEY_SELECT_SHIFT 8 + static int mxs_dcp_start_dma(struct dcp_async_ctx *actx) { int dma_err; @@ -224,13 +229,16 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, struct dcp *sdcp = global_sdcp; struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan]; struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); + bool key_referenced = actx->key_referenced; int ret; - key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key, - 2 * AES_KEYSIZE_128, DMA_TO_DEVICE); - ret = dma_mapping_error(sdcp->dev, key_phys); - if (ret) - return ret; + if (!key_referenced) { + key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key, + 2 * AES_KEYSIZE_128, DMA_TO_DEVICE); + ret = dma_mapping_error(sdcp->dev, key_phys); + if (ret) + return ret; + } src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf, DCP_BUF_SZ, DMA_TO_DEVICE); @@ -255,8 +263,12 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, MXS_DCP_CONTROL0_INTERRUPT | MXS_DCP_CONTROL0_ENABLE_CIPHER; - /* Payload contains the key. */ - desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; + if (key_referenced) + /* Set OTP key bit to select the key via KEY_SELECT. */ + desc->control0 |= MXS_DCP_CONTROL0_OTP_KEY; + else + /* Payload contains the key. */ + desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY; if (rctx->enc) desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT; @@ -270,6 +282,9 @@ static int mxs_dcp_run_aes(struct dcp_async_ctx *actx, else desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC; + if (key_referenced) + desc->control1 |= sdcp->coh->aes_key[0] << MXS_DCP_CONTROL1_KEY_SELECT_SHIFT; + desc->next_cmd_addr = 0; desc->source = src_phys; desc->destination = dst_phys; @@ -284,9 +299,9 @@ aes_done_run: err_dst: dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE); err_src: - dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128, - DMA_TO_DEVICE); - + if (!key_referenced) + dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128, + DMA_TO_DEVICE); return ret; } @@ -453,7 +468,7 @@ static int mxs_dcp_aes_enqueue(struct skcipher_request *req, int enc, int ecb) struct dcp_aes_req_ctx *rctx = skcipher_request_ctx(req); int ret; - if (unlikely(actx->key_len != AES_KEYSIZE_128)) + if (unlikely(actx->key_len != AES_KEYSIZE_128 && !actx->key_referenced)) return mxs_dcp_block_fallback(req, enc); rctx->enc = enc; @@ -500,6 +515,7 @@ static int mxs_dcp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, * there can still be an operation in progress. */ actx->key_len = len; + actx->key_referenced = false; if (len == AES_KEYSIZE_128) { memcpy(actx->key, key, len); return 0; @@ -516,6 +532,32 @@ static int mxs_dcp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, return crypto_skcipher_setkey(actx->fallback, key, len); } +static int mxs_dcp_aes_setrefkey(struct crypto_skcipher *tfm, const u8 *key, + unsigned int len) +{ + struct dcp_async_ctx *actx = crypto_skcipher_ctx(tfm); + + if (len != DCP_PAES_KEYSIZE) + return -EINVAL; + + switch (key[0]) { + case DCP_PAES_KEY_SLOT0: + case DCP_PAES_KEY_SLOT1: + case DCP_PAES_KEY_SLOT2: + case DCP_PAES_KEY_SLOT3: + case DCP_PAES_KEY_UNIQUE: + case DCP_PAES_KEY_OTP: + memcpy(actx->key, key, len); + actx->key_len = len; + actx->key_referenced = true; + break; + default: + return -EINVAL; + } + + return 0; +} + static int mxs_dcp_aes_fallback_init_tfm(struct crypto_skcipher *tfm) { const char *name = crypto_tfm_alg_name(crypto_skcipher_tfm(tfm)); @@ -539,6 +581,13 @@ static void mxs_dcp_aes_fallback_exit_tfm(struct crypto_skcipher *tfm) crypto_free_skcipher(actx->fallback); } +static int mxs_dcp_paes_init_tfm(struct crypto_skcipher *tfm) +{ + crypto_skcipher_set_reqsize(tfm, sizeof(struct dcp_aes_req_ctx)); + + return 0; +} + /* * Hashing (SHA1/SHA256) */ @@ -889,6 +938,39 @@ static struct skcipher_alg dcp_aes_algs[] = { .ivsize = AES_BLOCK_SIZE, .init = mxs_dcp_aes_fallback_init_tfm, .exit = mxs_dcp_aes_fallback_exit_tfm, + }, { + .base.cra_name = "ecb(paes)", + .base.cra_driver_name = "ecb-paes-dcp", + .base.cra_priority = 401, + .base.cra_alignmask = 15, + .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_INTERNAL, + .base.cra_blocksize = AES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct dcp_async_ctx), + .base.cra_module = THIS_MODULE, + + .min_keysize = DCP_PAES_KEYSIZE, + .max_keysize = DCP_PAES_KEYSIZE, + .setkey = mxs_dcp_aes_setrefkey, + .encrypt = mxs_dcp_aes_ecb_encrypt, + .decrypt = mxs_dcp_aes_ecb_decrypt, + .init = mxs_dcp_paes_init_tfm, + }, { + .base.cra_name = "cbc(paes)", + .base.cra_driver_name = "cbc-paes-dcp", + .base.cra_priority = 401, + .base.cra_alignmask = 15, + .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_INTERNAL, + .base.cra_blocksize = AES_BLOCK_SIZE, + .base.cra_ctxsize = sizeof(struct dcp_async_ctx), + .base.cra_module = THIS_MODULE, + + .min_keysize = DCP_PAES_KEYSIZE, + .max_keysize = DCP_PAES_KEYSIZE, + .setkey = mxs_dcp_aes_setrefkey, + .encrypt = mxs_dcp_aes_cbc_encrypt, + .decrypt = mxs_dcp_aes_cbc_decrypt, + .ivsize = AES_BLOCK_SIZE, + .init = mxs_dcp_paes_init_tfm, }, }; diff --git a/include/soc/fsl/dcp.h b/include/soc/fsl/dcp.h new file mode 100644 index 000000000000..3ec335d8ca8b --- /dev/null +++ b/include/soc/fsl/dcp.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 sigma star gmbh + * + * Specifies paes key slot handles for NXP's DCP (Data Co-Processor) to be used + * with the crypto_skcipher_setkey(). + */ + +#ifndef MXS_DCP_H +#define MXS_DCP_H + +#define DCP_PAES_KEYSIZE 1 +#define DCP_PAES_KEY_SLOT0 0x00 +#define DCP_PAES_KEY_SLOT1 0x01 +#define DCP_PAES_KEY_SLOT2 0x02 +#define DCP_PAES_KEY_SLOT3 0x03 +#define DCP_PAES_KEY_UNIQUE 0xfe +#define DCP_PAES_KEY_OTP 0xff + +#endif /* MXS_DCP_H */ From 633cb72fb6969e420518fee4b2ae6040688ecc5a Mon Sep 17 00:00:00 2001 From: David Gstir Date: Wed, 3 Apr 2024 09:21:18 +0200 Subject: [PATCH 933/969] KEYS: trusted: improve scalability of trust source config Enabling trusted keys requires at least one trust source implementation (currently TPM, TEE or CAAM) to be enabled. Currently, this is done by checking each trust source's config option individually. This does not scale when more trust sources like the one for DCP are added, because the condition will get long and hard to read. Add config HAVE_TRUSTED_KEYS which is set to true by each trust source once its enabled and adapt the check for having at least one active trust source to use this option. Whenever a new trust source is added, it now needs to select HAVE_TRUSTED_KEYS. Signed-off-by: David Gstir Tested-by: Jarkko Sakkinen # for TRUSTED_KEYS_TPM Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- security/keys/trusted-keys/Kconfig | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/security/keys/trusted-keys/Kconfig b/security/keys/trusted-keys/Kconfig index dbfdd8536468..553dc117f385 100644 --- a/security/keys/trusted-keys/Kconfig +++ b/security/keys/trusted-keys/Kconfig @@ -1,3 +1,6 @@ +config HAVE_TRUSTED_KEYS + bool + config TRUSTED_KEYS_TPM bool "TPM-based trusted keys" depends on TCG_TPM >= TRUSTED_KEYS @@ -9,6 +12,7 @@ config TRUSTED_KEYS_TPM select ASN1_ENCODER select OID_REGISTRY select ASN1 + select HAVE_TRUSTED_KEYS help Enable use of the Trusted Platform Module (TPM) as trusted key backend. Trusted keys are random number symmetric keys, @@ -20,6 +24,7 @@ config TRUSTED_KEYS_TEE bool "TEE-based trusted keys" depends on TEE >= TRUSTED_KEYS default y + select HAVE_TRUSTED_KEYS help Enable use of the Trusted Execution Environment (TEE) as trusted key backend. @@ -29,10 +34,11 @@ config TRUSTED_KEYS_CAAM depends on CRYPTO_DEV_FSL_CAAM_JR >= TRUSTED_KEYS select CRYPTO_DEV_FSL_CAAM_BLOB_GEN default y + select HAVE_TRUSTED_KEYS help Enable use of NXP's Cryptographic Accelerator and Assurance Module (CAAM) as trusted key backend. -if !TRUSTED_KEYS_TPM && !TRUSTED_KEYS_TEE && !TRUSTED_KEYS_CAAM -comment "No trust source selected!" +if !HAVE_TRUSTED_KEYS + comment "No trust source selected!" endif From 2e8a0f40a39cc253002f21c54e1b5b995e5ec510 Mon Sep 17 00:00:00 2001 From: David Gstir Date: Wed, 3 Apr 2024 09:21:19 +0200 Subject: [PATCH 934/969] KEYS: trusted: Introduce NXP DCP-backed trusted keys DCP (Data Co-Processor) is the little brother of NXP's CAAM IP. Beside of accelerated crypto operations, it also offers support for hardware-bound keys. Using this feature it is possible to implement a blob mechanism similar to what CAAM offers. Unlike on CAAM, constructing and parsing the blob has to happen in software (i.e. the kernel). The software-based blob format used by DCP trusted keys encrypts the payload using AES-128-GCM with a freshly generated random key and nonce. The random key itself is AES-128-ECB encrypted using the DCP unique or OTP key. The DCP trusted key blob format is: /* * struct dcp_blob_fmt - DCP BLOB format. * * @fmt_version: Format version, currently being %1 * @blob_key: Random AES 128 key which is used to encrypt @payload, * @blob_key itself is encrypted with OTP or UNIQUE device key in * AES-128-ECB mode by DCP. * @nonce: Random nonce used for @payload encryption. * @payload_len: Length of the plain text @payload. * @payload: The payload itself, encrypted using AES-128-GCM and @blob_key, * GCM auth tag of size AES_BLOCK_SIZE is attached at the end of it. * * The total size of a DCP BLOB is sizeof(struct dcp_blob_fmt) + @payload_len + * AES_BLOCK_SIZE. */ struct dcp_blob_fmt { __u8 fmt_version; __u8 blob_key[AES_KEYSIZE_128]; __u8 nonce[AES_KEYSIZE_128]; __le32 payload_len; __u8 payload[]; } __packed; By default the unique key is used. It is also possible to use the OTP key. While the unique key should be unique it is not documented how this key is derived. Therefore selection the OTP key is supported as well via the use_otp_key module parameter. Co-developed-by: Richard Weinberger Signed-off-by: Richard Weinberger Co-developed-by: David Oberhollenzer Signed-off-by: David Oberhollenzer Signed-off-by: David Gstir Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- include/keys/trusted_dcp.h | 11 + security/keys/trusted-keys/Kconfig | 8 + security/keys/trusted-keys/Makefile | 2 + security/keys/trusted-keys/trusted_core.c | 6 +- security/keys/trusted-keys/trusted_dcp.c | 313 ++++++++++++++++++++++ 5 files changed, 339 insertions(+), 1 deletion(-) create mode 100644 include/keys/trusted_dcp.h create mode 100644 security/keys/trusted-keys/trusted_dcp.c diff --git a/include/keys/trusted_dcp.h b/include/keys/trusted_dcp.h new file mode 100644 index 000000000000..9aaa42075b40 --- /dev/null +++ b/include/keys/trusted_dcp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 sigma star gmbh + */ + +#ifndef TRUSTED_DCP_H +#define TRUSTED_DCP_H + +extern struct trusted_key_ops dcp_trusted_key_ops; + +#endif diff --git a/security/keys/trusted-keys/Kconfig b/security/keys/trusted-keys/Kconfig index 553dc117f385..1fb8aa001995 100644 --- a/security/keys/trusted-keys/Kconfig +++ b/security/keys/trusted-keys/Kconfig @@ -39,6 +39,14 @@ config TRUSTED_KEYS_CAAM Enable use of NXP's Cryptographic Accelerator and Assurance Module (CAAM) as trusted key backend. +config TRUSTED_KEYS_DCP + bool "DCP-based trusted keys" + depends on CRYPTO_DEV_MXS_DCP >= TRUSTED_KEYS + default y + select HAVE_TRUSTED_KEYS + help + Enable use of NXP's DCP (Data Co-Processor) as trusted key backend. + if !HAVE_TRUSTED_KEYS comment "No trust source selected!" endif diff --git a/security/keys/trusted-keys/Makefile b/security/keys/trusted-keys/Makefile index 735aa0bc08ef..f0f3b27f688b 100644 --- a/security/keys/trusted-keys/Makefile +++ b/security/keys/trusted-keys/Makefile @@ -14,3 +14,5 @@ trusted-$(CONFIG_TRUSTED_KEYS_TPM) += tpm2key.asn1.o trusted-$(CONFIG_TRUSTED_KEYS_TEE) += trusted_tee.o trusted-$(CONFIG_TRUSTED_KEYS_CAAM) += trusted_caam.o + +trusted-$(CONFIG_TRUSTED_KEYS_DCP) += trusted_dcp.o diff --git a/security/keys/trusted-keys/trusted_core.c b/security/keys/trusted-keys/trusted_core.c index fee1ab2c734d..5113aeae5628 100644 --- a/security/keys/trusted-keys/trusted_core.c +++ b/security/keys/trusted-keys/trusted_core.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -30,7 +31,7 @@ MODULE_PARM_DESC(rng, "Select trusted key RNG"); static char *trusted_key_source; module_param_named(source, trusted_key_source, charp, 0); -MODULE_PARM_DESC(source, "Select trusted keys source (tpm, tee or caam)"); +MODULE_PARM_DESC(source, "Select trusted keys source (tpm, tee, caam or dcp)"); static const struct trusted_key_source trusted_key_sources[] = { #if defined(CONFIG_TRUSTED_KEYS_TPM) @@ -42,6 +43,9 @@ static const struct trusted_key_source trusted_key_sources[] = { #if defined(CONFIG_TRUSTED_KEYS_CAAM) { "caam", &trusted_key_caam_ops }, #endif +#if defined(CONFIG_TRUSTED_KEYS_DCP) + { "dcp", &dcp_trusted_key_ops }, +#endif }; DEFINE_STATIC_CALL_NULL(trusted_key_seal, *trusted_key_sources[0].ops->seal); diff --git a/security/keys/trusted-keys/trusted_dcp.c b/security/keys/trusted-keys/trusted_dcp.c new file mode 100644 index 000000000000..16c44aafeab3 --- /dev/null +++ b/security/keys/trusted-keys/trusted_dcp.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 sigma star gmbh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DCP_BLOB_VERSION 1 +#define DCP_BLOB_AUTHLEN 16 + +/** + * struct dcp_blob_fmt - DCP BLOB format. + * + * @fmt_version: Format version, currently being %1. + * @blob_key: Random AES 128 key which is used to encrypt @payload, + * @blob_key itself is encrypted with OTP or UNIQUE device key in + * AES-128-ECB mode by DCP. + * @nonce: Random nonce used for @payload encryption. + * @payload_len: Length of the plain text @payload. + * @payload: The payload itself, encrypted using AES-128-GCM and @blob_key, + * GCM auth tag of size DCP_BLOB_AUTHLEN is attached at the end of it. + * + * The total size of a DCP BLOB is sizeof(struct dcp_blob_fmt) + @payload_len + + * DCP_BLOB_AUTHLEN. + */ +struct dcp_blob_fmt { + __u8 fmt_version; + __u8 blob_key[AES_KEYSIZE_128]; + __u8 nonce[AES_KEYSIZE_128]; + __le32 payload_len; + __u8 payload[]; +} __packed; + +static bool use_otp_key; +module_param_named(dcp_use_otp_key, use_otp_key, bool, 0); +MODULE_PARM_DESC(dcp_use_otp_key, "Use OTP instead of UNIQUE key for sealing"); + +static bool skip_zk_test; +module_param_named(dcp_skip_zk_test, skip_zk_test, bool, 0); +MODULE_PARM_DESC(dcp_skip_zk_test, "Don't test whether device keys are zero'ed"); + +static unsigned int calc_blob_len(unsigned int payload_len) +{ + return sizeof(struct dcp_blob_fmt) + payload_len + DCP_BLOB_AUTHLEN; +} + +static int do_dcp_crypto(u8 *in, u8 *out, bool do_encrypt) +{ + struct skcipher_request *req = NULL; + struct scatterlist src_sg, dst_sg; + struct crypto_skcipher *tfm; + u8 paes_key[DCP_PAES_KEYSIZE]; + DECLARE_CRYPTO_WAIT(wait); + int res = 0; + + if (use_otp_key) + paes_key[0] = DCP_PAES_KEY_OTP; + else + paes_key[0] = DCP_PAES_KEY_UNIQUE; + + tfm = crypto_alloc_skcipher("ecb-paes-dcp", CRYPTO_ALG_INTERNAL, + CRYPTO_ALG_INTERNAL); + if (IS_ERR(tfm)) { + res = PTR_ERR(tfm); + tfm = NULL; + goto out; + } + + req = skcipher_request_alloc(tfm, GFP_NOFS); + if (!req) { + res = -ENOMEM; + goto out; + } + + skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG | + CRYPTO_TFM_REQ_MAY_SLEEP, + crypto_req_done, &wait); + res = crypto_skcipher_setkey(tfm, paes_key, sizeof(paes_key)); + if (res < 0) + goto out; + + sg_init_one(&src_sg, in, AES_KEYSIZE_128); + sg_init_one(&dst_sg, out, AES_KEYSIZE_128); + skcipher_request_set_crypt(req, &src_sg, &dst_sg, AES_KEYSIZE_128, + NULL); + + if (do_encrypt) + res = crypto_wait_req(crypto_skcipher_encrypt(req), &wait); + else + res = crypto_wait_req(crypto_skcipher_decrypt(req), &wait); + +out: + skcipher_request_free(req); + crypto_free_skcipher(tfm); + + return res; +} + +static int do_aead_crypto(u8 *in, u8 *out, size_t len, u8 *key, u8 *nonce, + bool do_encrypt) +{ + struct aead_request *aead_req = NULL; + struct scatterlist src_sg, dst_sg; + struct crypto_aead *aead; + int ret; + + aead = crypto_alloc_aead("gcm(aes)", 0, CRYPTO_ALG_ASYNC); + if (IS_ERR(aead)) { + ret = PTR_ERR(aead); + goto out; + } + + ret = crypto_aead_setauthsize(aead, DCP_BLOB_AUTHLEN); + if (ret < 0) { + pr_err("Can't set crypto auth tag len: %d\n", ret); + goto free_aead; + } + + aead_req = aead_request_alloc(aead, GFP_KERNEL); + if (!aead_req) { + ret = -ENOMEM; + goto free_aead; + } + + sg_init_one(&src_sg, in, len); + if (do_encrypt) { + /* + * If we encrypt our buffer has extra space for the auth tag. + */ + sg_init_one(&dst_sg, out, len + DCP_BLOB_AUTHLEN); + } else { + sg_init_one(&dst_sg, out, len); + } + + aead_request_set_crypt(aead_req, &src_sg, &dst_sg, len, nonce); + aead_request_set_callback(aead_req, CRYPTO_TFM_REQ_MAY_SLEEP, NULL, + NULL); + aead_request_set_ad(aead_req, 0); + + if (crypto_aead_setkey(aead, key, AES_KEYSIZE_128)) { + pr_err("Can't set crypto AEAD key\n"); + ret = -EINVAL; + goto free_req; + } + + if (do_encrypt) + ret = crypto_aead_encrypt(aead_req); + else + ret = crypto_aead_decrypt(aead_req); + +free_req: + aead_request_free(aead_req); +free_aead: + crypto_free_aead(aead); +out: + return ret; +} + +static int decrypt_blob_key(u8 *key) +{ + return do_dcp_crypto(key, key, false); +} + +static int encrypt_blob_key(u8 *key) +{ + return do_dcp_crypto(key, key, true); +} + +static int trusted_dcp_seal(struct trusted_key_payload *p, char *datablob) +{ + struct dcp_blob_fmt *b = (struct dcp_blob_fmt *)p->blob; + int blen, ret; + + blen = calc_blob_len(p->key_len); + if (blen > MAX_BLOB_SIZE) + return -E2BIG; + + b->fmt_version = DCP_BLOB_VERSION; + get_random_bytes(b->nonce, AES_KEYSIZE_128); + get_random_bytes(b->blob_key, AES_KEYSIZE_128); + + ret = do_aead_crypto(p->key, b->payload, p->key_len, b->blob_key, + b->nonce, true); + if (ret) { + pr_err("Unable to encrypt blob payload: %i\n", ret); + return ret; + } + + ret = encrypt_blob_key(b->blob_key); + if (ret) { + pr_err("Unable to encrypt blob key: %i\n", ret); + return ret; + } + + b->payload_len = get_unaligned_le32(&p->key_len); + p->blob_len = blen; + return 0; +} + +static int trusted_dcp_unseal(struct trusted_key_payload *p, char *datablob) +{ + struct dcp_blob_fmt *b = (struct dcp_blob_fmt *)p->blob; + int blen, ret; + + if (b->fmt_version != DCP_BLOB_VERSION) { + pr_err("DCP blob has bad version: %i, expected %i\n", + b->fmt_version, DCP_BLOB_VERSION); + ret = -EINVAL; + goto out; + } + + p->key_len = le32_to_cpu(b->payload_len); + blen = calc_blob_len(p->key_len); + if (blen != p->blob_len) { + pr_err("DCP blob has bad length: %i != %i\n", blen, + p->blob_len); + ret = -EINVAL; + goto out; + } + + ret = decrypt_blob_key(b->blob_key); + if (ret) { + pr_err("Unable to decrypt blob key: %i\n", ret); + goto out; + } + + ret = do_aead_crypto(b->payload, p->key, p->key_len + DCP_BLOB_AUTHLEN, + b->blob_key, b->nonce, false); + if (ret) { + pr_err("Unwrap of DCP payload failed: %i\n", ret); + goto out; + } + + ret = 0; +out: + return ret; +} + +static int test_for_zero_key(void) +{ + /* + * Encrypting a plaintext of all 0x55 bytes will yield + * this ciphertext in case the DCP test key is used. + */ + static const u8 bad[] = {0x9a, 0xda, 0xe0, 0x54, 0xf6, 0x3d, 0xfa, 0xff, + 0x5e, 0xa1, 0x8e, 0x45, 0xed, 0xf6, 0xea, 0x6f}; + void *buf = NULL; + int ret = 0; + + if (skip_zk_test) + goto out; + + buf = kmalloc(AES_BLOCK_SIZE, GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto out; + } + + memset(buf, 0x55, AES_BLOCK_SIZE); + + ret = do_dcp_crypto(buf, buf, true); + if (ret) + goto out; + + if (memcmp(buf, bad, AES_BLOCK_SIZE) == 0) { + pr_warn("Device neither in secure nor trusted mode!\n"); + ret = -EINVAL; + } +out: + kfree(buf); + return ret; +} + +static int trusted_dcp_init(void) +{ + int ret; + + if (use_otp_key) + pr_info("Using DCP OTP key\n"); + + ret = test_for_zero_key(); + if (ret) { + pr_warn("Test for zero'ed keys failed: %i\n", ret); + + return -EINVAL; + } + + return register_key_type(&key_type_trusted); +} + +static void trusted_dcp_exit(void) +{ + unregister_key_type(&key_type_trusted); +} + +struct trusted_key_ops dcp_trusted_key_ops = { + .exit = trusted_dcp_exit, + .init = trusted_dcp_init, + .seal = trusted_dcp_seal, + .unseal = trusted_dcp_unseal, + .migratable = 0, +}; From df866688d49ccbe4efcd2a3e7d1e1b5e6ee1aa71 Mon Sep 17 00:00:00 2001 From: David Gstir Date: Wed, 3 Apr 2024 09:21:20 +0200 Subject: [PATCH 935/969] MAINTAINERS: add entry for DCP-based trusted keys This covers trusted keys backed by NXP's DCP (Data Co-Processor) chip found in smaller i.MX SoCs. Signed-off-by: David Gstir Acked-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ec0284125e8f..23dfe1761fbc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12014,6 +12014,15 @@ S: Maintained F: include/keys/trusted_caam.h F: security/keys/trusted-keys/trusted_caam.c +KEYS-TRUSTED-DCP +M: David Gstir +R: sigma star Kernel Team +L: linux-integrity@vger.kernel.org +L: keyrings@vger.kernel.org +S: Supported +F: include/keys/trusted_dcp.h +F: security/keys/trusted-keys/trusted_dcp.c + KEYS-TRUSTED-TEE M: Sumit Garg L: linux-integrity@vger.kernel.org From b85b253e23bc985ecb0dad329da2147fb396223c Mon Sep 17 00:00:00 2001 From: David Gstir Date: Wed, 3 Apr 2024 09:21:21 +0200 Subject: [PATCH 936/969] docs: document DCP-backed trusted keys kernel params Document the kernel parameters trusted.dcp_use_otp_key and trusted.dcp_skip_zk_test for DCP-backed trusted keys. Co-developed-by: Richard Weinberger Signed-off-by: Richard Weinberger Co-developed-by: David Oberhollenzer Signed-off-by: David Oberhollenzer Signed-off-by: David Gstir Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- Documentation/admin-guide/kernel-parameters.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 396137ee018d..fd2b74092c47 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6749,6 +6749,7 @@ - "tpm" - "tee" - "caam" + - "dcp" If not specified then it defaults to iterating through the trust source list starting with TPM and assigns the first trust source as a backend which is initialized @@ -6764,6 +6765,18 @@ If not specified, "default" is used. In this case, the RNG's choice is left to each individual trust source. + trusted.dcp_use_otp_key + This is intended to be used in combination with + trusted.source=dcp and will select the DCP OTP key + instead of the DCP UNIQUE key blob encryption. + + trusted.dcp_skip_zk_test + This is intended to be used in combination with + trusted.source=dcp and will disable the check if the + blob key is all zeros. This is helpful for situations where + having this key zero'ed is acceptable. E.g. in testing + scenarios. + tsc= Disable clocksource stability checks for TSC. Format: [x86] reliable: mark tsc clocksource as reliable, this From 28c5f596ae3d1790cdc96fa5fc7370f934abfb2e Mon Sep 17 00:00:00 2001 From: David Gstir Date: Wed, 3 Apr 2024 09:21:22 +0200 Subject: [PATCH 937/969] docs: trusted-encrypted: add DCP as new trust source Update the documentation for trusted and encrypted KEYS with DCP as new trust source: - Describe security properties of DCP trust source - Describe key usage - Document blob format Co-developed-by: Richard Weinberger Signed-off-by: Richard Weinberger Co-developed-by: David Oberhollenzer Signed-off-by: David Oberhollenzer Signed-off-by: David Gstir Reviewed-by: Jarkko Sakkinen Reviewed-by: Bagas Sanjaya Signed-off-by: Jarkko Sakkinen --- .../security/keys/trusted-encrypted.rst | 53 +++++++++++++++++++ security/keys/trusted-keys/trusted_dcp.c | 19 +++++++ 2 files changed, 72 insertions(+) diff --git a/Documentation/security/keys/trusted-encrypted.rst b/Documentation/security/keys/trusted-encrypted.rst index e989b9802f92..f4d7e162d5e4 100644 --- a/Documentation/security/keys/trusted-encrypted.rst +++ b/Documentation/security/keys/trusted-encrypted.rst @@ -42,6 +42,14 @@ safe. randomly generated and fused into each SoC at manufacturing time. Otherwise, a common fixed test key is used instead. + (4) DCP (Data Co-Processor: crypto accelerator of various i.MX SoCs) + + Rooted to a one-time programmable key (OTP) that is generally burnt + in the on-chip fuses and is accessible to the DCP encryption engine only. + DCP provides two keys that can be used as root of trust: the OTP key + and the UNIQUE key. Default is to use the UNIQUE key, but selecting + the OTP key can be done via a module parameter (dcp_use_otp_key). + * Execution isolation (1) TPM @@ -57,6 +65,12 @@ safe. Fixed set of operations running in isolated execution environment. + (4) DCP + + Fixed set of cryptographic operations running in isolated execution + environment. Only basic blob key encryption is executed there. + The actual key sealing/unsealing is done on main processor/kernel space. + * Optional binding to platform integrity state (1) TPM @@ -79,6 +93,11 @@ safe. Relies on the High Assurance Boot (HAB) mechanism of NXP SoCs for platform integrity. + (4) DCP + + Relies on Secure/Trusted boot process (called HAB by vendor) for + platform integrity. + * Interfaces and APIs (1) TPM @@ -94,6 +113,11 @@ safe. Interface is specific to silicon vendor. + (4) DCP + + Vendor-specific API that is implemented as part of the DCP crypto driver in + ``drivers/crypto/mxs-dcp.c``. + * Threat model The strength and appropriateness of a particular trust source for a given @@ -129,6 +153,13 @@ selected trust source: CAAM HWRNG, enable CRYPTO_DEV_FSL_CAAM_RNG_API and ensure the device is probed. + * DCP (Data Co-Processor: crypto accelerator of various i.MX SoCs) + + The DCP hardware device itself does not provide a dedicated RNG interface, + so the kernel default RNG is used. SoCs with DCP like the i.MX6ULL do have + a dedicated hardware RNG that is independent from DCP which can be enabled + to back the kernel RNG. + Users may override this by specifying ``trusted.rng=kernel`` on the kernel command-line to override the used RNG with the kernel's random number pool. @@ -231,6 +262,19 @@ Usage:: CAAM-specific format. The key length for new keys is always in bytes. Trusted Keys can be 32 - 128 bytes (256 - 1024 bits). +Trusted Keys usage: DCP +----------------------- + +Usage:: + + keyctl add trusted name "new keylen" ring + keyctl add trusted name "load hex_blob" ring + keyctl print keyid + +"keyctl print" returns an ASCII hex copy of the sealed key, which is in format +specific to this DCP key-blob implementation. The key length for new keys is +always in bytes. Trusted Keys can be 32 - 128 bytes (256 - 1024 bits). + Encrypted Keys usage -------------------- @@ -426,3 +470,12 @@ string length. privkey is the binary representation of TPM2B_PUBLIC excluding the initial TPM2B header which can be reconstructed from the ASN.1 octed string length. + +DCP Blob Format +--------------- + +.. kernel-doc:: security/keys/trusted-keys/trusted_dcp.c + :doc: dcp blob format + +.. kernel-doc:: security/keys/trusted-keys/trusted_dcp.c + :identifiers: struct dcp_blob_fmt diff --git a/security/keys/trusted-keys/trusted_dcp.c b/security/keys/trusted-keys/trusted_dcp.c index 16c44aafeab3..b5f81a05be36 100644 --- a/security/keys/trusted-keys/trusted_dcp.c +++ b/security/keys/trusted-keys/trusted_dcp.c @@ -19,6 +19,25 @@ #define DCP_BLOB_VERSION 1 #define DCP_BLOB_AUTHLEN 16 +/** + * DOC: dcp blob format + * + * The Data Co-Processor (DCP) provides hardware-bound AES keys using its + * AES encryption engine only. It does not provide direct key sealing/unsealing. + * To make DCP hardware encryption keys usable as trust source, we define + * our own custom format that uses a hardware-bound key to secure the sealing + * key stored in the key blob. + * + * Whenever a new trusted key using DCP is generated, we generate a random 128-bit + * blob encryption key (BEK) and 128-bit nonce. The BEK and nonce are used to + * encrypt the trusted key payload using AES-128-GCM. + * + * The BEK itself is encrypted using the hardware-bound key using the DCP's AES + * encryption engine with AES-128-ECB. The encrypted BEK, generated nonce, + * BEK-encrypted payload and authentication tag make up the blob format together + * with a version number, payload length and authentication tag. + */ + /** * struct dcp_blob_fmt - DCP BLOB format. * From db5b4f3253ff73bc2e926ec76e1c0f662b38d9a4 Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Thu, 2 May 2024 19:50:24 +0100 Subject: [PATCH 938/969] cgroup: Add documentation for missing zswap memory.stat This includes zswpin, zswpout and zswpwb. Signed-off-by: Usama Arif Acked-by: Nhat Pham Acked-by: Johannes Weiner Signed-off-by: Jonathan Corbet Message-ID: <20240502185307.3942173-2-usamaarif642@gmail.com> --- Documentation/admin-guide/cgroup-v2.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 17e6e9565156..eaf9e66e472a 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -1572,6 +1572,15 @@ PAGE_SIZE multiple when read back. pglazyfreed (npn) Amount of reclaimed lazyfree pages + zswpin + Number of pages moved in to memory from zswap. + + zswpout + Number of pages moved out of memory to zswap. + + zswpwb + Number of pages written from zswap to swap. + thp_fault_alloc (npn) Number of transparent hugepages which were allocated to satisfy a page fault. This counter is not present when CONFIG_TRANSPARENT_HUGEPAGE From 6155153601183061cbc54516f4db843cb80f2e02 Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Thu, 4 Apr 2024 12:58:40 +0200 Subject: [PATCH 939/969] char: tpm: handle HAS_IOPORT dependencies In a future patch HAS_IOPORT=n will disable inb()/outb() and friends at compile time. We thus need to add this dependency and ifdef sections of code using inb()/outb() as alternative access methods. Reviewed-by: Jarkko Sakkinen Co-developed-by: Arnd Bergmann Signed-off-by: Arnd Bergmann Signed-off-by: Niklas Schnelle Acked-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/Kconfig | 1 + drivers/char/tpm/tpm_infineon.c | 16 ++++++++++++---- drivers/char/tpm/tpm_tis_core.c | 19 ++++++++----------- 3 files changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index 927088b2c3d3..418c9ed59ffd 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -149,6 +149,7 @@ config TCG_NSC config TCG_ATMEL tristate "Atmel TPM Interface" depends on PPC64 || HAS_IOPORT_MAP + depends on HAS_IOPORT help If you have a TPM security chip from Atmel say Yes and it will be accessible from within Linux. To compile this driver diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c index 9c924a1440a9..99c6e565ec8d 100644 --- a/drivers/char/tpm/tpm_infineon.c +++ b/drivers/char/tpm/tpm_infineon.c @@ -26,7 +26,9 @@ #define TPM_MAX_TRIES 5000 #define TPM_INFINEON_DEV_VEN_VALUE 0x15D1 +#ifdef CONFIG_HAS_IOPORT #define TPM_INF_IO_PORT 0x0 +#endif #define TPM_INF_IO_MEM 0x1 #define TPM_INF_ADDR 0x0 @@ -51,34 +53,40 @@ static struct tpm_inf_dev tpm_dev; static inline void tpm_data_out(unsigned char data, unsigned char offset) { +#ifdef CONFIG_HAS_IOPORT if (tpm_dev.iotype == TPM_INF_IO_PORT) outb(data, tpm_dev.data_regs + offset); else +#endif writeb(data, tpm_dev.mem_base + tpm_dev.data_regs + offset); } static inline unsigned char tpm_data_in(unsigned char offset) { +#ifdef CONFIG_HAS_IOPORT if (tpm_dev.iotype == TPM_INF_IO_PORT) return inb(tpm_dev.data_regs + offset); - else - return readb(tpm_dev.mem_base + tpm_dev.data_regs + offset); +#endif + return readb(tpm_dev.mem_base + tpm_dev.data_regs + offset); } static inline void tpm_config_out(unsigned char data, unsigned char offset) { +#ifdef CONFIG_HAS_IOPORT if (tpm_dev.iotype == TPM_INF_IO_PORT) outb(data, tpm_dev.config_port + offset); else +#endif writeb(data, tpm_dev.mem_base + tpm_dev.index_off + offset); } static inline unsigned char tpm_config_in(unsigned char offset) { +#ifdef CONFIG_HAS_IOPORT if (tpm_dev.iotype == TPM_INF_IO_PORT) return inb(tpm_dev.config_port + offset); - else - return readb(tpm_dev.mem_base + tpm_dev.index_off + offset); +#endif + return readb(tpm_dev.mem_base + tpm_dev.index_off + offset); } /* TPM header definitions */ diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c index 714070ebb6e7..176cd8dbf1db 100644 --- a/drivers/char/tpm/tpm_tis_core.c +++ b/drivers/char/tpm/tpm_tis_core.c @@ -1057,11 +1057,6 @@ static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value) clkrun_val &= ~LPC_CLKRUN_EN; iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET); - /* - * Write any random value on port 0x80 which is on LPC, to make - * sure LPC clock is running before sending any TPM command. - */ - outb(0xCC, 0x80); } else { data->clkrun_enabled--; if (data->clkrun_enabled) @@ -1072,13 +1067,15 @@ static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value) /* Enable LPC CLKRUN# */ clkrun_val |= LPC_CLKRUN_EN; iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET); - - /* - * Write any random value on port 0x80 which is on LPC, to make - * sure LPC clock is running before sending any TPM command. - */ - outb(0xCC, 0x80); } + +#ifdef CONFIG_HAS_IOPORT + /* + * Write any random value on port 0x80 which is on LPC, to make + * sure LPC clock is running before sending any TPM command. + */ + outb(0xCC, 0x80); +#endif } static const struct tpm_class_ops tpm_tis = { From d14d2cc265d01960cc5af468b4e718f5c4585d97 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 11 Apr 2024 09:49:13 +0100 Subject: [PATCH 940/969] tpm/eventlog: remove redundant assignment to variabel ret Variable ret is being assigned and error code that is never read, it is either being re-assigned in an error exit path or never referenced again on the non-error path. The assignment is redundant and can be removed. Cleans up clang scan build warning: drivers/char/tpm/eventlog/acpi.c:145:2: warning: Value stored to 'ret' is never read [deadcode.DeadStores] Signed-off-by: Colin Ian King Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/eventlog/acpi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/char/tpm/eventlog/acpi.c b/drivers/char/tpm/eventlog/acpi.c index bd757d836c5c..69533d0bfb51 100644 --- a/drivers/char/tpm/eventlog/acpi.c +++ b/drivers/char/tpm/eventlog/acpi.c @@ -142,7 +142,6 @@ int tpm_read_log_acpi(struct tpm_chip *chip) log->bios_event_log_end = log->bios_event_log + len; - ret = -EIO; virt = acpi_os_map_iomem(start, len); if (!virt) { dev_warn(&chip->dev, "%s: Failed to map ACPI memory\n", __func__); From 8a55256a8462480a42c0c18b58d374dfd053f89f Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Tue, 9 Apr 2024 22:08:47 +0300 Subject: [PATCH 941/969] Documentation: tpm_tis Based recent discussions on LKML, provide preliminary bits of tpm_tis_core dependent drivers. Includes only bare essentials but can be extended later on case by case. This way some people may even want to read it later on. Reviewed-by: Bagas Sanjaya Signed-off-by: Jarkko Sakkinen --- Documentation/security/tpm/index.rst | 1 + Documentation/security/tpm/tpm_tis.rst | 46 ++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 Documentation/security/tpm/tpm_tis.rst diff --git a/Documentation/security/tpm/index.rst b/Documentation/security/tpm/index.rst index fc40e9f23c85..f27a17f60a96 100644 --- a/Documentation/security/tpm/index.rst +++ b/Documentation/security/tpm/index.rst @@ -5,6 +5,7 @@ Trusted Platform Module documentation .. toctree:: tpm_event_log + tpm_tis tpm_vtpm_proxy xen-tpmfront tpm_ftpm_tee diff --git a/Documentation/security/tpm/tpm_tis.rst b/Documentation/security/tpm/tpm_tis.rst new file mode 100644 index 000000000000..b9637f295638 --- /dev/null +++ b/Documentation/security/tpm/tpm_tis.rst @@ -0,0 +1,46 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================= +TPM FIFO interface driver +========================= + +TCG PTP Specification defines two interface types: FIFO and CRB. The former is +based on sequenced read and write operations, and the latter is based on a +buffer containing the full command or response. + +FIFO (First-In-First-Out) interface is used by the tpm_tis_core dependent +drivers. Originally Linux had only a driver called tpm_tis, which covered +memory mapped (aka MMIO) interface but it was later on extended to cover other +physical interfaces supported by the TCG standard. + +For historical reasons above the original MMIO driver is called tpm_tis and the +framework for FIFO drivers is named as tpm_tis_core. The postfix "tis" in +tpm_tis comes from the TPM Interface Specification, which is the hardware +interface specification for TPM 1.x chips. + +Communication is based on a 20 KiB buffer shared by the TPM chip through a +hardware bus or memory map, depending on the physical wiring. The buffer is +further split into five equal-size 4 KiB buffers, which provide equivalent +sets of registers for communication between the CPU and TPM. These +communication endpoints are called localities in the TCG terminology. + +When the kernel wants to send commands to the TPM chip, it first reserves +locality 0 by setting the requestUse bit in the TPM_ACCESS register. The bit is +cleared by the chip when the access is granted. Once it completes its +communication, the kernel writes the TPM_ACCESS.activeLocality bit. This +informs the chip that the locality has been relinquished. + +Pending localities are served in order by the chip in descending order, one at +a time: + +- Locality 0 has the lowest priority. +- Locality 5 has the highest priority. + +Further information on the purpose and meaning of the localities can be found +in section 3.2 of the TCG PC Client Platform TPM Profile Specification. + +References +========== + +TCG PC Client Platform TPM Profile (PTP) Specification +https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/ From 45121fcbe7d200c1269804b5e191ce788fdc8364 Mon Sep 17 00:00:00 2001 From: Michael Haener Date: Sun, 14 Apr 2024 09:44:34 +0200 Subject: [PATCH 942/969] dt-bindings: tpm: Add st,st33ktpm2xi2c Add the ST chip st33ktpm2xi2c to the supported compatible strings of the TPM TIS I2C schema. The Chip is compliant with the TCG PC Client TPM Profile specification. For reference, a datasheet is available at: https://www.st.com/resource/en/data_brief/st33ktpm2xi2c.pdf Reviewed-by: Alexander Sverdlin Signed-off-by: Michael Haener Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml index 3ab4434b7352..af7720dc4a12 100644 --- a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml +++ b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml @@ -32,6 +32,7 @@ properties: - enum: - infineon,slb9673 - nuvoton,npct75x + - st,st33ktpm2xi2c - const: tcg,tpm-tis-i2c - description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface From 8516b23aa212a3ed6f6052418e66f22a83c7ee74 Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Mon, 22 Apr 2024 14:37:11 +0200 Subject: [PATCH 943/969] char: tpm: Keep TPM_INF_IO_PORT define for HAS_IOPORT=n The recent change to handle HAS_IOPORT removed the TPM_INF_IO_PORT define for the HAS_IOPORT=n case despite the define being used in sections of code not covered by the same ifdef check. This was missed because at the moment TCG_INFINEON indirectly depends on HAS_IOPORT via PNP which depends on ACPI || ISA. As TCG_INFINEON does in principle support MMIO only use add it for COMPILE_TEST to cover the HAS_IOPORT=n case. Link: https://lore.kernel.org/lkml/9d9fa267-067e-421b-9a39-aa178b913298@app.fastmail.com/ Fixes: dab56f80e7f9 ("char: tpm: handle HAS_IOPORT dependencies") Signed-off-by: Niklas Schnelle Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/Kconfig | 2 +- drivers/char/tpm/tpm_infineon.c | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index 418c9ed59ffd..852bb9344788 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -157,7 +157,7 @@ config TCG_ATMEL config TCG_INFINEON tristate "Infineon Technologies TPM Interface" - depends on PNP + depends on PNP || COMPILE_TEST help If you have a TPM security chip from Infineon Technologies (either SLD 9630 TT 1.1 or SLB 9635 TT 1.2) say Yes and it diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c index 99c6e565ec8d..2d2ae37153ba 100644 --- a/drivers/char/tpm/tpm_infineon.c +++ b/drivers/char/tpm/tpm_infineon.c @@ -26,9 +26,7 @@ #define TPM_MAX_TRIES 5000 #define TPM_INFINEON_DEV_VEN_VALUE 0x15D1 -#ifdef CONFIG_HAS_IOPORT #define TPM_INF_IO_PORT 0x0 -#endif #define TPM_INF_IO_MEM 0x1 #define TPM_INF_ADDR 0x0 From cf792e903affdf585f20fea41ea4f9b4eac124ab Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:50 -0400 Subject: [PATCH 944/969] tpm: Remove unused tpm_buf_tag() The helper function has no call sites. Thus, remove it. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- include/linux/tpm.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 4ee9d13749ad..6588ca87cf93 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -358,13 +358,6 @@ static inline u32 tpm_buf_length(struct tpm_buf *buf) return be32_to_cpu(head->length); } -static inline u16 tpm_buf_tag(struct tpm_buf *buf) -{ - struct tpm_header *head = (struct tpm_header *)buf->data; - - return be16_to_cpu(head->tag); -} - static inline void tpm_buf_append(struct tpm_buf *buf, const unsigned char *new_data, unsigned int new_len) From 4f0feb5463cc6783c9145e707f93c54e7bb1112e Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:51 -0400 Subject: [PATCH 945/969] tpm: Remove tpm_send() Open code the last remaining call site for tpm_send(). Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-interface.c | 25 ----------------------- include/linux/tpm.h | 5 ----- security/keys/trusted-keys/trusted_tpm1.c | 14 +++++++++++-- 3 files changed, 12 insertions(+), 32 deletions(-) diff --git a/drivers/char/tpm/tpm-interface.c b/drivers/char/tpm/tpm-interface.c index 757336324c90..f940045a014e 100644 --- a/drivers/char/tpm/tpm-interface.c +++ b/drivers/char/tpm/tpm-interface.c @@ -342,31 +342,6 @@ out: } EXPORT_SYMBOL_GPL(tpm_pcr_extend); -/** - * tpm_send - send a TPM command - * @chip: a &struct tpm_chip instance, %NULL for the default chip - * @cmd: a TPM command buffer - * @buflen: the length of the TPM command buffer - * - * Return: same as with tpm_transmit_cmd() - */ -int tpm_send(struct tpm_chip *chip, void *cmd, size_t buflen) -{ - struct tpm_buf buf; - int rc; - - chip = tpm_find_get_ops(chip); - if (!chip) - return -ENODEV; - - buf.data = cmd; - rc = tpm_transmit_cmd(chip, &buf, 0, "attempting to a send a command"); - - tpm_put_ops(chip); - return rc; -} -EXPORT_SYMBOL_GPL(tpm_send); - int tpm_auto_startup(struct tpm_chip *chip) { int rc; diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 6588ca87cf93..d9d645e9c52c 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -422,7 +422,6 @@ extern int tpm_pcr_read(struct tpm_chip *chip, u32 pcr_idx, struct tpm_digest *digest); extern int tpm_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, struct tpm_digest *digests); -extern int tpm_send(struct tpm_chip *chip, void *cmd, size_t buflen); extern int tpm_get_random(struct tpm_chip *chip, u8 *data, size_t max); extern struct tpm_chip *tpm_default_chip(void); void tpm2_flush_context(struct tpm_chip *chip, u32 handle); @@ -443,10 +442,6 @@ static inline int tpm_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, return -ENODEV; } -static inline int tpm_send(struct tpm_chip *chip, void *cmd, size_t buflen) -{ - return -ENODEV; -} static inline int tpm_get_random(struct tpm_chip *chip, u8 *data, size_t max) { return -ENODEV; diff --git a/security/keys/trusted-keys/trusted_tpm1.c b/security/keys/trusted-keys/trusted_tpm1.c index aa108bea6739..37bce84eef99 100644 --- a/security/keys/trusted-keys/trusted_tpm1.c +++ b/security/keys/trusted-keys/trusted_tpm1.c @@ -356,17 +356,27 @@ out: */ int trusted_tpm_send(unsigned char *cmd, size_t buflen) { + struct tpm_buf buf; int rc; if (!chip) return -ENODEV; + rc = tpm_try_get_ops(chip); + if (rc) + return rc; + + buf.flags = 0; + buf.data = cmd; dump_tpm_buf(cmd); - rc = tpm_send(chip, cmd, buflen); + rc = tpm_transmit_cmd(chip, &buf, 4, "sending data"); dump_tpm_buf(cmd); + if (rc > 0) - /* Can't return positive return codes values to keyctl */ + /* TPM error */ rc = -EPERM; + + tpm_put_ops(chip); return rc; } EXPORT_SYMBOL_GPL(trusted_tpm_send); From 17d89b2e2f76e8ae129467665ea7462401f37aa4 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:27:52 -0400 Subject: [PATCH 946/969] tpm: Move buffer handling from static inlines to real functions separate out the tpm_buf_... handling functions from static inlines in tpm.h and move them to their own tpm-buf.c file. This is a precursor to adding new functions for other TPM type handling because the amount of code will grow from the current 70 lines in tpm.h to about 200 lines when the additions are done. 200 lines of inline functions is a bit too much to keep in a header file. Signed-off-by: James Bottomley Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm-buf.c | 87 ++++++++++++++++++++++++++++++++++++++ include/linux/tpm.h | 80 ++++------------------------------- 3 files changed, 97 insertions(+), 71 deletions(-) create mode 100644 drivers/char/tpm/tpm-buf.c diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index 0222b1ddb310..ad3594e383e1 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -15,6 +15,7 @@ tpm-y += tpm-sysfs.o tpm-y += eventlog/common.o tpm-y += eventlog/tpm1.o tpm-y += eventlog/tpm2.o +tpm-y += tpm-buf.o tpm-$(CONFIG_ACPI) += tpm_ppi.o eventlog/acpi.o tpm-$(CONFIG_EFI) += eventlog/efi.o diff --git a/drivers/char/tpm/tpm-buf.c b/drivers/char/tpm/tpm-buf.c new file mode 100644 index 000000000000..96cee41d5b9c --- /dev/null +++ b/drivers/char/tpm/tpm-buf.c @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Handling of TPM command and other buffers. + */ + +#include +#include + +int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal) +{ + buf->data = (u8 *)__get_free_page(GFP_KERNEL); + if (!buf->data) + return -ENOMEM; + + buf->flags = 0; + tpm_buf_reset(buf, tag, ordinal); + return 0; +} +EXPORT_SYMBOL_GPL(tpm_buf_init); + +void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + + head->tag = cpu_to_be16(tag); + head->length = cpu_to_be32(sizeof(*head)); + head->ordinal = cpu_to_be32(ordinal); +} +EXPORT_SYMBOL_GPL(tpm_buf_reset); + +void tpm_buf_destroy(struct tpm_buf *buf) +{ + free_page((unsigned long)buf->data); +} +EXPORT_SYMBOL_GPL(tpm_buf_destroy); + +u32 tpm_buf_length(struct tpm_buf *buf) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + + return be32_to_cpu(head->length); +} +EXPORT_SYMBOL_GPL(tpm_buf_length); + +void tpm_buf_append(struct tpm_buf *buf, + const unsigned char *new_data, + unsigned int new_len) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + u32 len = tpm_buf_length(buf); + + /* Return silently if overflow has already happened. */ + if (buf->flags & TPM_BUF_OVERFLOW) + return; + + if ((len + new_len) > PAGE_SIZE) { + WARN(1, "tpm_buf: overflow\n"); + buf->flags |= TPM_BUF_OVERFLOW; + return; + } + + memcpy(&buf->data[len], new_data, new_len); + head->length = cpu_to_be32(len + new_len); +} +EXPORT_SYMBOL_GPL(tpm_buf_append); + +void tpm_buf_append_u8(struct tpm_buf *buf, const u8 value) +{ + tpm_buf_append(buf, &value, 1); +} +EXPORT_SYMBOL_GPL(tpm_buf_append_u8); + +void tpm_buf_append_u16(struct tpm_buf *buf, const u16 value) +{ + __be16 value2 = cpu_to_be16(value); + + tpm_buf_append(buf, (u8 *)&value2, 2); +} +EXPORT_SYMBOL_GPL(tpm_buf_append_u16); + +void tpm_buf_append_u32(struct tpm_buf *buf, const u32 value) +{ + __be32 value2 = cpu_to_be32(value); + + tpm_buf_append(buf, (u8 *)&value2, 4); +} +EXPORT_SYMBOL_GPL(tpm_buf_append_u32); diff --git a/include/linux/tpm.h b/include/linux/tpm.h index d9d645e9c52c..bb0e8718a432 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -326,77 +326,15 @@ struct tpm2_hash { unsigned int tpm_id; }; -static inline void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal) -{ - struct tpm_header *head = (struct tpm_header *)buf->data; - - head->tag = cpu_to_be16(tag); - head->length = cpu_to_be32(sizeof(*head)); - head->ordinal = cpu_to_be32(ordinal); -} - -static inline int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal) -{ - buf->data = (u8 *)__get_free_page(GFP_KERNEL); - if (!buf->data) - return -ENOMEM; - - buf->flags = 0; - tpm_buf_reset(buf, tag, ordinal); - return 0; -} - -static inline void tpm_buf_destroy(struct tpm_buf *buf) -{ - free_page((unsigned long)buf->data); -} - -static inline u32 tpm_buf_length(struct tpm_buf *buf) -{ - struct tpm_header *head = (struct tpm_header *)buf->data; - - return be32_to_cpu(head->length); -} - -static inline void tpm_buf_append(struct tpm_buf *buf, - const unsigned char *new_data, - unsigned int new_len) -{ - struct tpm_header *head = (struct tpm_header *)buf->data; - u32 len = tpm_buf_length(buf); - - /* Return silently if overflow has already happened. */ - if (buf->flags & TPM_BUF_OVERFLOW) - return; - - if ((len + new_len) > PAGE_SIZE) { - WARN(1, "tpm_buf: overflow\n"); - buf->flags |= TPM_BUF_OVERFLOW; - return; - } - - memcpy(&buf->data[len], new_data, new_len); - head->length = cpu_to_be32(len + new_len); -} - -static inline void tpm_buf_append_u8(struct tpm_buf *buf, const u8 value) -{ - tpm_buf_append(buf, &value, 1); -} - -static inline void tpm_buf_append_u16(struct tpm_buf *buf, const u16 value) -{ - __be16 value2 = cpu_to_be16(value); - - tpm_buf_append(buf, (u8 *) &value2, 2); -} - -static inline void tpm_buf_append_u32(struct tpm_buf *buf, const u32 value) -{ - __be32 value2 = cpu_to_be32(value); - - tpm_buf_append(buf, (u8 *) &value2, 4); -} +int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal); +void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal); +void tpm_buf_destroy(struct tpm_buf *buf); +u32 tpm_buf_length(struct tpm_buf *buf); +void tpm_buf_append(struct tpm_buf *buf, const unsigned char *new_data, + unsigned int new_len); +void tpm_buf_append_u8(struct tpm_buf *buf, const u8 value); +void tpm_buf_append_u16(struct tpm_buf *buf, const u16 value); +void tpm_buf_append_u32(struct tpm_buf *buf, const u32 value); /* * Check if TPM device is in the firmware upgrade mode. From 37e2ee16d67d17926085cbd0500dd78ca747e59c Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:53 -0400 Subject: [PATCH 947/969] tpm: Update struct tpm_buf documentation comments Remove deprecated portions and document enum values. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- include/linux/tpm.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/include/linux/tpm.h b/include/linux/tpm.h index bb0e8718a432..0a8c1351adc2 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -297,15 +297,14 @@ struct tpm_header { }; } __packed; -/* A string buffer type for constructing TPM commands. This is based on the - * ideas of string buffer code in security/keys/trusted.h but is heap based - * in order to keep the stack usage minimal. - */ - enum tpm_buf_flags { + /* the capacity exceeded: */ TPM_BUF_OVERFLOW = BIT(0), }; +/* + * A string buffer type for constructing TPM commands. + */ struct tpm_buf { unsigned int flags; u8 *data; From e1b72e1b11109bd81577950538a17bc0428e647f Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:54 -0400 Subject: [PATCH 948/969] tpm: Store the length of the tpm_buf data separately. TPM2B buffers, or sized buffers, have a two byte header, which contains the length of the payload as a 16-bit big-endian number, without counting in the space taken by the header. This differs from encoding in the TPM header where the length includes also the bytes taken by the header. Unbound the length of a tpm_buf from the value stored to the TPM command header. A separate encoding and decoding step so that different buffer types can be supported, with variant header format and length encoding. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-buf.c | 49 ++++++++++++++++++----- drivers/char/tpm/tpm-interface.c | 1 + include/keys/trusted_tpm.h | 2 - include/linux/tpm.h | 6 +-- security/keys/trusted-keys/trusted_tpm1.c | 9 +++-- 5 files changed, 47 insertions(+), 20 deletions(-) diff --git a/drivers/char/tpm/tpm-buf.c b/drivers/char/tpm/tpm-buf.c index 96cee41d5b9c..2f2710ca6f6d 100644 --- a/drivers/char/tpm/tpm-buf.c +++ b/drivers/char/tpm/tpm-buf.c @@ -3,25 +3,44 @@ * Handling of TPM command and other buffers. */ +#include #include #include +/** + * tpm_buf_init() - Allocate and initialize a TPM command + * @buf: A &tpm_buf + * @tag: TPM_TAG_RQU_COMMAND, TPM2_ST_NO_SESSIONS or TPM2_ST_SESSIONS + * @ordinal: A command ordinal + * + * Return: 0 or -ENOMEM + */ int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal) { buf->data = (u8 *)__get_free_page(GFP_KERNEL); if (!buf->data) return -ENOMEM; - buf->flags = 0; tpm_buf_reset(buf, tag, ordinal); return 0; } EXPORT_SYMBOL_GPL(tpm_buf_init); +/** + * tpm_buf_reset() - Initialize a TPM command + * @buf: A &tpm_buf + * @tag: TPM_TAG_RQU_COMMAND, TPM2_ST_NO_SESSIONS or TPM2_ST_SESSIONS + * @ordinal: A command ordinal + */ void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal) { struct tpm_header *head = (struct tpm_header *)buf->data; + WARN_ON(tag != TPM_TAG_RQU_COMMAND && tag != TPM2_ST_NO_SESSIONS && + tag != TPM2_ST_SESSIONS && tag != 0); + + buf->flags = 0; + buf->length = sizeof(*head); head->tag = cpu_to_be16(tag); head->length = cpu_to_be32(sizeof(*head)); head->ordinal = cpu_to_be32(ordinal); @@ -34,33 +53,41 @@ void tpm_buf_destroy(struct tpm_buf *buf) } EXPORT_SYMBOL_GPL(tpm_buf_destroy); +/** + * tpm_buf_length() - Return the number of bytes consumed by the data + * @buf: A &tpm_buf + * + * Return: The number of bytes consumed by the buffer + */ u32 tpm_buf_length(struct tpm_buf *buf) { - struct tpm_header *head = (struct tpm_header *)buf->data; - - return be32_to_cpu(head->length); + return buf->length; } EXPORT_SYMBOL_GPL(tpm_buf_length); -void tpm_buf_append(struct tpm_buf *buf, - const unsigned char *new_data, - unsigned int new_len) +/** + * tpm_buf_append() - Append data to an initialized buffer + * @buf: A &tpm_buf + * @new_data: A data blob + * @new_length: Size of the appended data + */ +void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length) { struct tpm_header *head = (struct tpm_header *)buf->data; - u32 len = tpm_buf_length(buf); /* Return silently if overflow has already happened. */ if (buf->flags & TPM_BUF_OVERFLOW) return; - if ((len + new_len) > PAGE_SIZE) { + if ((buf->length + new_length) > PAGE_SIZE) { WARN(1, "tpm_buf: overflow\n"); buf->flags |= TPM_BUF_OVERFLOW; return; } - memcpy(&buf->data[len], new_data, new_len); - head->length = cpu_to_be32(len + new_len); + memcpy(&buf->data[buf->length], new_data, new_length); + buf->length += new_length; + head->length = cpu_to_be32(buf->length); } EXPORT_SYMBOL_GPL(tpm_buf_append); diff --git a/drivers/char/tpm/tpm-interface.c b/drivers/char/tpm/tpm-interface.c index f940045a014e..5da134f12c9a 100644 --- a/drivers/char/tpm/tpm-interface.c +++ b/drivers/char/tpm/tpm-interface.c @@ -232,6 +232,7 @@ ssize_t tpm_transmit_cmd(struct tpm_chip *chip, struct tpm_buf *buf, if (len < min_rsp_body_length + TPM_HEADER_SIZE) return -EFAULT; + buf->length = len; return 0; } EXPORT_SYMBOL_GPL(tpm_transmit_cmd); diff --git a/include/keys/trusted_tpm.h b/include/keys/trusted_tpm.h index 7769b726863a..a088b33fd0e3 100644 --- a/include/keys/trusted_tpm.h +++ b/include/keys/trusted_tpm.h @@ -6,8 +6,6 @@ #include /* implementation specific TPM constants */ -#define MAX_BUF_SIZE 1024 -#define TPM_GETRANDOM_SIZE 14 #define TPM_SIZE_OFFSET 2 #define TPM_RETURN_OFFSET 6 #define TPM_DATA_OFFSET 10 diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 0a8c1351adc2..1d7b39b5c383 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -306,7 +306,8 @@ enum tpm_buf_flags { * A string buffer type for constructing TPM commands. */ struct tpm_buf { - unsigned int flags; + u32 flags; + u32 length; u8 *data; }; @@ -329,8 +330,7 @@ int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal); void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal); void tpm_buf_destroy(struct tpm_buf *buf); u32 tpm_buf_length(struct tpm_buf *buf); -void tpm_buf_append(struct tpm_buf *buf, const unsigned char *new_data, - unsigned int new_len); +void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length); void tpm_buf_append_u8(struct tpm_buf *buf, const u8 value); void tpm_buf_append_u16(struct tpm_buf *buf, const u16 value); void tpm_buf_append_u32(struct tpm_buf *buf, const u32 value); diff --git a/security/keys/trusted-keys/trusted_tpm1.c b/security/keys/trusted-keys/trusted_tpm1.c index 37bce84eef99..89c9798d1800 100644 --- a/security/keys/trusted-keys/trusted_tpm1.c +++ b/security/keys/trusted-keys/trusted_tpm1.c @@ -367,6 +367,7 @@ int trusted_tpm_send(unsigned char *cmd, size_t buflen) return rc; buf.flags = 0; + buf.length = buflen; buf.data = cmd; dump_tpm_buf(cmd); rc = tpm_transmit_cmd(chip, &buf, 4, "sending data"); @@ -417,7 +418,7 @@ static int osap(struct tpm_buf *tb, struct osapsess *s, tpm_buf_append_u32(tb, handle); tpm_buf_append(tb, ononce, TPM_NONCE_SIZE); - ret = trusted_tpm_send(tb->data, MAX_BUF_SIZE); + ret = trusted_tpm_send(tb->data, tb->length); if (ret < 0) return ret; @@ -441,7 +442,7 @@ int oiap(struct tpm_buf *tb, uint32_t *handle, unsigned char *nonce) return -ENODEV; tpm_buf_reset(tb, TPM_TAG_RQU_COMMAND, TPM_ORD_OIAP); - ret = trusted_tpm_send(tb->data, MAX_BUF_SIZE); + ret = trusted_tpm_send(tb->data, tb->length); if (ret < 0) return ret; @@ -553,7 +554,7 @@ static int tpm_seal(struct tpm_buf *tb, uint16_t keytype, tpm_buf_append_u8(tb, cont); tpm_buf_append(tb, td->pubauth, SHA1_DIGEST_SIZE); - ret = trusted_tpm_send(tb->data, MAX_BUF_SIZE); + ret = trusted_tpm_send(tb->data, tb->length); if (ret < 0) goto out; @@ -644,7 +645,7 @@ static int tpm_unseal(struct tpm_buf *tb, tpm_buf_append_u8(tb, cont); tpm_buf_append(tb, authdata2, SHA1_DIGEST_SIZE); - ret = trusted_tpm_send(tb->data, MAX_BUF_SIZE); + ret = trusted_tpm_send(tb->data, tb->length); if (ret < 0) { pr_info("authhmac failed (%d)\n", ret); return ret; From d926ee92e84146ff85877b15d9ac0c7cd7c422c6 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:55 -0400 Subject: [PATCH 949/969] tpm: TPM2B formatted buffers Declare tpm_buf_init_sized() and tpm_buf_reset_sized() for creating TPM2B formatted buffers. These buffers are also known as sized buffers in the specifications and literature. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-buf.c | 38 +++++++++++++++++++++++++++++++++++--- include/linux/tpm.h | 4 ++++ 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/char/tpm/tpm-buf.c b/drivers/char/tpm/tpm-buf.c index 2f2710ca6f6d..d679dc1cecc7 100644 --- a/drivers/char/tpm/tpm-buf.c +++ b/drivers/char/tpm/tpm-buf.c @@ -47,6 +47,36 @@ void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal) } EXPORT_SYMBOL_GPL(tpm_buf_reset); +/** + * tpm_buf_init_sized() - Allocate and initialize a sized (TPM2B) buffer + * @buf: A @tpm_buf + * + * Return: 0 or -ENOMEM + */ +int tpm_buf_init_sized(struct tpm_buf *buf) +{ + buf->data = (u8 *)__get_free_page(GFP_KERNEL); + if (!buf->data) + return -ENOMEM; + + tpm_buf_reset_sized(buf); + return 0; +} +EXPORT_SYMBOL_GPL(tpm_buf_init_sized); + +/** + * tpm_buf_reset_sized() - Initialize a sized buffer + * @buf: A &tpm_buf + */ +void tpm_buf_reset_sized(struct tpm_buf *buf) +{ + buf->flags = TPM_BUF_TPM2B; + buf->length = 2; + buf->data[0] = 0; + buf->data[1] = 0; +} +EXPORT_SYMBOL_GPL(tpm_buf_reset_sized); + void tpm_buf_destroy(struct tpm_buf *buf) { free_page((unsigned long)buf->data); @@ -73,8 +103,6 @@ EXPORT_SYMBOL_GPL(tpm_buf_length); */ void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length) { - struct tpm_header *head = (struct tpm_header *)buf->data; - /* Return silently if overflow has already happened. */ if (buf->flags & TPM_BUF_OVERFLOW) return; @@ -87,7 +115,11 @@ void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length) memcpy(&buf->data[buf->length], new_data, new_length); buf->length += new_length; - head->length = cpu_to_be32(buf->length); + + if (buf->flags & TPM_BUF_TPM2B) + ((__be16 *)buf->data)[0] = cpu_to_be16(buf->length - 2); + else + ((struct tpm_header *)buf->data)->length = cpu_to_be32(buf->length); } EXPORT_SYMBOL_GPL(tpm_buf_append); diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 1d7b39b5c383..715db4a91c1f 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -300,6 +300,8 @@ struct tpm_header { enum tpm_buf_flags { /* the capacity exceeded: */ TPM_BUF_OVERFLOW = BIT(0), + /* TPM2B format: */ + TPM_BUF_TPM2B = BIT(1), }; /* @@ -328,6 +330,8 @@ struct tpm2_hash { int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal); void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal); +int tpm_buf_init_sized(struct tpm_buf *buf); +void tpm_buf_reset_sized(struct tpm_buf *buf); void tpm_buf_destroy(struct tpm_buf *buf); u32 tpm_buf_length(struct tpm_buf *buf); void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length); From acd5eb4f50241c5e3c2e0056c0e2151295796416 Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:56 -0400 Subject: [PATCH 950/969] tpm: Add tpm_buf_read_{u8,u16,u32} Declare reader functions for the instances of struct tpm_buf. If the read goes out of boundary, TPM_BUF_BOUNDARY_ERROR is set, and subsequent read will do nothing. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-buf.c | 79 +++++++++++++++++++++++++++++++++++++- include/linux/tpm.h | 5 +++ 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/char/tpm/tpm-buf.c b/drivers/char/tpm/tpm-buf.c index d679dc1cecc7..cc14fa3fd8c2 100644 --- a/drivers/char/tpm/tpm-buf.c +++ b/drivers/char/tpm/tpm-buf.c @@ -108,7 +108,7 @@ void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length) return; if ((buf->length + new_length) > PAGE_SIZE) { - WARN(1, "tpm_buf: overflow\n"); + WARN(1, "tpm_buf: write overflow\n"); buf->flags |= TPM_BUF_OVERFLOW; return; } @@ -144,3 +144,80 @@ void tpm_buf_append_u32(struct tpm_buf *buf, const u32 value) tpm_buf_append(buf, (u8 *)&value2, 4); } EXPORT_SYMBOL_GPL(tpm_buf_append_u32); + +/** + * tpm_buf_read() - Read from a TPM buffer + * @buf: &tpm_buf instance + * @offset: offset within the buffer + * @count: the number of bytes to read + * @output: the output buffer + */ +static void tpm_buf_read(struct tpm_buf *buf, off_t *offset, size_t count, void *output) +{ + off_t next_offset; + + /* Return silently if overflow has already happened. */ + if (buf->flags & TPM_BUF_BOUNDARY_ERROR) + return; + + next_offset = *offset + count; + if (next_offset > buf->length) { + WARN(1, "tpm_buf: read out of boundary\n"); + buf->flags |= TPM_BUF_BOUNDARY_ERROR; + return; + } + + memcpy(output, &buf->data[*offset], count); + *offset = next_offset; +} + +/** + * tpm_buf_read_u8() - Read 8-bit word from a TPM buffer + * @buf: &tpm_buf instance + * @offset: offset within the buffer + * + * Return: next 8-bit word + */ +u8 tpm_buf_read_u8(struct tpm_buf *buf, off_t *offset) +{ + u8 value; + + tpm_buf_read(buf, offset, sizeof(value), &value); + + return value; +} +EXPORT_SYMBOL_GPL(tpm_buf_read_u8); + +/** + * tpm_buf_read_u16() - Read 16-bit word from a TPM buffer + * @buf: &tpm_buf instance + * @offset: offset within the buffer + * + * Return: next 16-bit word + */ +u16 tpm_buf_read_u16(struct tpm_buf *buf, off_t *offset) +{ + u16 value; + + tpm_buf_read(buf, offset, sizeof(value), &value); + + return be16_to_cpu(value); +} +EXPORT_SYMBOL_GPL(tpm_buf_read_u16); + +/** + * tpm_buf_read_u32() - Read 32-bit word from a TPM buffer + * @buf: &tpm_buf instance + * @offset: offset within the buffer + * + * Return: next 32-bit word + */ +u32 tpm_buf_read_u32(struct tpm_buf *buf, off_t *offset) +{ + u32 value; + + tpm_buf_read(buf, offset, sizeof(value), &value); + + return be32_to_cpu(value); +} +EXPORT_SYMBOL_GPL(tpm_buf_read_u32); diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 715db4a91c1f..e8172f81c562 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -302,6 +302,8 @@ enum tpm_buf_flags { TPM_BUF_OVERFLOW = BIT(0), /* TPM2B format: */ TPM_BUF_TPM2B = BIT(1), + /* read out of boundary: */ + TPM_BUF_BOUNDARY_ERROR = BIT(2), }; /* @@ -338,6 +340,9 @@ void tpm_buf_append(struct tpm_buf *buf, const u8 *new_data, u16 new_length); void tpm_buf_append_u8(struct tpm_buf *buf, const u8 value); void tpm_buf_append_u16(struct tpm_buf *buf, const u16 value); void tpm_buf_append_u32(struct tpm_buf *buf, const u32 value); +u8 tpm_buf_read_u8(struct tpm_buf *buf, off_t *offset); +u16 tpm_buf_read_u16(struct tpm_buf *buf, off_t *offset); +u32 tpm_buf_read_u32(struct tpm_buf *buf, off_t *offset); /* * Check if TPM device is in the firmware upgrade mode. From 40813f1879e7b7d33bf70bcd67fb443e8e52247b Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Mon, 29 Apr 2024 16:27:57 -0400 Subject: [PATCH 951/969] KEYS: trusted: tpm2: Use struct tpm_buf for sized buffers Take advantage of the new sized buffer (TPM2B) mode of struct tpm_buf in tpm2_seal_trusted(). This allows to add robustness to the command construction without requiring to calculate buffer sizes manually. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- security/keys/trusted-keys/trusted_tpm2.c | 54 +++++++++++++---------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/security/keys/trusted-keys/trusted_tpm2.c b/security/keys/trusted-keys/trusted_tpm2.c index bc700f85f80b..97b1dfca2dba 100644 --- a/security/keys/trusted-keys/trusted_tpm2.c +++ b/security/keys/trusted-keys/trusted_tpm2.c @@ -228,8 +228,9 @@ int tpm2_seal_trusted(struct tpm_chip *chip, struct trusted_key_payload *payload, struct trusted_key_options *options) { + off_t offset = TPM_HEADER_SIZE; + struct tpm_buf buf, sized; int blob_len = 0; - struct tpm_buf buf; u32 hash; u32 flags; int i; @@ -258,6 +259,14 @@ int tpm2_seal_trusted(struct tpm_chip *chip, return rc; } + rc = tpm_buf_init_sized(&sized); + if (rc) { + tpm_buf_destroy(&buf); + tpm_put_ops(chip); + return rc; + } + + tpm_buf_reset(&buf, TPM2_ST_SESSIONS, TPM2_CC_CREATE); tpm_buf_append_u32(&buf, options->keyhandle); tpm2_buf_append_auth(&buf, TPM2_RS_PW, NULL /* nonce */, 0, @@ -266,36 +275,36 @@ int tpm2_seal_trusted(struct tpm_chip *chip, TPM_DIGEST_SIZE); /* sensitive */ - tpm_buf_append_u16(&buf, 4 + options->blobauth_len + payload->key_len); + tpm_buf_append_u16(&sized, options->blobauth_len); - tpm_buf_append_u16(&buf, options->blobauth_len); if (options->blobauth_len) - tpm_buf_append(&buf, options->blobauth, options->blobauth_len); + tpm_buf_append(&sized, options->blobauth, options->blobauth_len); - tpm_buf_append_u16(&buf, payload->key_len); - tpm_buf_append(&buf, payload->key, payload->key_len); + tpm_buf_append_u16(&sized, payload->key_len); + tpm_buf_append(&sized, payload->key, payload->key_len); + tpm_buf_append(&buf, sized.data, sized.length); /* public */ - tpm_buf_append_u16(&buf, 14 + options->policydigest_len); - tpm_buf_append_u16(&buf, TPM_ALG_KEYEDHASH); - tpm_buf_append_u16(&buf, hash); + tpm_buf_reset_sized(&sized); + tpm_buf_append_u16(&sized, TPM_ALG_KEYEDHASH); + tpm_buf_append_u16(&sized, hash); /* key properties */ flags = 0; flags |= options->policydigest_len ? 0 : TPM2_OA_USER_WITH_AUTH; - flags |= payload->migratable ? 0 : (TPM2_OA_FIXED_TPM | - TPM2_OA_FIXED_PARENT); - tpm_buf_append_u32(&buf, flags); + flags |= payload->migratable ? 0 : (TPM2_OA_FIXED_TPM | TPM2_OA_FIXED_PARENT); + tpm_buf_append_u32(&sized, flags); /* policy */ - tpm_buf_append_u16(&buf, options->policydigest_len); + tpm_buf_append_u16(&sized, options->policydigest_len); if (options->policydigest_len) - tpm_buf_append(&buf, options->policydigest, - options->policydigest_len); + tpm_buf_append(&sized, options->policydigest, options->policydigest_len); /* public parameters */ - tpm_buf_append_u16(&buf, TPM_ALG_NULL); - tpm_buf_append_u16(&buf, 0); + tpm_buf_append_u16(&sized, TPM_ALG_NULL); + tpm_buf_append_u16(&sized, 0); + + tpm_buf_append(&buf, sized.data, sized.length); /* outside info */ tpm_buf_append_u16(&buf, 0); @@ -312,21 +321,20 @@ int tpm2_seal_trusted(struct tpm_chip *chip, if (rc) goto out; - blob_len = be32_to_cpup((__be32 *) &buf.data[TPM_HEADER_SIZE]); - if (blob_len > MAX_BLOB_SIZE) { + blob_len = tpm_buf_read_u32(&buf, &offset); + if (blob_len > MAX_BLOB_SIZE || buf.flags & TPM_BUF_BOUNDARY_ERROR) { rc = -E2BIG; goto out; } - if (tpm_buf_length(&buf) < TPM_HEADER_SIZE + 4 + blob_len) { + if (buf.length - offset < blob_len) { rc = -EFAULT; goto out; } - blob_len = tpm2_key_encode(payload, options, - &buf.data[TPM_HEADER_SIZE + 4], - blob_len); + blob_len = tpm2_key_encode(payload, options, &buf.data[offset], blob_len); out: + tpm_buf_destroy(&sized); tpm_buf_destroy(&buf); if (rc > 0) { From f135440447af5156de91272ee52ccedcf0796e94 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 29 Apr 2024 16:27:58 -0400 Subject: [PATCH 952/969] crypto: lib - implement library version of AES in CFB mode Implement AES in CFB mode using the existing, mostly constant-time generic AES library implementation. This will be used by the TPM code to encrypt communications with TPM hardware, which is often a discrete component connected using sniffable wires or traces. While a CFB template does exist, using a skcipher is a major pain for non-performance critical synchronous crypto where the algorithm is known at compile time and the data is in contiguous buffers with valid kernel virtual addresses. Tested-by: James Bottomley Reviewed-by: James Bottomley Reviewed-by: Jarkko Sakkinen Link: https://lore.kernel.org/all/20230216201410.15010-1-James.Bottomley@HansenPartnership.com/ Signed-off-by: Ard Biesheuvel Signed-off-by: James Bottomley Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- include/crypto/aes.h | 5 + lib/crypto/Kconfig | 5 + lib/crypto/Makefile | 3 + lib/crypto/aescfb.c | 257 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 270 insertions(+) create mode 100644 lib/crypto/aescfb.c diff --git a/include/crypto/aes.h b/include/crypto/aes.h index 2090729701ab..9339da7c20a8 100644 --- a/include/crypto/aes.h +++ b/include/crypto/aes.h @@ -87,4 +87,9 @@ void aes_decrypt(const struct crypto_aes_ctx *ctx, u8 *out, const u8 *in); extern const u8 crypto_aes_sbox[]; extern const u8 crypto_aes_inv_sbox[]; +void aescfb_encrypt(const struct crypto_aes_ctx *ctx, u8 *dst, const u8 *src, + int len, const u8 iv[AES_BLOCK_SIZE]); +void aescfb_decrypt(const struct crypto_aes_ctx *ctx, u8 *dst, const u8 *src, + int len, const u8 iv[AES_BLOCK_SIZE]); + #endif diff --git a/lib/crypto/Kconfig b/lib/crypto/Kconfig index 45436bfc6dff..b01253cac70a 100644 --- a/lib/crypto/Kconfig +++ b/lib/crypto/Kconfig @@ -8,6 +8,11 @@ config CRYPTO_LIB_UTILS config CRYPTO_LIB_AES tristate +config CRYPTO_LIB_AESCFB + tristate + select CRYPTO_LIB_AES + select CRYPTO_LIB_UTILS + config CRYPTO_LIB_AESGCM tristate select CRYPTO_LIB_AES diff --git a/lib/crypto/Makefile b/lib/crypto/Makefile index 8d1446c2be71..969baab8c805 100644 --- a/lib/crypto/Makefile +++ b/lib/crypto/Makefile @@ -10,6 +10,9 @@ obj-$(CONFIG_CRYPTO_LIB_CHACHA_GENERIC) += libchacha.o obj-$(CONFIG_CRYPTO_LIB_AES) += libaes.o libaes-y := aes.o +obj-$(CONFIG_CRYPTO_LIB_AESCFB) += libaescfb.o +libaescfb-y := aescfb.o + obj-$(CONFIG_CRYPTO_LIB_AESGCM) += libaesgcm.o libaesgcm-y := aesgcm.o diff --git a/lib/crypto/aescfb.c b/lib/crypto/aescfb.c new file mode 100644 index 000000000000..749dc1258a44 --- /dev/null +++ b/lib/crypto/aescfb.c @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Minimal library implementation of AES in CFB mode + * + * Copyright 2023 Google LLC + */ + +#include + +#include +#include + +#include + +static void aescfb_encrypt_block(const struct crypto_aes_ctx *ctx, void *dst, + const void *src) +{ + unsigned long flags; + + /* + * In AES-CFB, the AES encryption operates on known 'plaintext' (the IV + * and ciphertext), making it susceptible to timing attacks on the + * encryption key. The AES library already mitigates this risk to some + * extent by pulling the entire S-box into the caches before doing any + * substitutions, but this strategy is more effective when running with + * interrupts disabled. + */ + local_irq_save(flags); + aes_encrypt(ctx, dst, src); + local_irq_restore(flags); +} + +/** + * aescfb_encrypt - Perform AES-CFB encryption on a block of data + * + * @ctx: The AES-CFB key schedule + * @dst: Pointer to the ciphertext output buffer + * @src: Pointer the plaintext (may equal @dst for encryption in place) + * @len: The size in bytes of the plaintext and ciphertext. + * @iv: The initialization vector (IV) to use for this block of data + */ +void aescfb_encrypt(const struct crypto_aes_ctx *ctx, u8 *dst, const u8 *src, + int len, const u8 iv[AES_BLOCK_SIZE]) +{ + u8 ks[AES_BLOCK_SIZE]; + const u8 *v = iv; + + while (len > 0) { + aescfb_encrypt_block(ctx, ks, v); + crypto_xor_cpy(dst, src, ks, min(len, AES_BLOCK_SIZE)); + v = dst; + + dst += AES_BLOCK_SIZE; + src += AES_BLOCK_SIZE; + len -= AES_BLOCK_SIZE; + } + + memzero_explicit(ks, sizeof(ks)); +} +EXPORT_SYMBOL(aescfb_encrypt); + +/** + * aescfb_decrypt - Perform AES-CFB decryption on a block of data + * + * @ctx: The AES-CFB key schedule + * @dst: Pointer to the plaintext output buffer + * @src: Pointer the ciphertext (may equal @dst for decryption in place) + * @len: The size in bytes of the plaintext and ciphertext. + * @iv: The initialization vector (IV) to use for this block of data + */ +void aescfb_decrypt(const struct crypto_aes_ctx *ctx, u8 *dst, const u8 *src, + int len, const u8 iv[AES_BLOCK_SIZE]) +{ + u8 ks[2][AES_BLOCK_SIZE]; + + aescfb_encrypt_block(ctx, ks[0], iv); + + for (int i = 0; len > 0; i ^= 1) { + if (len > AES_BLOCK_SIZE) + /* + * Generate the keystream for the next block before + * performing the XOR, as that may update in place and + * overwrite the ciphertext. + */ + aescfb_encrypt_block(ctx, ks[!i], src); + + crypto_xor_cpy(dst, src, ks[i], min(len, AES_BLOCK_SIZE)); + + dst += AES_BLOCK_SIZE; + src += AES_BLOCK_SIZE; + len -= AES_BLOCK_SIZE; + } + + memzero_explicit(ks, sizeof(ks)); +} +EXPORT_SYMBOL(aescfb_decrypt); + +MODULE_DESCRIPTION("Generic AES-CFB library"); +MODULE_AUTHOR("Ard Biesheuvel "); +MODULE_LICENSE("GPL"); + +#ifndef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS + +/* + * Test code below. Vectors taken from crypto/testmgr.h + */ + +static struct { + u8 ptext[64]; + u8 ctext[64]; + + u8 key[AES_MAX_KEY_SIZE]; + u8 iv[AES_BLOCK_SIZE]; + + int klen; + int len; +} const aescfb_tv[] __initconst = { + { /* From NIST SP800-38A */ + .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" + "\xab\xf7\x15\x88\x09\xcf\x4f\x3c", + .klen = 16, + .iv = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", + .ptext = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96" + "\xe9\x3d\x7e\x11\x73\x93\x17\x2a" + "\xae\x2d\x8a\x57\x1e\x03\xac\x9c" + "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51" + "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11" + "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef" + "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17" + "\xad\x2b\x41\x7b\xe6\x6c\x37\x10", + .ctext = "\x3b\x3f\xd9\x2e\xb7\x2d\xad\x20" + "\x33\x34\x49\xf8\xe8\x3c\xfb\x4a" + "\xc8\xa6\x45\x37\xa0\xb3\xa9\x3f" + "\xcd\xe3\xcd\xad\x9f\x1c\xe5\x8b" + "\x26\x75\x1f\x67\xa3\xcb\xb1\x40" + "\xb1\x80\x8c\xf1\x87\xa4\xf4\xdf" + "\xc0\x4b\x05\x35\x7c\x5d\x1c\x0e" + "\xea\xc4\xc6\x6f\x9f\xf7\xf2\xe6", + .len = 64, + }, { + .key = "\x8e\x73\xb0\xf7\xda\x0e\x64\x52" + "\xc8\x10\xf3\x2b\x80\x90\x79\xe5" + "\x62\xf8\xea\xd2\x52\x2c\x6b\x7b", + .klen = 24, + .iv = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", + .ptext = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96" + "\xe9\x3d\x7e\x11\x73\x93\x17\x2a" + "\xae\x2d\x8a\x57\x1e\x03\xac\x9c" + "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51" + "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11" + "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef" + "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17" + "\xad\x2b\x41\x7b\xe6\x6c\x37\x10", + .ctext = "\xcd\xc8\x0d\x6f\xdd\xf1\x8c\xab" + "\x34\xc2\x59\x09\xc9\x9a\x41\x74" + "\x67\xce\x7f\x7f\x81\x17\x36\x21" + "\x96\x1a\x2b\x70\x17\x1d\x3d\x7a" + "\x2e\x1e\x8a\x1d\xd5\x9b\x88\xb1" + "\xc8\xe6\x0f\xed\x1e\xfa\xc4\xc9" + "\xc0\x5f\x9f\x9c\xa9\x83\x4f\xa0" + "\x42\xae\x8f\xba\x58\x4b\x09\xff", + .len = 64, + }, { + .key = "\x60\x3d\xeb\x10\x15\xca\x71\xbe" + "\x2b\x73\xae\xf0\x85\x7d\x77\x81" + "\x1f\x35\x2c\x07\x3b\x61\x08\xd7" + "\x2d\x98\x10\xa3\x09\x14\xdf\xf4", + .klen = 32, + .iv = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", + .ptext = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96" + "\xe9\x3d\x7e\x11\x73\x93\x17\x2a" + "\xae\x2d\x8a\x57\x1e\x03\xac\x9c" + "\x9e\xb7\x6f\xac\x45\xaf\x8e\x51" + "\x30\xc8\x1c\x46\xa3\x5c\xe4\x11" + "\xe5\xfb\xc1\x19\x1a\x0a\x52\xef" + "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17" + "\xad\x2b\x41\x7b\xe6\x6c\x37\x10", + .ctext = "\xdc\x7e\x84\xbf\xda\x79\x16\x4b" + "\x7e\xcd\x84\x86\x98\x5d\x38\x60" + "\x39\xff\xed\x14\x3b\x28\xb1\xc8" + "\x32\x11\x3c\x63\x31\xe5\x40\x7b" + "\xdf\x10\x13\x24\x15\xe5\x4b\x92" + "\xa1\x3e\xd0\xa8\x26\x7a\xe2\xf9" + "\x75\xa3\x85\x74\x1a\xb9\xce\xf8" + "\x20\x31\x62\x3d\x55\xb1\xe4\x71", + .len = 64, + }, { /* > 16 bytes, not a multiple of 16 bytes */ + .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" + "\xab\xf7\x15\x88\x09\xcf\x4f\x3c", + .klen = 16, + .iv = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", + .ptext = "\x6b\xc1\xbe\xe2\x2e\x40\x9f\x96" + "\xe9\x3d\x7e\x11\x73\x93\x17\x2a" + "\xae", + .ctext = "\x3b\x3f\xd9\x2e\xb7\x2d\xad\x20" + "\x33\x34\x49\xf8\xe8\x3c\xfb\x4a" + "\xc8", + .len = 17, + }, { /* < 16 bytes */ + .key = "\x2b\x7e\x15\x16\x28\xae\xd2\xa6" + "\xab\xf7\x15\x88\x09\xcf\x4f\x3c", + .klen = 16, + .iv = "\x00\x01\x02\x03\x04\x05\x06\x07" + "\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f", + .ptext = "\x6b\xc1\xbe\xe2\x2e\x40\x9f", + .ctext = "\x3b\x3f\xd9\x2e\xb7\x2d\xad", + .len = 7, + }, +}; + +static int __init libaescfb_init(void) +{ + for (int i = 0; i < ARRAY_SIZE(aescfb_tv); i++) { + struct crypto_aes_ctx ctx; + u8 buf[64]; + + if (aes_expandkey(&ctx, aescfb_tv[i].key, aescfb_tv[i].klen)) { + pr_err("aes_expandkey() failed on vector %d\n", i); + return -ENODEV; + } + + aescfb_encrypt(&ctx, buf, aescfb_tv[i].ptext, aescfb_tv[i].len, + aescfb_tv[i].iv); + if (memcmp(buf, aescfb_tv[i].ctext, aescfb_tv[i].len)) { + pr_err("aescfb_encrypt() #1 failed on vector %d\n", i); + return -ENODEV; + } + + /* decrypt in place */ + aescfb_decrypt(&ctx, buf, buf, aescfb_tv[i].len, aescfb_tv[i].iv); + if (memcmp(buf, aescfb_tv[i].ptext, aescfb_tv[i].len)) { + pr_err("aescfb_decrypt() failed on vector %d\n", i); + return -ENODEV; + } + + /* encrypt in place */ + aescfb_encrypt(&ctx, buf, buf, aescfb_tv[i].len, aescfb_tv[i].iv); + if (memcmp(buf, aescfb_tv[i].ctext, aescfb_tv[i].len)) { + pr_err("aescfb_encrypt() #2 failed on vector %d\n", i); + + return -ENODEV; + } + + } + return 0; +} +module_init(libaescfb_init); + +static void __exit libaescfb_exit(void) +{ +} +module_exit(libaescfb_exit); +#endif From 11189d6828ba4aa77916fdf4fcaebc304b349b51 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:27:59 -0400 Subject: [PATCH 953/969] tpm: add buffer function to point to returned parameters Replace all instances of &buf.data[TPM_HEADER_SIZE] with a new function tpm_buf_parameters() because encryption sessions change where the return parameters are located in the buffer since if a return session is present they're 4 bytes beyond the header with those 4 bytes giving the parameter length. If there is no return session, then they're in the usual place immediately after the header. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-buf.c | 28 ++++++++++++++++++++++++++++ include/linux/tpm.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/drivers/char/tpm/tpm-buf.c b/drivers/char/tpm/tpm-buf.c index cc14fa3fd8c2..6e4595cc98bc 100644 --- a/drivers/char/tpm/tpm-buf.c +++ b/drivers/char/tpm/tpm-buf.c @@ -221,3 +221,31 @@ u32 tpm_buf_read_u32(struct tpm_buf *buf, off_t *offset) return be32_to_cpu(value); } EXPORT_SYMBOL_GPL(tpm_buf_read_u32); + +static u16 tpm_buf_tag(struct tpm_buf *buf) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + + return be16_to_cpu(head->tag); +} + +/** + * tpm_buf_parameters - return the TPM response parameters area of the tpm_buf + * @buf: tpm_buf to use + * + * Where the parameters are located depends on the tag of a TPM + * command (it's immediately after the header for TPM_ST_NO_SESSIONS + * or 4 bytes after for TPM_ST_SESSIONS). Evaluate this and return a + * pointer to the first byte of the parameters area. + * + * @return: pointer to parameters area + */ +u8 *tpm_buf_parameters(struct tpm_buf *buf) +{ + int offset = TPM_HEADER_SIZE; + + if (tpm_buf_tag(buf) == TPM2_ST_SESSIONS) + offset += 4; + + return &buf->data[offset]; +} diff --git a/include/linux/tpm.h b/include/linux/tpm.h index e8172f81c562..6be263509e81 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -344,6 +344,8 @@ u8 tpm_buf_read_u8(struct tpm_buf *buf, off_t *offset); u16 tpm_buf_read_u16(struct tpm_buf *buf, off_t *offset); u32 tpm_buf_read_u32(struct tpm_buf *buf, off_t *offset); +u8 *tpm_buf_parameters(struct tpm_buf *buf); + /* * Check if TPM device is in the firmware upgrade mode. */ From fefb9f12726bebce74be7b95e259594696d0c423 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:00 -0400 Subject: [PATCH 954/969] tpm: export the context save and load commands The TPM2 session HMAC and encryption handling code needs to save and restore a single volatile context for the elliptic curve version of the NULL seed, so export the APIs which do this for internal use. Signed-off-by: James Bottomley Reviewed-by: Stefan Berger Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm.h | 4 ++++ drivers/char/tpm/tpm2-space.c | 8 ++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index 61445f1dc46d..cbc9d1e2974d 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h @@ -312,6 +312,10 @@ int tpm2_commit_space(struct tpm_chip *chip, struct tpm_space *space, void *buf, size_t *bufsiz); int tpm_devs_add(struct tpm_chip *chip); void tpm_devs_remove(struct tpm_chip *chip); +int tpm2_save_context(struct tpm_chip *chip, u32 handle, u8 *buf, + unsigned int buf_size, unsigned int *offset); +int tpm2_load_context(struct tpm_chip *chip, u8 *buf, + unsigned int *offset, u32 *handle); void tpm_bios_log_setup(struct tpm_chip *chip); void tpm_bios_log_teardown(struct tpm_chip *chip); diff --git a/drivers/char/tpm/tpm2-space.c b/drivers/char/tpm/tpm2-space.c index 363afdd4d1d3..24479a81c23c 100644 --- a/drivers/char/tpm/tpm2-space.c +++ b/drivers/char/tpm/tpm2-space.c @@ -68,8 +68,8 @@ void tpm2_del_space(struct tpm_chip *chip, struct tpm_space *space) kfree(space->session_buf); } -static int tpm2_load_context(struct tpm_chip *chip, u8 *buf, - unsigned int *offset, u32 *handle) +int tpm2_load_context(struct tpm_chip *chip, u8 *buf, + unsigned int *offset, u32 *handle) { struct tpm_buf tbuf; struct tpm2_context *ctx; @@ -119,8 +119,8 @@ static int tpm2_load_context(struct tpm_chip *chip, u8 *buf, return 0; } -static int tpm2_save_context(struct tpm_chip *chip, u32 handle, u8 *buf, - unsigned int buf_size, unsigned int *offset) +int tpm2_save_context(struct tpm_chip *chip, u32 handle, u8 *buf, + unsigned int buf_size, unsigned int *offset) { struct tpm_buf tbuf; unsigned int body_size; From d2add27cf2b823a8c1f8caf7ff10c98070df71f5 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:01 -0400 Subject: [PATCH 955/969] tpm: Add NULL primary creation The session handling code uses a "salted" session, meaning a session whose salt is encrypted to the public part of another TPM key so an observer cannot obtain it (and thus deduce the session keys). This patch creates and context saves in the tpm_chip area the primary key of the NULL hierarchy for this purpose. [jarkko@kernel.org: fixed documentation errors] Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/Kconfig | 11 ++ drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm.h | 10 + drivers/char/tpm/tpm2-cmd.c | 5 + drivers/char/tpm/tpm2-sessions.c | 322 +++++++++++++++++++++++++++++++ include/linux/tpm.h | 69 +++++++ 6 files changed, 418 insertions(+) create mode 100644 drivers/char/tpm/tpm2-sessions.c diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index 852bb9344788..ad37b55f5ff9 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -27,6 +27,17 @@ menuconfig TCG_TPM if TCG_TPM +config TCG_TPM2_HMAC + bool "Use HMAC and encrypted transactions on the TPM bus" + default y + help + Setting this causes us to deploy a scheme which uses request + and response HMACs in addition to encryption for + communicating with the TPM to prevent or detect bus snooping + and interposer attacks (see tpm-security.rst). Saying Y + here adds some encryption overhead to all kernel to TPM + transactions. + config HW_RANDOM_TPM bool "TPM HW Random Number Generator support" depends on TCG_TPM && HW_RANDOM && !(TCG_TPM=y && HW_RANDOM=m) diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index ad3594e383e1..4c695b0388f3 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -17,6 +17,7 @@ tpm-y += eventlog/tpm1.o tpm-y += eventlog/tpm2.o tpm-y += tpm-buf.o +tpm-$(CONFIG_TCG_TPM2_HMAC) += tpm2-sessions.o tpm-$(CONFIG_ACPI) += tpm_ppi.o eventlog/acpi.o tpm-$(CONFIG_EFI) += eventlog/efi.o tpm-$(CONFIG_OF) += eventlog/of.o diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index cbc9d1e2974d..6b8b9956ba69 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h @@ -321,4 +321,14 @@ void tpm_bios_log_setup(struct tpm_chip *chip); void tpm_bios_log_teardown(struct tpm_chip *chip); int tpm_dev_common_init(void); void tpm_dev_common_exit(void); + +#ifdef CONFIG_TCG_TPM2_HMAC +int tpm2_sessions_init(struct tpm_chip *chip); +#else +static inline int tpm2_sessions_init(struct tpm_chip *chip) +{ + return 0; +} +#endif + #endif diff --git a/drivers/char/tpm/tpm2-cmd.c b/drivers/char/tpm/tpm2-cmd.c index 93545be190a5..b0e72fb563d9 100644 --- a/drivers/char/tpm/tpm2-cmd.c +++ b/drivers/char/tpm/tpm2-cmd.c @@ -759,6 +759,11 @@ int tpm2_auto_startup(struct tpm_chip *chip) rc = 0; } + if (rc) + goto out; + + rc = tpm2_sessions_init(chip); + out: /* * Infineon TPM in field upgrade mode will return no data for the number diff --git a/drivers/char/tpm/tpm2-sessions.c b/drivers/char/tpm/tpm2-sessions.c new file mode 100644 index 000000000000..78b94097114d --- /dev/null +++ b/drivers/char/tpm/tpm2-sessions.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright (C) 2018 James.Bottomley@HansenPartnership.com + * + */ + +#include "tpm.h" +#include + +/** + * tpm2_parse_create_primary() - parse the data returned from TPM_CC_CREATE_PRIMARY + * + * @chip: The TPM the primary was created under + * @buf: The response buffer from the chip + * @handle: pointer to be filled in with the return handle of the primary + * @hierarchy: The hierarchy the primary was created for + * + * Return: + * * 0 - OK + * * -errno - A system error + * * TPM_RC - A TPM error + */ +static int tpm2_parse_create_primary(struct tpm_chip *chip, struct tpm_buf *buf, + u32 *handle, u32 hierarchy) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + off_t offset_r = TPM_HEADER_SIZE, offset_t; + u16 len = TPM_HEADER_SIZE; + u32 total_len = be32_to_cpu(head->length); + u32 val, param_len; + + *handle = tpm_buf_read_u32(buf, &offset_r); + param_len = tpm_buf_read_u32(buf, &offset_r); + /* + * param_len doesn't include the header, but all the other + * lengths and offsets do, so add it to parm len to make + * the comparisons easier + */ + param_len += TPM_HEADER_SIZE; + + if (param_len + 8 > total_len) + return -EINVAL; + len = tpm_buf_read_u16(buf, &offset_r); + offset_t = offset_r; + /* now we have the public area, compute the name of the object */ + put_unaligned_be16(TPM_ALG_SHA256, chip->null_key_name); + sha256(&buf->data[offset_r], len, chip->null_key_name + 2); + + /* validate the public key */ + val = tpm_buf_read_u16(buf, &offset_t); + + /* key type (must be what we asked for) */ + if (val != TPM_ALG_ECC) + return -EINVAL; + val = tpm_buf_read_u16(buf, &offset_t); + + /* name algorithm */ + if (val != TPM_ALG_SHA256) + return -EINVAL; + val = tpm_buf_read_u32(buf, &offset_t); + + /* object properties */ + if (val != TPM2_OA_TMPL) + return -EINVAL; + + /* auth policy (empty) */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != 0) + return -EINVAL; + + /* symmetric key parameters */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != TPM_ALG_AES) + return -EINVAL; + + /* symmetric key length */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != AES_KEY_BITS) + return -EINVAL; + + /* symmetric encryption scheme */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != TPM_ALG_CFB) + return -EINVAL; + + /* signing scheme */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != TPM_ALG_NULL) + return -EINVAL; + + /* ECC Curve */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != TPM2_ECC_NIST_P256) + return -EINVAL; + + /* KDF Scheme */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != TPM_ALG_NULL) + return -EINVAL; + + /* extract public key (x and y points) */ + val = tpm_buf_read_u16(buf, &offset_t); + if (val != EC_PT_SZ) + return -EINVAL; + memcpy(chip->null_ec_key_x, &buf->data[offset_t], val); + offset_t += val; + val = tpm_buf_read_u16(buf, &offset_t); + if (val != EC_PT_SZ) + return -EINVAL; + memcpy(chip->null_ec_key_y, &buf->data[offset_t], val); + offset_t += val; + + /* original length of the whole TPM2B */ + offset_r += len; + + /* should have exactly consumed the TPM2B public structure */ + if (offset_t != offset_r) + return -EINVAL; + if (offset_r > param_len) + return -EINVAL; + + /* creation data (skip) */ + len = tpm_buf_read_u16(buf, &offset_r); + offset_r += len; + if (offset_r > param_len) + return -EINVAL; + + /* creation digest (must be sha256) */ + len = tpm_buf_read_u16(buf, &offset_r); + offset_r += len; + if (len != SHA256_DIGEST_SIZE || offset_r > param_len) + return -EINVAL; + + /* TPMT_TK_CREATION follows */ + /* tag, must be TPM_ST_CREATION (0x8021) */ + val = tpm_buf_read_u16(buf, &offset_r); + if (val != TPM2_ST_CREATION || offset_r > param_len) + return -EINVAL; + + /* hierarchy */ + val = tpm_buf_read_u32(buf, &offset_r); + if (val != hierarchy || offset_r > param_len) + return -EINVAL; + + /* the ticket digest HMAC (might not be sha256) */ + len = tpm_buf_read_u16(buf, &offset_r); + offset_r += len; + if (offset_r > param_len) + return -EINVAL; + + /* + * finally we have the name, which is a sha256 digest plus a 2 + * byte algorithm type + */ + len = tpm_buf_read_u16(buf, &offset_r); + if (offset_r + len != param_len + 8) + return -EINVAL; + if (len != SHA256_DIGEST_SIZE + 2) + return -EINVAL; + + if (memcmp(chip->null_key_name, &buf->data[offset_r], + SHA256_DIGEST_SIZE + 2) != 0) { + dev_err(&chip->dev, "NULL Seed name comparison failed\n"); + return -EINVAL; + } + + return 0; +} + +/** + * tpm2_create_primary() - create a primary key using a fixed P-256 template + * + * @chip: the TPM chip to create under + * @hierarchy: The hierarchy handle to create under + * @handle: The returned volatile handle on success + * + * For platforms that might not have a persistent primary, this can be + * used to create one quickly on the fly (it uses Elliptic Curve not + * RSA, so even slow TPMs can create one fast). The template uses the + * TCG mandated H one for non-endorsement ECC primaries, i.e. P-256 + * elliptic curve (the only current one all TPM2s are required to + * have) a sha256 name hash and no policy. + * + * Return: + * * 0 - OK + * * -errno - A system error + * * TPM_RC - A TPM error + */ +static int tpm2_create_primary(struct tpm_chip *chip, u32 hierarchy, + u32 *handle) +{ + int rc; + struct tpm_buf buf; + struct tpm_buf template; + + rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_CREATE_PRIMARY); + if (rc) + return rc; + + rc = tpm_buf_init_sized(&template); + if (rc) { + tpm_buf_destroy(&buf); + return rc; + } + + /* + * create the template. Note: in order for userspace to + * verify the security of the system, it will have to create + * and certify this NULL primary, meaning all the template + * parameters will have to be identical, so conform exactly to + * the TCG TPM v2.0 Provisioning Guidance for the SRK ECC + * key H template (H has zero size unique points) + */ + + /* key type */ + tpm_buf_append_u16(&template, TPM_ALG_ECC); + + /* name algorithm */ + tpm_buf_append_u16(&template, TPM_ALG_SHA256); + + /* object properties */ + tpm_buf_append_u32(&template, TPM2_OA_TMPL); + + /* sauth policy (empty) */ + tpm_buf_append_u16(&template, 0); + + /* BEGIN parameters: key specific; for ECC*/ + + /* symmetric algorithm */ + tpm_buf_append_u16(&template, TPM_ALG_AES); + + /* bits for symmetric algorithm */ + tpm_buf_append_u16(&template, AES_KEY_BITS); + + /* algorithm mode (must be CFB) */ + tpm_buf_append_u16(&template, TPM_ALG_CFB); + + /* scheme (NULL means any scheme) */ + tpm_buf_append_u16(&template, TPM_ALG_NULL); + + /* ECC Curve ID */ + tpm_buf_append_u16(&template, TPM2_ECC_NIST_P256); + + /* KDF Scheme */ + tpm_buf_append_u16(&template, TPM_ALG_NULL); + + /* unique: key specific; for ECC it is two zero size points */ + tpm_buf_append_u16(&template, 0); + tpm_buf_append_u16(&template, 0); + + /* END parameters */ + + /* primary handle */ + tpm_buf_append_u32(&buf, hierarchy); + tpm_buf_append_empty_auth(&buf, TPM2_RS_PW); + + /* sensitive create size is 4 for two empty buffers */ + tpm_buf_append_u16(&buf, 4); + + /* sensitive create auth data (empty) */ + tpm_buf_append_u16(&buf, 0); + + /* sensitive create sensitive data (empty) */ + tpm_buf_append_u16(&buf, 0); + + /* the public template */ + tpm_buf_append(&buf, template.data, template.length); + tpm_buf_destroy(&template); + + /* outside info (empty) */ + tpm_buf_append_u16(&buf, 0); + + /* creation PCR (none) */ + tpm_buf_append_u32(&buf, 0); + + rc = tpm_transmit_cmd(chip, &buf, 0, + "attempting to create NULL primary"); + + if (rc == TPM2_RC_SUCCESS) + rc = tpm2_parse_create_primary(chip, &buf, handle, hierarchy); + + tpm_buf_destroy(&buf); + + return rc; +} + +static int tpm2_create_null_primary(struct tpm_chip *chip) +{ + u32 null_key; + int rc; + + rc = tpm2_create_primary(chip, TPM2_RH_NULL, &null_key); + + if (rc == TPM2_RC_SUCCESS) { + unsigned int offset = 0; /* dummy offset for null key context */ + + rc = tpm2_save_context(chip, null_key, chip->null_key_context, + sizeof(chip->null_key_context), &offset); + tpm2_flush_context(chip, null_key); + } + + return rc; +} + +/** + * tpm2_sessions_init() - start of day initialization for the sessions code + * @chip: TPM chip + * + * Derive and context save the null primary and allocate memory in the + * struct tpm_chip for the authorizations. + */ +int tpm2_sessions_init(struct tpm_chip *chip) +{ + int rc; + + rc = tpm2_create_null_primary(chip); + if (rc) + dev_err(&chip->dev, "TPM: security failed (NULL seed derivation): %d\n", rc); + + return rc; +} diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 6be263509e81..bc8c9a350e23 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -23,6 +23,7 @@ #include #include #include +#include #define TPM_DIGEST_SIZE 20 /* Max TPM v1.2 PCR size */ #define TPM_MAX_DIGEST_SIZE SHA512_DIGEST_SIZE @@ -35,12 +36,15 @@ struct trusted_key_options; enum tpm_algorithms { TPM_ALG_ERROR = 0x0000, TPM_ALG_SHA1 = 0x0004, + TPM_ALG_AES = 0x0006, TPM_ALG_KEYEDHASH = 0x0008, TPM_ALG_SHA256 = 0x000B, TPM_ALG_SHA384 = 0x000C, TPM_ALG_SHA512 = 0x000D, TPM_ALG_NULL = 0x0010, TPM_ALG_SM3_256 = 0x0012, + TPM_ALG_ECC = 0x0023, + TPM_ALG_CFB = 0x0043, }; /* @@ -49,6 +53,11 @@ enum tpm_algorithms { */ #define TPM_MAX_HASHES 5 +enum tpm2_curves { + TPM2_ECC_NONE = 0x0000, + TPM2_ECC_NIST_P256 = 0x0003, +}; + struct tpm_digest { u16 alg_id; u8 digest[TPM_MAX_DIGEST_SIZE]; @@ -116,6 +125,20 @@ struct tpm_chip_seqops { const struct seq_operations *seqops; }; +/* fixed define for the curve we use which is NIST_P256 */ +#define EC_PT_SZ 32 + +/* + * fixed define for the size of a name. This is actually HASHALG size + * plus 2, so 32 for SHA256 + */ +#define TPM2_NAME_SIZE 34 + +/* + * The maximum size for an object context + */ +#define TPM2_MAX_CONTEXT_SIZE 4096 + struct tpm_chip { struct device dev; struct device devs; @@ -170,6 +193,17 @@ struct tpm_chip { /* active locality */ int locality; + +#ifdef CONFIG_TCG_TPM2_HMAC + /* details for communication security via sessions */ + + /* saved context for NULL seed */ + u8 null_key_context[TPM2_MAX_CONTEXT_SIZE]; + /* name of NULL seed */ + u8 null_key_name[TPM2_NAME_SIZE]; + u8 null_ec_key_x[EC_PT_SZ]; + u8 null_ec_key_y[EC_PT_SZ]; +#endif }; #define TPM_HEADER_SIZE 10 @@ -194,6 +228,7 @@ enum tpm2_timeouts { enum tpm2_structures { TPM2_ST_NO_SESSIONS = 0x8001, TPM2_ST_SESSIONS = 0x8002, + TPM2_ST_CREATION = 0x8021, }; /* Indicates from what layer of the software stack the error comes from */ @@ -243,6 +278,7 @@ enum tpm2_command_codes { }; enum tpm2_permanent_handles { + TPM2_RH_NULL = 0x40000007, TPM2_RS_PW = 0x40000009, }; @@ -318,9 +354,28 @@ struct tpm_buf { enum tpm2_object_attributes { TPM2_OA_FIXED_TPM = BIT(1), TPM2_OA_FIXED_PARENT = BIT(4), + TPM2_OA_SENSITIVE_DATA_ORIGIN = BIT(5), TPM2_OA_USER_WITH_AUTH = BIT(6), + TPM2_OA_NO_DA = BIT(10), + TPM2_OA_RESTRICTED = BIT(16), + TPM2_OA_DECRYPT = BIT(17), }; +/* + * definitions for the canonical template. These are mandated + * by the TCG key template documents + */ + +#define AES_KEY_BYTES AES_KEYSIZE_128 +#define AES_KEY_BITS (AES_KEY_BYTES*8) +#define TPM2_OA_TMPL (TPM2_OA_NO_DA | \ + TPM2_OA_FIXED_TPM | \ + TPM2_OA_FIXED_PARENT | \ + TPM2_OA_SENSITIVE_DATA_ORIGIN | \ + TPM2_OA_USER_WITH_AUTH | \ + TPM2_OA_DECRYPT | \ + TPM2_OA_RESTRICTED) + enum tpm2_session_attributes { TPM2_SA_CONTINUE_SESSION = BIT(0), }; @@ -373,6 +428,16 @@ extern int tpm_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, extern int tpm_get_random(struct tpm_chip *chip, u8 *data, size_t max); extern struct tpm_chip *tpm_default_chip(void); void tpm2_flush_context(struct tpm_chip *chip, u32 handle); + +static inline void tpm_buf_append_empty_auth(struct tpm_buf *buf, u32 handle) +{ + /* simple authorization for empty auth */ + tpm_buf_append_u32(buf, 9); /* total length of auth */ + tpm_buf_append_u32(buf, handle); + tpm_buf_append_u16(buf, 0); /* nonce len */ + tpm_buf_append_u8(buf, 0); /* attributes */ + tpm_buf_append_u16(buf, 0); /* hmac len */ +} #else static inline int tpm_is_tpm2(struct tpm_chip *chip) { @@ -399,5 +464,9 @@ static inline struct tpm_chip *tpm_default_chip(void) { return NULL; } + +static inline void tpm_buf_append_empty_auth(struct tpm_buf *buf, u32 handle) +{ +} #endif #endif From 033ee84e5f01c86997cde29947805e9781ddf233 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:02 -0400 Subject: [PATCH 956/969] tpm: Add TCG mandated Key Derivation Functions (KDFs) The TCG mandates two Key derivation functions called KDFa and KDFe used to derive keys from seeds and elliptic curve points respectively. The definitions for these functions are found in the TPM 2.0 Library Specification Part 1 - Architecture Guide https://trustedcomputinggroup.org/resource/tpm-library-specification/ Implement a cut down version of each of these functions sufficient to support the key derivation needs of HMAC sessions. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/Kconfig | 1 + drivers/char/tpm/tpm2-sessions.c | 105 +++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index ad37b55f5ff9..c3996786f9bf 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -30,6 +30,7 @@ if TCG_TPM config TCG_TPM2_HMAC bool "Use HMAC and encrypted transactions on the TPM bus" default y + select CRYPTO_LIB_SHA256 help Setting this causes us to deploy a scheme which uses request and response HMACs in addition to encryption for diff --git a/drivers/char/tpm/tpm2-sessions.c b/drivers/char/tpm/tpm2-sessions.c index 78b94097114d..fd121dea614c 100644 --- a/drivers/char/tpm/tpm2-sessions.c +++ b/drivers/char/tpm/tpm2-sessions.c @@ -7,6 +7,111 @@ #include "tpm.h" #include +#include +#include + +/* + * It turns out the crypto hmac(sha256) is hard for us to consume + * because it assumes a fixed key and the TPM seems to change the key + * on every operation, so we weld the hmac init and final functions in + * here to give it the same usage characteristics as a regular hash + */ +static void tpm2_hmac_init(struct sha256_state *sctx, u8 *key, u32 key_len) +{ + u8 pad[SHA256_BLOCK_SIZE]; + int i; + + sha256_init(sctx); + for (i = 0; i < sizeof(pad); i++) { + if (i < key_len) + pad[i] = key[i]; + else + pad[i] = 0; + pad[i] ^= HMAC_IPAD_VALUE; + } + sha256_update(sctx, pad, sizeof(pad)); +} + +static void tpm2_hmac_final(struct sha256_state *sctx, u8 *key, u32 key_len, + u8 *out) +{ + u8 pad[SHA256_BLOCK_SIZE]; + int i; + + for (i = 0; i < sizeof(pad); i++) { + if (i < key_len) + pad[i] = key[i]; + else + pad[i] = 0; + pad[i] ^= HMAC_OPAD_VALUE; + } + + /* collect the final hash; use out as temporary storage */ + sha256_final(sctx, out); + + sha256_init(sctx); + sha256_update(sctx, pad, sizeof(pad)); + sha256_update(sctx, out, SHA256_DIGEST_SIZE); + sha256_final(sctx, out); +} + +/* + * assume hash sha256 and nonces u, v of size SHA256_DIGEST_SIZE but + * otherwise standard tpm2_KDFa. Note output is in bytes not bits. + */ +static void tpm2_KDFa(u8 *key, u32 key_len, const char *label, u8 *u, + u8 *v, u32 bytes, u8 *out) +{ + u32 counter = 1; + const __be32 bits = cpu_to_be32(bytes * 8); + + while (bytes > 0) { + struct sha256_state sctx; + __be32 c = cpu_to_be32(counter); + + tpm2_hmac_init(&sctx, key, key_len); + sha256_update(&sctx, (u8 *)&c, sizeof(c)); + sha256_update(&sctx, label, strlen(label)+1); + sha256_update(&sctx, u, SHA256_DIGEST_SIZE); + sha256_update(&sctx, v, SHA256_DIGEST_SIZE); + sha256_update(&sctx, (u8 *)&bits, sizeof(bits)); + tpm2_hmac_final(&sctx, key, key_len, out); + + bytes -= SHA256_DIGEST_SIZE; + counter++; + out += SHA256_DIGEST_SIZE; + } +} + +/* + * Somewhat of a bastardization of the real KDFe. We're assuming + * we're working with known point sizes for the input parameters and + * the hash algorithm is fixed at sha256. Because we know that the + * point size is 32 bytes like the hash size, there's no need to loop + * in this KDF. + */ +static void tpm2_KDFe(u8 z[EC_PT_SZ], const char *str, u8 *pt_u, u8 *pt_v, + u8 *out) +{ + struct sha256_state sctx; + /* + * this should be an iterative counter, but because we know + * we're only taking 32 bytes for the point using a sha256 + * hash which is also 32 bytes, there's only one loop + */ + __be32 c = cpu_to_be32(1); + + sha256_init(&sctx); + /* counter (BE) */ + sha256_update(&sctx, (u8 *)&c, sizeof(c)); + /* secret value */ + sha256_update(&sctx, z, EC_PT_SZ); + /* string including trailing zero */ + sha256_update(&sctx, str, strlen(str)+1); + sha256_update(&sctx, pt_u, EC_PT_SZ); + sha256_update(&sctx, pt_v, EC_PT_SZ); + sha256_final(&sctx, out); +} /** * tpm2_parse_create_primary() - parse the data returned from TPM_CC_CREATE_PRIMARY From 699e3efd6c645c741ea4d6d58282c56b6d108cf7 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:03 -0400 Subject: [PATCH 957/969] tpm: Add HMAC session start and end functions Add session based HMAC authentication plus parameter decryption and response encryption using AES. The basic design is to segregate all the nasty crypto, hash and hmac code into tpm2-sessions.c and export a usable API. The API first of all starts off by gaining a session with tpm2_start_auth_session() which initiates a session with the TPM and allocates an opaque tpm2_auth structure to handle the session parameters. The design is that session use will be single threaded from start to finish under the ops lock, so the tpm2_auth structure is stored in struct tpm2_chip to simpify the externally visible API. The session can be ended with tpm2_end_auth_session() which is designed only to be used in error legs. Ordinarily the further session API (future patches) will end or continue the session appropriately without having to call this. Signed-off-by: James Bottomley Reviewed-by: Ard Biesheuvel # crypto API parts Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/Kconfig | 2 + drivers/char/tpm/tpm-buf.c | 1 + drivers/char/tpm/tpm-chip.c | 3 + drivers/char/tpm/tpm2-sessions.c | 285 +++++++++++++++++++++++++++++++ include/linux/tpm.h | 34 ++++ 5 files changed, 325 insertions(+) diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig index c3996786f9bf..e63a6a17793c 100644 --- a/drivers/char/tpm/Kconfig +++ b/drivers/char/tpm/Kconfig @@ -30,6 +30,8 @@ if TCG_TPM config TCG_TPM2_HMAC bool "Use HMAC and encrypted transactions on the TPM bus" default y + select CRYPTO_ECDH + select CRYPTO_LIB_AESCFB select CRYPTO_LIB_SHA256 help Setting this causes us to deploy a scheme which uses request diff --git a/drivers/char/tpm/tpm-buf.c b/drivers/char/tpm/tpm-buf.c index 6e4595cc98bc..647c6ca92ac3 100644 --- a/drivers/char/tpm/tpm-buf.c +++ b/drivers/char/tpm/tpm-buf.c @@ -44,6 +44,7 @@ void tpm_buf_reset(struct tpm_buf *buf, u16 tag, u32 ordinal) head->tag = cpu_to_be16(tag); head->length = cpu_to_be32(sizeof(*head)); head->ordinal = cpu_to_be32(ordinal); + buf->handles = 0; } EXPORT_SYMBOL_GPL(tpm_buf_reset); diff --git a/drivers/char/tpm/tpm-chip.c b/drivers/char/tpm/tpm-chip.c index 42b1062e33cd..d93937326b2e 100644 --- a/drivers/char/tpm/tpm-chip.c +++ b/drivers/char/tpm/tpm-chip.c @@ -275,6 +275,9 @@ static void tpm_dev_release(struct device *dev) kfree(chip->work_space.context_buf); kfree(chip->work_space.session_buf); kfree(chip->allocated_banks); +#ifdef CONFIG_TCG_TPM2_HMAC + kfree(chip->auth); +#endif kfree(chip); } diff --git a/drivers/char/tpm/tpm2-sessions.c b/drivers/char/tpm/tpm2-sessions.c index fd121dea614c..1c8d50a501d7 100644 --- a/drivers/char/tpm/tpm2-sessions.c +++ b/drivers/char/tpm/tpm2-sessions.c @@ -3,13 +3,101 @@ /* * Copyright (C) 2018 James.Bottomley@HansenPartnership.com * + * Cryptographic helper routines for handling TPM2 sessions for + * authorization HMAC and request response encryption. + * + * The idea is to ensure that every TPM command is HMAC protected by a + * session, meaning in-flight tampering would be detected and in + * addition all sensitive inputs and responses should be encrypted. + * + * The basic way this works is to use a TPM feature called salted + * sessions where a random secret used in session construction is + * encrypted to the public part of a known TPM key. The problem is we + * have no known keys, so initially a primary Elliptic Curve key is + * derived from the NULL seed (we use EC because most TPMs generate + * these keys much faster than RSA ones). The curve used is NIST_P256 + * because that's now mandated to be present in 'TCG TPM v2.0 + * Provisioning Guidance' + * + * Threat problems: the initial TPM2_CreatePrimary is not (and cannot + * be) session protected, so a clever Man in the Middle could return a + * public key they control to this command and from there intercept + * and decode all subsequent session based transactions. The kernel + * cannot mitigate this threat but, after boot, userspace can get + * proof this has not happened by asking the TPM to certify the NULL + * key. This certification would chain back to the TPM Endorsement + * Certificate and prove the NULL seed primary had not been tampered + * with and thus all sessions must have been cryptographically secure. + * To assist with this, the initial NULL seed public key name is made + * available in a sysfs file. + * + * Use of these functions: + * + * The design is all the crypto, hash and hmac gunk is confined in this + * file and never needs to be seen even by the kernel internal user. To + * the user there's an init function tpm2_sessions_init() that needs to + * be called once per TPM which generates the NULL seed primary key. + * + * These are the usage functions: + * + * tpm2_start_auth_session() which allocates the opaque auth structure + * and gets a session from the TPM. This must be called before + * any of the following functions. The session is protected by a + * session_key which is derived from a random salt value + * encrypted to the NULL seed. + * tpm2_end_auth_session() kills the session and frees the resources. + * Under normal operation this function is done by + * tpm_buf_check_hmac_response(), so this is only to be used on + * error legs where the latter is not executed. */ #include "tpm.h" +#include +#include #include +#include +#include #include #include +/* + * This is the structure that carries all the auth information (like + * session handle, nonces, session key and auth) from use to use it is + * designed to be opaque to anything outside. + */ +struct tpm2_auth { + u32 handle; + /* + * This has two meanings: before tpm_buf_fill_hmac_session() + * it marks the offset in the buffer of the start of the + * sessions (i.e. after all the handles). Once the buffer has + * been filled it markes the session number of our auth + * session so we can find it again in the response buffer. + * + * The two cases are distinguished because the first offset + * must always be greater than TPM_HEADER_SIZE and the second + * must be less than or equal to 5. + */ + u32 session; + /* + * the size here is variable and set by the size of our_nonce + * which must be between 16 and the name hash length. we set + * the maximum sha256 size for the greatest protection + */ + u8 our_nonce[SHA256_DIGEST_SIZE]; + u8 tpm_nonce[SHA256_DIGEST_SIZE]; + /* + * the salt is only used across the session command/response + * after that it can be used as a scratch area + */ + union { + u8 salt[EC_PT_SZ]; + /* scratch for key + IV */ + u8 scratch[AES_KEY_BYTES + AES_BLOCK_SIZE]; + }; + u8 session_key[SHA256_DIGEST_SIZE]; +}; + /* * It turns out the crypto hmac(sha256) is hard for us to consume * because it assumes a fixed key and the TPM seems to change the key @@ -113,6 +201,199 @@ static void tpm2_KDFe(u8 z[EC_PT_SZ], const char *str, u8 *pt_u, u8 *pt_v, sha256_final(&sctx, out); } +static void tpm_buf_append_salt(struct tpm_buf *buf, struct tpm_chip *chip) +{ + struct crypto_kpp *kpp; + struct kpp_request *req; + struct scatterlist s[2], d[1]; + struct ecdh p = {0}; + u8 encoded_key[EC_PT_SZ], *x, *y; + unsigned int buf_len; + + /* secret is two sized points */ + tpm_buf_append_u16(buf, (EC_PT_SZ + 2)*2); + /* + * we cheat here and append uninitialized data to form + * the points. All we care about is getting the two + * co-ordinate pointers, which will be used to overwrite + * the uninitialized data + */ + tpm_buf_append_u16(buf, EC_PT_SZ); + x = &buf->data[tpm_buf_length(buf)]; + tpm_buf_append(buf, encoded_key, EC_PT_SZ); + tpm_buf_append_u16(buf, EC_PT_SZ); + y = &buf->data[tpm_buf_length(buf)]; + tpm_buf_append(buf, encoded_key, EC_PT_SZ); + sg_init_table(s, 2); + sg_set_buf(&s[0], x, EC_PT_SZ); + sg_set_buf(&s[1], y, EC_PT_SZ); + + kpp = crypto_alloc_kpp("ecdh-nist-p256", CRYPTO_ALG_INTERNAL, 0); + if (IS_ERR(kpp)) { + dev_err(&chip->dev, "crypto ecdh allocation failed\n"); + return; + } + + buf_len = crypto_ecdh_key_len(&p); + if (sizeof(encoded_key) < buf_len) { + dev_err(&chip->dev, "salt buffer too small needs %d\n", + buf_len); + goto out; + } + crypto_ecdh_encode_key(encoded_key, buf_len, &p); + /* this generates a random private key */ + crypto_kpp_set_secret(kpp, encoded_key, buf_len); + + /* salt is now the public point of this private key */ + req = kpp_request_alloc(kpp, GFP_KERNEL); + if (!req) + goto out; + kpp_request_set_input(req, NULL, 0); + kpp_request_set_output(req, s, EC_PT_SZ*2); + crypto_kpp_generate_public_key(req); + /* + * we're not done: now we have to compute the shared secret + * which is our private key multiplied by the tpm_key public + * point, we actually only take the x point and discard the y + * point and feed it through KDFe to get the final secret salt + */ + sg_set_buf(&s[0], chip->null_ec_key_x, EC_PT_SZ); + sg_set_buf(&s[1], chip->null_ec_key_y, EC_PT_SZ); + kpp_request_set_input(req, s, EC_PT_SZ*2); + sg_init_one(d, chip->auth->salt, EC_PT_SZ); + kpp_request_set_output(req, d, EC_PT_SZ); + crypto_kpp_compute_shared_secret(req); + kpp_request_free(req); + + /* + * pass the shared secret through KDFe for salt. Note salt + * area is used both for input shared secret and output salt. + * This works because KDFe fully consumes the secret before it + * writes the salt + */ + tpm2_KDFe(chip->auth->salt, "SECRET", x, chip->null_ec_key_x, + chip->auth->salt); + + out: + crypto_free_kpp(kpp); +} +/** + * tpm2_end_auth_session() - kill the allocated auth session + * @chip: the TPM chip structure + * + * ends the session started by tpm2_start_auth_session and frees all + * the resources. Under normal conditions, + * tpm_buf_check_hmac_response() will correctly end the session if + * required, so this function is only for use in error legs that will + * bypass the normal invocation of tpm_buf_check_hmac_response(). + */ +void tpm2_end_auth_session(struct tpm_chip *chip) +{ + tpm2_flush_context(chip, chip->auth->handle); + memzero_explicit(chip->auth, sizeof(*chip->auth)); +} +EXPORT_SYMBOL(tpm2_end_auth_session); + +static int tpm2_parse_start_auth_session(struct tpm2_auth *auth, + struct tpm_buf *buf) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + u32 tot_len = be32_to_cpu(head->length); + off_t offset = TPM_HEADER_SIZE; + u32 val; + + /* we're starting after the header so adjust the length */ + tot_len -= TPM_HEADER_SIZE; + + /* should have handle plus nonce */ + if (tot_len != 4 + 2 + sizeof(auth->tpm_nonce)) + return -EINVAL; + + auth->handle = tpm_buf_read_u32(buf, &offset); + val = tpm_buf_read_u16(buf, &offset); + if (val != sizeof(auth->tpm_nonce)) + return -EINVAL; + memcpy(auth->tpm_nonce, &buf->data[offset], sizeof(auth->tpm_nonce)); + /* now compute the session key from the nonces */ + tpm2_KDFa(auth->salt, sizeof(auth->salt), "ATH", auth->tpm_nonce, + auth->our_nonce, sizeof(auth->session_key), + auth->session_key); + + return 0; +} + +/** + * tpm2_start_auth_session() - create a HMAC authentication session with the TPM + * @chip: the TPM chip structure to create the session with + * + * This function loads the NULL seed from its saved context and starts + * an authentication session on the null seed, fills in the + * @chip->auth structure to contain all the session details necessary + * for performing the HMAC, encrypt and decrypt operations and + * returns. The NULL seed is flushed before this function returns. + * + * Return: zero on success or actual error encountered. + */ +int tpm2_start_auth_session(struct tpm_chip *chip) +{ + struct tpm_buf buf; + struct tpm2_auth *auth = chip->auth; + int rc; + /* null seed context has no offset, but we must provide one */ + unsigned int offset = 0; + u32 nullkey; + + rc = tpm2_load_context(chip, chip->null_key_context, &offset, + &nullkey); + if (rc) + goto out; + + auth->session = TPM_HEADER_SIZE; + + rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_START_AUTH_SESS); + if (rc) + goto out; + + /* salt key handle */ + tpm_buf_append_u32(&buf, nullkey); + /* bind key handle */ + tpm_buf_append_u32(&buf, TPM2_RH_NULL); + /* nonce caller */ + get_random_bytes(auth->our_nonce, sizeof(auth->our_nonce)); + tpm_buf_append_u16(&buf, sizeof(auth->our_nonce)); + tpm_buf_append(&buf, auth->our_nonce, sizeof(auth->our_nonce)); + + /* append encrypted salt and squirrel away unencrypted in auth */ + tpm_buf_append_salt(&buf, chip); + /* session type (HMAC, audit or policy) */ + tpm_buf_append_u8(&buf, TPM2_SE_HMAC); + + /* symmetric encryption parameters */ + /* symmetric algorithm */ + tpm_buf_append_u16(&buf, TPM_ALG_AES); + /* bits for symmetric algorithm */ + tpm_buf_append_u16(&buf, AES_KEY_BITS); + /* symmetric algorithm mode (must be CFB) */ + tpm_buf_append_u16(&buf, TPM_ALG_CFB); + /* hash algorithm for session */ + tpm_buf_append_u16(&buf, TPM_ALG_SHA256); + + rc = tpm_transmit_cmd(chip, &buf, 0, "start auth session"); + tpm2_flush_context(chip, nullkey); + + if (rc == TPM2_RC_SUCCESS) + rc = tpm2_parse_start_auth_session(auth, &buf); + + tpm_buf_destroy(&buf); + + if (rc) + goto out; + + out: + return rc; +} +EXPORT_SYMBOL(tpm2_start_auth_session); + /** * tpm2_parse_create_primary() - parse the data returned from TPM_CC_CREATE_PRIMARY * @@ -423,5 +704,9 @@ int tpm2_sessions_init(struct tpm_chip *chip) if (rc) dev_err(&chip->dev, "TPM: security failed (NULL seed derivation): %d\n", rc); + chip->auth = kmalloc(sizeof(*chip->auth), GFP_KERNEL); + if (!chip->auth) + return -ENOMEM; + return rc; } diff --git a/include/linux/tpm.h b/include/linux/tpm.h index bc8c9a350e23..81b5a70ff80d 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -31,6 +31,14 @@ struct tpm_chip; struct trusted_key_payload; struct trusted_key_options; +/* opaque structure, holds auth session parameters like the session key */ +struct tpm2_auth; + +enum tpm2_session_types { + TPM2_SE_HMAC = 0x00, + TPM2_SE_POLICY = 0x01, + TPM2_SE_TRIAL = 0x02, +}; /* if you add a new hash to this, increment TPM_MAX_HASHES below */ enum tpm_algorithms { @@ -203,6 +211,7 @@ struct tpm_chip { u8 null_key_name[TPM2_NAME_SIZE]; u8 null_ec_key_x[EC_PT_SZ]; u8 null_ec_key_y[EC_PT_SZ]; + struct tpm2_auth *auth; #endif }; @@ -266,6 +275,7 @@ enum tpm2_command_codes { TPM2_CC_CONTEXT_LOAD = 0x0161, TPM2_CC_CONTEXT_SAVE = 0x0162, TPM2_CC_FLUSH_CONTEXT = 0x0165, + TPM2_CC_START_AUTH_SESS = 0x0176, TPM2_CC_VERIFY_SIGNATURE = 0x0177, TPM2_CC_GET_CAPABILITY = 0x017A, TPM2_CC_GET_RANDOM = 0x017B, @@ -349,16 +359,21 @@ struct tpm_buf { u32 flags; u32 length; u8 *data; + u8 handles; }; enum tpm2_object_attributes { TPM2_OA_FIXED_TPM = BIT(1), + TPM2_OA_ST_CLEAR = BIT(2), TPM2_OA_FIXED_PARENT = BIT(4), TPM2_OA_SENSITIVE_DATA_ORIGIN = BIT(5), TPM2_OA_USER_WITH_AUTH = BIT(6), + TPM2_OA_ADMIN_WITH_POLICY = BIT(7), TPM2_OA_NO_DA = BIT(10), + TPM2_OA_ENCRYPTED_DUPLICATION = BIT(11), TPM2_OA_RESTRICTED = BIT(16), TPM2_OA_DECRYPT = BIT(17), + TPM2_OA_SIGN = BIT(18), }; /* @@ -378,6 +393,11 @@ enum tpm2_object_attributes { enum tpm2_session_attributes { TPM2_SA_CONTINUE_SESSION = BIT(0), + TPM2_SA_AUDIT_EXCLUSIVE = BIT(1), + TPM2_SA_AUDIT_RESET = BIT(3), + TPM2_SA_DECRYPT = BIT(5), + TPM2_SA_ENCRYPT = BIT(6), + TPM2_SA_AUDIT = BIT(7), }; struct tpm2_hash { @@ -469,4 +489,18 @@ static inline void tpm_buf_append_empty_auth(struct tpm_buf *buf, u32 handle) { } #endif +#ifdef CONFIG_TCG_TPM2_HMAC + +int tpm2_start_auth_session(struct tpm_chip *chip); +void tpm2_end_auth_session(struct tpm_chip *chip); +#else +static inline int tpm2_start_auth_session(struct tpm_chip *chip) +{ + return 0; +} +static inline void tpm2_end_auth_session(struct tpm_chip *chip) +{ +} +#endif /* CONFIG_TCG_TPM2_HMAC */ + #endif From d0a25bb961e6e5650083a4f15768e3075f7d8db7 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:04 -0400 Subject: [PATCH 958/969] tpm: Add HMAC session name/handle append Add tpm2_append_name() for appending to the handle area of the TPM command. When TPM_BUS_SECURITY is enabled and HMAC sessions are in use this adds the standard u32 handle to the buffer but additionally records the name of the object which must be used as part of the HMAC computation. The name of certain object types (volatile and permanent handles and NV indexes) is a hash of the public area of the object. Since this hash is not known ahead of time, it must be requested from the TPM using TPM2_ReadPublic() (which cannot be HMAC protected, but if an interposer lies about it, the HMAC check will fail and the problem will be detected). Signed-off-by: James Bottomley Reviewed-by: Ard Biesheuvel # crypto API parts Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm2-sessions.c | 129 +++++++++++++++++++++++++++++++ include/linux/tpm.h | 26 +++++++ 2 files changed, 155 insertions(+) diff --git a/drivers/char/tpm/tpm2-sessions.c b/drivers/char/tpm/tpm2-sessions.c index 1c8d50a501d7..203a3b3cee67 100644 --- a/drivers/char/tpm/tpm2-sessions.c +++ b/drivers/char/tpm/tpm2-sessions.c @@ -49,6 +49,11 @@ * Under normal operation this function is done by * tpm_buf_check_hmac_response(), so this is only to be used on * error legs where the latter is not executed. + * tpm_buf_append_name() to add a handle to the buffer. This must be + * used in place of the usual tpm_buf_append_u32() for adding + * handles because handles have to be processed specially when + * calculating the HMAC. In particular, for NV, volatile and + * permanent objects you now need to provide the name. */ #include "tpm.h" @@ -60,6 +65,9 @@ #include #include +/* maximum number of names the TPM must remember for authorization */ +#define AUTH_MAX_NAMES 3 + /* * This is the structure that carries all the auth information (like * session handle, nonces, session key and auth) from use to use it is @@ -96,8 +104,31 @@ struct tpm2_auth { u8 scratch[AES_KEY_BYTES + AES_BLOCK_SIZE]; }; u8 session_key[SHA256_DIGEST_SIZE]; + + /* + * memory for three authorization handles. We know them by + * handle, but they are part of the session by name, which + * we must compute and remember + */ + u32 name_h[AUTH_MAX_NAMES]; + u8 name[AUTH_MAX_NAMES][2 + SHA512_DIGEST_SIZE]; }; +/* + * Name Size based on TPM algorithm (assumes no hash bigger than 255) + */ +static u8 name_size(const u8 *name) +{ + static u8 size_map[] = { + [TPM_ALG_SHA1] = SHA1_DIGEST_SIZE, + [TPM_ALG_SHA256] = SHA256_DIGEST_SIZE, + [TPM_ALG_SHA384] = SHA384_DIGEST_SIZE, + [TPM_ALG_SHA512] = SHA512_DIGEST_SIZE, + }; + u16 alg = get_unaligned_be16(name); + return size_map[alg] + 2; +} + /* * It turns out the crypto hmac(sha256) is hard for us to consume * because it assumes a fixed key and the TPM seems to change the key @@ -277,6 +308,104 @@ static void tpm_buf_append_salt(struct tpm_buf *buf, struct tpm_chip *chip) out: crypto_free_kpp(kpp); } + +static int tpm2_parse_read_public(char *name, struct tpm_buf *buf) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + off_t offset = TPM_HEADER_SIZE; + u32 tot_len = be32_to_cpu(head->length); + u32 val; + + /* we're starting after the header so adjust the length */ + tot_len -= TPM_HEADER_SIZE; + + /* skip public */ + val = tpm_buf_read_u16(buf, &offset); + if (val > tot_len) + return -EINVAL; + offset += val; + /* name */ + val = tpm_buf_read_u16(buf, &offset); + if (val != name_size(&buf->data[offset])) + return -EINVAL; + memcpy(name, &buf->data[offset], val); + /* forget the rest */ + return 0; +} + +static int tpm2_read_public(struct tpm_chip *chip, u32 handle, char *name) +{ + struct tpm_buf buf; + int rc; + + rc = tpm_buf_init(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_READ_PUBLIC); + if (rc) + return rc; + + tpm_buf_append_u32(&buf, handle); + rc = tpm_transmit_cmd(chip, &buf, 0, "read public"); + if (rc == TPM2_RC_SUCCESS) + rc = tpm2_parse_read_public(name, &buf); + + tpm_buf_destroy(&buf); + + return rc; +} + +/** + * tpm_buf_append_name() - add a handle area to the buffer + * @chip: the TPM chip structure + * @buf: The buffer to be appended + * @handle: The handle to be appended + * @name: The name of the handle (may be NULL) + * + * In order to compute session HMACs, we need to know the names of the + * objects pointed to by the handles. For most objects, this is simply + * the actual 4 byte handle or an empty buf (in these cases @name + * should be NULL) but for volatile objects, permanent objects and NV + * areas, the name is defined as the hash (according to the name + * algorithm which should be set to sha256) of the public area to + * which the two byte algorithm id has been appended. For these + * objects, the @name pointer should point to this. If a name is + * required but @name is NULL, then TPM2_ReadPublic() will be called + * on the handle to obtain the name. + * + * As with most tpm_buf operations, success is assumed because failure + * will be caused by an incorrect programming model and indicated by a + * kernel message. + */ +void tpm_buf_append_name(struct tpm_chip *chip, struct tpm_buf *buf, + u32 handle, u8 *name) +{ + enum tpm2_mso_type mso = tpm2_handle_mso(handle); + struct tpm2_auth *auth = chip->auth; + int slot; + + slot = (tpm_buf_length(buf) - TPM_HEADER_SIZE)/4; + if (slot >= AUTH_MAX_NAMES) { + dev_err(&chip->dev, "TPM: too many handles\n"); + return; + } + WARN(auth->session != tpm_buf_length(buf), + "name added in wrong place\n"); + tpm_buf_append_u32(buf, handle); + auth->session += 4; + + if (mso == TPM2_MSO_PERSISTENT || + mso == TPM2_MSO_VOLATILE || + mso == TPM2_MSO_NVRAM) { + if (!name) + tpm2_read_public(chip, handle, auth->name[slot]); + } else { + if (name) + dev_err(&chip->dev, "TPM: Handle does not require name but one is specified\n"); + } + + auth->name_h[slot] = handle; + if (name) + memcpy(auth->name[slot], name, name_size(name)); +} +EXPORT_SYMBOL(tpm_buf_append_name); /** * tpm2_end_auth_session() - kill the allocated auth session * @chip: the TPM chip structure diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 81b5a70ff80d..31c2065fcd35 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -275,6 +275,7 @@ enum tpm2_command_codes { TPM2_CC_CONTEXT_LOAD = 0x0161, TPM2_CC_CONTEXT_SAVE = 0x0162, TPM2_CC_FLUSH_CONTEXT = 0x0165, + TPM2_CC_READ_PUBLIC = 0x0173, TPM2_CC_START_AUTH_SESS = 0x0176, TPM2_CC_VERIFY_SIGNATURE = 0x0177, TPM2_CC_GET_CAPABILITY = 0x017A, @@ -292,6 +293,21 @@ enum tpm2_permanent_handles { TPM2_RS_PW = 0x40000009, }; +/* Most Significant Octet for key types */ +enum tpm2_mso_type { + TPM2_MSO_NVRAM = 0x01, + TPM2_MSO_SESSION = 0x02, + TPM2_MSO_POLICY = 0x03, + TPM2_MSO_PERMANENT = 0x40, + TPM2_MSO_VOLATILE = 0x80, + TPM2_MSO_PERSISTENT = 0x81, +}; + +static inline enum tpm2_mso_type tpm2_handle_mso(u32 handle) +{ + return handle >> 24; +} + enum tpm2_capabilities { TPM2_CAP_HANDLES = 1, TPM2_CAP_COMMANDS = 2, @@ -492,6 +508,8 @@ static inline void tpm_buf_append_empty_auth(struct tpm_buf *buf, u32 handle) #ifdef CONFIG_TCG_TPM2_HMAC int tpm2_start_auth_session(struct tpm_chip *chip); +void tpm_buf_append_name(struct tpm_chip *chip, struct tpm_buf *buf, + u32 handle, u8 *name); void tpm2_end_auth_session(struct tpm_chip *chip); #else static inline int tpm2_start_auth_session(struct tpm_chip *chip) @@ -501,6 +519,14 @@ static inline int tpm2_start_auth_session(struct tpm_chip *chip) static inline void tpm2_end_auth_session(struct tpm_chip *chip) { } +static inline void tpm_buf_append_name(struct tpm_chip *chip, + struct tpm_buf *buf, + u32 handle, u8 *name) +{ + tpm_buf_append_u32(buf, handle); + /* count the number of handles in the upper bits of flags */ + buf->handles++; +} #endif /* CONFIG_TCG_TPM2_HMAC */ #endif From 1085b8276bb4239daa7008f0dcd5c973e4bd690f Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:05 -0400 Subject: [PATCH 959/969] tpm: Add the rest of the session HMAC API The final pieces of the HMAC API are for manipulating the session area of the command. To add an authentication HMAC session tpm_buf_append_hmac_session() is called where tpm2_append_auth() would go. If a non empty password is passed in, this is correctly added to the HMAC to prove knowledge of it without revealing it. Note that if the session is only used to encrypt or decrypt parameters (no authentication) then tpm_buf_append_hmac_session_opt() must be used instead. This functions identically to tpm_buf_append_hmac_session() when TPM_BUS_SECURITY is enabled, but differently when it isn't, because effectively nothing is appended to the session area. Next the parameters should be filled in for the command and finally tpm_buf_fill_hmac_session() is called immediately prior to transmitting the command which computes the correct HMAC and places it in the command at the session location in the tpm buffer Finally, after tpm_transmit_cmd() is called, tpm_buf_check_hmac_response() is called to check that the returned HMAC matched and collect the new state for the next use of the session, if any. The features of the session are controlled by the session attributes set in tpm_buf_append_hmac_session(). If TPM2_SA_CONTINUE_SESSION is not specified, the session will be flushed and the tpm2_auth structure freed in tpm_buf_check_hmac_response(); otherwise the session may be used again. Parameter encryption is specified by or'ing the flag TPM2_SA_DECRYPT and response encryption by or'ing the flag TPM2_SA_ENCRYPT. the various encryptions will be taken care of by tpm_buf_fill_hmac_session() and tpm_buf_check_hmac_response() respectively. Signed-off-by: James Bottomley Reviewed-by: Ard Biesheuvel # crypto API parts Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm2-sessions.c | 400 +++++++++++++++++++++++++++++++ include/linux/tpm.h | 69 ++++++ 2 files changed, 469 insertions(+) diff --git a/drivers/char/tpm/tpm2-sessions.c b/drivers/char/tpm/tpm2-sessions.c index 203a3b3cee67..dc50f635700c 100644 --- a/drivers/char/tpm/tpm2-sessions.c +++ b/drivers/char/tpm/tpm2-sessions.c @@ -54,6 +54,18 @@ * handles because handles have to be processed specially when * calculating the HMAC. In particular, for NV, volatile and * permanent objects you now need to provide the name. + * tpm_buf_append_hmac_session() which appends the hmac session to the + * buf in the same way tpm_buf_append_auth does(). + * tpm_buf_fill_hmac_session() This calculates the correct hash and + * places it in the buffer. It must be called after the complete + * command buffer is finalized so it can fill in the correct HMAC + * based on the parameters. + * tpm_buf_check_hmac_response() which checks the session response in + * the buffer and calculates what it should be. If there's a + * mismatch it will log a warning and return an error. If + * tpm_buf_append_hmac_session() did not specify + * TPM_SA_CONTINUE_SESSION then the session will be closed (if it + * hasn't been consumed) and the auth structure freed. */ #include "tpm.h" @@ -103,7 +115,23 @@ struct tpm2_auth { /* scratch for key + IV */ u8 scratch[AES_KEY_BYTES + AES_BLOCK_SIZE]; }; + /* + * the session key and passphrase are the same size as the + * name digest (sha256 again). The session key is constant + * for the use of the session and the passphrase can change + * with every invocation. + * + * Note: these fields must be adjacent and in this order + * because several HMAC/KDF schemes use the combination of the + * session_key and passphrase. + */ u8 session_key[SHA256_DIGEST_SIZE]; + u8 passphrase[SHA256_DIGEST_SIZE]; + int passphrase_len; + struct crypto_aes_ctx aes_ctx; + /* saved session attributes: */ + u8 attrs; + __be32 ordinal; /* * memory for three authorization handles. We know them by @@ -309,6 +337,230 @@ static void tpm_buf_append_salt(struct tpm_buf *buf, struct tpm_chip *chip) crypto_free_kpp(kpp); } +/** + * tpm_buf_append_hmac_session() - Append a TPM session element + * @chip: the TPM chip structure + * @buf: The buffer to be appended + * @attributes: The session attributes + * @passphrase: The session authority (NULL if none) + * @passphrase_len: The length of the session authority (0 if none) + * + * This fills in a session structure in the TPM command buffer, except + * for the HMAC which cannot be computed until the command buffer is + * complete. The type of session is controlled by the @attributes, + * the main ones of which are TPM2_SA_CONTINUE_SESSION which means the + * session won't terminate after tpm_buf_check_hmac_response(), + * TPM2_SA_DECRYPT which means this buffers first parameter should be + * encrypted with a session key and TPM2_SA_ENCRYPT, which means the + * response buffer's first parameter needs to be decrypted (confusing, + * but the defines are written from the point of view of the TPM). + * + * Any session appended by this command must be finalized by calling + * tpm_buf_fill_hmac_session() otherwise the HMAC will be incorrect + * and the TPM will reject the command. + * + * As with most tpm_buf operations, success is assumed because failure + * will be caused by an incorrect programming model and indicated by a + * kernel message. + */ +void tpm_buf_append_hmac_session(struct tpm_chip *chip, struct tpm_buf *buf, + u8 attributes, u8 *passphrase, + int passphrase_len) +{ + u8 nonce[SHA256_DIGEST_SIZE]; + u32 len; + struct tpm2_auth *auth = chip->auth; + + /* + * The Architecture Guide requires us to strip trailing zeros + * before computing the HMAC + */ + while (passphrase && passphrase_len > 0 + && passphrase[passphrase_len - 1] == '\0') + passphrase_len--; + + auth->attrs = attributes; + auth->passphrase_len = passphrase_len; + if (passphrase_len) + memcpy(auth->passphrase, passphrase, passphrase_len); + + if (auth->session != tpm_buf_length(buf)) { + /* we're not the first session */ + len = get_unaligned_be32(&buf->data[auth->session]); + if (4 + len + auth->session != tpm_buf_length(buf)) { + WARN(1, "session length mismatch, cannot append"); + return; + } + + /* add our new session */ + len += 9 + 2 * SHA256_DIGEST_SIZE; + put_unaligned_be32(len, &buf->data[auth->session]); + } else { + tpm_buf_append_u32(buf, 9 + 2 * SHA256_DIGEST_SIZE); + } + + /* random number for our nonce */ + get_random_bytes(nonce, sizeof(nonce)); + memcpy(auth->our_nonce, nonce, sizeof(nonce)); + tpm_buf_append_u32(buf, auth->handle); + /* our new nonce */ + tpm_buf_append_u16(buf, SHA256_DIGEST_SIZE); + tpm_buf_append(buf, nonce, SHA256_DIGEST_SIZE); + tpm_buf_append_u8(buf, auth->attrs); + /* and put a placeholder for the hmac */ + tpm_buf_append_u16(buf, SHA256_DIGEST_SIZE); + tpm_buf_append(buf, nonce, SHA256_DIGEST_SIZE); +} +EXPORT_SYMBOL(tpm_buf_append_hmac_session); + +/** + * tpm_buf_fill_hmac_session() - finalize the session HMAC + * @chip: the TPM chip structure + * @buf: The buffer to be appended + * + * This command must not be called until all of the parameters have + * been appended to @buf otherwise the computed HMAC will be + * incorrect. + * + * This function computes and fills in the session HMAC using the + * session key and, if TPM2_SA_DECRYPT was specified, computes the + * encryption key and encrypts the first parameter of the command + * buffer with it. + * + * As with most tpm_buf operations, success is assumed because failure + * will be caused by an incorrect programming model and indicated by a + * kernel message. + */ +void tpm_buf_fill_hmac_session(struct tpm_chip *chip, struct tpm_buf *buf) +{ + u32 cc, handles, val; + struct tpm2_auth *auth = chip->auth; + int i; + struct tpm_header *head = (struct tpm_header *)buf->data; + off_t offset_s = TPM_HEADER_SIZE, offset_p; + u8 *hmac = NULL; + u32 attrs; + u8 cphash[SHA256_DIGEST_SIZE]; + struct sha256_state sctx; + + /* save the command code in BE format */ + auth->ordinal = head->ordinal; + + cc = be32_to_cpu(head->ordinal); + + i = tpm2_find_cc(chip, cc); + if (i < 0) { + dev_err(&chip->dev, "Command 0x%x not found in TPM\n", cc); + return; + } + attrs = chip->cc_attrs_tbl[i]; + + handles = (attrs >> TPM2_CC_ATTR_CHANDLES) & GENMASK(2, 0); + + /* + * just check the names, it's easy to make mistakes. This + * would happen if someone added a handle via + * tpm_buf_append_u32() instead of tpm_buf_append_name() + */ + for (i = 0; i < handles; i++) { + u32 handle = tpm_buf_read_u32(buf, &offset_s); + + if (auth->name_h[i] != handle) { + dev_err(&chip->dev, "TPM: handle %d wrong for name\n", + i); + return; + } + } + /* point offset_s to the start of the sessions */ + val = tpm_buf_read_u32(buf, &offset_s); + /* point offset_p to the start of the parameters */ + offset_p = offset_s + val; + for (i = 1; offset_s < offset_p; i++) { + u32 handle = tpm_buf_read_u32(buf, &offset_s); + u16 len; + u8 a; + + /* nonce (already in auth) */ + len = tpm_buf_read_u16(buf, &offset_s); + offset_s += len; + + a = tpm_buf_read_u8(buf, &offset_s); + + len = tpm_buf_read_u16(buf, &offset_s); + if (handle == auth->handle && auth->attrs == a) { + hmac = &buf->data[offset_s]; + /* + * save our session number so we know which + * session in the response belongs to us + */ + auth->session = i; + } + + offset_s += len; + } + if (offset_s != offset_p) { + dev_err(&chip->dev, "TPM session length is incorrect\n"); + return; + } + if (!hmac) { + dev_err(&chip->dev, "TPM could not find HMAC session\n"); + return; + } + + /* encrypt before HMAC */ + if (auth->attrs & TPM2_SA_DECRYPT) { + u16 len; + + /* need key and IV */ + tpm2_KDFa(auth->session_key, SHA256_DIGEST_SIZE + + auth->passphrase_len, "CFB", auth->our_nonce, + auth->tpm_nonce, AES_KEY_BYTES + AES_BLOCK_SIZE, + auth->scratch); + + len = tpm_buf_read_u16(buf, &offset_p); + aes_expandkey(&auth->aes_ctx, auth->scratch, AES_KEY_BYTES); + aescfb_encrypt(&auth->aes_ctx, &buf->data[offset_p], + &buf->data[offset_p], len, + auth->scratch + AES_KEY_BYTES); + /* reset p to beginning of parameters for HMAC */ + offset_p -= 2; + } + + sha256_init(&sctx); + /* ordinal is already BE */ + sha256_update(&sctx, (u8 *)&head->ordinal, sizeof(head->ordinal)); + /* add the handle names */ + for (i = 0; i < handles; i++) { + enum tpm2_mso_type mso = tpm2_handle_mso(auth->name_h[i]); + + if (mso == TPM2_MSO_PERSISTENT || + mso == TPM2_MSO_VOLATILE || + mso == TPM2_MSO_NVRAM) { + sha256_update(&sctx, auth->name[i], + name_size(auth->name[i])); + } else { + __be32 h = cpu_to_be32(auth->name_h[i]); + + sha256_update(&sctx, (u8 *)&h, 4); + } + } + if (offset_s != tpm_buf_length(buf)) + sha256_update(&sctx, &buf->data[offset_s], + tpm_buf_length(buf) - offset_s); + sha256_final(&sctx, cphash); + + /* now calculate the hmac */ + tpm2_hmac_init(&sctx, auth->session_key, sizeof(auth->session_key) + + auth->passphrase_len); + sha256_update(&sctx, cphash, sizeof(cphash)); + sha256_update(&sctx, auth->our_nonce, sizeof(auth->our_nonce)); + sha256_update(&sctx, auth->tpm_nonce, sizeof(auth->tpm_nonce)); + sha256_update(&sctx, &auth->attrs, 1); + tpm2_hmac_final(&sctx, auth->session_key, sizeof(auth->session_key) + + auth->passphrase_len, hmac); +} +EXPORT_SYMBOL(tpm_buf_fill_hmac_session); + static int tpm2_parse_read_public(char *name, struct tpm_buf *buf) { struct tpm_header *head = (struct tpm_header *)buf->data; @@ -406,6 +658,154 @@ void tpm_buf_append_name(struct tpm_chip *chip, struct tpm_buf *buf, memcpy(auth->name[slot], name, name_size(name)); } EXPORT_SYMBOL(tpm_buf_append_name); + +/** + * tpm_buf_check_hmac_response() - check the TPM return HMAC for correctness + * @chip: the TPM chip structure + * @buf: the original command buffer (which now contains the response) + * @rc: the return code from tpm_transmit_cmd + * + * If @rc is non zero, @buf may not contain an actual return, so @rc + * is passed through as the return and the session cleaned up and + * de-allocated if required (this is required if + * TPM2_SA_CONTINUE_SESSION was not specified as a session flag). + * + * If @rc is zero, the response HMAC is computed against the returned + * @buf and matched to the TPM one in the session area. If there is a + * mismatch, an error is logged and -EINVAL returned. + * + * The reason for this is that the command issue and HMAC check + * sequence should look like: + * + * rc = tpm_transmit_cmd(...); + * rc = tpm_buf_check_hmac_response(&buf, auth, rc); + * if (rc) + * ... + * + * Which is easily layered into the current contrl flow. + * + * Returns: 0 on success or an error. + */ +int tpm_buf_check_hmac_response(struct tpm_chip *chip, struct tpm_buf *buf, + int rc) +{ + struct tpm_header *head = (struct tpm_header *)buf->data; + struct tpm2_auth *auth = chip->auth; + off_t offset_s, offset_p; + u8 rphash[SHA256_DIGEST_SIZE]; + u32 attrs; + struct sha256_state sctx; + u16 tag = be16_to_cpu(head->tag); + u32 cc = be32_to_cpu(auth->ordinal); + int parm_len, len, i, handles; + + if (auth->session >= TPM_HEADER_SIZE) { + WARN(1, "tpm session not filled correctly\n"); + goto out; + } + + if (rc != 0) + /* pass non success rc through and close the session */ + goto out; + + rc = -EINVAL; + if (tag != TPM2_ST_SESSIONS) { + dev_err(&chip->dev, "TPM: HMAC response check has no sessions tag\n"); + goto out; + } + + i = tpm2_find_cc(chip, cc); + if (i < 0) + goto out; + attrs = chip->cc_attrs_tbl[i]; + handles = (attrs >> TPM2_CC_ATTR_RHANDLE) & 1; + + /* point to area beyond handles */ + offset_s = TPM_HEADER_SIZE + handles * 4; + parm_len = tpm_buf_read_u32(buf, &offset_s); + offset_p = offset_s; + offset_s += parm_len; + /* skip over any sessions before ours */ + for (i = 0; i < auth->session - 1; i++) { + len = tpm_buf_read_u16(buf, &offset_s); + offset_s += len + 1; + len = tpm_buf_read_u16(buf, &offset_s); + offset_s += len; + } + /* TPM nonce */ + len = tpm_buf_read_u16(buf, &offset_s); + if (offset_s + len > tpm_buf_length(buf)) + goto out; + if (len != SHA256_DIGEST_SIZE) + goto out; + memcpy(auth->tpm_nonce, &buf->data[offset_s], len); + offset_s += len; + attrs = tpm_buf_read_u8(buf, &offset_s); + len = tpm_buf_read_u16(buf, &offset_s); + if (offset_s + len != tpm_buf_length(buf)) + goto out; + if (len != SHA256_DIGEST_SIZE) + goto out; + /* + * offset_s points to the HMAC. now calculate comparison, beginning + * with rphash + */ + sha256_init(&sctx); + /* yes, I know this is now zero, but it's what the standard says */ + sha256_update(&sctx, (u8 *)&head->return_code, + sizeof(head->return_code)); + /* ordinal is already BE */ + sha256_update(&sctx, (u8 *)&auth->ordinal, sizeof(auth->ordinal)); + sha256_update(&sctx, &buf->data[offset_p], parm_len); + sha256_final(&sctx, rphash); + + /* now calculate the hmac */ + tpm2_hmac_init(&sctx, auth->session_key, sizeof(auth->session_key) + + auth->passphrase_len); + sha256_update(&sctx, rphash, sizeof(rphash)); + sha256_update(&sctx, auth->tpm_nonce, sizeof(auth->tpm_nonce)); + sha256_update(&sctx, auth->our_nonce, sizeof(auth->our_nonce)); + sha256_update(&sctx, &auth->attrs, 1); + /* we're done with the rphash, so put our idea of the hmac there */ + tpm2_hmac_final(&sctx, auth->session_key, sizeof(auth->session_key) + + auth->passphrase_len, rphash); + if (memcmp(rphash, &buf->data[offset_s], SHA256_DIGEST_SIZE) == 0) { + rc = 0; + } else { + dev_err(&chip->dev, "TPM: HMAC check failed\n"); + goto out; + } + + /* now do response decryption */ + if (auth->attrs & TPM2_SA_ENCRYPT) { + /* need key and IV */ + tpm2_KDFa(auth->session_key, SHA256_DIGEST_SIZE + + auth->passphrase_len, "CFB", auth->tpm_nonce, + auth->our_nonce, AES_KEY_BYTES + AES_BLOCK_SIZE, + auth->scratch); + + len = tpm_buf_read_u16(buf, &offset_p); + aes_expandkey(&auth->aes_ctx, auth->scratch, AES_KEY_BYTES); + aescfb_decrypt(&auth->aes_ctx, &buf->data[offset_p], + &buf->data[offset_p], len, + auth->scratch + AES_KEY_BYTES); + } + + out: + if ((auth->attrs & TPM2_SA_CONTINUE_SESSION) == 0) { + if (rc) + /* manually close the session if it wasn't consumed */ + tpm2_flush_context(chip, auth->handle); + memzero_explicit(auth, sizeof(*auth)); + } else { + /* reset for next use */ + auth->session = TPM_HEADER_SIZE; + } + + return rc; +} +EXPORT_SYMBOL(tpm_buf_check_hmac_response); + /** * tpm2_end_auth_session() - kill the allocated auth session * @chip: the TPM chip structure diff --git a/include/linux/tpm.h b/include/linux/tpm.h index 31c2065fcd35..dd4d6a6158c4 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -510,8 +510,25 @@ static inline void tpm_buf_append_empty_auth(struct tpm_buf *buf, u32 handle) int tpm2_start_auth_session(struct tpm_chip *chip); void tpm_buf_append_name(struct tpm_chip *chip, struct tpm_buf *buf, u32 handle, u8 *name); +void tpm_buf_append_hmac_session(struct tpm_chip *chip, struct tpm_buf *buf, + u8 attributes, u8 *passphrase, + int passphraselen); +static inline void tpm_buf_append_hmac_session_opt(struct tpm_chip *chip, + struct tpm_buf *buf, + u8 attributes, + u8 *passphrase, + int passphraselen) +{ + tpm_buf_append_hmac_session(chip, buf, attributes, passphrase, + passphraselen); +} +void tpm_buf_fill_hmac_session(struct tpm_chip *chip, struct tpm_buf *buf); +int tpm_buf_check_hmac_response(struct tpm_chip *chip, struct tpm_buf *buf, + int rc); void tpm2_end_auth_session(struct tpm_chip *chip); #else +#include + static inline int tpm2_start_auth_session(struct tpm_chip *chip) { return 0; @@ -527,6 +544,58 @@ static inline void tpm_buf_append_name(struct tpm_chip *chip, /* count the number of handles in the upper bits of flags */ buf->handles++; } +static inline void tpm_buf_append_hmac_session(struct tpm_chip *chip, + struct tpm_buf *buf, + u8 attributes, u8 *passphrase, + int passphraselen) +{ + /* offset tells us where the sessions area begins */ + int offset = buf->handles * 4 + TPM_HEADER_SIZE; + u32 len = 9 + passphraselen; + + if (tpm_buf_length(buf) != offset) { + /* not the first session so update the existing length */ + len += get_unaligned_be32(&buf->data[offset]); + put_unaligned_be32(len, &buf->data[offset]); + } else { + tpm_buf_append_u32(buf, len); + } + /* auth handle */ + tpm_buf_append_u32(buf, TPM2_RS_PW); + /* nonce */ + tpm_buf_append_u16(buf, 0); + /* attributes */ + tpm_buf_append_u8(buf, 0); + /* passphrase */ + tpm_buf_append_u16(buf, passphraselen); + tpm_buf_append(buf, passphrase, passphraselen); +} +static inline void tpm_buf_append_hmac_session_opt(struct tpm_chip *chip, + struct tpm_buf *buf, + u8 attributes, + u8 *passphrase, + int passphraselen) +{ + int offset = buf->handles * 4 + TPM_HEADER_SIZE; + struct tpm_header *head = (struct tpm_header *) buf->data; + + /* + * if the only sessions are optional, the command tag + * must change to TPM2_ST_NO_SESSIONS + */ + if (tpm_buf_length(buf) == offset) + head->tag = cpu_to_be16(TPM2_ST_NO_SESSIONS); +} +static inline void tpm_buf_fill_hmac_session(struct tpm_chip *chip, + struct tpm_buf *buf) +{ +} +static inline int tpm_buf_check_hmac_response(struct tpm_chip *chip, + struct tpm_buf *buf, + int rc) +{ + return rc; +} #endif /* CONFIG_TCG_TPM2_HMAC */ #endif From 6519fea6fd372b2247a48d72dcb23e14de70b4ea Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:06 -0400 Subject: [PATCH 960/969] tpm: add hmac checks to tpm2_pcr_extend() tpm2_pcr_extend() is used by trusted keys to extend a PCR to prevent a key from being re-loaded until the next reboot. To use this functionality securely, that extend must be protected by a session hmac. This patch adds HMAC protection so tampering with the tpm2_pcr_extend() command in flight is detected. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm2-cmd.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/char/tpm/tpm2-cmd.c b/drivers/char/tpm/tpm2-cmd.c index b0e72fb563d9..a53a843294ed 100644 --- a/drivers/char/tpm/tpm2-cmd.c +++ b/drivers/char/tpm/tpm2-cmd.c @@ -216,13 +216,6 @@ out: return rc; } -struct tpm2_null_auth_area { - __be32 handle; - __be16 nonce_size; - u8 attributes; - __be16 auth_size; -} __packed; - /** * tpm2_pcr_extend() - extend a PCR value * @@ -236,24 +229,22 @@ int tpm2_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, struct tpm_digest *digests) { struct tpm_buf buf; - struct tpm2_null_auth_area auth_area; int rc; int i; - rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_PCR_EXTEND); + rc = tpm2_start_auth_session(chip); if (rc) return rc; - tpm_buf_append_u32(&buf, pcr_idx); + rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_PCR_EXTEND); + if (rc) { + tpm2_end_auth_session(chip); + return rc; + } - auth_area.handle = cpu_to_be32(TPM2_RS_PW); - auth_area.nonce_size = 0; - auth_area.attributes = 0; - auth_area.auth_size = 0; + tpm_buf_append_name(chip, &buf, pcr_idx, NULL); + tpm_buf_append_hmac_session(chip, &buf, 0, NULL, 0); - tpm_buf_append_u32(&buf, sizeof(struct tpm2_null_auth_area)); - tpm_buf_append(&buf, (const unsigned char *)&auth_area, - sizeof(auth_area)); tpm_buf_append_u32(&buf, chip->nr_allocated_banks); for (i = 0; i < chip->nr_allocated_banks; i++) { @@ -262,7 +253,9 @@ int tpm2_pcr_extend(struct tpm_chip *chip, u32 pcr_idx, chip->allocated_banks[i].digest_size); } + tpm_buf_fill_hmac_session(chip, &buf); rc = tpm_transmit_cmd(chip, &buf, 0, "attempting extend a PCR value"); + rc = tpm_buf_check_hmac_response(chip, &buf, rc); tpm_buf_destroy(&buf); From 1b6d7f9eb150305dcb0da4f7101a8d30dcdf0497 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:07 -0400 Subject: [PATCH 961/969] tpm: add session encryption protection to tpm2_get_random() If some entity is snooping the TPM bus, they can see the random numbers we're extracting from the TPM and do prediction attacks against their consumers. Foil this attack by using response encryption to prevent the attacker from seeing the random sequence. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm2-cmd.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/char/tpm/tpm2-cmd.c b/drivers/char/tpm/tpm2-cmd.c index a53a843294ed..0cdf892ec2a7 100644 --- a/drivers/char/tpm/tpm2-cmd.c +++ b/drivers/char/tpm/tpm2-cmd.c @@ -292,25 +292,35 @@ int tpm2_get_random(struct tpm_chip *chip, u8 *dest, size_t max) if (!num_bytes || max > TPM_MAX_RNG_DATA) return -EINVAL; - err = tpm_buf_init(&buf, 0, 0); + err = tpm2_start_auth_session(chip); if (err) return err; + err = tpm_buf_init(&buf, 0, 0); + if (err) { + tpm2_end_auth_session(chip); + return err; + } + do { - tpm_buf_reset(&buf, TPM2_ST_NO_SESSIONS, TPM2_CC_GET_RANDOM); + tpm_buf_reset(&buf, TPM2_ST_SESSIONS, TPM2_CC_GET_RANDOM); + tpm_buf_append_hmac_session_opt(chip, &buf, TPM2_SA_ENCRYPT + | TPM2_SA_CONTINUE_SESSION, + NULL, 0); tpm_buf_append_u16(&buf, num_bytes); + tpm_buf_fill_hmac_session(chip, &buf); err = tpm_transmit_cmd(chip, &buf, offsetof(struct tpm2_get_random_out, buffer), "attempting get random"); + err = tpm_buf_check_hmac_response(chip, &buf, err); if (err) { if (err > 0) err = -EIO; goto out; } - out = (struct tpm2_get_random_out *) - &buf.data[TPM_HEADER_SIZE]; + out = (struct tpm2_get_random_out *)tpm_buf_parameters(&buf); recd = min_t(u32, be16_to_cpu(out->size), num_bytes); if (tpm_buf_length(&buf) < TPM_HEADER_SIZE + @@ -327,9 +337,12 @@ int tpm2_get_random(struct tpm_chip *chip, u8 *dest, size_t max) } while (retries-- && total < max); tpm_buf_destroy(&buf); + tpm2_end_auth_session(chip); + return total ? total : -EIO; out: tpm_buf_destroy(&buf); + tpm2_end_auth_session(chip); return err; } From 52ce7d9731ed8fada505b5ac33fb1df0190fb8c3 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:08 -0400 Subject: [PATCH 962/969] KEYS: trusted: Add session encryption protection to the seal/unseal path If some entity is snooping the TPM bus, the can see the data going in to be sealed and the data coming out as it is unsealed. Add parameter and response encryption to these cases to ensure that no secrets are leaked even if the bus is snooped. As part of doing this conversion it was discovered that policy sessions can't work with HMAC protected authority because of missing pieces (the tpm Nonce). I've added code to work the same way as before, which will result in potential authority exposure (while still adding security for the command and the returned blob), and a fixme to redo the API to get rid of this security hole. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- security/keys/trusted-keys/trusted_tpm2.c | 88 ++++++++++++++++------- 1 file changed, 61 insertions(+), 27 deletions(-) diff --git a/security/keys/trusted-keys/trusted_tpm2.c b/security/keys/trusted-keys/trusted_tpm2.c index 97b1dfca2dba..dfeec06301ce 100644 --- a/security/keys/trusted-keys/trusted_tpm2.c +++ b/security/keys/trusted-keys/trusted_tpm2.c @@ -253,26 +253,26 @@ int tpm2_seal_trusted(struct tpm_chip *chip, if (rc) return rc; + rc = tpm2_start_auth_session(chip); + if (rc) + goto out_put; + rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_CREATE); if (rc) { - tpm_put_ops(chip); - return rc; + tpm2_end_auth_session(chip); + goto out_put; } rc = tpm_buf_init_sized(&sized); if (rc) { tpm_buf_destroy(&buf); - tpm_put_ops(chip); - return rc; + tpm2_end_auth_session(chip); + goto out_put; } - tpm_buf_reset(&buf, TPM2_ST_SESSIONS, TPM2_CC_CREATE); - tpm_buf_append_u32(&buf, options->keyhandle); - tpm2_buf_append_auth(&buf, TPM2_RS_PW, - NULL /* nonce */, 0, - 0 /* session_attributes */, - options->keyauth /* hmac */, - TPM_DIGEST_SIZE); + tpm_buf_append_name(chip, &buf, options->keyhandle, NULL); + tpm_buf_append_hmac_session(chip, &buf, TPM2_SA_DECRYPT, + options->keyauth, TPM_DIGEST_SIZE); /* sensitive */ tpm_buf_append_u16(&sized, options->blobauth_len); @@ -314,10 +314,13 @@ int tpm2_seal_trusted(struct tpm_chip *chip, if (buf.flags & TPM_BUF_OVERFLOW) { rc = -E2BIG; + tpm2_end_auth_session(chip); goto out; } + tpm_buf_fill_hmac_session(chip, &buf); rc = tpm_transmit_cmd(chip, &buf, 4, "sealing data"); + rc = tpm_buf_check_hmac_response(chip, &buf, rc); if (rc) goto out; @@ -348,6 +351,7 @@ out: else payload->blob_len = blob_len; +out_put: tpm_put_ops(chip); return rc; } @@ -417,25 +421,31 @@ static int tpm2_load_cmd(struct tpm_chip *chip, if (blob_len > payload->blob_len) return -E2BIG; - rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_LOAD); + rc = tpm2_start_auth_session(chip); if (rc) return rc; - tpm_buf_append_u32(&buf, options->keyhandle); - tpm2_buf_append_auth(&buf, TPM2_RS_PW, - NULL /* nonce */, 0, - 0 /* session_attributes */, - options->keyauth /* hmac */, - TPM_DIGEST_SIZE); + rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_LOAD); + if (rc) { + tpm2_end_auth_session(chip); + return rc; + } + + tpm_buf_append_name(chip, &buf, options->keyhandle, NULL); + tpm_buf_append_hmac_session(chip, &buf, 0, options->keyauth, + TPM_DIGEST_SIZE); tpm_buf_append(&buf, blob, blob_len); if (buf.flags & TPM_BUF_OVERFLOW) { rc = -E2BIG; + tpm2_end_auth_session(chip); goto out; } + tpm_buf_fill_hmac_session(chip, &buf); rc = tpm_transmit_cmd(chip, &buf, 4, "loading blob"); + rc = tpm_buf_check_hmac_response(chip, &buf, rc); if (!rc) *blob_handle = be32_to_cpup( (__be32 *) &buf.data[TPM_HEADER_SIZE]); @@ -473,20 +483,44 @@ static int tpm2_unseal_cmd(struct tpm_chip *chip, u8 *data; int rc; - rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_UNSEAL); + rc = tpm2_start_auth_session(chip); if (rc) return rc; - tpm_buf_append_u32(&buf, blob_handle); - tpm2_buf_append_auth(&buf, - options->policyhandle ? - options->policyhandle : TPM2_RS_PW, - NULL /* nonce */, 0, - TPM2_SA_CONTINUE_SESSION, - options->blobauth /* hmac */, - options->blobauth_len); + rc = tpm_buf_init(&buf, TPM2_ST_SESSIONS, TPM2_CC_UNSEAL); + if (rc) { + tpm2_end_auth_session(chip); + return rc; + } + tpm_buf_append_name(chip, &buf, blob_handle, NULL); + + if (!options->policyhandle) { + tpm_buf_append_hmac_session(chip, &buf, TPM2_SA_ENCRYPT, + options->blobauth, + options->blobauth_len); + } else { + /* + * FIXME: The policy session was generated outside the + * kernel so we don't known the nonce and thus can't + * calculate a HMAC on it. Therefore, the user can + * only really use TPM2_PolicyPassword and we must + * send down the plain text password, which could be + * intercepted. We can still encrypt the returned + * key, but that's small comfort since the interposer + * could repeat our actions with the exfiltrated + * password. + */ + tpm2_buf_append_auth(&buf, options->policyhandle, + NULL /* nonce */, 0, 0, + options->blobauth, options->blobauth_len); + tpm_buf_append_hmac_session_opt(chip, &buf, TPM2_SA_ENCRYPT, + NULL, 0); + } + + tpm_buf_fill_hmac_session(chip, &buf); rc = tpm_transmit_cmd(chip, &buf, 6, "unsealing"); + rc = tpm_buf_check_hmac_response(chip, &buf, rc); if (rc > 0) rc = -EPERM; From 089e0fb3f773a23a17b9945b0abeb075cb7c7186 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:09 -0400 Subject: [PATCH 963/969] tpm: add the null key name as a sysfs export This is the last component of encrypted tpm2 session handling that allows us to verify from userspace that the key derived from the NULL seed genuinely belongs to the TPM and has not been spoofed. The procedure for doing this involves creating an attestation identity key (which requires verification of the TPM EK certificate) and then using that AIK to sign a certification of the Elliptic Curve key over the NULL seed. Userspace must create this EC Key using the parameters prescribed in TCG TPM v2.0 Provisioning Guidance for the SRK ECC; if this is done correctly the names will match and the TPM can then run a TPM2_Certify operation on this derived primary key using the newly created AIK. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-sysfs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/char/tpm/tpm-sysfs.c b/drivers/char/tpm/tpm-sysfs.c index 54c71473aa29..94231f052ea7 100644 --- a/drivers/char/tpm/tpm-sysfs.c +++ b/drivers/char/tpm/tpm-sysfs.c @@ -309,6 +309,21 @@ static ssize_t tpm_version_major_show(struct device *dev, } static DEVICE_ATTR_RO(tpm_version_major); +#ifdef CONFIG_TCG_TPM2_HMAC +static ssize_t null_name_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct tpm_chip *chip = to_tpm_chip(dev); + int size = TPM2_NAME_SIZE; + + bin2hex(buf, chip->null_key_name, size); + size *= 2; + buf[size++] = '\n'; + return size; +} +static DEVICE_ATTR_RO(null_name); +#endif + static struct attribute *tpm1_dev_attrs[] = { &dev_attr_pubek.attr, &dev_attr_pcrs.attr, @@ -326,6 +341,9 @@ static struct attribute *tpm1_dev_attrs[] = { static struct attribute *tpm2_dev_attrs[] = { &dev_attr_tpm_version_major.attr, +#ifdef CONFIG_TCG_TPM2_HMAC + &dev_attr_null_name.attr, +#endif NULL }; From 3d2daf9d592e435c46a91841602e52ecbad48602 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:10 -0400 Subject: [PATCH 964/969] Documentation: add tpm-security.rst Document how the new encrypted secure interface for TPM2 works and how security can be assured after boot by certifying the NULL seed. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- Documentation/security/tpm/tpm-security.rst | 216 ++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 Documentation/security/tpm/tpm-security.rst diff --git a/Documentation/security/tpm/tpm-security.rst b/Documentation/security/tpm/tpm-security.rst new file mode 100644 index 000000000000..4f633f251033 --- /dev/null +++ b/Documentation/security/tpm/tpm-security.rst @@ -0,0 +1,216 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +TPM Security +============ + +The object of this document is to describe how we make the kernel's +use of the TPM reasonably robust in the face of external snooping and +packet alteration attacks (called passive and active interposer attack +in the literature). The current security document is for TPM 2.0. + +Introduction +------------ + +The TPM is usually a discrete chip attached to a PC via some type of +low bandwidth bus. There are exceptions to this such as the Intel +PTT, which is a software TPM running inside a software environment +close to the CPU, which are subject to different attacks, but right at +the moment, most hardened security environments require a discrete +hardware TPM, which is the use case discussed here. + +Snooping and Alteration Attacks against the bus +----------------------------------------------- + +The current state of the art for snooping the `TPM Genie`_ hardware +interposer which is a simple external device that can be installed in +a couple of seconds on any system or laptop. Recently attacks were +successfully demonstrated against the `Windows Bitlocker TPM`_ system. +Most recently the same `attack against TPM based Linux disk +encryption`_ schemes. The next phase of research seems to be hacking +existing devices on the bus to act as interposers, so the fact that +the attacker requires physical access for a few seconds might +evaporate. However, the goal of this document is to protect TPM +secrets and integrity as far as we are able in this environment and to +try to insure that if we can't prevent the attack then at least we can +detect it. + +Unfortunately, most of the TPM functionality, including the hardware +reset capability can be controlled by an attacker who has access to +the bus, so we'll discuss some of the disruption possibilities below. + +Measurement (PCR) Integrity +--------------------------- + +Since the attacker can send their own commands to the TPM, they can +send arbitrary PCR extends and thus disrupt the measurement system, +which would be an annoying denial of service attack. However, there +are two, more serious, classes of attack aimed at entities sealed to +trust measurements. + +1. The attacker could intercept all PCR extends coming from the system + and completely substitute their own values, producing a replay of + an untampered state that would cause PCR measurements to attest to + a trusted state and release secrets + +2. At some point in time the attacker could reset the TPM, clearing + the PCRs and then send down their own measurements which would + effectively overwrite the boot time measurements the TPM has + already done. + +The first can be thwarted by always doing HMAC protection of the PCR +extend and read command meaning measurement values cannot be +substituted without producing a detectable HMAC failure in the +response. However, the second can only really be detected by relying +on some sort of mechanism for protection which would change over TPM +reset. + +Secrets Guarding +---------------- + +Certain information passing in and out of the TPM, such as key sealing +and private key import and random number generation, is vulnerable to +interception which HMAC protection alone cannot protect against, so +for these types of command we must also employ request and response +encryption to prevent the loss of secret information. + +Establishing Initial Trust with the TPM +--------------------------------------- + +In order to provide security from the beginning, an initial shared or +asymmetric secret must be established which must also be unknown to +the attacker. The most obvious avenues for this are the endorsement +and storage seeds, which can be used to derive asymmetric keys. +However, using these keys is difficult because the only way to pass +them into the kernel would be on the command line, which requires +extensive support in the boot system, and there's no guarantee that +either hierarchy would not have some type of authorization. + +The mechanism chosen for the Linux Kernel is to derive the primary +elliptic curve key from the null seed using the standard storage seed +parameters. The null seed has two advantages: firstly the hierarchy +physically cannot have an authorization, so we are always able to use +it and secondly, the null seed changes across TPM resets, meaning if +we establish trust on the null seed at start of day, all sessions +salted with the derived key will fail if the TPM is reset and the seed +changes. + +Obviously using the null seed without any other prior shared secrets, +we have to create and read the initial public key which could, of +course, be intercepted and substituted by the bus interposer. +However, the TPM has a key certification mechanism (using the EK +endorsement certificate, creating an attestation identity key and +certifying the null seed primary with that key) which is too complex +to run within the kernel, so we keep a copy of the null primary key +name, which is what is exported via sysfs so user-space can run the +full certification when it boots. The definitive guarantee here is +that if the null primary key certifies correctly, you know all your +TPM transactions since start of day were secure and if it doesn't, you +know there's an interposer on your system (and that any secret used +during boot may have been leaked). + +Stacking Trust +-------------- + +In the current null primary scenario, the TPM must be completely +cleared before handing it on to the next consumer. However the kernel +hands to user-space the name of the derived null seed key which can +then be verified by certification in user-space. Therefore, this chain +of name handoff can be used between the various boot components as +well (via an unspecified mechanism). For instance, grub could use the +null seed scheme for security and hand the name off to the kernel in +the boot area. The kernel could make its own derivation of the key +and the name and know definitively that if they differ from the handed +off version that tampering has occurred. Thus it becomes possible to +chain arbitrary boot components together (UEFI to grub to kernel) via +the name handoff provided each successive component knows how to +collect the name and verifies it against its derived key. + +Session Properties +------------------ + +All TPM commands the kernel uses allow sessions. HMAC sessions may be +used to check the integrity of requests and responses and decrypt and +encrypt flags may be used to shield parameters and responses. The +HMAC and encryption keys are usually derived from the shared +authorization secret, but for a lot of kernel operations that is well +known (and usually empty). Thus, every HMAC session used by the +kernel must be created using the null primary key as the salt key +which thus provides a cryptographic input into the session key +derivation. Thus, the kernel creates the null primary key once (as a +volatile TPM handle) and keeps it around in a saved context stored in +tpm_chip for every in-kernel use of the TPM. Currently, because of a +lack of de-gapping in the in-kernel resource manager, the session must +be created and destroyed for each operation, but, in future, a single +session may also be reused for the in-kernel HMAC, encryption and +decryption sessions. + +Protection Types +---------------- + +For every in-kernel operation we use null primary salted HMAC to +protect the integrity. Additionally, we use parameter encryption to +protect key sealing and parameter decryption to protect key unsealing +and random number generation. + +Null Primary Key Certification in Userspace +=========================================== + +Every TPM comes shipped with a couple of X.509 certificates for the +primary endorsement key. This document assumes that the Elliptic +Curve version of the certificate exists at 01C00002, but will work +equally well with the RSA certificate (at 01C00001). + +The first step in the certification is primary creation using the +template from the `TCG EK Credential Profile`_ which allows comparison +of the generated primary key against the one in the certificate (the +public key must match). Note that generation of the EK primary +requires the EK hierarchy password, but a pre-generated version of the +EC primary should exist at 81010002 and a TPM2_ReadPublic() may be +performed on this without needing the key authority. Next, the +certificate itself must be verified to chain back to the manufacturer +root (which should be published on the manufacturer website). Once +this is done, an attestation key (AK) is generated within the TPM and +it's name and the EK public key can be used to encrypt a secret using +TPM2_MakeCredential. The TPM then runs TPM2_ActivateCredential which +will only recover the secret if the binding between the TPM, the EK +and the AK is true. the generated AK may now be used to run a +certification of the null primary key whose name the kernel has +exported. Since TPM2_MakeCredential/ActivateCredential are somewhat +complicated, a more simplified process involving an externally +generated private key is described below. + +This process is a simplified abbreviation of the usual privacy CA +based attestation process. The assumption here is that the +attestation is done by the TPM owner who thus has access to only the +owner hierarchy. The owner creates an external public/private key +pair (assume elliptic curve in this case) and wraps the private key +for import using an inner wrapping process and parented to the EC +derived storage primary. The TPM2_Import() is done using a parameter +decryption HMAC session salted to the EK primary (which also does not +require the EK key authority) meaning that the inner wrapping key is +the encrypted parameter and thus the TPM will not be able to perform +the import unless is possesses the certified EK so if the command +succeeds and the HMAC verifies on return we know we have a loadable +copy of the private key only for the certified TPM. This key is now +loaded into the TPM and the Storage primary flushed (to free up space +for the null key generation). + +The null EC primary is now generated using the Storage profile +outlined in the `TCG TPM v2.0 Provisioning Guidance`_; the name of +this key (the hash of the public area) is computed and compared to the +null seed name presented by the kernel in +/sys/class/tpm/tpm0/null_name. If the names do not match, the TPM is +compromised. If the names match, the user performs a TPM2_Certify() +using the null primary as the object handle and the loaded private key +as the sign handle and providing randomized qualifying data. The +signature of the returned certifyInfo is verified against the public +part of the loaded private key and the qualifying data checked to +prevent replay. If all of these tests pass, the user is now assured +that TPM integrity and privacy was preserved across the entire boot +sequence of this kernel. + +.. _TPM Genie: https://www.nccgroup.trust/globalassets/about-us/us/documents/tpm-genie.pdf +.. _Windows Bitlocker TPM: https://dolosgroup.io/blog/2021/7/9/from-stolen-laptop-to-inside-the-company-network +.. _attack against TPM based Linux disk encryption: https://www.secura.com/blog/tpm-sniffing-attacks-against-non-bitlocker-targets +.. _TCG EK Credential Profile: https://trustedcomputinggroup.org/resource/tcg-ek-credential-profile-for-tpm-family-2-0/ +.. _TCG TPM v2.0 Provisioning Guidance: https://trustedcomputinggroup.org/resource/tcg-tpm-v2-0-provisioning-guidance/ From eb24c9788cd90db397b3e41322aff4a5557623b4 Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Mon, 29 Apr 2024 16:28:11 -0400 Subject: [PATCH 965/969] tpm: disable the TPM if NULL name changes Update tpm2_load_context() to return -EINVAL on integrity failures and use this as a signal when loading the NULL context that something might be wrong. If the signal fails, check the name of the NULL primary against the one stored in the chip data and if there is a mismatch disable the TPM because it is likely to have suffered a reset attack. Signed-off-by: James Bottomley Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- drivers/char/tpm/tpm-chip.c | 3 ++ drivers/char/tpm/tpm2-sessions.c | 77 +++++++++++++++++++++++++------- drivers/char/tpm/tpm2-space.c | 3 ++ include/linux/tpm.h | 4 +- 4 files changed, 70 insertions(+), 17 deletions(-) diff --git a/drivers/char/tpm/tpm-chip.c b/drivers/char/tpm/tpm-chip.c index d93937326b2e..854546000c92 100644 --- a/drivers/char/tpm/tpm-chip.c +++ b/drivers/char/tpm/tpm-chip.c @@ -158,6 +158,9 @@ int tpm_try_get_ops(struct tpm_chip *chip) { int rc = -EIO; + if (chip->flags & TPM_CHIP_FLAG_DISABLE) + return rc; + get_device(&chip->dev); down_read(&chip->ops_sem); diff --git a/drivers/char/tpm/tpm2-sessions.c b/drivers/char/tpm/tpm2-sessions.c index dc50f635700c..ea8860661876 100644 --- a/drivers/char/tpm/tpm2-sessions.c +++ b/drivers/char/tpm/tpm2-sessions.c @@ -80,6 +80,9 @@ /* maximum number of names the TPM must remember for authorization */ #define AUTH_MAX_NAMES 3 +static int tpm2_create_primary(struct tpm_chip *chip, u32 hierarchy, + u32 *handle, u8 *name); + /* * This is the structure that carries all the auth information (like * session handle, nonces, session key and auth) from use to use it is @@ -851,6 +854,37 @@ static int tpm2_parse_start_auth_session(struct tpm2_auth *auth, return 0; } +static int tpm2_load_null(struct tpm_chip *chip, u32 *null_key) +{ + int rc; + unsigned int offset = 0; /* dummy offset for null seed context */ + u8 name[SHA256_DIGEST_SIZE + 2]; + + rc = tpm2_load_context(chip, chip->null_key_context, &offset, + null_key); + if (rc != -EINVAL) + return rc; + + /* an integrity failure may mean the TPM has been reset */ + dev_err(&chip->dev, "NULL key integrity failure!\n"); + /* check the null name against what we know */ + tpm2_create_primary(chip, TPM2_RH_NULL, NULL, name); + if (memcmp(name, chip->null_key_name, sizeof(name)) == 0) + /* name unchanged, assume transient integrity failure */ + return rc; + /* + * Fatal TPM failure: the NULL seed has actually changed, so + * the TPM must have been illegally reset. All in-kernel TPM + * operations will fail because the NULL primary can't be + * loaded to salt the sessions, but disable the TPM anyway so + * userspace programmes can't be compromised by it. + */ + dev_err(&chip->dev, "NULL name has changed, disabling TPM due to interference\n"); + chip->flags |= TPM_CHIP_FLAG_DISABLE; + + return rc; +} + /** * tpm2_start_auth_session() - create a HMAC authentication session with the TPM * @chip: the TPM chip structure to create the session with @@ -868,12 +902,9 @@ int tpm2_start_auth_session(struct tpm_chip *chip) struct tpm_buf buf; struct tpm2_auth *auth = chip->auth; int rc; - /* null seed context has no offset, but we must provide one */ - unsigned int offset = 0; - u32 nullkey; + u32 null_key; - rc = tpm2_load_context(chip, chip->null_key_context, &offset, - &nullkey); + rc = tpm2_load_null(chip, &null_key); if (rc) goto out; @@ -884,7 +915,7 @@ int tpm2_start_auth_session(struct tpm_chip *chip) goto out; /* salt key handle */ - tpm_buf_append_u32(&buf, nullkey); + tpm_buf_append_u32(&buf, null_key); /* bind key handle */ tpm_buf_append_u32(&buf, TPM2_RH_NULL); /* nonce caller */ @@ -908,7 +939,7 @@ int tpm2_start_auth_session(struct tpm_chip *chip) tpm_buf_append_u16(&buf, TPM_ALG_SHA256); rc = tpm_transmit_cmd(chip, &buf, 0, "start auth session"); - tpm2_flush_context(chip, nullkey); + tpm2_flush_context(chip, null_key); if (rc == TPM2_RC_SUCCESS) rc = tpm2_parse_start_auth_session(auth, &buf); @@ -930,6 +961,7 @@ EXPORT_SYMBOL(tpm2_start_auth_session); * @buf: The response buffer from the chip * @handle: pointer to be filled in with the return handle of the primary * @hierarchy: The hierarchy the primary was created for + * @name: pointer to be filled in with the primary key name * * Return: * * 0 - OK @@ -937,15 +969,20 @@ EXPORT_SYMBOL(tpm2_start_auth_session); * * TPM_RC - A TPM error */ static int tpm2_parse_create_primary(struct tpm_chip *chip, struct tpm_buf *buf, - u32 *handle, u32 hierarchy) + u32 *handle, u32 hierarchy, u8 *name) { struct tpm_header *head = (struct tpm_header *)buf->data; off_t offset_r = TPM_HEADER_SIZE, offset_t; u16 len = TPM_HEADER_SIZE; u32 total_len = be32_to_cpu(head->length); - u32 val, param_len; + u32 val, param_len, keyhandle; + + keyhandle = tpm_buf_read_u32(buf, &offset_r); + if (handle) + *handle = keyhandle; + else + tpm2_flush_context(chip, keyhandle); - *handle = tpm_buf_read_u32(buf, &offset_r); param_len = tpm_buf_read_u32(buf, &offset_r); /* * param_len doesn't include the header, but all the other @@ -958,9 +995,14 @@ static int tpm2_parse_create_primary(struct tpm_chip *chip, struct tpm_buf *buf, return -EINVAL; len = tpm_buf_read_u16(buf, &offset_r); offset_t = offset_r; - /* now we have the public area, compute the name of the object */ - put_unaligned_be16(TPM_ALG_SHA256, chip->null_key_name); - sha256(&buf->data[offset_r], len, chip->null_key_name + 2); + if (name) { + /* + * now we have the public area, compute the name of + * the object + */ + put_unaligned_be16(TPM_ALG_SHA256, name); + sha256(&buf->data[offset_r], len, name + 2); + } /* validate the public key */ val = tpm_buf_read_u16(buf, &offset_t); @@ -1089,6 +1131,7 @@ static int tpm2_parse_create_primary(struct tpm_chip *chip, struct tpm_buf *buf, * @chip: the TPM chip to create under * @hierarchy: The hierarchy handle to create under * @handle: The returned volatile handle on success + * @name: The name of the returned key * * For platforms that might not have a persistent primary, this can be * used to create one quickly on the fly (it uses Elliptic Curve not @@ -1103,7 +1146,7 @@ static int tpm2_parse_create_primary(struct tpm_chip *chip, struct tpm_buf *buf, * * TPM_RC - A TPM error */ static int tpm2_create_primary(struct tpm_chip *chip, u32 hierarchy, - u32 *handle) + u32 *handle, u8 *name) { int rc; struct tpm_buf buf; @@ -1193,7 +1236,8 @@ static int tpm2_create_primary(struct tpm_chip *chip, u32 hierarchy, "attempting to create NULL primary"); if (rc == TPM2_RC_SUCCESS) - rc = tpm2_parse_create_primary(chip, &buf, handle, hierarchy); + rc = tpm2_parse_create_primary(chip, &buf, handle, hierarchy, + name); tpm_buf_destroy(&buf); @@ -1205,7 +1249,8 @@ static int tpm2_create_null_primary(struct tpm_chip *chip) u32 null_key; int rc; - rc = tpm2_create_primary(chip, TPM2_RH_NULL, &null_key); + rc = tpm2_create_primary(chip, TPM2_RH_NULL, &null_key, + chip->null_key_name); if (rc == TPM2_RC_SUCCESS) { unsigned int offset = 0; /* dummy offset for null key context */ diff --git a/drivers/char/tpm/tpm2-space.c b/drivers/char/tpm/tpm2-space.c index 24479a81c23c..4892d491da8d 100644 --- a/drivers/char/tpm/tpm2-space.c +++ b/drivers/char/tpm/tpm2-space.c @@ -105,6 +105,9 @@ int tpm2_load_context(struct tpm_chip *chip, u8 *buf, *handle = 0; tpm_buf_destroy(&tbuf); return -ENOENT; + } else if (tpm2_rc_value(rc) == TPM2_RC_INTEGRITY) { + tpm_buf_destroy(&tbuf); + return -EINVAL; } else if (rc > 0) { dev_warn(&chip->dev, "%s: failed with a TPM error 0x%04X\n", __func__, rc); diff --git a/include/linux/tpm.h b/include/linux/tpm.h index dd4d6a6158c4..c17e4efbb2e5 100644 --- a/include/linux/tpm.h +++ b/include/linux/tpm.h @@ -248,6 +248,7 @@ enum tpm2_return_codes { TPM2_RC_SUCCESS = 0x0000, TPM2_RC_HASH = 0x0083, /* RC_FMT1 */ TPM2_RC_HANDLE = 0x008B, + TPM2_RC_INTEGRITY = 0x009F, TPM2_RC_INITIALIZE = 0x0100, /* RC_VER1 */ TPM2_RC_FAILURE = 0x0101, TPM2_RC_DISABLED = 0x0120, @@ -346,6 +347,7 @@ enum tpm_chip_flags { TPM_CHIP_FLAG_FIRMWARE_UPGRADE = BIT(7), TPM_CHIP_FLAG_SUSPENDED = BIT(8), TPM_CHIP_FLAG_HWRNG_DISABLED = BIT(9), + TPM_CHIP_FLAG_DISABLE = BIT(10), }; #define to_tpm_chip(d) container_of(d, struct tpm_chip, dev) @@ -447,7 +449,7 @@ static inline bool tpm_is_firmware_upgrade(struct tpm_chip *chip) static inline u32 tpm2_rc_value(u32 rc) { - return (rc & BIT(7)) ? rc & 0xff : rc; + return (rc & BIT(7)) ? rc & 0xbf : rc; } #if defined(CONFIG_TCG_TPM) || defined(CONFIG_TCG_TPM_MODULE) From 1d479e3cd6520085832a6b432d521eeead2691ba Mon Sep 17 00:00:00 2001 From: Bagas Sanjaya Date: Mon, 6 May 2024 17:59:36 +0700 Subject: [PATCH 966/969] Documentation: tpm: Add TPM security docs toctree entry Stephen Rothwell reports htmldocs warning when merging tpmdd tree for linux-next: Documentation/security/tpm/tpm-security.rst: WARNING: document isn't included in any toctree Add toctree entry for TPM security docs to fix above warning. Fixes: ddfb3687c538 ("Documentation: add tpm-security.rst") Reported-by: Stephen Rothwell Closes: https://lore.kernel.org/linux-next/20240506162105.42ce2ff7@canb.auug.org.au/ Signed-off-by: Bagas Sanjaya Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen --- Documentation/security/tpm/index.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/security/tpm/index.rst b/Documentation/security/tpm/index.rst index f27a17f60a96..fa593d960040 100644 --- a/Documentation/security/tpm/index.rst +++ b/Documentation/security/tpm/index.rst @@ -5,6 +5,7 @@ Trusted Platform Module documentation .. toctree:: tpm_event_log + tpm-security tpm_tis tpm_vtpm_proxy xen-tpmfront From 428ae88ef519f2009fac37563de76ffa6f93046f Mon Sep 17 00:00:00 2001 From: Daniel Danzberger Date: Sat, 9 Mar 2024 10:32:16 +0100 Subject: [PATCH 967/969] arm64: add Airoha EN7581 platform Introduce the Kconfig entry for the Airoha EN7581 multicore architecture available in the Airoha EN7581 evaluation board. Signed-off-by: Daniel Danzberger Co-developed-by: Lorenzo Bianconi Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/d52d95db313e6a58ba997ba2181faf78a1014bcc.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..36604db205a4 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -8,6 +8,13 @@ config ARCH_ACTIONS help This enables support for the Actions Semiconductor S900 SoC family. +config ARCH_AIROHA + bool "Airoha SoC Support" + select ARM_PSCI + select HAVE_ARM_ARCH_TIMER + help + This enables support for the ARM64 based Airoha SoCs. + config ARCH_SUNXI bool "Allwinner sunxi 64-bit SoC Family" select ARCH_HAS_RESET_CONTROLLER From 78b08cf6313061499948126aebdf00e1079e4d21 Mon Sep 17 00:00:00 2001 From: Daniel Danzberger Date: Sat, 9 Mar 2024 10:32:17 +0100 Subject: [PATCH 968/969] arm64: defconfig: enable Airoha platform Enables the ARCH_AIROHA config by default. Signed-off-by: Daniel Danzberger Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/65737ca5506371ef84c3a055e68d280f314e3b41.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 14d3182e5195..d35150a979d4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -34,6 +34,7 @@ CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y CONFIG_CRASH_DUMP=y CONFIG_ARCH_ACTIONS=y +CONFIG_ARCH_AIROHA=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_APPLE=y From 5800e77d88c0cd98bc10460df148631afa7b5e4d Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Wed, 27 Mar 2024 15:14:26 -0700 Subject: [PATCH 969/969] csky: Emulate one-byte cmpxchg Use the new cmpxchg_emu_u8() to emulate one-byte cmpxchg() on csky. [ paulmck: Apply kernel test robot feedback. ] [ paulmck: Drop two-byte support per Arnd Bergmann feedback. ] Co-developed-by: Yujie Liu Signed-off-by: Yujie Liu Signed-off-by: Paul E. McKenney Tested-by: Yujie Liu Reviewed-by: Guo Ren Cc: Arnd Bergmann Cc: --- arch/csky/Kconfig | 1 + arch/csky/include/asm/cmpxchg.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index d3ac36751ad1..5479707eb5d1 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -37,6 +37,7 @@ config CSKY select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION + select ARCH_NEED_CMPXCHG_1_EMU select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace) select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT select COMMON_CLK diff --git a/arch/csky/include/asm/cmpxchg.h b/arch/csky/include/asm/cmpxchg.h index 916043b845f1..db6dda47184e 100644 --- a/arch/csky/include/asm/cmpxchg.h +++ b/arch/csky/include/asm/cmpxchg.h @@ -6,6 +6,7 @@ #ifdef CONFIG_SMP #include #include +#include #define __xchg_relaxed(new, ptr, size) \ ({ \ @@ -61,6 +62,9 @@ __typeof__(old) __old = (old); \ __typeof__(*(ptr)) __ret; \ switch (size) { \ + case 1: \ + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, (uintptr_t)__old, (uintptr_t)__new); \ + break; \ case 4: \ asm volatile ( \ "1: ldex.w %0, (%3) \n" \ @@ -91,6 +95,9 @@ __typeof__(old) __old = (old); \ __typeof__(*(ptr)) __ret; \ switch (size) { \ + case 1: \ + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, (uintptr_t)__old, (uintptr_t)__new); \ + break; \ case 4: \ asm volatile ( \ "1: ldex.w %0, (%3) \n" \ @@ -122,6 +129,9 @@ __typeof__(old) __old = (old); \ __typeof__(*(ptr)) __ret; \ switch (size) { \ + case 1: \ + __ret = (__typeof__(*(ptr)))cmpxchg_emu_u8((volatile u8 *)__ptr, (uintptr_t)__old, (uintptr_t)__new); \ + break; \ case 4: \ asm volatile ( \ RELEASE_FENCE \