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PCI: tegra: Add DT support to disable CLKREQ# control on PLLE

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Sometimes CLKREQ# pin connection might be missing on a platform. Add DT
support to disable CLKREQ# control on PLLE in driver. Platform device tree
can use this DT property to disable CLKREQ# control on PLLE. In kernel-5.9,
upstream device tree property "supports-clkreq" is used in place of
kernel-4.14 custom device tree property "nvidia,disable-clock-request".

bug 200420606

Change-Id: I6ac44bd99d090e158fa10e5e9b62d63e52563c8c
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786551
(cherry picked from commit 6870a94b48a4bbbe9df607802c7f7c1f61806b7b)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407880
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Manikanta Maddireddy
2018-07-17 23:56:11 +05:30
committed by Thomas Makin
parent f6a8256ac3
commit 3ac7bfa0f3
1 changed files with 25 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/pci/controller/pci-tegra.c
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@@ -454,6 +454,7 @@ struct tegra_pcie_port {
unsigned int index;
unsigned int lanes;
unsigned int aspm_state;
bool supports_clkreq;
struct phy **phys;
@@ -762,6 +763,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
disable_aspm_l11(port);
if (port->aspm_state & 0x8)
disable_aspm_l12(port);
/* Disable L1SS capability if CLKREQ# is not present */
if (!port->supports_clkreq) {
value = readl(port->base + RP_L1_PM_SUBSTATES_CTL);
value |= RP_L1_PM_SUBSTATES_CTL_HIDE_CAP;
writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
}
}
}
@@ -959,8 +967,12 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
value = afi_readl(port->pcie, ctrl);
value |= AFI_PEX_CTRL_REFCLK_EN;
if (soc->has_pex_clkreq_en)
if (soc->has_pex_clkreq_en) {
if (port->supports_clkreq)
value &= ~AFI_PEX_CTRL_CLKREQ_EN;
else
value |= AFI_PEX_CTRL_CLKREQ_EN;
}
value |= AFI_PEX_CTRL_OVERRIDE_EN;
@@ -1394,6 +1406,14 @@ static void tegra_pcie_enable_controller(struct tegra_pcie *pcie)
value = afi_readl(pcie, AFI_PLLE_CONTROL);
value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
list_for_each_entry(port, &pcie->ports, list) {
if (!port->supports_clkreq) {
value &= ~AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
break;
}
}
value &= ~AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL;
value |= AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN;
afi_writel(pcie, value, AFI_PLLE_CONTROL);
@@ -2523,6 +2543,9 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
if (err < 0)
rp->aspm_state = 0;
rp->supports_clkreq = of_property_read_bool(port,
"supports-clkreq");
list_add_tail(&rp->list, &pcie->ports);
}