From 3a39898f0d4717fa8be0de2ee5f213b0ce70c37a Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Tue, 24 Jul 2018 10:30:34 +0530 Subject: [PATCH] PCI: tegra: Bypass CLKREQ# control over PLLE When PCIe link is L2 CLKREQ# will be floating and this might interfere with PLL power down. Bypass CLKREQ# control over PLLE when link is in L2. bug 1356695 bug 200420606 Change-Id: I361db03df5f9a1a8d38bd9fb816d17fc4c64a9fc Signed-off-by: Manikanta Maddireddy Reviewed-on: https://git-master.nvidia.com/r/1786565 (cherry picked from commit 69e79f42f65df70b0c76e62200aca40ed3972e3b) Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407877 Reviewed-by: Bitan Biswas Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/pci/controller/pci-tegra.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index e97cf6f71e32..77ca6f668cf2 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -1765,6 +1765,11 @@ static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port) val = afi_readl(pcie, AFI_PCIE_PME); val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit); afi_writel(pcie, val, AFI_PCIE_PME); + + /* PCIe link is in L2, bypass CLKREQ# control over PLLE power down */ + val = afi_readl(pcie, AFI_PLLE_CONTROL); + val |= AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; + afi_writel(pcie, val, AFI_PLLE_CONTROL); } static void tegra_pcie_msi_irq(struct irq_desc *desc)