From 3a1ca167bb4c4dae9089df48665c973fd381d098 Mon Sep 17 00:00:00 2001 From: Vincent Donnefort Date: Tue, 1 Oct 2024 13:44:47 +0100 Subject: [PATCH] ANDROID: KVM: arm64: Provide caches_clean_inval_pou_macro at EL2 In preparation for handling text section live patching in the pKVM hypervisor, introduce an EL2 copy of caches_clean_inval_pou_macro(). Bug: 357781595 Change-Id: I51e435d4298adedfc1292797effe349491565f50 Signed-off-by: Vincent Donnefort --- arch/arm64/kvm/hyp/nvhe/cache.S | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/cache.S b/arch/arm64/kvm/hyp/nvhe/cache.S index 85936c17ae40..b8debb962a71 100644 --- a/arch/arm64/kvm/hyp/nvhe/cache.S +++ b/arch/arm64/kvm/hyp/nvhe/cache.S @@ -23,3 +23,25 @@ alternative_else_nop_endif ret SYM_FUNC_END(__pi_icache_inval_pou) SYM_FUNC_ALIAS(icache_inval_pou, __pi_icache_inval_pou) + +.macro caches_clean_inval_pou_macro, fixup +alternative_if ARM64_HAS_CACHE_IDC + dsb ishst + b .Ldc_skip_\@ +alternative_else_nop_endif + mov x2, x0 + mov x3, x1 + dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup +.Ldc_skip_\@: +alternative_if ARM64_HAS_CACHE_DIC + isb + b .Lic_skip_\@ +alternative_else_nop_endif + invalidate_icache_by_line x0, x1, x2, x3, \fixup +.Lic_skip_\@: +.endm + +SYM_FUNC_START(caches_clean_inval_pou) + caches_clean_inval_pou_macro + ret +SYM_FUNC_END(caches_clean_inval_pou)